Skip to content

Commit

Permalink
PLLs
Browse files Browse the repository at this point in the history
  • Loading branch information
@mmicko
mmicko committed Mar 12, 2024
1 parent 16c1350 commit c5171d5
Show file tree
Hide file tree
Showing 5 changed files with 230 additions and 169 deletions.
168 changes: 0 additions & 168 deletions techlibs/nanoxplore/cells_bb.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5846,174 +5846,6 @@ endmodule
// parameter lut_table = 16'b0000000000000000;
//endmodule

(* blackbox *)
module NX_PLL(REF, FBK, VCO, D1, D2, D3, OSC, RDY);
output D1;
output D2;
output D3;
input FBK;
output OSC;
output RDY;
input REF;
output VCO;
parameter clk_outdiv1 = 0;
parameter clk_outdiv2 = 0;
parameter clk_outdiv3 = 0;
parameter ext_fbk_on = 1'b0;
parameter fbk_delay = 0;
parameter fbk_delay_on = 1'b0;
parameter fbk_div_on = 1'b0;
parameter fbk_intdiv = 2;
parameter location = "";
parameter ref_div_on = 1'b0;
parameter vco_range = 0;
endmodule

(* blackbox *)
module NX_PLL_L(REF, FBK, R, VCO, LDFO, REFO, DIVO1, DIVO2, DIVP1, DIVP2, DIVP3, OSC, PLL_LOCKED, CAL_LOCKED);
output CAL_LOCKED;
output DIVO1;
output DIVO2;
output DIVP1;
output DIVP2;
output DIVP3;
input FBK;
output LDFO;
output OSC;
output PLL_LOCKED;
input R;
input REF;
output REFO;
output VCO;
parameter cfg_use_pll = 1'b1;
parameter clk_outdivo1 = 0;
parameter clk_outdivp1 = 0;
parameter clk_outdivp2 = 0;
parameter clk_outdivp3o2 = 0;
parameter ext_fbk_on = 1'b0;
parameter fbk_delay = 0;
parameter fbk_delay_on = 1'b0;
parameter fbk_intdiv = 2;
parameter location = "";
parameter pll_cpump = 3'b010;
parameter ref_intdiv = 0;
parameter ref_osc_on = 1'b0;
parameter wfg_sync_cal_lock = 1'b0;
parameter wfg_sync_pll_lock = 1'b0;
endmodule

(* blackbox *)
module NX_PLL_U(R, REF, FBK, OSC, VCO, LDFO, REFO, CLK_DIV1, CLK_DIV2, CLK_DIV3, CLK_DIV4, CLK_DIVD1, CLK_DIVD2, CLK_DIVD3, CLK_DIVD4, CLK_DIVD5, PLL_LOCKED, PLL_LOCKEDA, ARST_CAL, CLK_CAL, CLK_CAL_DIV
, CAL_LOCKED, EXT_CAL_LOCKED, CAL1, CAL2, CAL3, CAL4, CAL5, EXT_CAL1, EXT_CAL2, EXT_CAL3, EXT_CAL4, EXT_CAL5);
input ARST_CAL;
output CAL1;
output CAL2;
output CAL3;
output CAL4;
output CAL5;
output CAL_LOCKED;
input CLK_CAL;
output CLK_CAL_DIV;
output CLK_DIV1;
output CLK_DIV2;
output CLK_DIV3;
output CLK_DIV4;
output CLK_DIVD1;
output CLK_DIVD2;
output CLK_DIVD3;
output CLK_DIVD4;
output CLK_DIVD5;
input EXT_CAL1;
input EXT_CAL2;
input EXT_CAL3;
input EXT_CAL4;
input EXT_CAL5;
input EXT_CAL_LOCKED;
input FBK;
output LDFO;
output OSC;
output PLL_LOCKED;
output PLL_LOCKEDA;
input R;
input REF;
output REFO;
output VCO;
parameter cal_delay = 6'b011011;
parameter cal_div = 4'b0111;
parameter clk_cal_sel = 2'b01;
parameter clk_outdiv1 = 3'b000;
parameter clk_outdiv2 = 3'b000;
parameter clk_outdiv3 = 3'b000;
parameter clk_outdiv4 = 3'b000;
parameter clk_outdivd1 = 4'b0000;
parameter clk_outdivd2 = 4'b0000;
parameter clk_outdivd3 = 4'b0000;
parameter clk_outdivd4 = 4'b0000;
parameter clk_outdivd5 = 4'b0000;
parameter ext_fbk_on = 1'b0;
parameter fbk_delay = 6'b000000;
parameter fbk_delay_on = 1'b0;
parameter fbk_intdiv = 7'b0000000;
parameter location = "";
parameter pll_cpump = 4'b0000;
parameter pll_lock = 4'b0000;
parameter pll_lpf_cap = 4'b0000;
parameter pll_lpf_res = 4'b0000;
parameter pll_odf = 2'b00;
parameter ref_intdiv = 5'b00000;
parameter ref_osc_on = 1'b0;
parameter use_cal = 1'b0;
parameter use_pll = 1'b1;
endmodule

(* blackbox *)
module NX_PLL_U_WRAP(R, REF, FBK, OSC, VCO, LDFO, REFO, PLL_LOCKED, PLL_LOCKEDA, ARST_CAL, CLK_CAL, CLK_CAL_DIV, CAL_LOCKED, EXT_CAL_LOCKED, CAL, CLK_DIVD, EXT_CAL, CLK_DIV);
input ARST_CAL;
output [4:0] CAL;
output CAL_LOCKED;
input CLK_CAL;
output CLK_CAL_DIV;
output [3:0] CLK_DIV;
output [4:0] CLK_DIVD;
input [4:0] EXT_CAL;
input EXT_CAL_LOCKED;
input FBK;
output LDFO;
output OSC;
output PLL_LOCKED;
output PLL_LOCKEDA;
input R;
input REF;
output REFO;
output VCO;
parameter cal_delay = 6'b011011;
parameter cal_div = 4'b0111;
parameter clk_cal_sel = 2'b01;
parameter clk_outdiv1 = 3'b000;
parameter clk_outdiv2 = 3'b000;
parameter clk_outdiv3 = 3'b000;
parameter clk_outdiv4 = 3'b000;
parameter clk_outdivd1 = 4'b0000;
parameter clk_outdivd2 = 4'b0000;
parameter clk_outdivd3 = 4'b0000;
parameter clk_outdivd4 = 4'b0000;
parameter clk_outdivd5 = 4'b0000;
parameter ext_fbk_on = 1'b0;
parameter fbk_delay = 6'b000000;
parameter fbk_delay_on = 1'b0;
parameter fbk_intdiv = 7'b0000000;
parameter location = "";
parameter pll_cpump = 4'b0000;
parameter pll_lock = 4'b0000;
parameter pll_lpf_cap = 4'b0000;
parameter pll_lpf_res = 4'b0000;
parameter pll_odf = 2'b00;
parameter ref_intdiv = 5'b00000;
parameter ref_osc_on = 1'b0;
parameter use_cal = 1'b0;
parameter use_pll = 1'b1;
endmodule

(* blackbox *)
module NX_PMA_L(CLK_USER_I, CLK_REF_I, PRE_SG_I, PRE_EN_I, PRE_IS_I1, PRE_IS_I2, PRE_IS_I3, PRE_IS_I4, MAIN_SG_I, MAIN_EN_I1, MAIN_EN_I2, MAIN_EN_I3, MAIN_EN_I4, MAIN_EN_I5, MAIN_EN_I6, MARG_S_I1, MARG_S_I2, MARG_S_I3, MARG_S_I4, MARG_IS_I1, MARG_IS_I2
, MARG_IS_I3, MARG_IS_I4, MARG_SV_I1, MARG_SV_I2, MARG_SV_I3, MARG_SV_I4, MARG_SV_I5, MARG_ISV_I1, MARG_ISV_I2, MARG_ISV_I3, MARG_ISV_I4, MARG_ISV_I5, POST_EN_I1, POST_EN_I2, POST_EN_I3, POST_EN_I4, POST_EN_I5, POST_SG_I, POST_IS_I1, POST_IS_I2, POST_IS_I3
Expand Down
32 changes: 32 additions & 0 deletions techlibs/nanoxplore/cells_bb_l.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -469,3 +469,35 @@ module NX_DSP_L(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15
parameter std_mode = "";
endmodule

(* blackbox *)
module NX_PLL_L(REF, FBK, R, VCO, LDFO, REFO, DIVO1, DIVO2, DIVP1, DIVP2, DIVP3, OSC, PLL_LOCKED, CAL_LOCKED);
output CAL_LOCKED;
output DIVO1;
output DIVO2;
output DIVP1;
output DIVP2;
output DIVP3;
input FBK;
output LDFO;
output OSC;
output PLL_LOCKED;
input R;
input REF;
output REFO;
output VCO;
parameter cfg_use_pll = 1'b1;
parameter clk_outdivo1 = 0;
parameter clk_outdivp1 = 0;
parameter clk_outdivp2 = 0;
parameter clk_outdivp3o2 = 0;
parameter ext_fbk_on = 1'b0;
parameter fbk_delay = 0;
parameter fbk_delay_on = 1'b0;
parameter fbk_intdiv = 2;
parameter location = "";
parameter pll_cpump = 3'b010;
parameter ref_intdiv = 0;
parameter ref_osc_on = 1'b0;
parameter wfg_sync_cal_lock = 1'b0;
parameter wfg_sync_pll_lock = 1'b0;
endmodule
23 changes: 23 additions & 0 deletions techlibs/nanoxplore/cells_bb_m.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -378,3 +378,26 @@ module NX_DSP(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15,
parameter std_mode = "";
endmodule

(* blackbox *)
module NX_PLL(REF, FBK, VCO, D1, D2, D3, OSC, RDY);
output D1;
output D2;
output D3;
input FBK;
output OSC;
output RDY;
input REF;
output VCO;
parameter clk_outdiv1 = 0;
parameter clk_outdiv2 = 0;
parameter clk_outdiv3 = 0;
parameter ext_fbk_on = 1'b0;
parameter fbk_delay = 0;
parameter fbk_delay_on = 1'b0;
parameter fbk_div_on = 1'b0;
parameter fbk_intdiv = 2;
parameter location = "";
parameter ref_div_on = 1'b0;
parameter vco_range = 0;
endmodule

64 changes: 64 additions & 0 deletions techlibs/nanoxplore/cells_bb_u.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -485,3 +485,67 @@ module NX_DSP_U(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15
parameter raw_config3 = 3'b000;
parameter std_mode = "";
endmodule

(* blackbox *)
module NX_PLL_U(R, REF, FBK, OSC, VCO, LDFO, REFO, CLK_DIV1, CLK_DIV2, CLK_DIV3, CLK_DIV4, CLK_DIVD1, CLK_DIVD2, CLK_DIVD3, CLK_DIVD4, CLK_DIVD5, PLL_LOCKED, PLL_LOCKEDA, ARST_CAL, CLK_CAL, CLK_CAL_DIV
, CAL_LOCKED, EXT_CAL_LOCKED, CAL1, CAL2, CAL3, CAL4, CAL5, EXT_CAL1, EXT_CAL2, EXT_CAL3, EXT_CAL4, EXT_CAL5);
input ARST_CAL;
output CAL1;
output CAL2;
output CAL3;
output CAL4;
output CAL5;
output CAL_LOCKED;
input CLK_CAL;
output CLK_CAL_DIV;
output CLK_DIV1;
output CLK_DIV2;
output CLK_DIV3;
output CLK_DIV4;
output CLK_DIVD1;
output CLK_DIVD2;
output CLK_DIVD3;
output CLK_DIVD4;
output CLK_DIVD5;
input EXT_CAL1;
input EXT_CAL2;
input EXT_CAL3;
input EXT_CAL4;
input EXT_CAL5;
input EXT_CAL_LOCKED;
input FBK;
output LDFO;
output OSC;
output PLL_LOCKED;
output PLL_LOCKEDA;
input R;
input REF;
output REFO;
output VCO;
parameter cal_delay = 6'b011011;
parameter cal_div = 4'b0111;
parameter clk_cal_sel = 2'b01;
parameter clk_outdiv1 = 3'b000;
parameter clk_outdiv2 = 3'b000;
parameter clk_outdiv3 = 3'b000;
parameter clk_outdiv4 = 3'b000;
parameter clk_outdivd1 = 4'b0000;
parameter clk_outdivd2 = 4'b0000;
parameter clk_outdivd3 = 4'b0000;
parameter clk_outdivd4 = 4'b0000;
parameter clk_outdivd5 = 4'b0000;
parameter ext_fbk_on = 1'b0;
parameter fbk_delay = 6'b000000;
parameter fbk_delay_on = 1'b0;
parameter fbk_intdiv = 7'b0000000;
parameter location = "";
parameter pll_cpump = 4'b0000;
parameter pll_lock = 4'b0000;
parameter pll_lpf_cap = 4'b0000;
parameter pll_lpf_res = 4'b0000;
parameter pll_odf = 2'b00;
parameter ref_intdiv = 5'b00000;
parameter ref_osc_on = 1'b0;
parameter use_cal = 1'b0;
parameter use_pll = 1'b1;
endmodule
Loading

0 comments on commit c5171d5

Please sign in to comment.