From c6dddac2f89deba3f58646a38982a35d40ba526f Mon Sep 17 00:00:00 2001
From: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
Date: Sat, 25 May 2024 11:35:09 +0200
Subject: [PATCH] Test all files in verilog dir

---
 tests/functional/.gitignore                   |  4 +-
 tests/functional/run-test.sh                  | 40 ++++++++++++-------
 tests/functional/vcd_harness.cpp              |  4 +-
 tests/functional/verilog/add.v                |  9 +++++
 tests/functional/verilog/and.v                | 12 +++---
 tests/functional/verilog/my_module_div.v      |  9 +++++
 tests/functional/verilog/my_module_eqx.v      |  9 +++++
 tests/functional/verilog/my_module_ge.v       |  9 +++++
 tests/functional/verilog/my_module_gt.v       |  9 +++++
 tests/functional/verilog/my_module_le.v       |  9 +++++
 .../functional/verilog/my_module_logic_and.v  |  9 +++++
 tests/functional/verilog/my_module_logic_or.v |  9 +++++
 tests/functional/verilog/my_module_lt.v       |  9 +++++
 tests/functional/verilog/my_module_mod.v      |  9 +++++
 tests/functional/verilog/my_module_mul.v      |  9 +++++
 tests/functional/verilog/my_module_ne.v       |  9 +++++
 tests/functional/verilog/my_module_nex.v      |  9 +++++
 tests/functional/verilog/my_module_or.v       |  9 +++++
 tests/functional/verilog/my_module_pow.v      |  9 +++++
 tests/functional/verilog/my_module_shl.v      |  9 +++++
 tests/functional/verilog/my_module_shr.v      |  9 +++++
 tests/functional/verilog/my_module_sshl.v     |  9 +++++
 tests/functional/verilog/my_module_sshr.v     |  9 +++++
 tests/functional/verilog/my_module_sub.v      |  9 +++++
 tests/functional/verilog/my_module_xnor.v     |  9 +++++
 tests/functional/verilog/my_module_xor.v      |  9 +++++
 26 files changed, 233 insertions(+), 25 deletions(-)
 create mode 100644 tests/functional/verilog/add.v
 create mode 100755 tests/functional/verilog/my_module_div.v
 create mode 100755 tests/functional/verilog/my_module_eqx.v
 create mode 100755 tests/functional/verilog/my_module_ge.v
 create mode 100755 tests/functional/verilog/my_module_gt.v
 create mode 100755 tests/functional/verilog/my_module_le.v
 create mode 100755 tests/functional/verilog/my_module_logic_and.v
 create mode 100755 tests/functional/verilog/my_module_logic_or.v
 create mode 100755 tests/functional/verilog/my_module_lt.v
 create mode 100755 tests/functional/verilog/my_module_mod.v
 create mode 100755 tests/functional/verilog/my_module_mul.v
 create mode 100755 tests/functional/verilog/my_module_ne.v
 create mode 100755 tests/functional/verilog/my_module_nex.v
 create mode 100755 tests/functional/verilog/my_module_or.v
 create mode 100755 tests/functional/verilog/my_module_pow.v
 create mode 100755 tests/functional/verilog/my_module_shl.v
 create mode 100755 tests/functional/verilog/my_module_shr.v
 create mode 100755 tests/functional/verilog/my_module_sshl.v
 create mode 100755 tests/functional/verilog/my_module_sshr.v
 create mode 100755 tests/functional/verilog/my_module_sub.v
 create mode 100755 tests/functional/verilog/my_module_xnor.v
 create mode 100755 tests/functional/verilog/my_module_xor.v

diff --git a/tests/functional/.gitignore b/tests/functional/.gitignore
index 06af41869c9..6ee14e70604 100644
--- a/tests/functional/.gitignore
+++ b/tests/functional/.gitignore
@@ -1,5 +1,5 @@
-and_cxxrtl.cc
-and_functional_cxx.cc
+my_module_cxxrtl.cc
+my_module_functional_cxx.cc
 vcd_harness
 cxxrtl.vcd
 functional_cxx.vcd
\ No newline at end of file
diff --git a/tests/functional/run-test.sh b/tests/functional/run-test.sh
index 3e9de003fc2..09ee5e0f9a3 100755
--- a/tests/functional/run-test.sh
+++ b/tests/functional/run-test.sh
@@ -2,19 +2,29 @@
 
 set -ex
 
-../../yosys -p "read_verilog verilog/and.v; write_cxxrtl and_cxxrtl.cc; write_functional_cxx and_functional_cxx.cc"
-${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cpp -I ../../backends/functional/cxx_runtime/ -I ../../backends/cxxrtl/runtime/ -o vcd_harness
-# Generate VCD files cxxrtl.vcd and functional_cxx.vcd
-./vcd_harness
-# Run vcdiff and capture the output
-output=$(vcdiff cxxrtl.vcd functional_cxx.vcd)
+# Loop through all Verilog files in the verilog directory
+for verilog_file in verilog/*.v; do
+    # Run yosys to process each Verilog file
+    ../../yosys -p "read_verilog $verilog_file; write_cxxrtl my_module_cxxrtl.cc; write_functional_cxx my_module_functional_cxx.cc"
 
-# Check if there is any output
-if [ -n "$output" ]; then
-    echo "Differences detected:"
-    echo "$output"
-    exit 1
-else
-    echo "No differences detected."
-    exit 0
-fi
+    # Compile the generated C++ files with vcd_harness.cpp
+    ${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cpp -I ../../backends/functional/cxx_runtime/ -I ../../backends/cxxrtl/runtime/ -o vcd_harness
+
+    # Generate VCD files cxxrtl.vcd and functional_cxx.vcd
+    ./vcd_harness
+
+    # Run vcdiff and capture the output
+    output=$(vcdiff cxxrtl.vcd functional_cxx.vcd)
+
+    # Check if there is any output
+    if [ -n "$output" ]; then
+        echo "Differences detected in $verilog_file:"
+        echo "$output"
+        exit 1
+    else
+        echo "No differences detected in $verilog_file."
+    fi
+done
+
+# If all files are processed without differences
+exit 0
diff --git a/tests/functional/vcd_harness.cpp b/tests/functional/vcd_harness.cpp
index ca27065f110..76d078b7103 100644
--- a/tests/functional/vcd_harness.cpp
+++ b/tests/functional/vcd_harness.cpp
@@ -5,8 +5,8 @@
 
 #include <cxxrtl/cxxrtl_vcd.h>
 
-#include "and_cxxrtl.cc"
-#include "and_functional_cxx.cc"
+#include "my_module_cxxrtl.cc"
+#include "my_module_functional_cxx.cc"
 
 struct DumpHeader {
     std::ofstream &ofs;
diff --git a/tests/functional/verilog/add.v b/tests/functional/verilog/add.v
new file mode 100644
index 00000000000..95bae7b3544
--- /dev/null
+++ b/tests/functional/verilog/add.v
@@ -0,0 +1,9 @@
+module my_module(
+		 input	a,
+		 input	b,
+		 output	sum
+		 );
+   // Perform addition
+   assign sum = a + b;
+
+endmodule
diff --git a/tests/functional/verilog/and.v b/tests/functional/verilog/and.v
index 95bae7b3544..ae07de221ff 100644
--- a/tests/functional/verilog/and.v
+++ b/tests/functional/verilog/and.v
@@ -1,9 +1,9 @@
 module my_module(
-		 input	a,
-		 input	b,
-		 output	sum
-		 );
-   // Perform addition
-   assign sum = a + b;
+    input a,
+    input b,
+    output y
+);
+   // Perform AND
+   assign y = a & b;
 
 endmodule
diff --git a/tests/functional/verilog/my_module_div.v b/tests/functional/verilog/my_module_div.v
new file mode 100755
index 00000000000..d9a5d372a40
--- /dev/null
+++ b/tests/functional/verilog/my_module_div.v
@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a / b;
+
+endmodule
diff --git a/tests/functional/verilog/my_module_eqx.v b/tests/functional/verilog/my_module_eqx.v
new file mode 100755
index 00000000000..09a2d9dd680
--- /dev/null
+++ b/tests/functional/verilog/my_module_eqx.v
@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a === b;
+
+endmodule
diff --git a/tests/functional/verilog/my_module_ge.v b/tests/functional/verilog/my_module_ge.v
new file mode 100755
index 00000000000..8fcfc8b7f6d
--- /dev/null
+++ b/tests/functional/verilog/my_module_ge.v
@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a >= b;
+
+endmodule
diff --git a/tests/functional/verilog/my_module_gt.v b/tests/functional/verilog/my_module_gt.v
new file mode 100755
index 00000000000..5667db3e746
--- /dev/null
+++ b/tests/functional/verilog/my_module_gt.v
@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a > b;
+
+endmodule
diff --git a/tests/functional/verilog/my_module_le.v b/tests/functional/verilog/my_module_le.v
new file mode 100755
index 00000000000..a4b7c482089
--- /dev/null
+++ b/tests/functional/verilog/my_module_le.v
@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a <= b;
+
+endmodule
diff --git a/tests/functional/verilog/my_module_logic_and.v b/tests/functional/verilog/my_module_logic_and.v
new file mode 100755
index 00000000000..3028d8361da
--- /dev/null
+++ b/tests/functional/verilog/my_module_logic_and.v
@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a && b;
+
+endmodule
diff --git a/tests/functional/verilog/my_module_logic_or.v b/tests/functional/verilog/my_module_logic_or.v
new file mode 100755
index 00000000000..ca37346d91f
--- /dev/null
+++ b/tests/functional/verilog/my_module_logic_or.v
@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a || b;
+
+endmodule
diff --git a/tests/functional/verilog/my_module_lt.v b/tests/functional/verilog/my_module_lt.v
new file mode 100755
index 00000000000..c702433d4f8
--- /dev/null
+++ b/tests/functional/verilog/my_module_lt.v
@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a < b;
+
+endmodule
diff --git a/tests/functional/verilog/my_module_mod.v b/tests/functional/verilog/my_module_mod.v
new file mode 100755
index 00000000000..84c8c91884f
--- /dev/null
+++ b/tests/functional/verilog/my_module_mod.v
@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a % b;
+
+endmodule
diff --git a/tests/functional/verilog/my_module_mul.v b/tests/functional/verilog/my_module_mul.v
new file mode 100755
index 00000000000..8eff36abce1
--- /dev/null
+++ b/tests/functional/verilog/my_module_mul.v
@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a * b;
+
+endmodule
diff --git a/tests/functional/verilog/my_module_ne.v b/tests/functional/verilog/my_module_ne.v
new file mode 100755
index 00000000000..c4e0dc1c916
--- /dev/null
+++ b/tests/functional/verilog/my_module_ne.v
@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a != b;
+
+endmodule
diff --git a/tests/functional/verilog/my_module_nex.v b/tests/functional/verilog/my_module_nex.v
new file mode 100755
index 00000000000..630dce4e915
--- /dev/null
+++ b/tests/functional/verilog/my_module_nex.v
@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a !== b;
+
+endmodule
diff --git a/tests/functional/verilog/my_module_or.v b/tests/functional/verilog/my_module_or.v
new file mode 100755
index 00000000000..ada39ee49ce
--- /dev/null
+++ b/tests/functional/verilog/my_module_or.v
@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a | b;
+
+endmodule
diff --git a/tests/functional/verilog/my_module_pow.v b/tests/functional/verilog/my_module_pow.v
new file mode 100755
index 00000000000..d9f09638510
--- /dev/null
+++ b/tests/functional/verilog/my_module_pow.v
@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a ** b;
+
+endmodule
diff --git a/tests/functional/verilog/my_module_shl.v b/tests/functional/verilog/my_module_shl.v
new file mode 100755
index 00000000000..66a435ad474
--- /dev/null
+++ b/tests/functional/verilog/my_module_shl.v
@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a << b;
+
+endmodule
diff --git a/tests/functional/verilog/my_module_shr.v b/tests/functional/verilog/my_module_shr.v
new file mode 100755
index 00000000000..791a2ab423a
--- /dev/null
+++ b/tests/functional/verilog/my_module_shr.v
@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a >> b;
+
+endmodule
diff --git a/tests/functional/verilog/my_module_sshl.v b/tests/functional/verilog/my_module_sshl.v
new file mode 100755
index 00000000000..8a2f5fe5e95
--- /dev/null
+++ b/tests/functional/verilog/my_module_sshl.v
@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a <<< b;
+
+endmodule
diff --git a/tests/functional/verilog/my_module_sshr.v b/tests/functional/verilog/my_module_sshr.v
new file mode 100755
index 00000000000..9fc46102305
--- /dev/null
+++ b/tests/functional/verilog/my_module_sshr.v
@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a >>> b;
+
+endmodule
diff --git a/tests/functional/verilog/my_module_sub.v b/tests/functional/verilog/my_module_sub.v
new file mode 100755
index 00000000000..2f4e4380e89
--- /dev/null
+++ b/tests/functional/verilog/my_module_sub.v
@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a - b;
+
+endmodule
diff --git a/tests/functional/verilog/my_module_xnor.v b/tests/functional/verilog/my_module_xnor.v
new file mode 100755
index 00000000000..4f1b0148ddb
--- /dev/null
+++ b/tests/functional/verilog/my_module_xnor.v
@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a ~^ b;
+
+endmodule
diff --git a/tests/functional/verilog/my_module_xor.v b/tests/functional/verilog/my_module_xor.v
new file mode 100755
index 00000000000..6e241186f97
--- /dev/null
+++ b/tests/functional/verilog/my_module_xor.v
@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a ^ b;
+
+endmodule