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Merge pull request #4806 from YosysHQ/micko/verific_blackbox
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verific: Disable module existence check during static elaboration
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@mmicko
mmicko authored Dec 9, 2024
2 parents 481162b + 0539888 commit d0f239a
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Showing 3 changed files with 104 additions and 23 deletions.
69 changes: 46 additions & 23 deletions frontends/verific/verific.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -2688,11 +2688,51 @@ struct VerificExtNets
}
};

#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
static msg_type_t prev_1063;
#endif
#ifdef VERIFIC_VHDL_SUPPORT
static msg_type_t prev_1240 ;
static msg_type_t prev_1241 ;
#endif
void save_blackbox_msg_state()
{
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
prev_1063 = Message::GetMessageType("VERI-1063") ;
Message::SetMessageType("VERI-1063", VERIFIC_INFO);
#endif
#ifdef VERIFIC_VHDL_SUPPORT
prev_1240 = Message::GetMessageType("VHDL-1240") ;
prev_1241 = Message::GetMessageType("VHDL-1241") ;
Message::SetMessageType("VHDL-1240", VERIFIC_INFO);
Message::SetMessageType("VHDL-1241", VERIFIC_INFO);
#endif
}

void restore_blackbox_msg_state()
{
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
Message::ClearMessageType("VERI-1063") ;
if (Message::GetMessageType("VERI-1063")!=prev_1063)
Message::SetMessageType("VERI-1063", prev_1063);
#endif
#ifdef VERIFIC_VHDL_SUPPORT
Message::ClearMessageType("VHDL-1240") ;
Message::ClearMessageType("VHDL-1241") ;
if (Message::GetMessageType("VHDL-1240")!=prev_1240)
Message::SetMessageType("VHDL-1240", prev_1240);
if (Message::GetMessageType("VHDL-1241")!=prev_1241)
Message::SetMessageType("VHDL-1241", prev_1241);
#endif
}

void import_all(const char* work, std::map<std::string,Netlist*> *nl_todo, Map *parameters, bool show_message, std::string ppfile YS_MAYBE_UNUSED)
{
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
save_blackbox_msg_state();
VerificExtensions::ElaborateAndRewrite(work, parameters);
verific_error_msg.clear();
restore_blackbox_msg_state();
#endif
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
if (!ppfile.empty())
Expand Down Expand Up @@ -2823,8 +2863,10 @@ std::set<std::string> import_tops(const char* work, std::map<std::string,Netlist

#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
if (static_elaborate) {
save_blackbox_msg_state();
VerificExtensions::ElaborateAndRewrite(work, &veri_modules, &vhdl_units, parameters);
verific_error_msg.clear();
restore_blackbox_msg_state();
#endif
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
if (!ppfile.empty())
Expand Down Expand Up @@ -3290,10 +3332,8 @@ struct VerificPass : public Pass {
return filename;
}

#ifdef VERIFIC_VHDL_SUPPORT
msg_type_t prev_1240 ;
msg_type_t prev_1241 ;

#ifdef VERIFIC_VHDL_SUPPORT
void add_units_to_map(Map &map, std::string work, bool flag_lib)
{
MapIter mi ;
Expand All @@ -3306,11 +3346,7 @@ struct VerificPass : public Pass {
map.Insert(unit,unit);
}
}

prev_1240 = Message::GetMessageType("VHDL-1240") ;
prev_1241 = Message::GetMessageType("VHDL-1241") ;
Message::SetMessageType("VHDL-1240", VERIFIC_INFO);
Message::SetMessageType("VHDL-1241", VERIFIC_INFO);
save_blackbox_msg_state();
}

void set_units_to_blackbox(Map &map, std::string work, bool flag_lib)
Expand All @@ -3325,17 +3361,10 @@ struct VerificPass : public Pass {
unit->SetCompileAsBlackbox();
}
}
Message::ClearMessageType("VHDL-1240") ;
Message::ClearMessageType("VHDL-1241") ;
if (Message::GetMessageType("VHDL-1240")!=prev_1240)
Message::SetMessageType("VHDL-1240", prev_1240);
if (Message::GetMessageType("VHDL-1241")!=prev_1241)
Message::SetMessageType("VHDL-1241", prev_1241);

restore_blackbox_msg_state();
}
#endif

msg_type_t prev_1063;
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
void add_modules_to_map(Map &map, std::string work, bool flag_lib)
{
Expand All @@ -3349,9 +3378,7 @@ struct VerificPass : public Pass {
map.Insert(veri_module,veri_module);
}
}

prev_1063 = Message::GetMessageType("VERI-1063") ;
Message::SetMessageType("VERI-1063", VERIFIC_INFO);
save_blackbox_msg_state();
}

void set_modules_to_blackbox(Map &map, std::string work, bool flag_lib)
Expand All @@ -3366,9 +3393,6 @@ struct VerificPass : public Pass {
veri_module->SetCompileAsBlackbox();
}
}
Message::ClearMessageType("VERI-1063") ;
if (Message::GetMessageType("VERI-1063")!=prev_1063)
Message::SetMessageType("VERI-1063", prev_1063);
}
#endif

Expand Down Expand Up @@ -3424,7 +3448,6 @@ struct VerificPass : public Pass {
RuntimeFlags::SetVar("veri_preserve_assignments", 1);
RuntimeFlags::SetVar("veri_preserve_comments", 1);
RuntimeFlags::SetVar("veri_preserve_drivers", 1);
RuntimeFlags::SetVar("veri_create_empty_box", 1);

// Workaround for VIPER #13851
RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1);
Expand Down
17 changes: 17 additions & 0 deletions tests/verific/blackbox_empty.ys
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Original file line number Diff line number Diff line change
@@ -0,0 +1,17 @@
verific -sv <<EOF
module TEST_CELL(input clk, input a, input b, output reg c);
parameter PATH = "DEFAULT";
endmodule
EOF

verific -sv <<EOF
module top(input clk, input a, input b, output c, output d);
TEST_CELL #(.PATH("TEST")) test1(.clk(clk),.a(a),.b(1'b1),.c(c));
TEST_CELL #(.PATH("DEFAULT")) test2(.clk(clk),.a(a),.b(1'bx),.c(d));
endmodule
EOF

verific -import top
hierarchy -top top
stat
select -assert-count 2 t:TEST_CELL
41 changes: 41 additions & 0 deletions tests/verific/blackbox_ql.ys
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,41 @@
verific -sv -lib +/quicklogic/qlf_k6n10f/dsp_sim.v

verific -sv <<EOF
module top (
input wire [19:0] a,
input wire [17:0] b,
output wire [37:0] z,
input wire clk,
input wire reset,
input wire unsigned_a,
input wire unsigned_b,
input wire f_mode,
input wire [2:0] output_select,
input wire register_inputs
);

// module instantiation
QL_DSP2_MULT_REGIN_REGOUT #(
.MODE_BITS(80'h1232324)
) u1 (
.a (a),
.b (b),
.z (z),
.clk (clk),
.reset (reset),

.unsigned_a (unsigned_a),
.unsigned_b (unsigned_b),

.f_mode (f_mode),
.output_select (output_select),
.register_inputs (register_inputs)
);
endmodule

EOF

verific -import top
hierarchy -top top
synth_quicklogic -family qlf_k6n10f
select -assert-count 1 t:QL_DSP2_MULT_REGIN_REGOUT a:MODE_BITS=80'h1232324

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