From d4546d83985d47195eb7fd0faa1eb6caab995612 Mon Sep 17 00:00:00 2001 From: George Rennie Date: Thu, 3 Oct 2024 16:34:19 +0200 Subject: [PATCH] tests: remove -seq 1 from sat with -tempinduct where possible * When used with -tempinduct mode, -seq causes assertions to be ignored in the first N steps. While this has uses for reset modelling, for these test cases it is unnecessary and could lead to failures slipping through uncaught --- tests/simple_abc9/abc9.err | 5747 +++++++++++++++++++ tests/simple_abc9/case_large.err | 609 ++ tests/simple_abc9/dynslice.err | 680 +++ tests/simple_abc9/generate.err | 1589 +++++ tests/simple_abc9/memory.err | 3096 ++++++++++ tests/simple_abc9/multiplier.err | 1388 +++++ tests/simple_abc9/operators.err | 939 +++ tests/simple_abc9/paramods.err | 925 +++ tests/simple_abc9/partsel.err | 492 ++ tests/simple_abc9/process.err | 1019 ++++ tests/simple_abc9/realexpr.err | 779 +++ tests/simple_abc9/repwhile.err | 609 ++ tests/svtypes/typedef_initial_and_assign.ys | 2 +- tests/svtypes/typedef_struct_port.ys | 4 +- tests/various/const_arg_loop.ys | 2 +- tests/various/const_func.ys | 2 +- tests/various/countbits.ys | 2 +- tests/various/param_struct.ys | 2 +- tests/verilog/atom_type_signedness.ys | 2 +- tests/verilog/int_types.ys | 2 +- tests/verilog/mem_bounds.ys | 2 +- tests/verilog/param_no_default.ys | 2 +- tests/verilog/parameters_across_files.ys | 2 +- tests/verilog/typedef_across_files.ys | 2 +- tests/verilog/typedef_legacy_conflict.ys | 2 +- tests/verilog/unbased_unsized.ys | 2 +- tests/verilog/unbased_unsized_shift.ys | 2 +- 27 files changed, 17888 insertions(+), 16 deletions(-) create mode 100644 tests/simple_abc9/abc9.err create mode 100644 tests/simple_abc9/case_large.err create mode 100644 tests/simple_abc9/dynslice.err create mode 100644 tests/simple_abc9/generate.err create mode 100644 tests/simple_abc9/memory.err create mode 100644 tests/simple_abc9/multiplier.err create mode 100644 tests/simple_abc9/operators.err create mode 100644 tests/simple_abc9/paramods.err create mode 100644 tests/simple_abc9/partsel.err create mode 100644 tests/simple_abc9/process.err create mode 100644 tests/simple_abc9/realexpr.err create mode 100644 tests/simple_abc9/repwhile.err diff --git a/tests/simple_abc9/abc9.err b/tests/simple_abc9/abc9.err new file mode 100644 index 00000000000..9c5cc4b0335 --- /dev/null +++ b/tests/simple_abc9/abc9.err @@ -0,0 +1,5747 @@ ++ body ++ cd abc9.out +++ basename abc9.v ++ fn=abc9.v +++ basename abc9 ++ bn=abc9 ++ refext=v ++ rm -f abc9_ref.fir ++ [[ v == \v ]] ++ egrep -v '^\s*`timescale' ../abc9.v +egrep: warning: egrep is obsolescent; using grep -E ++ '[' '!' -f ../abc9_tb.v ']' ++ /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../yosys -f 'verilog -noblackbox -specify -D_AUTOTB' -b 'test_autotb -n 300' -o abc9_tb.v abc9_ref.v + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2024 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) + +-- Parsing `abc9_ref.v' using frontend `verilog -noblackbox -specify -D_AUTOTB' -- + +1. Executing Verilog-2005 frontend: abc9_ref.v +Parsing Verilog input from `abc9_ref.v' to AST representation. +Warning: Yosys has only limited support for tri-state logic at the moment. (abc9_ref.v:55) +Warning: Yosys has only limited support for tri-state logic at the moment. (abc9_ref.v:63) +Warning: Yosys has only limited support for tri-state logic at the moment. (abc9_ref.v:79) +Warning: Yosys has only limited support for tri-state logic at the moment. (abc9_ref.v:89) +Warning: Yosys has only limited support for tri-state logic at the moment. (abc9_ref.v:90) +Warning: Yosys has only limited support for tri-state logic at the moment. (abc9_ref.v:104) +Warning: Yosys has only limited support for tri-state logic at the moment. (abc9_ref.v:105) +Generating RTLIL representation for module `\abc9_test001'. +Generating RTLIL representation for module `\abc9_test002'. +Generating RTLIL representation for module `\abc9_test003'. +Generating RTLIL representation for module `\abc9_test004'. +Generating RTLIL representation for module `\abc9_test005'. +Generating RTLIL representation for module `\abc9_test006'. +Generating RTLIL representation for module `\abc9_test007'. +Generating RTLIL representation for module `\abc9_test007_sub'. +Generating RTLIL representation for module `\abc9_test008'. +Generating RTLIL representation for module `\abc9_test008_sub'. +Generating RTLIL representation for module `\abc9_test009'. +Note: Assuming pure combinatorial block at abc9_ref.v:52.1-54.21 in +compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending +use of @* instead of @(...) for better match of synthesis and simulation. +Generating RTLIL representation for module `\abc9_test010'. +Note: Assuming pure combinatorial block at abc9_ref.v:60.1-62.21 in +compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending +use of @* instead of @(...) for better match of synthesis and simulation. +Generating RTLIL representation for module `\abc9_test011'. +Note: Assuming pure combinatorial block at abc9_ref.v:68.1-70.21 in +compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending +use of @* instead of @(...) for better match of synthesis and simulation. +Generating RTLIL representation for module `\abc9_test012'. +Generating RTLIL representation for module `\abc9_test013'. +abc9_ref.v:88: Warning: Range select [7:4] out of bounds on signal `\latch': Setting all 4 result bits to undef. +Note: Assuming pure combinatorial block at abc9_ref.v:84.1-88.26 in +compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending +use of @* instead of @(...) for better match of synthesis and simulation. +abc9_ref.v:88: Warning: Range select [7:4] out of bounds on signal `\latch': Setting all 4 result bits to undef. +abc9_ref.v:90: Warning: Range select [7:4] out of bounds on signal `\io': Setting all 4 result bits to undef. +abc9_ref.v:90: Warning: Range [7:3] select out of bounds on signal `\latch': Setting 4 MSB bits to undef. +abc9_ref.v:90: Warning: Range select out of bounds on signal `\latch': Setting result bit to undef. +abc9_ref.v:90: Warning: Ignoring assignment to constant bits: + old assignment: 4'x = $ternary$abc9_ref.v:90$34_Y [3:0] + new assignment: { } = { }. +Generating RTLIL representation for module `\abc9_test014'. +Generating RTLIL representation for module `\abc9_test012_sub'. +Note: Assuming pure combinatorial block at abc9_ref.v:99.1-103.26 in +compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending +use of @* instead of @(...) for better match of synthesis and simulation. +Generating RTLIL representation for module `\abc9_test015'. +Generating RTLIL representation for module `\abc9_test016'. +Generating RTLIL representation for module `\abc9_test017'. +Generating RTLIL representation for module `\abc9_test018'. +Generating RTLIL representation for module `\abc9_test019'. +Generating RTLIL representation for module `\abc9_test020'. +Generating RTLIL representation for module `\abc9_test021'. +abc9_ref.v:192: Warning: Identifier `\o' is implicitly declared. +abc9_ref.v:196: Warning: Identifier `\acknowledge' is implicitly declared. +abc9_ref.v:199: Warning: Identifier `\grant_encoded' is implicitly declared. +abc9_ref.v:200: Warning: Identifier `\grant_valid' is implicitly declared. +Generating RTLIL representation for module `\arbiter'. +Generating RTLIL representation for module `\MUXF8'. +Generating RTLIL representation for module `\abc9_test022'. +Generating RTLIL representation for module `\abc9_test023'. +Generating RTLIL representation for module `\abc9_test024'. +Generating RTLIL representation for module `\abc9_test024_sub'. +Generating RTLIL representation for module `\abc9_test025'. +Generating RTLIL representation for module `\abc9_test026'. +Generating RTLIL representation for module `\abc9_test030'. +Generating RTLIL representation for module `\abc9_test031'. +Generating RTLIL representation for module `\abc9_test032'. +Generating RTLIL representation for module `\abc9_test033'. +Generating RTLIL representation for module `\abc9_test034'. +Generating RTLIL representation for module `\abc9_test035'. +Generating RTLIL representation for module `\abc9_test036'. +Generating RTLIL representation for module `\MUXF7'. +Generating RTLIL representation for module `\abc9_test037'. +Successfully finished Verilog frontend. + +-- Writing to `abc9_tb.v' using backend `test_autotb -n 300' -- + +2. Executing TEST_AUTOTB backend (auto-generate pseudo-random test benches). +Generating test bench for module `\abc9_test037'. +Generating test bench for module `\MUXF7'. +Generating test bench for module `\abc9_test036'. +Generating test bench for module `\abc9_test035'. +Generating test bench for module `\abc9_test034'. +Generating test bench for module `\abc9_test033'. +Generating test bench for module `\abc9_test032'. +Generating test bench for module `\abc9_test031'. +Generating test bench for module `\abc9_test030'. +Generating test bench for module `\abc9_test026'. +Generating test bench for module `\abc9_test025'. +Generating test bench for module `\abc9_test024_sub'. +Generating test bench for module `\abc9_test024'. +Generating test bench for module `\abc9_test023'. +Generating test bench for module `\abc9_test022'. +Generating test bench for module `\MUXF8'. +Generating test bench for module `\arbiter'. +Generating test bench for module `\abc9_test021'. +Generating test bench for module `\abc9_test020'. +Generating test bench for module `\abc9_test019'. +Generating test bench for module `\abc9_test018'. +Generating test bench for module `\abc9_test017'. +Generating test bench for module `\abc9_test016'. +Generating test bench for module `\abc9_test015'. +Generating test bench for module `\abc9_test012_sub'. +Generating test bench for module `\abc9_test014'. +Generating test bench for module `\abc9_test013'. +Generating test bench for module `\abc9_test012'. +Generating test bench for module `\abc9_test011'. +Generating test bench for module `\abc9_test010'. +Generating test bench for module `\abc9_test009'. +Generating test bench for module `\abc9_test008_sub'. +Generating test bench for module `\abc9_test008'. +Generating test bench for module `\abc9_test007_sub'. +Generating test bench for module `\abc9_test007'. +Generating test bench for module `\abc9_test006'. +Generating test bench for module `\abc9_test005'. +Generating test bench for module `\abc9_test004'. +Generating test bench for module `\abc9_test003'. +Generating test bench for module `\abc9_test002'. +Generating test bench for module `\abc9_test001'. + +Warnings: 16 unique messages, 17 total +End of script. Logfile hash: a92aff5acb, CPU: user 0.01s system 0.00s, MEM: 15.04 MB peak +Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) +Time spent: 80% 1x read_verilog (0 sec), 19% 1x test_autotb (0 sec) ++ false ++ compile_and_run abc9_tb_ref abc9_out_ref abc9_tb.v abc9_ref.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simlib.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simcells.v ++ exe=abc9_tb_ref ++ output=abc9_out_ref ++ shift 2 ++ '[' v == sv ']' ++ language_gen=-g2005 ++ false ++ false ++ iverilog -g2005 '-Doutfile="abc9_out_ref"' -s testbench -o abc9_tb_ref abc9_tb.v abc9_ref.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simlib.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simcells.v +abc9_ref.v:195: warning: Port 3 (request) of arbiter expects 4 bits, got 1. +abc9_ref.v:195: : Padding 3 high bits of the port. +abc9_ref.v:195: warning: Port 4 (acknowledge) of arbiter expects 4 bits, got 1. +abc9_ref.v:195: : Padding 3 high bits of the port. +abc9_ref.v:195: warning: Port 5 (grant) of arbiter expects 4 bits, got 1. +abc9_ref.v:195: : Padding 3 high bits of the port. +abc9_ref.v:195: warning: Port 7 (grant_encoded) of arbiter expects 2 bits, got 1. +abc9_ref.v:195: : Padding 1 high bits of the port. +abc9_ref.v:90: warning: Part select io[7:4] is out of range. ++ vvp -n abc9_tb_ref +abc9_tb.v:2800: $finish called at 4871400 (1s) ++ false ++ test_count=0 ++ '[' 'verilog -noblackbox -specify' = verific -o 'verilog -noblackbox -specify' = verific_gates ']' ++ '[' -n '' ']' ++ '[' -n ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' ']' ++ test_passes -f 'verilog -noblackbox -specify ' -p ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' abc9_ref.v ++ /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../yosys -b 'verilog -noattr -noexpr -siminit' -o abc9_syn0.v -f 'verilog -noblackbox -specify ' -p ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' abc9_ref.v + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2024 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) + +-- Parsing `abc9_ref.v' using frontend `verilog -noblackbox -specify ' -- + +1. Executing Verilog-2005 frontend: abc9_ref.v +Parsing Verilog input from `abc9_ref.v' to AST representation. +Warning: Yosys has only limited support for tri-state logic at the moment. (abc9_ref.v:55) +Warning: Yosys has only limited support for tri-state logic at the moment. (abc9_ref.v:63) +Warning: Yosys has only limited support for tri-state logic at the moment. (abc9_ref.v:79) +Warning: Yosys has only limited support for tri-state logic at the moment. (abc9_ref.v:89) +Warning: Yosys has only limited support for tri-state logic at the moment. (abc9_ref.v:90) +Warning: Yosys has only limited support for tri-state logic at the moment. (abc9_ref.v:104) +Warning: Yosys has only limited support for tri-state logic at the moment. (abc9_ref.v:105) +Generating RTLIL representation for module `\abc9_test001'. +Generating RTLIL representation for module `\abc9_test002'. +Generating RTLIL representation for module `\abc9_test003'. +Generating RTLIL representation for module `\abc9_test004'. +Generating RTLIL representation for module `\abc9_test005'. +Generating RTLIL representation for module `\abc9_test006'. +Generating RTLIL representation for module `\abc9_test007'. +Generating RTLIL representation for module `\abc9_test007_sub'. +Generating RTLIL representation for module `\abc9_test008'. +Generating RTLIL representation for module `\abc9_test008_sub'. +Generating RTLIL representation for module `\abc9_test009'. +Note: Assuming pure combinatorial block at abc9_ref.v:52.1-54.21 in +compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending +use of @* instead of @(...) for better match of synthesis and simulation. +Generating RTLIL representation for module `\abc9_test010'. +Note: Assuming pure combinatorial block at abc9_ref.v:60.1-62.21 in +compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending +use of @* instead of @(...) for better match of synthesis and simulation. +Generating RTLIL representation for module `\abc9_test011'. +Note: Assuming pure combinatorial block at abc9_ref.v:68.1-70.21 in +compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending +use of @* instead of @(...) for better match of synthesis and simulation. +Generating RTLIL representation for module `\abc9_test012'. +Generating RTLIL representation for module `\abc9_test013'. +abc9_ref.v:88: Warning: Range select [7:4] out of bounds on signal `\latch': Setting all 4 result bits to undef. +Note: Assuming pure combinatorial block at abc9_ref.v:84.1-88.26 in +compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending +use of @* instead of @(...) for better match of synthesis and simulation. +abc9_ref.v:88: Warning: Range select [7:4] out of bounds on signal `\latch': Setting all 4 result bits to undef. +abc9_ref.v:90: Warning: Range select [7:4] out of bounds on signal `\io': Setting all 4 result bits to undef. +abc9_ref.v:90: Warning: Range [7:3] select out of bounds on signal `\latch': Setting 4 MSB bits to undef. +abc9_ref.v:90: Warning: Range select out of bounds on signal `\latch': Setting result bit to undef. +abc9_ref.v:90: Warning: Ignoring assignment to constant bits: + old assignment: 4'x = $ternary$abc9_ref.v:90$34_Y [3:0] + new assignment: { } = { }. +Generating RTLIL representation for module `\abc9_test014'. +Generating RTLIL representation for module `\abc9_test012_sub'. +Note: Assuming pure combinatorial block at abc9_ref.v:99.1-103.26 in +compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending +use of @* instead of @(...) for better match of synthesis and simulation. +Generating RTLIL representation for module `\abc9_test015'. +Generating RTLIL representation for module `\abc9_test016'. +Generating RTLIL representation for module `\abc9_test017'. +Generating RTLIL representation for module `\abc9_test018'. +Generating RTLIL representation for module `\abc9_test019'. +Generating RTLIL representation for module `\abc9_test020'. +Generating RTLIL representation for module `\abc9_test021'. +abc9_ref.v:192: Warning: Identifier `\o' is implicitly declared. +abc9_ref.v:196: Warning: Identifier `\acknowledge' is implicitly declared. +abc9_ref.v:199: Warning: Identifier `\grant_encoded' is implicitly declared. +abc9_ref.v:200: Warning: Identifier `\grant_valid' is implicitly declared. +Generating RTLIL representation for module `\arbiter'. +Generating RTLIL representation for module `\MUXF8'. +Generating RTLIL representation for module `\abc9_test022'. +Generating RTLIL representation for module `\abc9_test023'. +Generating RTLIL representation for module `\abc9_test024'. +Generating RTLIL representation for module `\abc9_test024_sub'. +Generating RTLIL representation for module `\abc9_test025'. +Generating RTLIL representation for module `\abc9_test026'. +Generating RTLIL representation for module `\abc9_test030'. +Generating RTLIL representation for module `\abc9_test031'. +Generating RTLIL representation for module `\abc9_test032'. +Generating RTLIL representation for module `\abc9_test033'. +Generating RTLIL representation for module `\abc9_test034'. +Generating RTLIL representation for module `\abc9_test035'. +Generating RTLIL representation for module `\abc9_test036'. +Generating RTLIL representation for module `\MUXF7'. +Generating RTLIL representation for module `\abc9_test037'. +Successfully finished Verilog frontend. + +-- Running command ` read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' -- + +2. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v' to AST representation. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +3. Executing HIERARCHY pass (managing design hierarchy). +Mapping positional arguments of cell abc9_test025.a (abc9_test024_sub). +Mapping positional arguments of cell abc9_test024.a (abc9_test024_sub). +Mapping positional arguments of cell abc9_test014.sub (abc9_test012_sub). +Mapping positional arguments of cell abc9_test008.s (abc9_test008_sub). +Mapping positional arguments of cell abc9_test007.s (abc9_test007_sub). +Warning: Resizing cell port abc9_test021.arb_inst.request from 1 bits to 4 bits. +Warning: Resizing cell port abc9_test021.arb_inst.grant_encoded from 1 bits to 2 bits. +Warning: Resizing cell port abc9_test021.arb_inst.grant from 1 bits to 4 bits. +Warning: Resizing cell port abc9_test021.arb_inst.acknowledge from 1 bits to 4 bits. + +4. Executing SYNTH pass. + +4.1. Executing PROC pass (convert processes to netlists). + +4.1.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +4.1.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$abc9_ref.v:285$68 in module abc9_test033. +Marked 1 switch rules as full_case in process $proc$abc9_ref.v:279$67 in module abc9_test032. +Marked 1 switch rules as full_case in process $proc$abc9_ref.v:99$35 in module abc9_test012_sub. +Removed a total of 0 dead cases. + +4.1.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 2 redundant assignments. +Promoted 12 assignments to connections. + +4.1.4. Executing PROC_INIT pass (extract init attributes). +Found init rule in `\abc9_test022.$proc$abc9_ref.v:232$61'. + Set init value: \m_eth_payload_axis_tkeep_reg = 8'00000000 + +4.1.5. Executing PROC_ARST pass (detect async resets in processes). +Found async reset \r in `\abc9_test033.$proc$abc9_ref.v:285$68'. +Found async reset \r in `\abc9_test032.$proc$abc9_ref.v:279$67'. + +4.1.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +4.1.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\abc9_test035.$proc$abc9_ref.v:297$72'. +Creating decoders for process `\abc9_test035.$proc$abc9_ref.v:296$71'. +Creating decoders for process `\abc9_test034.$proc$abc9_ref.v:292$70'. +Creating decoders for process `\abc9_test034.$proc$abc9_ref.v:291$69'. +Creating decoders for process `\abc9_test033.$proc$abc9_ref.v:285$68'. + 1/1: $0\q[0:0] +Creating decoders for process `\abc9_test032.$proc$abc9_ref.v:279$67'. + 1/1: $0\q[0:0] +Creating decoders for process `\abc9_test031.$proc$abc9_ref.v:275$66'. +Creating decoders for process `\abc9_test031.$proc$abc9_ref.v:274$65'. +Creating decoders for process `\abc9_test030.$proc$abc9_ref.v:268$64'. + 1/1: $0\q[3:0] +Creating decoders for process `\abc9_test022.$proc$abc9_ref.v:232$61'. +Creating decoders for process `\abc9_test022.$proc$abc9_ref.v:234$59'. +Creating decoders for process `\abc9_test020.$proc$abc9_ref.v:143$55'. +Creating decoders for process `\abc9_test019.$proc$abc9_ref.v:136$52'. +Creating decoders for process `\abc9_test017.$proc$abc9_ref.v:123$48'. +Creating decoders for process `\abc9_test016.$proc$abc9_ref.v:117$45'. +Creating decoders for process `\abc9_test012_sub.$proc$abc9_ref.v:99$35'. + 1/2: $0\latch[7:0] [7:4] + 2/2: $0\latch[7:0] [3:0] +Creating decoders for process `\abc9_test013.$proc$abc9_ref.v:84$28'. + 1/1: $0\latch[3:0] +Creating decoders for process `\abc9_test011.$proc$abc9_ref.v:68$23'. + 1/1: $0\latch[0:0] +Creating decoders for process `\abc9_test010.$proc$abc9_ref.v:60$19'. + 1/1: $0\latch[7:0] +Creating decoders for process `\abc9_test009.$proc$abc9_ref.v:52$15'. + 1/1: $0\latch[0:0] + +4.1.8. Executing PROC_DLATCH pass (convert process syncs to latches). +Latch inferred for signal `\abc9_test030.\q' from process `\abc9_test030.$proc$abc9_ref.v:268$64': $auto$proc_dlatch.cc:433:proc_dlatch$102 +No latch inferred for signal `\abc9_test020.\d' from process `\abc9_test020.$proc$abc9_ref.v:143$55'. +No latch inferred for signal `\abc9_test019.\d' from process `\abc9_test019.$proc$abc9_ref.v:136$52'. +No latch inferred for signal `\abc9_test017.\c' from process `\abc9_test017.$proc$abc9_ref.v:123$48'. +No latch inferred for signal `\abc9_test016.\c' from process `\abc9_test016.$proc$abc9_ref.v:117$45'. +Latch inferred for signal `\abc9_test012_sub.\latch [3:0]' from process `\abc9_test012_sub.$proc$abc9_ref.v:99$35': $auto$proc_dlatch.cc:433:proc_dlatch$113 +Latch inferred for signal `\abc9_test012_sub.\latch [7:4]' from process `\abc9_test012_sub.$proc$abc9_ref.v:99$35': $auto$proc_dlatch.cc:433:proc_dlatch$122 +Latch inferred for signal `\abc9_test013.\latch' from process `\abc9_test013.$proc$abc9_ref.v:84$28': $auto$proc_dlatch.cc:433:proc_dlatch$133 +Latch inferred for signal `\abc9_test011.\latch' from process `\abc9_test011.$proc$abc9_ref.v:68$23': $auto$proc_dlatch.cc:433:proc_dlatch$144 +Latch inferred for signal `\abc9_test010.\latch' from process `\abc9_test010.$proc$abc9_ref.v:60$19': $auto$proc_dlatch.cc:433:proc_dlatch$155 +Latch inferred for signal `\abc9_test009.\latch' from process `\abc9_test009.$proc$abc9_ref.v:52$15': $auto$proc_dlatch.cc:433:proc_dlatch$166 + +4.1.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\abc9_test035.\q [1]' using process `\abc9_test035.$proc$abc9_ref.v:297$72'. + created $dff cell `$procdff$167' with negative edge clock. +Creating register for signal `\abc9_test035.\q [0]' using process `\abc9_test035.$proc$abc9_ref.v:296$71'. + created $dff cell `$procdff$168' with positive edge clock. +Creating register for signal `\abc9_test034.\q2' using process `\abc9_test034.$proc$abc9_ref.v:292$70'. + created $dff cell `$procdff$169' with positive edge clock. +Creating register for signal `\abc9_test034.\q1' using process `\abc9_test034.$proc$abc9_ref.v:291$69'. + created $dff cell `$procdff$170' with positive edge clock. +Creating register for signal `\abc9_test033.\q' using process `\abc9_test033.$proc$abc9_ref.v:285$68'. + created $adff cell `$procdff$173' with negative edge clock and positive level reset. +Creating register for signal `\abc9_test032.\q' using process `\abc9_test032.$proc$abc9_ref.v:279$67'. + created $adff cell `$procdff$176' with positive edge clock and positive level reset. +Creating register for signal `\abc9_test031.\q2' using process `\abc9_test031.$proc$abc9_ref.v:275$66'. + created $dff cell `$procdff$177' with negative edge clock. +Creating register for signal `\abc9_test031.\q1' using process `\abc9_test031.$proc$abc9_ref.v:274$65'. + created $dff cell `$procdff$178' with positive edge clock. +Creating register for signal `\abc9_test022.\m_eth_payload_axis_tkeep_reg' using process `\abc9_test022.$proc$abc9_ref.v:234$59'. + created $dff cell `$procdff$179' with positive edge clock. + +4.1.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +4.1.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `abc9_test035.$proc$abc9_ref.v:297$72'. +Removing empty process `abc9_test035.$proc$abc9_ref.v:296$71'. +Removing empty process `abc9_test034.$proc$abc9_ref.v:292$70'. +Removing empty process `abc9_test034.$proc$abc9_ref.v:291$69'. +Removing empty process `abc9_test033.$proc$abc9_ref.v:285$68'. +Removing empty process `abc9_test032.$proc$abc9_ref.v:279$67'. +Removing empty process `abc9_test031.$proc$abc9_ref.v:275$66'. +Removing empty process `abc9_test031.$proc$abc9_ref.v:274$65'. +Found and cleaned up 1 empty switch in `\abc9_test030.$proc$abc9_ref.v:268$64'. +Removing empty process `abc9_test030.$proc$abc9_ref.v:268$64'. +Removing empty process `abc9_test022.$proc$abc9_ref.v:232$61'. +Removing empty process `abc9_test022.$proc$abc9_ref.v:234$59'. +Removing empty process `abc9_test020.$proc$abc9_ref.v:143$55'. +Removing empty process `abc9_test019.$proc$abc9_ref.v:136$52'. +Removing empty process `abc9_test017.$proc$abc9_ref.v:123$48'. +Removing empty process `abc9_test016.$proc$abc9_ref.v:117$45'. +Found and cleaned up 1 empty switch in `\abc9_test012_sub.$proc$abc9_ref.v:99$35'. +Removing empty process `abc9_test012_sub.$proc$abc9_ref.v:99$35'. +Found and cleaned up 1 empty switch in `\abc9_test013.$proc$abc9_ref.v:84$28'. +Removing empty process `abc9_test013.$proc$abc9_ref.v:84$28'. +Found and cleaned up 1 empty switch in `\abc9_test011.$proc$abc9_ref.v:68$23'. +Removing empty process `abc9_test011.$proc$abc9_ref.v:68$23'. +Found and cleaned up 1 empty switch in `\abc9_test010.$proc$abc9_ref.v:60$19'. +Removing empty process `abc9_test010.$proc$abc9_ref.v:60$19'. +Found and cleaned up 1 empty switch in `\abc9_test009.$proc$abc9_ref.v:52$15'. +Removing empty process `abc9_test009.$proc$abc9_ref.v:52$15'. +Cleaned up 6 empty switches. + +4.1.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module abc9_test037. +Optimizing module abc9_test036. +Optimizing module abc9_test035. +Optimizing module abc9_test034. +Optimizing module abc9_test033. + +Optimizing module abc9_test032. + +Optimizing module abc9_test031. +Optimizing module abc9_test030. + +Optimizing module abc9_test026. +Optimizing module abc9_test025. +Optimizing module abc9_test024_sub. +Optimizing module abc9_test024. +Optimizing module abc9_test023. + +Optimizing module abc9_test022. +Optimizing module arbiter. +Optimizing module abc9_test021. +Optimizing module abc9_test020. +Optimizing module abc9_test019. +Optimizing module abc9_test018. +Optimizing module abc9_test017. +Optimizing module abc9_test016. +Optimizing module abc9_test015. +Optimizing module abc9_test012_sub. + +Optimizing module abc9_test014. +Optimizing module abc9_test013. + +Optimizing module abc9_test012. +Optimizing module abc9_test011. + +Optimizing module abc9_test010. + +Optimizing module abc9_test009. + +Optimizing module abc9_test008_sub. +Optimizing module abc9_test008. +Optimizing module abc9_test007_sub. +Optimizing module abc9_test007. +Optimizing module abc9_test006. +Optimizing module abc9_test005. +Optimizing module abc9_test004. +Optimizing module abc9_test003. +Optimizing module abc9_test002. +Optimizing module abc9_test001. + +4.2. Executing OPT_EXPR pass (perform const folding). +Optimizing module abc9_test037. +Optimizing module abc9_test036. +Optimizing module abc9_test035. +Optimizing module abc9_test034. +Optimizing module abc9_test033. +Optimizing module abc9_test032. +Optimizing module abc9_test031. +Optimizing module abc9_test030. +Optimizing module abc9_test026. +Optimizing module abc9_test025. +Optimizing module abc9_test024_sub. +Optimizing module abc9_test024. +Optimizing module abc9_test023. +Optimizing module abc9_test022. +Optimizing module arbiter. +Optimizing module abc9_test021. +Optimizing module abc9_test020. +Optimizing module abc9_test019. +Optimizing module abc9_test018. +Optimizing module abc9_test017. +Optimizing module abc9_test016. +Optimizing module abc9_test015. +Optimizing module abc9_test012_sub. +Optimizing module abc9_test014. +Optimizing module abc9_test013. +Optimizing module abc9_test012. +Optimizing module abc9_test011. +Optimizing module abc9_test010. +Optimizing module abc9_test009. +Optimizing module abc9_test008_sub. +Optimizing module abc9_test008. +Optimizing module abc9_test007_sub. +Optimizing module abc9_test007. +Optimizing module abc9_test006. +Optimizing module abc9_test005. +Optimizing module abc9_test004. +Optimizing module abc9_test003. +Optimizing module abc9_test002. +Optimizing module abc9_test001. + +4.3. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \abc9_test037.. +Finding unused cells or wires in module \abc9_test036.. +Finding unused cells or wires in module \abc9_test035.. +Finding unused cells or wires in module \abc9_test034.. +Finding unused cells or wires in module \abc9_test033.. +Finding unused cells or wires in module \abc9_test032.. +Finding unused cells or wires in module \abc9_test031.. +Finding unused cells or wires in module \abc9_test030.. +Finding unused cells or wires in module \abc9_test026.. +Finding unused cells or wires in module \abc9_test025.. +Finding unused cells or wires in module \abc9_test024_sub.. +Finding unused cells or wires in module \abc9_test024.. +Finding unused cells or wires in module \abc9_test023.. +Finding unused cells or wires in module \abc9_test022.. +Finding unused cells or wires in module \arbiter.. +Finding unused cells or wires in module \abc9_test021.. +Finding unused cells or wires in module \abc9_test020.. +Finding unused cells or wires in module \abc9_test019.. +Finding unused cells or wires in module \abc9_test018.. +Finding unused cells or wires in module \abc9_test017.. +Finding unused cells or wires in module \abc9_test016.. +Finding unused cells or wires in module \abc9_test015.. +Finding unused cells or wires in module \abc9_test012_sub.. +Finding unused cells or wires in module \abc9_test014.. +Finding unused cells or wires in module \abc9_test013.. +Finding unused cells or wires in module \abc9_test012.. +Finding unused cells or wires in module \abc9_test011.. +Finding unused cells or wires in module \abc9_test010.. +Finding unused cells or wires in module \abc9_test009.. +Finding unused cells or wires in module \abc9_test008_sub.. +Finding unused cells or wires in module \abc9_test008.. +Finding unused cells or wires in module \abc9_test007_sub.. +Finding unused cells or wires in module \abc9_test007.. +Finding unused cells or wires in module \abc9_test006.. +Finding unused cells or wires in module \abc9_test005.. +Finding unused cells or wires in module \abc9_test004.. +Finding unused cells or wires in module \abc9_test003.. +Finding unused cells or wires in module \abc9_test002.. +Finding unused cells or wires in module \abc9_test001.. +Removed 16 unused cells and 113 unused wires. + + +4.4. Executing CHECK pass (checking for obvious problems). +Checking module abc9_test001... +Checking module abc9_test002... +Checking module abc9_test003... +Checking module abc9_test004... +Checking module abc9_test005... +Checking module abc9_test006... +Checking module abc9_test007... +Checking module abc9_test007_sub... +Checking module abc9_test008... +Checking module abc9_test008_sub... +Checking module abc9_test009... +Warning: found logic loop in module abc9_test009: + cell $auto$proc_dlatch.cc:433:proc_dlatch$166 ($dlatch) source: abc9_ref.v:52.1-54.21 + D[0] --> Q[0] + wire \latch source: abc9_ref.v:51.5-51.10 + cell $not$abc9_ref.v:55$17 ($not) source: abc9_ref.v:55.18-55.24 + A[0] --> Y[0] + wire \io source: abc9_ref.v:50.27-50.29 +Checking module abc9_test010... +Warning: found logic loop in module abc9_test010: + cell $auto$proc_dlatch.cc:433:proc_dlatch$155 ($dlatch) source: abc9_ref.v:60.1-62.21 + D[0] --> Q[0] + wire \latch [0] source: abc9_ref.v:59.11-59.16 + cell $not$abc9_ref.v:63$21 ($not) source: abc9_ref.v:63.18-63.24 + A[0] --> Y[0] + wire \io [0] source: abc9_ref.v:58.33-58.35 +Warning: found logic loop in module abc9_test010: + cell $auto$proc_dlatch.cc:433:proc_dlatch$155 ($dlatch) source: abc9_ref.v:60.1-62.21 + D[1] --> Q[1] + wire \latch [1] source: abc9_ref.v:59.11-59.16 + cell $not$abc9_ref.v:63$21 ($not) source: abc9_ref.v:63.18-63.24 + A[1] --> Y[1] + wire \io [1] source: abc9_ref.v:58.33-58.35 +Warning: found logic loop in module abc9_test010: + cell $auto$proc_dlatch.cc:433:proc_dlatch$155 ($dlatch) source: abc9_ref.v:60.1-62.21 + D[2] --> Q[2] + wire \latch [2] source: abc9_ref.v:59.11-59.16 + cell $not$abc9_ref.v:63$21 ($not) source: abc9_ref.v:63.18-63.24 + A[2] --> Y[2] + wire \io [2] source: abc9_ref.v:58.33-58.35 +Warning: found logic loop in module abc9_test010: + cell $auto$proc_dlatch.cc:433:proc_dlatch$155 ($dlatch) source: abc9_ref.v:60.1-62.21 + D[3] --> Q[3] + wire \latch [3] source: abc9_ref.v:59.11-59.16 + cell $not$abc9_ref.v:63$21 ($not) source: abc9_ref.v:63.18-63.24 + A[3] --> Y[3] + wire \io [3] source: abc9_ref.v:58.33-58.35 +Warning: found logic loop in module abc9_test010: + cell $auto$proc_dlatch.cc:433:proc_dlatch$155 ($dlatch) source: abc9_ref.v:60.1-62.21 + D[4] --> Q[4] + wire \latch [4] source: abc9_ref.v:59.11-59.16 + cell $not$abc9_ref.v:63$21 ($not) source: abc9_ref.v:63.18-63.24 + A[4] --> Y[4] + wire \io [4] source: abc9_ref.v:58.33-58.35 +Warning: found logic loop in module abc9_test010: + cell $auto$proc_dlatch.cc:433:proc_dlatch$155 ($dlatch) source: abc9_ref.v:60.1-62.21 + D[5] --> Q[5] + wire \latch [5] source: abc9_ref.v:59.11-59.16 + cell $not$abc9_ref.v:63$21 ($not) source: abc9_ref.v:63.18-63.24 + A[5] --> Y[5] + wire \io [5] source: abc9_ref.v:58.33-58.35 +Warning: found logic loop in module abc9_test010: + cell $auto$proc_dlatch.cc:433:proc_dlatch$155 ($dlatch) source: abc9_ref.v:60.1-62.21 + D[6] --> Q[6] + wire \latch [6] source: abc9_ref.v:59.11-59.16 + cell $not$abc9_ref.v:63$21 ($not) source: abc9_ref.v:63.18-63.24 + A[6] --> Y[6] + wire \io [6] source: abc9_ref.v:58.33-58.35 +Warning: found logic loop in module abc9_test010: + cell $auto$proc_dlatch.cc:433:proc_dlatch$155 ($dlatch) source: abc9_ref.v:60.1-62.21 + D[7] --> Q[7] + wire \latch [7] source: abc9_ref.v:59.11-59.16 + cell $not$abc9_ref.v:63$21 ($not) source: abc9_ref.v:63.18-63.24 + A[7] --> Y[7] + wire \io [7] source: abc9_ref.v:58.33-58.35 +Checking module abc9_test011... +Checking module abc9_test012... +Warning: Wire abc9_test012.\latch is used but has no driver. +Checking module abc9_test012_sub... +Warning: found logic loop in module abc9_test012_sub: + cell $auto$proc_dlatch.cc:433:proc_dlatch$113 ($dlatch) source: abc9_ref.v:99.1-103.26 + D[0] --> Q[0] + wire \latch [0] source: abc9_ref.v:98.11-98.16 + cell $not$abc9_ref.v:104$37 ($not) source: abc9_ref.v:104.23-104.34 + A[0] --> Y[0] + wire \io [0] source: abc9_ref.v:97.37-97.39 +Warning: found logic loop in module abc9_test012_sub: + cell $auto$proc_dlatch.cc:433:proc_dlatch$113 ($dlatch) source: abc9_ref.v:99.1-103.26 + D[1] --> Q[1] + wire \latch [1] source: abc9_ref.v:98.11-98.16 + cell $not$abc9_ref.v:104$37 ($not) source: abc9_ref.v:104.23-104.34 + A[1] --> Y[1] + wire \io [1] source: abc9_ref.v:97.37-97.39 +Warning: found logic loop in module abc9_test012_sub: + cell $auto$proc_dlatch.cc:433:proc_dlatch$113 ($dlatch) source: abc9_ref.v:99.1-103.26 + D[2] --> Q[2] + wire \latch [2] source: abc9_ref.v:98.11-98.16 + cell $not$abc9_ref.v:104$37 ($not) source: abc9_ref.v:104.23-104.34 + A[2] --> Y[2] + wire \io [2] source: abc9_ref.v:97.37-97.39 +Warning: found logic loop in module abc9_test012_sub: + cell $auto$proc_dlatch.cc:433:proc_dlatch$113 ($dlatch) source: abc9_ref.v:99.1-103.26 + D[3] --> Q[3] + wire \latch [3] source: abc9_ref.v:98.11-98.16 + cell $not$abc9_ref.v:104$37 ($not) source: abc9_ref.v:104.23-104.34 + A[3] --> Y[3] + wire \io [3] source: abc9_ref.v:97.37-97.39 +Checking module abc9_test013... +Warning: found logic loop in module abc9_test013: + cell $auto$proc_dlatch.cc:433:proc_dlatch$133 ($dlatch) source: abc9_ref.v:84.1-88.26 + D[0] --> Q[0] + wire \latch [0] source: abc9_ref.v:83.11-83.16 + cell $not$abc9_ref.v:89$30 ($not) source: abc9_ref.v:89.23-89.34 + A[0] --> Y[0] + wire \io [0] source: abc9_ref.v:82.33-82.35 +Warning: found logic loop in module abc9_test013: + cell $auto$proc_dlatch.cc:433:proc_dlatch$133 ($dlatch) source: abc9_ref.v:84.1-88.26 + D[1] --> Q[1] + wire \latch [1] source: abc9_ref.v:83.11-83.16 + cell $not$abc9_ref.v:89$30 ($not) source: abc9_ref.v:89.23-89.34 + A[1] --> Y[1] + wire \io [1] source: abc9_ref.v:82.33-82.35 +Warning: found logic loop in module abc9_test013: + cell $auto$proc_dlatch.cc:433:proc_dlatch$133 ($dlatch) source: abc9_ref.v:84.1-88.26 + D[2] --> Q[2] + wire \latch [2] source: abc9_ref.v:83.11-83.16 + cell $not$abc9_ref.v:89$30 ($not) source: abc9_ref.v:89.23-89.34 + A[2] --> Y[2] + wire \io [2] source: abc9_ref.v:82.33-82.35 +Warning: found logic loop in module abc9_test013: + cell $auto$proc_dlatch.cc:433:proc_dlatch$133 ($dlatch) source: abc9_ref.v:84.1-88.26 + D[3] --> Q[3] + wire \latch [3] source: abc9_ref.v:83.11-83.16 + cell $not$abc9_ref.v:89$30 ($not) source: abc9_ref.v:89.23-89.34 + A[3] --> Y[3] + wire \io [3] source: abc9_ref.v:82.33-82.35 +Checking module abc9_test014... +Checking module abc9_test015... +Checking module abc9_test016... +Checking module abc9_test017... +Checking module abc9_test018... +Warning: Wire abc9_test018.\d [1] is used but has no driver. +Warning: Wire abc9_test018.\d [0] is used but has no driver. +Checking module abc9_test019... +Checking module abc9_test020... +Warning: Wire abc9_test020.\c [1] is used but has no driver. +Warning: Wire abc9_test020.\c [0] is used but has no driver. +Checking module abc9_test021... +Warning: Wire abc9_test021.\s_eth_payload_axis_tready [3] is used but has no driver. +Warning: Wire abc9_test021.\s_eth_payload_axis_tready [2] is used but has no driver. +Warning: Wire abc9_test021.\s_eth_payload_axis_tready [1] is used but has no driver. +Warning: Wire abc9_test021.\s_eth_payload_axis_tready [0] is used but has no driver. +Warning: Wire abc9_test021.\s_eth_hdr_ready [3] is used but has no driver. +Warning: Wire abc9_test021.\s_eth_hdr_ready [2] is used but has no driver. +Warning: Wire abc9_test021.\s_eth_hdr_ready [1] is used but has no driver. +Warning: Wire abc9_test021.\s_eth_hdr_ready [0] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_type [15] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_type [14] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_type [13] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_type [12] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_type [11] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_type [10] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_type [9] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_type [8] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_type [7] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_type [6] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_type [5] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_type [4] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_type [3] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_type [2] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_type [1] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_type [0] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [47] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [46] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [45] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [44] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [43] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [42] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [41] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [40] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [39] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [38] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [37] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [36] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [35] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [34] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [33] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [32] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [31] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [30] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [29] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [28] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [27] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [26] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [25] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [24] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [23] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [22] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [21] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [20] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [19] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [18] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [17] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [16] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [15] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [14] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [13] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [12] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [11] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [10] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [9] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [8] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [7] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [6] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [5] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [4] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [3] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [2] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [1] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_src_mac [0] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_payload_axis_tvalid is used but has no driver. +Warning: Wire abc9_test021.\m_eth_payload_axis_tuser is used but has no driver. +Warning: Wire abc9_test021.\m_eth_payload_axis_tlast is used but has no driver. +Warning: Wire abc9_test021.\m_eth_payload_axis_tkeep is used but has no driver. +Warning: Wire abc9_test021.\m_eth_payload_axis_tid [7] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_payload_axis_tid [6] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_payload_axis_tid [5] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_payload_axis_tid [4] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_payload_axis_tid [3] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_payload_axis_tid [2] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_payload_axis_tid [1] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_payload_axis_tid [0] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_payload_axis_tdest [7] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_payload_axis_tdest [6] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_payload_axis_tdest [5] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_payload_axis_tdest [4] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_payload_axis_tdest [3] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_payload_axis_tdest [2] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_payload_axis_tdest [1] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_payload_axis_tdest [0] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_payload_axis_tdata [7] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_payload_axis_tdata [6] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_payload_axis_tdata [5] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_payload_axis_tdata [4] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_payload_axis_tdata [3] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_payload_axis_tdata [2] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_payload_axis_tdata [1] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_payload_axis_tdata [0] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_hdr_valid is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [47] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [46] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [45] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [44] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [43] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [42] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [41] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [40] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [39] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [38] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [37] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [36] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [35] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [34] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [33] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [32] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [31] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [30] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [29] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [28] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [27] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [26] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [25] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [24] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [23] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [22] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [21] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [20] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [19] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [18] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [17] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [16] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [15] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [14] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [13] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [12] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [11] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [10] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [9] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [8] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [7] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [6] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [5] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [4] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [3] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [2] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [1] is used but has no driver. +Warning: Wire abc9_test021.\m_eth_dest_mac [0] is used but has no driver. +Warning: Wire abc9_test021.\acknowledge is used but has no driver. +Checking module abc9_test022... +Checking module abc9_test023... +Checking module abc9_test024... +Warning: Wire abc9_test024.\o [3] is used but has no driver. +Warning: Wire abc9_test024.\o [2] is used but has no driver. +Checking module abc9_test024_sub... +Checking module abc9_test025... +Warning: Wire abc9_test025.\o [3] is used but has no driver. +Warning: Wire abc9_test025.\o [0] is used but has no driver. +Checking module abc9_test026... +Checking module abc9_test030... +Checking module abc9_test031... +Checking module abc9_test032... +Checking module abc9_test033... +Checking module abc9_test034... +Checking module abc9_test035... +Checking module abc9_test036... +Checking module abc9_test037... +Checking module arbiter... +Warning: Wire arbiter.\grant_valid is used but has no driver. +Warning: Wire arbiter.\grant_encoded [1] is used but has no driver. +Warning: Wire arbiter.\grant_encoded [0] is used but has no driver. +Warning: Wire arbiter.\grant [3] is used but has no driver. +Warning: Wire arbiter.\grant [2] is used but has no driver. +Warning: Wire arbiter.\grant [1] is used but has no driver. +Warning: Wire arbiter.\grant [0] is used but has no driver. +Found and reported 183 problems. + +4.5. Executing OPT pass (performing simple optimizations). + +4.5.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module abc9_test001. +Optimizing module abc9_test002. +Optimizing module abc9_test003. +Optimizing module abc9_test004. +Optimizing module abc9_test005. +Optimizing module abc9_test006. +Optimizing module abc9_test007. +Optimizing module abc9_test007_sub. +Optimizing module abc9_test008. +Optimizing module abc9_test008_sub. +Optimizing module abc9_test009. +Optimizing module abc9_test010. +Optimizing module abc9_test011. +Optimizing module abc9_test012. +Optimizing module abc9_test012_sub. +Optimizing module abc9_test013. +Optimizing module abc9_test014. +Optimizing module abc9_test015. +Optimizing module abc9_test016. +Optimizing module abc9_test017. +Optimizing module abc9_test018. +Optimizing module abc9_test019. +Optimizing module abc9_test020. +Optimizing module abc9_test021. +Optimizing module abc9_test022. +Optimizing module abc9_test023. +Optimizing module abc9_test024. +Optimizing module abc9_test024_sub. +Optimizing module abc9_test025. +Optimizing module abc9_test026. +Optimizing module abc9_test030. +Optimizing module abc9_test031. +Optimizing module abc9_test032. +Optimizing module abc9_test033. +Optimizing module abc9_test034. +Optimizing module abc9_test035. +Optimizing module abc9_test036. +Optimizing module abc9_test037. +Optimizing module arbiter. + +4.5.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\abc9_test001'. +Finding identical cells in module `\abc9_test002'. +Finding identical cells in module `\abc9_test003'. +Finding identical cells in module `\abc9_test004'. +Finding identical cells in module `\abc9_test005'. +Finding identical cells in module `\abc9_test006'. +Finding identical cells in module `\abc9_test007'. +Finding identical cells in module `\abc9_test007_sub'. +Finding identical cells in module `\abc9_test008'. +Finding identical cells in module `\abc9_test008_sub'. +Finding identical cells in module `\abc9_test009'. +Finding identical cells in module `\abc9_test010'. +Finding identical cells in module `\abc9_test011'. +Finding identical cells in module `\abc9_test012'. +Finding identical cells in module `\abc9_test012_sub'. +Finding identical cells in module `\abc9_test013'. +Finding identical cells in module `\abc9_test014'. +Finding identical cells in module `\abc9_test015'. +Finding identical cells in module `\abc9_test016'. + +Finding identical cells in module `\abc9_test017'. +Finding identical cells in module `\abc9_test018'. +Finding identical cells in module `\abc9_test019'. +Finding identical cells in module `\abc9_test020'. +Finding identical cells in module `\abc9_test021'. +Finding identical cells in module `\abc9_test022'. +Finding identical cells in module `\abc9_test023'. +Finding identical cells in module `\abc9_test024'. +Finding identical cells in module `\abc9_test024_sub'. +Finding identical cells in module `\abc9_test025'. +Finding identical cells in module `\abc9_test026'. +Finding identical cells in module `\abc9_test030'. +Finding identical cells in module `\abc9_test031'. +Finding identical cells in module `\abc9_test032'. +Finding identical cells in module `\abc9_test033'. +Finding identical cells in module `\abc9_test034'. +Finding identical cells in module `\abc9_test035'. +Finding identical cells in module `\abc9_test036'. +Finding identical cells in module `\abc9_test037'. +Finding identical cells in module `\arbiter'. +Removed a total of 1 cells. + +4.5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \abc9_test001.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test002.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test003.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test004.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test005.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test006.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test007.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test007_sub.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test008.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test008_sub.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test009.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test010.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test011.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test012.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \abc9_test012_sub.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \abc9_test013.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test014.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test015.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test016.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test017.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test018.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test019.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test020.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test021.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test022.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \abc9_test023.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test024.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test024_sub.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test025.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test026.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test030.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test031.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test032.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test033.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test034.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test035.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test036.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test037.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \arbiter.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + + +4.5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \abc9_test001. + Optimizing cells in module \abc9_test002. + Optimizing cells in module \abc9_test003. + Optimizing cells in module \abc9_test004. + Optimizing cells in module \abc9_test005. + Optimizing cells in module \abc9_test006. + Optimizing cells in module \abc9_test007. + Optimizing cells in module \abc9_test007_sub. + Optimizing cells in module \abc9_test008. + Optimizing cells in module \abc9_test008_sub. + Optimizing cells in module \abc9_test009. + Optimizing cells in module \abc9_test010. + Optimizing cells in module \abc9_test011. + Optimizing cells in module \abc9_test012. + Optimizing cells in module \abc9_test012_sub. + Optimizing cells in module \abc9_test013. + Optimizing cells in module \abc9_test014. + Optimizing cells in module \abc9_test015. + Optimizing cells in module \abc9_test016. + Optimizing cells in module \abc9_test017. + Optimizing cells in module \abc9_test018. + Optimizing cells in module \abc9_test019. + Optimizing cells in module \abc9_test020. + Optimizing cells in module \abc9_test021. + Optimizing cells in module \abc9_test022. + Optimizing cells in module \abc9_test023. + Optimizing cells in module \abc9_test024. + Optimizing cells in module \abc9_test024_sub. + Optimizing cells in module \abc9_test025. + Optimizing cells in module \abc9_test026. + Optimizing cells in module \abc9_test030. + Optimizing cells in module \abc9_test031. + Optimizing cells in module \abc9_test032. + Optimizing cells in module \abc9_test033. + Optimizing cells in module \abc9_test034. + Optimizing cells in module \abc9_test035. + Optimizing cells in module \abc9_test036. + Optimizing cells in module \abc9_test037. + Optimizing cells in module \arbiter. +Performed a total of 0 changes. + +4.5.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\abc9_test001'. +Finding identical cells in module `\abc9_test002'. +Finding identical cells in module `\abc9_test003'. +Finding identical cells in module `\abc9_test004'. +Finding identical cells in module `\abc9_test005'. +Finding identical cells in module `\abc9_test006'. +Finding identical cells in module `\abc9_test007'. +Finding identical cells in module `\abc9_test007_sub'. +Finding identical cells in module `\abc9_test008'. +Finding identical cells in module `\abc9_test008_sub'. +Finding identical cells in module `\abc9_test009'. +Finding identical cells in module `\abc9_test010'. +Finding identical cells in module `\abc9_test011'. +Finding identical cells in module `\abc9_test012'. +Finding identical cells in module `\abc9_test012_sub'. +Finding identical cells in module `\abc9_test013'. +Finding identical cells in module `\abc9_test014'. +Finding identical cells in module `\abc9_test015'. +Finding identical cells in module `\abc9_test016'. +Finding identical cells in module `\abc9_test017'. +Finding identical cells in module `\abc9_test018'. +Finding identical cells in module `\abc9_test019'. +Finding identical cells in module `\abc9_test020'. +Finding identical cells in module `\abc9_test021'. +Finding identical cells in module `\abc9_test022'. +Finding identical cells in module `\abc9_test023'. +Finding identical cells in module `\abc9_test024'. +Finding identical cells in module `\abc9_test024_sub'. +Finding identical cells in module `\abc9_test025'. +Finding identical cells in module `\abc9_test026'. +Finding identical cells in module `\abc9_test030'. +Finding identical cells in module `\abc9_test031'. +Finding identical cells in module `\abc9_test032'. +Finding identical cells in module `\abc9_test033'. +Finding identical cells in module `\abc9_test034'. +Finding identical cells in module `\abc9_test035'. +Finding identical cells in module `\abc9_test036'. +Finding identical cells in module `\abc9_test037'. +Finding identical cells in module `\arbiter'. +Removed a total of 0 cells. + +4.5.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.5.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \abc9_test001.. +Finding unused cells or wires in module \abc9_test002.. +Finding unused cells or wires in module \abc9_test003.. +Finding unused cells or wires in module \abc9_test004.. +Finding unused cells or wires in module \abc9_test005.. +Finding unused cells or wires in module \abc9_test006.. +Finding unused cells or wires in module \abc9_test007.. +Finding unused cells or wires in module \abc9_test007_sub.. +Finding unused cells or wires in module \abc9_test008.. +Finding unused cells or wires in module \abc9_test008_sub.. +Finding unused cells or wires in module \abc9_test009.. +Finding unused cells or wires in module \abc9_test010.. +Finding unused cells or wires in module \abc9_test011.. +Finding unused cells or wires in module \abc9_test012.. +Finding unused cells or wires in module \abc9_test012_sub.. +Finding unused cells or wires in module \abc9_test013.. +Finding unused cells or wires in module \abc9_test014.. +Finding unused cells or wires in module \abc9_test015.. +Finding unused cells or wires in module \abc9_test016.. +Finding unused cells or wires in module \abc9_test017.. +Finding unused cells or wires in module \abc9_test018.. +Finding unused cells or wires in module \abc9_test019.. +Finding unused cells or wires in module \abc9_test020.. +Finding unused cells or wires in module \abc9_test021.. +Finding unused cells or wires in module \abc9_test022.. +Finding unused cells or wires in module \abc9_test023.. +Finding unused cells or wires in module \abc9_test024.. +Finding unused cells or wires in module \abc9_test024_sub.. +Finding unused cells or wires in module \abc9_test025.. +Finding unused cells or wires in module \abc9_test026.. +Finding unused cells or wires in module \abc9_test030.. +Finding unused cells or wires in module \abc9_test031.. +Finding unused cells or wires in module \abc9_test032.. +Finding unused cells or wires in module \abc9_test033.. +Finding unused cells or wires in module \abc9_test034.. +Finding unused cells or wires in module \abc9_test035.. +Finding unused cells or wires in module \abc9_test036.. +Finding unused cells or wires in module \abc9_test037.. +Finding unused cells or wires in module \arbiter.. + +4.5.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module abc9_test001. +Optimizing module abc9_test002. +Optimizing module abc9_test003. +Optimizing module abc9_test004. +Optimizing module abc9_test005. +Optimizing module abc9_test006. +Optimizing module abc9_test007. +Optimizing module abc9_test007_sub. +Optimizing module abc9_test008. +Optimizing module abc9_test008_sub. +Optimizing module abc9_test009. +Optimizing module abc9_test010. +Optimizing module abc9_test011. +Optimizing module abc9_test012. +Optimizing module abc9_test012_sub. +Optimizing module abc9_test013. +Optimizing module abc9_test014. +Optimizing module abc9_test015. +Optimizing module abc9_test016. +Optimizing module abc9_test017. +Optimizing module abc9_test018. +Optimizing module abc9_test019. +Optimizing module abc9_test020. +Optimizing module abc9_test021. +Optimizing module abc9_test022. +Optimizing module abc9_test023. +Optimizing module abc9_test024. +Optimizing module abc9_test024_sub. +Optimizing module abc9_test025. +Optimizing module abc9_test026. +Optimizing module abc9_test030. +Optimizing module abc9_test031. +Optimizing module abc9_test032. +Optimizing module abc9_test033. +Optimizing module abc9_test034. +Optimizing module abc9_test035. +Optimizing module abc9_test036. +Optimizing module abc9_test037. +Optimizing module arbiter. + +4.5.9. Finished OPT passes. (There is nothing left to do.) + +4.6. Executing FSM pass (extract and optimize FSM). + +4.6.1. Executing FSM_DETECT pass (finding FSMs in design). +Not marking abc9_test022.m_eth_payload_axis_tkeep_reg as FSM state register: + Register is connected to module port. + Users of register don't seem to benefit from recoding. + Register has an initialization value. + +4.6.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +4.6.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.6.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \abc9_test001.. +Finding unused cells or wires in module \abc9_test002.. +Finding unused cells or wires in module \abc9_test003.. +Finding unused cells or wires in module \abc9_test004.. +Finding unused cells or wires in module \abc9_test005.. +Finding unused cells or wires in module \abc9_test006.. +Finding unused cells or wires in module \abc9_test007.. +Finding unused cells or wires in module \abc9_test007_sub.. +Finding unused cells or wires in module \abc9_test008.. +Finding unused cells or wires in module \abc9_test008_sub.. +Finding unused cells or wires in module \abc9_test009.. +Finding unused cells or wires in module \abc9_test010.. +Finding unused cells or wires in module \abc9_test011.. +Finding unused cells or wires in module \abc9_test012.. +Finding unused cells or wires in module \abc9_test012_sub.. +Finding unused cells or wires in module \abc9_test013.. +Finding unused cells or wires in module \abc9_test014.. +Finding unused cells or wires in module \abc9_test015.. +Finding unused cells or wires in module \abc9_test016.. +Finding unused cells or wires in module \abc9_test017.. +Finding unused cells or wires in module \abc9_test018.. +Finding unused cells or wires in module \abc9_test019.. +Finding unused cells or wires in module \abc9_test020.. +Finding unused cells or wires in module \abc9_test021.. +Finding unused cells or wires in module \abc9_test022.. +Finding unused cells or wires in module \abc9_test023.. +Finding unused cells or wires in module \abc9_test024.. +Finding unused cells or wires in module \abc9_test024_sub.. +Finding unused cells or wires in module \abc9_test025.. +Finding unused cells or wires in module \abc9_test026.. +Finding unused cells or wires in module \abc9_test030.. +Finding unused cells or wires in module \abc9_test031.. +Finding unused cells or wires in module \abc9_test032.. +Finding unused cells or wires in module \abc9_test033.. +Finding unused cells or wires in module \abc9_test034.. +Finding unused cells or wires in module \abc9_test035.. +Finding unused cells or wires in module \abc9_test036.. +Finding unused cells or wires in module \abc9_test037.. +Finding unused cells or wires in module \arbiter.. + +4.6.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.6.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +4.6.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +4.6.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +4.7. Executing OPT pass (performing simple optimizations). + +4.7.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module abc9_test001. +Optimizing module abc9_test002. +Optimizing module abc9_test003. +Optimizing module abc9_test004. +Optimizing module abc9_test005. +Optimizing module abc9_test006. +Optimizing module abc9_test007. +Optimizing module abc9_test007_sub. +Optimizing module abc9_test008. +Optimizing module abc9_test008_sub. +Optimizing module abc9_test009. +Optimizing module abc9_test010. +Optimizing module abc9_test011. +Optimizing module abc9_test012. +Optimizing module abc9_test012_sub. +Optimizing module abc9_test013. +Optimizing module abc9_test014. +Optimizing module abc9_test015. +Optimizing module abc9_test016. +Optimizing module abc9_test017. +Optimizing module abc9_test018. +Optimizing module abc9_test019. +Optimizing module abc9_test020. +Optimizing module abc9_test021. +Optimizing module abc9_test022. +Optimizing module abc9_test023. +Optimizing module abc9_test024. +Optimizing module abc9_test024_sub. +Optimizing module abc9_test025. +Optimizing module abc9_test026. +Optimizing module abc9_test030. +Optimizing module abc9_test031. +Optimizing module abc9_test032. +Optimizing module abc9_test033. +Optimizing module abc9_test034. +Optimizing module abc9_test035. +Optimizing module abc9_test036. +Optimizing module abc9_test037. +Optimizing module arbiter. + +4.7.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\abc9_test001'. +Finding identical cells in module `\abc9_test002'. +Finding identical cells in module `\abc9_test003'. +Finding identical cells in module `\abc9_test004'. +Finding identical cells in module `\abc9_test005'. +Finding identical cells in module `\abc9_test006'. +Finding identical cells in module `\abc9_test007'. +Finding identical cells in module `\abc9_test007_sub'. +Finding identical cells in module `\abc9_test008'. +Finding identical cells in module `\abc9_test008_sub'. +Finding identical cells in module `\abc9_test009'. +Finding identical cells in module `\abc9_test010'. +Finding identical cells in module `\abc9_test011'. +Finding identical cells in module `\abc9_test012'. +Finding identical cells in module `\abc9_test012_sub'. +Finding identical cells in module `\abc9_test013'. +Finding identical cells in module `\abc9_test014'. +Finding identical cells in module `\abc9_test015'. +Finding identical cells in module `\abc9_test016'. +Finding identical cells in module `\abc9_test017'. +Finding identical cells in module `\abc9_test018'. +Finding identical cells in module `\abc9_test019'. +Finding identical cells in module `\abc9_test020'. +Finding identical cells in module `\abc9_test021'. +Finding identical cells in module `\abc9_test022'. +Finding identical cells in module `\abc9_test023'. +Finding identical cells in module `\abc9_test024'. +Finding identical cells in module `\abc9_test024_sub'. +Finding identical cells in module `\abc9_test025'. +Finding identical cells in module `\abc9_test026'. +Finding identical cells in module `\abc9_test030'. +Finding identical cells in module `\abc9_test031'. +Finding identical cells in module `\abc9_test032'. +Finding identical cells in module `\abc9_test033'. +Finding identical cells in module `\abc9_test034'. +Finding identical cells in module `\abc9_test035'. +Finding identical cells in module `\abc9_test036'. +Finding identical cells in module `\abc9_test037'. +Finding identical cells in module `\arbiter'. +Removed a total of 0 cells. + +4.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \abc9_test001.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test002.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test003.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test004.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test005.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test006.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test007.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test007_sub.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test008.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test008_sub.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test009.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test010.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test011.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test012.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \abc9_test012_sub.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \abc9_test013.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test014.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test015.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test016.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test017.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test018.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test019.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test020.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test021.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test022.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \abc9_test023.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test024.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test024_sub.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test025.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test026.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test030.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test031.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test032.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test033.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test034.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test035.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test036.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test037.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \arbiter.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + + +4.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \abc9_test001. + Optimizing cells in module \abc9_test002. + Optimizing cells in module \abc9_test003. + Optimizing cells in module \abc9_test004. + Optimizing cells in module \abc9_test005. + Optimizing cells in module \abc9_test006. + Optimizing cells in module \abc9_test007. + Optimizing cells in module \abc9_test007_sub. + Optimizing cells in module \abc9_test008. + Optimizing cells in module \abc9_test008_sub. + Optimizing cells in module \abc9_test009. + Optimizing cells in module \abc9_test010. + Optimizing cells in module \abc9_test011. + Optimizing cells in module \abc9_test012. + Optimizing cells in module \abc9_test012_sub. + Optimizing cells in module \abc9_test013. + Optimizing cells in module \abc9_test014. + Optimizing cells in module \abc9_test015. + Optimizing cells in module \abc9_test016. + Optimizing cells in module \abc9_test017. + Optimizing cells in module \abc9_test018. + Optimizing cells in module \abc9_test019. + Optimizing cells in module \abc9_test020. + Optimizing cells in module \abc9_test021. + Optimizing cells in module \abc9_test022. + Optimizing cells in module \abc9_test023. + Optimizing cells in module \abc9_test024. + Optimizing cells in module \abc9_test024_sub. + Optimizing cells in module \abc9_test025. + Optimizing cells in module \abc9_test026. + Optimizing cells in module \abc9_test030. + Optimizing cells in module \abc9_test031. + Optimizing cells in module \abc9_test032. + Optimizing cells in module \abc9_test033. + Optimizing cells in module \abc9_test034. + Optimizing cells in module \abc9_test035. + Optimizing cells in module \abc9_test036. + Optimizing cells in module \abc9_test037. + Optimizing cells in module \arbiter. +Performed a total of 0 changes. + +4.7.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\abc9_test001'. +Finding identical cells in module `\abc9_test002'. +Finding identical cells in module `\abc9_test003'. +Finding identical cells in module `\abc9_test004'. +Finding identical cells in module `\abc9_test005'. +Finding identical cells in module `\abc9_test006'. +Finding identical cells in module `\abc9_test007'. +Finding identical cells in module `\abc9_test007_sub'. +Finding identical cells in module `\abc9_test008'. +Finding identical cells in module `\abc9_test008_sub'. +Finding identical cells in module `\abc9_test009'. +Finding identical cells in module `\abc9_test010'. +Finding identical cells in module `\abc9_test011'. +Finding identical cells in module `\abc9_test012'. +Finding identical cells in module `\abc9_test012_sub'. +Finding identical cells in module `\abc9_test013'. +Finding identical cells in module `\abc9_test014'. +Finding identical cells in module `\abc9_test015'. +Finding identical cells in module `\abc9_test016'. +Finding identical cells in module `\abc9_test017'. +Finding identical cells in module `\abc9_test018'. +Finding identical cells in module `\abc9_test019'. +Finding identical cells in module `\abc9_test020'. +Finding identical cells in module `\abc9_test021'. +Finding identical cells in module `\abc9_test022'. +Finding identical cells in module `\abc9_test023'. +Finding identical cells in module `\abc9_test024'. +Finding identical cells in module `\abc9_test024_sub'. +Finding identical cells in module `\abc9_test025'. +Finding identical cells in module `\abc9_test026'. +Finding identical cells in module `\abc9_test030'. +Finding identical cells in module `\abc9_test031'. +Finding identical cells in module `\abc9_test032'. +Finding identical cells in module `\abc9_test033'. +Finding identical cells in module `\abc9_test034'. +Finding identical cells in module `\abc9_test035'. +Finding identical cells in module `\abc9_test036'. +Finding identical cells in module `\abc9_test037'. +Finding identical cells in module `\arbiter'. +Removed a total of 0 cells. + +4.7.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \abc9_test001.. +Finding unused cells or wires in module \abc9_test002.. +Finding unused cells or wires in module \abc9_test003.. +Finding unused cells or wires in module \abc9_test004.. +Finding unused cells or wires in module \abc9_test005.. +Finding unused cells or wires in module \abc9_test006.. +Finding unused cells or wires in module \abc9_test007.. +Finding unused cells or wires in module \abc9_test007_sub.. +Finding unused cells or wires in module \abc9_test008.. +Finding unused cells or wires in module \abc9_test008_sub.. +Finding unused cells or wires in module \abc9_test009.. +Finding unused cells or wires in module \abc9_test010.. +Finding unused cells or wires in module \abc9_test011.. +Finding unused cells or wires in module \abc9_test012.. +Finding unused cells or wires in module \abc9_test012_sub.. +Finding unused cells or wires in module \abc9_test013.. +Finding unused cells or wires in module \abc9_test014.. +Finding unused cells or wires in module \abc9_test015.. +Finding unused cells or wires in module \abc9_test016.. +Finding unused cells or wires in module \abc9_test017.. +Finding unused cells or wires in module \abc9_test018.. +Finding unused cells or wires in module \abc9_test019.. +Finding unused cells or wires in module \abc9_test020.. +Finding unused cells or wires in module \abc9_test021.. +Finding unused cells or wires in module \abc9_test022.. +Finding unused cells or wires in module \abc9_test023.. +Finding unused cells or wires in module \abc9_test024.. +Finding unused cells or wires in module \abc9_test024_sub.. +Finding unused cells or wires in module \abc9_test025.. +Finding unused cells or wires in module \abc9_test026.. +Finding unused cells or wires in module \abc9_test030.. +Finding unused cells or wires in module \abc9_test031.. +Finding unused cells or wires in module \abc9_test032.. +Finding unused cells or wires in module \abc9_test033.. +Finding unused cells or wires in module \abc9_test034.. +Finding unused cells or wires in module \abc9_test035.. +Finding unused cells or wires in module \abc9_test036.. +Finding unused cells or wires in module \abc9_test037.. +Finding unused cells or wires in module \arbiter.. + +4.7.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module abc9_test001. +Optimizing module abc9_test002. +Optimizing module abc9_test003. +Optimizing module abc9_test004. +Optimizing module abc9_test005. +Optimizing module abc9_test006. +Optimizing module abc9_test007. +Optimizing module abc9_test007_sub. +Optimizing module abc9_test008. +Optimizing module abc9_test008_sub. +Optimizing module abc9_test009. +Optimizing module abc9_test010. +Optimizing module abc9_test011. +Optimizing module abc9_test012. +Optimizing module abc9_test012_sub. +Optimizing module abc9_test013. +Optimizing module abc9_test014. +Optimizing module abc9_test015. +Optimizing module abc9_test016. +Optimizing module abc9_test017. +Optimizing module abc9_test018. +Optimizing module abc9_test019. +Optimizing module abc9_test020. +Optimizing module abc9_test021. +Optimizing module abc9_test022. +Optimizing module abc9_test023. +Optimizing module abc9_test024. +Optimizing module abc9_test024_sub. +Optimizing module abc9_test025. +Optimizing module abc9_test026. +Optimizing module abc9_test030. +Optimizing module abc9_test031. +Optimizing module abc9_test032. +Optimizing module abc9_test033. +Optimizing module abc9_test034. +Optimizing module abc9_test035. +Optimizing module abc9_test036. +Optimizing module abc9_test037. +Optimizing module arbiter. + +4.7.9. Finished OPT passes. (There is nothing left to do.) + +4.8. Executing WREDUCE pass (reducing word size of cells). +Removed top 7 bits (of 8) from port A of cell abc9_test012.$not$abc9_ref.v:79$26 ($not). +Removed top 7 bits (of 8) from mux cell abc9_test012.$ternary$abc9_ref.v:79$27 ($mux). +Removed top 7 bits (of 8) from port Y of cell abc9_test012.$not$abc9_ref.v:79$26 ($not). +Removed top 7 bits (of 8) from wire abc9_test012.$not$abc9_ref.v:79$26_Y. +Removed top 2 bits (of 6) from mux cell abc9_test012_sub.$ternary$abc9_ref.v:105$41 ($mux). +Removed top 1 bits (of 4) from FF cell abc9_test012_sub.$auto$proc_dlatch.cc:433:proc_dlatch$122 ($dlatch). +Removed top 2 bits (of 6) from wire abc9_test012_sub.$ternary$abc9_ref.v:105$41_Y. +Removed top 1 bits (of 8) from wire abc9_test012_sub.latch. +Removed top 2 bits (of 4) from port A of cell abc9_test023.$shl$abc9_ref.v:247$62 ($shl). + +4.9. Executing PEEPOPT pass (run peephole optimizers). + +4.10. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \abc9_test001.. +Finding unused cells or wires in module \abc9_test002.. +Finding unused cells or wires in module \abc9_test003.. +Finding unused cells or wires in module \abc9_test004.. +Finding unused cells or wires in module \abc9_test005.. +Finding unused cells or wires in module \abc9_test006.. +Finding unused cells or wires in module \abc9_test007.. +Finding unused cells or wires in module \abc9_test007_sub.. +Finding unused cells or wires in module \abc9_test008.. +Finding unused cells or wires in module \abc9_test008_sub.. +Finding unused cells or wires in module \abc9_test009.. +Finding unused cells or wires in module \abc9_test010.. +Finding unused cells or wires in module \abc9_test011.. +Finding unused cells or wires in module \abc9_test012.. +Finding unused cells or wires in module \abc9_test012_sub.. +Finding unused cells or wires in module \abc9_test013.. +Finding unused cells or wires in module \abc9_test014.. +Finding unused cells or wires in module \abc9_test015.. +Finding unused cells or wires in module \abc9_test016.. +Finding unused cells or wires in module \abc9_test017.. +Finding unused cells or wires in module \abc9_test018.. +Finding unused cells or wires in module \abc9_test019.. +Finding unused cells or wires in module \abc9_test020.. +Finding unused cells or wires in module \abc9_test021.. +Finding unused cells or wires in module \abc9_test022.. +Finding unused cells or wires in module \abc9_test023.. +Finding unused cells or wires in module \abc9_test024.. +Finding unused cells or wires in module \abc9_test024_sub.. +Finding unused cells or wires in module \abc9_test025.. +Finding unused cells or wires in module \abc9_test026.. +Finding unused cells or wires in module \abc9_test030.. +Finding unused cells or wires in module \abc9_test031.. +Finding unused cells or wires in module \abc9_test032.. +Finding unused cells or wires in module \abc9_test033.. +Finding unused cells or wires in module \abc9_test034.. +Finding unused cells or wires in module \abc9_test035.. +Finding unused cells or wires in module \abc9_test036.. +Finding unused cells or wires in module \abc9_test037.. +Finding unused cells or wires in module \arbiter.. +Removed 0 unused cells and 5 unused wires. + + +4.11. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module abc9_test001: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test002: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test003: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test004: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test005: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test006: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test007: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test007_sub: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test008: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test008_sub: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test009: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test010: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test011: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test012: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test012_sub: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test013: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test014: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test015: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test016: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test017: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test018: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test019: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test020: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test021: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test022: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test023: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test024: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test024_sub: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test025: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test026: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test030: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test031: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test032: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test033: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test034: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test035: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test036: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module abc9_test037: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module arbiter: + created 0 $alu and 0 $macc cells. + +4.12. Executing SHARE pass (SAT-based resource sharing). + +4.13. Executing OPT pass (performing simple optimizations). + +4.13.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module abc9_test001. +Optimizing module abc9_test002. +Optimizing module abc9_test003. +Optimizing module abc9_test004. +Optimizing module abc9_test005. +Optimizing module abc9_test006. +Optimizing module abc9_test007. +Optimizing module abc9_test007_sub. +Optimizing module abc9_test008. +Optimizing module abc9_test008_sub. +Optimizing module abc9_test009. +Optimizing module abc9_test010. +Optimizing module abc9_test011. +Optimizing module abc9_test012. +Optimizing module abc9_test012_sub. +Optimizing module abc9_test013. +Optimizing module abc9_test014. +Optimizing module abc9_test015. +Optimizing module abc9_test016. +Optimizing module abc9_test017. +Optimizing module abc9_test018. +Optimizing module abc9_test019. +Optimizing module abc9_test020. +Optimizing module abc9_test021. +Optimizing module abc9_test022. +Optimizing module abc9_test023. +Optimizing module abc9_test024. +Optimizing module abc9_test024_sub. +Optimizing module abc9_test025. +Optimizing module abc9_test026. +Optimizing module abc9_test030. +Optimizing module abc9_test031. +Optimizing module abc9_test032. +Optimizing module abc9_test033. +Optimizing module abc9_test034. +Optimizing module abc9_test035. +Optimizing module abc9_test036. +Optimizing module abc9_test037. +Optimizing module arbiter. + +4.13.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\abc9_test001'. +Finding identical cells in module `\abc9_test002'. +Finding identical cells in module `\abc9_test003'. +Finding identical cells in module `\abc9_test004'. +Finding identical cells in module `\abc9_test005'. +Finding identical cells in module `\abc9_test006'. +Finding identical cells in module `\abc9_test007'. +Finding identical cells in module `\abc9_test007_sub'. +Finding identical cells in module `\abc9_test008'. +Finding identical cells in module `\abc9_test008_sub'. +Finding identical cells in module `\abc9_test009'. +Finding identical cells in module `\abc9_test010'. +Finding identical cells in module `\abc9_test011'. +Finding identical cells in module `\abc9_test012'. +Finding identical cells in module `\abc9_test012_sub'. +Finding identical cells in module `\abc9_test013'. +Finding identical cells in module `\abc9_test014'. +Finding identical cells in module `\abc9_test015'. +Finding identical cells in module `\abc9_test016'. +Finding identical cells in module `\abc9_test017'. +Finding identical cells in module `\abc9_test018'. +Finding identical cells in module `\abc9_test019'. +Finding identical cells in module `\abc9_test020'. +Finding identical cells in module `\abc9_test021'. +Finding identical cells in module `\abc9_test022'. +Finding identical cells in module `\abc9_test023'. +Finding identical cells in module `\abc9_test024'. +Finding identical cells in module `\abc9_test024_sub'. +Finding identical cells in module `\abc9_test025'. +Finding identical cells in module `\abc9_test026'. +Finding identical cells in module `\abc9_test030'. +Finding identical cells in module `\abc9_test031'. +Finding identical cells in module `\abc9_test032'. +Finding identical cells in module `\abc9_test033'. +Finding identical cells in module `\abc9_test034'. +Finding identical cells in module `\abc9_test035'. +Finding identical cells in module `\abc9_test036'. +Finding identical cells in module `\abc9_test037'. +Finding identical cells in module `\arbiter'. +Removed a total of 0 cells. + +4.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \abc9_test001.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test002.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test003.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test004.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test005.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test006.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test007.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test007_sub.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test008.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test008_sub.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test009.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test010.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test011.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test012.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \abc9_test012_sub.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \abc9_test013.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test014.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test015.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test016.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test017.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test018.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test019.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test020.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test021.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test022.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \abc9_test023.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test024.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test024_sub.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test025.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test026.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test030.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test031.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test032.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test033.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test034.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test035.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test036.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test037.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \arbiter.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + + +4.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \abc9_test001. + Optimizing cells in module \abc9_test002. + Optimizing cells in module \abc9_test003. + Optimizing cells in module \abc9_test004. + Optimizing cells in module \abc9_test005. + Optimizing cells in module \abc9_test006. + Optimizing cells in module \abc9_test007. + Optimizing cells in module \abc9_test007_sub. + Optimizing cells in module \abc9_test008. + Optimizing cells in module \abc9_test008_sub. + Optimizing cells in module \abc9_test009. + Optimizing cells in module \abc9_test010. + Optimizing cells in module \abc9_test011. + Optimizing cells in module \abc9_test012. + Optimizing cells in module \abc9_test012_sub. + Optimizing cells in module \abc9_test013. + Optimizing cells in module \abc9_test014. + Optimizing cells in module \abc9_test015. + Optimizing cells in module \abc9_test016. + Optimizing cells in module \abc9_test017. + Optimizing cells in module \abc9_test018. + Optimizing cells in module \abc9_test019. + Optimizing cells in module \abc9_test020. + Optimizing cells in module \abc9_test021. + Optimizing cells in module \abc9_test022. + Optimizing cells in module \abc9_test023. + Optimizing cells in module \abc9_test024. + Optimizing cells in module \abc9_test024_sub. + Optimizing cells in module \abc9_test025. + Optimizing cells in module \abc9_test026. + Optimizing cells in module \abc9_test030. + Optimizing cells in module \abc9_test031. + Optimizing cells in module \abc9_test032. + Optimizing cells in module \abc9_test033. + Optimizing cells in module \abc9_test034. + Optimizing cells in module \abc9_test035. + Optimizing cells in module \abc9_test036. + Optimizing cells in module \abc9_test037. + Optimizing cells in module \arbiter. +Performed a total of 0 changes. + +4.13.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\abc9_test001'. +Finding identical cells in module `\abc9_test002'. +Finding identical cells in module `\abc9_test003'. +Finding identical cells in module `\abc9_test004'. +Finding identical cells in module `\abc9_test005'. +Finding identical cells in module `\abc9_test006'. +Finding identical cells in module `\abc9_test007'. +Finding identical cells in module `\abc9_test007_sub'. +Finding identical cells in module `\abc9_test008'. +Finding identical cells in module `\abc9_test008_sub'. +Finding identical cells in module `\abc9_test009'. +Finding identical cells in module `\abc9_test010'. +Finding identical cells in module `\abc9_test011'. +Finding identical cells in module `\abc9_test012'. +Finding identical cells in module `\abc9_test012_sub'. +Finding identical cells in module `\abc9_test013'. +Finding identical cells in module `\abc9_test014'. +Finding identical cells in module `\abc9_test015'. +Finding identical cells in module `\abc9_test016'. +Finding identical cells in module `\abc9_test017'. +Finding identical cells in module `\abc9_test018'. +Finding identical cells in module `\abc9_test019'. +Finding identical cells in module `\abc9_test020'. +Finding identical cells in module `\abc9_test021'. +Finding identical cells in module `\abc9_test022'. +Finding identical cells in module `\abc9_test023'. +Finding identical cells in module `\abc9_test024'. +Finding identical cells in module `\abc9_test024_sub'. +Finding identical cells in module `\abc9_test025'. +Finding identical cells in module `\abc9_test026'. +Finding identical cells in module `\abc9_test030'. +Finding identical cells in module `\abc9_test031'. +Finding identical cells in module `\abc9_test032'. +Finding identical cells in module `\abc9_test033'. +Finding identical cells in module `\abc9_test034'. +Finding identical cells in module `\abc9_test035'. +Finding identical cells in module `\abc9_test036'. +Finding identical cells in module `\abc9_test037'. +Finding identical cells in module `\arbiter'. +Removed a total of 0 cells. + +4.13.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \abc9_test001.. +Finding unused cells or wires in module \abc9_test002.. +Finding unused cells or wires in module \abc9_test003.. +Finding unused cells or wires in module \abc9_test004.. +Finding unused cells or wires in module \abc9_test005.. +Finding unused cells or wires in module \abc9_test006.. +Finding unused cells or wires in module \abc9_test007.. +Finding unused cells or wires in module \abc9_test007_sub.. +Finding unused cells or wires in module \abc9_test008.. +Finding unused cells or wires in module \abc9_test008_sub.. +Finding unused cells or wires in module \abc9_test009.. +Finding unused cells or wires in module \abc9_test010.. +Finding unused cells or wires in module \abc9_test011.. +Finding unused cells or wires in module \abc9_test012.. +Finding unused cells or wires in module \abc9_test012_sub.. +Finding unused cells or wires in module \abc9_test013.. +Finding unused cells or wires in module \abc9_test014.. +Finding unused cells or wires in module \abc9_test015.. +Finding unused cells or wires in module \abc9_test016.. +Finding unused cells or wires in module \abc9_test017.. +Finding unused cells or wires in module \abc9_test018.. +Finding unused cells or wires in module \abc9_test019.. +Finding unused cells or wires in module \abc9_test020.. +Finding unused cells or wires in module \abc9_test021.. +Finding unused cells or wires in module \abc9_test022.. +Finding unused cells or wires in module \abc9_test023.. +Finding unused cells or wires in module \abc9_test024.. +Finding unused cells or wires in module \abc9_test024_sub.. +Finding unused cells or wires in module \abc9_test025.. +Finding unused cells or wires in module \abc9_test026.. +Finding unused cells or wires in module \abc9_test030.. +Finding unused cells or wires in module \abc9_test031.. +Finding unused cells or wires in module \abc9_test032.. +Finding unused cells or wires in module \abc9_test033.. +Finding unused cells or wires in module \abc9_test034.. +Finding unused cells or wires in module \abc9_test035.. +Finding unused cells or wires in module \abc9_test036.. +Finding unused cells or wires in module \abc9_test037.. +Finding unused cells or wires in module \arbiter.. + +4.13.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module abc9_test001. +Optimizing module abc9_test002. +Optimizing module abc9_test003. +Optimizing module abc9_test004. +Optimizing module abc9_test005. +Optimizing module abc9_test006. +Optimizing module abc9_test007. +Optimizing module abc9_test007_sub. +Optimizing module abc9_test008. +Optimizing module abc9_test008_sub. +Optimizing module abc9_test009. +Optimizing module abc9_test010. +Optimizing module abc9_test011. +Optimizing module abc9_test012. +Optimizing module abc9_test012_sub. +Optimizing module abc9_test013. +Optimizing module abc9_test014. +Optimizing module abc9_test015. +Optimizing module abc9_test016. +Optimizing module abc9_test017. +Optimizing module abc9_test018. +Optimizing module abc9_test019. +Optimizing module abc9_test020. +Optimizing module abc9_test021. +Optimizing module abc9_test022. +Optimizing module abc9_test023. +Optimizing module abc9_test024. +Optimizing module abc9_test024_sub. +Optimizing module abc9_test025. +Optimizing module abc9_test026. +Optimizing module abc9_test030. +Optimizing module abc9_test031. +Optimizing module abc9_test032. +Optimizing module abc9_test033. +Optimizing module abc9_test034. +Optimizing module abc9_test035. +Optimizing module abc9_test036. +Optimizing module abc9_test037. +Optimizing module arbiter. + +4.13.9. Finished OPT passes. (There is nothing left to do.) + +4.14. Executing MEMORY pass. + +4.14.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +4.14.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +4.14.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + +4.14.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +4.14.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). + +4.14.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \abc9_test001.. +Finding unused cells or wires in module \abc9_test002.. +Finding unused cells or wires in module \abc9_test003.. +Finding unused cells or wires in module \abc9_test004.. +Finding unused cells or wires in module \abc9_test005.. +Finding unused cells or wires in module \abc9_test006.. +Finding unused cells or wires in module \abc9_test007.. +Finding unused cells or wires in module \abc9_test007_sub.. +Finding unused cells or wires in module \abc9_test008.. +Finding unused cells or wires in module \abc9_test008_sub.. +Finding unused cells or wires in module \abc9_test009.. +Finding unused cells or wires in module \abc9_test010.. +Finding unused cells or wires in module \abc9_test011.. +Finding unused cells or wires in module \abc9_test012.. +Finding unused cells or wires in module \abc9_test012_sub.. +Finding unused cells or wires in module \abc9_test013.. +Finding unused cells or wires in module \abc9_test014.. +Finding unused cells or wires in module \abc9_test015.. +Finding unused cells or wires in module \abc9_test016.. +Finding unused cells or wires in module \abc9_test017.. +Finding unused cells or wires in module \abc9_test018.. +Finding unused cells or wires in module \abc9_test019.. +Finding unused cells or wires in module \abc9_test020.. +Finding unused cells or wires in module \abc9_test021.. +Finding unused cells or wires in module \abc9_test022.. +Finding unused cells or wires in module \abc9_test023.. +Finding unused cells or wires in module \abc9_test024.. +Finding unused cells or wires in module \abc9_test024_sub.. +Finding unused cells or wires in module \abc9_test025.. +Finding unused cells or wires in module \abc9_test026.. +Finding unused cells or wires in module \abc9_test030.. +Finding unused cells or wires in module \abc9_test031.. +Finding unused cells or wires in module \abc9_test032.. +Finding unused cells or wires in module \abc9_test033.. +Finding unused cells or wires in module \abc9_test034.. +Finding unused cells or wires in module \abc9_test035.. +Finding unused cells or wires in module \abc9_test036.. +Finding unused cells or wires in module \abc9_test037.. +Finding unused cells or wires in module \arbiter.. + +4.14.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +4.14.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +4.14.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \abc9_test001.. +Finding unused cells or wires in module \abc9_test002.. +Finding unused cells or wires in module \abc9_test003.. +Finding unused cells or wires in module \abc9_test004.. +Finding unused cells or wires in module \abc9_test005.. +Finding unused cells or wires in module \abc9_test006.. +Finding unused cells or wires in module \abc9_test007.. +Finding unused cells or wires in module \abc9_test007_sub.. +Finding unused cells or wires in module \abc9_test008.. +Finding unused cells or wires in module \abc9_test008_sub.. +Finding unused cells or wires in module \abc9_test009.. +Finding unused cells or wires in module \abc9_test010.. +Finding unused cells or wires in module \abc9_test011.. +Finding unused cells or wires in module \abc9_test012.. +Finding unused cells or wires in module \abc9_test012_sub.. +Finding unused cells or wires in module \abc9_test013.. +Finding unused cells or wires in module \abc9_test014.. +Finding unused cells or wires in module \abc9_test015.. +Finding unused cells or wires in module \abc9_test016.. +Finding unused cells or wires in module \abc9_test017.. +Finding unused cells or wires in module \abc9_test018.. +Finding unused cells or wires in module \abc9_test019.. +Finding unused cells or wires in module \abc9_test020.. +Finding unused cells or wires in module \abc9_test021.. +Finding unused cells or wires in module \abc9_test022.. +Finding unused cells or wires in module \abc9_test023.. +Finding unused cells or wires in module \abc9_test024.. +Finding unused cells or wires in module \abc9_test024_sub.. +Finding unused cells or wires in module \abc9_test025.. +Finding unused cells or wires in module \abc9_test026.. +Finding unused cells or wires in module \abc9_test030.. +Finding unused cells or wires in module \abc9_test031.. +Finding unused cells or wires in module \abc9_test032.. +Finding unused cells or wires in module \abc9_test033.. +Finding unused cells or wires in module \abc9_test034.. +Finding unused cells or wires in module \abc9_test035.. +Finding unused cells or wires in module \abc9_test036.. +Finding unused cells or wires in module \abc9_test037.. +Finding unused cells or wires in module \arbiter.. + +4.14.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +4.15. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \abc9_test001.. +Finding unused cells or wires in module \abc9_test002.. +Finding unused cells or wires in module \abc9_test003.. +Finding unused cells or wires in module \abc9_test004.. +Finding unused cells or wires in module \abc9_test005.. +Finding unused cells or wires in module \abc9_test006.. +Finding unused cells or wires in module \abc9_test007.. +Finding unused cells or wires in module \abc9_test007_sub.. +Finding unused cells or wires in module \abc9_test008.. +Finding unused cells or wires in module \abc9_test008_sub.. +Finding unused cells or wires in module \abc9_test009.. +Finding unused cells or wires in module \abc9_test010.. +Finding unused cells or wires in module \abc9_test011.. +Finding unused cells or wires in module \abc9_test012.. +Finding unused cells or wires in module \abc9_test012_sub.. +Finding unused cells or wires in module \abc9_test013.. +Finding unused cells or wires in module \abc9_test014.. +Finding unused cells or wires in module \abc9_test015.. +Finding unused cells or wires in module \abc9_test016.. +Finding unused cells or wires in module \abc9_test017.. +Finding unused cells or wires in module \abc9_test018.. +Finding unused cells or wires in module \abc9_test019.. +Finding unused cells or wires in module \abc9_test020.. +Finding unused cells or wires in module \abc9_test021.. +Finding unused cells or wires in module \abc9_test022.. +Finding unused cells or wires in module \abc9_test023.. +Finding unused cells or wires in module \abc9_test024.. +Finding unused cells or wires in module \abc9_test024_sub.. +Finding unused cells or wires in module \abc9_test025.. +Finding unused cells or wires in module \abc9_test026.. +Finding unused cells or wires in module \abc9_test030.. +Finding unused cells or wires in module \abc9_test031.. +Finding unused cells or wires in module \abc9_test032.. +Finding unused cells or wires in module \abc9_test033.. +Finding unused cells or wires in module \abc9_test034.. +Finding unused cells or wires in module \abc9_test035.. +Finding unused cells or wires in module \abc9_test036.. +Finding unused cells or wires in module \abc9_test037.. +Finding unused cells or wires in module \arbiter.. + +5. Executing OPT pass (performing simple optimizations). + +5.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module abc9_test001. +Optimizing module abc9_test002. +Optimizing module abc9_test003. +Optimizing module abc9_test004. +Optimizing module abc9_test005. +Optimizing module abc9_test006. +Optimizing module abc9_test007. +Optimizing module abc9_test007_sub. +Optimizing module abc9_test008. +Optimizing module abc9_test008_sub. +Optimizing module abc9_test009. +Optimizing module abc9_test010. +Optimizing module abc9_test011. +Optimizing module abc9_test012. + +Optimizing module abc9_test012_sub. + +Optimizing module abc9_test013. +Optimizing module abc9_test014. +Optimizing module abc9_test015. +Optimizing module abc9_test016. +Optimizing module abc9_test017. +Optimizing module abc9_test018. + +Optimizing module abc9_test019. + +Optimizing module abc9_test020. + +Optimizing module abc9_test021. + +Optimizing module abc9_test022. +Optimizing module abc9_test023. +Optimizing module abc9_test024. + +Optimizing module abc9_test024_sub. +Optimizing module abc9_test025. + +Optimizing module abc9_test026. +Optimizing module abc9_test030. +Optimizing module abc9_test031. +Optimizing module abc9_test032. +Optimizing module abc9_test033. +Optimizing module abc9_test034. +Optimizing module abc9_test035. +Optimizing module abc9_test036. +Optimizing module abc9_test037. +Optimizing module arbiter. + + +5.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\abc9_test001'. +Finding identical cells in module `\abc9_test002'. +Finding identical cells in module `\abc9_test003'. +Finding identical cells in module `\abc9_test004'. +Finding identical cells in module `\abc9_test005'. +Finding identical cells in module `\abc9_test006'. +Finding identical cells in module `\abc9_test007'. +Finding identical cells in module `\abc9_test007_sub'. +Finding identical cells in module `\abc9_test008'. +Finding identical cells in module `\abc9_test008_sub'. +Finding identical cells in module `\abc9_test009'. +Finding identical cells in module `\abc9_test010'. +Finding identical cells in module `\abc9_test011'. +Finding identical cells in module `\abc9_test012'. +Finding identical cells in module `\abc9_test012_sub'. +Finding identical cells in module `\abc9_test013'. +Finding identical cells in module `\abc9_test014'. +Finding identical cells in module `\abc9_test015'. +Finding identical cells in module `\abc9_test016'. +Finding identical cells in module `\abc9_test017'. +Finding identical cells in module `\abc9_test018'. +Finding identical cells in module `\abc9_test019'. +Finding identical cells in module `\abc9_test020'. +Finding identical cells in module `\abc9_test021'. +Finding identical cells in module `\abc9_test022'. +Finding identical cells in module `\abc9_test023'. +Finding identical cells in module `\abc9_test024'. +Finding identical cells in module `\abc9_test024_sub'. +Finding identical cells in module `\abc9_test025'. +Finding identical cells in module `\abc9_test026'. +Finding identical cells in module `\abc9_test030'. +Finding identical cells in module `\abc9_test031'. +Finding identical cells in module `\abc9_test032'. +Finding identical cells in module `\abc9_test033'. +Finding identical cells in module `\abc9_test034'. +Finding identical cells in module `\abc9_test035'. +Finding identical cells in module `\abc9_test036'. +Finding identical cells in module `\abc9_test037'. +Finding identical cells in module `\arbiter'. +Removed a total of 0 cells. + +5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \abc9_test001.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test002.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test003.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test004.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test005.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test006.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test007.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test007_sub.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test008.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test008_sub.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test009.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test010.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test011.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test012.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test012_sub.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test013.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test014.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test015.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test016.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test017.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test018.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test019.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test020.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test021.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test022.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \abc9_test023.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test024.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test024_sub.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test025.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test026.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test030.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test031.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test032.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test033.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test034.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test035.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test036.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test037.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \arbiter.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + + +5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \abc9_test001. + Optimizing cells in module \abc9_test002. + Optimizing cells in module \abc9_test003. + Optimizing cells in module \abc9_test004. + Optimizing cells in module \abc9_test005. + Optimizing cells in module \abc9_test006. + Optimizing cells in module \abc9_test007. + Optimizing cells in module \abc9_test007_sub. + Optimizing cells in module \abc9_test008. + Optimizing cells in module \abc9_test008_sub. + Optimizing cells in module \abc9_test009. + Optimizing cells in module \abc9_test010. + Optimizing cells in module \abc9_test011. + Optimizing cells in module \abc9_test012. + Optimizing cells in module \abc9_test012_sub. + Optimizing cells in module \abc9_test013. + Optimizing cells in module \abc9_test014. + Optimizing cells in module \abc9_test015. + Optimizing cells in module \abc9_test016. + Optimizing cells in module \abc9_test017. + Optimizing cells in module \abc9_test018. + Optimizing cells in module \abc9_test019. + Optimizing cells in module \abc9_test020. + Optimizing cells in module \abc9_test021. + Optimizing cells in module \abc9_test022. + Consolidated identical input bits for $mux cell $ternary$abc9_ref.v:235$60: + Old ports: A=8'00001111, B=8'11111111, Y=$0\m_eth_payload_axis_tkeep_reg[7:0] + New ports: A=1'0, B=1'1, Y=$0\m_eth_payload_axis_tkeep_reg[7:0] [4] + New connections: { $0\m_eth_payload_axis_tkeep_reg[7:0] [7:5] $0\m_eth_payload_axis_tkeep_reg[7:0] [3:0] } = { $0\m_eth_payload_axis_tkeep_reg[7:0] [4] $0\m_eth_payload_axis_tkeep_reg[7:0] [4] $0\m_eth_payload_axis_tkeep_reg[7:0] [4] 4'1111 } + Optimizing cells in module \abc9_test022. + Optimizing cells in module \abc9_test023. + Optimizing cells in module \abc9_test024. + Optimizing cells in module \abc9_test024_sub. + Optimizing cells in module \abc9_test025. + Optimizing cells in module \abc9_test026. + Optimizing cells in module \abc9_test030. + Optimizing cells in module \abc9_test031. + Optimizing cells in module \abc9_test032. + Optimizing cells in module \abc9_test033. + Optimizing cells in module \abc9_test034. + Optimizing cells in module \abc9_test035. + Optimizing cells in module \abc9_test036. + Optimizing cells in module \abc9_test037. + Optimizing cells in module \arbiter. +Performed a total of 1 changes. + +5.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\abc9_test001'. +Finding identical cells in module `\abc9_test002'. +Finding identical cells in module `\abc9_test003'. +Finding identical cells in module `\abc9_test004'. +Finding identical cells in module `\abc9_test005'. +Finding identical cells in module `\abc9_test006'. +Finding identical cells in module `\abc9_test007'. +Finding identical cells in module `\abc9_test007_sub'. +Finding identical cells in module `\abc9_test008'. +Finding identical cells in module `\abc9_test008_sub'. +Finding identical cells in module `\abc9_test009'. +Finding identical cells in module `\abc9_test010'. +Finding identical cells in module `\abc9_test011'. +Finding identical cells in module `\abc9_test012'. +Finding identical cells in module `\abc9_test012_sub'. +Finding identical cells in module `\abc9_test013'. +Finding identical cells in module `\abc9_test014'. +Finding identical cells in module `\abc9_test015'. +Finding identical cells in module `\abc9_test016'. +Finding identical cells in module `\abc9_test017'. +Finding identical cells in module `\abc9_test018'. +Finding identical cells in module `\abc9_test019'. +Finding identical cells in module `\abc9_test020'. +Finding identical cells in module `\abc9_test021'. +Finding identical cells in module `\abc9_test022'. +Finding identical cells in module `\abc9_test023'. +Finding identical cells in module `\abc9_test024'. +Finding identical cells in module `\abc9_test024_sub'. +Finding identical cells in module `\abc9_test025'. +Finding identical cells in module `\abc9_test026'. +Finding identical cells in module `\abc9_test030'. +Finding identical cells in module `\abc9_test031'. +Finding identical cells in module `\abc9_test032'. +Finding identical cells in module `\abc9_test033'. +Finding identical cells in module `\abc9_test034'. +Finding identical cells in module `\abc9_test035'. +Finding identical cells in module `\abc9_test036'. +Finding identical cells in module `\abc9_test037'. +Finding identical cells in module `\arbiter'. +Removed a total of 0 cells. + +5.6. Executing OPT_SHARE pass. + +5.7. Executing OPT_DFF pass (perform DFF optimizations). + +5.8. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \abc9_test001.. +Finding unused cells or wires in module \abc9_test002.. +Finding unused cells or wires in module \abc9_test003.. +Finding unused cells or wires in module \abc9_test004.. +Finding unused cells or wires in module \abc9_test005.. +Finding unused cells or wires in module \abc9_test006.. +Finding unused cells or wires in module \abc9_test007.. +Finding unused cells or wires in module \abc9_test007_sub.. +Finding unused cells or wires in module \abc9_test008.. +Finding unused cells or wires in module \abc9_test008_sub.. +Finding unused cells or wires in module \abc9_test009.. +Finding unused cells or wires in module \abc9_test010.. +Finding unused cells or wires in module \abc9_test011.. +Finding unused cells or wires in module \abc9_test012.. +Finding unused cells or wires in module \abc9_test012_sub.. +Finding unused cells or wires in module \abc9_test013.. +Finding unused cells or wires in module \abc9_test014.. +Finding unused cells or wires in module \abc9_test015.. +Finding unused cells or wires in module \abc9_test016.. +Finding unused cells or wires in module \abc9_test017.. +Finding unused cells or wires in module \abc9_test018.. +Finding unused cells or wires in module \abc9_test019.. +Finding unused cells or wires in module \abc9_test020.. +Finding unused cells or wires in module \abc9_test021.. +Finding unused cells or wires in module \abc9_test022.. +Finding unused cells or wires in module \abc9_test023.. +Finding unused cells or wires in module \abc9_test024.. +Finding unused cells or wires in module \abc9_test024_sub.. +Finding unused cells or wires in module \abc9_test025.. +Finding unused cells or wires in module \abc9_test026.. +Finding unused cells or wires in module \abc9_test030.. +Finding unused cells or wires in module \abc9_test031.. +Finding unused cells or wires in module \abc9_test032.. +Finding unused cells or wires in module \abc9_test033.. +Finding unused cells or wires in module \abc9_test034.. +Finding unused cells or wires in module \abc9_test035.. +Finding unused cells or wires in module \abc9_test036.. +Finding unused cells or wires in module \abc9_test037.. +Finding unused cells or wires in module \arbiter.. +Removed 0 unused cells and 1 unused wires. + + +5.9. Executing OPT_EXPR pass (perform const folding). +Optimizing module abc9_test001. +Optimizing module abc9_test002. +Optimizing module abc9_test003. +Optimizing module abc9_test004. +Optimizing module abc9_test005. +Optimizing module abc9_test006. +Optimizing module abc9_test007. +Optimizing module abc9_test007_sub. +Optimizing module abc9_test008. +Optimizing module abc9_test008_sub. +Optimizing module abc9_test009. +Optimizing module abc9_test010. +Optimizing module abc9_test011. +Optimizing module abc9_test012. +Optimizing module abc9_test012_sub. +Optimizing module abc9_test013. +Optimizing module abc9_test014. +Optimizing module abc9_test015. +Optimizing module abc9_test016. +Optimizing module abc9_test017. +Optimizing module abc9_test018. +Optimizing module abc9_test019. +Optimizing module abc9_test020. +Optimizing module abc9_test021. +Optimizing module abc9_test022. + +Optimizing module abc9_test023. +Optimizing module abc9_test024. +Optimizing module abc9_test024_sub. +Optimizing module abc9_test025. +Optimizing module abc9_test026. +Optimizing module abc9_test030. +Optimizing module abc9_test031. +Optimizing module abc9_test032. +Optimizing module abc9_test033. +Optimizing module abc9_test034. +Optimizing module abc9_test035. +Optimizing module abc9_test036. +Optimizing module abc9_test037. +Optimizing module arbiter. + +5.10. Rerunning OPT passes. (Maybe there is more to do..) + +5.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \abc9_test001.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test002.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test003.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test004.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test005.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test006.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test007.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test007_sub.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test008.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test008_sub.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test009.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test010.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test011.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test012.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test012_sub.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test013.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test014.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test015.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test016.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test017.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test018.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test019.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test020.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test021.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test022.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test023.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test024.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test024_sub.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test025.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test026.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test030.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test031.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test032.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test033.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test034.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test035.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test036.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test037.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \arbiter.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +5.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \abc9_test001. + Optimizing cells in module \abc9_test002. + Optimizing cells in module \abc9_test003. + Optimizing cells in module \abc9_test004. + Optimizing cells in module \abc9_test005. + Optimizing cells in module \abc9_test006. + Optimizing cells in module \abc9_test007. + Optimizing cells in module \abc9_test007_sub. + Optimizing cells in module \abc9_test008. + Optimizing cells in module \abc9_test008_sub. + Optimizing cells in module \abc9_test009. + Optimizing cells in module \abc9_test010. + Optimizing cells in module \abc9_test011. + Optimizing cells in module \abc9_test012. + Optimizing cells in module \abc9_test012_sub. + Optimizing cells in module \abc9_test013. + Optimizing cells in module \abc9_test014. + Optimizing cells in module \abc9_test015. + Optimizing cells in module \abc9_test016. + Optimizing cells in module \abc9_test017. + Optimizing cells in module \abc9_test018. + Optimizing cells in module \abc9_test019. + Optimizing cells in module \abc9_test020. + Optimizing cells in module \abc9_test021. + Optimizing cells in module \abc9_test022. + Optimizing cells in module \abc9_test023. + Optimizing cells in module \abc9_test024. + Optimizing cells in module \abc9_test024_sub. + Optimizing cells in module \abc9_test025. + Optimizing cells in module \abc9_test026. + Optimizing cells in module \abc9_test030. + Optimizing cells in module \abc9_test031. + Optimizing cells in module \abc9_test032. + Optimizing cells in module \abc9_test033. + Optimizing cells in module \abc9_test034. + Optimizing cells in module \abc9_test035. + Optimizing cells in module \abc9_test036. + Optimizing cells in module \abc9_test037. + Optimizing cells in module \arbiter. +Performed a total of 0 changes. + +5.13. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\abc9_test001'. +Finding identical cells in module `\abc9_test002'. +Finding identical cells in module `\abc9_test003'. +Finding identical cells in module `\abc9_test004'. +Finding identical cells in module `\abc9_test005'. +Finding identical cells in module `\abc9_test006'. +Finding identical cells in module `\abc9_test007'. +Finding identical cells in module `\abc9_test007_sub'. +Finding identical cells in module `\abc9_test008'. +Finding identical cells in module `\abc9_test008_sub'. +Finding identical cells in module `\abc9_test009'. +Finding identical cells in module `\abc9_test010'. +Finding identical cells in module `\abc9_test011'. +Finding identical cells in module `\abc9_test012'. +Finding identical cells in module `\abc9_test012_sub'. +Finding identical cells in module `\abc9_test013'. +Finding identical cells in module `\abc9_test014'. +Finding identical cells in module `\abc9_test015'. +Finding identical cells in module `\abc9_test016'. +Finding identical cells in module `\abc9_test017'. +Finding identical cells in module `\abc9_test018'. +Finding identical cells in module `\abc9_test019'. +Finding identical cells in module `\abc9_test020'. +Finding identical cells in module `\abc9_test021'. +Finding identical cells in module `\abc9_test022'. +Finding identical cells in module `\abc9_test023'. +Finding identical cells in module `\abc9_test024'. +Finding identical cells in module `\abc9_test024_sub'. +Finding identical cells in module `\abc9_test025'. +Finding identical cells in module `\abc9_test026'. +Finding identical cells in module `\abc9_test030'. +Finding identical cells in module `\abc9_test031'. +Finding identical cells in module `\abc9_test032'. +Finding identical cells in module `\abc9_test033'. +Finding identical cells in module `\abc9_test034'. +Finding identical cells in module `\abc9_test035'. +Finding identical cells in module `\abc9_test036'. +Finding identical cells in module `\abc9_test037'. +Finding identical cells in module `\arbiter'. +Removed a total of 0 cells. + +5.14. Executing OPT_SHARE pass. + +5.15. Executing OPT_DFF pass (perform DFF optimizations). + +5.16. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \abc9_test001.. +Finding unused cells or wires in module \abc9_test002.. +Finding unused cells or wires in module \abc9_test003.. +Finding unused cells or wires in module \abc9_test004.. +Finding unused cells or wires in module \abc9_test005.. +Finding unused cells or wires in module \abc9_test006.. +Finding unused cells or wires in module \abc9_test007.. +Finding unused cells or wires in module \abc9_test007_sub.. +Finding unused cells or wires in module \abc9_test008.. +Finding unused cells or wires in module \abc9_test008_sub.. +Finding unused cells or wires in module \abc9_test009.. +Finding unused cells or wires in module \abc9_test010.. +Finding unused cells or wires in module \abc9_test011.. +Finding unused cells or wires in module \abc9_test012.. +Finding unused cells or wires in module \abc9_test012_sub.. +Finding unused cells or wires in module \abc9_test013.. +Finding unused cells or wires in module \abc9_test014.. +Finding unused cells or wires in module \abc9_test015.. +Finding unused cells or wires in module \abc9_test016.. +Finding unused cells or wires in module \abc9_test017.. +Finding unused cells or wires in module \abc9_test018.. +Finding unused cells or wires in module \abc9_test019.. +Finding unused cells or wires in module \abc9_test020.. +Finding unused cells or wires in module \abc9_test021.. +Finding unused cells or wires in module \abc9_test022.. +Finding unused cells or wires in module \abc9_test023.. +Finding unused cells or wires in module \abc9_test024.. +Finding unused cells or wires in module \abc9_test024_sub.. +Finding unused cells or wires in module \abc9_test025.. +Finding unused cells or wires in module \abc9_test026.. +Finding unused cells or wires in module \abc9_test030.. +Finding unused cells or wires in module \abc9_test031.. +Finding unused cells or wires in module \abc9_test032.. +Finding unused cells or wires in module \abc9_test033.. +Finding unused cells or wires in module \abc9_test034.. +Finding unused cells or wires in module \abc9_test035.. +Finding unused cells or wires in module \abc9_test036.. +Finding unused cells or wires in module \abc9_test037.. +Finding unused cells or wires in module \arbiter.. +Removed 0 unused cells and 1 unused wires. + + +5.17. Executing OPT_EXPR pass (perform const folding). +Optimizing module abc9_test001. +Optimizing module abc9_test002. +Optimizing module abc9_test003. +Optimizing module abc9_test004. +Optimizing module abc9_test005. +Optimizing module abc9_test006. +Optimizing module abc9_test007. +Optimizing module abc9_test007_sub. +Optimizing module abc9_test008. +Optimizing module abc9_test008_sub. +Optimizing module abc9_test009. +Optimizing module abc9_test010. +Optimizing module abc9_test011. +Optimizing module abc9_test012. +Optimizing module abc9_test012_sub. +Optimizing module abc9_test013. +Optimizing module abc9_test014. +Optimizing module abc9_test015. +Optimizing module abc9_test016. +Optimizing module abc9_test017. +Optimizing module abc9_test018. +Optimizing module abc9_test019. +Optimizing module abc9_test020. +Optimizing module abc9_test021. +Optimizing module abc9_test022. +Optimizing module abc9_test023. +Optimizing module abc9_test024. +Optimizing module abc9_test024_sub. +Optimizing module abc9_test025. +Optimizing module abc9_test026. +Optimizing module abc9_test030. +Optimizing module abc9_test031. +Optimizing module abc9_test032. +Optimizing module abc9_test033. +Optimizing module abc9_test034. +Optimizing module abc9_test035. +Optimizing module abc9_test036. +Optimizing module abc9_test037. +Optimizing module arbiter. + +5.18. Rerunning OPT passes. (Maybe there is more to do..) + +5.19. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \abc9_test001.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test002.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test003.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test004.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test005.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test006.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test007.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test007_sub.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test008.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test008_sub.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test009.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test010.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test011.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test012.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test012_sub.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test013.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test014.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test015.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test016.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test017.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test018.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test019.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test020.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test021.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test022.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test023.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test024.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test024_sub.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test025.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test026.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test030.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test031.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test032.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test033.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test034.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test035.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test036.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test037.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \arbiter.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +5.20. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \abc9_test001. + Optimizing cells in module \abc9_test002. + Optimizing cells in module \abc9_test003. + Optimizing cells in module \abc9_test004. + Optimizing cells in module \abc9_test005. + Optimizing cells in module \abc9_test006. + Optimizing cells in module \abc9_test007. + Optimizing cells in module \abc9_test007_sub. + Optimizing cells in module \abc9_test008. + Optimizing cells in module \abc9_test008_sub. + Optimizing cells in module \abc9_test009. + Optimizing cells in module \abc9_test010. + Optimizing cells in module \abc9_test011. + Optimizing cells in module \abc9_test012. + Optimizing cells in module \abc9_test012_sub. + Optimizing cells in module \abc9_test013. + Optimizing cells in module \abc9_test014. + Optimizing cells in module \abc9_test015. + Optimizing cells in module \abc9_test016. + Optimizing cells in module \abc9_test017. + Optimizing cells in module \abc9_test018. + Optimizing cells in module \abc9_test019. + Optimizing cells in module \abc9_test020. + Optimizing cells in module \abc9_test021. + Optimizing cells in module \abc9_test022. + Optimizing cells in module \abc9_test023. + Optimizing cells in module \abc9_test024. + Optimizing cells in module \abc9_test024_sub. + Optimizing cells in module \abc9_test025. + Optimizing cells in module \abc9_test026. + Optimizing cells in module \abc9_test030. + Optimizing cells in module \abc9_test031. + Optimizing cells in module \abc9_test032. + Optimizing cells in module \abc9_test033. + Optimizing cells in module \abc9_test034. + Optimizing cells in module \abc9_test035. + Optimizing cells in module \abc9_test036. + Optimizing cells in module \abc9_test037. + Optimizing cells in module \arbiter. +Performed a total of 0 changes. + +5.21. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\abc9_test001'. +Finding identical cells in module `\abc9_test002'. +Finding identical cells in module `\abc9_test003'. +Finding identical cells in module `\abc9_test004'. +Finding identical cells in module `\abc9_test005'. +Finding identical cells in module `\abc9_test006'. +Finding identical cells in module `\abc9_test007'. +Finding identical cells in module `\abc9_test007_sub'. +Finding identical cells in module `\abc9_test008'. +Finding identical cells in module `\abc9_test008_sub'. +Finding identical cells in module `\abc9_test009'. +Finding identical cells in module `\abc9_test010'. +Finding identical cells in module `\abc9_test011'. +Finding identical cells in module `\abc9_test012'. +Finding identical cells in module `\abc9_test012_sub'. +Finding identical cells in module `\abc9_test013'. +Finding identical cells in module `\abc9_test014'. +Finding identical cells in module `\abc9_test015'. +Finding identical cells in module `\abc9_test016'. +Finding identical cells in module `\abc9_test017'. +Finding identical cells in module `\abc9_test018'. +Finding identical cells in module `\abc9_test019'. +Finding identical cells in module `\abc9_test020'. +Finding identical cells in module `\abc9_test021'. +Finding identical cells in module `\abc9_test022'. +Finding identical cells in module `\abc9_test023'. +Finding identical cells in module `\abc9_test024'. +Finding identical cells in module `\abc9_test024_sub'. +Finding identical cells in module `\abc9_test025'. +Finding identical cells in module `\abc9_test026'. +Finding identical cells in module `\abc9_test030'. +Finding identical cells in module `\abc9_test031'. +Finding identical cells in module `\abc9_test032'. +Finding identical cells in module `\abc9_test033'. +Finding identical cells in module `\abc9_test034'. +Finding identical cells in module `\abc9_test035'. +Finding identical cells in module `\abc9_test036'. +Finding identical cells in module `\abc9_test037'. +Finding identical cells in module `\arbiter'. +Removed a total of 0 cells. + +5.22. Executing OPT_SHARE pass. + +5.23. Executing OPT_DFF pass (perform DFF optimizations). + +5.24. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \abc9_test001.. +Finding unused cells or wires in module \abc9_test002.. +Finding unused cells or wires in module \abc9_test003.. +Finding unused cells or wires in module \abc9_test004.. +Finding unused cells or wires in module \abc9_test005.. +Finding unused cells or wires in module \abc9_test006.. +Finding unused cells or wires in module \abc9_test007.. +Finding unused cells or wires in module \abc9_test007_sub.. +Finding unused cells or wires in module \abc9_test008.. +Finding unused cells or wires in module \abc9_test008_sub.. +Finding unused cells or wires in module \abc9_test009.. +Finding unused cells or wires in module \abc9_test010.. +Finding unused cells or wires in module \abc9_test011.. +Finding unused cells or wires in module \abc9_test012.. +Finding unused cells or wires in module \abc9_test012_sub.. +Finding unused cells or wires in module \abc9_test013.. +Finding unused cells or wires in module \abc9_test014.. +Finding unused cells or wires in module \abc9_test015.. +Finding unused cells or wires in module \abc9_test016.. +Finding unused cells or wires in module \abc9_test017.. +Finding unused cells or wires in module \abc9_test018.. +Finding unused cells or wires in module \abc9_test019.. +Finding unused cells or wires in module \abc9_test020.. +Finding unused cells or wires in module \abc9_test021.. +Finding unused cells or wires in module \abc9_test022.. +Finding unused cells or wires in module \abc9_test023.. +Finding unused cells or wires in module \abc9_test024.. +Finding unused cells or wires in module \abc9_test024_sub.. +Finding unused cells or wires in module \abc9_test025.. +Finding unused cells or wires in module \abc9_test026.. +Finding unused cells or wires in module \abc9_test030.. +Finding unused cells or wires in module \abc9_test031.. +Finding unused cells or wires in module \abc9_test032.. +Finding unused cells or wires in module \abc9_test033.. +Finding unused cells or wires in module \abc9_test034.. +Finding unused cells or wires in module \abc9_test035.. +Finding unused cells or wires in module \abc9_test036.. +Finding unused cells or wires in module \abc9_test037.. +Finding unused cells or wires in module \arbiter.. + +5.25. Executing OPT_EXPR pass (perform const folding). +Optimizing module abc9_test001. +Optimizing module abc9_test002. +Optimizing module abc9_test003. +Optimizing module abc9_test004. +Optimizing module abc9_test005. +Optimizing module abc9_test006. +Optimizing module abc9_test007. +Optimizing module abc9_test007_sub. +Optimizing module abc9_test008. +Optimizing module abc9_test008_sub. +Optimizing module abc9_test009. +Optimizing module abc9_test010. +Optimizing module abc9_test011. +Optimizing module abc9_test012. +Optimizing module abc9_test012_sub. +Optimizing module abc9_test013. +Optimizing module abc9_test014. +Optimizing module abc9_test015. +Optimizing module abc9_test016. +Optimizing module abc9_test017. +Optimizing module abc9_test018. +Optimizing module abc9_test019. +Optimizing module abc9_test020. +Optimizing module abc9_test021. +Optimizing module abc9_test022. +Optimizing module abc9_test023. +Optimizing module abc9_test024. +Optimizing module abc9_test024_sub. +Optimizing module abc9_test025. +Optimizing module abc9_test026. +Optimizing module abc9_test030. +Optimizing module abc9_test031. +Optimizing module abc9_test032. +Optimizing module abc9_test033. +Optimizing module abc9_test034. +Optimizing module abc9_test035. +Optimizing module abc9_test036. +Optimizing module abc9_test037. +Optimizing module arbiter. + +5.26. Finished OPT passes. (There is nothing left to do.) + +6. Executing TECHMAP pass (map to technology primitives). + +6.1. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/techmap.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +6.2. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $dff. +Using extmapper simplemap for cells of type $adff. +Using extmapper simplemap for cells of type $dlatch. +Using template $paramod$constmap:7ad8fbc46f703f685a088264bc000efc3b6130e2$paramod$cbc044d1bfac1f26bafb5691fcbb649e98f6b6fc\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. +Using extmapper simplemap for cells of type $and. +Using extmapper simplemap for cells of type $not. +Using extmapper simplemap for cells of type $reduce_xor. +No more expansions possible. + + +7. Executing ABC9 pass. + +7.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.2. Executing ABC9_OPS pass (helper functions for ABC9). + +7.3. Executing SCC pass (detecting logic loops). +Found 0 SCCs in module abc9_test001. +Found 0 SCCs in module abc9_test002. +Found 0 SCCs in module abc9_test003. +Found 0 SCCs in module abc9_test004. +Found 0 SCCs in module abc9_test005. +Found 0 SCCs in module abc9_test006. +Found 0 SCCs in module abc9_test007. +Found 0 SCCs in module abc9_test007_sub. +Found 0 SCCs in module abc9_test008. +Found 0 SCCs in module abc9_test008_sub. +Found 0 SCCs in module abc9_test009. +Found 0 SCCs in module abc9_test010. +Found 0 SCCs in module abc9_test011. +Found 0 SCCs in module abc9_test012. +Found 0 SCCs in module abc9_test012_sub. +Found 0 SCCs in module abc9_test013. +Found 0 SCCs in module abc9_test014. +Found 0 SCCs in module abc9_test015. +Found 0 SCCs in module abc9_test016. +Found 0 SCCs in module abc9_test017. +Found 0 SCCs in module abc9_test018. +Found 0 SCCs in module abc9_test019. +Found 0 SCCs in module abc9_test020. +Found 0 SCCs in module abc9_test021. +Found 0 SCCs in module abc9_test022. +Found 0 SCCs in module abc9_test023. +Found 0 SCCs in module abc9_test024. +Found 0 SCCs in module abc9_test024_sub. +Found 0 SCCs in module abc9_test025. +Found 0 SCCs in module abc9_test026. +Found 0 SCCs in module abc9_test030. +Found 0 SCCs in module abc9_test031. +Found 0 SCCs in module abc9_test032. +Found 0 SCCs in module abc9_test033. +Found 0 SCCs in module abc9_test034. +Found 0 SCCs in module abc9_test035. +Found 0 SCCs in module abc9_test036. +Found an SCC: m +Found 1 SCCs in module abc9_test037. +Found 0 SCCs in module arbiter. +Found 1 SCCs. + +7.4. Executing ABC9_OPS pass (helper functions for ABC9). + +7.5. Executing PROC pass (convert processes to netlists). + +7.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +7.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +7.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 0 assignments to connections. + +7.5.4. Executing PROC_INIT pass (extract init attributes). + +7.5.5. Executing PROC_ARST pass (detect async resets in processes). + +7.5.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + +7.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). + +7.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +7.5.9. Executing PROC_DFF pass (convert process syncs to FFs). + +7.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +7.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +7.5.12. Executing OPT_EXPR pass (perform const folding). + +7.6. Executing TECHMAP pass (map to technology primitives). + +7.6.1. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/techmap.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +7.6.2. Continuing TECHMAP pass. +No more expansions possible. + + +7.7. Executing OPT pass (performing simple optimizations). + +7.7.1. Executing OPT_EXPR pass (perform const folding). + +7.7.2. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +7.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Removed 0 multiplexer ports. + +7.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +Performed a total of 0 changes. + +7.7.5. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +7.7.6. Executing OPT_DFF pass (perform DFF optimizations). + +7.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). + +7.7.8. Executing OPT_EXPR pass (perform const folding). + +7.7.9. Finished OPT passes. (There is nothing left to do.) + +7.8. Executing TECHMAP pass (map to technology primitives). + +7.8.1. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/abc9_map.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/abc9_map.v' to AST representation. +Successfully finished Verilog frontend. + +7.8.2. Continuing TECHMAP pass. +No more expansions possible. + + +7.9. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v' to AST representation. +Replacing existing blackbox module `$__ABC9_DELAY' at /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v:2.1-7.10. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Replacing existing blackbox module `$__ABC9_SCC_BREAKER' at /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v:9.1-11.10. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Replacing existing module `$__DFF_N__$abc9_flop' at /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v:14.1-20.10. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Replacing existing module `$__DFF_P__$abc9_flop' at /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v:23.1-29.10. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +7.10. Executing ABC9_OPS pass (helper functions for ABC9). + + +7.11. Executing ABC9_OPS pass (helper functions for ABC9). + + +7.12. Executing TECHMAP pass (map to technology primitives). + +7.12.1. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/techmap.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +7.12.2. Continuing TECHMAP pass. +Using template MUXF7 for cells of type MUXF7. +Using extmapper simplemap for cells of type $mux. +No more expansions possible. + + +7.13. Executing OPT pass (performing simple optimizations). + +7.13.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module abc9_test036. +Optimizing module abc9_test037. + +7.13.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\abc9_test036'. +Finding identical cells in module `\abc9_test037'. +Removed a total of 0 cells. + +7.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \abc9_test036.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test037.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +7.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \abc9_test036. + Optimizing cells in module \abc9_test037. +Performed a total of 0 changes. + +7.13.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\abc9_test036'. +Finding identical cells in module `\abc9_test037'. +Removed a total of 0 cells. + +7.13.6. Executing OPT_DFF pass (perform DFF optimizations). + +7.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \abc9_test036.. +Finding unused cells or wires in module \abc9_test037.. +Removed 0 unused cells and 6 unused wires. + + +7.13.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module abc9_test036. +Optimizing module abc9_test037. + +7.13.9. Rerunning OPT passes. (Maybe there is more to do..) + +7.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \abc9_test036.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \abc9_test037.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +7.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \abc9_test036. + Optimizing cells in module \abc9_test037. +Performed a total of 0 changes. + +7.13.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\abc9_test036'. +Finding identical cells in module `\abc9_test037'. +Removed a total of 0 cells. + +7.13.13. Executing OPT_DFF pass (perform DFF optimizations). + +7.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \abc9_test036.. +Finding unused cells or wires in module \abc9_test037.. + +7.13.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module abc9_test036. +Optimizing module abc9_test037. + +7.13.16. Finished OPT passes. (There is nothing left to do.) + +7.14. Executing AIGMAP pass (map logic to AIG). +Module abc9_test037: replaced 1 cells with 7 new cells, skipped 3 cells. + replaced 1 cell types: + 1 $_MUX_ + not replaced 1 cell types: + 3 $specify2 + +7.15. Executing AIGMAP pass (map logic to AIG). +Module abc9_test004: replaced 1 cells with 7 new cells, skipped 0 cells. + replaced 1 cell types: + 1 $_XOR_ +Module abc9_test005: replaced 1 cells with 7 new cells, skipped 1 cells. + replaced 1 cell types: + 1 $_XOR_ + not replaced 1 cell types: + 1 $_NOT_ +Module abc9_test006: replaced 1 cells with 7 new cells, skipped 1 cells. + replaced 1 cell types: + 1 $_XOR_ + not replaced 1 cell types: + 1 $_NOT_ +Module abc9_test007: replaced 0 cells with 0 new cells, skipped 2 cells. + not replaced 2 cell types: + 1 $_NOT_ + 1 abc9_test007_sub +Module abc9_test008: replaced 0 cells with 0 new cells, skipped 2 cells. + not replaced 2 cell types: + 1 $_NOT_ + 1 abc9_test008_sub +Module abc9_test008_sub: replaced 0 cells with 0 new cells, skipped 1 cells. + not replaced 1 cell types: + 1 $_NOT_ +Module abc9_test009: replaced 0 cells with 0 new cells, skipped 2 cells. + not replaced 2 cell types: + 1 $_NOT_ + 1 $_DLATCH_N_ +Module abc9_test010: replaced 0 cells with 0 new cells, skipped 16 cells. + not replaced 2 cell types: + 8 $_NOT_ + 8 $_DLATCH_N_ +Module abc9_test012_sub: replaced 0 cells with 0 new cells, skipped 11 cells. + not replaced 3 cell types: + 4 $_NOT_ + 4 $_DLATCH_N_ + 3 $_DLATCH_P_ +Module abc9_test013: replaced 0 cells with 0 new cells, skipped 8 cells. + not replaced 2 cell types: + 4 $_NOT_ + 4 $_DLATCH_N_ +Module abc9_test014: replaced 0 cells with 0 new cells, skipped 1 cells. + not replaced 1 cell types: + 1 abc9_test012_sub +Module abc9_test015: replaced 0 cells with 0 new cells, skipped 2 cells. + not replaced 1 cell types: + 2 $_NOT_ +Module abc9_test016: replaced 0 cells with 0 new cells, skipped 1 cells. + not replaced 1 cell types: + 1 $_NOT_ +Module abc9_test017: replaced 0 cells with 0 new cells, skipped 1 cells. + not replaced 1 cell types: + 1 $_NOT_ +Module abc9_test018: replaced 0 cells with 0 new cells, skipped 1 cells. + not replaced 1 cell types: + 1 $_NOT_ +Module abc9_test019: replaced 0 cells with 0 new cells, skipped 1 cells. + not replaced 1 cell types: + 1 $_NOT_ +Module abc9_test020: replaced 0 cells with 0 new cells, skipped 1 cells. + not replaced 1 cell types: + 1 $_NOT_ +Module abc9_test021: replaced 0 cells with 0 new cells, skipped 4 cells. + not replaced 4 cell types: + 1 $_NOT_ + 1 $_AND_ + 1 MUXF8 + 1 arbiter +Module abc9_test022: replaced 0 cells with 0 new cells, skipped 8 cells. + not replaced 1 cell types: + 8 $_DFF_P_ +Module abc9_test023: replaced 2 cells with 14 new cells, skipped 2 cells. + replaced 1 cell types: + 2 $_MUX_ + not replaced 1 cell types: + 2 $_NOT_ +Module abc9_test024: replaced 0 cells with 0 new cells, skipped 1 cells. + not replaced 1 cell types: + 1 abc9_test024_sub +Module abc9_test025: replaced 0 cells with 0 new cells, skipped 1 cells. + not replaced 1 cell types: + 1 abc9_test024_sub +Module abc9_test030: replaced 0 cells with 0 new cells, skipped 4 cells. + not replaced 1 cell types: + 4 $_DLATCH_P_ +Module abc9_test031: replaced 0 cells with 0 new cells, skipped 2 cells. + not replaced 2 cell types: + 1 $_DFF_N_ + 1 $_DFF_P_ +Module abc9_test032: replaced 0 cells with 0 new cells, skipped 1 cells. + not replaced 1 cell types: + 1 $_DFF_PP0_ +Module abc9_test033: replaced 0 cells with 0 new cells, skipped 1 cells. + not replaced 1 cell types: + 1 $_DFF_NP1_ +Module abc9_test034: replaced 0 cells with 0 new cells, skipped 2 cells. + not replaced 1 cell types: + 2 $_DFF_P_ +Module abc9_test035: replaced 0 cells with 0 new cells, skipped 2 cells. + not replaced 2 cell types: + 1 $_DFF_N_ + 1 $_DFF_P_ +Module abc9_test036: replaced 0 cells with 0 new cells, skipped 2 cells. + not replaced 1 cell types: + 2 MUXF8 +Module abc9_test037: replaced 0 cells with 0 new cells, skipped 2 cells. + not replaced 2 cell types: + 1 MUXF7 + 1 $__ABC9_SCC_BREAKER + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 0 AND gates and 4 wires from module `abc9_test001' to a netlist network with 1 inputs and 1 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 1/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 1/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 1/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.00 seconds, total: 0.00 seconds + +7.15.5. Executing AIGER frontend. + +Removed 0 unused cells and 1 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: input signals: 1 +ABC RESULTS: output signals: 1 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 0 AND gates and 5 wires from module `abc9_test002' to a netlist network with 2 inputs and 1 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 2/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 2/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 2/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.01 seconds, total: 0.01 seconds + +7.15.5. Executing AIGER frontend. + +Removed 0 unused cells and 2 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: input signals: 1 +ABC RESULTS: output signals: 1 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 0 AND gates and 6 wires from module `abc9_test003' to a netlist network with 2 inputs and 2 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 2/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 2/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 2/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.01 seconds, total: 0.01 seconds + +7.15.5. Executing AIGER frontend. + +Removed 0 unused cells and 2 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: input signals: 1 +ABC RESULTS: output signals: 1 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 3 AND gates and 11 wires from module `abc9_test004' to a netlist network with 2 inputs and 1 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 2/ 1 and = 3 lev = 2 (2.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 2/ 1 and = 6 lev = 2 (2.00) mem = 0.00 MB ch = 1 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 6. Ch = 1. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 1.00. Ar = 1.0. Edge = 2. Cut = 12. T = 0.00 sec +ABC: P: Del = 1.00. Ar = 1.0. Edge = 2. Cut = 12. T = 0.00 sec +ABC: P: Del = 1.00. Ar = 1.0. Edge = 2. Cut = 12. T = 0.00 sec +ABC: F: Del = 1.00. Ar = 1.0. Edge = 2. Cut = 12. T = 0.00 sec +ABC: A: Del = 1.00. Ar = 1.0. Edge = 2. Cut = 12. T = 0.00 sec +ABC: A: Del = 1.00. Ar = 1.0. Edge = 2. Cut = 12. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 2/ 1 and = 3 lev = 2 (2.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=2) : lut = 1 edge = 2 lev = 1 (1.00) mem = 0.00 MB +ABC: LUT = 1 : 2=1 100.0 % Ave = 2.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.01 seconds, total: 0.01 seconds + +7.15.5. Executing AIGER frontend. + +Removed 6 unused cells and 9 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: $lut cells: 1 +ABC RESULTS: input signals: 1 +ABC RESULTS: output signals: 1 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 3 AND gates and 12 wires from module `abc9_test005' to a netlist network with 2 inputs and 2 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 2/ 2 and = 3 lev = 2 (2.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 2/ 2 and = 6 lev = 2 (2.00) mem = 0.00 MB ch = 1 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 6. Ch = 1. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 1.00. Ar = 1.0. Edge = 2. Cut = 12. T = 0.00 sec +ABC: P: Del = 1.00. Ar = 1.0. Edge = 2. Cut = 12. T = 0.00 sec +ABC: P: Del = 1.00. Ar = 1.0. Edge = 2. Cut = 12. T = 0.00 sec +ABC: F: Del = 1.00. Ar = 1.0. Edge = 2. Cut = 12. T = 0.00 sec +ABC: A: Del = 1.00. Ar = 1.0. Edge = 2. Cut = 12. T = 0.00 sec +ABC: A: Del = 1.00. Ar = 1.0. Edge = 2. Cut = 12. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 2/ 2 and = 3 lev = 2 (2.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=2) : lut = 1 edge = 2 lev = 1 (1.00) mem = 0.00 MB +ABC: LUT = 1 : 2=1 100.0 % Ave = 2.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.01 seconds, total: 0.01 seconds + +7.15.5. Executing AIGER frontend. + +Removed 6 unused cells and 10 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: $lut cells: 1 +ABC RESULTS: input signals: 1 +ABC RESULTS: output signals: 2 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 3 AND gates and 13 wires from module `abc9_test006' to a netlist network with 2 inputs and 3 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 2/ 3 and = 3 lev = 2 (2.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 2/ 3 and = 6 lev = 2 (2.00) mem = 0.00 MB ch = 1 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 6. Ch = 1. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 1.00. Ar = 1.0. Edge = 2. Cut = 12. T = 0.00 sec +ABC: P: Del = 1.00. Ar = 1.0. Edge = 2. Cut = 12. T = 0.00 sec +ABC: P: Del = 1.00. Ar = 1.0. Edge = 2. Cut = 12. T = 0.00 sec +ABC: F: Del = 1.00. Ar = 1.0. Edge = 2. Cut = 12. T = 0.00 sec +ABC: A: Del = 1.00. Ar = 1.0. Edge = 2. Cut = 12. T = 0.00 sec +ABC: A: Del = 1.00. Ar = 1.0. Edge = 2. Cut = 12. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 2/ 3 and = 3 lev = 2 (2.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=2) : lut = 1 edge = 2 lev = 1 (1.00) mem = 0.00 MB +ABC: LUT = 1 : 2=1 100.0 % Ave = 2.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.01 seconds, total: 0.01 seconds + +7.15.5. Executing AIGER frontend. + +Removed 6 unused cells and 10 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: $lut cells: 1 +ABC RESULTS: input signals: 1 +ABC RESULTS: output signals: 1 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 0 AND gates and 6 wires from module `abc9_test007' to a netlist network with 2 inputs and 2 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 2/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 2/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 2/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.01 seconds, total: 0.01 seconds + +7.15.5. Executing AIGER frontend. + +Removed 0 unused cells and 4 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: $lut cells: 1 +ABC RESULTS: input signals: 1 +ABC RESULTS: output signals: 2 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 0 AND gates and 4 wires from module `abc9_test007_sub' to a netlist network with 1 inputs and 1 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 1/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 1/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 1/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.01 seconds, total: 0.01 seconds + +7.15.5. Executing AIGER frontend. + +Removed 0 unused cells and 1 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: input signals: 1 +ABC RESULTS: output signals: 1 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 0 AND gates and 6 wires from module `abc9_test008' to a netlist network with 2 inputs and 2 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 2/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 2/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 2/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.00 seconds, total: 0.00 seconds + +7.15.5. Executing AIGER frontend. + +Removed 0 unused cells and 4 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: $lut cells: 1 +ABC RESULTS: input signals: 1 +ABC RESULTS: output signals: 2 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 0 AND gates and 4 wires from module `abc9_test008_sub' to a netlist network with 1 inputs and 1 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 1/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 1/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 1/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.00 seconds, total: 0.00 seconds + +7.15.5. Executing AIGER frontend. + +Removed 0 unused cells and 2 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: $lut cells: 1 +ABC RESULTS: input signals: 1 +ABC RESULTS: output signals: 1 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 0 AND gates and 5 wires from module `abc9_test009' to a netlist network with 3 inputs and 1 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 3/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 3/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 3/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.00 seconds, total: 0.00 seconds + +7.15.5. Executing AIGER frontend. + +Removed 0 unused cells and 5 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: $lut cells: 1 +ABC RESULTS: input signals: 2 +ABC RESULTS: output signals: 1 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 0 AND gates and 19 wires from module `abc9_test010' to a netlist network with 17 inputs and 8 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 17/ 8 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 17/ 8 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 17/ 8 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.00 seconds, total: 0.00 seconds + +7.15.5. Executing AIGER frontend. + +Removed 0 unused cells and 33 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: $lut cells: 8 +ABC RESULTS: input signals: 2 +ABC RESULTS: output signals: 1 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 0 AND gates and 4 wires from module `abc9_test011' to a netlist network with 2 inputs and 1 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 2/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 2/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 2/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.00 seconds, total: 0.00 seconds + +7.15.5. Executing AIGER frontend. + +Removed 0 unused cells and 3 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: input signals: 1 +ABC RESULTS: output signals: 1 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 0 AND gates and 4 wires from module `abc9_test012' to a netlist network with 1 inputs and 1 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 1/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 1/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = -100000000.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = -100000000.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = -100000000.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = -100000000.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = -100000000.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = -100000000.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 1/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.01 seconds, total: 0.01 seconds + +7.15.5. Executing AIGER frontend. + +Removed 0 unused cells and 2 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: input signals: 1 +ABC RESULTS: output signals: 1 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 0 AND gates and 14 wires from module `abc9_test012_sub' to a netlist network with 12 inputs and 8 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 12/ 8 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 12/ 8 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 12/ 8 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.00 seconds, total: 0.00 seconds + +7.15.5. Executing AIGER frontend. + +Removed 0 unused cells and 24 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: $lut cells: 4 +ABC RESULTS: input signals: 2 +ABC RESULTS: output signals: 1 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 0 AND gates and 11 wires from module `abc9_test013' to a netlist network with 9 inputs and 4 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 9/ 4 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 9/ 4 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 9/ 4 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.00 seconds, total: 0.00 seconds + +7.15.5. Executing AIGER frontend. + +Removed 0 unused cells and 17 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: $lut cells: 4 +ABC RESULTS: input signals: 2 +ABC RESULTS: output signals: 1 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 0 AND gates and 11 wires from module `abc9_test014' to a netlist network with 9 inputs and 8 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 9/ 8 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 9/ 8 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 9/ 8 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.00 seconds, total: 0.00 seconds + +7.15.5. Executing AIGER frontend. + +Removed 0 unused cells and 17 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: input signals: 1 +ABC RESULTS: output signals: 1 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 0 AND gates and 6 wires from module `abc9_test015' to a netlist network with 2 inputs and 2 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 2/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 2/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 2/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.00 seconds, total: 0.00 seconds + +7.15.5. Executing AIGER frontend. + +Removed 0 unused cells and 4 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: $lut cells: 2 +ABC RESULTS: input signals: 2 +ABC RESULTS: output signals: 2 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 0 AND gates and 5 wires from module `abc9_test016' to a netlist network with 1 inputs and 2 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 1/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 1/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 1/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.00 seconds, total: 0.00 seconds + +7.15.5. Executing AIGER frontend. + +Removed 0 unused cells and 2 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: $lut cells: 1 +ABC RESULTS: input signals: 1 +ABC RESULTS: output signals: 2 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 0 AND gates and 5 wires from module `abc9_test017' to a netlist network with 1 inputs and 2 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 1/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 1/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 1/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.00 seconds, total: 0.00 seconds + +7.15.5. Executing AIGER frontend. + +Removed 0 unused cells and 2 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: $lut cells: 1 +ABC RESULTS: input signals: 1 +ABC RESULTS: output signals: 2 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 0 AND gates and 5 wires from module `abc9_test018' to a netlist network with 1 inputs and 2 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 1/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 1/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 1/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.00 seconds, total: 0.00 seconds + +7.15.5. Executing AIGER frontend. + +Removed 0 unused cells and 3 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: $lut cells: 1 +ABC RESULTS: input signals: 1 +ABC RESULTS: output signals: 2 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 0 AND gates and 4 wires from module `abc9_test019' to a netlist network with 1 inputs and 1 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 1/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 1/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 1/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.00 seconds, total: 0.00 seconds + +7.15.5. Executing AIGER frontend. + +Removed 0 unused cells and 2 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: $lut cells: 1 +ABC RESULTS: input signals: 1 +ABC RESULTS: output signals: 1 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 0 AND gates and 4 wires from module `abc9_test020' to a netlist network with 1 inputs and 1 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 1/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 1/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 1/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.01 seconds, total: 0.01 seconds + +7.15.5. Executing AIGER frontend. + +Removed 0 unused cells and 2 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: $lut cells: 1 +ABC RESULTS: input signals: 1 +ABC RESULTS: output signals: 1 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 1 AND gates and 722 wires from module `abc9_test021' to a netlist network with 569 inputs and 151 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 569/ 151 and = 1 lev = 1 (0.01) mem = 0.01 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 569/ 151 and = 1 lev = 1 (0.01) mem = 0.01 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 1. Ch = 0. Total mem = 0.10 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 1.00. Ar = 1.0. Edge = 2. Cut = 1. T = 0.00 sec +ABC: P: Del = 1.00. Ar = 1.0. Edge = 2. Cut = 1. T = 0.00 sec +ABC: P: Del = 1.00. Ar = 1.0. Edge = 2. Cut = 1. T = 0.00 sec +ABC: F: Del = 1.00. Ar = 1.0. Edge = 2. Cut = 1. T = 0.00 sec +ABC: A: Del = 1.00. Ar = 1.0. Edge = 2. Cut = 1. T = 0.00 sec +ABC: A: Del = 1.00. Ar = 1.0. Edge = 2. Cut = 1. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 569/ 151 and = 1 lev = 1 (0.01) mem = 0.01 MB box = 0 bb = 0 +ABC: Mapping (K=2) : lut = 1 edge = 2 lev = 1 (0.01) mem = 0.00 MB +ABC: LUT = 1 : 2=1 100.0 % Ave = 2.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.01 seconds, total: 0.01 seconds + +7.15.5. Executing AIGER frontend. + +Removed 1 unused cells and 573 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: $lut cells: 1 +ABC RESULTS: input signals: 15 +ABC RESULTS: output signals: 15 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 0 AND gates and 20 wires from module `abc9_test022' to a netlist network with 10 inputs and 8 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 10/ 8 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 10/ 8 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 10/ 8 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.00 seconds, total: 0.00 seconds + +7.15.5. Executing AIGER frontend. + +Removed 0 unused cells and 10 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: input signals: 3 +ABC RESULTS: output signals: 1 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 6 AND gates and 19 wires from module `abc9_test023' to a netlist network with 8 inputs and 2 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 8/ 2 and = 3 lev = 2 (1.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 8/ 2 and = 6 lev = 2 (1.00) mem = 0.00 MB ch = 1 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 6. Ch = 1. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 1.00. Ar = 1.0. Edge = 2. Cut = 12. T = 0.00 sec +ABC: P: Del = 1.00. Ar = 1.0. Edge = 2. Cut = 12. T = 0.00 sec +ABC: P: Del = 1.00. Ar = 1.0. Edge = 2. Cut = 12. T = 0.00 sec +ABC: F: Del = 1.00. Ar = 1.0. Edge = 2. Cut = 12. T = 0.00 sec +ABC: A: Del = 1.00. Ar = 1.0. Edge = 2. Cut = 12. T = 0.00 sec +ABC: A: Del = 1.00. Ar = 1.0. Edge = 2. Cut = 12. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 8/ 2 and = 3 lev = 2 (1.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=2) : lut = 1 edge = 2 lev = 1 (0.50) mem = 0.00 MB +ABC: LUT = 1 : 2=1 100.0 % Ave = 2.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.01 seconds, total: 0.01 seconds + +7.15.5. Executing AIGER frontend. + +Removed 6 unused cells and 15 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: $lut cells: 1 +ABC RESULTS: input signals: 1 +ABC RESULTS: output signals: 1 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 0 AND gates and 10 wires from module `abc9_test024' to a netlist network with 6 inputs and 4 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 6/ 4 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 6/ 4 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 6/ 4 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.00 seconds, total: 0.00 seconds + +7.15.5. Executing AIGER frontend. + +Removed 0 unused cells and 9 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: input signals: 1 +ABC RESULTS: output signals: 1 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 0 AND gates and 6 wires from module `abc9_test024_sub' to a netlist network with 2 inputs and 2 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 2/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 2/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 2/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.01 seconds, total: 0.01 seconds + +7.15.5. Executing AIGER frontend. + +Removed 0 unused cells and 2 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: input signals: 1 +ABC RESULTS: output signals: 1 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 0 AND gates and 10 wires from module `abc9_test025' to a netlist network with 6 inputs and 4 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 6/ 4 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 6/ 4 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 6/ 4 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.01 seconds, total: 0.01 seconds + +7.15.5. Executing AIGER frontend. + +Removed 0 unused cells and 9 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: input signals: 1 +ABC RESULTS: output signals: 1 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 0 AND gates and 10 wires from module `abc9_test026' to a netlist network with 0 inputs and 8 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 0/ 8 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 0/ 8 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = -100000000.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = -100000000.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = -100000000.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = -100000000.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = -100000000.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = -100000000.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 0/ 8 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.01 seconds, total: 0.01 seconds + +7.15.5. Executing AIGER frontend. + +Removed 0 unused cells and 2 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: input signals: 0 +ABC RESULTS: output signals: 2 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 0 AND gates and 11 wires from module `abc9_test030' to a netlist network with 9 inputs and 4 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 9/ 4 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 9/ 4 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 9/ 4 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.01 seconds, total: 0.01 seconds + +7.15.5. Executing AIGER frontend. + +Removed 0 unused cells and 13 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: input signals: 2 +ABC RESULTS: output signals: 1 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 0 AND gates and 7 wires from module `abc9_test031' to a netlist network with 5 inputs and 2 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 5/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 5/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 5/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.00 seconds, total: 0.00 seconds + +7.15.5. Executing AIGER frontend. + +Removed 0 unused cells and 7 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: input signals: 3 +ABC RESULTS: output signals: 2 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 0 AND gates and 6 wires from module `abc9_test032' to a netlist network with 4 inputs and 1 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 4/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 4/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 4/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.01 seconds, total: 0.01 seconds + +7.15.5. Executing AIGER frontend. + +Removed 0 unused cells and 5 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: input signals: 3 +ABC RESULTS: output signals: 1 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 0 AND gates and 6 wires from module `abc9_test033' to a netlist network with 4 inputs and 1 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 4/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 4/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 4/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.01 seconds, total: 0.01 seconds + +7.15.5. Executing AIGER frontend. + +Removed 0 unused cells and 5 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: input signals: 3 +ABC RESULTS: output signals: 1 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 0 AND gates and 6 wires from module `abc9_test034' to a netlist network with 4 inputs and 2 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 4/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 4/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 4/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.01 seconds, total: 0.01 seconds + +7.15.5. Executing AIGER frontend. + +Removed 0 unused cells and 6 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: input signals: 2 +ABC RESULTS: output signals: 2 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 0 AND gates and 6 wires from module `abc9_test035' to a netlist network with 4 inputs and 2 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 4/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 4/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 4/ 2 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.00 seconds, total: 0.00 seconds + +7.15.5. Executing AIGER frontend. + +Removed 0 unused cells and 6 unused wires. + +7.15.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: input signals: 2 +ABC RESULTS: output signals: 1 +Removing temp directory. + +7.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.15.2. Executing XAIGER backend. + +Extracted 0 AND gates and 7 wires from module `abc9_test036' to a netlist network with 4 inputs and 2 outputs. + +7.15.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.15.4. Executing ABC9. diff --git a/tests/simple_abc9/case_large.err b/tests/simple_abc9/case_large.err new file mode 100644 index 00000000000..c6eee51e298 --- /dev/null +++ b/tests/simple_abc9/case_large.err @@ -0,0 +1,609 @@ ++ body ++ cd case_large.out +++ basename case_large.v ++ fn=case_large.v +++ basename case_large ++ bn=case_large ++ refext=v ++ rm -f case_large_ref.fir ++ [[ v == \v ]] ++ egrep -v '^\s*`timescale' ../case_large.v +egrep: warning: egrep is obsolescent; using grep -E ++ '[' '!' -f ../case_large_tb.v ']' ++ /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../yosys -f 'verilog -noblackbox -specify -D_AUTOTB' -b 'test_autotb -n 300' -o case_large_tb.v case_large_ref.v + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2024 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) + +-- Parsing `case_large_ref.v' using frontend `verilog -noblackbox -specify -D_AUTOTB' -- + +1. Executing Verilog-2005 frontend: case_large_ref.v +Parsing Verilog input from `case_large_ref.v' to AST representation. +Generating RTLIL representation for module `\case_lage_top'. +Successfully finished Verilog frontend. + +-- Writing to `case_large_tb.v' using backend `test_autotb -n 300' -- + +2. Executing TEST_AUTOTB backend (auto-generate pseudo-random test benches). +Generating test bench for module `\case_lage_top'. + +End of script. Logfile hash: 8f86c16e9c, CPU: user 0.01s system 0.01s, MEM: 16.60 MB peak +Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) +Time spent: 99% 1x read_verilog (0 sec), 0% 1x test_autotb (0 sec) ++ false ++ compile_and_run case_large_tb_ref case_large_out_ref case_large_tb.v case_large_ref.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simlib.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simcells.v ++ exe=case_large_tb_ref ++ output=case_large_out_ref ++ shift 2 ++ '[' v == sv ']' ++ language_gen=-g2005 ++ false ++ false ++ iverilog -g2005 '-Doutfile="case_large_out_ref"' -s testbench -o case_large_tb_ref case_large_tb.v case_large_ref.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simlib.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simcells.v ++ vvp -n case_large_tb_ref +case_large_tb.v:98: $finish called at 120200 (1s) ++ false ++ test_count=0 ++ '[' 'verilog -noblackbox -specify' = verific -o 'verilog -noblackbox -specify' = verific_gates ']' ++ '[' -n '' ']' ++ '[' -n ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' ']' ++ test_passes -f 'verilog -noblackbox -specify ' -p ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' case_large_ref.v ++ /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../yosys -b 'verilog -noattr -noexpr -siminit' -o case_large_syn0.v -f 'verilog -noblackbox -specify ' -p ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' case_large_ref.v + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2024 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) + +-- Parsing `case_large_ref.v' using frontend `verilog -noblackbox -specify ' -- + +1. Executing Verilog-2005 frontend: case_large_ref.v +Parsing Verilog input from `case_large_ref.v' to AST representation. +Generating RTLIL representation for module `\case_lage_top'. +Successfully finished Verilog frontend. + +-- Running command ` read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' -- + +2. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v' to AST representation. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +3. Executing HIERARCHY pass (managing design hierarchy). + +4. Executing SYNTH pass. + +4.1. Executing PROC pass (convert processes to netlists). + +4.1.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +4.1.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$case_large_ref.v:10$1 in module case_lage_top. +Removed a total of 0 dead cases. + +4.1.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 1 assignment to connection. + +4.1.4. Executing PROC_INIT pass (extract init attributes). + +4.1.5. Executing PROC_ARST pass (detect async resets in processes). + +4.1.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +4.1.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\case_lage_top.$proc$case_large_ref.v:10$1'. + 1/1: $1\y[31:0] + +4.1.8. Executing PROC_DLATCH pass (convert process syncs to latches). +No latch inferred for signal `\case_lage_top.\y' from process `\case_lage_top.$proc$case_large_ref.v:10$1'. + +4.1.9. Executing PROC_DFF pass (convert process syncs to FFs). + +4.1.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +4.1.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 1 empty switch in `\case_lage_top.$proc$case_large_ref.v:10$1'. +Removing empty process `case_lage_top.$proc$case_large_ref.v:10$1'. +Cleaned up 1 empty switch. + +4.1.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module case_lage_top. + +4.2. Executing OPT_EXPR pass (perform const folding). +Optimizing module case_lage_top. + +4.3. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \case_lage_top.. +Removed 0 unused cells and 3 unused wires. + + +4.4. Executing CHECK pass (checking for obvious problems). +Checking module case_lage_top... +Found and reported 0 problems. + +4.5. Executing OPT pass (performing simple optimizations). + +4.5.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module case_lage_top. + +4.5.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\case_lage_top'. +Removed a total of 0 cells. + +4.5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \case_lage_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \case_lage_top. +Performed a total of 0 changes. + +4.5.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\case_lage_top'. +Removed a total of 0 cells. + +4.5.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.5.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \case_lage_top.. + +4.5.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module case_lage_top. + +4.5.9. Finished OPT passes. (There is nothing left to do.) + +4.6. Executing FSM pass (extract and optimize FSM). + +4.6.1. Executing FSM_DETECT pass (finding FSMs in design). + +4.6.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +4.6.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.6.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \case_lage_top.. + +4.6.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.6.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +4.6.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +4.6.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +4.7. Executing OPT pass (performing simple optimizations). + +4.7.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module case_lage_top. + +4.7.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\case_lage_top'. +Removed a total of 0 cells. + +4.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \case_lage_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \case_lage_top. +Performed a total of 0 changes. + +4.7.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\case_lage_top'. +Removed a total of 0 cells. + +4.7.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \case_lage_top.. + +4.7.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module case_lage_top. + +4.7.9. Finished OPT passes. (There is nothing left to do.) + +4.8. Executing WREDUCE pass (reducing word size of cells). +Removed top 23 bits (of 32) from mux cell case_lage_top.$procmux$3 ($pmux). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$5_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$6_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$7_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$8_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$11_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$12_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$16_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$17_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$18_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$21_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$23_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$25_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$27_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$28_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$29_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$30_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$34_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$35_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$36_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$38_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$40_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$42_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$43_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$45_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$47_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$48_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$49_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$50_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$51_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$53_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$54_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$55_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$57_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$59_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$60_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$61_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$62_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$63_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$65_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$68_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$69_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$70_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$73_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$74_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$75_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$76_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$77_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$79_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$80_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$86_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$92_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$93_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$94_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$95_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$97_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$98_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$99_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$100_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$104_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$105_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$106_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$107_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$111_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$113_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$114_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$117_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$119_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$121_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$122_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$125_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$126_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$128_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$130_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$133_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$138_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$139_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$141_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$146_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$149_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$154_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$155_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$156_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$157_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$158_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$160_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$161_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$163_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$166_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$171_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$173_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$175_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$178_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$179_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$181_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$182_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$184_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$185_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$186_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$187_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$188_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$190_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$192_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$194_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$195_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$197_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$199_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$201_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$203_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$204_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$207_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$208_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$210_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$214_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$215_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$216_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$217_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$218_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$224_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$225_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$226_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$229_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$234_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$237_CMP0 ($eq). +Removed top 4 bits (of 128) from port B of cell case_lage_top.$procmux$241_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$243_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$247_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$251_CMP0 ($eq). +Removed top 3 bits (of 128) from port B of cell case_lage_top.$procmux$257_CMP0 ($eq). + +4.9. Executing PEEPOPT pass (run peephole optimizers). + +4.10. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \case_lage_top.. + +4.11. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module case_lage_top: + created 0 $alu and 0 $macc cells. + +4.12. Executing SHARE pass (SAT-based resource sharing). + +4.13. Executing OPT pass (performing simple optimizations). + +4.13.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module case_lage_top. + +4.13.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\case_lage_top'. +Removed a total of 0 cells. + +4.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \case_lage_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \case_lage_top. +Performed a total of 0 changes. + +4.13.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\case_lage_top'. +Removed a total of 0 cells. + +4.13.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \case_lage_top.. + +4.13.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module case_lage_top. + +4.13.9. Finished OPT passes. (There is nothing left to do.) + +4.14. Executing MEMORY pass. + +4.14.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +4.14.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +4.14.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + +4.14.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +4.14.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). + +4.14.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \case_lage_top.. + +4.14.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +4.14.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +4.14.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \case_lage_top.. + +4.14.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +4.15. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \case_lage_top.. + +5. Executing OPT pass (performing simple optimizations). + +5.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module case_lage_top. + +5.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\case_lage_top'. +Removed a total of 0 cells. + +5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \case_lage_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \case_lage_top. +Performed a total of 0 changes. + +5.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\case_lage_top'. +Removed a total of 0 cells. + +5.6. Executing OPT_SHARE pass. + +5.7. Executing OPT_DFF pass (perform DFF optimizations). + +5.8. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \case_lage_top.. + +5.9. Executing OPT_EXPR pass (perform const folding). +Optimizing module case_lage_top. + +5.10. Finished OPT passes. (There is nothing left to do.) + +6. Executing TECHMAP pass (map to technology primitives). + +6.1. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/techmap.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +6.2. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $eq. +Using template $paramod$204bd9472a10bc021642557ec33ba57f089a5c66\_90_pmux for cells of type $pmux. +Using extmapper simplemap for cells of type $reduce_or. +Using extmapper simplemap for cells of type $and. +Using extmapper simplemap for cells of type $mux. +No more expansions possible. + + +7. Executing ABC9 pass. + +7.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.2. Executing ABC9_OPS pass (helper functions for ABC9). + +7.3. Executing SCC pass (detecting logic loops). +Found 0 SCCs in module case_lage_top. +Found 0 SCCs. + +7.4. Executing ABC9_OPS pass (helper functions for ABC9). + +7.5. Executing PROC pass (convert processes to netlists). + +7.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +7.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +7.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 0 assignments to connections. + +7.5.4. Executing PROC_INIT pass (extract init attributes). + +7.5.5. Executing PROC_ARST pass (detect async resets in processes). + +7.5.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + +7.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). + +7.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +7.5.9. Executing PROC_DFF pass (convert process syncs to FFs). + +7.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +7.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +7.5.12. Executing OPT_EXPR pass (perform const folding). + +7.6. Executing TECHMAP pass (map to technology primitives). + +7.6.1. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/techmap.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +7.6.2. Continuing TECHMAP pass. +No more expansions possible. + + +7.7. Executing OPT pass (performing simple optimizations). + +7.7.1. Executing OPT_EXPR pass (perform const folding). + +7.7.2. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +7.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Removed 0 multiplexer ports. + +7.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +Performed a total of 0 changes. + +7.7.5. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +7.7.6. Executing OPT_DFF pass (perform DFF optimizations). + +7.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). + +7.7.8. Executing OPT_EXPR pass (perform const folding). + +7.7.9. Finished OPT passes. (There is nothing left to do.) diff --git a/tests/simple_abc9/dynslice.err b/tests/simple_abc9/dynslice.err new file mode 100644 index 00000000000..2c28b7190cd --- /dev/null +++ b/tests/simple_abc9/dynslice.err @@ -0,0 +1,680 @@ ++ body ++ cd dynslice.out +++ basename dynslice.v ++ fn=dynslice.v +++ basename dynslice ++ bn=dynslice ++ refext=v ++ rm -f dynslice_ref.fir ++ [[ v == \v ]] ++ egrep -v '^\s*`timescale' ../dynslice.v +egrep: warning: egrep is obsolescent; using grep -E ++ '[' '!' -f ../dynslice_tb.v ']' ++ /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../yosys -f 'verilog -noblackbox -specify -D_AUTOTB' -b 'test_autotb -n 300' -o dynslice_tb.v dynslice_ref.v + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2024 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) + +-- Parsing `dynslice_ref.v' using frontend `verilog -noblackbox -specify -D_AUTOTB' -- + +1. Executing Verilog-2005 frontend: dynslice_ref.v +Parsing Verilog input from `dynslice_ref.v' to AST representation. +Generating RTLIL representation for module `\dynslice'. +Successfully finished Verilog frontend. + +-- Writing to `dynslice_tb.v' using backend `test_autotb -n 300' -- + +2. Executing TEST_AUTOTB backend (auto-generate pseudo-random test benches). +Generating test bench for module `\dynslice'. + +End of script. Logfile hash: f95ec3ac7a, CPU: user 0.00s system 0.00s, MEM: 14.04 MB peak +Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) +Time spent: 88% 1x read_verilog (0 sec), 11% 1x test_autotb (0 sec) ++ false ++ compile_and_run dynslice_tb_ref dynslice_out_ref dynslice_tb.v dynslice_ref.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simlib.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simcells.v ++ exe=dynslice_tb_ref ++ output=dynslice_out_ref ++ shift 2 ++ '[' v == sv ']' ++ language_gen=-g2005 ++ false ++ false ++ iverilog -g2005 '-Doutfile="dynslice_out_ref"' -s testbench -o dynslice_tb_ref dynslice_tb.v dynslice_ref.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simlib.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simcells.v ++ vvp -n dynslice_tb_ref +dynslice_tb.v:122: $finish called at 120600 (1s) ++ false ++ test_count=0 ++ '[' 'verilog -noblackbox -specify' = verific -o 'verilog -noblackbox -specify' = verific_gates ']' ++ '[' -n '' ']' ++ '[' -n ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' ']' ++ test_passes -f 'verilog -noblackbox -specify ' -p ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' dynslice_ref.v ++ /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../yosys -b 'verilog -noattr -noexpr -siminit' -o dynslice_syn0.v -f 'verilog -noblackbox -specify ' -p ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' dynslice_ref.v + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2024 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) + +-- Parsing `dynslice_ref.v' using frontend `verilog -noblackbox -specify ' -- + +1. Executing Verilog-2005 frontend: dynslice_ref.v +Parsing Verilog input from `dynslice_ref.v' to AST representation. +Generating RTLIL representation for module `\dynslice'. +Successfully finished Verilog frontend. + +-- Running command ` read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' -- + +2. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v' to AST representation. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +3. Executing HIERARCHY pass (managing design hierarchy). + +4. Executing SYNTH pass. + +4.1. Executing PROC pass (convert processes to netlists). + +4.1.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +4.1.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +4.1.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 3 assignments to connections. + +4.1.4. Executing PROC_INIT pass (extract init attributes). + +4.1.5. Executing PROC_ARST pass (detect async resets in processes). + +4.1.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + +4.1.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\dynslice.$proc$dynslice_ref.v:8$3'. + +4.1.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +4.1.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\dynslice.\dout' using process `\dynslice.$proc$dynslice_ref.v:8$3'. + created $dff cell `$procdff$15' with positive edge clock. +Creating register for signal `\dynslice.$bitselwrite$pos$dynslice_ref.v:10$1' using process `\dynslice.$proc$dynslice_ref.v:8$3'. + created $dff cell `$procdff$16' with positive edge clock. +Creating register for signal `\dynslice.$lookahead\dout$2' using process `\dynslice.$proc$dynslice_ref.v:8$3'. + created $dff cell `$procdff$17' with positive edge clock. + +4.1.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +4.1.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `dynslice.$proc$dynslice_ref.v:8$3'. +Cleaned up 0 empty switches. + +4.1.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module dynslice. + +4.2. Executing OPT_EXPR pass (perform const folding). +Optimizing module dynslice. + + +4.3. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \dynslice.. +Removed 2 unused cells and 6 unused wires. + + +4.4. Executing CHECK pass (checking for obvious problems). +Checking module dynslice... +Found and reported 0 problems. + +4.5. Executing OPT pass (performing simple optimizations). + +4.5.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module dynslice. + +4.5.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\dynslice'. + +Removed a total of 1 cells. + +4.5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \dynslice.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \dynslice. +Performed a total of 0 changes. + +4.5.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\dynslice'. +Removed a total of 0 cells. + +4.5.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.5.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \dynslice.. +Removed 0 unused cells and 1 unused wires. + + +4.5.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module dynslice. + +4.5.9. Rerunning OPT passes. (Maybe there is more to do..) + +4.5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \dynslice.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \dynslice. +Performed a total of 0 changes. + +4.5.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\dynslice'. +Removed a total of 0 cells. + +4.5.13. Executing OPT_DFF pass (perform DFF optimizations). + +4.5.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \dynslice.. + +4.5.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module dynslice. + +4.5.16. Finished OPT passes. (There is nothing left to do.) + +4.6. Executing FSM pass (extract and optimize FSM). + +4.6.1. Executing FSM_DETECT pass (finding FSMs in design). + +4.6.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +4.6.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.6.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \dynslice.. + +4.6.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.6.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +4.6.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +4.6.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +4.7. Executing OPT pass (performing simple optimizations). + +4.7.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module dynslice. + +4.7.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\dynslice'. +Removed a total of 0 cells. + +4.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \dynslice.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \dynslice. +Performed a total of 0 changes. + +4.7.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\dynslice'. +Removed a total of 0 cells. + +4.7.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \dynslice.. + +4.7.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module dynslice. + +4.7.9. Finished OPT passes. (There is nothing left to do.) + +4.8. Executing WREDUCE pass (reducing word size of cells). +Removed top 22 bits (of 33) from port A of cell dynslice.$neg$dynslice_ref.v:0$12 ($neg). +Converting cell dynslice.$neg$dynslice_ref.v:0$12 ($neg) from signed to unsigned. +Removed top 1 bits (of 11) from port A of cell dynslice.$neg$dynslice_ref.v:0$12 ($neg). +Removed top 22 bits (of 32) from wire dynslice.$0$bitselwrite$pos$dynslice_ref.v:10$1[31:0]$4. + +4.9. Executing PEEPOPT pass (run peephole optimizers). + +4.10. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \dynslice.. +Removed 0 unused cells and 1 unused wires. + + +4.11. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module dynslice: + creating $macc model for $mul$dynslice_ref.v:10$6 ($mul). + creating $macc model for $neg$dynslice_ref.v:0$12 ($neg). + creating $alu model for $macc $neg$dynslice_ref.v:0$12. + creating $macc cell for $mul$dynslice_ref.v:10$6: $auto$alumacc.cc:365:replace_macc$19 + creating $alu cell for $neg$dynslice_ref.v:0$12: $auto$alumacc.cc:485:replace_alu$20 + created 1 $alu and 1 $macc cells. + +4.12. Executing SHARE pass (SAT-based resource sharing). + +4.13. Executing OPT pass (performing simple optimizations). + +4.13.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module dynslice. + +4.13.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\dynslice'. +Removed a total of 0 cells. + +4.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \dynslice.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \dynslice. +Performed a total of 0 changes. + +4.13.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\dynslice'. +Removed a total of 0 cells. + +4.13.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \dynslice.. + +4.13.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module dynslice. + +4.13.9. Finished OPT passes. (There is nothing left to do.) + +4.14. Executing MEMORY pass. + +4.14.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +4.14.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +4.14.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + +4.14.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +4.14.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). + +4.14.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \dynslice.. + +4.14.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +4.14.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +4.14.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \dynslice.. + +4.14.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +4.15. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \dynslice.. + +5. Executing OPT pass (performing simple optimizations). + +5.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module dynslice. + +5.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\dynslice'. +Removed a total of 0 cells. + +5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \dynslice.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \dynslice. +Performed a total of 0 changes. + +5.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\dynslice'. +Removed a total of 0 cells. + +5.6. Executing OPT_SHARE pass. + +5.7. Executing OPT_DFF pass (perform DFF optimizations). + +5.8. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \dynslice.. + +5.9. Executing OPT_EXPR pass (perform const folding). +Optimizing module dynslice. + +5.10. Finished OPT passes. (There is nothing left to do.) + +6. Executing TECHMAP pass (map to technology primitives). + +6.1. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/techmap.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +6.2. Continuing TECHMAP pass. +Using template $paramod$40ec39fdbb40e313957832362e47914160e3dfcb\_90_alu for cells of type $alu. +Using extmapper maccmap for cells of type $macc. + add \ctrl * \sel (10x4 bits, unsigned) +Using template $paramod$constmap:5b7a86f055f056b0ef5c3c2a54cd0bcbfbd78a91$paramod$35d43f283fa197ecd06c429c67def546fd6dc204\_90_shift_shiftx for cells of type $shift. +Using extmapper simplemap for cells of type $not. +Using extmapper simplemap for cells of type $and. +Analyzing pattern of constant bits for this cell: +Creating constmapped module `$paramod$constmap:391ed386a5460bc01550bbd1e64ddee1e6666a82$paramod$35d43f283fa197ecd06c429c67def546fd6dc204\_90_shift_shiftx'. + +6.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:391ed386a5460bc01550bbd1e64ddee1e6666a82$paramod$35d43f283fa197ecd06c429c67def546fd6dc204\_90_shift_shiftx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$192. + dead port 2/2 on $mux $procmux$186. + dead port 2/2 on $mux $procmux$180. + dead port 2/2 on $mux $procmux$174. + dead port 2/2 on $mux $procmux$168. + dead port 2/2 on $mux $procmux$162. + dead port 2/2 on $mux $procmux$156. + dead port 2/2 on $mux $procmux$150. +Removed 8 multiplexer ports. + + +6.11. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:391ed386a5460bc01550bbd1e64ddee1e6666a82$paramod$35d43f283fa197ecd06c429c67def546fd6dc204\_90_shift_shiftx. + +Removed 0 unused cells and 13 unused wires. +Using template $paramod$constmap:391ed386a5460bc01550bbd1e64ddee1e6666a82$paramod$35d43f283fa197ecd06c429c67def546fd6dc204\_90_shift_shiftx for cells of type $shift. +Using extmapper simplemap for cells of type $or. +Using extmapper simplemap for cells of type $dff. +Using extmapper simplemap for cells of type $xor. +Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000100001 for cells of type $lcu. +Using extmapper simplemap for cells of type $pos. +Using extmapper simplemap for cells of type $mux. +Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000001010 for cells of type $fa. +Using template $paramod$484d51534650924b7ed4c69e46eed3a56904771f\_90_alu for cells of type $alu. +Using extmapper simplemap for cells of type $ne. +Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000001010 for cells of type $lcu. +No more expansions possible. + + +7. Executing ABC9 pass. + +7.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.2. Executing ABC9_OPS pass (helper functions for ABC9). + +7.3. Executing SCC pass (detecting logic loops). +Found 0 SCCs in module dynslice. +Found 0 SCCs. + +7.4. Executing ABC9_OPS pass (helper functions for ABC9). + +7.5. Executing PROC pass (convert processes to netlists). + +7.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +7.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +7.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 0 assignments to connections. + +7.5.4. Executing PROC_INIT pass (extract init attributes). + +7.5.5. Executing PROC_ARST pass (detect async resets in processes). + +7.5.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + +7.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). + +7.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +7.5.9. Executing PROC_DFF pass (convert process syncs to FFs). + +7.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +7.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +7.5.12. Executing OPT_EXPR pass (perform const folding). + +7.6. Executing TECHMAP pass (map to technology primitives). + +7.6.1. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/techmap.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +7.6.2. Continuing TECHMAP pass. +No more expansions possible. + + +7.7. Executing OPT pass (performing simple optimizations). + +7.7.1. Executing OPT_EXPR pass (perform const folding). + +7.7.2. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +7.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Removed 0 multiplexer ports. + +7.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +Performed a total of 0 changes. + +7.7.5. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +7.7.6. Executing OPT_DFF pass (perform DFF optimizations). + +7.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). + +7.7.8. Executing OPT_EXPR pass (perform const folding). + +7.7.9. Finished OPT passes. (There is nothing left to do.) + +7.8. Executing TECHMAP pass (map to technology primitives). + +7.8.1. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/abc9_map.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/abc9_map.v' to AST representation. +Successfully finished Verilog frontend. + +7.8.2. Continuing TECHMAP pass. +No more expansions possible. + + +7.9. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v' to AST representation. +Replacing existing blackbox module `$__ABC9_DELAY' at /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v:2.1-7.10. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Replacing existing blackbox module `$__ABC9_SCC_BREAKER' at /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v:9.1-11.10. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Replacing existing module `$__DFF_N__$abc9_flop' at /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v:14.1-20.10. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Replacing existing module `$__DFF_P__$abc9_flop' at /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v:23.1-29.10. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +7.10. Executing ABC9_OPS pass (helper functions for ABC9). + +7.11. Executing ABC9_OPS pass (helper functions for ABC9). + + +7.12. Executing AIGMAP pass (map logic to AIG). +Module dynslice: replaced 8167 cells with 56365 new cells, skipped 655 cells. + replaced 3 cell types: + 268 $_OR_ + 176 $_XOR_ + 7723 $_MUX_ + not replaced 3 cell types: + 171 $_NOT_ + 356 $_AND_ + 128 $_DFF_P_ + +7.12.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.12.2. Executing XAIGER backend. + +Extracted 24321 AND gates and 49969 wires from module `dynslice' to a netlist network with 159 inputs and 256 outputs. + +7.12.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.12.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 159/ 256 and = 2165 lev = 66 (32.94) mem = 0.03 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 159/ 256 and = 2065 lev = 38 (18.15) mem = 0.03 MB ch = 291 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 2065. Ch = 271. Total mem = 0.36 MB. Peak cut mem = 0.11 MB. +ABC: P: Del = 13.00. Ar = 751.0. Edge = 2433. Cut = 20031. T = 0.00 sec +ABC: P: Del = 13.00. Ar = 608.0. Edge = 2215. Cut = 16466. T = 0.00 sec +ABC: P: Del = 13.00. Ar = 591.0. Edge = 2034. Cut = 18539. T = 0.00 sec +ABC: F: Del = 13.00. Ar = 563.0. Edge = 1986. Cut = 15178. T = 0.00 sec +ABC: A: Del = 13.00. Ar = 549.0. Edge = 1873. Cut = 15729. T = 0.01 sec +ABC: A: Del = 13.00. Ar = 546.0. Edge = 1871. Cut = 15621. T = 0.00 sec +ABC: Total time = 0.03 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: + &ps -l +ABC: /input : i/o = 159/ 256 and = 1773 lev = 36 (17.47) mem = 0.03 MB box = 0 bb = 0 +ABC: Mapping (K=4) : lut = 542 edge = 1852 lev = 13 (6.46) mem = 0.02 MB +ABC: LUT = 542 : 2=72 13.3 % 3=172 31.7 % 4=298 55.0 % Ave = 3.42 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.56 seconds, total: 0.56 seconds + +7.12.5. Executing AIGER frontend. + +Removed 2538 unused cells and 3081 unused wires. + +7.12.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: $lut cells: 542 +ABC RESULTS: input signals: 4 +ABC RESULTS: output signals: 2 +Removing temp directory. + +7.13. Executing TECHMAP pass (map to technology primitives). + +7.13.1. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/abc9_unmap.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/abc9_unmap.v' to AST representation. +Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'. +Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'. +Successfully finished Verilog frontend. + +7.13.2. Continuing TECHMAP pass. +No more expansions possible. + +Removed 126 unused cells and 57060 unused wires. +Warning: Selection "abc9_test037" did not match any module. + +8. Executing CHECK pass (checking for obvious problems). +Checking module dynslice... +Found and reported 0 problems. + +-- Writing to `dynslice_syn0.v' using backend `verilog -noattr -noexpr -siminit' -- + +9. Executing Verilog backend. +Dumping module `$__ABC9_DELAY'. +Dumping module `$__ABC9_SCC_BREAKER'. +Dumping module `$__DFF_N__$abc9_flop'. +Dumping module `$__DFF_P__$abc9_flop'. +Dumping module `\dynslice'. + +Warnings: 1 unique messages, 1 total +End of script. Logfile hash: 4a98ef5f5c, CPU: user 1.21s system 0.05s, MEM: 107.92 MB peak +Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) +Time spent: 32% 1x abc9_exe (0 sec), 11% 5x clean (0 sec), ... ++ compile_and_run dynslice_tb_syn0 dynslice_out_syn0 dynslice_tb.v dynslice_syn0.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simlib.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simcells.v ++ exe=dynslice_tb_syn0 ++ output=dynslice_out_syn0 ++ shift 2 ++ '[' v == sv ']' ++ language_gen=-g2005 ++ false ++ false ++ iverilog -g2005 '-Doutfile="dynslice_out_syn0"' -s testbench -o dynslice_tb_syn0 dynslice_tb.v dynslice_syn0.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simlib.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simcells.v diff --git a/tests/simple_abc9/generate.err b/tests/simple_abc9/generate.err new file mode 100644 index 00000000000..a10ad226bcd --- /dev/null +++ b/tests/simple_abc9/generate.err @@ -0,0 +1,1589 @@ ++ body ++ cd generate.out +++ basename generate.v ++ fn=generate.v +++ basename generate ++ bn=generate ++ refext=v ++ rm -f generate_ref.fir ++ [[ v == \v ]] ++ egrep -v '^\s*`timescale' ../generate.v +egrep: warning: egrep is obsolescent; using grep -E ++ '[' '!' -f ../generate_tb.v ']' ++ /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../yosys -f 'verilog -noblackbox -specify -D_AUTOTB' -b 'test_autotb -n 300' -o generate_tb.v generate_ref.v + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2024 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) + +-- Parsing `generate_ref.v' using frontend `verilog -noblackbox -specify -D_AUTOTB' -- + +1. Executing Verilog-2005 frontend: generate_ref.v +Parsing Verilog input from `generate_ref.v' to AST representation. +Generating RTLIL representation for module `\gen_test1'. +Generating RTLIL representation for module `\gen_test2'. +Generating RTLIL representation for module `\gen_test3'. +Generating RTLIL representation for module `\gen_test4'. +Generating RTLIL representation for module `\gen_test5'. +Generating RTLIL representation for module `\gen_test6'. +Generating RTLIL representation for module `\gen_test7'. +Generating RTLIL representation for module `\gen_test8'. +Generating RTLIL representation for module `\gen_test9'. +Successfully finished Verilog frontend. + +-- Writing to `generate_tb.v' using backend `test_autotb -n 300' -- + +2. Executing TEST_AUTOTB backend (auto-generate pseudo-random test benches). +Generating test bench for module `\gen_test9'. +Generating test bench for module `\gen_test8'. +Generating test bench for module `\gen_test7'. +Generating test bench for module `\gen_test6'. +Generating test bench for module `\gen_test5'. +Generating test bench for module `\gen_test4'. +Generating test bench for module `\gen_test3'. +Generating test bench for module `\gen_test2'. +Generating test bench for module `\gen_test1'. + +End of script. Logfile hash: 1c78986cfe, CPU: user 0.18s system 0.01s, MEM: 22.41 MB peak +Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) +Time spent: 99% 1x read_verilog (0 sec), 0% 1x test_autotb (0 sec) ++ false ++ compile_and_run generate_tb_ref generate_out_ref generate_tb.v generate_ref.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simlib.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simcells.v ++ exe=generate_tb_ref ++ output=generate_out_ref ++ shift 2 ++ '[' v == sv ']' ++ language_gen=-g2005 ++ false ++ false ++ iverilog -g2005 '-Doutfile="generate_out_ref"' -s testbench -o generate_tb_ref generate_tb.v generate_ref.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simlib.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simcells.v +generate_ref.v:279: warning: Anachronistic use of named begin/end to surround generate schemes. +generate_ref.v:292: warning: Anachronistic use of named begin/end to surround generate schemes. +generate_ref.v:277: warning: Anachronistic use of named begin/end to surround generate schemes. ++ vvp -n generate_tb_ref +generate_tb.v:592: $finish called at 961800 (1s) ++ false ++ test_count=0 ++ '[' 'verilog -noblackbox -specify' = verific -o 'verilog -noblackbox -specify' = verific_gates ']' ++ '[' -n '' ']' ++ '[' -n ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' ']' ++ test_passes -f 'verilog -noblackbox -specify ' -p ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' generate_ref.v ++ /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../yosys -b 'verilog -noattr -noexpr -siminit' -o generate_syn0.v -f 'verilog -noblackbox -specify ' -p ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' generate_ref.v + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2024 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) + +-- Parsing `generate_ref.v' using frontend `verilog -noblackbox -specify ' -- + +1. Executing Verilog-2005 frontend: generate_ref.v +Parsing Verilog input from `generate_ref.v' to AST representation. +Generating RTLIL representation for module `\gen_test1'. +Generating RTLIL representation for module `\gen_test2'. +Generating RTLIL representation for module `\gen_test3'. +Generating RTLIL representation for module `\gen_test4'. +Generating RTLIL representation for module `\gen_test5'. +Generating RTLIL representation for module `\gen_test6'. +Generating RTLIL representation for module `\gen_test7'. +Generating RTLIL representation for module `\gen_test8'. +Generating RTLIL representation for module `\gen_test9'. +Successfully finished Verilog frontend. + +-- Running command ` read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' -- + +2. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v' to AST representation. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +3. Executing HIERARCHY pass (managing design hierarchy). + +4. Executing SYNTH pass. + +4.1. Executing PROC pass (convert processes to netlists). + +4.1.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +4.1.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 8 switch rules as full_case in process $proc$generate_ref.v:52$34 in module gen_test2. +Removed a total of 0 dead cases. + +4.1.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 33 assignments to connections. + +4.1.4. Executing PROC_INIT pass (extract init attributes). + +4.1.5. Executing PROC_ARST pass (detect async resets in processes). + +4.1.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +4.1.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\gen_test7.$proc$generate_ref.v:0$317'. +Creating decoders for process `\gen_test7.$proc$generate_ref.v:180$316'. +Creating decoders for process `\gen_test2.$proc$generate_ref.v:52$34'. + 1/8: $8\carry[8:8] + 2/8: $7\carry[7:7] + 3/8: $6\carry[6:6] + 4/8: $5\carry[5:5] + 5/8: $4\carry[4:4] + 6/8: $3\carry[3:3] + 7/8: $2\carry[2:2] + 8/8: $1\carry[1:1] +Creating decoders for process `\gen_test1.$proc$generate_ref.v:33$32'. +Creating decoders for process `\gen_test1.$proc$generate_ref.v:33$30'. +Creating decoders for process `\gen_test1.$proc$generate_ref.v:33$28'. +Creating decoders for process `\gen_test1.$proc$generate_ref.v:33$26'. +Creating decoders for process `\gen_test1.$proc$generate_ref.v:33$24'. +Creating decoders for process `\gen_test1.$proc$generate_ref.v:33$22'. +Creating decoders for process `\gen_test1.$proc$generate_ref.v:33$20'. +Creating decoders for process `\gen_test1.$proc$generate_ref.v:33$18'. + +4.1.8. Executing PROC_DLATCH pass (convert process syncs to latches). +No latch inferred for signal `\gen_test7.\out1' from process `\gen_test7.$proc$generate_ref.v:0$317'. +No latch inferred for signal `\gen_test7.\cond.sub_out1' from process `\gen_test7.$proc$generate_ref.v:0$317'. +No latch inferred for signal `\gen_test7.\cond.init.x' from process `\gen_test7.$proc$generate_ref.v:0$317'. +No latch inferred for signal `\gen_test7.\out2' from process `\gen_test7.$proc$generate_ref.v:180$316'. +No latch inferred for signal `\gen_test7.\cond.sub_out2' from process `\gen_test7.$proc$generate_ref.v:180$316'. +No latch inferred for signal `\gen_test7.\cond.proc.x' from process `\gen_test7.$proc$generate_ref.v:180$316'. + +4.1.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\gen_test2.\y' using process `\gen_test2.$proc$generate_ref.v:52$34'. + created $dff cell `$procdff$346' with positive edge clock. +Creating register for signal `\gen_test2.\i' using process `\gen_test2.$proc$generate_ref.v:52$34'. + created $dff cell `$procdff$347' with positive edge clock. +Creating register for signal `\gen_test2.\carry' using process `\gen_test2.$proc$generate_ref.v:52$34'. + created $dff cell `$procdff$348' with positive edge clock. +Creating register for signal `\gen_test1.\y [7]' using process `\gen_test1.$proc$generate_ref.v:33$32'. + created $dff cell `$procdff$349' with positive edge clock. +Creating register for signal `\gen_test1.\y [6]' using process `\gen_test1.$proc$generate_ref.v:33$30'. + created $dff cell `$procdff$350' with positive edge clock. +Creating register for signal `\gen_test1.\y [5]' using process `\gen_test1.$proc$generate_ref.v:33$28'. + created $dff cell `$procdff$351' with positive edge clock. +Creating register for signal `\gen_test1.\y [4]' using process `\gen_test1.$proc$generate_ref.v:33$26'. + created $dff cell `$procdff$352' with positive edge clock. +Creating register for signal `\gen_test1.\y [3]' using process `\gen_test1.$proc$generate_ref.v:33$24'. + created $dff cell `$procdff$353' with positive edge clock. +Creating register for signal `\gen_test1.\y [2]' using process `\gen_test1.$proc$generate_ref.v:33$22'. + created $dff cell `$procdff$354' with positive edge clock. +Creating register for signal `\gen_test1.\y [1]' using process `\gen_test1.$proc$generate_ref.v:33$20'. + created $dff cell `$procdff$355' with positive edge clock. +Creating register for signal `\gen_test1.\y [0]' using process `\gen_test1.$proc$generate_ref.v:33$18'. + created $dff cell `$procdff$356' with positive edge clock. + +4.1.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +4.1.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `gen_test7.$proc$generate_ref.v:0$317'. +Removing empty process `gen_test7.$proc$generate_ref.v:180$316'. +Found and cleaned up 8 empty switches in `\gen_test2.$proc$generate_ref.v:52$34'. +Removing empty process `gen_test2.$proc$generate_ref.v:52$34'. +Removing empty process `gen_test1.$proc$generate_ref.v:33$32'. +Removing empty process `gen_test1.$proc$generate_ref.v:33$30'. +Removing empty process `gen_test1.$proc$generate_ref.v:33$28'. +Removing empty process `gen_test1.$proc$generate_ref.v:33$26'. +Removing empty process `gen_test1.$proc$generate_ref.v:33$24'. +Removing empty process `gen_test1.$proc$generate_ref.v:33$22'. +Removing empty process `gen_test1.$proc$generate_ref.v:33$20'. +Removing empty process `gen_test1.$proc$generate_ref.v:33$18'. +Cleaned up 8 empty switches. + +4.1.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module gen_test9. + +Optimizing module gen_test8. + +Optimizing module gen_test7. +Optimizing module gen_test6. +Optimizing module gen_test5. +Optimizing module gen_test4. +Optimizing module gen_test3. +Optimizing module gen_test2. + +Optimizing module gen_test1. + +4.2. Executing OPT_EXPR pass (perform const folding). +Optimizing module gen_test9. +Optimizing module gen_test8. +Optimizing module gen_test7. +Optimizing module gen_test6. +Optimizing module gen_test5. +Optimizing module gen_test4. +Optimizing module gen_test3. +Optimizing module gen_test2. +Optimizing module gen_test1. + +4.3. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \gen_test9.. +Finding unused cells or wires in module \gen_test8.. +Finding unused cells or wires in module \gen_test7.. +Finding unused cells or wires in module \gen_test6.. +Finding unused cells or wires in module \gen_test5.. +Finding unused cells or wires in module \gen_test4.. +Finding unused cells or wires in module \gen_test3.. +Finding unused cells or wires in module \gen_test2.. +Finding unused cells or wires in module \gen_test1.. +Removed 2 unused cells and 327 unused wires. + + +4.4. Executing CHECK pass (checking for obvious problems). +Checking module gen_test1... +Checking module gen_test2... +Checking module gen_test3... +Checking module gen_test4... +Warning: Wire gen_test4.\b [3] is used but has no driver. +Checking module gen_test5... +Checking module gen_test6... +Checking module gen_test7... +Checking module gen_test8... +Checking module gen_test9... +Found and reported 1 problems. + +4.5. Executing OPT pass (performing simple optimizations). + +4.5.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module gen_test1. +Optimizing module gen_test2. +Optimizing module gen_test3. +Optimizing module gen_test4. +Optimizing module gen_test5. +Optimizing module gen_test6. +Optimizing module gen_test7. +Optimizing module gen_test8. +Optimizing module gen_test9. + +4.5.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\gen_test1'. +Finding identical cells in module `\gen_test2'. +Finding identical cells in module `\gen_test3'. +Finding identical cells in module `\gen_test4'. +Finding identical cells in module `\gen_test5'. +Finding identical cells in module `\gen_test6'. +Finding identical cells in module `\gen_test7'. +Finding identical cells in module `\gen_test8'. +Finding identical cells in module `\gen_test9'. +Removed a total of 0 cells. + +4.5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \gen_test1.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test2.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \gen_test3.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \gen_test4.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test5.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test6.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test7.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test8.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test9.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + + +4.5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \gen_test1. + Optimizing cells in module \gen_test2. + Optimizing cells in module \gen_test3. + Optimizing cells in module \gen_test4. + Optimizing cells in module \gen_test5. + Optimizing cells in module \gen_test6. + Optimizing cells in module \gen_test7. + Optimizing cells in module \gen_test8. + Optimizing cells in module \gen_test9. +Performed a total of 0 changes. + +4.5.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\gen_test1'. +Finding identical cells in module `\gen_test2'. +Finding identical cells in module `\gen_test3'. + +Finding identical cells in module `\gen_test4'. +Finding identical cells in module `\gen_test5'. +Finding identical cells in module `\gen_test6'. +Finding identical cells in module `\gen_test7'. +Finding identical cells in module `\gen_test8'. +Finding identical cells in module `\gen_test9'. +Removed a total of 2 cells. + +4.5.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.5.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \gen_test1.. +Finding unused cells or wires in module \gen_test2.. +Finding unused cells or wires in module \gen_test3.. +Finding unused cells or wires in module \gen_test4.. +Finding unused cells or wires in module \gen_test5.. +Finding unused cells or wires in module \gen_test6.. +Finding unused cells or wires in module \gen_test7.. +Finding unused cells or wires in module \gen_test8.. +Finding unused cells or wires in module \gen_test9.. + +4.5.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module gen_test1. +Optimizing module gen_test2. +Optimizing module gen_test3. +Optimizing module gen_test4. +Optimizing module gen_test5. +Optimizing module gen_test6. +Optimizing module gen_test7. +Optimizing module gen_test8. +Optimizing module gen_test9. + +4.5.9. Rerunning OPT passes. (Maybe there is more to do..) + +4.5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \gen_test1.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test2.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \gen_test3.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \gen_test4.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test5.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test6.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test7.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test8.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test9.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + + +4.5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \gen_test1. + Optimizing cells in module \gen_test2. + Optimizing cells in module \gen_test3. + Optimizing cells in module \gen_test4. + Optimizing cells in module \gen_test5. + Optimizing cells in module \gen_test6. + Optimizing cells in module \gen_test7. + Optimizing cells in module \gen_test8. + Optimizing cells in module \gen_test9. +Performed a total of 0 changes. + +4.5.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\gen_test1'. +Finding identical cells in module `\gen_test2'. +Finding identical cells in module `\gen_test3'. +Finding identical cells in module `\gen_test4'. +Finding identical cells in module `\gen_test5'. +Finding identical cells in module `\gen_test6'. +Finding identical cells in module `\gen_test7'. +Finding identical cells in module `\gen_test8'. +Finding identical cells in module `\gen_test9'. +Removed a total of 0 cells. + +4.5.13. Executing OPT_DFF pass (perform DFF optimizations). + +4.5.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \gen_test1.. +Finding unused cells or wires in module \gen_test2.. +Finding unused cells or wires in module \gen_test3.. +Finding unused cells or wires in module \gen_test4.. +Finding unused cells or wires in module \gen_test5.. +Finding unused cells or wires in module \gen_test6.. +Finding unused cells or wires in module \gen_test7.. +Finding unused cells or wires in module \gen_test8.. +Finding unused cells or wires in module \gen_test9.. + +4.5.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module gen_test1. +Optimizing module gen_test2. +Optimizing module gen_test3. +Optimizing module gen_test4. +Optimizing module gen_test5. +Optimizing module gen_test6. +Optimizing module gen_test7. +Optimizing module gen_test8. +Optimizing module gen_test9. + +4.5.16. Finished OPT passes. (There is nothing left to do.) + +4.6. Executing FSM pass (extract and optimize FSM). + +4.6.1. Executing FSM_DETECT pass (finding FSMs in design). + +4.6.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +4.6.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.6.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \gen_test1.. +Finding unused cells or wires in module \gen_test2.. +Finding unused cells or wires in module \gen_test3.. +Finding unused cells or wires in module \gen_test4.. +Finding unused cells or wires in module \gen_test5.. +Finding unused cells or wires in module \gen_test6.. +Finding unused cells or wires in module \gen_test7.. +Finding unused cells or wires in module \gen_test8.. +Finding unused cells or wires in module \gen_test9.. + +4.6.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.6.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +4.6.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +4.6.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +4.7. Executing OPT pass (performing simple optimizations). + +4.7.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module gen_test1. +Optimizing module gen_test2. +Optimizing module gen_test3. +Optimizing module gen_test4. +Optimizing module gen_test5. +Optimizing module gen_test6. +Optimizing module gen_test7. +Optimizing module gen_test8. +Optimizing module gen_test9. + +4.7.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\gen_test1'. +Finding identical cells in module `\gen_test2'. +Finding identical cells in module `\gen_test3'. +Finding identical cells in module `\gen_test4'. +Finding identical cells in module `\gen_test5'. +Finding identical cells in module `\gen_test6'. +Finding identical cells in module `\gen_test7'. +Finding identical cells in module `\gen_test8'. +Finding identical cells in module `\gen_test9'. +Removed a total of 0 cells. + +4.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \gen_test1.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test2.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \gen_test3.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \gen_test4.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test5.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test6.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test7.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test8.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test9.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + + +4.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \gen_test1. + Optimizing cells in module \gen_test2. + Optimizing cells in module \gen_test3. + Optimizing cells in module \gen_test4. + Optimizing cells in module \gen_test5. + Optimizing cells in module \gen_test6. + Optimizing cells in module \gen_test7. + Optimizing cells in module \gen_test8. + Optimizing cells in module \gen_test9. +Performed a total of 0 changes. + +4.7.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\gen_test1'. +Finding identical cells in module `\gen_test2'. +Finding identical cells in module `\gen_test3'. +Finding identical cells in module `\gen_test4'. +Finding identical cells in module `\gen_test5'. +Finding identical cells in module `\gen_test6'. +Finding identical cells in module `\gen_test7'. +Finding identical cells in module `\gen_test8'. +Finding identical cells in module `\gen_test9'. +Removed a total of 0 cells. + +4.7.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \gen_test1.. +Finding unused cells or wires in module \gen_test2.. +Finding unused cells or wires in module \gen_test3.. +Finding unused cells or wires in module \gen_test4.. +Finding unused cells or wires in module \gen_test5.. +Finding unused cells or wires in module \gen_test6.. +Finding unused cells or wires in module \gen_test7.. +Finding unused cells or wires in module \gen_test8.. +Finding unused cells or wires in module \gen_test9.. + +4.7.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module gen_test1. +Optimizing module gen_test2. +Optimizing module gen_test3. +Optimizing module gen_test4. +Optimizing module gen_test5. +Optimizing module gen_test6. +Optimizing module gen_test7. +Optimizing module gen_test8. +Optimizing module gen_test9. + +4.7.9. Finished OPT passes. (There is nothing left to do.) + +4.8. Executing WREDUCE pass (reducing word size of cells). + +4.9. Executing PEEPOPT pass (run peephole optimizers). + +4.10. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \gen_test1.. +Finding unused cells or wires in module \gen_test2.. +Finding unused cells or wires in module \gen_test3.. +Finding unused cells or wires in module \gen_test4.. +Finding unused cells or wires in module \gen_test5.. +Finding unused cells or wires in module \gen_test6.. +Finding unused cells or wires in module \gen_test7.. +Finding unused cells or wires in module \gen_test8.. +Finding unused cells or wires in module \gen_test9.. + +4.11. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module gen_test1: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module gen_test2: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module gen_test3: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module gen_test4: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module gen_test5: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module gen_test6: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module gen_test7: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module gen_test8: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module gen_test9: + created 0 $alu and 0 $macc cells. + +4.12. Executing SHARE pass (SAT-based resource sharing). + +4.13. Executing OPT pass (performing simple optimizations). + +4.13.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module gen_test1. +Optimizing module gen_test2. +Optimizing module gen_test3. +Optimizing module gen_test4. +Optimizing module gen_test5. +Optimizing module gen_test6. +Optimizing module gen_test7. +Optimizing module gen_test8. +Optimizing module gen_test9. + +4.13.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\gen_test1'. +Finding identical cells in module `\gen_test2'. +Finding identical cells in module `\gen_test3'. +Finding identical cells in module `\gen_test4'. +Finding identical cells in module `\gen_test5'. +Finding identical cells in module `\gen_test6'. +Finding identical cells in module `\gen_test7'. +Finding identical cells in module `\gen_test8'. +Finding identical cells in module `\gen_test9'. +Removed a total of 0 cells. + +4.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \gen_test1.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test2.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \gen_test3.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \gen_test4.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test5.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test6.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test7.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test8.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test9.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + + +4.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \gen_test1. + Optimizing cells in module \gen_test2. + Optimizing cells in module \gen_test3. + Optimizing cells in module \gen_test4. + Optimizing cells in module \gen_test5. + Optimizing cells in module \gen_test6. + Optimizing cells in module \gen_test7. + Optimizing cells in module \gen_test8. + Optimizing cells in module \gen_test9. +Performed a total of 0 changes. + +4.13.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\gen_test1'. +Finding identical cells in module `\gen_test2'. +Finding identical cells in module `\gen_test3'. +Finding identical cells in module `\gen_test4'. +Finding identical cells in module `\gen_test5'. +Finding identical cells in module `\gen_test6'. +Finding identical cells in module `\gen_test7'. +Finding identical cells in module `\gen_test8'. +Finding identical cells in module `\gen_test9'. +Removed a total of 0 cells. + +4.13.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \gen_test1.. +Finding unused cells or wires in module \gen_test2.. +Finding unused cells or wires in module \gen_test3.. +Finding unused cells or wires in module \gen_test4.. +Finding unused cells or wires in module \gen_test5.. +Finding unused cells or wires in module \gen_test6.. +Finding unused cells or wires in module \gen_test7.. +Finding unused cells or wires in module \gen_test8.. +Finding unused cells or wires in module \gen_test9.. + +4.13.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module gen_test1. +Optimizing module gen_test2. +Optimizing module gen_test3. +Optimizing module gen_test4. +Optimizing module gen_test5. +Optimizing module gen_test6. +Optimizing module gen_test7. +Optimizing module gen_test8. +Optimizing module gen_test9. + +4.13.9. Finished OPT passes. (There is nothing left to do.) + +4.14. Executing MEMORY pass. + +4.14.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +4.14.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +4.14.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + +4.14.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +4.14.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). + +4.14.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \gen_test1.. +Finding unused cells or wires in module \gen_test2.. +Finding unused cells or wires in module \gen_test3.. +Finding unused cells or wires in module \gen_test4.. +Finding unused cells or wires in module \gen_test5.. +Finding unused cells or wires in module \gen_test6.. +Finding unused cells or wires in module \gen_test7.. +Finding unused cells or wires in module \gen_test8.. +Finding unused cells or wires in module \gen_test9.. + +4.14.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +4.14.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +4.14.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \gen_test1.. +Finding unused cells or wires in module \gen_test2.. +Finding unused cells or wires in module \gen_test3.. +Finding unused cells or wires in module \gen_test4.. +Finding unused cells or wires in module \gen_test5.. +Finding unused cells or wires in module \gen_test6.. +Finding unused cells or wires in module \gen_test7.. +Finding unused cells or wires in module \gen_test8.. +Finding unused cells or wires in module \gen_test9.. + +4.14.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +4.15. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \gen_test1.. +Finding unused cells or wires in module \gen_test2.. +Finding unused cells or wires in module \gen_test3.. +Finding unused cells or wires in module \gen_test4.. +Finding unused cells or wires in module \gen_test5.. +Finding unused cells or wires in module \gen_test6.. +Finding unused cells or wires in module \gen_test7.. +Finding unused cells or wires in module \gen_test8.. +Finding unused cells or wires in module \gen_test9.. + +5. Executing OPT pass (performing simple optimizations). + +5.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module gen_test1. +Optimizing module gen_test2. + +Optimizing module gen_test3. +Optimizing module gen_test4. + +Optimizing module gen_test5. +Optimizing module gen_test6. +Optimizing module gen_test7. +Optimizing module gen_test8. +Optimizing module gen_test9. + +5.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\gen_test1'. +Finding identical cells in module `\gen_test2'. +Finding identical cells in module `\gen_test3'. +Finding identical cells in module `\gen_test4'. +Finding identical cells in module `\gen_test5'. +Finding identical cells in module `\gen_test6'. +Finding identical cells in module `\gen_test7'. +Finding identical cells in module `\gen_test8'. +Finding identical cells in module `\gen_test9'. +Removed a total of 0 cells. + +5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \gen_test1.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test2.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test3.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \gen_test4.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test5.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test6.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test7.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test8.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test9.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + + +5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \gen_test1. + Optimizing cells in module \gen_test2. + Optimizing cells in module \gen_test3. + Optimizing cells in module \gen_test4. + Optimizing cells in module \gen_test5. + Optimizing cells in module \gen_test6. + Optimizing cells in module \gen_test7. + Optimizing cells in module \gen_test8. + Optimizing cells in module \gen_test9. +Performed a total of 0 changes. + +5.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\gen_test1'. +Finding identical cells in module `\gen_test2'. +Finding identical cells in module `\gen_test3'. +Finding identical cells in module `\gen_test4'. +Finding identical cells in module `\gen_test5'. +Finding identical cells in module `\gen_test6'. +Finding identical cells in module `\gen_test7'. +Finding identical cells in module `\gen_test8'. +Finding identical cells in module `\gen_test9'. +Removed a total of 0 cells. + +5.6. Executing OPT_SHARE pass. + +5.7. Executing OPT_DFF pass (perform DFF optimizations). + +5.8. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \gen_test1.. +Finding unused cells or wires in module \gen_test2.. +Finding unused cells or wires in module \gen_test3.. +Finding unused cells or wires in module \gen_test4.. +Finding unused cells or wires in module \gen_test5.. +Finding unused cells or wires in module \gen_test6.. +Finding unused cells or wires in module \gen_test7.. +Finding unused cells or wires in module \gen_test8.. +Finding unused cells or wires in module \gen_test9.. +Removed 0 unused cells and 8 unused wires. + + +5.9. Executing OPT_EXPR pass (perform const folding). +Optimizing module gen_test1. +Optimizing module gen_test2. +Optimizing module gen_test3. +Optimizing module gen_test4. +Optimizing module gen_test5. +Optimizing module gen_test6. +Optimizing module gen_test7. +Optimizing module gen_test8. +Optimizing module gen_test9. + +5.10. Rerunning OPT passes. (Maybe there is more to do..) + +5.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \gen_test1.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test2.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test3.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \gen_test4.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test5.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test6.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test7.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test8.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \gen_test9.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + + +5.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \gen_test1. + Optimizing cells in module \gen_test2. + Optimizing cells in module \gen_test3. + Optimizing cells in module \gen_test4. + Optimizing cells in module \gen_test5. + Optimizing cells in module \gen_test6. + Optimizing cells in module \gen_test7. + Optimizing cells in module \gen_test8. + Optimizing cells in module \gen_test9. +Performed a total of 0 changes. + +5.13. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\gen_test1'. +Finding identical cells in module `\gen_test2'. +Finding identical cells in module `\gen_test3'. +Finding identical cells in module `\gen_test4'. +Finding identical cells in module `\gen_test5'. +Finding identical cells in module `\gen_test6'. +Finding identical cells in module `\gen_test7'. +Finding identical cells in module `\gen_test8'. +Finding identical cells in module `\gen_test9'. +Removed a total of 0 cells. + +5.14. Executing OPT_SHARE pass. + +5.15. Executing OPT_DFF pass (perform DFF optimizations). + +5.16. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \gen_test1.. +Finding unused cells or wires in module \gen_test2.. +Finding unused cells or wires in module \gen_test3.. +Finding unused cells or wires in module \gen_test4.. +Finding unused cells or wires in module \gen_test5.. +Finding unused cells or wires in module \gen_test6.. +Finding unused cells or wires in module \gen_test7.. +Finding unused cells or wires in module \gen_test8.. +Finding unused cells or wires in module \gen_test9.. + +5.17. Executing OPT_EXPR pass (perform const folding). +Optimizing module gen_test1. +Optimizing module gen_test2. +Optimizing module gen_test3. +Optimizing module gen_test4. +Optimizing module gen_test5. +Optimizing module gen_test6. +Optimizing module gen_test7. +Optimizing module gen_test8. +Optimizing module gen_test9. + +5.18. Finished OPT passes. (There is nothing left to do.) + +6. Executing TECHMAP pass (map to technology primitives). + +6.1. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/techmap.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +6.2. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $and. +Using extmapper simplemap for cells of type $mux. +Using extmapper simplemap for cells of type $xor. +Using extmapper simplemap for cells of type $eq. +Using extmapper simplemap for cells of type $reduce_or. +Using extmapper simplemap for cells of type $dff. +Using extmapper simplemap for cells of type $or. +Using extmapper simplemap for cells of type $reduce_xor. +No more expansions possible. + + +7. Executing ABC9 pass. + +7.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.2. Executing ABC9_OPS pass (helper functions for ABC9). + +7.3. Executing SCC pass (detecting logic loops). +Found 0 SCCs in module gen_test1. +Found 0 SCCs in module gen_test2. +Found 0 SCCs in module gen_test3. +Found 0 SCCs in module gen_test4. +Found 0 SCCs in module gen_test5. +Found 0 SCCs in module gen_test6. +Found 0 SCCs in module gen_test7. +Found 0 SCCs in module gen_test8. +Found 0 SCCs in module gen_test9. +Found 0 SCCs. + +7.4. Executing ABC9_OPS pass (helper functions for ABC9). + +7.5. Executing PROC pass (convert processes to netlists). + +7.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +7.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +7.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 0 assignments to connections. + +7.5.4. Executing PROC_INIT pass (extract init attributes). + +7.5.5. Executing PROC_ARST pass (detect async resets in processes). + +7.5.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + +7.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). + +7.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +7.5.9. Executing PROC_DFF pass (convert process syncs to FFs). + +7.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +7.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +7.5.12. Executing OPT_EXPR pass (perform const folding). + +7.6. Executing TECHMAP pass (map to technology primitives). + +7.6.1. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/techmap.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +7.6.2. Continuing TECHMAP pass. +No more expansions possible. + + +7.7. Executing OPT pass (performing simple optimizations). + +7.7.1. Executing OPT_EXPR pass (perform const folding). + +7.7.2. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +7.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Removed 0 multiplexer ports. + +7.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +Performed a total of 0 changes. + +7.7.5. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +7.7.6. Executing OPT_DFF pass (perform DFF optimizations). + +7.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). + +7.7.8. Executing OPT_EXPR pass (perform const folding). + +7.7.9. Finished OPT passes. (There is nothing left to do.) + +7.8. Executing TECHMAP pass (map to technology primitives). + +7.8.1. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/abc9_map.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/abc9_map.v' to AST representation. +Successfully finished Verilog frontend. + +7.8.2. Continuing TECHMAP pass. +No more expansions possible. + + +7.9. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v' to AST representation. +Replacing existing blackbox module `$__ABC9_DELAY' at /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v:2.1-7.10. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Replacing existing blackbox module `$__ABC9_SCC_BREAKER' at /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v:9.1-11.10. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Replacing existing module `$__DFF_N__$abc9_flop' at /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v:14.1-20.10. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Replacing existing module `$__DFF_P__$abc9_flop' at /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v:23.1-29.10. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +7.10. Executing ABC9_OPS pass (helper functions for ABC9). + +7.11. Executing ABC9_OPS pass (helper functions for ABC9). + + +7.12. Executing AIGMAP pass (map logic to AIG). +Module gen_test1: replaced 40 cells with 256 new cells, skipped 16 cells. + replaced 2 cell types: + 8 $_OR_ + 32 $_XOR_ + not replaced 2 cell types: + 8 $_AND_ + 8 $_DFF_P_ +Module gen_test2: replaced 95 cells with 557 new cells, skipped 31 cells. + replaced 2 cell types: + 36 $_OR_ + 59 $_XOR_ + not replaced 2 cell types: + 22 $_NOT_ + 9 $_DFF_P_ +Module gen_test3: replaced 6 cells with 42 new cells, skipped 0 cells. + replaced 1 cell types: + 6 $_MUX_ +Module gen_test4: replaced 0 cells with 0 new cells, skipped 2 cells. + not replaced 1 cell types: + 2 $_AND_ +Module gen_test5: replaced 0 cells with 0 new cells, skipped 255 cells. + not replaced 1 cell types: + 255 $_AND_ + +7.12.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.12.2. Executing XAIGER backend. + +Extracted 112 AND gates and 299 wires from module `gen_test1' to a netlist network with 25 inputs and 16 outputs. + +7.12.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.12.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 25/ 16 and = 100 lev = 7 (3.50) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 25/ 16 and = 128 lev = 7 (3.25) mem = 0.00 MB ch = 12 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 128. Ch = 12. Total mem = 0.02 MB. Peak cut mem = 0.01 MB. +ABC: P: Del = 2.00. Ar = 22.0. Edge = 68. Cut = 1392. T = 0.00 sec +ABC: P: Del = 2.00. Ar = 22.0. Edge = 72. Cut = 1286. T = 0.00 sec +ABC: P: Del = 2.00. Ar = 22.0. Edge = 72. Cut = 1302. T = 0.00 sec +ABC: F: Del = 2.00. Ar = 18.0. Edge = 64. Cut = 1050. T = 0.00 sec +ABC: A: Del = 2.00. Ar = 18.0. Edge = 64. Cut = 946. T = 0.00 sec +ABC: A: Del = 2.00. Ar = 18.0. Edge = 64. Cut = 942. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 25/ 16 and = 98 lev = 7 (3.25) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=4) : lut = 18 edge = 64 lev = 2 (1.00) mem = 0.00 MB +ABC: LUT = 18 : 2=4 22.2 % 3=0 0.0 % 4=14 77.8 % Ave = 3.56 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.01 seconds, total: 0.01 seconds + +7.12.5. Executing AIGER frontend. + +Removed 186 unused cells and 227 unused wires. + +7.12.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: $lut cells: 18 +ABC RESULTS: input signals: 3 +ABC RESULTS: output signals: 9 +Removing temp directory. + +7.12.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.12.2. Executing XAIGER backend. + +Extracted 213 AND gates and 616 wires from module `gen_test2' to a netlist network with 26 inputs and 18 outputs. + +7.12.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.12.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 26/ 18 and = 73 lev = 22 (6.06) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 26/ 18 and = 94 lev = 15 (4.50) mem = 0.00 MB ch = 14 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 94. Ch = 14. Total mem = 0.02 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 5.00. Ar = 23.0. Edge = 64. Cut = 906. T = 0.00 sec +ABC: P: Del = 5.00. Ar = 23.0. Edge = 70. Cut = 824. T = 0.00 sec +ABC: P: Del = 5.00. Ar = 22.0. Edge = 67. Cut = 904. T = 0.00 sec +ABC: F: Del = 5.00. Ar = 21.0. Edge = 64. Cut = 697. T = 0.00 sec +ABC: A: Del = 5.00. Ar = 19.0. Edge = 60. Cut = 704. T = 0.00 sec +ABC: A: Del = 5.00. Ar = 19.0. Edge = 60. Cut = 694. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 26/ 18 and = 85 lev = 15 (4.50) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=4) : lut = 19 edge = 60 lev = 5 (1.61) mem = 0.00 MB +ABC: LUT = 19 : 2=5 26.3 % 3=6 31.6 % 4=8 42.1 % Ave = 3.16 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.01 seconds, total: 0.01 seconds + +7.12.5. Executing AIGER frontend. + +Removed 157 unused cells and 210 unused wires. + +7.12.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: $lut cells: 19 +ABC RESULTS: input signals: 3 +ABC RESULTS: output signals: 3 +Removing temp directory. + +7.12.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.12.2. Executing XAIGER backend. + +Extracted 18 AND gates and 55 wires from module `gen_test3' to a netlist network with 9 inputs and 8 outputs. + +7.12.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.12.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 9/ 8 and = 18 lev = 2 (2.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 9/ 8 and = 36 lev = 2 (2.00) mem = 0.00 MB ch = 6 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 36. Ch = 6. Total mem = 0.01 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 1.00. Ar = 6.0. Edge = 18. Cut = 72. T = 0.00 sec +ABC: P: Del = 1.00. Ar = 6.0. Edge = 18. Cut = 72. T = 0.00 sec +ABC: P: Del = 1.00. Ar = 6.0. Edge = 18. Cut = 72. T = 0.00 sec +ABC: F: Del = 1.00. Ar = 6.0. Edge = 18. Cut = 72. T = 0.00 sec +ABC: A: Del = 1.00. Ar = 6.0. Edge = 18. Cut = 72. T = 0.00 sec +ABC: A: Del = 1.00. Ar = 6.0. Edge = 18. Cut = 72. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 9/ 8 and = 18 lev = 2 (2.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=3) : lut = 6 edge = 18 lev = 1 (1.00) mem = 0.00 MB +ABC: LUT = 6 : 2=0 0.0 % 3=6 100.0 % Ave = 3.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.01 seconds, total: 0.01 seconds + +7.12.5. Executing AIGER frontend. + +Removed 25 unused cells and 40 unused wires. + +7.12.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: $lut cells: 6 +ABC RESULTS: input signals: 3 +ABC RESULTS: output signals: 2 +Removing temp directory. + +7.12.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.12.2. Executing XAIGER backend. + +Extracted 2 AND gates and 12 wires from module `gen_test4' to a netlist network with 4 inputs and 4 outputs. + +7.12.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.12.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 4/ 4 and = 2 lev = 2 (0.75) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 4/ 4 and = 2 lev = 2 (0.75) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 2. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 1.00. Ar = 2.0. Edge = 5. Cut = 3. T = 0.00 sec +ABC: P: Del = 1.00. Ar = 2.0. Edge = 5. Cut = 3. T = 0.00 sec +ABC: P: Del = 1.00. Ar = 2.0. Edge = 5. Cut = 3. T = 0.00 sec +ABC: F: Del = 1.00. Ar = 2.0. Edge = 5. Cut = 3. T = 0.00 sec +ABC: A: Del = 1.00. Ar = 2.0. Edge = 5. Cut = 3. T = 0.00 sec +ABC: A: Del = 1.00. Ar = 2.0. Edge = 5. Cut = 3. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 4/ 4 and = 3 lev = 2 (0.75) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=3) : lut = 2 edge = 5 lev = 1 (0.50) mem = 0.00 MB +ABC: LUT = 2 : 2=1 50.0 % 3=1 50.0 % Ave = 2.50 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.00 seconds, total: 0.00 seconds + +7.12.5. Executing AIGER frontend. + +Removed 1 unused cells and 8 unused wires. + +7.12.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: $lut cells: 2 +ABC RESULTS: input signals: 1 +ABC RESULTS: output signals: 1 +Removing temp directory. + +7.12.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.12.2. Executing XAIGER backend. + +Extracted 255 AND gates and 514 wires from module `gen_test5' to a netlist network with 256 inputs and 1 outputs. + +7.12.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.12.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 256/ 1 and = 255 lev = 12 (12.00) mem = 0.01 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 256/ 1 and = 255 lev = 8 (8.00) mem = 0.01 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 255. Ch = 0. Total mem = 0.07 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 4.00. Ar = 85.0. Edge = 340. Cut = 888. T = 0.00 sec +ABC: P: Del = 4.00. Ar = 85.0. Edge = 340. Cut = 888. T = 0.00 sec +ABC: P: Del = 4.00. Ar = 85.0. Edge = 340. Cut = 888. T = 0.00 sec +ABC: F: Del = 4.00. Ar = 85.0. Edge = 340. Cut = 510. T = 0.00 sec +ABC: A: Del = 4.00. Ar = 85.0. Edge = 340. Cut = 510. T = 0.00 sec +ABC: A: Del = 4.00. Ar = 85.0. Edge = 340. Cut = 510. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 256/ 1 and = 255 lev = 8 (8.00) mem = 0.01 MB box = 0 bb = 0 +ABC: Mapping (K=4) : lut = 85 edge = 340 lev = 4 (4.00) mem = 0.00 MB +ABC: LUT = 85 : 2=0 0.0 % 3=0 0.0 % 4=85 100.0 % Ave = 4.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.03 seconds, total: 0.03 seconds + +7.12.5. Executing AIGER frontend. + +Removed 170 unused cells and 427 unused wires. + +7.12.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: $lut cells: 85 +ABC RESULTS: input signals: 1 +ABC RESULTS: output signals: 1 +Removing temp directory. + +7.12.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.12.2. Executing XAIGER backend. + +Extracted 0 AND gates and 6 wires from module `gen_test6' to a netlist network with 0 inputs and 4 outputs. + +7.12.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.12.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 0/ 4 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 0/ 4 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = -100000000.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = -100000000.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = -100000000.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = -100000000.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = -100000000.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = -100000000.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 0/ 4 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.00 seconds, total: 0.00 seconds + +7.12.5. Executing AIGER frontend. + +Removed 0 unused cells and 1 unused wires. + +7.12.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: input signals: 0 +ABC RESULTS: output signals: 1 +Removing temp directory. + +7.12.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.12.2. Executing XAIGER backend. + +Extracted 0 AND gates and 2 wires from module `gen_test7' to a netlist network with 0 inputs and 0 outputs. +Don't call ABC as there is nothing to map. +Removing temp directory. + +7.12.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.12.2. Executing XAIGER backend. + +Extracted 0 AND gates and 2 wires from module `gen_test8' to a netlist network with 0 inputs and 0 outputs. +Don't call ABC as there is nothing to map. +Removing temp directory. + +7.12.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.12.2. Executing XAIGER backend. + +Extracted 0 AND gates and 2 wires from module `gen_test9' to a netlist network with 0 inputs and 0 outputs. +Don't call ABC as there is nothing to map. +Removing temp directory. + +7.13. Executing TECHMAP pass (map to technology primitives). + +7.13.1. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/abc9_unmap.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/abc9_unmap.v' to AST representation. +Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'. +Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'. +Successfully finished Verilog frontend. + +7.13.2. Continuing TECHMAP pass. +No more expansions possible. + +Removed 16 unused cells and 1774 unused wires. +Warning: Selection "abc9_test037" did not match any module. + +8. Executing CHECK pass (checking for obvious problems). +Checking module gen_test1... +Checking module gen_test2... +Checking module gen_test3... +Checking module gen_test4... +Checking module gen_test5... +Checking module gen_test6... +Checking module gen_test7... +Checking module gen_test8... +Checking module gen_test9... +Found and reported 0 problems. + +-- Writing to `generate_syn0.v' using backend `verilog -noattr -noexpr -siminit' -- + +9. Executing Verilog backend. +Dumping module `$__ABC9_DELAY'. +Dumping module `$__ABC9_SCC_BREAKER'. +Dumping module `$__DFF_N__$abc9_flop'. +Dumping module `$__DFF_P__$abc9_flop'. +Dumping module `\gen_test1'. +Dumping module `\gen_test2'. +Dumping module `\gen_test3'. +Dumping module `\gen_test4'. +Dumping module `\gen_test5'. +Dumping module `\gen_test6'. +Dumping module `\gen_test7'. +Dumping module `\gen_test8'. +Dumping module `\gen_test9'. + +Warnings: 2 unique messages, 2 total +End of script. Logfile hash: 9d73bd81e6, CPU: user 0.56s system 0.01s, MEM: 27.73 MB peak +Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) +Time spent: 35% 6x abc9_exe (0 sec), 19% 9x read_verilog (0 sec), ... ++ compile_and_run generate_tb_syn0 generate_out_syn0 generate_tb.v generate_syn0.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simlib.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simcells.v ++ exe=generate_tb_syn0 ++ output=generate_out_syn0 ++ shift 2 ++ '[' v == sv ']' ++ language_gen=-g2005 ++ false ++ false ++ iverilog -g2005 '-Doutfile="generate_out_syn0"' -s testbench -o generate_tb_syn0 generate_tb.v generate_syn0.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simlib.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simcells.v diff --git a/tests/simple_abc9/memory.err b/tests/simple_abc9/memory.err new file mode 100644 index 00000000000..89a9b51c35d --- /dev/null +++ b/tests/simple_abc9/memory.err @@ -0,0 +1,3096 @@ ++ body ++ cd memory.out +++ basename memory.v ++ fn=memory.v +++ basename memory ++ bn=memory ++ refext=v ++ rm -f memory_ref.fir ++ [[ v == \v ]] ++ egrep -v '^\s*`timescale' ../memory.v +egrep: warning: egrep is obsolescent; using grep -E ++ '[' '!' -f ../memory_tb.v ']' ++ /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../yosys -f 'verilog -noblackbox -specify -D_AUTOTB' -b 'test_autotb -n 300' -o memory_tb.v memory_ref.v + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2024 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) + +-- Parsing `memory_ref.v' using frontend `verilog -noblackbox -specify -D_AUTOTB' -- + +1. Executing Verilog-2005 frontend: memory_ref.v +Parsing Verilog input from `memory_ref.v' to AST representation. +Lexer warning: The SystemVerilog keyword `bit' (at memory_ref.v:39) is not recognized unless read_verilog is called with -sv! +Lexer warning: The SystemVerilog keyword `bit' (at memory_ref.v:43) is not recognized unless read_verilog is called with -sv! +Lexer warning: The SystemVerilog keyword `bit' (at memory_ref.v:70) is not recognized unless read_verilog is called with -sv! +Lexer warning: The SystemVerilog keyword `bit' (at memory_ref.v:71) is not recognized unless read_verilog is called with -sv! +Lexer warning: The SystemVerilog keyword `bit' (at memory_ref.v:74) is not recognized unless read_verilog is called with -sv! +Lexer warning: The SystemVerilog keyword `bit' (at memory_ref.v:75) is not recognized unless read_verilog is called with -sv! +Generating RTLIL representation for module `\memtest00'. +Warning: Replacing memory \mem with list of registers. See memory_ref.v:9 +Generating RTLIL representation for module `\memtest01'. +Generating RTLIL representation for module `\memtest02'. +Generating RTLIL representation for module `\memtest03'. +Generating RTLIL representation for module `\memtest04'. +Generating RTLIL representation for module `\memtest05'. +Generating RTLIL representation for module `\memtest06_sync'. +Generating RTLIL representation for module `\memtest06_async'. +Warning: Replacing memory \test with list of registers. See memory_ref.v:177 +Generating RTLIL representation for module `\memtest07'. +Generating RTLIL representation for module `\memtest08'. +Generating RTLIL representation for module `\memtest09'. +Generating RTLIL representation for module `\memtest10'. +Warning: Replacing memory \queue with list of registers. See memory_ref.v:249 +Generating RTLIL representation for module `\memtest11'. +Generating RTLIL representation for module `\memtest12'. +Generating RTLIL representation for module `\memtest13'. +Successfully finished Verilog frontend. + +-- Writing to `memory_tb.v' using backend `test_autotb -n 300' -- + +2. Executing TEST_AUTOTB backend (auto-generate pseudo-random test benches). +Generating test bench for module `\memtest13'. +Generating test bench for module `\memtest12'. +Generating test bench for module `\memtest11'. +Generating test bench for module `\memtest10'. +Generating test bench for module `\memtest09'. +Generating test bench for module `\memtest08'. +Generating test bench for module `\memtest07'. +Generating test bench for module `\memtest06_async'. +Generating test bench for module `\memtest06_sync'. +Generating test bench for module `\memtest05'. +Generating test bench for module `\memtest04'. +Generating test bench for module `\memtest03'. +Generating test bench for module `\memtest02'. +Generating test bench for module `\memtest01'. +Generating test bench for module `\memtest00'. + +Warnings: 3 unique messages, 3 total +End of script. Logfile hash: 8aa5dddfc5, CPU: user 0.02s system 0.00s, MEM: 16.73 MB peak +Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) +Time spent: 97% 1x read_verilog (0 sec), 2% 1x test_autotb (0 sec) ++ false ++ compile_and_run memory_tb_ref memory_out_ref memory_tb.v memory_ref.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simlib.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simcells.v ++ exe=memory_tb_ref ++ output=memory_out_ref ++ shift 2 ++ '[' v == sv ']' ++ language_gen=-g2005 ++ false ++ false ++ iverilog -g2005 '-Doutfile="memory_out_ref"' -s testbench -o memory_tb_ref memory_tb.v memory_ref.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simlib.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simcells.v ++ vvp -n memory_tb_ref +memory_tb.v:1405: $finish called at 1809200 (1s) ++ false ++ test_count=0 ++ '[' 'verilog -noblackbox -specify' = verific -o 'verilog -noblackbox -specify' = verific_gates ']' ++ '[' -n '' ']' ++ '[' -n ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' ']' ++ test_passes -f 'verilog -noblackbox -specify ' -p ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' memory_ref.v ++ /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../yosys -b 'verilog -noattr -noexpr -siminit' -o memory_syn0.v -f 'verilog -noblackbox -specify ' -p ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' memory_ref.v + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2024 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) + +-- Parsing `memory_ref.v' using frontend `verilog -noblackbox -specify ' -- + +1. Executing Verilog-2005 frontend: memory_ref.v +Parsing Verilog input from `memory_ref.v' to AST representation. +Lexer warning: The SystemVerilog keyword `bit' (at memory_ref.v:39) is not recognized unless read_verilog is called with -sv! +Lexer warning: The SystemVerilog keyword `bit' (at memory_ref.v:43) is not recognized unless read_verilog is called with -sv! +Lexer warning: The SystemVerilog keyword `bit' (at memory_ref.v:70) is not recognized unless read_verilog is called with -sv! +Lexer warning: The SystemVerilog keyword `bit' (at memory_ref.v:71) is not recognized unless read_verilog is called with -sv! +Lexer warning: The SystemVerilog keyword `bit' (at memory_ref.v:74) is not recognized unless read_verilog is called with -sv! +Lexer warning: The SystemVerilog keyword `bit' (at memory_ref.v:75) is not recognized unless read_verilog is called with -sv! +Generating RTLIL representation for module `\memtest00'. +Warning: Replacing memory \mem with list of registers. See memory_ref.v:9 +Generating RTLIL representation for module `\memtest01'. +Generating RTLIL representation for module `\memtest02'. +Generating RTLIL representation for module `\memtest03'. +Generating RTLIL representation for module `\memtest04'. +Generating RTLIL representation for module `\memtest05'. +Generating RTLIL representation for module `\memtest06_sync'. +Generating RTLIL representation for module `\memtest06_async'. +Warning: Replacing memory \test with list of registers. See memory_ref.v:177 +Generating RTLIL representation for module `\memtest07'. +Generating RTLIL representation for module `\memtest08'. +Generating RTLIL representation for module `\memtest09'. +Generating RTLIL representation for module `\memtest10'. +Warning: Replacing memory \queue with list of registers. See memory_ref.v:249 +Generating RTLIL representation for module `\memtest11'. +Generating RTLIL representation for module `\memtest12'. +Generating RTLIL representation for module `\memtest13'. +Successfully finished Verilog frontend. + +-- Running command ` read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' -- + +2. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v' to AST representation. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +3. Executing HIERARCHY pass (managing design hierarchy). + +4. Executing SYNTH pass. + +4.1. Executing PROC pass (convert processes to netlists). + +4.1.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +4.1.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$memory_ref.v:304$430 in module memtest13. +Marked 1 switch rules as full_case in process $proc$memory_ref.v:270$399 in module memtest11. +Marked 1 switch rules as full_case in process $proc$memory_ref.v:235$379 in module memtest09. +Marked 1 switch rules as full_case in process $proc$memory_ref.v:229$369 in module memtest09. +Removed 1 dead cases from process $proc$memory_ref.v:0$344 in module memtest06_async. +Marked 1 switch rules as full_case in process $proc$memory_ref.v:0$344 in module memtest06_async. +Removed 5 dead cases from process $proc$memory_ref.v:174$198 in module memtest06_async. +Marked 6 switch rules as full_case in process $proc$memory_ref.v:174$198 in module memtest06_async. +Marked 1 switch rules as full_case in process $proc$memory_ref.v:150$118 in module memtest06_sync. +Marked 4 switch rules as full_case in process $proc$memory_ref.v:131$76 in module memtest05. +Marked 1 switch rules as full_case in process $proc$memory_ref.v:108$64 in module memtest04. +Marked 1 switch rules as full_case in process $proc$memory_ref.v:89$55 in module memtest03. +Removed 1 dead cases from process $proc$memory_ref.v:0$48 in module memtest02. +Marked 1 switch rules as full_case in process $proc$memory_ref.v:0$48 in module memtest02. +Removed 1 dead cases from process $proc$memory_ref.v:53$26 in module memtest02. +Marked 3 switch rules as full_case in process $proc$memory_ref.v:53$26 in module memtest02. +Marked 1 switch rules as full_case in process $proc$memory_ref.v:28$7 in module memtest01. +Removed a total of 8 dead cases. + +4.1.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 147 assignments to connections. + +4.1.4. Executing PROC_INIT pass (extract init attributes). + +4.1.5. Executing PROC_ARST pass (detect async resets in processes). +Found async reset \rst in `\memtest06_async.$proc$memory_ref.v:174$198'. + +4.1.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +4.1.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\memtest13.$proc$memory_ref.v:304$430'. + 1/18: $1$memwr$\mem$memory_ref.v:309$424_EN[26:0]$449 + 2/18: $1$memwr$\mem$memory_ref.v:308$423_EN[26:0]$448 + 3/18: $1$memwr$\mem$memory_ref.v:307$422_EN[26:0]$447 + 4/18: $1$memwr$\mem$memory_ref.v:306$421_EN[26:0]$446 + 5/18: $1$mem2bits$\mem$memory_ref.v:315$429[26:0]$460 + 6/18: $1$mem2bits$\mem$memory_ref.v:314$428[26:0]$459 + 7/18: $1$memwr$\mem$memory_ref.v:313$427_EN[26:0]$458 + 8/18: $1$memwr$\mem$memory_ref.v:313$427_DATA[26:0]$457 + 9/18: $1$memwr$\mem$memory_ref.v:313$427_ADDR[1:0]$456 + 10/18: $1$memwr$\mem$memory_ref.v:312$426_EN[26:0]$455 + 11/18: $1$memwr$\mem$memory_ref.v:312$426_DATA[26:0]$454 + 12/18: $1$memwr$\mem$memory_ref.v:312$426_ADDR[1:0]$453 + 13/18: $1$memwr$\mem$memory_ref.v:311$425_EN[26:0]$452 + 14/18: $1$memwr$\mem$memory_ref.v:311$425_DATA[26:0]$451 + 15/18: $1$memwr$\mem$memory_ref.v:311$425_ADDR[1:0]$450 + 16/18: $0\dout3[26:0] + 17/18: $0\dout2[3:0] + 18/18: $0\dout1[3:0] +Creating decoders for process `\memtest12.$proc$memory_ref.v:287$415'. +Creating decoders for process `\memtest11.$proc$memory_ref.v:270$399'. + 1/6: $1$memwr$\mem$memory_ref.v:272$396_EN[7:0]$408 + 2/6: $1$memwr$\mem$memory_ref.v:272$396_DATA[7:0]$407 + 3/6: $1$memwr$\mem$memory_ref.v:272$396_ADDR[1:0]$406 + 4/6: $1$memwr$\mem$memory_ref.v:274$397_EN[7:0]$411 + 5/6: $1$memwr$\mem$memory_ref.v:274$397_DATA[7:0]$410 + 6/6: $1$memwr$\mem$memory_ref.v:274$397_ADDR[1:0]$409 +Creating decoders for process `\memtest10.$proc$memory_ref.v:248$395'. +Creating decoders for process `\memtest09.$proc$memory_ref.v:235$379'. + 1/3: $1$memwr$\memory$memory_ref.v:237$368_EN[3:0]$391 + 2/3: $1$memwr$\memory$memory_ref.v:237$368_DATA[3:0]$390 + 3/3: $1$memwr$\memory$memory_ref.v:237$368_ADDR[31:0]$389 +Creating decoders for process `\memtest09.$proc$memory_ref.v:229$369'. + 1/3: $1$memwr$\memory$memory_ref.v:231$367_EN[3:0]$375 + 2/3: $1$memwr$\memory$memory_ref.v:231$367_DATA[3:0]$374 + 3/3: $1$memwr$\memory$memory_ref.v:231$367_ADDR[31:0]$373 +Creating decoders for process `\memtest08.$proc$memory_ref.v:213$358'. +Creating decoders for process `\memtest07.$proc$memory_ref.v:202$348'. +Creating decoders for process `\memtest06_async.$proc$memory_ref.v:0$344'. + 1/1: $1$mem2reg_rd$\test$memory_ref.v:186$181_DATA[7:0]$346 +Creating decoders for process `\memtest06_async.$proc$memory_ref.v:174$198'. + 1/61: $4$lookahead\test[0]$190[7:0]$280 + 2/61: $2$bitselwrite$pos$memory_ref.v:0$182[2:0]$272 + 3/61: $4$lookahead\test[7]$197[7:0]$287 + 4/61: $4$lookahead\test[6]$196[7:0]$286 + 5/61: $4$lookahead\test[5]$195[7:0]$285 + 6/61: $4$lookahead\test[4]$194[7:0]$284 + 7/61: $4$lookahead\test[3]$193[7:0]$283 + 8/61: $4$lookahead\test[2]$192[7:0]$282 + 9/61: $4$lookahead\test[1]$191[7:0]$281 + 10/61: $2$bitselwrite$pos$memory_ref.v:0$189[2:0]$279 + 11/61: $2$bitselwrite$pos$memory_ref.v:0$188[2:0]$278 + 12/61: $2$bitselwrite$pos$memory_ref.v:0$187[2:0]$277 + 13/61: $2$bitselwrite$pos$memory_ref.v:0$186[2:0]$276 + 14/61: $2$bitselwrite$pos$memory_ref.v:0$185[2:0]$275 + 15/61: $2$bitselwrite$pos$memory_ref.v:0$184[2:0]$274 + 16/61: $2$bitselwrite$pos$memory_ref.v:0$183[2:0]$273 + 17/61: $2$mem2reg_rd$\test$memory_ref.v:183$180_DATA[7:0]$269 + 18/61: $3$lookahead\test[0]$190[6:6]$261 + 19/61: $3$lookahead\test[7]$197[6:6]$268 + 20/61: $3$lookahead\test[6]$196[6:6]$267 + 21/61: $3$lookahead\test[5]$195[6:6]$266 + 22/61: $3$lookahead\test[4]$194[6:6]$265 + 23/61: $3$lookahead\test[3]$193[6:6]$264 + 24/61: $3$lookahead\test[2]$192[6:6]$263 + 25/61: $3$lookahead\test[1]$191[6:6]$262 + 26/61: $2$mem2reg_rd$\test$memory_ref.v:182$178_DATA[7:0]$260 + 27/61: $2$lookahead\test[0]$190[3:3]$252 + 28/61: $2$lookahead\test[7]$197[3:3]$259 + 29/61: $2$lookahead\test[6]$196[3:3]$258 + 30/61: $2$lookahead\test[5]$195[3:3]$257 + 31/61: $2$lookahead\test[4]$194[3:3]$256 + 32/61: $2$lookahead\test[3]$193[3:3]$255 + 33/61: $2$lookahead\test[2]$192[3:3]$254 + 34/61: $2$lookahead\test[1]$191[3:3]$253 + 35/61: $1$lookahead\test[7]$197[7:0]$250 + 36/61: $1$lookahead\test[6]$196[7:0]$249 + 37/61: $1$lookahead\test[5]$195[7:0]$248 + 38/61: $1$lookahead\test[4]$194[7:0]$247 + 39/61: $1$lookahead\test[3]$193[7:0]$246 + 40/61: $1$lookahead\test[2]$192[7:0]$245 + 41/61: $1$lookahead\test[1]$191[7:0]$244 + 42/61: $1$lookahead\test[0]$190[7:0]$243 + 43/61: $1$bitselwrite$pos$memory_ref.v:0$189[2:0]$242 + 44/61: $1$bitselwrite$pos$memory_ref.v:0$188[2:0]$241 + 45/61: $1$bitselwrite$pos$memory_ref.v:0$187[2:0]$240 + 46/61: $1$bitselwrite$pos$memory_ref.v:0$186[2:0]$239 + 47/61: $1$bitselwrite$pos$memory_ref.v:0$185[2:0]$238 + 48/61: $1$bitselwrite$pos$memory_ref.v:0$184[2:0]$237 + 49/61: $1$bitselwrite$pos$memory_ref.v:0$183[2:0]$236 + 50/61: $1$bitselwrite$pos$memory_ref.v:0$182[2:0]$235 + 51/61: $1$mem2reg_wr$\test$memory_ref.v:183$179_ADDR[2:0]$231 + 52/61: $1$mem2reg_wr$\test$memory_ref.v:183$179_DATA[7:0]$232 + 53/61: $1$mem2reg_rd$\test$memory_ref.v:183$180_DATA[7:0]$234 + 54/61: $1$mem2reg_rd$\test$memory_ref.v:183$180_ADDR[2:0]$233 + 55/61: $1$mem2reg_wr$\test$memory_ref.v:182$177_ADDR[2:0]$227 + 56/61: $1$mem2reg_wr$\test$memory_ref.v:182$177_DATA[7:0]$228 + 57/61: $1$mem2reg_rd$\test$memory_ref.v:182$178_DATA[7:0]$230 + 58/61: $1$mem2reg_rd$\test$memory_ref.v:182$178_ADDR[2:0]$229 + 59/61: $1$mem2reg_wr$\test$memory_ref.v:181$176_ADDR[2:0]$225 + 60/61: $1$mem2reg_wr$\test$memory_ref.v:181$176_DATA[7:0]$226 + 61/61: $1\i[31:0] +Creating decoders for process `\memtest06_sync.$proc$memory_ref.v:150$118'. + 1/25: $1\i[31:0] + 2/25: $1$memwr$\test$memory_ref.v:153$109_EN[7:0]$150 + 3/25: $1$memwr$\test$memory_ref.v:153$108_EN[7:0]$149 + 4/25: $1$memwr$\test$memory_ref.v:153$107_EN[7:0]$148 + 5/25: $1$memwr$\test$memory_ref.v:153$106_EN[7:0]$147 + 6/25: $1$memwr$\test$memory_ref.v:153$105_EN[7:0]$146 + 7/25: $1$memwr$\test$memory_ref.v:153$104_EN[7:0]$145 + 8/25: $1$memwr$\test$memory_ref.v:153$103_EN[7:0]$144 + 9/25: $1$memwr$\test$memory_ref.v:153$102_EN[7:0]$143 + 10/25: $1$memwr$\test$memory_ref.v:159$117_EN[7:0]$166 + 11/25: $1$memwr$\test$memory_ref.v:159$117_DATA[7:0]$165 + 12/25: $1$memwr$\test$memory_ref.v:159$117_ADDR[2:0]$164 + 13/25: $1$mem2bits$\test$memory_ref.v:159$116[7:0]$163 + 14/25: $1$memwr$\test$memory_ref.v:158$115_EN[7:0]$162 + 15/25: $1$memwr$\test$memory_ref.v:158$115_DATA[7:0]$161 + 16/25: $1$memwr$\test$memory_ref.v:158$115_ADDR[2:0]$160 + 17/25: $1$mem2bits$\test$memory_ref.v:158$114[7:0]$159 + 18/25: $1$memwr$\test$memory_ref.v:157$113_EN[7:0]$158 + 19/25: $1$memwr$\test$memory_ref.v:157$113_DATA[7:0]$157 + 20/25: $1$memwr$\test$memory_ref.v:157$113_ADDR[2:0]$156 + 21/25: $1$memwr$\test$memory_ref.v:156$112_EN[7:0]$155 + 22/25: $1$memwr$\test$memory_ref.v:156$112_DATA[7:0]$154 + 23/25: $1$mem2bits$\test$memory_ref.v:156$111[7:0]$153 + 24/25: $1$memwr$\test$memory_ref.v:155$110_EN[7:0]$152 + 25/25: $1$memwr$\test$memory_ref.v:155$110_DATA[7:0]$151 +Creating decoders for process `\memtest05.$proc$memory_ref.v:131$76'. + 1/12: $1$memwr$\mem$memory_ref.v:133$75_EN[7:0]$100 + 2/12: $1$memwr$\mem$memory_ref.v:133$75_DATA[7:0]$99 + 3/12: $1$memwr$\mem$memory_ref.v:133$75_ADDR[1:0]$98 + 4/12: $1$memwr$\mem$memory_ref.v:133$74_EN[7:0]$97 + 5/12: $1$memwr$\mem$memory_ref.v:133$74_DATA[7:0]$96 + 6/12: $1$memwr$\mem$memory_ref.v:133$74_ADDR[1:0]$95 + 7/12: $1$memwr$\mem$memory_ref.v:133$73_EN[7:0]$94 + 8/12: $1$memwr$\mem$memory_ref.v:133$73_DATA[7:0]$93 + 9/12: $1$memwr$\mem$memory_ref.v:133$73_ADDR[1:0]$92 + 10/12: $1$memwr$\mem$memory_ref.v:133$72_EN[7:0]$91 + 11/12: $1$memwr$\mem$memory_ref.v:133$72_DATA[7:0]$90 + 12/12: $1$memwr$\mem$memory_ref.v:133$72_ADDR[1:0]$89 +Creating decoders for process `\memtest04.$proc$memory_ref.v:108$64'. + 1/3: $1$memwr$\memory$memory_ref.v:110$63_EN[3:0]$70 + 2/3: $1$memwr$\memory$memory_ref.v:110$63_DATA[3:0]$69 + 3/3: $1$memwr$\memory$memory_ref.v:110$63_ADDR[3:0]$68 +Creating decoders for process `\memtest03.$proc$memory_ref.v:89$55'. + 1/3: $1$memwr$\memory$memory_ref.v:91$54_EN[3:0]$61 + 2/3: $1$memwr$\memory$memory_ref.v:91$54_DATA[3:0]$60 + 3/3: $1$memwr$\memory$memory_ref.v:91$54_ADDR[3:0]$59 +Creating decoders for process `\memtest02.$proc$memory_ref.v:0$51'. +Creating decoders for process `\memtest02.$proc$memory_ref.v:0$48'. + 1/1: $1$mem2reg_rd$\mem2$memory_ref.v:75$17_DATA[7:0]$50 +Creating decoders for process `\memtest02.$proc$memory_ref.v:53$26'. + 1/10: $1$mem2reg_rd$\mem2$memory_ref.v:71$16_DATA[7:0]$44 + 2/10: $1$memwr$\mem1$memory_ref.v:65$23_EN[7:0]$41 + 3/10: $1$memwr$\mem1$memory_ref.v:64$22_EN[7:0]$40 + 4/10: $1$memwr$\mem1$memory_ref.v:63$21_EN[7:0]$39 + 5/10: $1$memwr$\mem1$memory_ref.v:57$20_EN[7:0]$38 + 6/10: $1$memwr$\mem1$memory_ref.v:56$19_EN[7:0]$37 + 7/10: $1$memwr$\mem1$memory_ref.v:55$18_EN[7:0]$36 + 8/10: $0\mem2[2][7:0] + 9/10: $0\mem2[1][7:0] + 10/10: $0\mem2[0][7:0] +Creating decoders for process `\memtest01.$proc$memory_ref.v:32$14'. +Creating decoders for process `\memtest01.$proc$memory_ref.v:28$7'. + 1/3: $1$memwr$\data$memory_ref.v:30$6_EN[7:0]$13 + 2/3: $1$memwr$\data$memory_ref.v:30$6_DATA[7:0]$12 + 3/3: $1$memwr$\data$memory_ref.v:30$6_ADDR[3:0]$11 +Creating decoders for process `\memtest00.$proc$memory_ref.v:8$5'. + 1/1: $0\mem[0][0:0] + +4.1.8. Executing PROC_DLATCH pass (convert process syncs to latches). +No latch inferred for signal `\memtest06_async.$mem2reg_rd$\test$memory_ref.v:186$181_DATA' from process `\memtest06_async.$proc$memory_ref.v:0$344'. +No latch inferred for signal `\memtest02.$mem2bits$\mem1$memory_ref.v:74$25' from process `\memtest02.$proc$memory_ref.v:0$51'. +No latch inferred for signal `\memtest02.$mem2reg_rd$\mem2$memory_ref.v:75$17_DATA' from process `\memtest02.$proc$memory_ref.v:0$48'. + +4.1.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\memtest13.\dout1' using process `\memtest13.$proc$memory_ref.v:304$430'. + created $dff cell `$procdff$1070' with positive edge clock. +Creating register for signal `\memtest13.\dout2' using process `\memtest13.$proc$memory_ref.v:304$430'. + created $dff cell `$procdff$1071' with positive edge clock. +Creating register for signal `\memtest13.\dout3' using process `\memtest13.$proc$memory_ref.v:304$430'. + created $dff cell `$procdff$1072' with positive edge clock. +Creating register for signal `\memtest13.$memwr$\mem$memory_ref.v:306$421_EN' using process `\memtest13.$proc$memory_ref.v:304$430'. + created $dff cell `$procdff$1073' with positive edge clock. +Creating register for signal `\memtest13.$memwr$\mem$memory_ref.v:307$422_EN' using process `\memtest13.$proc$memory_ref.v:304$430'. + created $dff cell `$procdff$1074' with positive edge clock. +Creating register for signal `\memtest13.$memwr$\mem$memory_ref.v:308$423_EN' using process `\memtest13.$proc$memory_ref.v:304$430'. + created $dff cell `$procdff$1075' with positive edge clock. +Creating register for signal `\memtest13.$memwr$\mem$memory_ref.v:309$424_EN' using process `\memtest13.$proc$memory_ref.v:304$430'. + created $dff cell `$procdff$1076' with positive edge clock. +Creating register for signal `\memtest13.$memwr$\mem$memory_ref.v:311$425_ADDR' using process `\memtest13.$proc$memory_ref.v:304$430'. + created $dff cell `$procdff$1077' with positive edge clock. +Creating register for signal `\memtest13.$memwr$\mem$memory_ref.v:311$425_DATA' using process `\memtest13.$proc$memory_ref.v:304$430'. + created $dff cell `$procdff$1078' with positive edge clock. +Creating register for signal `\memtest13.$memwr$\mem$memory_ref.v:311$425_EN' using process `\memtest13.$proc$memory_ref.v:304$430'. + created $dff cell `$procdff$1079' with positive edge clock. +Creating register for signal `\memtest13.$memwr$\mem$memory_ref.v:312$426_ADDR' using process `\memtest13.$proc$memory_ref.v:304$430'. + created $dff cell `$procdff$1080' with positive edge clock. +Creating register for signal `\memtest13.$memwr$\mem$memory_ref.v:312$426_DATA' using process `\memtest13.$proc$memory_ref.v:304$430'. + created $dff cell `$procdff$1081' with positive edge clock. +Creating register for signal `\memtest13.$memwr$\mem$memory_ref.v:312$426_EN' using process `\memtest13.$proc$memory_ref.v:304$430'. + created $dff cell `$procdff$1082' with positive edge clock. +Creating register for signal `\memtest13.$memwr$\mem$memory_ref.v:313$427_ADDR' using process `\memtest13.$proc$memory_ref.v:304$430'. + created $dff cell `$procdff$1083' with positive edge clock. +Creating register for signal `\memtest13.$memwr$\mem$memory_ref.v:313$427_DATA' using process `\memtest13.$proc$memory_ref.v:304$430'. + created $dff cell `$procdff$1084' with positive edge clock. +Creating register for signal `\memtest13.$memwr$\mem$memory_ref.v:313$427_EN' using process `\memtest13.$proc$memory_ref.v:304$430'. + created $dff cell `$procdff$1085' with positive edge clock. +Creating register for signal `\memtest13.$mem2bits$\mem$memory_ref.v:314$428' using process `\memtest13.$proc$memory_ref.v:304$430'. + created $dff cell `$procdff$1086' with positive edge clock. +Creating register for signal `\memtest13.$mem2bits$\mem$memory_ref.v:315$429' using process `\memtest13.$proc$memory_ref.v:304$430'. + created $dff cell `$procdff$1087' with positive edge clock. +Creating register for signal `\memtest12.\q' using process `\memtest12.$proc$memory_ref.v:287$415'. + created $dff cell `$procdff$1088' with positive edge clock. +Creating register for signal `\memtest12.$splitcmplxassign$memory_ref.v:288$413' using process `\memtest12.$proc$memory_ref.v:287$415'. + created $dff cell `$procdff$1089' with positive edge clock. +Creating register for signal `\memtest12.$memwr$\ram$memory_ref.v:0$414_ADDR' using process `\memtest12.$proc$memory_ref.v:287$415'. + created $dff cell `$procdff$1090' with positive edge clock. +Creating register for signal `\memtest12.$memwr$\ram$memory_ref.v:0$414_DATA' using process `\memtest12.$proc$memory_ref.v:287$415'. + created $dff cell `$procdff$1091' with positive edge clock. +Creating register for signal `\memtest12.$memwr$\ram$memory_ref.v:0$414_EN' using process `\memtest12.$proc$memory_ref.v:287$415'. + created $dff cell `$procdff$1092' with positive edge clock. +Creating register for signal `\memtest11.$memwr$\mem$memory_ref.v:272$396_ADDR' using process `\memtest11.$proc$memory_ref.v:270$399'. + created $dff cell `$procdff$1093' with positive edge clock. +Creating register for signal `\memtest11.$memwr$\mem$memory_ref.v:272$396_DATA' using process `\memtest11.$proc$memory_ref.v:270$399'. + created $dff cell `$procdff$1094' with positive edge clock. +Creating register for signal `\memtest11.$memwr$\mem$memory_ref.v:272$396_EN' using process `\memtest11.$proc$memory_ref.v:270$399'. + created $dff cell `$procdff$1095' with positive edge clock. +Creating register for signal `\memtest11.$memwr$\mem$memory_ref.v:274$397_ADDR' using process `\memtest11.$proc$memory_ref.v:270$399'. + created $dff cell `$procdff$1096' with positive edge clock. +Creating register for signal `\memtest11.$memwr$\mem$memory_ref.v:274$397_DATA' using process `\memtest11.$proc$memory_ref.v:270$399'. + created $dff cell `$procdff$1097' with positive edge clock. +Creating register for signal `\memtest11.$memwr$\mem$memory_ref.v:274$397_EN' using process `\memtest11.$proc$memory_ref.v:270$399'. + created $dff cell `$procdff$1098' with positive edge clock. +Creating register for signal `\memtest10.\i' using process `\memtest10.$proc$memory_ref.v:248$395'. + created $dff cell `$procdff$1099' with positive edge clock. +Creating register for signal `\memtest10.\queue[0]' using process `\memtest10.$proc$memory_ref.v:248$395'. + created $dff cell `$procdff$1100' with positive edge clock. +Creating register for signal `\memtest10.\queue[1]' using process `\memtest10.$proc$memory_ref.v:248$395'. + created $dff cell `$procdff$1101' with positive edge clock. +Creating register for signal `\memtest10.\queue[2]' using process `\memtest10.$proc$memory_ref.v:248$395'. + created $dff cell `$procdff$1102' with positive edge clock. +Creating register for signal `\memtest10.\queue[3]' using process `\memtest10.$proc$memory_ref.v:248$395'. + created $dff cell `$procdff$1103' with positive edge clock. +Creating register for signal `\memtest09.\b_dout' using process `\memtest09.$proc$memory_ref.v:235$379'. + created $dff cell `$procdff$1104' with positive edge clock. +Creating register for signal `\memtest09.$memwr$\memory$memory_ref.v:237$368_ADDR' using process `\memtest09.$proc$memory_ref.v:235$379'. + created $dff cell `$procdff$1105' with positive edge clock. +Creating register for signal `\memtest09.$memwr$\memory$memory_ref.v:237$368_DATA' using process `\memtest09.$proc$memory_ref.v:235$379'. + created $dff cell `$procdff$1106' with positive edge clock. +Creating register for signal `\memtest09.$memwr$\memory$memory_ref.v:237$368_EN' using process `\memtest09.$proc$memory_ref.v:235$379'. + created $dff cell `$procdff$1107' with positive edge clock. +Creating register for signal `\memtest09.\a_dout' using process `\memtest09.$proc$memory_ref.v:229$369'. + created $dff cell `$procdff$1108' with positive edge clock. +Creating register for signal `\memtest09.$memwr$\memory$memory_ref.v:231$367_ADDR' using process `\memtest09.$proc$memory_ref.v:229$369'. + created $dff cell `$procdff$1109' with positive edge clock. +Creating register for signal `\memtest09.$memwr$\memory$memory_ref.v:231$367_DATA' using process `\memtest09.$proc$memory_ref.v:229$369'. + created $dff cell `$procdff$1110' with positive edge clock. +Creating register for signal `\memtest09.$memwr$\memory$memory_ref.v:231$367_EN' using process `\memtest09.$proc$memory_ref.v:229$369'. + created $dff cell `$procdff$1111' with positive edge clock. +Creating register for signal `\memtest08.\y' using process `\memtest08.$proc$memory_ref.v:213$358'. + created $dff cell `$procdff$1112' with positive edge clock. +Creating register for signal `\memtest08.$memwr$\mem$memory_ref.v:215$357_ADDR' using process `\memtest08.$proc$memory_ref.v:213$358'. + created $dff cell `$procdff$1113' with positive edge clock. +Creating register for signal `\memtest08.$memwr$\mem$memory_ref.v:215$357_DATA' using process `\memtest08.$proc$memory_ref.v:213$358'. + created $dff cell `$procdff$1114' with positive edge clock. +Creating register for signal `\memtest08.$memwr$\mem$memory_ref.v:215$357_EN' using process `\memtest08.$proc$memory_ref.v:213$358'. + created $dff cell `$procdff$1115' with positive edge clock. +Creating register for signal `\memtest07.\rdata' using process `\memtest07.$proc$memory_ref.v:202$348'. + created $dff cell `$procdff$1116' with positive edge clock. +Creating register for signal `\memtest07.$memwr$\mem$memory_ref.v:203$347_ADDR' using process `\memtest07.$proc$memory_ref.v:202$348'. + created $dff cell `$procdff$1117' with positive edge clock. +Creating register for signal `\memtest07.$memwr$\mem$memory_ref.v:203$347_DATA' using process `\memtest07.$proc$memory_ref.v:202$348'. + created $dff cell `$procdff$1118' with positive edge clock. +Creating register for signal `\memtest07.$memwr$\mem$memory_ref.v:203$347_EN' using process `\memtest07.$proc$memory_ref.v:202$348'. + created $dff cell `$procdff$1119' with positive edge clock. +Creating register for signal `\memtest06_async.\i' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1122' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.\test[0]' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1125' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.\test[1]' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1128' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.\test[2]' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1131' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.\test[3]' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1134' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.\test[4]' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1137' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.\test[5]' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1140' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.\test[6]' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1143' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.\test[7]' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1146' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.$mem2reg_wr$\test$memory_ref.v:181$176_ADDR' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1149' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.$mem2reg_wr$\test$memory_ref.v:181$176_DATA' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1152' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.$mem2reg_wr$\test$memory_ref.v:182$177_ADDR' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1155' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.$mem2reg_wr$\test$memory_ref.v:182$177_DATA' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1158' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.$mem2reg_rd$\test$memory_ref.v:182$178_ADDR' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1161' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.$mem2reg_rd$\test$memory_ref.v:182$178_DATA' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1164' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.$mem2reg_wr$\test$memory_ref.v:183$179_ADDR' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1167' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.$mem2reg_wr$\test$memory_ref.v:183$179_DATA' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1170' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.$mem2reg_rd$\test$memory_ref.v:183$180_ADDR' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1173' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.$mem2reg_rd$\test$memory_ref.v:183$180_DATA' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1176' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.$bitselwrite$pos$memory_ref.v:0$182' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1179' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.$bitselwrite$pos$memory_ref.v:0$183' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1182' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.$bitselwrite$pos$memory_ref.v:0$184' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1185' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.$bitselwrite$pos$memory_ref.v:0$185' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1188' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.$bitselwrite$pos$memory_ref.v:0$186' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1191' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.$bitselwrite$pos$memory_ref.v:0$187' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1194' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.$bitselwrite$pos$memory_ref.v:0$188' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1197' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.$bitselwrite$pos$memory_ref.v:0$189' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1200' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.$lookahead\test[0]$190' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1203' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.$lookahead\test[1]$191' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1206' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.$lookahead\test[2]$192' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1209' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.$lookahead\test[3]$193' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1212' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.$lookahead\test[4]$194' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1215' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.$lookahead\test[5]$195' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1218' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.$lookahead\test[6]$196' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1221' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_async.$lookahead\test[7]$197' using process `\memtest06_async.$proc$memory_ref.v:174$198'. + created $adff cell `$procdff$1224' with positive edge clock and positive level reset. +Creating register for signal `\memtest06_sync.\i' using process `\memtest06_sync.$proc$memory_ref.v:150$118'. + created $dff cell `$procdff$1225' with positive edge clock. +Creating register for signal `\memtest06_sync.$memwr$\test$memory_ref.v:153$102_EN' using process `\memtest06_sync.$proc$memory_ref.v:150$118'. + created $dff cell `$procdff$1226' with positive edge clock. +Creating register for signal `\memtest06_sync.$memwr$\test$memory_ref.v:153$103_EN' using process `\memtest06_sync.$proc$memory_ref.v:150$118'. + created $dff cell `$procdff$1227' with positive edge clock. +Creating register for signal `\memtest06_sync.$memwr$\test$memory_ref.v:153$104_EN' using process `\memtest06_sync.$proc$memory_ref.v:150$118'. + created $dff cell `$procdff$1228' with positive edge clock. +Creating register for signal `\memtest06_sync.$memwr$\test$memory_ref.v:153$105_EN' using process `\memtest06_sync.$proc$memory_ref.v:150$118'. + created $dff cell `$procdff$1229' with positive edge clock. +Creating register for signal `\memtest06_sync.$memwr$\test$memory_ref.v:153$106_EN' using process `\memtest06_sync.$proc$memory_ref.v:150$118'. + created $dff cell `$procdff$1230' with positive edge clock. +Creating register for signal `\memtest06_sync.$memwr$\test$memory_ref.v:153$107_EN' using process `\memtest06_sync.$proc$memory_ref.v:150$118'. + created $dff cell `$procdff$1231' with positive edge clock. +Creating register for signal `\memtest06_sync.$memwr$\test$memory_ref.v:153$108_EN' using process `\memtest06_sync.$proc$memory_ref.v:150$118'. + created $dff cell `$procdff$1232' with positive edge clock. +Creating register for signal `\memtest06_sync.$memwr$\test$memory_ref.v:153$109_EN' using process `\memtest06_sync.$proc$memory_ref.v:150$118'. + created $dff cell `$procdff$1233' with positive edge clock. +Creating register for signal `\memtest06_sync.$memwr$\test$memory_ref.v:155$110_DATA' using process `\memtest06_sync.$proc$memory_ref.v:150$118'. + created $dff cell `$procdff$1234' with positive edge clock. +Creating register for signal `\memtest06_sync.$memwr$\test$memory_ref.v:155$110_EN' using process `\memtest06_sync.$proc$memory_ref.v:150$118'. + created $dff cell `$procdff$1235' with positive edge clock. +Creating register for signal `\memtest06_sync.$mem2bits$\test$memory_ref.v:156$111' using process `\memtest06_sync.$proc$memory_ref.v:150$118'. + created $dff cell `$procdff$1236' with positive edge clock. +Creating register for signal `\memtest06_sync.$memwr$\test$memory_ref.v:156$112_DATA' using process `\memtest06_sync.$proc$memory_ref.v:150$118'. + created $dff cell `$procdff$1237' with positive edge clock. +Creating register for signal `\memtest06_sync.$memwr$\test$memory_ref.v:156$112_EN' using process `\memtest06_sync.$proc$memory_ref.v:150$118'. + created $dff cell `$procdff$1238' with positive edge clock. +Creating register for signal `\memtest06_sync.$memwr$\test$memory_ref.v:157$113_ADDR' using process `\memtest06_sync.$proc$memory_ref.v:150$118'. + created $dff cell `$procdff$1239' with positive edge clock. +Creating register for signal `\memtest06_sync.$memwr$\test$memory_ref.v:157$113_DATA' using process `\memtest06_sync.$proc$memory_ref.v:150$118'. + created $dff cell `$procdff$1240' with positive edge clock. +Creating register for signal `\memtest06_sync.$memwr$\test$memory_ref.v:157$113_EN' using process `\memtest06_sync.$proc$memory_ref.v:150$118'. + created $dff cell `$procdff$1241' with positive edge clock. +Creating register for signal `\memtest06_sync.$mem2bits$\test$memory_ref.v:158$114' using process `\memtest06_sync.$proc$memory_ref.v:150$118'. + created $dff cell `$procdff$1242' with positive edge clock. +Creating register for signal `\memtest06_sync.$memwr$\test$memory_ref.v:158$115_ADDR' using process `\memtest06_sync.$proc$memory_ref.v:150$118'. + created $dff cell `$procdff$1243' with positive edge clock. +Creating register for signal `\memtest06_sync.$memwr$\test$memory_ref.v:158$115_DATA' using process `\memtest06_sync.$proc$memory_ref.v:150$118'. + created $dff cell `$procdff$1244' with positive edge clock. +Creating register for signal `\memtest06_sync.$memwr$\test$memory_ref.v:158$115_EN' using process `\memtest06_sync.$proc$memory_ref.v:150$118'. + created $dff cell `$procdff$1245' with positive edge clock. +Creating register for signal `\memtest06_sync.$mem2bits$\test$memory_ref.v:159$116' using process `\memtest06_sync.$proc$memory_ref.v:150$118'. + created $dff cell `$procdff$1246' with positive edge clock. +Creating register for signal `\memtest06_sync.$memwr$\test$memory_ref.v:159$117_ADDR' using process `\memtest06_sync.$proc$memory_ref.v:150$118'. + created $dff cell `$procdff$1247' with positive edge clock. +Creating register for signal `\memtest06_sync.$memwr$\test$memory_ref.v:159$117_DATA' using process `\memtest06_sync.$proc$memory_ref.v:150$118'. + created $dff cell `$procdff$1248' with positive edge clock. +Creating register for signal `\memtest06_sync.$memwr$\test$memory_ref.v:159$117_EN' using process `\memtest06_sync.$proc$memory_ref.v:150$118'. + created $dff cell `$procdff$1249' with positive edge clock. +Creating register for signal `\memtest05.\rdata' using process `\memtest05.$proc$memory_ref.v:131$76'. + created $dff cell `$procdff$1250' with positive edge clock. +Creating register for signal `\memtest05.\i' using process `\memtest05.$proc$memory_ref.v:131$76'. + created $dff cell `$procdff$1251' with positive edge clock. +Creating register for signal `\memtest05.$memwr$\mem$memory_ref.v:133$72_ADDR' using process `\memtest05.$proc$memory_ref.v:131$76'. + created $dff cell `$procdff$1252' with positive edge clock. +Creating register for signal `\memtest05.$memwr$\mem$memory_ref.v:133$72_DATA' using process `\memtest05.$proc$memory_ref.v:131$76'. + created $dff cell `$procdff$1253' with positive edge clock. +Creating register for signal `\memtest05.$memwr$\mem$memory_ref.v:133$72_EN' using process `\memtest05.$proc$memory_ref.v:131$76'. + created $dff cell `$procdff$1254' with positive edge clock. +Creating register for signal `\memtest05.$memwr$\mem$memory_ref.v:133$73_ADDR' using process `\memtest05.$proc$memory_ref.v:131$76'. + created $dff cell `$procdff$1255' with positive edge clock. +Creating register for signal `\memtest05.$memwr$\mem$memory_ref.v:133$73_DATA' using process `\memtest05.$proc$memory_ref.v:131$76'. + created $dff cell `$procdff$1256' with positive edge clock. +Creating register for signal `\memtest05.$memwr$\mem$memory_ref.v:133$73_EN' using process `\memtest05.$proc$memory_ref.v:131$76'. + created $dff cell `$procdff$1257' with positive edge clock. +Creating register for signal `\memtest05.$memwr$\mem$memory_ref.v:133$74_ADDR' using process `\memtest05.$proc$memory_ref.v:131$76'. + created $dff cell `$procdff$1258' with positive edge clock. +Creating register for signal `\memtest05.$memwr$\mem$memory_ref.v:133$74_DATA' using process `\memtest05.$proc$memory_ref.v:131$76'. + created $dff cell `$procdff$1259' with positive edge clock. +Creating register for signal `\memtest05.$memwr$\mem$memory_ref.v:133$74_EN' using process `\memtest05.$proc$memory_ref.v:131$76'. + created $dff cell `$procdff$1260' with positive edge clock. +Creating register for signal `\memtest05.$memwr$\mem$memory_ref.v:133$75_ADDR' using process `\memtest05.$proc$memory_ref.v:131$76'. + created $dff cell `$procdff$1261' with positive edge clock. +Creating register for signal `\memtest05.$memwr$\mem$memory_ref.v:133$75_DATA' using process `\memtest05.$proc$memory_ref.v:131$76'. + created $dff cell `$procdff$1262' with positive edge clock. +Creating register for signal `\memtest05.$memwr$\mem$memory_ref.v:133$75_EN' using process `\memtest05.$proc$memory_ref.v:131$76'. + created $dff cell `$procdff$1263' with positive edge clock. +Creating register for signal `\memtest04.\rd_addr_buf' using process `\memtest04.$proc$memory_ref.v:108$64'. + created $dff cell `$procdff$1264' with positive edge clock. +Creating register for signal `\memtest04.$memwr$\memory$memory_ref.v:110$63_ADDR' using process `\memtest04.$proc$memory_ref.v:108$64'. + created $dff cell `$procdff$1265' with positive edge clock. +Creating register for signal `\memtest04.$memwr$\memory$memory_ref.v:110$63_DATA' using process `\memtest04.$proc$memory_ref.v:108$64'. + created $dff cell `$procdff$1266' with positive edge clock. +Creating register for signal `\memtest04.$memwr$\memory$memory_ref.v:110$63_EN' using process `\memtest04.$proc$memory_ref.v:108$64'. + created $dff cell `$procdff$1267' with positive edge clock. +Creating register for signal `\memtest03.\rd_data' using process `\memtest03.$proc$memory_ref.v:89$55'. + created $dff cell `$procdff$1268' with positive edge clock. +Creating register for signal `\memtest03.$memwr$\memory$memory_ref.v:91$54_ADDR' using process `\memtest03.$proc$memory_ref.v:89$55'. + created $dff cell `$procdff$1269' with positive edge clock. +Creating register for signal `\memtest03.$memwr$\memory$memory_ref.v:91$54_DATA' using process `\memtest03.$proc$memory_ref.v:89$55'. + created $dff cell `$procdff$1270' with positive edge clock. +Creating register for signal `\memtest03.$memwr$\memory$memory_ref.v:91$54_EN' using process `\memtest03.$proc$memory_ref.v:89$55'. + created $dff cell `$procdff$1271' with positive edge clock. +Creating register for signal `\memtest02.\y1' using process `\memtest02.$proc$memory_ref.v:53$26'. + created $dff cell `$procdff$1272' with positive edge clock. +Creating register for signal `\memtest02.\y2' using process `\memtest02.$proc$memory_ref.v:53$26'. + created $dff cell `$procdff$1273' with positive edge clock. +Creating register for signal `\memtest02.\mem2[0]' using process `\memtest02.$proc$memory_ref.v:53$26'. + created $dff cell `$procdff$1274' with positive edge clock. +Creating register for signal `\memtest02.\mem2[1]' using process `\memtest02.$proc$memory_ref.v:53$26'. + created $dff cell `$procdff$1275' with positive edge clock. +Creating register for signal `\memtest02.\mem2[2]' using process `\memtest02.$proc$memory_ref.v:53$26'. + created $dff cell `$procdff$1276' with positive edge clock. +Creating register for signal `\memtest02.$mem2reg_rd$\mem2$memory_ref.v:71$16_ADDR' using process `\memtest02.$proc$memory_ref.v:53$26'. + created $dff cell `$procdff$1277' with positive edge clock. +Creating register for signal `\memtest02.$mem2reg_rd$\mem2$memory_ref.v:71$16_DATA' using process `\memtest02.$proc$memory_ref.v:53$26'. + created $dff cell `$procdff$1278' with positive edge clock. +Creating register for signal `\memtest02.$memwr$\mem1$memory_ref.v:55$18_EN' using process `\memtest02.$proc$memory_ref.v:53$26'. + created $dff cell `$procdff$1279' with positive edge clock. +Creating register for signal `\memtest02.$memwr$\mem1$memory_ref.v:56$19_EN' using process `\memtest02.$proc$memory_ref.v:53$26'. + created $dff cell `$procdff$1280' with positive edge clock. +Creating register for signal `\memtest02.$memwr$\mem1$memory_ref.v:57$20_EN' using process `\memtest02.$proc$memory_ref.v:53$26'. + created $dff cell `$procdff$1281' with positive edge clock. +Creating register for signal `\memtest02.$memwr$\mem1$memory_ref.v:63$21_EN' using process `\memtest02.$proc$memory_ref.v:53$26'. + created $dff cell `$procdff$1282' with positive edge clock. +Creating register for signal `\memtest02.$memwr$\mem1$memory_ref.v:64$22_EN' using process `\memtest02.$proc$memory_ref.v:53$26'. + created $dff cell `$procdff$1283' with positive edge clock. +Creating register for signal `\memtest02.$memwr$\mem1$memory_ref.v:65$23_EN' using process `\memtest02.$proc$memory_ref.v:53$26'. + created $dff cell `$procdff$1284' with positive edge clock. +Creating register for signal `\memtest02.$mem2bits$\mem1$memory_ref.v:70$24' using process `\memtest02.$proc$memory_ref.v:53$26'. + created $dff cell `$procdff$1285' with positive edge clock. +Creating register for signal `\memtest01.\rd_value' using process `\memtest01.$proc$memory_ref.v:32$14'. + created $dff cell `$procdff$1286' with positive edge clock. +Creating register for signal `\memtest01.$memwr$\data$memory_ref.v:30$6_ADDR' using process `\memtest01.$proc$memory_ref.v:28$7'. + created $dff cell `$procdff$1287' with positive edge clock. +Creating register for signal `\memtest01.$memwr$\data$memory_ref.v:30$6_DATA' using process `\memtest01.$proc$memory_ref.v:28$7'. + created $dff cell `$procdff$1288' with positive edge clock. +Creating register for signal `\memtest01.$memwr$\data$memory_ref.v:30$6_EN' using process `\memtest01.$proc$memory_ref.v:28$7'. + created $dff cell `$procdff$1289' with positive edge clock. +Creating register for signal `\memtest00.\mem[0]' using process `\memtest00.$proc$memory_ref.v:8$5'. + created $dff cell `$procdff$1290' with positive edge clock. + +4.1.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +4.1.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 1 empty switch in `\memtest13.$proc$memory_ref.v:304$430'. +Removing empty process `memtest13.$proc$memory_ref.v:304$430'. +Removing empty process `memtest12.$proc$memory_ref.v:287$415'. +Found and cleaned up 1 empty switch in `\memtest11.$proc$memory_ref.v:270$399'. +Removing empty process `memtest11.$proc$memory_ref.v:270$399'. +Removing empty process `memtest10.$proc$memory_ref.v:248$395'. +Found and cleaned up 1 empty switch in `\memtest09.$proc$memory_ref.v:235$379'. +Removing empty process `memtest09.$proc$memory_ref.v:235$379'. +Found and cleaned up 1 empty switch in `\memtest09.$proc$memory_ref.v:229$369'. +Removing empty process `memtest09.$proc$memory_ref.v:229$369'. +Removing empty process `memtest08.$proc$memory_ref.v:213$358'. +Removing empty process `memtest07.$proc$memory_ref.v:202$348'. +Found and cleaned up 1 empty switch in `\memtest06_async.$proc$memory_ref.v:0$344'. +Removing empty process `memtest06_async.$proc$memory_ref.v:0$344'. +Found and cleaned up 5 empty switches in `\memtest06_async.$proc$memory_ref.v:174$198'. +Removing empty process `memtest06_async.$proc$memory_ref.v:174$198'. +Found and cleaned up 1 empty switch in `\memtest06_sync.$proc$memory_ref.v:150$118'. +Removing empty process `memtest06_sync.$proc$memory_ref.v:150$118'. +Found and cleaned up 4 empty switches in `\memtest05.$proc$memory_ref.v:131$76'. +Removing empty process `memtest05.$proc$memory_ref.v:131$76'. +Found and cleaned up 1 empty switch in `\memtest04.$proc$memory_ref.v:108$64'. +Removing empty process `memtest04.$proc$memory_ref.v:108$64'. +Found and cleaned up 1 empty switch in `\memtest03.$proc$memory_ref.v:89$55'. +Removing empty process `memtest03.$proc$memory_ref.v:89$55'. +Removing empty process `memtest02.$proc$memory_ref.v:0$51'. +Found and cleaned up 1 empty switch in `\memtest02.$proc$memory_ref.v:0$48'. +Removing empty process `memtest02.$proc$memory_ref.v:0$48'. +Found and cleaned up 3 empty switches in `\memtest02.$proc$memory_ref.v:53$26'. +Removing empty process `memtest02.$proc$memory_ref.v:53$26'. +Removing empty process `memtest01.$proc$memory_ref.v:32$14'. +Found and cleaned up 1 empty switch in `\memtest01.$proc$memory_ref.v:28$7'. +Removing empty process `memtest01.$proc$memory_ref.v:28$7'. +Found and cleaned up 2 empty switches in `\memtest00.$proc$memory_ref.v:8$5'. +Removing empty process `memtest00.$proc$memory_ref.v:8$5'. +Cleaned up 24 empty switches. + +4.1.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module memtest13. +Optimizing module memtest12. +Optimizing module memtest11. +Optimizing module memtest10. +Optimizing module memtest09. +Optimizing module memtest08. +Optimizing module memtest07. +Optimizing module memtest06_async. + +Optimizing module memtest06_sync. +Optimizing module memtest05. +Optimizing module memtest04. +Optimizing module memtest03. +Optimizing module memtest02. + +Optimizing module memtest01. +Optimizing module memtest00. + +4.2. Executing OPT_EXPR pass (perform const folding). +Optimizing module memtest13. + +Optimizing module memtest12. +Optimizing module memtest11. +Optimizing module memtest10. +Optimizing module memtest09. +Optimizing module memtest08. + +Optimizing module memtest07. + +Optimizing module memtest06_async. +Optimizing module memtest06_sync. +Optimizing module memtest05. +Optimizing module memtest04. +Optimizing module memtest03. +Optimizing module memtest02. +Optimizing module memtest01. +Optimizing module memtest00. + +4.3. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memtest13.. +Finding unused cells or wires in module \memtest12.. +Finding unused cells or wires in module \memtest11.. +Finding unused cells or wires in module \memtest10.. +Finding unused cells or wires in module \memtest09.. +Finding unused cells or wires in module \memtest08.. +Finding unused cells or wires in module \memtest07.. +Finding unused cells or wires in module \memtest06_async.. +Finding unused cells or wires in module \memtest06_sync.. +Finding unused cells or wires in module \memtest05.. +Finding unused cells or wires in module \memtest04.. +Finding unused cells or wires in module \memtest03.. +Finding unused cells or wires in module \memtest02.. +Finding unused cells or wires in module \memtest01.. +Finding unused cells or wires in module \memtest00.. +Removed 199 unused cells and 641 unused wires. + + +4.4. Executing CHECK pass (checking for obvious problems). +Checking module memtest00... +Checking module memtest01... +Checking module memtest02... +Warning: Wire memtest02.\mem2[3] [7] is used but has no driver. +Warning: Wire memtest02.\mem2[3] [6] is used but has no driver. +Warning: Wire memtest02.\mem2[3] [5] is used but has no driver. +Warning: Wire memtest02.\mem2[3] [4] is used but has no driver. +Warning: Wire memtest02.\mem2[3] [3] is used but has no driver. +Warning: Wire memtest02.\mem2[3] [2] is used but has no driver. +Warning: Wire memtest02.\mem2[3] [1] is used but has no driver. +Warning: Wire memtest02.\mem2[3] [0] is used but has no driver. +Checking module memtest03... +Checking module memtest04... +Checking module memtest05... +Checking module memtest06_async... +Checking module memtest06_sync... +Checking module memtest07... +Checking module memtest08... +Checking module memtest09... +Checking module memtest10... +Checking module memtest11... +Checking module memtest12... +Checking module memtest13... +Found and reported 8 problems. + +4.5. Executing OPT pass (performing simple optimizations). + +4.5.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module memtest00. +Optimizing module memtest01. +Optimizing module memtest02. +Optimizing module memtest03. +Optimizing module memtest04. +Optimizing module memtest05. +Optimizing module memtest06_async. +Optimizing module memtest06_sync. +Optimizing module memtest07. +Optimizing module memtest08. +Optimizing module memtest09. +Optimizing module memtest10. +Optimizing module memtest11. +Optimizing module memtest12. +Optimizing module memtest13. + +4.5.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memtest00'. +Finding identical cells in module `\memtest01'. +Finding identical cells in module `\memtest02'. + +Finding identical cells in module `\memtest03'. +Finding identical cells in module `\memtest04'. +Finding identical cells in module `\memtest05'. +Finding identical cells in module `\memtest06_async'. + +Finding identical cells in module `\memtest06_sync'. + +Finding identical cells in module `\memtest07'. +Finding identical cells in module `\memtest08'. + +Finding identical cells in module `\memtest09'. + +Finding identical cells in module `\memtest10'. +Finding identical cells in module `\memtest11'. +Finding identical cells in module `\memtest12'. +Finding identical cells in module `\memtest13'. + +Removed a total of 259 cells. + +4.5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \memtest00.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest01.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest02.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest03.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest04.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest05.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest06_async.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 9/9 on $pmux $procmux$801. +Running muxtree optimizer on module \memtest06_sync.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest07.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest08.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest09.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest10.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest11.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest12.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest13.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 1 multiplexer ports. + + +4.5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \memtest00. + Optimizing cells in module \memtest01. + Consolidated identical input bits for $mux cell $procmux$1058: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\data$memory_ref.v:30$6_EN[7:0]$10 + New ports: A=1'0, B=1'1, Y=$0$memwr$\data$memory_ref.v:30$6_EN[7:0]$10 [0] + New connections: $0$memwr$\data$memory_ref.v:30$6_EN[7:0]$10 [7:1] = { $0$memwr$\data$memory_ref.v:30$6_EN[7:0]$10 [0] $0$memwr$\data$memory_ref.v:30$6_EN[7:0]$10 [0] $0$memwr$\data$memory_ref.v:30$6_EN[7:0]$10 [0] $0$memwr$\data$memory_ref.v:30$6_EN[7:0]$10 [0] $0$memwr$\data$memory_ref.v:30$6_EN[7:0]$10 [0] $0$memwr$\data$memory_ref.v:30$6_EN[7:0]$10 [0] $0$memwr$\data$memory_ref.v:30$6_EN[7:0]$10 [0] } + Optimizing cells in module \memtest01. + Optimizing cells in module \memtest02. + Consolidated identical input bits for $mux cell $procmux$1022: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\mem1$memory_ref.v:65$23_EN[7:0]$34 + New ports: A=1'0, B=1'1, Y=$0$memwr$\mem1$memory_ref.v:65$23_EN[7:0]$34 [0] + New connections: $0$memwr$\mem1$memory_ref.v:65$23_EN[7:0]$34 [7:1] = { $0$memwr$\mem1$memory_ref.v:65$23_EN[7:0]$34 [0] $0$memwr$\mem1$memory_ref.v:65$23_EN[7:0]$34 [0] $0$memwr$\mem1$memory_ref.v:65$23_EN[7:0]$34 [0] $0$memwr$\mem1$memory_ref.v:65$23_EN[7:0]$34 [0] $0$memwr$\mem1$memory_ref.v:65$23_EN[7:0]$34 [0] $0$memwr$\mem1$memory_ref.v:65$23_EN[7:0]$34 [0] $0$memwr$\mem1$memory_ref.v:65$23_EN[7:0]$34 [0] } + Consolidated identical input bits for $mux cell $procmux$1025: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\mem1$memory_ref.v:64$22_EN[7:0]$33 + New ports: A=1'0, B=1'1, Y=$0$memwr$\mem1$memory_ref.v:64$22_EN[7:0]$33 [0] + New connections: $0$memwr$\mem1$memory_ref.v:64$22_EN[7:0]$33 [7:1] = { $0$memwr$\mem1$memory_ref.v:64$22_EN[7:0]$33 [0] $0$memwr$\mem1$memory_ref.v:64$22_EN[7:0]$33 [0] $0$memwr$\mem1$memory_ref.v:64$22_EN[7:0]$33 [0] $0$memwr$\mem1$memory_ref.v:64$22_EN[7:0]$33 [0] $0$memwr$\mem1$memory_ref.v:64$22_EN[7:0]$33 [0] $0$memwr$\mem1$memory_ref.v:64$22_EN[7:0]$33 [0] $0$memwr$\mem1$memory_ref.v:64$22_EN[7:0]$33 [0] } + Consolidated identical input bits for $mux cell $procmux$1028: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\mem1$memory_ref.v:63$21_EN[7:0]$32 + New ports: A=1'0, B=1'1, Y=$0$memwr$\mem1$memory_ref.v:63$21_EN[7:0]$32 [0] + New connections: $0$memwr$\mem1$memory_ref.v:63$21_EN[7:0]$32 [7:1] = { $0$memwr$\mem1$memory_ref.v:63$21_EN[7:0]$32 [0] $0$memwr$\mem1$memory_ref.v:63$21_EN[7:0]$32 [0] $0$memwr$\mem1$memory_ref.v:63$21_EN[7:0]$32 [0] $0$memwr$\mem1$memory_ref.v:63$21_EN[7:0]$32 [0] $0$memwr$\mem1$memory_ref.v:63$21_EN[7:0]$32 [0] $0$memwr$\mem1$memory_ref.v:63$21_EN[7:0]$32 [0] $0$memwr$\mem1$memory_ref.v:63$21_EN[7:0]$32 [0] } + Consolidated identical input bits for $mux cell $procmux$1031: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\mem1$memory_ref.v:57$20_EN[7:0]$31 + New ports: A=1'0, B=1'1, Y=$0$memwr$\mem1$memory_ref.v:57$20_EN[7:0]$31 [0] + New connections: $0$memwr$\mem1$memory_ref.v:57$20_EN[7:0]$31 [7:1] = { $0$memwr$\mem1$memory_ref.v:57$20_EN[7:0]$31 [0] $0$memwr$\mem1$memory_ref.v:57$20_EN[7:0]$31 [0] $0$memwr$\mem1$memory_ref.v:57$20_EN[7:0]$31 [0] $0$memwr$\mem1$memory_ref.v:57$20_EN[7:0]$31 [0] $0$memwr$\mem1$memory_ref.v:57$20_EN[7:0]$31 [0] $0$memwr$\mem1$memory_ref.v:57$20_EN[7:0]$31 [0] $0$memwr$\mem1$memory_ref.v:57$20_EN[7:0]$31 [0] } + Consolidated identical input bits for $mux cell $procmux$1034: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\mem1$memory_ref.v:56$19_EN[7:0]$30 + New ports: A=1'0, B=1'1, Y=$0$memwr$\mem1$memory_ref.v:56$19_EN[7:0]$30 [0] + New connections: $0$memwr$\mem1$memory_ref.v:56$19_EN[7:0]$30 [7:1] = { $0$memwr$\mem1$memory_ref.v:56$19_EN[7:0]$30 [0] $0$memwr$\mem1$memory_ref.v:56$19_EN[7:0]$30 [0] $0$memwr$\mem1$memory_ref.v:56$19_EN[7:0]$30 [0] $0$memwr$\mem1$memory_ref.v:56$19_EN[7:0]$30 [0] $0$memwr$\mem1$memory_ref.v:56$19_EN[7:0]$30 [0] $0$memwr$\mem1$memory_ref.v:56$19_EN[7:0]$30 [0] $0$memwr$\mem1$memory_ref.v:56$19_EN[7:0]$30 [0] } + Consolidated identical input bits for $mux cell $procmux$1037: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\mem1$memory_ref.v:55$18_EN[7:0]$29 + New ports: A=1'0, B=1'1, Y=$0$memwr$\mem1$memory_ref.v:55$18_EN[7:0]$29 [0] + New connections: $0$memwr$\mem1$memory_ref.v:55$18_EN[7:0]$29 [7:1] = { $0$memwr$\mem1$memory_ref.v:55$18_EN[7:0]$29 [0] $0$memwr$\mem1$memory_ref.v:55$18_EN[7:0]$29 [0] $0$memwr$\mem1$memory_ref.v:55$18_EN[7:0]$29 [0] $0$memwr$\mem1$memory_ref.v:55$18_EN[7:0]$29 [0] $0$memwr$\mem1$memory_ref.v:55$18_EN[7:0]$29 [0] $0$memwr$\mem1$memory_ref.v:55$18_EN[7:0]$29 [0] $0$memwr$\mem1$memory_ref.v:55$18_EN[7:0]$29 [0] } + Optimizing cells in module \memtest02. + Optimizing cells in module \memtest03. + Consolidated identical input bits for $mux cell $procmux$1003: + Old ports: A=4'0000, B=4'1111, Y=$0$memwr$\memory$memory_ref.v:91$54_EN[3:0]$58 + New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$memory_ref.v:91$54_EN[3:0]$58 [0] + New connections: $0$memwr$\memory$memory_ref.v:91$54_EN[3:0]$58 [3:1] = { $0$memwr$\memory$memory_ref.v:91$54_EN[3:0]$58 [0] $0$memwr$\memory$memory_ref.v:91$54_EN[3:0]$58 [0] $0$memwr$\memory$memory_ref.v:91$54_EN[3:0]$58 [0] } + Optimizing cells in module \memtest03. + Optimizing cells in module \memtest04. + Consolidated identical input bits for $mux cell $procmux$994: + Old ports: A=4'0000, B=4'1111, Y=$0$memwr$\memory$memory_ref.v:110$63_EN[3:0]$67 + New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$memory_ref.v:110$63_EN[3:0]$67 [0] + New connections: $0$memwr$\memory$memory_ref.v:110$63_EN[3:0]$67 [3:1] = { $0$memwr$\memory$memory_ref.v:110$63_EN[3:0]$67 [0] $0$memwr$\memory$memory_ref.v:110$63_EN[3:0]$67 [0] $0$memwr$\memory$memory_ref.v:110$63_EN[3:0]$67 [0] } + Optimizing cells in module \memtest04. + Optimizing cells in module \memtest05. + Consolidated identical input bits for $mux cell $procmux$958: + Old ports: A=8'00000000, B=8'11000000, Y=$0$memwr$\mem$memory_ref.v:133$75_EN[7:0]$88 + New ports: A=1'0, B=1'1, Y=$0$memwr$\mem$memory_ref.v:133$75_EN[7:0]$88 [6] + New connections: { $0$memwr$\mem$memory_ref.v:133$75_EN[7:0]$88 [7] $0$memwr$\mem$memory_ref.v:133$75_EN[7:0]$88 [5:0] } = { $0$memwr$\mem$memory_ref.v:133$75_EN[7:0]$88 [6] 6'000000 } + Consolidated identical input bits for $mux cell $procmux$967: + Old ports: A=8'00000000, B=8'00110000, Y=$0$memwr$\mem$memory_ref.v:133$74_EN[7:0]$85 + New ports: A=1'0, B=1'1, Y=$0$memwr$\mem$memory_ref.v:133$74_EN[7:0]$85 [4] + New connections: { $0$memwr$\mem$memory_ref.v:133$74_EN[7:0]$85 [7:5] $0$memwr$\mem$memory_ref.v:133$74_EN[7:0]$85 [3:0] } = { 2'00 $0$memwr$\mem$memory_ref.v:133$74_EN[7:0]$85 [4] 4'0000 } + Consolidated identical input bits for $mux cell $procmux$976: + Old ports: A=8'00000000, B=8'00001100, Y=$0$memwr$\mem$memory_ref.v:133$73_EN[7:0]$82 + New ports: A=1'0, B=1'1, Y=$0$memwr$\mem$memory_ref.v:133$73_EN[7:0]$82 [2] + New connections: { $0$memwr$\mem$memory_ref.v:133$73_EN[7:0]$82 [7:3] $0$memwr$\mem$memory_ref.v:133$73_EN[7:0]$82 [1:0] } = { 4'0000 $0$memwr$\mem$memory_ref.v:133$73_EN[7:0]$82 [2] 2'00 } + Consolidated identical input bits for $mux cell $procmux$985: + Old ports: A=8'00000000, B=8'00000011, Y=$0$memwr$\mem$memory_ref.v:133$72_EN[7:0]$79 + New ports: A=1'0, B=1'1, Y=$0$memwr$\mem$memory_ref.v:133$72_EN[7:0]$79 [0] + New connections: $0$memwr$\mem$memory_ref.v:133$72_EN[7:0]$79 [7:1] = { 6'000000 $0$memwr$\mem$memory_ref.v:133$72_EN[7:0]$79 [0] } + Optimizing cells in module \memtest05. + Optimizing cells in module \memtest06_async. + New ctrl vector for $pmux cell $procmux$828: { $procmux$569_CMP $auto$opt_reduce.cc:134:opt_pmux$1332 } + New ctrl vector for $pmux cell $procmux$765: { $procmux$571_CMP $auto$opt_reduce.cc:134:opt_pmux$1334 } + New ctrl vector for $pmux cell $procmux$837: { $procmux$570_CMP $auto$opt_reduce.cc:134:opt_pmux$1336 } + New ctrl vector for $pmux cell $procmux$774: { $procmux$572_CMP $auto$opt_reduce.cc:134:opt_pmux$1338 } + New ctrl vector for $pmux cell $procmux$603: { $procmux$569_CMP $auto$opt_reduce.cc:134:opt_pmux$1340 } + New ctrl vector for $pmux cell $procmux$648: { $procmux$574_CMP $auto$opt_reduce.cc:134:opt_pmux$1342 } + New ctrl vector for $pmux cell $procmux$846: { $procmux$571_CMP $auto$opt_reduce.cc:134:opt_pmux$1344 } + New ctrl vector for $pmux cell $procmux$783: { $procmux$573_CMP $auto$opt_reduce.cc:134:opt_pmux$1346 } + New ctrl vector for $pmux cell $procmux$612: { $procmux$570_CMP $auto$opt_reduce.cc:134:opt_pmux$1348 } + New ctrl vector for $pmux cell $procmux$729: { $procmux$575_CMP $auto$opt_reduce.cc:134:opt_pmux$1350 } + New ctrl vector for $pmux cell $procmux$855: { $procmux$572_CMP $auto$opt_reduce.cc:134:opt_pmux$1352 } + New ctrl vector for $pmux cell $procmux$792: { $procmux$574_CMP $auto$opt_reduce.cc:134:opt_pmux$1354 } + New ctrl vector for $pmux cell $procmux$864: { $procmux$573_CMP $auto$opt_reduce.cc:134:opt_pmux$1356 } + New ctrl vector for $pmux cell $procmux$621: { $procmux$571_CMP $auto$opt_reduce.cc:134:opt_pmux$1358 } + New ctrl vector for $pmux cell $procmux$738: { $auto$opt_reduce.cc:134:opt_pmux$1360 $procmux$568_CMP } + New ctrl vector for $pmux cell $procmux$873: { $procmux$574_CMP $auto$opt_reduce.cc:134:opt_pmux$1362 } + New ctrl vector for $pmux cell $procmux$747: { $procmux$569_CMP $auto$opt_reduce.cc:134:opt_pmux$1364 } + New ctrl vector for $pmux cell $procmux$630: { $procmux$572_CMP $auto$opt_reduce.cc:134:opt_pmux$1366 } + New ctrl vector for $pmux cell $procmux$810: { $procmux$575_CMP $auto$opt_reduce.cc:134:opt_pmux$1368 } + New ctrl vector for $pmux cell $procmux$576: { $procmux$575_CMP $auto$opt_reduce.cc:134:opt_pmux$1370 } + New ctrl vector for $pmux cell $procmux$756: { $procmux$570_CMP $auto$opt_reduce.cc:134:opt_pmux$1372 } + New ctrl vector for $pmux cell $procmux$819: { $auto$opt_reduce.cc:134:opt_pmux$1374 $procmux$568_CMP } + New ctrl vector for $pmux cell $procmux$639: { $procmux$573_CMP $auto$opt_reduce.cc:134:opt_pmux$1376 } + New ctrl vector for $pmux cell $procmux$594: { $auto$opt_reduce.cc:134:opt_pmux$1378 $procmux$568_CMP } + Optimizing cells in module \memtest06_async. + Optimizing cells in module \memtest06_sync. + Consolidated identical input bits for $mux cell $procmux$886: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\test$memory_ref.v:153$109_EN[7:0]$126 + New ports: A=1'0, B=1'1, Y=$0$memwr$\test$memory_ref.v:153$109_EN[7:0]$126 [0] + New connections: $0$memwr$\test$memory_ref.v:153$109_EN[7:0]$126 [7:1] = { $0$memwr$\test$memory_ref.v:153$109_EN[7:0]$126 [0] $0$memwr$\test$memory_ref.v:153$109_EN[7:0]$126 [0] $0$memwr$\test$memory_ref.v:153$109_EN[7:0]$126 [0] $0$memwr$\test$memory_ref.v:153$109_EN[7:0]$126 [0] $0$memwr$\test$memory_ref.v:153$109_EN[7:0]$126 [0] $0$memwr$\test$memory_ref.v:153$109_EN[7:0]$126 [0] $0$memwr$\test$memory_ref.v:153$109_EN[7:0]$126 [0] } + Consolidated identical input bits for $mux cell $procmux$889: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\test$memory_ref.v:153$108_EN[7:0]$125 + New ports: A=1'0, B=1'1, Y=$0$memwr$\test$memory_ref.v:153$108_EN[7:0]$125 [0] + New connections: $0$memwr$\test$memory_ref.v:153$108_EN[7:0]$125 [7:1] = { $0$memwr$\test$memory_ref.v:153$108_EN[7:0]$125 [0] $0$memwr$\test$memory_ref.v:153$108_EN[7:0]$125 [0] $0$memwr$\test$memory_ref.v:153$108_EN[7:0]$125 [0] $0$memwr$\test$memory_ref.v:153$108_EN[7:0]$125 [0] $0$memwr$\test$memory_ref.v:153$108_EN[7:0]$125 [0] $0$memwr$\test$memory_ref.v:153$108_EN[7:0]$125 [0] $0$memwr$\test$memory_ref.v:153$108_EN[7:0]$125 [0] } + Consolidated identical input bits for $mux cell $procmux$892: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\test$memory_ref.v:153$107_EN[7:0]$124 + New ports: A=1'0, B=1'1, Y=$0$memwr$\test$memory_ref.v:153$107_EN[7:0]$124 [0] + New connections: $0$memwr$\test$memory_ref.v:153$107_EN[7:0]$124 [7:1] = { $0$memwr$\test$memory_ref.v:153$107_EN[7:0]$124 [0] $0$memwr$\test$memory_ref.v:153$107_EN[7:0]$124 [0] $0$memwr$\test$memory_ref.v:153$107_EN[7:0]$124 [0] $0$memwr$\test$memory_ref.v:153$107_EN[7:0]$124 [0] $0$memwr$\test$memory_ref.v:153$107_EN[7:0]$124 [0] $0$memwr$\test$memory_ref.v:153$107_EN[7:0]$124 [0] $0$memwr$\test$memory_ref.v:153$107_EN[7:0]$124 [0] } + Consolidated identical input bits for $mux cell $procmux$895: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\test$memory_ref.v:153$106_EN[7:0]$123 + New ports: A=1'0, B=1'1, Y=$0$memwr$\test$memory_ref.v:153$106_EN[7:0]$123 [0] + New connections: $0$memwr$\test$memory_ref.v:153$106_EN[7:0]$123 [7:1] = { $0$memwr$\test$memory_ref.v:153$106_EN[7:0]$123 [0] $0$memwr$\test$memory_ref.v:153$106_EN[7:0]$123 [0] $0$memwr$\test$memory_ref.v:153$106_EN[7:0]$123 [0] $0$memwr$\test$memory_ref.v:153$106_EN[7:0]$123 [0] $0$memwr$\test$memory_ref.v:153$106_EN[7:0]$123 [0] $0$memwr$\test$memory_ref.v:153$106_EN[7:0]$123 [0] $0$memwr$\test$memory_ref.v:153$106_EN[7:0]$123 [0] } + Consolidated identical input bits for $mux cell $procmux$898: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\test$memory_ref.v:153$105_EN[7:0]$122 + New ports: A=1'0, B=1'1, Y=$0$memwr$\test$memory_ref.v:153$105_EN[7:0]$122 [0] + New connections: $0$memwr$\test$memory_ref.v:153$105_EN[7:0]$122 [7:1] = { $0$memwr$\test$memory_ref.v:153$105_EN[7:0]$122 [0] $0$memwr$\test$memory_ref.v:153$105_EN[7:0]$122 [0] $0$memwr$\test$memory_ref.v:153$105_EN[7:0]$122 [0] $0$memwr$\test$memory_ref.v:153$105_EN[7:0]$122 [0] $0$memwr$\test$memory_ref.v:153$105_EN[7:0]$122 [0] $0$memwr$\test$memory_ref.v:153$105_EN[7:0]$122 [0] $0$memwr$\test$memory_ref.v:153$105_EN[7:0]$122 [0] } + Consolidated identical input bits for $mux cell $procmux$901: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\test$memory_ref.v:153$104_EN[7:0]$121 + New ports: A=1'0, B=1'1, Y=$0$memwr$\test$memory_ref.v:153$104_EN[7:0]$121 [0] + New connections: $0$memwr$\test$memory_ref.v:153$104_EN[7:0]$121 [7:1] = { $0$memwr$\test$memory_ref.v:153$104_EN[7:0]$121 [0] $0$memwr$\test$memory_ref.v:153$104_EN[7:0]$121 [0] $0$memwr$\test$memory_ref.v:153$104_EN[7:0]$121 [0] $0$memwr$\test$memory_ref.v:153$104_EN[7:0]$121 [0] $0$memwr$\test$memory_ref.v:153$104_EN[7:0]$121 [0] $0$memwr$\test$memory_ref.v:153$104_EN[7:0]$121 [0] $0$memwr$\test$memory_ref.v:153$104_EN[7:0]$121 [0] } + Consolidated identical input bits for $mux cell $procmux$904: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\test$memory_ref.v:153$103_EN[7:0]$120 + New ports: A=1'0, B=1'1, Y=$0$memwr$\test$memory_ref.v:153$103_EN[7:0]$120 [0] + New connections: $0$memwr$\test$memory_ref.v:153$103_EN[7:0]$120 [7:1] = { $0$memwr$\test$memory_ref.v:153$103_EN[7:0]$120 [0] $0$memwr$\test$memory_ref.v:153$103_EN[7:0]$120 [0] $0$memwr$\test$memory_ref.v:153$103_EN[7:0]$120 [0] $0$memwr$\test$memory_ref.v:153$103_EN[7:0]$120 [0] $0$memwr$\test$memory_ref.v:153$103_EN[7:0]$120 [0] $0$memwr$\test$memory_ref.v:153$103_EN[7:0]$120 [0] $0$memwr$\test$memory_ref.v:153$103_EN[7:0]$120 [0] } + Consolidated identical input bits for $mux cell $procmux$907: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\test$memory_ref.v:153$102_EN[7:0]$119 + New ports: A=1'0, B=1'1, Y=$0$memwr$\test$memory_ref.v:153$102_EN[7:0]$119 [0] + New connections: $0$memwr$\test$memory_ref.v:153$102_EN[7:0]$119 [7:1] = { $0$memwr$\test$memory_ref.v:153$102_EN[7:0]$119 [0] $0$memwr$\test$memory_ref.v:153$102_EN[7:0]$119 [0] $0$memwr$\test$memory_ref.v:153$102_EN[7:0]$119 [0] $0$memwr$\test$memory_ref.v:153$102_EN[7:0]$119 [0] $0$memwr$\test$memory_ref.v:153$102_EN[7:0]$119 [0] $0$memwr$\test$memory_ref.v:153$102_EN[7:0]$119 [0] $0$memwr$\test$memory_ref.v:153$102_EN[7:0]$119 [0] } + Consolidated identical input bits for $mux cell $procmux$922: + Old ports: A=8'01000000, B=8'00000000, Y=$0$memwr$\test$memory_ref.v:158$115_EN[7:0]$138 + New ports: A=1'1, B=1'0, Y=$0$memwr$\test$memory_ref.v:158$115_EN[7:0]$138 [6] + New connections: { $0$memwr$\test$memory_ref.v:158$115_EN[7:0]$138 [7] $0$memwr$\test$memory_ref.v:158$115_EN[7:0]$138 [5:0] } = 7'0000000 + Consolidated identical input bits for $mux cell $procmux$934: + Old ports: A=8'00001000, B=8'00000000, Y=$0$memwr$\test$memory_ref.v:157$113_EN[7:0]$134 + New ports: A=1'1, B=1'0, Y=$0$memwr$\test$memory_ref.v:157$113_EN[7:0]$134 [3] + New connections: { $0$memwr$\test$memory_ref.v:157$113_EN[7:0]$134 [7:4] $0$memwr$\test$memory_ref.v:157$113_EN[7:0]$134 [2:0] } = 7'0000000 + Consolidated identical input bits for $mux cell $procmux$943: + Old ports: A=8'00100000, B=8'00000000, Y=$0$memwr$\test$memory_ref.v:156$112_EN[7:0]$131 + New ports: A=1'1, B=1'0, Y=$0$memwr$\test$memory_ref.v:156$112_EN[7:0]$131 [5] + New connections: { $0$memwr$\test$memory_ref.v:156$112_EN[7:0]$131 [7:6] $0$memwr$\test$memory_ref.v:156$112_EN[7:0]$131 [4:0] } = 7'0000000 + Consolidated identical input bits for $mux cell $procmux$952: + Old ports: A=8'00000100, B=8'00000000, Y=$0$memwr$\test$memory_ref.v:155$110_EN[7:0]$128 + New ports: A=1'1, B=1'0, Y=$0$memwr$\test$memory_ref.v:155$110_EN[7:0]$128 [2] + New connections: { $0$memwr$\test$memory_ref.v:155$110_EN[7:0]$128 [7:3] $0$memwr$\test$memory_ref.v:155$110_EN[7:0]$128 [1:0] } = 7'0000000 + Optimizing cells in module \memtest06_sync. + Optimizing cells in module \memtest07. + Optimizing cells in module \memtest08. + Optimizing cells in module \memtest09. + Consolidated identical input bits for $mux cell $procmux$550: + Old ports: A=4'0000, B=4'1111, Y=$0$memwr$\memory$memory_ref.v:237$368_EN[3:0]$382 + New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$memory_ref.v:237$368_EN[3:0]$382 [0] + New connections: $0$memwr$\memory$memory_ref.v:237$368_EN[3:0]$382 [3:1] = { $0$memwr$\memory$memory_ref.v:237$368_EN[3:0]$382 [0] $0$memwr$\memory$memory_ref.v:237$368_EN[3:0]$382 [0] $0$memwr$\memory$memory_ref.v:237$368_EN[3:0]$382 [0] } + Consolidated identical input bits for $mux cell $procmux$559: + Old ports: A=4'0000, B=4'1111, Y=$0$memwr$\memory$memory_ref.v:231$367_EN[3:0]$372 + New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$memory_ref.v:231$367_EN[3:0]$372 [0] + New connections: $0$memwr$\memory$memory_ref.v:231$367_EN[3:0]$372 [3:1] = { $0$memwr$\memory$memory_ref.v:231$367_EN[3:0]$372 [0] $0$memwr$\memory$memory_ref.v:231$367_EN[3:0]$372 [0] $0$memwr$\memory$memory_ref.v:231$367_EN[3:0]$372 [0] } + Optimizing cells in module \memtest09. + Optimizing cells in module \memtest10. + Optimizing cells in module \memtest11. + Consolidated identical input bits for $mux cell $procmux$532: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\mem$memory_ref.v:272$396_EN[7:0]$402 + New ports: A=1'0, B=1'1, Y=$0$memwr$\mem$memory_ref.v:272$396_EN[7:0]$402 [0] + New connections: $0$memwr$\mem$memory_ref.v:272$396_EN[7:0]$402 [7:1] = { $0$memwr$\mem$memory_ref.v:272$396_EN[7:0]$402 [0] $0$memwr$\mem$memory_ref.v:272$396_EN[7:0]$402 [0] $0$memwr$\mem$memory_ref.v:272$396_EN[7:0]$402 [0] $0$memwr$\mem$memory_ref.v:272$396_EN[7:0]$402 [0] $0$memwr$\mem$memory_ref.v:272$396_EN[7:0]$402 [0] $0$memwr$\mem$memory_ref.v:272$396_EN[7:0]$402 [0] $0$memwr$\mem$memory_ref.v:272$396_EN[7:0]$402 [0] } + Consolidated identical input bits for $mux cell $procmux$541: + Old ports: A=8'11111111, B=8'00000000, Y=$0$memwr$\mem$memory_ref.v:274$397_EN[7:0]$405 + New ports: A=1'1, B=1'0, Y=$0$memwr$\mem$memory_ref.v:274$397_EN[7:0]$405 [0] + New connections: $0$memwr$\mem$memory_ref.v:274$397_EN[7:0]$405 [7:1] = { $0$memwr$\mem$memory_ref.v:274$397_EN[7:0]$405 [0] $0$memwr$\mem$memory_ref.v:274$397_EN[7:0]$405 [0] $0$memwr$\mem$memory_ref.v:274$397_EN[7:0]$405 [0] $0$memwr$\mem$memory_ref.v:274$397_EN[7:0]$405 [0] $0$memwr$\mem$memory_ref.v:274$397_EN[7:0]$405 [0] $0$memwr$\mem$memory_ref.v:274$397_EN[7:0]$405 [0] $0$memwr$\mem$memory_ref.v:274$397_EN[7:0]$405 [0] } + Optimizing cells in module \memtest11. + Optimizing cells in module \memtest12. + Optimizing cells in module \memtest13. + Consolidated identical input bits for $mux cell $procmux$478: + Old ports: A=27'000000000000000000000000000, B=27'111111111111111111111111111, Y=$0$memwr$\mem$memory_ref.v:309$424_EN[26:0]$434 + New ports: A=1'0, B=1'1, Y=$0$memwr$\mem$memory_ref.v:309$424_EN[26:0]$434 [0] + New connections: $0$memwr$\mem$memory_ref.v:309$424_EN[26:0]$434 [26:1] = { $0$memwr$\mem$memory_ref.v:309$424_EN[26:0]$434 [0] $0$memwr$\mem$memory_ref.v:309$424_EN[26:0]$434 [0] $0$memwr$\mem$memory_ref.v:309$424_EN[26:0]$434 [0] $0$memwr$\mem$memory_ref.v:309$424_EN[26:0]$434 [0] $0$memwr$\mem$memory_ref.v:309$424_EN[26:0]$434 [0] $0$memwr$\mem$memory_ref.v:309$424_EN[26:0]$434 [0] $0$memwr$\mem$memory_ref.v:309$424_EN[26:0]$434 [0] $0$memwr$\mem$memory_ref.v:309$424_EN[26:0]$434 [0] $0$memwr$\mem$memory_ref.v:309$424_EN[26:0]$434 [0] $0$memwr$\mem$memory_ref.v:309$424_EN[26:0]$434 [0] $0$memwr$\mem$memory_ref.v:309$424_EN[26:0]$434 [0] $0$memwr$\mem$memory_ref.v:309$424_EN[26:0]$434 [0] $0$memwr$\mem$memory_ref.v:309$424_EN[26:0]$434 [0] $0$memwr$\mem$memory_ref.v:309$424_EN[26:0]$434 [0] $0$memwr$\mem$memory_ref.v:309$424_EN[26:0]$434 [0] $0$memwr$\mem$memory_ref.v:309$424_EN[26:0]$434 [0] $0$memwr$\mem$memory_ref.v:309$424_EN[26:0]$434 [0] $0$memwr$\mem$memory_ref.v:309$424_EN[26:0]$434 [0] $0$memwr$\mem$memory_ref.v:309$424_EN[26:0]$434 [0] $0$memwr$\mem$memory_ref.v:309$424_EN[26:0]$434 [0] $0$memwr$\mem$memory_ref.v:309$424_EN[26:0]$434 [0] $0$memwr$\mem$memory_ref.v:309$424_EN[26:0]$434 [0] $0$memwr$\mem$memory_ref.v:309$424_EN[26:0]$434 [0] $0$memwr$\mem$memory_ref.v:309$424_EN[26:0]$434 [0] $0$memwr$\mem$memory_ref.v:309$424_EN[26:0]$434 [0] $0$memwr$\mem$memory_ref.v:309$424_EN[26:0]$434 [0] } + Consolidated identical input bits for $mux cell $procmux$481: + Old ports: A=27'000000000000000000000000000, B=27'111111111111111111111111111, Y=$0$memwr$\mem$memory_ref.v:308$423_EN[26:0]$433 + New ports: A=1'0, B=1'1, Y=$0$memwr$\mem$memory_ref.v:308$423_EN[26:0]$433 [0] + New connections: $0$memwr$\mem$memory_ref.v:308$423_EN[26:0]$433 [26:1] = { $0$memwr$\mem$memory_ref.v:308$423_EN[26:0]$433 [0] $0$memwr$\mem$memory_ref.v:308$423_EN[26:0]$433 [0] $0$memwr$\mem$memory_ref.v:308$423_EN[26:0]$433 [0] $0$memwr$\mem$memory_ref.v:308$423_EN[26:0]$433 [0] $0$memwr$\mem$memory_ref.v:308$423_EN[26:0]$433 [0] $0$memwr$\mem$memory_ref.v:308$423_EN[26:0]$433 [0] $0$memwr$\mem$memory_ref.v:308$423_EN[26:0]$433 [0] $0$memwr$\mem$memory_ref.v:308$423_EN[26:0]$433 [0] $0$memwr$\mem$memory_ref.v:308$423_EN[26:0]$433 [0] $0$memwr$\mem$memory_ref.v:308$423_EN[26:0]$433 [0] $0$memwr$\mem$memory_ref.v:308$423_EN[26:0]$433 [0] $0$memwr$\mem$memory_ref.v:308$423_EN[26:0]$433 [0] $0$memwr$\mem$memory_ref.v:308$423_EN[26:0]$433 [0] $0$memwr$\mem$memory_ref.v:308$423_EN[26:0]$433 [0] $0$memwr$\mem$memory_ref.v:308$423_EN[26:0]$433 [0] $0$memwr$\mem$memory_ref.v:308$423_EN[26:0]$433 [0] $0$memwr$\mem$memory_ref.v:308$423_EN[26:0]$433 [0] $0$memwr$\mem$memory_ref.v:308$423_EN[26:0]$433 [0] $0$memwr$\mem$memory_ref.v:308$423_EN[26:0]$433 [0] $0$memwr$\mem$memory_ref.v:308$423_EN[26:0]$433 [0] $0$memwr$\mem$memory_ref.v:308$423_EN[26:0]$433 [0] $0$memwr$\mem$memory_ref.v:308$423_EN[26:0]$433 [0] $0$memwr$\mem$memory_ref.v:308$423_EN[26:0]$433 [0] $0$memwr$\mem$memory_ref.v:308$423_EN[26:0]$433 [0] $0$memwr$\mem$memory_ref.v:308$423_EN[26:0]$433 [0] $0$memwr$\mem$memory_ref.v:308$423_EN[26:0]$433 [0] } + Consolidated identical input bits for $mux cell $procmux$484: + Old ports: A=27'000000000000000000000000000, B=27'111111111111111111111111111, Y=$0$memwr$\mem$memory_ref.v:307$422_EN[26:0]$432 + New ports: A=1'0, B=1'1, Y=$0$memwr$\mem$memory_ref.v:307$422_EN[26:0]$432 [0] + New connections: $0$memwr$\mem$memory_ref.v:307$422_EN[26:0]$432 [26:1] = { $0$memwr$\mem$memory_ref.v:307$422_EN[26:0]$432 [0] $0$memwr$\mem$memory_ref.v:307$422_EN[26:0]$432 [0] $0$memwr$\mem$memory_ref.v:307$422_EN[26:0]$432 [0] $0$memwr$\mem$memory_ref.v:307$422_EN[26:0]$432 [0] $0$memwr$\mem$memory_ref.v:307$422_EN[26:0]$432 [0] $0$memwr$\mem$memory_ref.v:307$422_EN[26:0]$432 [0] $0$memwr$\mem$memory_ref.v:307$422_EN[26:0]$432 [0] $0$memwr$\mem$memory_ref.v:307$422_EN[26:0]$432 [0] $0$memwr$\mem$memory_ref.v:307$422_EN[26:0]$432 [0] $0$memwr$\mem$memory_ref.v:307$422_EN[26:0]$432 [0] $0$memwr$\mem$memory_ref.v:307$422_EN[26:0]$432 [0] $0$memwr$\mem$memory_ref.v:307$422_EN[26:0]$432 [0] $0$memwr$\mem$memory_ref.v:307$422_EN[26:0]$432 [0] $0$memwr$\mem$memory_ref.v:307$422_EN[26:0]$432 [0] $0$memwr$\mem$memory_ref.v:307$422_EN[26:0]$432 [0] $0$memwr$\mem$memory_ref.v:307$422_EN[26:0]$432 [0] $0$memwr$\mem$memory_ref.v:307$422_EN[26:0]$432 [0] $0$memwr$\mem$memory_ref.v:307$422_EN[26:0]$432 [0] $0$memwr$\mem$memory_ref.v:307$422_EN[26:0]$432 [0] $0$memwr$\mem$memory_ref.v:307$422_EN[26:0]$432 [0] $0$memwr$\mem$memory_ref.v:307$422_EN[26:0]$432 [0] $0$memwr$\mem$memory_ref.v:307$422_EN[26:0]$432 [0] $0$memwr$\mem$memory_ref.v:307$422_EN[26:0]$432 [0] $0$memwr$\mem$memory_ref.v:307$422_EN[26:0]$432 [0] $0$memwr$\mem$memory_ref.v:307$422_EN[26:0]$432 [0] $0$memwr$\mem$memory_ref.v:307$422_EN[26:0]$432 [0] } + Consolidated identical input bits for $mux cell $procmux$487: + Old ports: A=27'000000000000000000000000000, B=27'111111111111111111111111111, Y=$0$memwr$\mem$memory_ref.v:306$421_EN[26:0]$431 + New ports: A=1'0, B=1'1, Y=$0$memwr$\mem$memory_ref.v:306$421_EN[26:0]$431 [0] + New connections: $0$memwr$\mem$memory_ref.v:306$421_EN[26:0]$431 [26:1] = { $0$memwr$\mem$memory_ref.v:306$421_EN[26:0]$431 [0] $0$memwr$\mem$memory_ref.v:306$421_EN[26:0]$431 [0] $0$memwr$\mem$memory_ref.v:306$421_EN[26:0]$431 [0] $0$memwr$\mem$memory_ref.v:306$421_EN[26:0]$431 [0] $0$memwr$\mem$memory_ref.v:306$421_EN[26:0]$431 [0] $0$memwr$\mem$memory_ref.v:306$421_EN[26:0]$431 [0] $0$memwr$\mem$memory_ref.v:306$421_EN[26:0]$431 [0] $0$memwr$\mem$memory_ref.v:306$421_EN[26:0]$431 [0] $0$memwr$\mem$memory_ref.v:306$421_EN[26:0]$431 [0] $0$memwr$\mem$memory_ref.v:306$421_EN[26:0]$431 [0] $0$memwr$\mem$memory_ref.v:306$421_EN[26:0]$431 [0] $0$memwr$\mem$memory_ref.v:306$421_EN[26:0]$431 [0] $0$memwr$\mem$memory_ref.v:306$421_EN[26:0]$431 [0] $0$memwr$\mem$memory_ref.v:306$421_EN[26:0]$431 [0] $0$memwr$\mem$memory_ref.v:306$421_EN[26:0]$431 [0] $0$memwr$\mem$memory_ref.v:306$421_EN[26:0]$431 [0] $0$memwr$\mem$memory_ref.v:306$421_EN[26:0]$431 [0] $0$memwr$\mem$memory_ref.v:306$421_EN[26:0]$431 [0] $0$memwr$\mem$memory_ref.v:306$421_EN[26:0]$431 [0] $0$memwr$\mem$memory_ref.v:306$421_EN[26:0]$431 [0] $0$memwr$\mem$memory_ref.v:306$421_EN[26:0]$431 [0] $0$memwr$\mem$memory_ref.v:306$421_EN[26:0]$431 [0] $0$memwr$\mem$memory_ref.v:306$421_EN[26:0]$431 [0] $0$memwr$\mem$memory_ref.v:306$421_EN[26:0]$431 [0] $0$memwr$\mem$memory_ref.v:306$421_EN[26:0]$431 [0] $0$memwr$\mem$memory_ref.v:306$421_EN[26:0]$431 [0] } + Consolidated identical input bits for $mux cell $procmux$505: + Old ports: A=27'000000000000000001111000000, B=27'000000000000000000000000000, Y=$0$memwr$\mem$memory_ref.v:312$426_EN[26:0]$440 + New ports: A=1'1, B=1'0, Y=$0$memwr$\mem$memory_ref.v:312$426_EN[26:0]$440 [6] + New connections: { $0$memwr$\mem$memory_ref.v:312$426_EN[26:0]$440 [26:7] $0$memwr$\mem$memory_ref.v:312$426_EN[26:0]$440 [5:0] } = { 17'00000000000000000 $0$memwr$\mem$memory_ref.v:312$426_EN[26:0]$440 [6] $0$memwr$\mem$memory_ref.v:312$426_EN[26:0]$440 [6] $0$memwr$\mem$memory_ref.v:312$426_EN[26:0]$440 [6] 6'000000 } + Consolidated identical input bits for $mux cell $procmux$514: + Old ports: A=27'111111111111111111111111111, B=27'000000000000000000000000000, Y=$0$memwr$\mem$memory_ref.v:311$425_EN[26:0]$437 + New ports: A=1'1, B=1'0, Y=$0$memwr$\mem$memory_ref.v:311$425_EN[26:0]$437 [0] + New connections: $0$memwr$\mem$memory_ref.v:311$425_EN[26:0]$437 [26:1] = { $0$memwr$\mem$memory_ref.v:311$425_EN[26:0]$437 [0] $0$memwr$\mem$memory_ref.v:311$425_EN[26:0]$437 [0] $0$memwr$\mem$memory_ref.v:311$425_EN[26:0]$437 [0] $0$memwr$\mem$memory_ref.v:311$425_EN[26:0]$437 [0] $0$memwr$\mem$memory_ref.v:311$425_EN[26:0]$437 [0] $0$memwr$\mem$memory_ref.v:311$425_EN[26:0]$437 [0] $0$memwr$\mem$memory_ref.v:311$425_EN[26:0]$437 [0] $0$memwr$\mem$memory_ref.v:311$425_EN[26:0]$437 [0] $0$memwr$\mem$memory_ref.v:311$425_EN[26:0]$437 [0] $0$memwr$\mem$memory_ref.v:311$425_EN[26:0]$437 [0] $0$memwr$\mem$memory_ref.v:311$425_EN[26:0]$437 [0] $0$memwr$\mem$memory_ref.v:311$425_EN[26:0]$437 [0] $0$memwr$\mem$memory_ref.v:311$425_EN[26:0]$437 [0] $0$memwr$\mem$memory_ref.v:311$425_EN[26:0]$437 [0] $0$memwr$\mem$memory_ref.v:311$425_EN[26:0]$437 [0] $0$memwr$\mem$memory_ref.v:311$425_EN[26:0]$437 [0] $0$memwr$\mem$memory_ref.v:311$425_EN[26:0]$437 [0] $0$memwr$\mem$memory_ref.v:311$425_EN[26:0]$437 [0] $0$memwr$\mem$memory_ref.v:311$425_EN[26:0]$437 [0] $0$memwr$\mem$memory_ref.v:311$425_EN[26:0]$437 [0] $0$memwr$\mem$memory_ref.v:311$425_EN[26:0]$437 [0] $0$memwr$\mem$memory_ref.v:311$425_EN[26:0]$437 [0] $0$memwr$\mem$memory_ref.v:311$425_EN[26:0]$437 [0] $0$memwr$\mem$memory_ref.v:311$425_EN[26:0]$437 [0] $0$memwr$\mem$memory_ref.v:311$425_EN[26:0]$437 [0] $0$memwr$\mem$memory_ref.v:311$425_EN[26:0]$437 [0] } + Optimizing cells in module \memtest13. +Performed a total of 59 changes. + +4.5.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memtest00'. +Finding identical cells in module `\memtest01'. +Finding identical cells in module `\memtest02'. + +Finding identical cells in module `\memtest03'. +Finding identical cells in module `\memtest04'. +Finding identical cells in module `\memtest05'. +Finding identical cells in module `\memtest06_async'. + +Finding identical cells in module `\memtest06_sync'. + +Finding identical cells in module `\memtest07'. +Finding identical cells in module `\memtest08'. +Finding identical cells in module `\memtest09'. +Finding identical cells in module `\memtest10'. +Finding identical cells in module `\memtest11'. +Finding identical cells in module `\memtest12'. +Finding identical cells in module `\memtest13'. + +Removed a total of 39 cells. + +4.5.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.5.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memtest00.. +Finding unused cells or wires in module \memtest01.. +Finding unused cells or wires in module \memtest02.. +Finding unused cells or wires in module \memtest03.. +Finding unused cells or wires in module \memtest04.. +Finding unused cells or wires in module \memtest05.. +Finding unused cells or wires in module \memtest06_async.. +Finding unused cells or wires in module \memtest06_sync.. +Finding unused cells or wires in module \memtest07.. +Finding unused cells or wires in module \memtest08.. +Finding unused cells or wires in module \memtest09.. +Finding unused cells or wires in module \memtest10.. +Finding unused cells or wires in module \memtest11.. +Finding unused cells or wires in module \memtest12.. +Finding unused cells or wires in module \memtest13.. +Removed 0 unused cells and 298 unused wires. + + +4.5.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module memtest00. +Optimizing module memtest01. +Optimizing module memtest02. +Optimizing module memtest03. +Optimizing module memtest04. +Optimizing module memtest05. +Optimizing module memtest06_async. +Optimizing module memtest06_sync. +Optimizing module memtest07. +Optimizing module memtest08. +Optimizing module memtest09. +Optimizing module memtest10. +Optimizing module memtest11. +Optimizing module memtest12. +Optimizing module memtest13. + +4.5.9. Rerunning OPT passes. (Maybe there is more to do..) + +4.5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \memtest00.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest01.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest02.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest03.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest04.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest05.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest06_async.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest06_sync.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest07.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest08.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest09.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest10.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest11.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest12.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest13.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \memtest00. + Optimizing cells in module \memtest01. + Optimizing cells in module \memtest02. + Optimizing cells in module \memtest03. + Optimizing cells in module \memtest04. + Optimizing cells in module \memtest05. + Optimizing cells in module \memtest06_async. + Optimizing cells in module \memtest06_sync. + Optimizing cells in module \memtest07. + Optimizing cells in module \memtest08. + Optimizing cells in module \memtest09. + Optimizing cells in module \memtest10. + Optimizing cells in module \memtest11. + Optimizing cells in module \memtest12. + Optimizing cells in module \memtest13. +Performed a total of 0 changes. + +4.5.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memtest00'. +Finding identical cells in module `\memtest01'. +Finding identical cells in module `\memtest02'. +Finding identical cells in module `\memtest03'. +Finding identical cells in module `\memtest04'. +Finding identical cells in module `\memtest05'. +Finding identical cells in module `\memtest06_async'. +Finding identical cells in module `\memtest06_sync'. +Finding identical cells in module `\memtest07'. +Finding identical cells in module `\memtest08'. +Finding identical cells in module `\memtest09'. +Finding identical cells in module `\memtest10'. +Finding identical cells in module `\memtest11'. +Finding identical cells in module `\memtest12'. +Finding identical cells in module `\memtest13'. +Removed a total of 0 cells. + +4.5.13. Executing OPT_DFF pass (perform DFF optimizations). + +4.5.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memtest00.. +Finding unused cells or wires in module \memtest01.. +Finding unused cells or wires in module \memtest02.. +Finding unused cells or wires in module \memtest03.. +Finding unused cells or wires in module \memtest04.. +Finding unused cells or wires in module \memtest05.. +Finding unused cells or wires in module \memtest06_async.. +Finding unused cells or wires in module \memtest06_sync.. +Finding unused cells or wires in module \memtest07.. +Finding unused cells or wires in module \memtest08.. +Finding unused cells or wires in module \memtest09.. +Finding unused cells or wires in module \memtest10.. +Finding unused cells or wires in module \memtest11.. +Finding unused cells or wires in module \memtest12.. +Finding unused cells or wires in module \memtest13.. + +4.5.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module memtest00. +Optimizing module memtest01. +Optimizing module memtest02. +Optimizing module memtest03. +Optimizing module memtest04. +Optimizing module memtest05. +Optimizing module memtest06_async. +Optimizing module memtest06_sync. +Optimizing module memtest07. +Optimizing module memtest08. +Optimizing module memtest09. +Optimizing module memtest10. +Optimizing module memtest11. +Optimizing module memtest12. +Optimizing module memtest13. + +4.5.16. Finished OPT passes. (There is nothing left to do.) + +4.6. Executing FSM pass (extract and optimize FSM). + +4.6.1. Executing FSM_DETECT pass (finding FSMs in design). +Not marking memtest02.mem2[0] as FSM state register: + Users of register don't seem to benefit from recoding. +Not marking memtest02.mem2[1] as FSM state register: + Users of register don't seem to benefit from recoding. +Not marking memtest02.mem2[2] as FSM state register: + Users of register don't seem to benefit from recoding. + +4.6.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +4.6.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.6.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memtest00.. +Finding unused cells or wires in module \memtest01.. +Finding unused cells or wires in module \memtest02.. +Finding unused cells or wires in module \memtest03.. +Finding unused cells or wires in module \memtest04.. +Finding unused cells or wires in module \memtest05.. +Finding unused cells or wires in module \memtest06_async.. +Finding unused cells or wires in module \memtest06_sync.. +Finding unused cells or wires in module \memtest07.. +Finding unused cells or wires in module \memtest08.. +Finding unused cells or wires in module \memtest09.. +Finding unused cells or wires in module \memtest10.. +Finding unused cells or wires in module \memtest11.. +Finding unused cells or wires in module \memtest12.. +Finding unused cells or wires in module \memtest13.. + +4.6.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.6.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +4.6.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +4.6.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +4.7. Executing OPT pass (performing simple optimizations). + +4.7.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module memtest00. +Optimizing module memtest01. +Optimizing module memtest02. +Optimizing module memtest03. +Optimizing module memtest04. +Optimizing module memtest05. +Optimizing module memtest06_async. +Optimizing module memtest06_sync. +Optimizing module memtest07. +Optimizing module memtest08. +Optimizing module memtest09. +Optimizing module memtest10. +Optimizing module memtest11. +Optimizing module memtest12. +Optimizing module memtest13. + +4.7.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memtest00'. +Finding identical cells in module `\memtest01'. +Finding identical cells in module `\memtest02'. +Finding identical cells in module `\memtest03'. +Finding identical cells in module `\memtest04'. +Finding identical cells in module `\memtest05'. +Finding identical cells in module `\memtest06_async'. +Finding identical cells in module `\memtest06_sync'. +Finding identical cells in module `\memtest07'. +Finding identical cells in module `\memtest08'. +Finding identical cells in module `\memtest09'. +Finding identical cells in module `\memtest10'. +Finding identical cells in module `\memtest11'. +Finding identical cells in module `\memtest12'. +Finding identical cells in module `\memtest13'. +Removed a total of 0 cells. + +4.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \memtest00.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest01.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest02.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest03.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest04.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest05.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest06_async.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest06_sync.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest07.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest08.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest09.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest10.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest11.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest12.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest13.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \memtest00. + Optimizing cells in module \memtest01. + Optimizing cells in module \memtest02. + Optimizing cells in module \memtest03. + Optimizing cells in module \memtest04. + Optimizing cells in module \memtest05. + Optimizing cells in module \memtest06_async. + Optimizing cells in module \memtest06_sync. + Optimizing cells in module \memtest07. + Optimizing cells in module \memtest08. + Optimizing cells in module \memtest09. + Optimizing cells in module \memtest10. + Optimizing cells in module \memtest11. + Optimizing cells in module \memtest12. + Optimizing cells in module \memtest13. +Performed a total of 0 changes. + +4.7.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memtest00'. +Finding identical cells in module `\memtest01'. +Finding identical cells in module `\memtest02'. +Finding identical cells in module `\memtest03'. +Finding identical cells in module `\memtest04'. +Finding identical cells in module `\memtest05'. +Finding identical cells in module `\memtest06_async'. +Finding identical cells in module `\memtest06_sync'. +Finding identical cells in module `\memtest07'. +Finding identical cells in module `\memtest08'. +Finding identical cells in module `\memtest09'. +Finding identical cells in module `\memtest10'. +Finding identical cells in module `\memtest11'. +Finding identical cells in module `\memtest12'. +Finding identical cells in module `\memtest13'. +Removed a total of 0 cells. + +4.7.6. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $procdff$1290 ($dff) from module memtest00 (D = $procmux$1066_Y, Q = \mem[0], rval = 1'1). +Adding EN signal on $auto$ff.cc:266:slice$1379 ($sdff) from module memtest00 (D = 1'0, Q = \mem[0]). +Adding SRST signal on $procdff$1276 ($dff) from module memtest02 (D = $procmux$1040_Y, Q = \mem2[2], rval = 8'01001001). +Adding EN signal on $auto$ff.cc:266:slice$1381 ($sdff) from module memtest02 (D = 8'00100101, Q = \mem2[2]). +Adding SRST signal on $procdff$1275 ($dff) from module memtest02 (D = $procmux$1046_Y, Q = \mem2[1], rval = 8'01001000). +Adding EN signal on $auto$ff.cc:266:slice$1383 ($sdff) from module memtest02 (D = 8'00011011, Q = \mem2[1]). +Adding SRST signal on $procdff$1274 ($dff) from module memtest02 (D = $procmux$1052_Y, Q = \mem2[0], rval = 8'01000111). +Adding EN signal on $auto$ff.cc:266:slice$1385 ($sdff) from module memtest02 (D = 8'00010001, Q = \mem2[0]). +Setting constant 1-bit at position 0 on $auto$ff.cc:266:slice$1386 ($sdffe) from module memtest02. +Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$1386 ($sdffe) from module memtest02. +Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$1386 ($sdffe) from module memtest02. +Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$1386 ($sdffe) from module memtest02. +Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$1384 ($sdffe) from module memtest02. +Setting constant 1-bit at position 3 on $auto$ff.cc:266:slice$1384 ($sdffe) from module memtest02. +Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$1384 ($sdffe) from module memtest02. +Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$1384 ($sdffe) from module memtest02. +Setting constant 1-bit at position 0 on $auto$ff.cc:266:slice$1382 ($sdffe) from module memtest02. +Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$1382 ($sdffe) from module memtest02. +Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$1382 ($sdffe) from module memtest02. +Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$1382 ($sdffe) from module memtest02. +Adding EN signal on $procdff$1146 ($adff) from module memtest06_async (D = { $0$lookahead\test[7]$197[7:0]$224 [7] $0$lookahead\test[7]$197[7:0]$224 [5:4] $0$lookahead\test[7]$197[7:0]$224 [2:0] }, Q = { \test[7] [7] \test[7] [5:4] \test[7] [2:0] }). +Adding EN signal on $procdff$1143 ($adff) from module memtest06_async (D = { $0$lookahead\test[6]$196[7:0]$223 [7] $0$lookahead\test[6]$196[7:0]$223 [5:4] $0$lookahead\test[6]$196[7:0]$223 [2:0] }, Q = { \test[6] [7] \test[6] [5:4] \test[6] [2:0] }). +Adding EN signal on $procdff$1140 ($adff) from module memtest06_async (D = { $0$lookahead\test[5]$195[7:0]$222 [7] $0$lookahead\test[5]$195[7:0]$222 [5:4] $0$lookahead\test[5]$195[7:0]$222 [2:0] }, Q = { \test[5] [7] \test[5] [5:4] \test[5] [2:0] }). +Adding EN signal on $procdff$1137 ($adff) from module memtest06_async (D = { $0$lookahead\test[4]$194[7:0]$221 [7] $0$lookahead\test[4]$194[7:0]$221 [5:4] $0$lookahead\test[4]$194[7:0]$221 [2:0] }, Q = { \test[4] [7] \test[4] [5:4] \test[4] [2:0] }). +Adding EN signal on $procdff$1134 ($adff) from module memtest06_async (D = { $0$lookahead\test[3]$193[7:0]$220 [7] $0$lookahead\test[3]$193[7:0]$220 [5:4] $0$lookahead\test[3]$193[7:0]$220 [2:0] }, Q = { \test[3] [7] \test[3] [5:4] \test[3] [2:0] }). +Adding EN signal on $procdff$1131 ($adff) from module memtest06_async (D = { $0$lookahead\test[2]$192[7:0]$219 [7] $0$lookahead\test[2]$192[7:0]$219 [5:4] $0$lookahead\test[2]$192[7:0]$219 [2:0] }, Q = { \test[2] [7] \test[2] [5:4] \test[2] [2:0] }). +Adding EN signal on $procdff$1128 ($adff) from module memtest06_async (D = { $0$lookahead\test[1]$191[7:0]$218 [7] $0$lookahead\test[1]$191[7:0]$218 [5:4] $0$lookahead\test[1]$191[7:0]$218 [2:0] }, Q = { \test[1] [7] \test[1] [5:4] \test[1] [2:0] }). +Adding EN signal on $procdff$1125 ($adff) from module memtest06_async (D = { $0$lookahead\test[0]$190[7:0]$217 [7] $0$lookahead\test[0]$190[7:0]$217 [4] $0$lookahead\test[0]$190[7:0]$217 [1:0] }, Q = { \test[0] [7] \test[0] [4] \test[0] [1:0] }). +Adding EN signal on $procdff$1072 ($dff) from module memtest13 (D = $memrd$\mem$memory_ref.v:316$476_DATA, Q = \dout3). +Adding EN signal on $procdff$1071 ($dff) from module memtest13 (D = $shiftx$memory_ref.v:0$475_Y, Q = \dout2). +Adding EN signal on $procdff$1070 ($dff) from module memtest13 (D = $memrd$\mem$memory_ref.v:314$469_DATA [7:4], Q = \dout1). + +4.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memtest00.. +Finding unused cells or wires in module \memtest01.. +Finding unused cells or wires in module \memtest02.. +Finding unused cells or wires in module \memtest03.. +Finding unused cells or wires in module \memtest04.. +Finding unused cells or wires in module \memtest05.. +Finding unused cells or wires in module \memtest06_async.. +Finding unused cells or wires in module \memtest06_sync.. +Finding unused cells or wires in module \memtest07.. +Finding unused cells or wires in module \memtest08.. +Finding unused cells or wires in module \memtest09.. +Finding unused cells or wires in module \memtest10.. +Finding unused cells or wires in module \memtest11.. +Finding unused cells or wires in module \memtest12.. +Finding unused cells or wires in module \memtest13.. +Removed 11 unused cells and 11 unused wires. + + +4.7.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module memtest00. +Optimizing module memtest01. +Optimizing module memtest02. +Optimizing module memtest03. +Optimizing module memtest04. +Optimizing module memtest05. +Optimizing module memtest06_async. + +Optimizing module memtest06_sync. +Optimizing module memtest07. +Optimizing module memtest08. +Optimizing module memtest09. +Optimizing module memtest10. +Optimizing module memtest11. +Optimizing module memtest12. +Optimizing module memtest13. + +4.7.9. Rerunning OPT passes. (Maybe there is more to do..) + +4.7.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \memtest00.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest01.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest02.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest03.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest04.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest05.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest06_async.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest06_sync.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest07.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest08.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest09.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest10.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest11.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest12.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest13.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.7.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \memtest00. + Optimizing cells in module \memtest01. + Optimizing cells in module \memtest02. + Optimizing cells in module \memtest03. + Optimizing cells in module \memtest04. + Optimizing cells in module \memtest05. + Optimizing cells in module \memtest06_async. + Optimizing cells in module \memtest06_sync. + Optimizing cells in module \memtest07. + Optimizing cells in module \memtest08. + Optimizing cells in module \memtest09. + Optimizing cells in module \memtest10. + Optimizing cells in module \memtest11. + Optimizing cells in module \memtest12. + Optimizing cells in module \memtest13. +Performed a total of 0 changes. + +4.7.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memtest00'. +Finding identical cells in module `\memtest01'. +Finding identical cells in module `\memtest02'. +Finding identical cells in module `\memtest03'. +Finding identical cells in module `\memtest04'. +Finding identical cells in module `\memtest05'. +Finding identical cells in module `\memtest06_async'. +Finding identical cells in module `\memtest06_sync'. +Finding identical cells in module `\memtest07'. +Finding identical cells in module `\memtest08'. +Finding identical cells in module `\memtest09'. +Finding identical cells in module `\memtest10'. +Finding identical cells in module `\memtest11'. +Finding identical cells in module `\memtest12'. +Finding identical cells in module `\memtest13'. +Removed a total of 0 cells. + +4.7.13. Executing OPT_DFF pass (perform DFF optimizations). + +4.7.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memtest00.. +Finding unused cells or wires in module \memtest01.. +Finding unused cells or wires in module \memtest02.. +Finding unused cells or wires in module \memtest03.. +Finding unused cells or wires in module \memtest04.. +Finding unused cells or wires in module \memtest05.. +Finding unused cells or wires in module \memtest06_async.. +Finding unused cells or wires in module \memtest06_sync.. +Finding unused cells or wires in module \memtest07.. +Finding unused cells or wires in module \memtest08.. +Finding unused cells or wires in module \memtest09.. +Finding unused cells or wires in module \memtest10.. +Finding unused cells or wires in module \memtest11.. +Finding unused cells or wires in module \memtest12.. +Finding unused cells or wires in module \memtest13.. +Removed 8 unused cells and 8 unused wires. + + +4.7.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module memtest00. +Optimizing module memtest01. +Optimizing module memtest02. +Optimizing module memtest03. +Optimizing module memtest04. +Optimizing module memtest05. +Optimizing module memtest06_async. +Optimizing module memtest06_sync. +Optimizing module memtest07. +Optimizing module memtest08. +Optimizing module memtest09. +Optimizing module memtest10. +Optimizing module memtest11. +Optimizing module memtest12. +Optimizing module memtest13. + +4.7.16. Rerunning OPT passes. (Maybe there is more to do..) + +4.7.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \memtest00.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest01.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest02.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest03.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest04.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest05.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest06_async.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest06_sync.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest07.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest08.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest09.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest10.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest11.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest12.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest13.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.7.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \memtest00. + Optimizing cells in module \memtest01. + Optimizing cells in module \memtest02. + Optimizing cells in module \memtest03. + Optimizing cells in module \memtest04. + Optimizing cells in module \memtest05. + Optimizing cells in module \memtest06_async. + Optimizing cells in module \memtest06_sync. + Optimizing cells in module \memtest07. + Optimizing cells in module \memtest08. + Optimizing cells in module \memtest09. + Optimizing cells in module \memtest10. + Optimizing cells in module \memtest11. + Optimizing cells in module \memtest12. + Optimizing cells in module \memtest13. +Performed a total of 0 changes. + +4.7.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memtest00'. +Finding identical cells in module `\memtest01'. +Finding identical cells in module `\memtest02'. +Finding identical cells in module `\memtest03'. +Finding identical cells in module `\memtest04'. +Finding identical cells in module `\memtest05'. +Finding identical cells in module `\memtest06_async'. +Finding identical cells in module `\memtest06_sync'. +Finding identical cells in module `\memtest07'. +Finding identical cells in module `\memtest08'. +Finding identical cells in module `\memtest09'. +Finding identical cells in module `\memtest10'. +Finding identical cells in module `\memtest11'. +Finding identical cells in module `\memtest12'. +Finding identical cells in module `\memtest13'. +Removed a total of 0 cells. + +4.7.20. Executing OPT_DFF pass (perform DFF optimizations). + +4.7.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memtest00.. +Finding unused cells or wires in module \memtest01.. +Finding unused cells or wires in module \memtest02.. +Finding unused cells or wires in module \memtest03.. +Finding unused cells or wires in module \memtest04.. +Finding unused cells or wires in module \memtest05.. +Finding unused cells or wires in module \memtest06_async.. +Finding unused cells or wires in module \memtest06_sync.. +Finding unused cells or wires in module \memtest07.. +Finding unused cells or wires in module \memtest08.. +Finding unused cells or wires in module \memtest09.. +Finding unused cells or wires in module \memtest10.. +Finding unused cells or wires in module \memtest11.. +Finding unused cells or wires in module \memtest12.. +Finding unused cells or wires in module \memtest13.. + +4.7.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module memtest00. +Optimizing module memtest01. +Optimizing module memtest02. +Optimizing module memtest03. +Optimizing module memtest04. +Optimizing module memtest05. +Optimizing module memtest06_async. +Optimizing module memtest06_sync. +Optimizing module memtest07. +Optimizing module memtest08. +Optimizing module memtest09. +Optimizing module memtest10. +Optimizing module memtest11. +Optimizing module memtest12. +Optimizing module memtest13. + +4.7.23. Finished OPT passes. (There is nothing left to do.) + +4.8. Executing WREDUCE pass (reducing word size of cells). +Removed top 30 address bits (of 32) from memory init port memtest02.$auto$proc_memwr.cc:45:proc_memwr$1324 (mem1). +Removed top 30 address bits (of 32) from memory init port memtest02.$auto$proc_memwr.cc:45:proc_memwr$1325 (mem1). +Removed top 30 address bits (of 32) from memory init port memtest02.$auto$proc_memwr.cc:45:proc_memwr$1326 (mem1). +Removed top 30 address bits (of 32) from memory init port memtest02.$auto$proc_memwr.cc:45:proc_memwr$1327 (mem1). +Removed top 30 address bits (of 32) from memory init port memtest02.$auto$proc_memwr.cc:45:proc_memwr$1328 (mem1). +Removed top 30 address bits (of 32) from memory init port memtest02.$auto$proc_memwr.cc:45:proc_memwr$1329 (mem1). +Removed top 1 bits (of 2) from port B of cell memtest02.$procmux$1014_CMP0 ($eq). +Removed top 1 bits (of 8) from wire memtest02.mem2[0]. +Removed top 1 bits (of 8) from wire memtest02.mem2[1]. +Removed top 6 bits (of 8) from wire memtest05.$0$memwr$\mem$memory_ref.v:133$72_EN[7:0]$79. +Removed top 4 bits (of 8) from wire memtest05.$0$memwr$\mem$memory_ref.v:133$73_EN[7:0]$82. +Removed top 2 bits (of 8) from wire memtest05.$0$memwr$\mem$memory_ref.v:133$74_EN[7:0]$85. +Converting cell memtest06_async.$neg$memory_ref.v:0$288 ($neg) from signed to unsigned. +Removed top 1 bits (of 4) from port A of cell memtest06_async.$neg$memory_ref.v:0$288 ($neg). +Removed top 1 bits (of 3) from port B of cell memtest06_async.$procmux$572_CMP0 ($eq). +Removed top 1 bits (of 3) from port B of cell memtest06_async.$procmux$573_CMP0 ($eq). +Removed top 2 bits (of 3) from port B of cell memtest06_async.$procmux$574_CMP0 ($eq). +Removed top 5 bits (of 8) from mux cell memtest06_async.$procmux$801 ($pmux). +Removed top 5 bits (of 8) from wire memtest06_async.$0$mem2reg_rd$\test$memory_ref.v:182$178_DATA[7:0]$204. +Removed top 7 bits (of 8) from wire memtest06_async.$0$mem2reg_wr$\test$memory_ref.v:183$179_DATA[7:0]$206. +Removed top 29 address bits (of 32) from memory init port memtest06_sync.$auto$proc_memwr.cc:45:proc_memwr$1305 (test). +Removed top 29 address bits (of 32) from memory init port memtest06_sync.$auto$proc_memwr.cc:45:proc_memwr$1306 (test). +Removed top 29 address bits (of 32) from memory init port memtest06_sync.$auto$proc_memwr.cc:45:proc_memwr$1307 (test). +Removed top 29 address bits (of 32) from memory init port memtest06_sync.$auto$proc_memwr.cc:45:proc_memwr$1308 (test). +Removed top 29 address bits (of 32) from memory init port memtest06_sync.$auto$proc_memwr.cc:45:proc_memwr$1309 (test). +Removed top 29 address bits (of 32) from memory init port memtest06_sync.$auto$proc_memwr.cc:45:proc_memwr$1310 (test). +Removed top 29 address bits (of 32) from memory init port memtest06_sync.$auto$proc_memwr.cc:45:proc_memwr$1311 (test). +Removed top 29 address bits (of 32) from memory init port memtest06_sync.$auto$proc_memwr.cc:45:proc_memwr$1312 (test). +Removed top 29 address bits (of 32) from memory init port memtest06_sync.$auto$proc_memwr.cc:45:proc_memwr$1313 (test). +Removed top 29 address bits (of 32) from memory init port memtest06_sync.$auto$proc_memwr.cc:45:proc_memwr$1314 (test). +Removed top 29 address bits (of 32) from memory read port memtest06_sync.$memrd$\test$memory_ref.v:156$167 (test). +Removed top 7 bits (of 8) from port A of cell memtest06_sync.$shl$memory_ref.v:0$173 ($shl). +Removed top 7 bits (of 8) from port A of cell memtest06_sync.$shl$memory_ref.v:0$174 ($shl). +Removed top 5 bits (of 8) from wire memtest06_sync.$0$memwr$\test$memory_ref.v:155$110_EN[7:0]$128. +Removed top 7 bits (of 8) from wire memtest06_sync.$logic_not$memory_ref.v:159$172_Y. +Removed top 30 bits (of 32) from port B of cell memtest07.$shl$memory_ref.v:0$353 ($shl). +Removed top 4 bits (of 8) from port A of cell memtest07.$shl$memory_ref.v:0$355 ($shl). +Removed top 30 bits (of 32) from port B of cell memtest07.$shl$memory_ref.v:0$355 ($shl). +Removed top 24 address bits (of 32) from memory init port memtest08.$auto$proc_memwr.cc:45:proc_memwr$1303 (mem). +Removed top 24 address bits (of 32) from memory read port memtest08.$memrd$\mem$memory_ref.v:214$362 (mem). +Removed top 24 bits (of 32) from port A of cell memtest08.$add$memory_ref.v:0$364 ($add). +Removed top 24 bits (of 32) from port Y of cell memtest08.$add$memory_ref.v:0$364 ($add). +Removed top 24 bits (of 32) from wire memtest08.$0$memwr$\mem$memory_ref.v:215$357_ADDR[31:0]$359. +Removed top 26 address bits (of 32) from memory init port memtest09.$auto$proc_memwr.cc:45:proc_memwr$1301 (memory). +Removed top 26 address bits (of 32) from memory init port memtest09.$auto$proc_memwr.cc:45:proc_memwr$1302 (memory). +Removed top 26 address bits (of 32) from memory read port memtest09.$memrd$\memory$memory_ref.v:232$377 (memory). +Removed top 26 address bits (of 32) from memory read port memtest09.$memrd$\memory$memory_ref.v:238$393 (memory). +Removed top 28 bits (of 32) from port A of cell memtest09.$add$memory_ref.v:231$376 ($add). +Removed top 27 bits (of 32) from port Y of cell memtest09.$add$memory_ref.v:231$376 ($add). +Removed top 27 bits (of 32) from port A of cell memtest09.$add$memory_ref.v:236$384 ($add). +Removed top 26 bits (of 32) from port Y of cell memtest09.$add$memory_ref.v:236$384 ($add). +Removed top 27 bits (of 32) from port A of cell memtest09.$ne$memory_ref.v:236$385 ($ne). +Removed top 26 bits (of 32) from port B of cell memtest09.$ne$memory_ref.v:236$385 ($ne). +Removed top 26 bits (of 32) from mux cell memtest09.$procmux$556 ($mux). +Removed top 26 bits (of 32) from mux cell memtest09.$procmux$565 ($mux). +Removed top 26 bits (of 32) from wire memtest09.$0$memwr$\memory$memory_ref.v:231$367_ADDR[31:0]$370. +Removed top 26 bits (of 32) from wire memtest09.$0$memwr$\memory$memory_ref.v:237$368_ADDR[31:0]$380. +Removed top 3 bits (of 4) from wire memtest09.$0\b_dout[3:0]. +Removed top 27 bits (of 32) from wire memtest09.$add$memory_ref.v:231$376_Y. +Removed top 26 bits (of 32) from wire memtest09.$add$memory_ref.v:236$384_Y. +Removed top 30 address bits (of 32) from memory init port memtest13.$auto$proc_memwr.cc:45:proc_memwr$1291 (mem). +Removed top 30 address bits (of 32) from memory init port memtest13.$auto$proc_memwr.cc:45:proc_memwr$1292 (mem). +Removed top 30 address bits (of 32) from memory init port memtest13.$auto$proc_memwr.cc:45:proc_memwr$1293 (mem). +Removed top 30 address bits (of 32) from memory init port memtest13.$auto$proc_memwr.cc:45:proc_memwr$1294 (mem). +Removed top 29 bits (of 32) from port A of cell memtest13.$add$memory_ref.v:313$461 ($add). +Removed top 27 bits (of 32) from port Y of cell memtest13.$add$memory_ref.v:313$461 ($add). +Removed top 27 bits (of 32) from port A of cell memtest13.$sub$memory_ref.v:0$463 ($sub). +Removed top 29 bits (of 32) from port B of cell memtest13.$sub$memory_ref.v:0$463 ($sub). +Removed top 26 bits (of 32) from port Y of cell memtest13.$sub$memory_ref.v:0$463 ($sub). +Removed top 23 bits (of 27) from port A of cell memtest13.$shl$memory_ref.v:0$468 ($shl). +Removed top 29 bits (of 32) from port A of cell memtest13.$add$memory_ref.v:315$471 ($add). +Removed top 27 bits (of 32) from port Y of cell memtest13.$add$memory_ref.v:315$471 ($add). +Removed top 27 bits (of 32) from port A of cell memtest13.$auto$genrtlil.cc:1629:genRTLIL$473 ($sub). +Removed top 29 bits (of 32) from port B of cell memtest13.$auto$genrtlil.cc:1629:genRTLIL$473 ($sub). +Removed top 26 bits (of 32) from port Y of cell memtest13.$auto$genrtlil.cc:1629:genRTLIL$473 ($sub). +Removed top 26 bits (of 32) from port B of cell memtest13.$shiftx$memory_ref.v:0$475 ($shiftx). +Removed top 27 bits (of 32) from wire memtest13.$add$memory_ref.v:0$462_Y. +Removed top 27 bits (of 32) from wire memtest13.$add$memory_ref.v:0$472_Y. + +4.9. Executing PEEPOPT pass (run peephole optimizers). + +4.10. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memtest00.. +Finding unused cells or wires in module \memtest01.. +Finding unused cells or wires in module \memtest02.. +Finding unused cells or wires in module \memtest03.. +Finding unused cells or wires in module \memtest04.. +Finding unused cells or wires in module \memtest05.. +Finding unused cells or wires in module \memtest06_async.. +Finding unused cells or wires in module \memtest06_sync.. +Finding unused cells or wires in module \memtest07.. +Finding unused cells or wires in module \memtest08.. +Finding unused cells or wires in module \memtest09.. +Finding unused cells or wires in module \memtest10.. +Finding unused cells or wires in module \memtest11.. +Finding unused cells or wires in module \memtest12.. +Finding unused cells or wires in module \memtest13.. +Removed 0 unused cells and 16 unused wires. + + +4.11. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module memtest00: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module memtest01: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module memtest02: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module memtest03: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module memtest04: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module memtest05: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module memtest06_async: + creating $macc model for $neg$memory_ref.v:0$288 ($neg). + creating $alu model for $macc $neg$memory_ref.v:0$288. + creating $alu cell for $neg$memory_ref.v:0$288: $auto$alumacc.cc:485:replace_alu$1442 + created 1 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module memtest06_sync: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module memtest07: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module memtest08: + creating $macc model for $add$memory_ref.v:0$364 ($add). + creating $alu model for $macc $add$memory_ref.v:0$364. + creating $alu cell for $add$memory_ref.v:0$364: $auto$alumacc.cc:485:replace_alu$1445 + created 1 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module memtest09: + creating $macc model for $add$memory_ref.v:231$376 ($add). + creating $macc model for $add$memory_ref.v:236$384 ($add). + creating $alu model for $macc $add$memory_ref.v:236$384. + creating $alu model for $macc $add$memory_ref.v:231$376. + creating $alu cell for $add$memory_ref.v:231$376: $auto$alumacc.cc:485:replace_alu$1448 + creating $alu cell for $add$memory_ref.v:236$384: $auto$alumacc.cc:485:replace_alu$1451 + created 2 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module memtest10: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module memtest11: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module memtest12: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module memtest13: + creating $macc model for $add$memory_ref.v:313$461 ($add). + creating $macc model for $add$memory_ref.v:315$471 ($add). + creating $macc model for $auto$genrtlil.cc:1629:genRTLIL$473 ($sub). + creating $macc model for $sub$memory_ref.v:0$463 ($sub). + merging $macc model for $add$memory_ref.v:313$461 into $sub$memory_ref.v:0$463. + merging $macc model for $add$memory_ref.v:315$471 into $auto$genrtlil.cc:1629:genRTLIL$473. + creating $macc cell for $sub$memory_ref.v:0$463: $auto$alumacc.cc:365:replace_macc$1454 + creating $macc cell for $auto$genrtlil.cc:1629:genRTLIL$473: $auto$alumacc.cc:365:replace_macc$1455 + created 0 $alu and 2 $macc cells. + +4.12. Executing SHARE pass (SAT-based resource sharing). +Found 2 cells in module memtest06_sync that may be considered for resource sharing. + Analyzing resource sharing options for $shl$memory_ref.v:0$174 ($shl): + Found 1 activation_patterns using ctrl signal \rst. + Found 1 candidates: $shl$memory_ref.v:0$173 + Analyzing resource sharing with $shl$memory_ref.v:0$173 ($shl): + Found 1 activation_patterns using ctrl signal \rst. + Activation pattern for cell $shl$memory_ref.v:0$174: \rst = 1'0 + Activation pattern for cell $shl$memory_ref.v:0$173: \rst = 1'0 + Size of SAT problem: 0 cells, 5 variables, 9 clauses + According to the SAT solver this pair of cells can not be shared. + Model from SAT solver: \rst = 1'0 + Analyzing resource sharing options for $shl$memory_ref.v:0$173 ($shl): + Found 1 activation_patterns using ctrl signal \rst. + No candidates found. +Found 2 cells in module memtest13 that may be considered for resource sharing. + Analyzing resource sharing options for $shl$memory_ref.v:0$468 ($shl): + Found 1 activation_patterns using ctrl signal \rst. + Found 1 candidates: $shl$memory_ref.v:0$464 + Analyzing resource sharing with $shl$memory_ref.v:0$464 ($shl): + Found 1 activation_patterns using ctrl signal \rst. + Activation pattern for cell $shl$memory_ref.v:0$468: \rst = 1'0 + Activation pattern for cell $shl$memory_ref.v:0$464: \rst = 1'0 + Size of SAT problem: 0 cells, 5 variables, 9 clauses + According to the SAT solver this pair of cells can not be shared. + Model from SAT solver: \rst = 1'0 + Analyzing resource sharing options for $shl$memory_ref.v:0$464 ($shl): + Found 1 activation_patterns using ctrl signal \rst. + No candidates found. + +4.13. Executing OPT pass (performing simple optimizations). + +4.13.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module memtest00. +Optimizing module memtest01. +Optimizing module memtest02. +Optimizing module memtest03. +Optimizing module memtest04. +Optimizing module memtest05. +Optimizing module memtest06_async. +Optimizing module memtest06_sync. +Optimizing module memtest07. +Optimizing module memtest08. +Optimizing module memtest09. +Optimizing module memtest10. +Optimizing module memtest11. +Optimizing module memtest12. +Optimizing module memtest13. + +4.13.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memtest00'. +Finding identical cells in module `\memtest01'. +Finding identical cells in module `\memtest02'. +Finding identical cells in module `\memtest03'. +Finding identical cells in module `\memtest04'. +Finding identical cells in module `\memtest05'. +Finding identical cells in module `\memtest06_async'. +Finding identical cells in module `\memtest06_sync'. +Finding identical cells in module `\memtest07'. +Finding identical cells in module `\memtest08'. +Finding identical cells in module `\memtest09'. +Finding identical cells in module `\memtest10'. +Finding identical cells in module `\memtest11'. +Finding identical cells in module `\memtest12'. +Finding identical cells in module `\memtest13'. +Removed a total of 0 cells. + +4.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \memtest00.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest01.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest02.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest03.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest04.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest05.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest06_async.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest06_sync.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest07.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest08.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest09.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest10.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest11.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest12.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest13.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \memtest00. + Optimizing cells in module \memtest01. + Optimizing cells in module \memtest02. + Optimizing cells in module \memtest03. + Optimizing cells in module \memtest04. + Optimizing cells in module \memtest05. + Optimizing cells in module \memtest06_async. + Optimizing cells in module \memtest06_sync. + Optimizing cells in module \memtest07. + Optimizing cells in module \memtest08. + Optimizing cells in module \memtest09. + Optimizing cells in module \memtest10. + Optimizing cells in module \memtest11. + Optimizing cells in module \memtest12. + Optimizing cells in module \memtest13. +Performed a total of 0 changes. + +4.13.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memtest00'. +Finding identical cells in module `\memtest01'. +Finding identical cells in module `\memtest02'. +Finding identical cells in module `\memtest03'. +Finding identical cells in module `\memtest04'. +Finding identical cells in module `\memtest05'. +Finding identical cells in module `\memtest06_async'. +Finding identical cells in module `\memtest06_sync'. +Finding identical cells in module `\memtest07'. +Finding identical cells in module `\memtest08'. +Finding identical cells in module `\memtest09'. +Finding identical cells in module `\memtest10'. +Finding identical cells in module `\memtest11'. +Finding identical cells in module `\memtest12'. +Finding identical cells in module `\memtest13'. +Removed a total of 0 cells. + +4.13.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memtest00.. +Finding unused cells or wires in module \memtest01.. +Finding unused cells or wires in module \memtest02.. +Finding unused cells or wires in module \memtest03.. +Finding unused cells or wires in module \memtest04.. +Finding unused cells or wires in module \memtest05.. +Finding unused cells or wires in module \memtest06_async.. +Finding unused cells or wires in module \memtest06_sync.. +Finding unused cells or wires in module \memtest07.. +Finding unused cells or wires in module \memtest08.. +Finding unused cells or wires in module \memtest09.. +Finding unused cells or wires in module \memtest10.. +Finding unused cells or wires in module \memtest11.. +Finding unused cells or wires in module \memtest12.. +Finding unused cells or wires in module \memtest13.. +Removed 2 unused cells and 2 unused wires. + + +4.13.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module memtest00. +Optimizing module memtest01. +Optimizing module memtest02. +Optimizing module memtest03. +Optimizing module memtest04. +Optimizing module memtest05. +Optimizing module memtest06_async. +Optimizing module memtest06_sync. +Optimizing module memtest07. +Optimizing module memtest08. +Optimizing module memtest09. +Optimizing module memtest10. +Optimizing module memtest11. +Optimizing module memtest12. +Optimizing module memtest13. + +4.13.9. Rerunning OPT passes. (Maybe there is more to do..) + +4.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \memtest00.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest01.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest02.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest03.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest04.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest05.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest06_async.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest06_sync.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest07.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest08.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest09.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest10.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest11.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest12.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest13.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \memtest00. + Optimizing cells in module \memtest01. + Optimizing cells in module \memtest02. + Optimizing cells in module \memtest03. + Optimizing cells in module \memtest04. + Optimizing cells in module \memtest05. + Optimizing cells in module \memtest06_async. + Optimizing cells in module \memtest06_sync. + Optimizing cells in module \memtest07. + Optimizing cells in module \memtest08. + Optimizing cells in module \memtest09. + Optimizing cells in module \memtest10. + Optimizing cells in module \memtest11. + Optimizing cells in module \memtest12. + Optimizing cells in module \memtest13. +Performed a total of 0 changes. + +4.13.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memtest00'. +Finding identical cells in module `\memtest01'. +Finding identical cells in module `\memtest02'. +Finding identical cells in module `\memtest03'. +Finding identical cells in module `\memtest04'. +Finding identical cells in module `\memtest05'. +Finding identical cells in module `\memtest06_async'. +Finding identical cells in module `\memtest06_sync'. +Finding identical cells in module `\memtest07'. +Finding identical cells in module `\memtest08'. +Finding identical cells in module `\memtest09'. +Finding identical cells in module `\memtest10'. +Finding identical cells in module `\memtest11'. +Finding identical cells in module `\memtest12'. +Finding identical cells in module `\memtest13'. +Removed a total of 0 cells. + +4.13.13. Executing OPT_DFF pass (perform DFF optimizations). + +4.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memtest00.. +Finding unused cells or wires in module \memtest01.. +Finding unused cells or wires in module \memtest02.. +Finding unused cells or wires in module \memtest03.. +Finding unused cells or wires in module \memtest04.. +Finding unused cells or wires in module \memtest05.. +Finding unused cells or wires in module \memtest06_async.. +Finding unused cells or wires in module \memtest06_sync.. +Finding unused cells or wires in module \memtest07.. +Finding unused cells or wires in module \memtest08.. +Finding unused cells or wires in module \memtest09.. +Finding unused cells or wires in module \memtest10.. +Finding unused cells or wires in module \memtest11.. +Finding unused cells or wires in module \memtest12.. +Finding unused cells or wires in module \memtest13.. + +4.13.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module memtest00. +Optimizing module memtest01. +Optimizing module memtest02. +Optimizing module memtest03. +Optimizing module memtest04. +Optimizing module memtest05. +Optimizing module memtest06_async. +Optimizing module memtest06_sync. +Optimizing module memtest07. +Optimizing module memtest08. +Optimizing module memtest09. +Optimizing module memtest10. +Optimizing module memtest11. +Optimizing module memtest12. +Optimizing module memtest13. + +4.13.16. Finished OPT passes. (There is nothing left to do.) + +4.14. Executing MEMORY pass. + +4.14.1. Executing OPT_MEM pass (optimize memories). +memtest02.mem1: removing const-0 lane 5 +memtest02.mem1: removing const-0 lane 6 +memtest02.mem1: removing const-0 lane 7 +Performed a total of 76 transformations. + +4.14.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 58 transformations. + +4.14.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + Analyzing memtest01.data write port 0. + Analyzing memtest02.mem1 write port 0. + Analyzing memtest02.mem1 write port 1. + Analyzing memtest02.mem1 write port 2. + Analyzing memtest02.mem1 write port 3. + Analyzing memtest02.mem1 write port 4. + Analyzing memtest02.mem1 write port 5. + Analyzing memtest03.memory write port 0. + Analyzing memtest04.memory write port 0. + Analyzing memtest05.mem write port 0. + Analyzing memtest05.mem write port 1. + Analyzing memtest05.mem write port 2. + Analyzing memtest05.mem write port 3. + Analyzing memtest06_sync.test write port 0. + Analyzing memtest06_sync.test write port 1. + Analyzing memtest06_sync.test write port 2. + Analyzing memtest06_sync.test write port 3. + Analyzing memtest06_sync.test write port 4. + Analyzing memtest06_sync.test write port 5. + Analyzing memtest06_sync.test write port 6. + Analyzing memtest06_sync.test write port 7. + Analyzing memtest06_sync.test write port 8. + Analyzing memtest06_sync.test write port 9. + Analyzing memtest06_sync.test write port 10. + Analyzing memtest06_sync.test write port 11. + Analyzing memtest06_sync.test write port 12. + Analyzing memtest07.mem write port 0. + Analyzing memtest08.mem write port 0. + Analyzing memtest09.memory write port 0. + Analyzing memtest09.memory write port 1. + Analyzing memtest11.mem write port 0. + Analyzing memtest11.mem write port 1. +Populating enable bits on write ports of memory memtest11.mem with async read feedback: + Port 1 bit 7: added enable logic for 1 different cases. + Port 1 bit 6: added enable logic for 1 different cases. + Port 1 bit 5: added enable logic for 1 different cases. + Port 1 bit 4: added enable logic for 1 different cases. + Port 1 bit 3: added enable logic for 1 different cases. + Port 1 bit 2: added enable logic for 1 different cases. + Port 1 bit 1: added enable logic for 1 different cases. + Port 1 bit 0: added enable logic for 1 different cases. + Analyzing memtest12.ram write port 0. + Analyzing memtest13.mem write port 0. + Analyzing memtest13.mem write port 1. + Analyzing memtest13.mem write port 2. + Analyzing memtest13.mem write port 3. + Analyzing memtest13.mem write port 4. + Analyzing memtest13.mem write port 5. + Analyzing memtest13.mem write port 6. + +4.14.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +4.14.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). +Checking read port `\data'[0] in module `\memtest01': merging output FF to cell. + Write port 0: non-transparent. +Checking read port `\mem1'[0] in module `\memtest02': no output FF found. +Checking read port address `\mem1'[0] in module `\memtest02': no address FF found. +Checking read port `\memory'[0] in module `\memtest03': merging output FF to cell. + Write port 0: non-transparent. +Checking read port `\memory'[0] in module `\memtest04': no output FF found. +Checking read port address `\memory'[0] in module `\memtest04': merged address FF to cell. +Checking read port `\mem'[0] in module `\memtest05': merging output FF to cell. + Write port 0: non-transparent. + Write port 1: non-transparent. + Write port 2: non-transparent. + Write port 3: non-transparent. +Checking read port `\test'[0] in module `\memtest06_sync': no output FF found. +Checking read port `\test'[1] in module `\memtest06_sync': no output FF found. +Checking read port address `\test'[0] in module `\memtest06_sync': no address FF found. +Checking read port address `\test'[1] in module `\memtest06_sync': no address FF found. +Checking read port `\mem'[0] in module `\memtest07': merging output FF to cell. + Write port 0: non-transparent. +Checking read port `\mem'[0] in module `\memtest08': merging output FF to cell. + Write port 0: non-transparent. +Checking read port `\memory'[0] in module `\memtest09': merging output FF to cell. + Write port 0: non-transparent. + Write port 1: non-transparent. +Checking read port `\memory'[1] in module `\memtest09': merging output FF to cell. + Write port 0: non-transparent. + Write port 1: non-transparent. +Checking read port `\mem'[0] in module `\memtest11': no output FF found. +Checking read port address `\mem'[0] in module `\memtest11': no address FF found. +Checking read port `\ram'[0] in module `\memtest12': merging output FF to cell. + Write port 0: non-transparent. +Checking read port `\mem'[0] in module `\memtest13': merging output FF to cell. + Write port 0: don't care on collision. + Write port 1: don't care on collision. + Write port 2: don't care on collision. + Write port 3: don't care on collision. + Write port 4: non-transparent. + Write port 5: non-transparent. + Write port 6: non-transparent. +Checking read port `\mem'[1] in module `\memtest13': no output FF found. +Checking read port `\mem'[2] in module `\memtest13': merging output FF to cell. + Write port 0: don't care on collision. + Write port 1: don't care on collision. + Write port 2: don't care on collision. + Write port 3: don't care on collision. + Write port 4: non-transparent. + Write port 5: non-transparent. + Write port 6: non-transparent. +Checking read port address `\mem'[1] in module `\memtest13': no address FF found. + +4.14.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memtest00.. +Finding unused cells or wires in module \memtest01.. +Finding unused cells or wires in module \memtest02.. +Finding unused cells or wires in module \memtest03.. +Finding unused cells or wires in module \memtest04.. +Finding unused cells or wires in module \memtest05.. +Finding unused cells or wires in module \memtest06_async.. +Finding unused cells or wires in module \memtest06_sync.. +Finding unused cells or wires in module \memtest07.. +Finding unused cells or wires in module \memtest08.. +Finding unused cells or wires in module \memtest09.. +Finding unused cells or wires in module \memtest10.. +Finding unused cells or wires in module \memtest11.. +Finding unused cells or wires in module \memtest12.. +Finding unused cells or wires in module \memtest13.. +Removed 11 unused cells and 85 unused wires. + + +4.14.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). +Consolidating write ports of memory memtest02.mem1 by address: + Merging ports 0, 1 (address 2'00). + Merging ports 0, 2 (address 2'00). + Merging ports 3, 4 (address 2'00). + Merging ports 3, 5 (address 2'00). +Consolidating write ports of memory memtest02.mem1 by address: +Consolidating write ports of memory memtest02.mem1 using sat-based resource sharing: + Checking group clocked with posedge \clk, width 20: ports 0, 1. + Common input cone for all EN signals: 2 cells. + Size of unconstrained SAT problem: 16 variables, 34 clauses + According to SAT solver sharing of port 0 with port 1 is not possible. +Consolidating write ports of memory memtest05.mem by address: + Merging ports 0, 1 (address \addr). + Merging ports 0, 2 (address \addr). + Merging ports 0, 3 (address \addr). +Consolidating read ports of memory memtest06_sync.test by address: +Consolidating write ports of memory memtest06_sync.test by address: + Merging ports 0, 1 (address 3'000). + Merging ports 0, 2 (address 3'000). + Merging ports 0, 3 (address 3'000). + Merging ports 0, 4 (address 3'000). + Merging ports 6, 7 (address 3'110). + Merging ports 8, 9 (address 3'000). + Merging ports 10, 11 (address \idx). + Merging ports 10, 12 (address \idx). +Consolidating write ports of memory memtest06_sync.test by address: + Merging ports 1, 2 (address 3'101). + Merging ports 1, 3 (address 3'100). +Consolidating write ports of memory memtest06_sync.test by address: +Consolidating write ports of memory memtest06_sync.test using sat-based resource sharing: + Checking group clocked with posedge \clk, width 64: ports 0, 1. + Common input cone for all EN signals: 2 cells. + Size of unconstrained SAT problem: 15 variables, 34 clauses + According to SAT solver sharing of port 0 with port 1 is not possible. +Consolidating read ports of memory memtest09.memory by address: +Consolidating write ports of memory memtest09.memory by address: +Consolidating write ports of memory memtest09.memory using sat-based resource sharing: + Checking group clocked with posedge \clk, width 4: ports 0, 1. + Common input cone for all EN signals: 8 cells. + Size of unconstrained SAT problem: 240 variables, 618 clauses + According to SAT solver sharing of port 0 with port 1 is not possible. +Consolidating write ports of memory memtest11.mem by address: + Merging ports 0, 1 (address \waddr). +Consolidating read ports of memory memtest13.mem by address: +Consolidating write ports of memory memtest13.mem by address: + Merging ports 0, 1 (address 2'00). + Merging ports 0, 2 (address 2'00). +Consolidating write ports of memory memtest13.mem by address: +Consolidating write ports of memory memtest13.mem using sat-based resource sharing: + Checking group clocked with posedge \clk, width 27: ports 1, 2, 3, 4. + Common input cone for all EN signals: 3 cells. + Size of unconstrained SAT problem: 204 variables, 466 clauses + Merging port 2 into port 1. + According to SAT solver sharing of port 1 with port 3 is not possible. + According to SAT solver sharing of port 1 with port 4 is not possible. + According to SAT solver sharing of port 3 with port 4 is not possible. + +4.14.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +4.14.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memtest00.. +Finding unused cells or wires in module \memtest01.. +Finding unused cells or wires in module \memtest02.. +Finding unused cells or wires in module \memtest03.. +Finding unused cells or wires in module \memtest04.. +Finding unused cells or wires in module \memtest05.. +Finding unused cells or wires in module \memtest06_async.. +Finding unused cells or wires in module \memtest06_sync.. +Finding unused cells or wires in module \memtest07.. +Finding unused cells or wires in module \memtest08.. +Finding unused cells or wires in module \memtest09.. +Finding unused cells or wires in module \memtest10.. +Finding unused cells or wires in module \memtest11.. +Finding unused cells or wires in module \memtest12.. +Finding unused cells or wires in module \memtest13.. +Removed 7 unused cells and 7 unused wires. + + +4.14.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +4.15. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memtest00.. +Finding unused cells or wires in module \memtest01.. +Finding unused cells or wires in module \memtest02.. +Finding unused cells or wires in module \memtest03.. +Finding unused cells or wires in module \memtest04.. +Finding unused cells or wires in module \memtest05.. +Finding unused cells or wires in module \memtest06_async.. +Finding unused cells or wires in module \memtest06_sync.. +Finding unused cells or wires in module \memtest07.. +Finding unused cells or wires in module \memtest08.. +Finding unused cells or wires in module \memtest09.. +Finding unused cells or wires in module \memtest10.. +Finding unused cells or wires in module \memtest11.. +Finding unused cells or wires in module \memtest12.. +Finding unused cells or wires in module \memtest13.. + +5. Executing OPT pass (performing simple optimizations). + +5.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module memtest00. +Optimizing module memtest01. + +Optimizing module memtest02. + +Optimizing module memtest03. + +Optimizing module memtest04. + +Optimizing module memtest05. + +Optimizing module memtest06_async. + +Optimizing module memtest06_sync. + +Optimizing module memtest07. +Optimizing module memtest08. + +Optimizing module memtest09. + +Optimizing module memtest10. +Optimizing module memtest11. + +Optimizing module memtest12. +Optimizing module memtest13. + + +5.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memtest00'. +Finding identical cells in module `\memtest01'. +Finding identical cells in module `\memtest02'. +Finding identical cells in module `\memtest03'. +Finding identical cells in module `\memtest04'. +Finding identical cells in module `\memtest05'. +Finding identical cells in module `\memtest06_async'. +Finding identical cells in module `\memtest06_sync'. +Finding identical cells in module `\memtest07'. +Finding identical cells in module `\memtest08'. +Finding identical cells in module `\memtest09'. +Finding identical cells in module `\memtest10'. +Finding identical cells in module `\memtest11'. +Finding identical cells in module `\memtest12'. +Finding identical cells in module `\memtest13'. + +Removed a total of 1 cells. + +5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \memtest00.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest01.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest02.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest03.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest04.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest05.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest06_async.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest06_sync.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest07.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest08.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest09.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest10.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest11.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest12.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest13.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Replacing known input bits on port B of cell $auto$memory_share.cc:453:consolidate_wr_using_sat$1578: $0$memwr$\mem$memory_ref.v:306$421_EN[26:0]$431 [26] -> 1'1 + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \memtest00. + Optimizing cells in module \memtest01. + Optimizing cells in module \memtest02. + Optimizing cells in module \memtest03. + Optimizing cells in module \memtest04. + Optimizing cells in module \memtest05. + Optimizing cells in module \memtest06_async. + Optimizing cells in module \memtest06_sync. + Optimizing cells in module \memtest07. + Optimizing cells in module \memtest08. + Optimizing cells in module \memtest09. + Optimizing cells in module \memtest10. + Optimizing cells in module \memtest11. + Optimizing cells in module \memtest12. + Optimizing cells in module \memtest13. +Performed a total of 0 changes. + +5.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memtest00'. +Finding identical cells in module `\memtest01'. +Finding identical cells in module `\memtest02'. +Finding identical cells in module `\memtest03'. +Finding identical cells in module `\memtest04'. +Finding identical cells in module `\memtest05'. +Finding identical cells in module `\memtest06_async'. +Finding identical cells in module `\memtest06_sync'. +Finding identical cells in module `\memtest07'. +Finding identical cells in module `\memtest08'. +Finding identical cells in module `\memtest09'. +Finding identical cells in module `\memtest10'. +Finding identical cells in module `\memtest11'. +Finding identical cells in module `\memtest12'. +Finding identical cells in module `\memtest13'. +Removed a total of 0 cells. + +5.6. Executing OPT_SHARE pass. + +5.7. Executing OPT_DFF pass (perform DFF optimizations). + +5.8. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memtest00.. +Finding unused cells or wires in module \memtest01.. +Finding unused cells or wires in module \memtest02.. +Finding unused cells or wires in module \memtest03.. +Finding unused cells or wires in module \memtest04.. +Finding unused cells or wires in module \memtest05.. +Finding unused cells or wires in module \memtest06_async.. +Finding unused cells or wires in module \memtest06_sync.. +Finding unused cells or wires in module \memtest07.. +Finding unused cells or wires in module \memtest08.. +Finding unused cells or wires in module \memtest09.. +Finding unused cells or wires in module \memtest10.. +Finding unused cells or wires in module \memtest11.. +Finding unused cells or wires in module \memtest12.. +Finding unused cells or wires in module \memtest13.. +Removed 2 unused cells and 51 unused wires. + + +5.9. Executing OPT_EXPR pass (perform const folding). +Optimizing module memtest00. +Optimizing module memtest01. +Optimizing module memtest02. + +Optimizing module memtest03. +Optimizing module memtest04. +Optimizing module memtest05. +Optimizing module memtest06_async. +Optimizing module memtest06_sync. +Optimizing module memtest07. +Optimizing module memtest08. +Optimizing module memtest09. +Optimizing module memtest10. +Optimizing module memtest11. +Optimizing module memtest12. +Optimizing module memtest13. + + +5.10. Rerunning OPT passes. (Maybe there is more to do..) + +5.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \memtest00.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest01.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest02.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest03.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest04.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest05.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest06_async.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest06_sync.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest07.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest08.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest09.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest10.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest11.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest12.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest13.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +5.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \memtest00. + Optimizing cells in module \memtest01. + Optimizing cells in module \memtest02. + Consolidated identical input bits for $pmux cell $procmux$1011: + Old ports: A={ 1'0 \mem2[0] [6] 1'0 \mem2[0] [4] 1'0 \mem2[0] [2:1] 1'1 }, B={ 1'0 \mem2[1] [6] 1'0 \mem2[1] [4] 2'10 \mem2[1] [1:0] 1'0 \mem2[2] [6:5] 1'0 \mem2[2] [3:2] 2'01 }, Y=$0$mem2reg_rd$\mem2$memory_ref.v:71$16_DATA[7:0]$28 + New ports: A={ \mem2[0] [6] 1'0 \mem2[0] [4] 1'0 \mem2[0] [2:1] 1'1 }, B={ \mem2[1] [6] 1'0 \mem2[1] [4] 2'10 \mem2[1] [1:0] \mem2[2] [6:5] 1'0 \mem2[2] [3:2] 2'01 }, Y=$0$mem2reg_rd$\mem2$memory_ref.v:71$16_DATA[7:0]$28 [6:0] + New connections: $0$mem2reg_rd$\mem2$memory_ref.v:71$16_DATA[7:0]$28 [7] = 1'0 + Optimizing cells in module \memtest02. + Optimizing cells in module \memtest03. + Optimizing cells in module \memtest04. + Optimizing cells in module \memtest05. + Optimizing cells in module \memtest06_async. + Optimizing cells in module \memtest06_sync. + Optimizing cells in module \memtest07. + Optimizing cells in module \memtest08. + Optimizing cells in module \memtest09. + Optimizing cells in module \memtest10. + Optimizing cells in module \memtest11. + Optimizing cells in module \memtest12. + Optimizing cells in module \memtest13. +Performed a total of 1 changes. + +5.13. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memtest00'. +Finding identical cells in module `\memtest01'. +Finding identical cells in module `\memtest02'. +Finding identical cells in module `\memtest03'. +Finding identical cells in module `\memtest04'. +Finding identical cells in module `\memtest05'. +Finding identical cells in module `\memtest06_async'. +Finding identical cells in module `\memtest06_sync'. +Finding identical cells in module `\memtest07'. +Finding identical cells in module `\memtest08'. +Finding identical cells in module `\memtest09'. +Finding identical cells in module `\memtest10'. +Finding identical cells in module `\memtest11'. +Finding identical cells in module `\memtest12'. +Finding identical cells in module `\memtest13'. +Removed a total of 0 cells. + +5.14. Executing OPT_SHARE pass. + +5.15. Executing OPT_DFF pass (perform DFF optimizations). + +5.16. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memtest00.. +Finding unused cells or wires in module \memtest01.. +Finding unused cells or wires in module \memtest02.. +Finding unused cells or wires in module \memtest03.. +Finding unused cells or wires in module \memtest04.. +Finding unused cells or wires in module \memtest05.. +Finding unused cells or wires in module \memtest06_async.. +Finding unused cells or wires in module \memtest06_sync.. +Finding unused cells or wires in module \memtest07.. +Finding unused cells or wires in module \memtest08.. +Finding unused cells or wires in module \memtest09.. +Finding unused cells or wires in module \memtest10.. +Finding unused cells or wires in module \memtest11.. +Finding unused cells or wires in module \memtest12.. +Finding unused cells or wires in module \memtest13.. +Removed 1 unused cells and 2 unused wires. + + +5.17. Executing OPT_EXPR pass (perform const folding). +Optimizing module memtest00. +Optimizing module memtest01. +Optimizing module memtest02. +Optimizing module memtest03. +Optimizing module memtest04. +Optimizing module memtest05. +Optimizing module memtest06_async. +Optimizing module memtest06_sync. +Optimizing module memtest07. +Optimizing module memtest08. +Optimizing module memtest09. +Optimizing module memtest10. +Optimizing module memtest11. +Optimizing module memtest12. +Optimizing module memtest13. + +5.18. Rerunning OPT passes. (Maybe there is more to do..) + +5.19. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \memtest00.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest01.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest02.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest03.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest04.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest05.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest06_async.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest06_sync.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \memtest07.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest08.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest09.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest10.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest11.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest12.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \memtest13.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +5.20. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \memtest00. + Optimizing cells in module \memtest01. + Optimizing cells in module \memtest02. + Optimizing cells in module \memtest03. + Optimizing cells in module \memtest04. + Optimizing cells in module \memtest05. + Optimizing cells in module \memtest06_async. + Optimizing cells in module \memtest06_sync. + Optimizing cells in module \memtest07. + Optimizing cells in module \memtest08. + Optimizing cells in module \memtest09. + Optimizing cells in module \memtest10. + Optimizing cells in module \memtest11. + Optimizing cells in module \memtest12. + Optimizing cells in module \memtest13. +Performed a total of 0 changes. + +5.21. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memtest00'. +Finding identical cells in module `\memtest01'. +Finding identical cells in module `\memtest02'. +Finding identical cells in module `\memtest03'. +Finding identical cells in module `\memtest04'. +Finding identical cells in module `\memtest05'. +Finding identical cells in module `\memtest06_async'. +Finding identical cells in module `\memtest06_sync'. +Finding identical cells in module `\memtest07'. +Finding identical cells in module `\memtest08'. +Finding identical cells in module `\memtest09'. +Finding identical cells in module `\memtest10'. +Finding identical cells in module `\memtest11'. +Finding identical cells in module `\memtest12'. +Finding identical cells in module `\memtest13'. +Removed a total of 0 cells. + +5.22. Executing OPT_SHARE pass. + +5.23. Executing OPT_DFF pass (perform DFF optimizations). + +5.24. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memtest00.. +Finding unused cells or wires in module \memtest01.. +Finding unused cells or wires in module \memtest02.. +Finding unused cells or wires in module \memtest03.. +Finding unused cells or wires in module \memtest04.. +Finding unused cells or wires in module \memtest05.. +Finding unused cells or wires in module \memtest06_async.. +Finding unused cells or wires in module \memtest06_sync.. +Finding unused cells or wires in module \memtest07.. +Finding unused cells or wires in module \memtest08.. +Finding unused cells or wires in module \memtest09.. +Finding unused cells or wires in module \memtest10.. +Finding unused cells or wires in module \memtest11.. +Finding unused cells or wires in module \memtest12.. +Finding unused cells or wires in module \memtest13.. + +5.25. Executing OPT_EXPR pass (perform const folding). +Optimizing module memtest00. +Optimizing module memtest01. +Optimizing module memtest02. +Optimizing module memtest03. +Optimizing module memtest04. +Optimizing module memtest05. +Optimizing module memtest06_async. +Optimizing module memtest06_sync. +Optimizing module memtest07. +Optimizing module memtest08. +Optimizing module memtest09. +Optimizing module memtest10. +Optimizing module memtest11. +Optimizing module memtest12. +Optimizing module memtest13. + +5.26. Finished OPT passes. (There is nothing left to do.) + +6. Executing TECHMAP pass (map to technology primitives). + +6.1. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/techmap.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +6.2. Continuing TECHMAP pass. +Using extmapper maccmap for cells of type $macc. + add \off1 (4 bits, unsigned) + add \off2 (4 bits, unsigned) +Using template $paramod$constmap:d86f4f9d093692d5234fe301cf2e145804f3c20a$paramod$09c85ea041cfda80b9c3e1d6e784839adb3d903e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. +Analyzing pattern of constant bits for this cell: + Constant input on bit 0 of port A: 1'1 + Constant input on bit 1 of port A: 1'1 + Constant input on bit 2 of port A: 1'1 + Constant input on bit 3 of port A: 1'1 + Bit 6 of port B and bit 5 of port B are connected. + Bit 7 of port B and bit 5 of port B are connected. + Bit 8 of port B and bit 5 of port B are connected. + Bit 9 of port B and bit 5 of port B are connected. + Bit 10 of port B and bit 5 of port B are connected. + Bit 11 of port B and bit 5 of port B are connected. + Bit 12 of port B and bit 5 of port B are connected. + Bit 13 of port B and bit 5 of port B are connected. + Bit 14 of port B and bit 5 of port B are connected. + Bit 15 of port B and bit 5 of port B are connected. + Bit 16 of port B and bit 5 of port B are connected. + Bit 17 of port B and bit 5 of port B are connected. + Bit 18 of port B and bit 5 of port B are connected. + Bit 19 of port B and bit 5 of port B are connected. + Bit 20 of port B and bit 5 of port B are connected. + Bit 21 of port B and bit 5 of port B are connected. + Bit 22 of port B and bit 5 of port B are connected. + Bit 23 of port B and bit 5 of port B are connected. + Bit 24 of port B and bit 5 of port B are connected. + Bit 25 of port B and bit 5 of port B are connected. + Bit 26 of port B and bit 5 of port B are connected. + Bit 27 of port B and bit 5 of port B are connected. + Bit 28 of port B and bit 5 of port B are connected. + Bit 29 of port B and bit 5 of port B are connected. + Bit 30 of port B and bit 5 of port B are connected. + Bit 31 of port B and bit 5 of port B are connected. +Creating constmapped module `$paramod$constmap:e8bf115bc1b09ae996e23225f8453ee4df303d23$paramod$09c85ea041cfda80b9c3e1d6e784839adb3d903e\_90_shift_ops_shr_shl_sshl_sshr'. + +6.8. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:e8bf115bc1b09ae996e23225f8453ee4df303d23$paramod$09c85ea041cfda80b9c3e1d6e784839adb3d903e\_90_shift_ops_shr_shl_sshl_sshr.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + + +6.9. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:e8bf115bc1b09ae996e23225f8453ee4df303d23$paramod$09c85ea041cfda80b9c3e1d6e784839adb3d903e\_90_shift_ops_shr_shl_sshl_sshr. + +Removed 0 unused cells and 15 unused wires. +Using template $paramod$constmap:e8bf115bc1b09ae996e23225f8453ee4df303d23$paramod$09c85ea041cfda80b9c3e1d6e784839adb3d903e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. +Using template $paramod$constmap:7ee925567db15a43161bd110370f2f1f87f1d80e$paramod$bd39882db1303613e10879f9fd08465cb0f20532\_90_shift_shiftx for cells of type $shiftx. +Using extmapper simplemap for cells of type $not. +Using extmapper simplemap for cells of type $logic_not. +Using extmapper simplemap for cells of type $dffe. +Using extmapper simplemap for cells of type $dff. +Using template $paramod$0563fff2c395e9892f21c131fa33d5e0ad144e72\_90_alu for cells of type $alu. +Using template $paramod$aebc44f5eedf4f1603d7564e4920ac508059c773\_90_alu for cells of type $alu. +Using extmapper simplemap for cells of type $ne. +Using extmapper simplemap for cells of type $logic_or. +Using extmapper simplemap for cells of type $logic_and. +Using extmapper simplemap for cells of type $pos. +Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu. +Using extmapper simplemap for cells of type $and. +Using extmapper simplemap for cells of type $xor. +Using extmapper simplemap for cells of type $or. +Using template $paramod$constmap:c234fc9e9444480dc4664b8a71dddde60decac86$paramod$d45a745761a8cee5fd89c8b85b79c07cde203344\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. +Analyzing pattern of constant bits for this cell: + Constant input on bit 0 of port A: 1'1 + Constant input on bit 1 of port A: 1'1 + Constant input on bit 2 of port A: 1'1 + Constant input on bit 3 of port A: 1'1 +Creating constmapped module `$paramod$constmap:067ff0cf0273578988bc21056c52c343a10cf874$paramod$d45a745761a8cee5fd89c8b85b79c07cde203344\_90_shift_ops_shr_shl_sshl_sshr'. + +6.28. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:067ff0cf0273578988bc21056c52c343a10cf874$paramod$d45a745761a8cee5fd89c8b85b79c07cde203344\_90_shift_ops_shr_shl_sshl_sshr.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + + +6.29. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:067ff0cf0273578988bc21056c52c343a10cf874$paramod$d45a745761a8cee5fd89c8b85b79c07cde203344\_90_shift_ops_shr_shl_sshl_sshr. + +Removed 0 unused cells and 7 unused wires. +Using template $paramod$constmap:067ff0cf0273578988bc21056c52c343a10cf874$paramod$d45a745761a8cee5fd89c8b85b79c07cde203344\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. +Using template $paramod$constmap:ee5af906ae0d3d414c6a0471604c553ef70c8e09$paramod$92adee9538f2381d8e5006822c900eb986d754e8\_90_shift_shiftx for cells of type $shiftx. +Using template $paramod$constmap:f062eb9b59fe112e8a37f22ba8867a126e0dc845$paramod$3b3a66a7766bf28794ddcd35314b025da1fe57c8\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. +Analyzing pattern of constant bits for this cell: + Constant input on bit 0 of port A: 1'1 +Creating constmapped module `$paramod$constmap:1b6115d36d46c0296d0024e3e3623593810ba834$paramod$3b3a66a7766bf28794ddcd35314b025da1fe57c8\_90_shift_ops_shr_shl_sshl_sshr'. + +6.40. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:1b6115d36d46c0296d0024e3e3623593810ba834$paramod$3b3a66a7766bf28794ddcd35314b025da1fe57c8\_90_shift_ops_shr_shl_sshl_sshr.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + + +6.41. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:1b6115d36d46c0296d0024e3e3623593810ba834$paramod$3b3a66a7766bf28794ddcd35314b025da1fe57c8\_90_shift_ops_shr_shl_sshl_sshr. + +Removed 0 unused cells and 8 unused wires. +Using template $paramod$constmap:1b6115d36d46c0296d0024e3e3623593810ba834$paramod$3b3a66a7766bf28794ddcd35314b025da1fe57c8\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. +Using extmapper simplemap for cells of type $adff. +Using template $paramod$d7387fdb214042e5ef2d69a3f74948694b4bb65e\_90_pmux for cells of type $pmux. +Using template $paramod$025d767fc934a3e7d59a671de523743ebaa07759\_90_alu for cells of type $alu. diff --git a/tests/simple_abc9/multiplier.err b/tests/simple_abc9/multiplier.err new file mode 100644 index 00000000000..2f7ce213f6b --- /dev/null +++ b/tests/simple_abc9/multiplier.err @@ -0,0 +1,1388 @@ ++ body ++ cd multiplier.out +++ basename multiplier.v ++ fn=multiplier.v +++ basename multiplier ++ bn=multiplier ++ refext=v ++ rm -f multiplier_ref.fir ++ [[ v == \v ]] ++ egrep -v '^\s*`timescale' ../multiplier.v +egrep: warning: egrep is obsolescent; using grep -E ++ '[' '!' -f ../multiplier_tb.v ']' ++ /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../yosys -f 'verilog -noblackbox -specify -D_AUTOTB' -b 'test_autotb -n 300' -o multiplier_tb.v multiplier_ref.v + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2024 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) + +-- Parsing `multiplier_ref.v' using frontend `verilog -noblackbox -specify -D_AUTOTB' -- + +1. Executing Verilog-2005 frontend: multiplier_ref.v +Parsing Verilog input from `multiplier_ref.v' to AST representation. +Generating RTLIL representation for module `\Multiplier_flat'. +Generating RTLIL representation for module `\Multiplier_2D'. +Generating RTLIL representation for module `\RippleCarryAdder'. +Generating RTLIL representation for module `\FullAdder'. +Successfully finished Verilog frontend. + +-- Writing to `multiplier_tb.v' using backend `test_autotb -n 300' -- + +2. Executing TEST_AUTOTB backend (auto-generate pseudo-random test benches). +Generating test bench for module `\FullAdder'. +Generating test bench for module `\RippleCarryAdder'. +Generating test bench for module `\Multiplier_2D'. +Generating test bench for module `\Multiplier_flat'. + +End of script. Logfile hash: 5639294ea1, CPU: user 0.00s system 0.00s, MEM: 14.53 MB peak +Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) +Time spent: 96% 1x read_verilog (0 sec), 3% 1x test_autotb (0 sec) ++ false ++ compile_and_run multiplier_tb_ref multiplier_out_ref multiplier_tb.v multiplier_ref.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simlib.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simcells.v ++ exe=multiplier_tb_ref ++ output=multiplier_out_ref ++ shift 2 ++ '[' v == sv ']' ++ language_gen=-g2005 ++ false ++ false ++ iverilog -g2005 '-Doutfile="multiplier_out_ref"' -s testbench -o multiplier_tb_ref multiplier_tb.v multiplier_ref.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simlib.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simcells.v ++ vvp -n multiplier_tb_ref +multiplier_tb.v:326: $finish called at 480800 (1s) ++ false ++ test_count=0 ++ '[' 'verilog -noblackbox -specify' = verific -o 'verilog -noblackbox -specify' = verific_gates ']' ++ '[' -n '' ']' ++ '[' -n ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' ']' ++ test_passes -f 'verilog -noblackbox -specify ' -p ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' multiplier_ref.v ++ /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../yosys -b 'verilog -noattr -noexpr -siminit' -o multiplier_syn0.v -f 'verilog -noblackbox -specify ' -p ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' multiplier_ref.v + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2024 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) + +-- Parsing `multiplier_ref.v' using frontend `verilog -noblackbox -specify ' -- + +1. Executing Verilog-2005 frontend: multiplier_ref.v +Parsing Verilog input from `multiplier_ref.v' to AST representation. +Generating RTLIL representation for module `\Multiplier_flat'. +Generating RTLIL representation for module `\Multiplier_2D'. +Generating RTLIL representation for module `\RippleCarryAdder'. +Generating RTLIL representation for module `\FullAdder'. +Successfully finished Verilog frontend. + +-- Running command ` read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' -- + +2. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v' to AST representation. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +3. Executing HIERARCHY pass (managing design hierarchy). +Parameter 1 (\N) = 7 + +3.1. Executing AST frontend in derive mode using pre-parsed AST for module `\RippleCarryAdder'. +Parameter 1 (\N) = 7 +Generating RTLIL representation for module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111'. +Parameter 1 (\N) = 6 + +3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\RippleCarryAdder'. +Parameter 1 (\N) = 6 +Generating RTLIL representation for module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110'. +Parameter 1 (\N) = 5 + +3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\RippleCarryAdder'. +Parameter 1 (\N) = 5 +Generating RTLIL representation for module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101'. +Parameter 1 (\N) = 7 +Found cached RTLIL representation for module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111'. +Parameter 1 (\N) = 6 +Found cached RTLIL representation for module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110'. +Parameter 1 (\N) = 5 +Found cached RTLIL representation for module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101'. +Mapping positional arguments of cell $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101.addbit[4].unit (FullAdder). +Mapping positional arguments of cell $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101.addbit[3].unit (FullAdder). +Mapping positional arguments of cell $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101.addbit[2].unit (FullAdder). +Mapping positional arguments of cell $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101.addbit[1].unit (FullAdder). +Mapping positional arguments of cell $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101.addbit[0].unit (FullAdder). +Mapping positional arguments of cell $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110.addbit[5].unit (FullAdder). +Mapping positional arguments of cell $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110.addbit[4].unit (FullAdder). +Mapping positional arguments of cell $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110.addbit[3].unit (FullAdder). +Mapping positional arguments of cell $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110.addbit[2].unit (FullAdder). +Mapping positional arguments of cell $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110.addbit[1].unit (FullAdder). +Mapping positional arguments of cell $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110.addbit[0].unit (FullAdder). +Mapping positional arguments of cell $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111.addbit[6].unit (FullAdder). +Mapping positional arguments of cell $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111.addbit[5].unit (FullAdder). +Mapping positional arguments of cell $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111.addbit[4].unit (FullAdder). +Mapping positional arguments of cell $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111.addbit[3].unit (FullAdder). +Mapping positional arguments of cell $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111.addbit[2].unit (FullAdder). +Mapping positional arguments of cell $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111.addbit[1].unit (FullAdder). +Mapping positional arguments of cell $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111.addbit[0].unit (FullAdder). +Mapping positional arguments of cell RippleCarryAdder.addbit[3].unit (FullAdder). +Mapping positional arguments of cell RippleCarryAdder.addbit[2].unit (FullAdder). +Mapping positional arguments of cell RippleCarryAdder.addbit[1].unit (FullAdder). +Mapping positional arguments of cell RippleCarryAdder.addbit[0].unit (FullAdder). + +4. Executing SYNTH pass. + +4.1. Executing PROC pass (convert processes to netlists). + +4.1.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +4.1.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +4.1.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 4 assignments to connections. + +4.1.4. Executing PROC_INIT pass (extract init attributes). + +4.1.5. Executing PROC_ARST pass (detect async resets in processes). + +4.1.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + +4.1.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\Multiplier_2D.$proc$multiplier_ref.v:0$8'. + +4.1.8. Executing PROC_DLATCH pass (convert process syncs to latches). +No latch inferred for signal `\Multiplier_2D.\PP[0]' from process `\Multiplier_2D.$proc$multiplier_ref.v:0$8'. +No latch inferred for signal `\Multiplier_2D.\PP[1]' from process `\Multiplier_2D.$proc$multiplier_ref.v:0$8'. +No latch inferred for signal `\Multiplier_2D.\PP[2]' from process `\Multiplier_2D.$proc$multiplier_ref.v:0$8'. +No latch inferred for signal `\Multiplier_2D.\PP[3]' from process `\Multiplier_2D.$proc$multiplier_ref.v:0$8'. + +4.1.9. Executing PROC_DFF pass (convert process syncs to FFs). + +4.1.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +4.1.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `Multiplier_2D.$proc$multiplier_ref.v:0$8'. +Cleaned up 0 empty switches. + +4.1.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101. +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110. +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111. +Optimizing module FullAdder. +Optimizing module RippleCarryAdder. +Optimizing module Multiplier_2D. +Optimizing module Multiplier_flat. + +4.2. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101. +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110. +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111. +Optimizing module FullAdder. +Optimizing module RippleCarryAdder. +Optimizing module Multiplier_2D. +Optimizing module Multiplier_flat. + +4.3. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101.. +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110.. +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111.. +Finding unused cells or wires in module \FullAdder.. +Finding unused cells or wires in module \RippleCarryAdder.. +Finding unused cells or wires in module \Multiplier_2D.. +Finding unused cells or wires in module \Multiplier_flat.. +Removed 0 unused cells and 13 unused wires. + + +4.4. Executing CHECK pass (checking for obvious problems). +Checking module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101... +Checking module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110... +Checking module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111... +Checking module FullAdder... +Checking module Multiplier_2D... +Checking module Multiplier_flat... +Checking module RippleCarryAdder... +Found and reported 0 problems. + +4.5. Executing OPT pass (performing simple optimizations). + +4.5.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101. +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110. +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111. +Optimizing module FullAdder. +Optimizing module Multiplier_2D. +Optimizing module Multiplier_flat. +Optimizing module RippleCarryAdder. + +4.5.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101'. +Finding identical cells in module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110'. +Finding identical cells in module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111'. +Finding identical cells in module `\FullAdder'. +Finding identical cells in module `\Multiplier_2D'. +Finding identical cells in module `\Multiplier_flat'. +Finding identical cells in module `\RippleCarryAdder'. +Removed a total of 0 cells. + +4.5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \FullAdder.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \Multiplier_2D.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \Multiplier_flat.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \RippleCarryAdder.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101. + Optimizing cells in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110. + Optimizing cells in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111. + Optimizing cells in module \FullAdder. + Optimizing cells in module \Multiplier_2D. + Optimizing cells in module \Multiplier_flat. + Optimizing cells in module \RippleCarryAdder. +Performed a total of 0 changes. + +4.5.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101'. +Finding identical cells in module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110'. +Finding identical cells in module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111'. +Finding identical cells in module `\FullAdder'. +Finding identical cells in module `\Multiplier_2D'. +Finding identical cells in module `\Multiplier_flat'. +Finding identical cells in module `\RippleCarryAdder'. +Removed a total of 0 cells. + +4.5.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.5.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101.. +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110.. +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111.. +Finding unused cells or wires in module \FullAdder.. +Finding unused cells or wires in module \Multiplier_2D.. +Finding unused cells or wires in module \Multiplier_flat.. +Finding unused cells or wires in module \RippleCarryAdder.. + +4.5.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101. +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110. +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111. +Optimizing module FullAdder. +Optimizing module Multiplier_2D. +Optimizing module Multiplier_flat. +Optimizing module RippleCarryAdder. + +4.5.9. Finished OPT passes. (There is nothing left to do.) + +4.6. Executing FSM pass (extract and optimize FSM). + +4.6.1. Executing FSM_DETECT pass (finding FSMs in design). + +4.6.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +4.6.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.6.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101.. +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110.. +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111.. +Finding unused cells or wires in module \FullAdder.. +Finding unused cells or wires in module \Multiplier_2D.. +Finding unused cells or wires in module \Multiplier_flat.. +Finding unused cells or wires in module \RippleCarryAdder.. + +4.6.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.6.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +4.6.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +4.6.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +4.7. Executing OPT pass (performing simple optimizations). + +4.7.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101. +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110. +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111. +Optimizing module FullAdder. +Optimizing module Multiplier_2D. +Optimizing module Multiplier_flat. +Optimizing module RippleCarryAdder. + +4.7.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101'. +Finding identical cells in module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110'. +Finding identical cells in module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111'. +Finding identical cells in module `\FullAdder'. +Finding identical cells in module `\Multiplier_2D'. +Finding identical cells in module `\Multiplier_flat'. +Finding identical cells in module `\RippleCarryAdder'. +Removed a total of 0 cells. + +4.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \FullAdder.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \Multiplier_2D.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \Multiplier_flat.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \RippleCarryAdder.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101. + Optimizing cells in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110. + Optimizing cells in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111. + Optimizing cells in module \FullAdder. + Optimizing cells in module \Multiplier_2D. + Optimizing cells in module \Multiplier_flat. + Optimizing cells in module \RippleCarryAdder. +Performed a total of 0 changes. + +4.7.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101'. +Finding identical cells in module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110'. +Finding identical cells in module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111'. +Finding identical cells in module `\FullAdder'. +Finding identical cells in module `\Multiplier_2D'. +Finding identical cells in module `\Multiplier_flat'. +Finding identical cells in module `\RippleCarryAdder'. +Removed a total of 0 cells. + +4.7.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101.. +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110.. +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111.. +Finding unused cells or wires in module \FullAdder.. +Finding unused cells or wires in module \Multiplier_2D.. +Finding unused cells or wires in module \Multiplier_flat.. +Finding unused cells or wires in module \RippleCarryAdder.. + +4.7.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101. +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110. +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111. +Optimizing module FullAdder. +Optimizing module Multiplier_2D. +Optimizing module Multiplier_flat. +Optimizing module RippleCarryAdder. + +4.7.9. Finished OPT passes. (There is nothing left to do.) + +4.8. Executing WREDUCE pass (reducing word size of cells). +Removed top 4 bits (of 8) from wire Multiplier_2D.PP[0]. +Removed top 1 bits (of 5) from wire Multiplier_2D.addPartialProduct[1].gB. +Removed top 1 bits (of 5) from wire Multiplier_flat.addPartialProduct[1].gB. + +4.9. Executing PEEPOPT pass (run peephole optimizers). + +4.10. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101.. +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110.. +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111.. +Finding unused cells or wires in module \FullAdder.. +Finding unused cells or wires in module \Multiplier_2D.. +Finding unused cells or wires in module \Multiplier_flat.. +Finding unused cells or wires in module \RippleCarryAdder.. +Removed 0 unused cells and 3 unused wires. + + +4.11. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module FullAdder: + creating $macc model for $add$multiplier_ref.v:131$10 ($add). + creating $macc model for $add$multiplier_ref.v:131$11 ($add). + merging $macc model for $add$multiplier_ref.v:131$10 into $add$multiplier_ref.v:131$11. + creating $alu model for $macc $add$multiplier_ref.v:131$11. + creating $alu cell for $add$multiplier_ref.v:131$11: $auto$alumacc.cc:485:replace_alu$15 + created 1 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module Multiplier_2D: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module Multiplier_flat: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module RippleCarryAdder: + created 0 $alu and 0 $macc cells. + +4.12. Executing SHARE pass (SAT-based resource sharing). + +4.13. Executing OPT pass (performing simple optimizations). + +4.13.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101. +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110. +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111. +Optimizing module FullAdder. +Optimizing module Multiplier_2D. +Optimizing module Multiplier_flat. +Optimizing module RippleCarryAdder. + +4.13.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101'. +Finding identical cells in module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110'. +Finding identical cells in module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111'. +Finding identical cells in module `\FullAdder'. +Finding identical cells in module `\Multiplier_2D'. +Finding identical cells in module `\Multiplier_flat'. +Finding identical cells in module `\RippleCarryAdder'. +Removed a total of 0 cells. + +4.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \FullAdder.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \Multiplier_2D.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \Multiplier_flat.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \RippleCarryAdder.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101. + Optimizing cells in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110. + Optimizing cells in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111. + Optimizing cells in module \FullAdder. + Optimizing cells in module \Multiplier_2D. + Optimizing cells in module \Multiplier_flat. + Optimizing cells in module \RippleCarryAdder. +Performed a total of 0 changes. + +4.13.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101'. +Finding identical cells in module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110'. +Finding identical cells in module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111'. +Finding identical cells in module `\FullAdder'. +Finding identical cells in module `\Multiplier_2D'. +Finding identical cells in module `\Multiplier_flat'. +Finding identical cells in module `\RippleCarryAdder'. +Removed a total of 0 cells. + +4.13.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101.. +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110.. +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111.. +Finding unused cells or wires in module \FullAdder.. +Finding unused cells or wires in module \Multiplier_2D.. +Finding unused cells or wires in module \Multiplier_flat.. +Finding unused cells or wires in module \RippleCarryAdder.. +Removed 1 unused cells and 1 unused wires. + + +4.13.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101. +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110. +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111. +Optimizing module FullAdder. +Optimizing module Multiplier_2D. +Optimizing module Multiplier_flat. +Optimizing module RippleCarryAdder. + +4.13.9. Rerunning OPT passes. (Maybe there is more to do..) + +4.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \FullAdder.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \Multiplier_2D.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \Multiplier_flat.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \RippleCarryAdder.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101. + Optimizing cells in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110. + Optimizing cells in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111. + Optimizing cells in module \FullAdder. + Optimizing cells in module \Multiplier_2D. + Optimizing cells in module \Multiplier_flat. + Optimizing cells in module \RippleCarryAdder. +Performed a total of 0 changes. + +4.13.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101'. +Finding identical cells in module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110'. +Finding identical cells in module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111'. +Finding identical cells in module `\FullAdder'. +Finding identical cells in module `\Multiplier_2D'. +Finding identical cells in module `\Multiplier_flat'. +Finding identical cells in module `\RippleCarryAdder'. +Removed a total of 0 cells. + +4.13.13. Executing OPT_DFF pass (perform DFF optimizations). + +4.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101.. +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110.. +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111.. +Finding unused cells or wires in module \FullAdder.. +Finding unused cells or wires in module \Multiplier_2D.. +Finding unused cells or wires in module \Multiplier_flat.. +Finding unused cells or wires in module \RippleCarryAdder.. + +4.13.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101. +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110. +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111. +Optimizing module FullAdder. +Optimizing module Multiplier_2D. +Optimizing module Multiplier_flat. +Optimizing module RippleCarryAdder. + +4.13.16. Finished OPT passes. (There is nothing left to do.) + +4.14. Executing MEMORY pass. + +4.14.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +4.14.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +4.14.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + +4.14.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +4.14.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). + +4.14.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101.. +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110.. +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111.. +Finding unused cells or wires in module \FullAdder.. +Finding unused cells or wires in module \Multiplier_2D.. +Finding unused cells or wires in module \Multiplier_flat.. +Finding unused cells or wires in module \RippleCarryAdder.. + +4.14.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +4.14.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +4.14.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101.. +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110.. +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111.. +Finding unused cells or wires in module \FullAdder.. +Finding unused cells or wires in module \Multiplier_2D.. +Finding unused cells or wires in module \Multiplier_flat.. +Finding unused cells or wires in module \RippleCarryAdder.. + +4.14.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +4.15. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101.. +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110.. +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111.. +Finding unused cells or wires in module \FullAdder.. +Finding unused cells or wires in module \Multiplier_2D.. +Finding unused cells or wires in module \Multiplier_flat.. +Finding unused cells or wires in module \RippleCarryAdder.. + +5. Executing OPT pass (performing simple optimizations). + +5.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101. +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110. +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111. +Optimizing module FullAdder. +Optimizing module Multiplier_2D. +Optimizing module Multiplier_flat. +Optimizing module RippleCarryAdder. + +5.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101'. +Finding identical cells in module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110'. +Finding identical cells in module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111'. +Finding identical cells in module `\FullAdder'. +Finding identical cells in module `\Multiplier_2D'. +Finding identical cells in module `\Multiplier_flat'. +Finding identical cells in module `\RippleCarryAdder'. +Removed a total of 0 cells. + +5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \FullAdder.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \Multiplier_2D.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \Multiplier_flat.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \RippleCarryAdder.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101. + Optimizing cells in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110. + Optimizing cells in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111. + Optimizing cells in module \FullAdder. + Optimizing cells in module \Multiplier_2D. + Optimizing cells in module \Multiplier_flat. + Optimizing cells in module \RippleCarryAdder. +Performed a total of 0 changes. + +5.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101'. +Finding identical cells in module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110'. +Finding identical cells in module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111'. +Finding identical cells in module `\FullAdder'. +Finding identical cells in module `\Multiplier_2D'. +Finding identical cells in module `\Multiplier_flat'. +Finding identical cells in module `\RippleCarryAdder'. +Removed a total of 0 cells. + +5.6. Executing OPT_SHARE pass. + +5.7. Executing OPT_DFF pass (perform DFF optimizations). + +5.8. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101.. +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110.. +Finding unused cells or wires in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111.. +Finding unused cells or wires in module \FullAdder.. +Finding unused cells or wires in module \Multiplier_2D.. +Finding unused cells or wires in module \Multiplier_flat.. +Finding unused cells or wires in module \RippleCarryAdder.. + +5.9. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101. +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110. +Optimizing module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111. +Optimizing module FullAdder. +Optimizing module Multiplier_2D. +Optimizing module Multiplier_flat. +Optimizing module RippleCarryAdder. + +5.10. Finished OPT passes. (There is nothing left to do.) + +6. Executing TECHMAP pass (map to technology primitives). + +6.1. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/techmap.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +6.2. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $and. +Using template $paramod$1d1e68f77481583066c6d429218f48ea9d5739b3\_90_alu for cells of type $alu. +Using extmapper simplemap for cells of type $xor. +Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. +Using extmapper simplemap for cells of type $pos. +Using extmapper simplemap for cells of type $mux. +Using extmapper simplemap for cells of type $not. +Using extmapper simplemap for cells of type $or. +No more expansions possible. + + +7. Executing ABC9 pass. + +7.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.2. Executing ABC9_OPS pass (helper functions for ABC9). + +7.3. Executing SCC pass (detecting logic loops). +Found 0 SCCs in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101. +Found 0 SCCs in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110. +Found 0 SCCs in module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111. +Found 0 SCCs in module FullAdder. +Found 0 SCCs in module Multiplier_2D. +Found 0 SCCs in module Multiplier_flat. +Found 0 SCCs in module RippleCarryAdder. +Found 0 SCCs. + +7.4. Executing ABC9_OPS pass (helper functions for ABC9). + +7.5. Executing PROC pass (convert processes to netlists). + +7.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +7.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +7.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 0 assignments to connections. + +7.5.4. Executing PROC_INIT pass (extract init attributes). + +7.5.5. Executing PROC_ARST pass (detect async resets in processes). + +7.5.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + +7.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). + +7.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +7.5.9. Executing PROC_DFF pass (convert process syncs to FFs). + +7.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +7.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +7.5.12. Executing OPT_EXPR pass (perform const folding). + +7.6. Executing TECHMAP pass (map to technology primitives). + +7.6.1. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/techmap.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +7.6.2. Continuing TECHMAP pass. +No more expansions possible. + + +7.7. Executing OPT pass (performing simple optimizations). + +7.7.1. Executing OPT_EXPR pass (perform const folding). + +7.7.2. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +7.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Removed 0 multiplexer ports. + +7.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +Performed a total of 0 changes. + +7.7.5. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +7.7.6. Executing OPT_DFF pass (perform DFF optimizations). + +7.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). + +7.7.8. Executing OPT_EXPR pass (perform const folding). + +7.7.9. Finished OPT passes. (There is nothing left to do.) + +7.8. Executing TECHMAP pass (map to technology primitives). + +7.8.1. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/abc9_map.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/abc9_map.v' to AST representation. +Successfully finished Verilog frontend. + +7.8.2. Continuing TECHMAP pass. +No more expansions possible. + + +7.9. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v' to AST representation. +Replacing existing blackbox module `$__ABC9_DELAY' at /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v:2.1-7.10. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Replacing existing blackbox module `$__ABC9_SCC_BREAKER' at /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v:9.1-11.10. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Replacing existing module `$__DFF_N__$abc9_flop' at /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v:14.1-20.10. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Replacing existing module `$__DFF_P__$abc9_flop' at /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v:23.1-29.10. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +7.10. Executing ABC9_OPS pass (helper functions for ABC9). + +7.11. Executing ABC9_OPS pass (helper functions for ABC9). + + +7.12. Executing AIGMAP pass (map logic to AIG). +Module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101: replaced 0 cells with 0 new cells, skipped 5 cells. + not replaced 1 cell types: + 5 FullAdder +Module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110: replaced 0 cells with 0 new cells, skipped 6 cells. + not replaced 1 cell types: + 6 FullAdder +Module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111: replaced 0 cells with 0 new cells, skipped 7 cells. + not replaced 1 cell types: + 7 FullAdder +Module FullAdder: replaced 9 cells with 57 new cells, skipped 6 cells. + replaced 3 cell types: + 2 $_OR_ + 5 $_XOR_ + 2 $_MUX_ + not replaced 2 cell types: + 2 $_NOT_ + 4 $_AND_ +Module Multiplier_2D: replaced 0 cells with 0 new cells, skipped 19 cells. + not replaced 4 cell types: + 16 $_AND_ + 1 $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111 + 1 $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110 + 1 $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101 +Module Multiplier_flat: replaced 0 cells with 0 new cells, skipped 19 cells. + not replaced 4 cell types: + 16 $_AND_ + 1 $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111 + 1 $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110 + 1 $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101 +Module RippleCarryAdder: replaced 0 cells with 0 new cells, skipped 4 cells. + not replaced 1 cell types: + 4 FullAdder + +7.12.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.12.2. Executing XAIGER backend. + +Extracted 0 AND gates and 23 wires from module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101' to a netlist network with 21 inputs and 10 outputs. + +7.12.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.12.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 21/ 10 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 21/ 10 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 21/ 10 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.00 seconds, total: 0.00 seconds + +7.12.5. Executing AIGER frontend. + +Removed 0 unused cells and 31 unused wires. + +7.12.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: input signals: 3 +ABC RESULTS: output signals: 3 +Removing temp directory. + +7.12.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.12.2. Executing XAIGER backend. + +Extracted 0 AND gates and 27 wires from module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110' to a netlist network with 25 inputs and 12 outputs. + +7.12.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.12.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 25/ 12 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 25/ 12 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.01 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 25/ 12 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.00 seconds, total: 0.00 seconds + +7.12.5. Executing AIGER frontend. + +Removed 0 unused cells and 37 unused wires. + +7.12.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: input signals: 3 +ABC RESULTS: output signals: 3 +Removing temp directory. + +7.12.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.12.2. Executing XAIGER backend. + +Extracted 0 AND gates and 31 wires from module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111' to a netlist network with 29 inputs and 14 outputs. + +7.12.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.12.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 29/ 14 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 29/ 14 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.01 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 29/ 14 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.00 seconds, total: 0.00 seconds + +7.12.5. Executing AIGER frontend. + +Removed 0 unused cells and 43 unused wires. + +7.12.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: input signals: 3 +ABC RESULTS: output signals: 3 +Removing temp directory. + +7.12.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.12.2. Executing XAIGER backend. + +Extracted 27 AND gates and 55 wires from module `FullAdder' to a netlist network with 3 inputs and 2 outputs. + +7.12.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.12.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 3/ 2 and = 7 lev = 4 (4.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 3/ 2 and = 7 lev = 4 (4.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 7. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 1.00. Ar = 2.0. Edge = 6. Cut = 33. T = 0.00 sec +ABC: P: Del = 1.00. Ar = 2.0. Edge = 6. Cut = 33. T = 0.00 sec +ABC: P: Del = 1.00. Ar = 2.0. Edge = 6. Cut = 33. T = 0.00 sec +ABC: F: Del = 1.00. Ar = 2.0. Edge = 6. Cut = 33. T = 0.00 sec +ABC: A: Del = 1.00. Ar = 2.0. Edge = 6. Cut = 33. T = 0.00 sec +ABC: A: Del = 1.00. Ar = 2.0. Edge = 6. Cut = 33. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 3/ 2 and = 11 lev = 4 (4.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=3) : lut = 2 edge = 6 lev = 1 (1.00) mem = 0.00 MB +ABC: LUT = 2 : 2=0 0.0 % 3=2 100.0 % Ave = 3.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.00 seconds, total: 0.00 seconds + +7.12.5. Executing AIGER frontend. + +Removed 20 unused cells and 25 unused wires. + +7.12.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: $lut cells: 2 +ABC RESULTS: input signals: 3 +ABC RESULTS: output signals: 2 +Removing temp directory. + +7.12.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.12.2. Executing XAIGER backend. + +Extracted 16 AND gates and 72 wires from module `Multiplier_2D' to a netlist network with 29 inputs and 37 outputs. + +7.12.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.12.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 29/ 37 and = 16 lev = 1 (0.43) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 29/ 37 and = 16 lev = 1 (0.43) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 16. Ch = 0. Total mem = 0.01 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 1.00. Ar = 16.0. Edge = 32. Cut = 16. T = 0.00 sec +ABC: P: Del = 1.00. Ar = 16.0. Edge = 32. Cut = 16. T = 0.00 sec +ABC: P: Del = 1.00. Ar = 16.0. Edge = 32. Cut = 16. T = 0.00 sec +ABC: F: Del = 1.00. Ar = 16.0. Edge = 32. Cut = 16. T = 0.00 sec +ABC: A: Del = 1.00. Ar = 16.0. Edge = 32. Cut = 16. T = 0.00 sec +ABC: A: Del = 1.00. Ar = 16.0. Edge = 32. Cut = 16. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 29/ 37 and = 16 lev = 1 (0.43) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=2) : lut = 16 edge = 32 lev = 1 (0.43) mem = 0.00 MB +ABC: LUT = 16 : 2=16 100.0 % Ave = 2.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.00 seconds, total: 0.00 seconds + +7.12.5. Executing AIGER frontend. + +Removed 0 unused cells and 45 unused wires. + +7.12.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: $lut cells: 16 +ABC RESULTS: input signals: 6 +ABC RESULTS: output signals: 9 +Removing temp directory. + +7.12.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.12.2. Executing XAIGER backend. + +Extracted 16 AND gates and 68 wires from module `Multiplier_flat' to a netlist network with 29 inputs and 37 outputs. + +7.12.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.12.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 29/ 37 and = 16 lev = 1 (0.43) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 29/ 37 and = 16 lev = 1 (0.43) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 16. Ch = 0. Total mem = 0.01 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 1.00. Ar = 16.0. Edge = 32. Cut = 16. T = 0.00 sec +ABC: P: Del = 1.00. Ar = 16.0. Edge = 32. Cut = 16. T = 0.00 sec +ABC: P: Del = 1.00. Ar = 16.0. Edge = 32. Cut = 16. T = 0.00 sec +ABC: F: Del = 1.00. Ar = 16.0. Edge = 32. Cut = 16. T = 0.00 sec +ABC: A: Del = 1.00. Ar = 16.0. Edge = 32. Cut = 16. T = 0.00 sec +ABC: A: Del = 1.00. Ar = 16.0. Edge = 32. Cut = 16. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 29/ 37 and = 16 lev = 1 (0.43) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=2) : lut = 16 edge = 32 lev = 1 (0.43) mem = 0.00 MB +ABC: LUT = 16 : 2=16 100.0 % Ave = 2.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.00 seconds, total: 0.00 seconds + +7.12.5. Executing AIGER frontend. + +Removed 0 unused cells and 45 unused wires. + +7.12.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: $lut cells: 16 +ABC RESULTS: input signals: 6 +ABC RESULTS: output signals: 9 +Removing temp directory. + +7.12.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.12.2. Executing XAIGER backend. + +Extracted 0 AND gates and 19 wires from module `RippleCarryAdder' to a netlist network with 17 inputs and 8 outputs. + +7.12.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.12.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 17/ 8 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 17/ 8 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 17/ 8 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.00 seconds, total: 0.00 seconds + +7.12.5. Executing AIGER frontend. + +Removed 0 unused cells and 25 unused wires. + +7.12.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: input signals: 3 +ABC RESULTS: output signals: 3 +Removing temp directory. + +7.13. Executing TECHMAP pass (map to technology primitives). + +7.13.1. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/abc9_unmap.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/abc9_unmap.v' to AST representation. +Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'. +Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'. +Successfully finished Verilog frontend. + +7.13.2. Continuing TECHMAP pass. +No more expansions possible. + +Removed 1 unused cells and 356 unused wires. +Warning: Selection "abc9_test037" did not match any module. + +8. Executing CHECK pass (checking for obvious problems). +Checking module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101... +Checking module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110... +Checking module $paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111... +Checking module FullAdder... +Checking module Multiplier_2D... +Checking module Multiplier_flat... +Checking module RippleCarryAdder... +Found and reported 0 problems. + +-- Writing to `multiplier_syn0.v' using backend `verilog -noattr -noexpr -siminit' -- + +9. Executing Verilog backend. +Dumping module `$__ABC9_DELAY'. +Dumping module `$__ABC9_SCC_BREAKER'. +Dumping module `$__DFF_N__$abc9_flop'. +Dumping module `$__DFF_P__$abc9_flop'. +Dumping module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000101'. +Dumping module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000110'. +Dumping module `$paramod\RippleCarryAdder\N=s32'00000000000000000000000000000111'. +Dumping module `\FullAdder'. +Dumping module `\Multiplier_2D'. +Dumping module `\Multiplier_flat'. +Dumping module `\RippleCarryAdder'. + +Warnings: 1 unique messages, 1 total +End of script. Logfile hash: 63b98b4632, CPU: user 0.17s system 0.01s, MEM: 21.48 MB peak +Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) +Time spent: 62% 7x abc9_exe (0 sec), 9% 16x opt_expr (0 sec), ... ++ compile_and_run multiplier_tb_syn0 multiplier_out_syn0 multiplier_tb.v multiplier_syn0.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simlib.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simcells.v ++ exe=multiplier_tb_syn0 ++ output=multiplier_out_syn0 ++ shift 2 ++ '[' v == sv ']' ++ language_gen=-g2005 ++ false ++ false ++ iverilog -g2005 '-Doutfile="multiplier_out_syn0"' -s testbench -o multiplier_tb_syn0 multiplier_tb.v multiplier_syn0.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simlib.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simcells.v ++ vvp -n multiplier_tb_syn0 diff --git a/tests/simple_abc9/operators.err b/tests/simple_abc9/operators.err new file mode 100644 index 00000000000..8b65191bcff --- /dev/null +++ b/tests/simple_abc9/operators.err @@ -0,0 +1,939 @@ ++ body ++ cd operators.out +++ basename operators.v ++ fn=operators.v +++ basename operators ++ bn=operators ++ refext=v ++ rm -f operators_ref.fir ++ [[ v == \v ]] ++ egrep -v '^\s*`timescale' ../operators.v +egrep: warning: egrep is obsolescent; using grep -E ++ '[' '!' -f ../operators_tb.v ']' ++ /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../yosys -f 'verilog -noblackbox -specify -D_AUTOTB' -b 'test_autotb -n 300' -o operators_tb.v operators_ref.v + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2024 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) + +-- Parsing `operators_ref.v' using frontend `verilog -noblackbox -specify -D_AUTOTB' -- + +1. Executing Verilog-2005 frontend: operators_ref.v +Parsing Verilog input from `operators_ref.v' to AST representation. +Generating RTLIL representation for module `\optest'. +Successfully finished Verilog frontend. + +-- Writing to `operators_tb.v' using backend `test_autotb -n 300' -- + +2. Executing TEST_AUTOTB backend (auto-generate pseudo-random test benches). +Generating test bench for module `\optest'. + +End of script. Logfile hash: 2abd7d2f59, CPU: user 0.01s system 0.00s, MEM: 15.13 MB peak +Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) +Time spent: 97% 1x read_verilog (0 sec), 2% 1x test_autotb (0 sec) ++ false ++ compile_and_run operators_tb_ref operators_out_ref operators_tb.v operators_ref.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simlib.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simcells.v ++ exe=operators_tb_ref ++ output=operators_out_ref ++ shift 2 ++ '[' v == sv ']' ++ language_gen=-g2005 ++ false ++ false ++ iverilog -g2005 '-Doutfile="operators_out_ref"' -s testbench -o operators_tb_ref operators_tb.v operators_ref.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simlib.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simcells.v ++ vvp -n operators_tb_ref +operators_tb.v:136: $finish called at 120600 (1s) ++ false ++ test_count=0 ++ '[' 'verilog -noblackbox -specify' = verific -o 'verilog -noblackbox -specify' = verific_gates ']' ++ '[' -n '' ']' ++ '[' -n ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' ']' ++ test_passes -f 'verilog -noblackbox -specify ' -p ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' operators_ref.v ++ /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../yosys -b 'verilog -noattr -noexpr -siminit' -o operators_syn0.v -f 'verilog -noblackbox -specify ' -p ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' operators_ref.v + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2024 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) + +-- Parsing `operators_ref.v' using frontend `verilog -noblackbox -specify ' -- + +1. Executing Verilog-2005 frontend: operators_ref.v +Parsing Verilog input from `operators_ref.v' to AST representation. +Generating RTLIL representation for module `\optest'. +Successfully finished Verilog frontend. + +-- Running command ` read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' -- + +2. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v' to AST representation. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +3. Executing HIERARCHY pass (managing design hierarchy). + +4. Executing SYNTH pass. + +4.1. Executing PROC pass (convert processes to netlists). + +4.1.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +4.1.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +4.1.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 0 assignments to connections. + +4.1.4. Executing PROC_INIT pass (extract init attributes). + +4.1.5. Executing PROC_ARST pass (detect async resets in processes). + +4.1.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +4.1.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\optest.$proc$operators_ref.v:11$1'. + 1/1: $0\y[7:0] + +4.1.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +4.1.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\optest.\y' using process `\optest.$proc$operators_ref.v:11$1'. + created $dff cell `$procdff$210' with positive edge clock. + +4.1.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +4.1.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 1 empty switch in `\optest.$proc$operators_ref.v:11$1'. +Removing empty process `optest.$proc$operators_ref.v:11$1'. +Cleaned up 1 empty switch. + +4.1.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module optest. + + +4.2. Executing OPT_EXPR pass (perform const folding). +Optimizing module optest. + +4.3. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \optest.. +Removed 0 unused cells and 9 unused wires. + + +4.4. Executing CHECK pass (checking for obvious problems). +Checking module optest... +Found and reported 0 problems. + +4.5. Executing OPT pass (performing simple optimizations). + +4.5.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module optest. + +4.5.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\optest'. + +Removed a total of 13 cells. + +4.5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \optest.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Replacing known input bits on port B of cell $ternary$operators_ref.v:115$122: \u1 -> { \u1 [3:1] 1'1 } + Replacing known input bits on port B of cell $ternary$operators_ref.v:114$121: \u1 -> { \u1 [3:1] 1'1 } + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \optest. +Performed a total of 0 changes. + +4.5.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\optest'. +Removed a total of 0 cells. + +4.5.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.5.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \optest.. +Removed 0 unused cells and 13 unused wires. + + +4.5.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module optest. + +4.5.9. Rerunning OPT passes. (Maybe there is more to do..) + +4.5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \optest.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \optest. +Performed a total of 0 changes. + +4.5.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\optest'. +Removed a total of 0 cells. + +4.5.13. Executing OPT_DFF pass (perform DFF optimizations). + +4.5.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \optest.. + +4.5.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module optest. + +4.5.16. Finished OPT passes. (There is nothing left to do.) + +4.6. Executing FSM pass (extract and optimize FSM). + +4.6.1. Executing FSM_DETECT pass (finding FSMs in design). + +4.6.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +4.6.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.6.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \optest.. + +4.6.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.6.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +4.6.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +4.6.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +4.7. Executing OPT pass (performing simple optimizations). + +4.7.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module optest. + +4.7.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\optest'. +Removed a total of 0 cells. + +4.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \optest.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \optest. +Performed a total of 0 changes. + +4.7.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\optest'. +Removed a total of 0 cells. + +4.7.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \optest.. + +4.7.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module optest. + +4.7.9. Finished OPT passes. (There is nothing left to do.) + +4.8. Executing WREDUCE pass (reducing word size of cells). +Removed top 2 bits (of 4) from port A of cell optest.$pow$operators_ref.v:90$63 ($pow). +Removed top 1 bits (of 4) from port A of cell optest.$pow$operators_ref.v:92$65 ($pow). +Removed top 3 bits (of 8) from port Y of cell optest.$add$operators_ref.v:64$42 ($add). +Removed top 3 bits (of 8) from port Y of cell optest.$add$operators_ref.v:65$43 ($add). +Removed top 3 bits (of 8) from port Y of cell optest.$add$operators_ref.v:66$44 ($add). +Removed top 3 bits (of 8) from port Y of cell optest.$add$operators_ref.v:67$45 ($add). +Removed top 3 bits (of 8) from port Y of cell optest.$sub$operators_ref.v:69$46 ($sub). +Removed top 3 bits (of 8) from port Y of cell optest.$sub$operators_ref.v:70$47 ($sub). +Removed top 3 bits (of 8) from port Y of cell optest.$sub$operators_ref.v:71$48 ($sub). +Removed top 3 bits (of 8) from port Y of cell optest.$sub$operators_ref.v:72$49 ($sub). +Removed top 3 bits (of 4) from port A of cell optest.$shl$operators_ref.v:89$62 ($shl). +Removed top 2 bits (of 4) from port A of cell optest.$shl$operators_ref.v:91$64 ($shl). +Removed top 4 bits (of 8) from port A of cell optest.$neg$operators_ref.v:95$69 ($neg). +Removed top 4 bits (of 8) from port A of cell optest.$not$operators_ref.v:96$71 ($not). +Removed top 4 bits (of 8) from port A of cell optest.$neg$operators_ref.v:100$76 ($neg). +Removed top 4 bits (of 8) from port A of cell optest.$not$operators_ref.v:101$78 ($not). +Removed top 1 bits (of 7) from port B of cell optest.$procmux$146_CMP0 ($eq). +Removed top 1 bits (of 7) from port B of cell optest.$procmux$147_CMP0 ($eq). +Removed top 1 bits (of 7) from port B of cell optest.$procmux$148_CMP0 ($eq). +Removed top 1 bits (of 7) from port B of cell optest.$procmux$149_CMP0 ($eq). +Removed top 1 bits (of 7) from port B of cell optest.$procmux$150_CMP0 ($eq). +Removed top 1 bits (of 7) from port B of cell optest.$procmux$151_CMP0 ($eq). +Removed top 1 bits (of 7) from port B of cell optest.$procmux$152_CMP0 ($eq). +Removed top 1 bits (of 7) from port B of cell optest.$procmux$153_CMP0 ($eq). +Removed top 1 bits (of 7) from port B of cell optest.$procmux$154_CMP0 ($eq). +Removed top 1 bits (of 7) from port B of cell optest.$procmux$155_CMP0 ($eq). +Removed top 1 bits (of 7) from port B of cell optest.$procmux$156_CMP0 ($eq). +Removed top 1 bits (of 7) from port B of cell optest.$procmux$157_CMP0 ($eq). +Removed top 1 bits (of 7) from port B of cell optest.$procmux$158_CMP0 ($eq). +Removed top 1 bits (of 7) from port B of cell optest.$procmux$159_CMP0 ($eq). +Removed top 1 bits (of 7) from port B of cell optest.$procmux$160_CMP0 ($eq). +Removed top 1 bits (of 7) from port B of cell optest.$procmux$161_CMP0 ($eq). +Removed top 1 bits (of 7) from port B of cell optest.$procmux$162_CMP0 ($eq). +Removed top 1 bits (of 7) from port B of cell optest.$procmux$163_CMP0 ($eq). +Removed top 1 bits (of 7) from port B of cell optest.$procmux$164_CMP0 ($eq). +Removed top 1 bits (of 7) from port B of cell optest.$procmux$165_CMP0 ($eq). +Removed top 1 bits (of 7) from port B of cell optest.$procmux$166_CMP0 ($eq). +Removed top 1 bits (of 7) from port B of cell optest.$procmux$167_CMP0 ($eq). +Removed top 1 bits (of 7) from port B of cell optest.$procmux$168_CMP0 ($eq). +Removed top 1 bits (of 7) from port B of cell optest.$procmux$169_CMP0 ($eq). +Removed top 1 bits (of 7) from port B of cell optest.$procmux$170_CMP0 ($eq). +Removed top 1 bits (of 7) from port B of cell optest.$procmux$171_CMP0 ($eq). +Removed top 1 bits (of 7) from port B of cell optest.$procmux$172_CMP0 ($eq). +Removed top 1 bits (of 7) from port B of cell optest.$procmux$173_CMP0 ($eq). +Removed top 1 bits (of 7) from port B of cell optest.$procmux$174_CMP0 ($eq). +Removed top 1 bits (of 7) from port B of cell optest.$procmux$175_CMP0 ($eq). +Removed top 1 bits (of 7) from port B of cell optest.$procmux$176_CMP0 ($eq). +Removed top 1 bits (of 7) from port B of cell optest.$procmux$177_CMP0 ($eq). +Removed top 2 bits (of 7) from port B of cell optest.$procmux$178_CMP0 ($eq). +Removed top 2 bits (of 7) from port B of cell optest.$procmux$179_CMP0 ($eq). +Removed top 2 bits (of 7) from port B of cell optest.$procmux$180_CMP0 ($eq). +Removed top 2 bits (of 7) from port B of cell optest.$procmux$181_CMP0 ($eq). +Removed top 2 bits (of 7) from port B of cell optest.$procmux$182_CMP0 ($eq). +Removed top 2 bits (of 7) from port B of cell optest.$procmux$183_CMP0 ($eq). +Removed top 2 bits (of 7) from port B of cell optest.$procmux$184_CMP0 ($eq). +Removed top 2 bits (of 7) from port B of cell optest.$procmux$185_CMP0 ($eq). +Removed top 2 bits (of 7) from port B of cell optest.$procmux$186_CMP0 ($eq). +Removed top 2 bits (of 7) from port B of cell optest.$procmux$187_CMP0 ($eq). +Removed top 2 bits (of 7) from port B of cell optest.$procmux$188_CMP0 ($eq). +Removed top 2 bits (of 7) from port B of cell optest.$procmux$189_CMP0 ($eq). +Removed top 2 bits (of 7) from port B of cell optest.$procmux$190_CMP0 ($eq). +Removed top 2 bits (of 7) from port B of cell optest.$procmux$191_CMP0 ($eq). +Removed top 2 bits (of 7) from port B of cell optest.$procmux$192_CMP0 ($eq). +Removed top 2 bits (of 7) from port B of cell optest.$procmux$193_CMP0 ($eq). +Removed top 3 bits (of 7) from port B of cell optest.$procmux$194_CMP0 ($eq). +Removed top 3 bits (of 7) from port B of cell optest.$procmux$195_CMP0 ($eq). +Removed top 3 bits (of 7) from port B of cell optest.$procmux$196_CMP0 ($eq). +Removed top 3 bits (of 7) from port B of cell optest.$procmux$197_CMP0 ($eq). +Removed top 3 bits (of 7) from port B of cell optest.$procmux$198_CMP0 ($eq). +Removed top 3 bits (of 7) from port B of cell optest.$procmux$199_CMP0 ($eq). +Removed top 3 bits (of 7) from port B of cell optest.$procmux$200_CMP0 ($eq). +Removed top 3 bits (of 7) from port B of cell optest.$procmux$201_CMP0 ($eq). +Removed top 4 bits (of 7) from port B of cell optest.$procmux$202_CMP0 ($eq). +Removed top 4 bits (of 7) from port B of cell optest.$procmux$203_CMP0 ($eq). +Removed top 4 bits (of 7) from port B of cell optest.$procmux$204_CMP0 ($eq). +Removed top 4 bits (of 7) from port B of cell optest.$procmux$205_CMP0 ($eq). +Removed top 5 bits (of 7) from port B of cell optest.$procmux$206_CMP0 ($eq). +Removed top 5 bits (of 7) from port B of cell optest.$procmux$207_CMP0 ($eq). +Removed top 6 bits (of 7) from port B of cell optest.$procmux$208_CMP0 ($eq). +Removed top 3 bits (of 8) from wire optest.$add$operators_ref.v:64$42_Y. +Removed top 3 bits (of 8) from wire optest.$add$operators_ref.v:65$43_Y. +Removed top 7 bits (of 8) from wire optest.$eq$operators_ref.v:44$26_Y. +Removed top 7 bits (of 8) from wire optest.$eq$operators_ref.v:46$28_Y. +Removed top 7 bits (of 8) from wire optest.$ge$operators_ref.v:54$34_Y. +Removed top 7 bits (of 8) from wire optest.$ge$operators_ref.v:56$36_Y. +Removed top 7 bits (of 8) from wire optest.$gt$operators_ref.v:59$38_Y. +Removed top 7 bits (of 8) from wire optest.$gt$operators_ref.v:61$40_Y. +Removed top 7 bits (of 8) from wire optest.$le$operators_ref.v:39$22_Y. +Removed top 7 bits (of 8) from wire optest.$le$operators_ref.v:41$24_Y. +Removed top 7 bits (of 8) from wire optest.$logic_not$operators_ref.v:102$79_Y. +Removed top 7 bits (of 8) from wire optest.$logic_not$operators_ref.v:97$72_Y. +Removed top 7 bits (of 8) from wire optest.$lt$operators_ref.v:34$18_Y. +Removed top 7 bits (of 8) from wire optest.$lt$operators_ref.v:36$20_Y. +Removed top 7 bits (of 8) from wire optest.$ne$operators_ref.v:49$30_Y. +Removed top 7 bits (of 8) from wire optest.$ne$operators_ref.v:51$32_Y. + +4.9. Executing PEEPOPT pass (run peephole optimizers). + +4.10. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \optest.. +Removed 0 unused cells and 16 unused wires. + + +4.11. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module optest: + creating $macc model for $add$operators_ref.v:64$42 ($add). + creating $macc model for $add$operators_ref.v:65$43 ($add). + creating $macc model for $add$operators_ref.v:66$44 ($add). + creating $macc model for $add$operators_ref.v:67$45 ($add). + creating $macc model for $mul$operators_ref.v:74$50 ($mul). + creating $macc model for $mul$operators_ref.v:75$51 ($mul). + creating $macc model for $mul$operators_ref.v:76$52 ($mul). + creating $macc model for $mul$operators_ref.v:77$53 ($mul). + creating $macc model for $neg$operators_ref.v:100$76 ($neg). + creating $macc model for $neg$operators_ref.v:95$69 ($neg). + creating $macc model for $sub$operators_ref.v:69$46 ($sub). + creating $macc model for $sub$operators_ref.v:70$47 ($sub). + creating $macc model for $sub$operators_ref.v:71$48 ($sub). + creating $macc model for $sub$operators_ref.v:72$49 ($sub). + creating $alu model for $macc $sub$operators_ref.v:72$49. + creating $alu model for $macc $sub$operators_ref.v:71$48. + creating $alu model for $macc $sub$operators_ref.v:70$47. + creating $alu model for $macc $sub$operators_ref.v:69$46. + creating $alu model for $macc $neg$operators_ref.v:95$69. + creating $alu model for $macc $add$operators_ref.v:67$45. + creating $alu model for $macc $add$operators_ref.v:66$44. + creating $alu model for $macc $add$operators_ref.v:65$43. + creating $alu model for $macc $add$operators_ref.v:64$42. + creating $macc cell for $mul$operators_ref.v:74$50: $auto$alumacc.cc:365:replace_macc$227 + creating $macc cell for $neg$operators_ref.v:100$76: $auto$alumacc.cc:365:replace_macc$228 + creating $macc cell for $mul$operators_ref.v:77$53: $auto$alumacc.cc:365:replace_macc$229 + creating $macc cell for $mul$operators_ref.v:76$52: $auto$alumacc.cc:365:replace_macc$230 + creating $macc cell for $mul$operators_ref.v:75$51: $auto$alumacc.cc:365:replace_macc$231 + creating $alu model for $ge$operators_ref.v:54$34 ($ge): new $alu + creating $alu model for $ge$operators_ref.v:55$35 ($ge): new $alu + creating $alu model for $ge$operators_ref.v:56$36 ($ge): merged with $sub$operators_ref.v:71$48. + creating $alu model for $ge$operators_ref.v:57$37 ($ge): merged with $sub$operators_ref.v:72$49. + creating $alu model for $gt$operators_ref.v:59$38 ($gt): merged with $ge$operators_ref.v:54$34. + creating $alu model for $gt$operators_ref.v:60$39 ($gt): merged with $ge$operators_ref.v:55$35. + creating $alu model for $gt$operators_ref.v:61$40 ($gt): merged with $sub$operators_ref.v:71$48. + creating $alu model for $gt$operators_ref.v:62$41 ($gt): merged with $sub$operators_ref.v:72$49. + creating $alu model for $le$operators_ref.v:39$22 ($le): merged with $ge$operators_ref.v:54$34. + creating $alu model for $le$operators_ref.v:40$23 ($le): merged with $ge$operators_ref.v:55$35. + creating $alu model for $le$operators_ref.v:41$24 ($le): merged with $sub$operators_ref.v:71$48. + creating $alu model for $le$operators_ref.v:42$25 ($le): merged with $sub$operators_ref.v:72$49. + creating $alu model for $lt$operators_ref.v:34$18 ($lt): merged with $ge$operators_ref.v:54$34. + creating $alu model for $lt$operators_ref.v:35$19 ($lt): merged with $ge$operators_ref.v:55$35. + creating $alu model for $lt$operators_ref.v:36$20 ($lt): merged with $sub$operators_ref.v:71$48. + creating $alu model for $lt$operators_ref.v:37$21 ($lt): merged with $sub$operators_ref.v:72$49. + creating $alu model for $eq$operators_ref.v:44$26 ($eq): merged with $ge$operators_ref.v:54$34. + creating $alu model for $eq$operators_ref.v:45$27 ($eq): merged with $ge$operators_ref.v:55$35. + creating $alu model for $eq$operators_ref.v:46$28 ($eq): merged with $sub$operators_ref.v:71$48. + creating $alu model for $eq$operators_ref.v:47$29 ($eq): merged with $sub$operators_ref.v:72$49. + creating $alu model for $ne$operators_ref.v:49$30 ($ne): merged with $ge$operators_ref.v:54$34. + creating $alu model for $ne$operators_ref.v:50$31 ($ne): merged with $ge$operators_ref.v:55$35. + creating $alu model for $ne$operators_ref.v:51$32 ($ne): merged with $sub$operators_ref.v:71$48. + creating $alu model for $ne$operators_ref.v:52$33 ($ne): merged with $sub$operators_ref.v:72$49. + creating $alu cell for $ge$operators_ref.v:54$34, $gt$operators_ref.v:59$38, $le$operators_ref.v:39$22, $lt$operators_ref.v:34$18, $eq$operators_ref.v:44$26, $ne$operators_ref.v:49$30: $auto$alumacc.cc:485:replace_alu$234 + creating $alu cell for $add$operators_ref.v:64$42: $auto$alumacc.cc:485:replace_alu$251 + creating $alu cell for $ge$operators_ref.v:55$35, $gt$operators_ref.v:60$39, $le$operators_ref.v:40$23, $lt$operators_ref.v:35$19, $eq$operators_ref.v:45$27, $ne$operators_ref.v:50$31: $auto$alumacc.cc:485:replace_alu$254 + creating $alu cell for $add$operators_ref.v:65$43: $auto$alumacc.cc:485:replace_alu$271 + creating $alu cell for $neg$operators_ref.v:95$69: $auto$alumacc.cc:485:replace_alu$274 + creating $alu cell for $sub$operators_ref.v:69$46: $auto$alumacc.cc:485:replace_alu$277 + creating $alu cell for $sub$operators_ref.v:70$47: $auto$alumacc.cc:485:replace_alu$280 + creating $alu cell for $add$operators_ref.v:66$44: $auto$alumacc.cc:485:replace_alu$283 + creating $alu cell for $sub$operators_ref.v:71$48, $ge$operators_ref.v:56$36, $gt$operators_ref.v:61$40, $le$operators_ref.v:41$24, $lt$operators_ref.v:36$20, $eq$operators_ref.v:46$28, $ne$operators_ref.v:51$32: $auto$alumacc.cc:485:replace_alu$286 + creating $alu cell for $add$operators_ref.v:67$45: $auto$alumacc.cc:485:replace_alu$303 + creating $alu cell for $sub$operators_ref.v:72$49, $ge$operators_ref.v:57$37, $gt$operators_ref.v:62$41, $le$operators_ref.v:42$25, $lt$operators_ref.v:37$21, $eq$operators_ref.v:47$29, $ne$operators_ref.v:52$33: $auto$alumacc.cc:485:replace_alu$306 + created 11 $alu and 5 $macc cells. + +4.12. Executing SHARE pass (SAT-based resource sharing). +Found 26 cells in module optest that may be considered for resource sharing. + Analyzing resource sharing options for $sshr$operators_ref.v:32$17 ($sshr): + Found 1 activation_patterns using ctrl signal $procmux$194_CMP. + Found 3 candidates: $sshr$operators_ref.v:31$16 $sshr$operators_ref.v:30$15 $sshr$operators_ref.v:29$14 + Analyzing resource sharing with $sshr$operators_ref.v:31$16 ($sshr): + Found 1 activation_patterns using ctrl signal $procmux$195_CMP. + Activation pattern for cell $sshr$operators_ref.v:32$17: $procmux$194_CMP = 1'1 + Activation pattern for cell $sshr$operators_ref.v:31$16: $procmux$195_CMP = 1'1 + Size of SAT problem: 0 cells, 40 variables, 103 clauses + According to the SAT solver this pair of cells can be shared. + Activation signal for $sshr$operators_ref.v:32$17: $auto$share.cc:977:make_cell_activation_logic$325 + New cell: $auto$share.cc:667:make_supercell$332 ($sshr) + Analyzing resource sharing options for $auto$share.cc:667:make_supercell$332 ($sshr): + Found 2 activation_patterns using ctrl signal { $procmux$195_CMP $procmux$194_CMP }. + Found 2 candidates: $sshr$operators_ref.v:30$15 $sshr$operators_ref.v:29$14 + Analyzing resource sharing with $sshr$operators_ref.v:30$15 ($sshr): + Found 1 activation_patterns using ctrl signal $procmux$196_CMP. + Activation pattern for cell $auto$share.cc:667:make_supercell$332: $procmux$194_CMP = 1'1 + Activation pattern for cell $auto$share.cc:667:make_supercell$332: $procmux$195_CMP = 1'1 + Activation pattern for cell $sshr$operators_ref.v:30$15: $procmux$196_CMP = 1'1 + Size of SAT problem: 0 cells, 52 variables, 142 clauses + According to the SAT solver this pair of cells can be shared. + Activation signal for $sshr$operators_ref.v:30$15: $auto$share.cc:977:make_cell_activation_logic$335 + New cell: $auto$share.cc:667:make_supercell$342 ($sshr) + Analyzing resource sharing options for $auto$share.cc:667:make_supercell$342 ($sshr): + Found 3 activation_patterns using ctrl signal { $procmux$196_CMP $procmux$195_CMP $procmux$194_CMP }. + Found 1 candidates: $sshr$operators_ref.v:29$14 + Analyzing resource sharing with $sshr$operators_ref.v:29$14 ($sshr): + Found 1 activation_patterns using ctrl signal $procmux$197_CMP. + Activation pattern for cell $auto$share.cc:667:make_supercell$342: $procmux$194_CMP = 1'1 + Activation pattern for cell $auto$share.cc:667:make_supercell$342: $procmux$195_CMP = 1'1 + Activation pattern for cell $auto$share.cc:667:make_supercell$342: $procmux$196_CMP = 1'1 + Activation pattern for cell $sshr$operators_ref.v:29$14: $procmux$197_CMP = 1'1 + Size of SAT problem: 0 cells, 60 variables, 171 clauses + According to the SAT solver this pair of cells can be shared. + Activation signal for $sshr$operators_ref.v:29$14: $auto$share.cc:977:make_cell_activation_logic$345 + New cell: $auto$share.cc:667:make_supercell$352 ($sshr) + Analyzing resource sharing options for $auto$share.cc:667:make_supercell$352 ($sshr): + Found 4 activation_patterns using ctrl signal { $procmux$197_CMP $procmux$196_CMP $procmux$195_CMP $procmux$194_CMP }. + No candidates found. + Analyzing resource sharing options for $sshl$operators_ref.v:27$13 ($sshl): + Found 1 activation_patterns using ctrl signal $procmux$198_CMP. + Found 3 candidates: $sshl$operators_ref.v:26$12 $sshl$operators_ref.v:25$11 $sshl$operators_ref.v:24$10 + Analyzing resource sharing with $sshl$operators_ref.v:26$12 ($sshl): + Found 1 activation_patterns using ctrl signal $procmux$199_CMP. + Activation pattern for cell $sshl$operators_ref.v:27$13: $procmux$198_CMP = 1'1 + Activation pattern for cell $sshl$operators_ref.v:26$12: $procmux$199_CMP = 1'1 + Size of SAT problem: 0 cells, 40 variables, 103 clauses + According to the SAT solver this pair of cells can be shared. + Activation signal for $sshl$operators_ref.v:27$13: $auto$share.cc:977:make_cell_activation_logic$355 + New cell: $auto$share.cc:667:make_supercell$362 ($sshl) + Analyzing resource sharing options for $auto$share.cc:667:make_supercell$362 ($sshl): + Found 2 activation_patterns using ctrl signal { $procmux$199_CMP $procmux$198_CMP }. + Found 2 candidates: $sshl$operators_ref.v:25$11 $sshl$operators_ref.v:24$10 + Analyzing resource sharing with $sshl$operators_ref.v:25$11 ($sshl): + Found 1 activation_patterns using ctrl signal $procmux$200_CMP. + Activation pattern for cell $auto$share.cc:667:make_supercell$362: $procmux$198_CMP = 1'1 + Activation pattern for cell $auto$share.cc:667:make_supercell$362: $procmux$199_CMP = 1'1 + Activation pattern for cell $sshl$operators_ref.v:25$11: $procmux$200_CMP = 1'1 + Size of SAT problem: 0 cells, 52 variables, 142 clauses + According to the SAT solver this pair of cells can be shared. + Activation signal for $sshl$operators_ref.v:25$11: $auto$share.cc:977:make_cell_activation_logic$365 + New cell: $auto$share.cc:667:make_supercell$372 ($sshl) + Analyzing resource sharing options for $auto$share.cc:667:make_supercell$372 ($sshl): + Found 3 activation_patterns using ctrl signal { $procmux$200_CMP $procmux$199_CMP $procmux$198_CMP }. + Found 1 candidates: $sshl$operators_ref.v:24$10 + Analyzing resource sharing with $sshl$operators_ref.v:24$10 ($sshl): + Found 1 activation_patterns using ctrl signal $procmux$201_CMP. + Activation pattern for cell $auto$share.cc:667:make_supercell$372: $procmux$198_CMP = 1'1 + Activation pattern for cell $auto$share.cc:667:make_supercell$372: $procmux$199_CMP = 1'1 + Activation pattern for cell $auto$share.cc:667:make_supercell$372: $procmux$200_CMP = 1'1 + Activation pattern for cell $sshl$operators_ref.v:24$10: $procmux$201_CMP = 1'1 + Size of SAT problem: 0 cells, 60 variables, 171 clauses + According to the SAT solver this pair of cells can be shared. + Activation signal for $sshl$operators_ref.v:24$10: $auto$share.cc:977:make_cell_activation_logic$375 + New cell: $auto$share.cc:667:make_supercell$382 ($sshl) + Analyzing resource sharing options for $auto$share.cc:667:make_supercell$382 ($sshl): + Found 4 activation_patterns using ctrl signal { $procmux$201_CMP $procmux$200_CMP $procmux$199_CMP $procmux$198_CMP }. + No candidates found. + Analyzing resource sharing options for $shr$operators_ref.v:22$9 ($shr): + Found 1 activation_patterns using ctrl signal $procmux$202_CMP. + Found 3 candidates: $shr$operators_ref.v:21$8 $shr$operators_ref.v:20$7 $shr$operators_ref.v:19$6 + Analyzing resource sharing with $shr$operators_ref.v:21$8 ($shr): + Found 1 activation_patterns using ctrl signal $procmux$203_CMP. + Activation pattern for cell $shr$operators_ref.v:22$9: $procmux$202_CMP = 1'1 + Activation pattern for cell $shr$operators_ref.v:21$8: $procmux$203_CMP = 1'1 + Size of SAT problem: 0 cells, 40 variables, 103 clauses + According to the SAT solver this pair of cells can be shared. + Activation signal for $shr$operators_ref.v:22$9: $auto$share.cc:977:make_cell_activation_logic$385 + New cell: $auto$share.cc:667:make_supercell$392 ($shr) + Analyzing resource sharing options for $auto$share.cc:667:make_supercell$392 ($shr): + Found 2 activation_patterns using ctrl signal { $procmux$203_CMP $procmux$202_CMP }. + Found 2 candidates: $shr$operators_ref.v:20$7 $shr$operators_ref.v:19$6 + Analyzing resource sharing with $shr$operators_ref.v:20$7 ($shr): + Found 1 activation_patterns using ctrl signal $procmux$204_CMP. + Activation pattern for cell $auto$share.cc:667:make_supercell$392: $procmux$202_CMP = 1'1 + Activation pattern for cell $auto$share.cc:667:make_supercell$392: $procmux$203_CMP = 1'1 + Activation pattern for cell $shr$operators_ref.v:20$7: $procmux$204_CMP = 1'1 + Size of SAT problem: 0 cells, 52 variables, 142 clauses + According to the SAT solver this pair of cells can be shared. + Activation signal for $shr$operators_ref.v:20$7: $auto$share.cc:977:make_cell_activation_logic$395 + New cell: $auto$share.cc:667:make_supercell$402 ($shr) + Analyzing resource sharing options for $auto$share.cc:667:make_supercell$402 ($shr): + Found 3 activation_patterns using ctrl signal { $procmux$204_CMP $procmux$203_CMP $procmux$202_CMP }. + Found 1 candidates: $shr$operators_ref.v:19$6 + Analyzing resource sharing with $shr$operators_ref.v:19$6 ($shr): + Found 1 activation_patterns using ctrl signal $procmux$205_CMP. + Activation pattern for cell $auto$share.cc:667:make_supercell$402: $procmux$202_CMP = 1'1 + Activation pattern for cell $auto$share.cc:667:make_supercell$402: $procmux$203_CMP = 1'1 + Activation pattern for cell $auto$share.cc:667:make_supercell$402: $procmux$204_CMP = 1'1 + Activation pattern for cell $shr$operators_ref.v:19$6: $procmux$205_CMP = 1'1 + Size of SAT problem: 0 cells, 60 variables, 171 clauses + According to the SAT solver this pair of cells can be shared. + Activation signal for $shr$operators_ref.v:19$6: $auto$share.cc:977:make_cell_activation_logic$405 + New cell: $auto$share.cc:667:make_supercell$412 ($shr) + Analyzing resource sharing options for $auto$share.cc:667:make_supercell$412 ($shr): + Found 4 activation_patterns using ctrl signal { $procmux$205_CMP $procmux$204_CMP $procmux$203_CMP $procmux$202_CMP }. + No candidates found. + Analyzing resource sharing options for $shl$operators_ref.v:91$64 ($shl): + Found 1 activation_patterns using ctrl signal $procmux$147_CMP. + Found 5 candidates: $shl$operators_ref.v:89$62 $shl$operators_ref.v:17$5 $shl$operators_ref.v:16$4 $shl$operators_ref.v:15$3 $shl$operators_ref.v:14$2 + Analyzing resource sharing with $shl$operators_ref.v:89$62 ($shl): + Found 1 activation_patterns using ctrl signal $procmux$149_CMP. + Activation pattern for cell $shl$operators_ref.v:91$64: $procmux$147_CMP = 1'1 + Activation pattern for cell $shl$operators_ref.v:89$62: $procmux$149_CMP = 1'1 + Size of SAT problem: 0 cells, 40 variables, 103 clauses + According to the SAT solver this pair of cells can be shared. + Activation signal for $shl$operators_ref.v:91$64: $auto$share.cc:977:make_cell_activation_logic$415 + New cell: $auto$share.cc:667:make_supercell$422 ($shl) + Analyzing resource sharing options for $auto$share.cc:667:make_supercell$422 ($shl): + Found 2 activation_patterns using ctrl signal { $procmux$149_CMP $procmux$147_CMP }. + Found 4 candidates: $shl$operators_ref.v:17$5 $shl$operators_ref.v:16$4 $shl$operators_ref.v:15$3 $shl$operators_ref.v:14$2 + Analyzing resource sharing with $shl$operators_ref.v:17$5 ($shl): + Found 1 activation_patterns using ctrl signal $procmux$206_CMP. + Activation pattern for cell $auto$share.cc:667:make_supercell$422: $procmux$147_CMP = 1'1 + Activation pattern for cell $auto$share.cc:667:make_supercell$422: $procmux$149_CMP = 1'1 + Activation pattern for cell $shl$operators_ref.v:17$5: $procmux$206_CMP = 1'1 + Size of SAT problem: 0 cells, 60 variables, 166 clauses + According to the SAT solver this pair of cells can be shared. + Activation signal for $shl$operators_ref.v:17$5: $auto$share.cc:977:make_cell_activation_logic$425 + New cell: $auto$share.cc:667:make_supercell$432 ($shl) + Analyzing resource sharing options for $auto$share.cc:667:make_supercell$432 ($shl): + Found 3 activation_patterns using ctrl signal { $procmux$206_CMP $procmux$149_CMP $procmux$147_CMP }. + Found 3 candidates: $shl$operators_ref.v:16$4 $shl$operators_ref.v:15$3 $shl$operators_ref.v:14$2 + Analyzing resource sharing with $shl$operators_ref.v:16$4 ($shl): + Found 1 activation_patterns using ctrl signal $procmux$207_CMP. + Activation pattern for cell $auto$share.cc:667:make_supercell$432: $procmux$147_CMP = 1'1 + Activation pattern for cell $auto$share.cc:667:make_supercell$432: $procmux$149_CMP = 1'1 + Activation pattern for cell $auto$share.cc:667:make_supercell$432: $procmux$206_CMP = 1'1 + Activation pattern for cell $shl$operators_ref.v:16$4: $procmux$207_CMP = 1'1 + Size of SAT problem: 0 cells, 68 variables, 195 clauses + According to the SAT solver this pair of cells can be shared. + Activation signal for $shl$operators_ref.v:16$4: $auto$share.cc:977:make_cell_activation_logic$435 + New cell: $auto$share.cc:667:make_supercell$442 ($shl) + Analyzing resource sharing options for $auto$share.cc:667:make_supercell$442 ($shl): + Found 4 activation_patterns using ctrl signal { $procmux$207_CMP $procmux$206_CMP $procmux$149_CMP $procmux$147_CMP }. + Found 2 candidates: $shl$operators_ref.v:15$3 $shl$operators_ref.v:14$2 + Analyzing resource sharing with $shl$operators_ref.v:15$3 ($shl): + Found 1 activation_patterns using ctrl signal $procmux$208_CMP. + Activation pattern for cell $auto$share.cc:667:make_supercell$442: $procmux$147_CMP = 1'1 + Activation pattern for cell $auto$share.cc:667:make_supercell$442: $procmux$149_CMP = 1'1 + Activation pattern for cell $auto$share.cc:667:make_supercell$442: $procmux$206_CMP = 1'1 + Activation pattern for cell $auto$share.cc:667:make_supercell$442: $procmux$207_CMP = 1'1 + Activation pattern for cell $shl$operators_ref.v:15$3: $procmux$208_CMP = 1'1 + Size of SAT problem: 0 cells, 76 variables, 224 clauses + According to the SAT solver this pair of cells can be shared. + Activation signal for $shl$operators_ref.v:15$3: $auto$share.cc:977:make_cell_activation_logic$445 + New cell: $auto$share.cc:667:make_supercell$452 ($shl) + Analyzing resource sharing options for $auto$share.cc:667:make_supercell$452 ($shl): + Found 5 activation_patterns using ctrl signal { $procmux$208_CMP $procmux$207_CMP $procmux$206_CMP $procmux$149_CMP $procmux$147_CMP }. + Found 1 candidates: $shl$operators_ref.v:14$2 + Analyzing resource sharing with $shl$operators_ref.v:14$2 ($shl): + Found 1 activation_patterns using ctrl signal $procmux$209_CMP. + Activation pattern for cell $auto$share.cc:667:make_supercell$452: $procmux$147_CMP = 1'1 + Activation pattern for cell $auto$share.cc:667:make_supercell$452: $procmux$149_CMP = 1'1 + Activation pattern for cell $auto$share.cc:667:make_supercell$452: $procmux$206_CMP = 1'1 + Activation pattern for cell $auto$share.cc:667:make_supercell$452: $procmux$207_CMP = 1'1 + Activation pattern for cell $auto$share.cc:667:make_supercell$452: $procmux$208_CMP = 1'1 + Activation pattern for cell $shl$operators_ref.v:14$2: $procmux$209_CMP = 1'1 + Size of SAT problem: 0 cells, 84 variables, 253 clauses + According to the SAT solver this pair of cells can be shared. + Activation signal for $shl$operators_ref.v:14$2: $auto$share.cc:977:make_cell_activation_logic$455 + New cell: $auto$share.cc:667:make_supercell$462 ($shl) + Analyzing resource sharing options for $auto$share.cc:667:make_supercell$462 ($shl): + Found 6 activation_patterns using ctrl signal { $procmux$209_CMP $procmux$208_CMP $procmux$207_CMP $procmux$206_CMP $procmux$149_CMP $procmux$147_CMP }. + No candidates found. + Analyzing resource sharing options for $mod$operators_ref.v:87$61 ($mod): + Found 1 activation_patterns using ctrl signal $procmux$150_CMP. + Found 3 candidates: $mod$operators_ref.v:86$60 $mod$operators_ref.v:85$59 $mod$operators_ref.v:84$58 + Analyzing resource sharing with $mod$operators_ref.v:86$60 ($mod): + Found 1 activation_patterns using ctrl signal $procmux$151_CMP. + Activation pattern for cell $mod$operators_ref.v:87$61: $procmux$150_CMP = 1'1 + Activation pattern for cell $mod$operators_ref.v:86$60: $procmux$151_CMP = 1'1 + Size of SAT problem: 0 cells, 40 variables, 103 clauses + According to the SAT solver this pair of cells can be shared. + Activation signal for $mod$operators_ref.v:87$61: $auto$share.cc:977:make_cell_activation_logic$465 + New cell: $auto$share.cc:667:make_supercell$472 ($mod) + Analyzing resource sharing options for $auto$share.cc:667:make_supercell$472 ($mod): + Found 2 activation_patterns using ctrl signal { $procmux$151_CMP $procmux$150_CMP }. + Found 2 candidates: $mod$operators_ref.v:85$59 $mod$operators_ref.v:84$58 + Analyzing resource sharing with $mod$operators_ref.v:85$59 ($mod): + Found 1 activation_patterns using ctrl signal $procmux$152_CMP. + Activation pattern for cell $auto$share.cc:667:make_supercell$472: $procmux$150_CMP = 1'1 + Activation pattern for cell $auto$share.cc:667:make_supercell$472: $procmux$151_CMP = 1'1 + Activation pattern for cell $mod$operators_ref.v:85$59: $procmux$152_CMP = 1'1 + Size of SAT problem: 0 cells, 52 variables, 142 clauses + According to the SAT solver this pair of cells can be shared. + Activation signal for $mod$operators_ref.v:85$59: $auto$share.cc:977:make_cell_activation_logic$475 + New cell: $auto$share.cc:667:make_supercell$482 ($mod) + Analyzing resource sharing options for $auto$share.cc:667:make_supercell$482 ($mod): + Found 3 activation_patterns using ctrl signal { $procmux$152_CMP $procmux$151_CMP $procmux$150_CMP }. + Found 1 candidates: $mod$operators_ref.v:84$58 + Analyzing resource sharing with $mod$operators_ref.v:84$58 ($mod): + Found 1 activation_patterns using ctrl signal $procmux$153_CMP. + Activation pattern for cell $auto$share.cc:667:make_supercell$482: $procmux$150_CMP = 1'1 + Activation pattern for cell $auto$share.cc:667:make_supercell$482: $procmux$151_CMP = 1'1 + Activation pattern for cell $auto$share.cc:667:make_supercell$482: $procmux$152_CMP = 1'1 + Activation pattern for cell $mod$operators_ref.v:84$58: $procmux$153_CMP = 1'1 + Size of SAT problem: 0 cells, 60 variables, 171 clauses + According to the SAT solver this pair of cells can be shared. + Activation signal for $mod$operators_ref.v:84$58: $auto$share.cc:977:make_cell_activation_logic$485 + New cell: $auto$share.cc:667:make_supercell$492 ($mod) + Analyzing resource sharing options for $auto$share.cc:667:make_supercell$492 ($mod): + Found 4 activation_patterns using ctrl signal { $procmux$153_CMP $procmux$152_CMP $procmux$151_CMP $procmux$150_CMP }. + No candidates found. + Analyzing resource sharing options for $div$operators_ref.v:82$57 ($div): + Found 1 activation_patterns using ctrl signal $procmux$154_CMP. + Found 3 candidates: $div$operators_ref.v:81$56 $div$operators_ref.v:80$55 $div$operators_ref.v:79$54 + Analyzing resource sharing with $div$operators_ref.v:81$56 ($div): + Found 1 activation_patterns using ctrl signal $procmux$155_CMP. + Activation pattern for cell $div$operators_ref.v:82$57: $procmux$154_CMP = 1'1 + Activation pattern for cell $div$operators_ref.v:81$56: $procmux$155_CMP = 1'1 + Size of SAT problem: 0 cells, 40 variables, 103 clauses + According to the SAT solver this pair of cells can be shared. + Activation signal for $div$operators_ref.v:82$57: $auto$share.cc:977:make_cell_activation_logic$495 + New cell: $auto$share.cc:667:make_supercell$502 ($div) + Analyzing resource sharing options for $auto$share.cc:667:make_supercell$502 ($div): + Found 2 activation_patterns using ctrl signal { $procmux$155_CMP $procmux$154_CMP }. + Found 2 candidates: $div$operators_ref.v:80$55 $div$operators_ref.v:79$54 + Analyzing resource sharing with $div$operators_ref.v:80$55 ($div): + Found 1 activation_patterns using ctrl signal $procmux$156_CMP. + Activation pattern for cell $auto$share.cc:667:make_supercell$502: $procmux$154_CMP = 1'1 + Activation pattern for cell $auto$share.cc:667:make_supercell$502: $procmux$155_CMP = 1'1 + Activation pattern for cell $div$operators_ref.v:80$55: $procmux$156_CMP = 1'1 + Size of SAT problem: 0 cells, 52 variables, 142 clauses + According to the SAT solver this pair of cells can be shared. + Activation signal for $div$operators_ref.v:80$55: $auto$share.cc:977:make_cell_activation_logic$505 + New cell: $auto$share.cc:667:make_supercell$512 ($div) + Analyzing resource sharing options for $auto$share.cc:667:make_supercell$512 ($div): + Found 3 activation_patterns using ctrl signal { $procmux$156_CMP $procmux$155_CMP $procmux$154_CMP }. + Found 1 candidates: $div$operators_ref.v:79$54 + Analyzing resource sharing with $div$operators_ref.v:79$54 ($div): + Found 1 activation_patterns using ctrl signal $procmux$157_CMP. + Activation pattern for cell $auto$share.cc:667:make_supercell$512: $procmux$154_CMP = 1'1 + Activation pattern for cell $auto$share.cc:667:make_supercell$512: $procmux$155_CMP = 1'1 + Activation pattern for cell $auto$share.cc:667:make_supercell$512: $procmux$156_CMP = 1'1 + Activation pattern for cell $div$operators_ref.v:79$54: $procmux$157_CMP = 1'1 + Size of SAT problem: 0 cells, 60 variables, 171 clauses + According to the SAT solver this pair of cells can be shared. + Activation signal for $div$operators_ref.v:79$54: $auto$share.cc:977:make_cell_activation_logic$515 + New cell: $auto$share.cc:667:make_supercell$522 ($div) + Analyzing resource sharing options for $auto$share.cc:667:make_supercell$522 ($div): + Found 4 activation_patterns using ctrl signal { $procmux$157_CMP $procmux$156_CMP $procmux$155_CMP $procmux$154_CMP }. + No candidates found. +Removing 40 cells in module optest: + Removing cell $div$operators_ref.v:79$54 ($div). + Removing cell $auto$share.cc:667:make_supercell$512 ($div). + Removing cell $div$operators_ref.v:80$55 ($div). + Removing cell $auto$share.cc:667:make_supercell$502 ($div). + Removing cell $div$operators_ref.v:81$56 ($div). + Removing cell $div$operators_ref.v:82$57 ($div). + Removing cell $mod$operators_ref.v:84$58 ($mod). + Removing cell $auto$share.cc:667:make_supercell$482 ($mod). + Removing cell $mod$operators_ref.v:85$59 ($mod). + Removing cell $auto$share.cc:667:make_supercell$472 ($mod). + Removing cell $mod$operators_ref.v:86$60 ($mod). + Removing cell $mod$operators_ref.v:87$61 ($mod). + Removing cell $shl$operators_ref.v:14$2 ($shl). + Removing cell $auto$share.cc:667:make_supercell$452 ($shl). + Removing cell $shl$operators_ref.v:15$3 ($shl). + Removing cell $auto$share.cc:667:make_supercell$442 ($shl). + Removing cell $shl$operators_ref.v:16$4 ($shl). + Removing cell $auto$share.cc:667:make_supercell$432 ($shl). + Removing cell $shl$operators_ref.v:17$5 ($shl). + Removing cell $auto$share.cc:667:make_supercell$422 ($shl). + Removing cell $shl$operators_ref.v:89$62 ($shl). + Removing cell $shl$operators_ref.v:91$64 ($shl). + Removing cell $shr$operators_ref.v:19$6 ($shr). + Removing cell $auto$share.cc:667:make_supercell$402 ($shr). + Removing cell $shr$operators_ref.v:20$7 ($shr). + Removing cell $auto$share.cc:667:make_supercell$392 ($shr). + Removing cell $shr$operators_ref.v:21$8 ($shr). + Removing cell $shr$operators_ref.v:22$9 ($shr). + Removing cell $sshl$operators_ref.v:24$10 ($sshl). + Removing cell $auto$share.cc:667:make_supercell$372 ($sshl). + Removing cell $sshl$operators_ref.v:25$11 ($sshl). + Removing cell $auto$share.cc:667:make_supercell$362 ($sshl). + Removing cell $sshl$operators_ref.v:26$12 ($sshl). + Removing cell $sshl$operators_ref.v:27$13 ($sshl). + Removing cell $sshr$operators_ref.v:29$14 ($sshr). + Removing cell $auto$share.cc:667:make_supercell$342 ($sshr). + Removing cell $sshr$operators_ref.v:30$15 ($sshr). + Removing cell $auto$share.cc:667:make_supercell$332 ($sshr). + Removing cell $sshr$operators_ref.v:31$16 ($sshr). + Removing cell $sshr$operators_ref.v:32$17 ($sshr). + +4.13. Executing OPT pass (performing simple optimizations). + +4.13.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module optest. + + +4.13.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\optest'. + +Removed a total of 20 cells. + +4.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \optest.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \optest. + New ctrl vector for $pmux cell $procmux$125: { $procmux$209_CMP $procmux$208_CMP $procmux$207_CMP $procmux$206_CMP $procmux$205_CMP $procmux$204_CMP $auto$opt_reduce.cc:134:opt_pmux$536 $procmux$201_CMP $procmux$200_CMP $auto$opt_reduce.cc:134:opt_pmux$534 $procmux$197_CMP $procmux$196_CMP $auto$opt_reduce.cc:134:opt_pmux$532 $procmux$193_CMP $procmux$192_CMP $procmux$191_CMP $procmux$190_CMP $procmux$189_CMP $procmux$188_CMP $procmux$187_CMP $procmux$186_CMP $procmux$185_CMP $procmux$184_CMP $procmux$183_CMP $procmux$182_CMP $procmux$181_CMP $procmux$180_CMP $procmux$179_CMP $procmux$178_CMP $procmux$177_CMP $procmux$176_CMP $procmux$175_CMP $procmux$174_CMP $procmux$173_CMP $procmux$172_CMP $procmux$171_CMP $procmux$170_CMP $procmux$169_CMP $procmux$168_CMP $procmux$167_CMP $procmux$166_CMP $procmux$165_CMP $procmux$164_CMP $procmux$163_CMP $procmux$162_CMP $procmux$161_CMP $procmux$160_CMP $procmux$159_CMP $procmux$158_CMP $procmux$157_CMP $procmux$156_CMP $auto$opt_reduce.cc:134:opt_pmux$530 $procmux$153_CMP $procmux$152_CMP $auto$opt_reduce.cc:134:opt_pmux$528 $procmux$148_CMP $auto$opt_reduce.cc:134:opt_pmux$526 $procmux$146_CMP $procmux$145_CMP $procmux$144_CMP $procmux$143_CMP $procmux$142_CMP $procmux$141_CMP $procmux$140_CMP $procmux$139_CMP $procmux$138_CMP $procmux$137_CMP $procmux$136_CMP $procmux$135_CMP $procmux$134_CMP $procmux$133_CMP $procmux$132_CMP $procmux$131_CMP $procmux$130_CMP $procmux$129_CMP $procmux$128_CMP $procmux$127_CMP $procmux$126_CMP } + Optimizing cells in module \optest. +Performed a total of 1 changes. + +4.13.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\optest'. +Removed a total of 0 cells. + +4.13.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \optest.. +Removed 0 unused cells and 89 unused wires. + + +4.13.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module optest. + +4.13.9. Rerunning OPT passes. (Maybe there is more to do..) + +4.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \optest.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \optest. + New ctrl vector for $pmux cell $procmux$125: { $auto$opt_reduce.cc:134:opt_pmux$548 $auto$opt_reduce.cc:134:opt_pmux$546 $auto$opt_reduce.cc:134:opt_pmux$544 $procmux$193_CMP $procmux$192_CMP $procmux$191_CMP $procmux$190_CMP $procmux$189_CMP $procmux$188_CMP $procmux$187_CMP $procmux$186_CMP $procmux$185_CMP $procmux$184_CMP $procmux$183_CMP $procmux$182_CMP $procmux$181_CMP $procmux$180_CMP $procmux$179_CMP $procmux$178_CMP $procmux$177_CMP $procmux$176_CMP $procmux$175_CMP $procmux$174_CMP $procmux$173_CMP $procmux$172_CMP $procmux$171_CMP $procmux$170_CMP $procmux$169_CMP $procmux$168_CMP $procmux$167_CMP $procmux$166_CMP $procmux$165_CMP $procmux$164_CMP $procmux$163_CMP $procmux$162_CMP $procmux$161_CMP $procmux$160_CMP $procmux$159_CMP $procmux$158_CMP $auto$opt_reduce.cc:134:opt_pmux$542 $auto$opt_reduce.cc:134:opt_pmux$540 $procmux$148_CMP $auto$opt_reduce.cc:134:opt_pmux$538 $procmux$146_CMP $procmux$145_CMP $procmux$144_CMP $procmux$143_CMP $procmux$142_CMP $procmux$141_CMP $procmux$140_CMP $procmux$139_CMP $procmux$138_CMP $procmux$137_CMP $procmux$136_CMP $procmux$135_CMP $procmux$134_CMP $procmux$133_CMP $procmux$132_CMP $procmux$131_CMP $procmux$130_CMP $procmux$129_CMP $procmux$128_CMP $procmux$127_CMP $procmux$126_CMP } + New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$537: { $auto$share.cc:977:make_cell_activation_logic$455 $auto$share.cc:977:make_cell_activation_logic$445 $auto$share.cc:977:make_cell_activation_logic$435 $auto$share.cc:977:make_cell_activation_logic$425 $auto$share.cc:977:make_cell_activation_logic$415 $procmux$149_CMP } + New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$539: { $auto$share.cc:977:make_cell_activation_logic$485 $auto$share.cc:977:make_cell_activation_logic$475 $auto$share.cc:977:make_cell_activation_logic$465 $procmux$151_CMP } + New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$541: { $auto$share.cc:977:make_cell_activation_logic$515 $auto$share.cc:977:make_cell_activation_logic$505 $auto$share.cc:977:make_cell_activation_logic$495 $procmux$155_CMP } + New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$543: { $auto$share.cc:977:make_cell_activation_logic$345 $auto$share.cc:977:make_cell_activation_logic$335 $procmux$195_CMP $auto$share.cc:977:make_cell_activation_logic$325 } + New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$545: { $auto$share.cc:977:make_cell_activation_logic$375 $auto$share.cc:977:make_cell_activation_logic$365 $auto$share.cc:977:make_cell_activation_logic$355 $procmux$199_CMP } + New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$547: { $auto$share.cc:977:make_cell_activation_logic$405 $auto$share.cc:977:make_cell_activation_logic$395 $auto$share.cc:977:make_cell_activation_logic$385 $procmux$203_CMP } + Optimizing cells in module \optest. +Performed a total of 7 changes. + +4.13.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\optest'. +Removed a total of 0 cells. + +4.13.13. Executing OPT_DFF pass (perform DFF optimizations). + +4.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \optest.. +Removed 6 unused cells and 6 unused wires. + + +4.13.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module optest. + +4.13.16. Rerunning OPT passes. (Maybe there is more to do..) + +4.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \optest.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \optest. +Performed a total of 0 changes. + +4.13.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\optest'. +Removed a total of 0 cells. + +4.13.20. Executing OPT_DFF pass (perform DFF optimizations). + +4.13.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \optest.. + +4.13.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module optest. + +4.13.23. Finished OPT passes. (There is nothing left to do.) + +4.14. Executing MEMORY pass. + +4.14.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +4.14.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +4.14.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + +4.14.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +4.14.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). + +4.14.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \optest.. + +4.14.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +4.14.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +4.14.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \optest.. + +4.14.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +4.15. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \optest.. + +5. Executing OPT pass (performing simple optimizations). + +5.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module optest. + + +5.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\optest'. +Removed a total of 0 cells. + +5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \optest.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \optest. + Consolidated identical input bits for $mux cell $auto$share.cc:660:make_supercell$399: + Old ports: A={ \s1 [3] \s1 [3] \s1 [3] \s1 [3] \s1 }, B={ 4'0000 \u1 }, Y=$auto$share.cc:657:make_supercell$397 + New ports: A={ \s1 [3] \s1 }, B={ 1'0 \u1 }, Y=$auto$share.cc:657:make_supercell$397 [4:0] + New connections: $auto$share.cc:657:make_supercell$397 [7:5] = { $auto$share.cc:657:make_supercell$397 [4] $auto$share.cc:657:make_supercell$397 [4] $auto$share.cc:657:make_supercell$397 [4] } + Consolidated identical input bits for $mux cell $auto$share.cc:660:make_supercell$469: + Old ports: A={ 1'0 \s1 }, B={ \s1 [3] \s1 }, Y=$auto$share.cc:657:make_supercell$467 + New ports: A=1'0, B=\s1 [3], Y=$auto$share.cc:657:make_supercell$467 [4] + New connections: $auto$share.cc:657:make_supercell$467 [3:0] = \s1 + Consolidated identical input bits for $mux cell $auto$share.cc:660:make_supercell$499: + Old ports: A={ 1'0 \s1 }, B={ \s1 [3] \s1 }, Y=$auto$share.cc:657:make_supercell$497 + New ports: A=1'0, B=\s1 [3], Y=$auto$share.cc:657:make_supercell$497 [4] + New connections: $auto$share.cc:657:make_supercell$497 [3:0] = \s1 + Optimizing cells in module \optest. + Consolidated identical input bits for $mux cell $auto$share.cc:660:make_supercell$409: + Old ports: A=$auto$share.cc:657:make_supercell$397, B={ 4'0000 \u1 }, Y=$auto$share.cc:657:make_supercell$407 + New ports: A=$auto$share.cc:657:make_supercell$397 [4:0], B={ 1'0 \u1 }, Y=$auto$share.cc:657:make_supercell$407 [4:0] + New connections: $auto$share.cc:657:make_supercell$407 [7:5] = { $auto$share.cc:657:make_supercell$407 [4] $auto$share.cc:657:make_supercell$407 [4] $auto$share.cc:657:make_supercell$407 [4] } + Optimizing cells in module \optest. +Performed a total of 4 changes. + +5.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\optest'. +Removed a total of 0 cells. + +5.6. Executing OPT_SHARE pass. + Found cells that share an operand and can be merged by moving the $pmux $procmux$125 in front of them: + $auto$alumacc.cc:485:replace_alu$283 + $auto$alumacc.cc:485:replace_alu$251 + +5.7. Executing OPT_DFF pass (perform DFF optimizations). + +5.8. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \optest.. +Removed 0 unused cells and 9 unused wires. + + +5.9. Executing OPT_EXPR pass (perform const folding). +Optimizing module optest. + + +5.10. Rerunning OPT passes. (Maybe there is more to do..) + +5.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \optest.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +5.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). diff --git a/tests/simple_abc9/paramods.err b/tests/simple_abc9/paramods.err new file mode 100644 index 00000000000..a0bc8b8f63f --- /dev/null +++ b/tests/simple_abc9/paramods.err @@ -0,0 +1,925 @@ ++ body ++ cd paramods.out +++ basename paramods.v ++ fn=paramods.v +++ basename paramods ++ bn=paramods ++ refext=v ++ rm -f paramods_ref.fir ++ [[ v == \v ]] ++ egrep -v '^\s*`timescale' ../paramods.v +egrep: warning: egrep is obsolescent; using grep -E ++ '[' '!' -f ../paramods_tb.v ']' ++ /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../yosys -f 'verilog -noblackbox -specify -D_AUTOTB' -b 'test_autotb -n 300' -o paramods_tb.v paramods_ref.v + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2024 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) + +-- Parsing `paramods_ref.v' using frontend `verilog -noblackbox -specify -D_AUTOTB' -- + +1. Executing Verilog-2005 frontend: paramods_ref.v +Parsing Verilog input from `paramods_ref.v' to AST representation. +Generating RTLIL representation for module `\pm_test1'. +Generating RTLIL representation for module `\pm_test2'. +Generating RTLIL representation for module `\pm_test3'. +Generating RTLIL representation for module `\inc'. +Successfully finished Verilog frontend. + +-- Writing to `paramods_tb.v' using backend `test_autotb -n 300' -- + +2. Executing TEST_AUTOTB backend (auto-generate pseudo-random test benches). +Generating test bench for module `\inc'. +Generating test bench for module `\pm_test3'. +Generating test bench for module `\pm_test2'. +Generating test bench for module `\pm_test1'. + +End of script. Logfile hash: d413d55926, CPU: user 0.01s system 0.00s, MEM: 13.73 MB peak +Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) +Time spent: 82% 1x read_verilog (0 sec), 17% 1x test_autotb (0 sec) ++ false ++ compile_and_run paramods_tb_ref paramods_out_ref paramods_tb.v paramods_ref.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simlib.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simcells.v ++ exe=paramods_tb_ref ++ output=paramods_out_ref ++ shift 2 ++ '[' v == sv ']' ++ language_gen=-g2005 ++ false ++ false ++ iverilog -g2005 '-Doutfile="paramods_out_ref"' -s testbench -o paramods_tb_ref paramods_tb.v paramods_ref.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simlib.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simcells.v +paramods_ref.v:32: warning: Port 1 (in) of inc expects 4 bits, got 8. +paramods_ref.v:32: : Pruning 4 high bits of the expression. +paramods_ref.v:32: warning: Port 2 (out) of inc expects 4 bits, got 8. +paramods_ref.v:32: : Padding 4 high bits of the expression. +paramods_ref.v:19: warning: Port 1 (in) of inc expects 5 bits, got 8. +paramods_ref.v:19: : Pruning 3 high bits of the expression. +paramods_ref.v:19: warning: Port 2 (out) of inc expects 5 bits, got 8. +paramods_ref.v:19: : Padding 3 high bits of the expression. +paramods_ref.v:20: warning: Port 1 (in) of inc expects 4 bits, got 8. +paramods_ref.v:20: : Pruning 4 high bits of the expression. +paramods_ref.v:20: warning: Port 2 (out) of inc expects 4 bits, got 8. +paramods_ref.v:20: : Padding 4 high bits of the expression. +paramods_ref.v:8: warning: Port 1 (in) of inc expects 4 bits, got 8. +paramods_ref.v:8: : Pruning 4 high bits of the expression. +paramods_ref.v:8: warning: Port 2 (out) of inc expects 4 bits, got 8. +paramods_ref.v:8: : Padding 4 high bits of the expression. ++ vvp -n paramods_tb_ref +paramods_tb.v:308: $finish called at 480800 (1s) ++ false ++ test_count=0 ++ '[' 'verilog -noblackbox -specify' = verific -o 'verilog -noblackbox -specify' = verific_gates ']' ++ '[' -n '' ']' ++ '[' -n ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' ']' ++ test_passes -f 'verilog -noblackbox -specify ' -p ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' paramods_ref.v ++ /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../yosys -b 'verilog -noattr -noexpr -siminit' -o paramods_syn0.v -f 'verilog -noblackbox -specify ' -p ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' paramods_ref.v + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2024 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) + +-- Parsing `paramods_ref.v' using frontend `verilog -noblackbox -specify ' -- + +1. Executing Verilog-2005 frontend: paramods_ref.v +Parsing Verilog input from `paramods_ref.v' to AST representation. +Generating RTLIL representation for module `\pm_test1'. +Generating RTLIL representation for module `\pm_test2'. +Generating RTLIL representation for module `\pm_test3'. +Generating RTLIL representation for module `\inc'. +Successfully finished Verilog frontend. + +-- Running command ` read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' -- + +2. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v' to AST representation. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +3. Executing HIERARCHY pass (managing design hierarchy). +Parameter \width = 4 +Parameter \step = 7 + +3.1. Executing AST frontend in derive mode using pre-parsed AST for module `\inc'. +Parameter \width = 4 +Parameter \step = 7 +Generating RTLIL representation for module `$paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc'. +Parameter \step = 3 + +3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\inc'. +Parameter \step = 3 +Generating RTLIL representation for module `$paramod\inc\step=s32'00000000000000000000000000000011'. +Parameter 1 (\width) = 4 +Parameter 2 (\step) = 7 +Found cached RTLIL representation for module `$paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc'. +Parameter 1 (\width) = 5 + +3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\inc'. +Parameter 1 (\width) = 5 +Generating RTLIL representation for module `$paramod\inc\width=s32'00000000000000000000000000000101'. +Parameter \width = 4 +Parameter \step = 7 +Found cached RTLIL representation for module `$paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc'. +Parameter \step = 3 +Found cached RTLIL representation for module `$paramod\inc\step=s32'00000000000000000000000000000011'. +Mapping positional arguments of cell pm_test3.inc_b ($paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc). +Mapping positional arguments of cell pm_test2.inc_b ($paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc). +Mapping positional arguments of cell pm_test1.inc_b ($paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc). +Warning: Resizing cell port pm_test3.inc_b.in from 8 bits to 4 bits. +Warning: Resizing cell port pm_test3.inc_b.out from 8 bits to 4 bits. +Warning: Resizing cell port pm_test2.inc_b.in from 8 bits to 4 bits. +Warning: Resizing cell port pm_test2.inc_b.out from 8 bits to 4 bits. +Warning: Resizing cell port pm_test2.inc_a.out from 8 bits to 5 bits. +Warning: Resizing cell port pm_test2.inc_a.in from 8 bits to 5 bits. +Warning: Resizing cell port pm_test1.inc_b.in from 8 bits to 4 bits. +Warning: Resizing cell port pm_test1.inc_b.out from 8 bits to 4 bits. + +4. Executing SYNTH pass. + +4.1. Executing PROC pass (convert processes to netlists). + +4.1.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +4.1.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +4.1.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 0 assignments to connections. + +4.1.4. Executing PROC_INIT pass (extract init attributes). + +4.1.5. Executing PROC_ARST pass (detect async resets in processes). + +4.1.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + +4.1.7. Executing PROC_MUX pass (convert decision trees to multiplexers). + +4.1.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +4.1.9. Executing PROC_DFF pass (convert process syncs to FFs). + +4.1.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +4.1.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +4.1.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod\inc\width=s32'00000000000000000000000000000101. +Optimizing module $paramod\inc\step=s32'00000000000000000000000000000011. +Optimizing module $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc. +Optimizing module inc. +Optimizing module pm_test3. +Optimizing module pm_test2. +Optimizing module pm_test1. + +4.2. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod\inc\width=s32'00000000000000000000000000000101. +Optimizing module $paramod\inc\step=s32'00000000000000000000000000000011. +Optimizing module $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc. +Optimizing module inc. +Optimizing module pm_test3. +Optimizing module pm_test2. +Optimizing module pm_test1. + +4.3. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod\inc\width=s32'00000000000000000000000000000101.. +Finding unused cells or wires in module $paramod\inc\step=s32'00000000000000000000000000000011.. +Finding unused cells or wires in module $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc.. +Finding unused cells or wires in module \inc.. +Finding unused cells or wires in module \pm_test3.. +Finding unused cells or wires in module \pm_test2.. +Finding unused cells or wires in module \pm_test1.. + +4.4. Executing CHECK pass (checking for obvious problems). +Checking module $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc... +Checking module $paramod\inc\step=s32'00000000000000000000000000000011... +Checking module $paramod\inc\width=s32'00000000000000000000000000000101... +Checking module inc... +Checking module pm_test1... +Checking module pm_test2... +Checking module pm_test3... +Found and reported 0 problems. + +4.5. Executing OPT pass (performing simple optimizations). + +4.5.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc. +Optimizing module $paramod\inc\step=s32'00000000000000000000000000000011. +Optimizing module $paramod\inc\width=s32'00000000000000000000000000000101. +Optimizing module inc. +Optimizing module pm_test1. +Optimizing module pm_test2. +Optimizing module pm_test3. + +4.5.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `$paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc'. +Finding identical cells in module `$paramod\inc\step=s32'00000000000000000000000000000011'. +Finding identical cells in module `$paramod\inc\width=s32'00000000000000000000000000000101'. +Finding identical cells in module `\inc'. +Finding identical cells in module `\pm_test1'. +Finding identical cells in module `\pm_test2'. +Finding identical cells in module `\pm_test3'. +Removed a total of 0 cells. + +4.5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module $paramod\inc\step=s32'00000000000000000000000000000011.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module $paramod\inc\width=s32'00000000000000000000000000000101.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \inc.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \pm_test1.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \pm_test2.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \pm_test3.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc. + Optimizing cells in module $paramod\inc\step=s32'00000000000000000000000000000011. + Optimizing cells in module $paramod\inc\width=s32'00000000000000000000000000000101. + Optimizing cells in module \inc. + Optimizing cells in module \pm_test1. + Optimizing cells in module \pm_test2. + Optimizing cells in module \pm_test3. +Performed a total of 0 changes. + +4.5.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `$paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc'. +Finding identical cells in module `$paramod\inc\step=s32'00000000000000000000000000000011'. +Finding identical cells in module `$paramod\inc\width=s32'00000000000000000000000000000101'. +Finding identical cells in module `\inc'. +Finding identical cells in module `\pm_test1'. +Finding identical cells in module `\pm_test2'. +Finding identical cells in module `\pm_test3'. +Removed a total of 0 cells. + +4.5.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.5.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc.. +Finding unused cells or wires in module $paramod\inc\step=s32'00000000000000000000000000000011.. +Finding unused cells or wires in module $paramod\inc\width=s32'00000000000000000000000000000101.. +Finding unused cells or wires in module \inc.. +Finding unused cells or wires in module \pm_test1.. +Finding unused cells or wires in module \pm_test2.. +Finding unused cells or wires in module \pm_test3.. + +4.5.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc. +Optimizing module $paramod\inc\step=s32'00000000000000000000000000000011. +Optimizing module $paramod\inc\width=s32'00000000000000000000000000000101. +Optimizing module inc. +Optimizing module pm_test1. +Optimizing module pm_test2. +Optimizing module pm_test3. + +4.5.9. Finished OPT passes. (There is nothing left to do.) + +4.6. Executing FSM pass (extract and optimize FSM). + +4.6.1. Executing FSM_DETECT pass (finding FSMs in design). + +4.6.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +4.6.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.6.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc.. +Finding unused cells or wires in module $paramod\inc\step=s32'00000000000000000000000000000011.. +Finding unused cells or wires in module $paramod\inc\width=s32'00000000000000000000000000000101.. +Finding unused cells or wires in module \inc.. +Finding unused cells or wires in module \pm_test1.. +Finding unused cells or wires in module \pm_test2.. +Finding unused cells or wires in module \pm_test3.. + +4.6.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.6.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +4.6.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +4.6.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +4.7. Executing OPT pass (performing simple optimizations). + +4.7.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc. +Optimizing module $paramod\inc\step=s32'00000000000000000000000000000011. +Optimizing module $paramod\inc\width=s32'00000000000000000000000000000101. +Optimizing module inc. +Optimizing module pm_test1. +Optimizing module pm_test2. +Optimizing module pm_test3. + +4.7.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `$paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc'. +Finding identical cells in module `$paramod\inc\step=s32'00000000000000000000000000000011'. +Finding identical cells in module `$paramod\inc\width=s32'00000000000000000000000000000101'. +Finding identical cells in module `\inc'. +Finding identical cells in module `\pm_test1'. +Finding identical cells in module `\pm_test2'. +Finding identical cells in module `\pm_test3'. +Removed a total of 0 cells. + +4.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module $paramod\inc\step=s32'00000000000000000000000000000011.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module $paramod\inc\width=s32'00000000000000000000000000000101.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \inc.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \pm_test1.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \pm_test2.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \pm_test3.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc. + Optimizing cells in module $paramod\inc\step=s32'00000000000000000000000000000011. + Optimizing cells in module $paramod\inc\width=s32'00000000000000000000000000000101. + Optimizing cells in module \inc. + Optimizing cells in module \pm_test1. + Optimizing cells in module \pm_test2. + Optimizing cells in module \pm_test3. +Performed a total of 0 changes. + +4.7.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `$paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc'. +Finding identical cells in module `$paramod\inc\step=s32'00000000000000000000000000000011'. +Finding identical cells in module `$paramod\inc\width=s32'00000000000000000000000000000101'. +Finding identical cells in module `\inc'. +Finding identical cells in module `\pm_test1'. +Finding identical cells in module `\pm_test2'. +Finding identical cells in module `\pm_test3'. +Removed a total of 0 cells. + +4.7.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc.. +Finding unused cells or wires in module $paramod\inc\step=s32'00000000000000000000000000000011.. +Finding unused cells or wires in module $paramod\inc\width=s32'00000000000000000000000000000101.. +Finding unused cells or wires in module \inc.. +Finding unused cells or wires in module \pm_test1.. +Finding unused cells or wires in module \pm_test2.. +Finding unused cells or wires in module \pm_test3.. + +4.7.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc. +Optimizing module $paramod\inc\step=s32'00000000000000000000000000000011. +Optimizing module $paramod\inc\width=s32'00000000000000000000000000000101. +Optimizing module inc. +Optimizing module pm_test1. +Optimizing module pm_test2. +Optimizing module pm_test3. + +4.7.9. Finished OPT passes. (There is nothing left to do.) + +4.8. Executing WREDUCE pass (reducing word size of cells). +Removed top 29 bits (of 32) from port B of cell $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc.$add$paramods_ref.v:50$2 ($add). +Removed top 28 bits (of 32) from port Y of cell $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc.$add$paramods_ref.v:50$2 ($add). +Removed top 30 bits (of 32) from port B of cell $paramod\inc\step=s32'00000000000000000000000000000011.$add$paramods_ref.v:50$3 ($add). +Removed top 24 bits (of 32) from port Y of cell $paramod\inc\step=s32'00000000000000000000000000000011.$add$paramods_ref.v:50$3 ($add). +Removed top 31 bits (of 32) from port B of cell $paramod\inc\width=s32'00000000000000000000000000000101.$add$paramods_ref.v:50$4 ($add). +Removed top 27 bits (of 32) from port Y of cell $paramod\inc\width=s32'00000000000000000000000000000101.$add$paramods_ref.v:50$4 ($add). +Removed top 31 bits (of 32) from port B of cell inc.$add$paramods_ref.v:50$1 ($add). +Removed top 24 bits (of 32) from port Y of cell inc.$add$paramods_ref.v:50$1 ($add). + +4.9. Executing PEEPOPT pass (run peephole optimizers). + +4.10. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc.. +Finding unused cells or wires in module $paramod\inc\step=s32'00000000000000000000000000000011.. +Finding unused cells or wires in module $paramod\inc\width=s32'00000000000000000000000000000101.. +Finding unused cells or wires in module \inc.. +Finding unused cells or wires in module \pm_test1.. +Finding unused cells or wires in module \pm_test2.. +Finding unused cells or wires in module \pm_test3.. +Removed 0 unused cells and 4 unused wires. + + +4.11. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc: + creating $macc model for $add$paramods_ref.v:50$2 ($add). + creating $alu model for $macc $add$paramods_ref.v:50$2. + creating $alu cell for $add$paramods_ref.v:50$2: $auto$alumacc.cc:485:replace_alu$5 + created 1 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module $paramod\inc\step=s32'00000000000000000000000000000011: + creating $macc model for $add$paramods_ref.v:50$3 ($add). + creating $alu model for $macc $add$paramods_ref.v:50$3. + creating $alu cell for $add$paramods_ref.v:50$3: $auto$alumacc.cc:485:replace_alu$8 + created 1 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module $paramod\inc\width=s32'00000000000000000000000000000101: + creating $macc model for $add$paramods_ref.v:50$4 ($add). + creating $alu model for $macc $add$paramods_ref.v:50$4. + creating $alu cell for $add$paramods_ref.v:50$4: $auto$alumacc.cc:485:replace_alu$11 + created 1 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module inc: + creating $macc model for $add$paramods_ref.v:50$1 ($add). + creating $alu model for $macc $add$paramods_ref.v:50$1. + creating $alu cell for $add$paramods_ref.v:50$1: $auto$alumacc.cc:485:replace_alu$14 + created 1 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module pm_test1: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module pm_test2: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module pm_test3: + created 0 $alu and 0 $macc cells. + +4.12. Executing SHARE pass (SAT-based resource sharing). + +4.13. Executing OPT pass (performing simple optimizations). + +4.13.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc. +Optimizing module $paramod\inc\step=s32'00000000000000000000000000000011. +Optimizing module $paramod\inc\width=s32'00000000000000000000000000000101. +Optimizing module inc. +Optimizing module pm_test1. +Optimizing module pm_test2. +Optimizing module pm_test3. + +4.13.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `$paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc'. +Finding identical cells in module `$paramod\inc\step=s32'00000000000000000000000000000011'. +Finding identical cells in module `$paramod\inc\width=s32'00000000000000000000000000000101'. +Finding identical cells in module `\inc'. +Finding identical cells in module `\pm_test1'. +Finding identical cells in module `\pm_test2'. +Finding identical cells in module `\pm_test3'. +Removed a total of 0 cells. + +4.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module $paramod\inc\step=s32'00000000000000000000000000000011.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module $paramod\inc\width=s32'00000000000000000000000000000101.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \inc.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \pm_test1.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \pm_test2.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \pm_test3.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc. + Optimizing cells in module $paramod\inc\step=s32'00000000000000000000000000000011. + Optimizing cells in module $paramod\inc\width=s32'00000000000000000000000000000101. + Optimizing cells in module \inc. + Optimizing cells in module \pm_test1. + Optimizing cells in module \pm_test2. + Optimizing cells in module \pm_test3. +Performed a total of 0 changes. + +4.13.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `$paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc'. +Finding identical cells in module `$paramod\inc\step=s32'00000000000000000000000000000011'. +Finding identical cells in module `$paramod\inc\width=s32'00000000000000000000000000000101'. +Finding identical cells in module `\inc'. +Finding identical cells in module `\pm_test1'. +Finding identical cells in module `\pm_test2'. +Finding identical cells in module `\pm_test3'. +Removed a total of 0 cells. + +4.13.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc.. +Finding unused cells or wires in module $paramod\inc\step=s32'00000000000000000000000000000011.. +Finding unused cells or wires in module $paramod\inc\width=s32'00000000000000000000000000000101.. +Finding unused cells or wires in module \inc.. +Finding unused cells or wires in module \pm_test1.. +Finding unused cells or wires in module \pm_test2.. +Finding unused cells or wires in module \pm_test3.. + +4.13.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc. +Optimizing module $paramod\inc\step=s32'00000000000000000000000000000011. +Optimizing module $paramod\inc\width=s32'00000000000000000000000000000101. +Optimizing module inc. +Optimizing module pm_test1. +Optimizing module pm_test2. +Optimizing module pm_test3. + +4.13.9. Finished OPT passes. (There is nothing left to do.) + +4.14. Executing MEMORY pass. + +4.14.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +4.14.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +4.14.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + +4.14.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +4.14.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). + +4.14.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc.. +Finding unused cells or wires in module $paramod\inc\step=s32'00000000000000000000000000000011.. +Finding unused cells or wires in module $paramod\inc\width=s32'00000000000000000000000000000101.. +Finding unused cells or wires in module \inc.. +Finding unused cells or wires in module \pm_test1.. +Finding unused cells or wires in module \pm_test2.. +Finding unused cells or wires in module \pm_test3.. + +4.14.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +4.14.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +4.14.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc.. +Finding unused cells or wires in module $paramod\inc\step=s32'00000000000000000000000000000011.. +Finding unused cells or wires in module $paramod\inc\width=s32'00000000000000000000000000000101.. +Finding unused cells or wires in module \inc.. +Finding unused cells or wires in module \pm_test1.. +Finding unused cells or wires in module \pm_test2.. +Finding unused cells or wires in module \pm_test3.. + +4.14.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +4.15. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc.. +Finding unused cells or wires in module $paramod\inc\step=s32'00000000000000000000000000000011.. +Finding unused cells or wires in module $paramod\inc\width=s32'00000000000000000000000000000101.. +Finding unused cells or wires in module \inc.. +Finding unused cells or wires in module \pm_test1.. +Finding unused cells or wires in module \pm_test2.. +Finding unused cells or wires in module \pm_test3.. + +5. Executing OPT pass (performing simple optimizations). + +5.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc. +Optimizing module $paramod\inc\step=s32'00000000000000000000000000000011. +Optimizing module $paramod\inc\width=s32'00000000000000000000000000000101. +Optimizing module inc. +Optimizing module pm_test1. +Optimizing module pm_test2. +Optimizing module pm_test3. + +5.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `$paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc'. +Finding identical cells in module `$paramod\inc\step=s32'00000000000000000000000000000011'. +Finding identical cells in module `$paramod\inc\width=s32'00000000000000000000000000000101'. +Finding identical cells in module `\inc'. +Finding identical cells in module `\pm_test1'. +Finding identical cells in module `\pm_test2'. +Finding identical cells in module `\pm_test3'. +Removed a total of 0 cells. + +5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module $paramod\inc\step=s32'00000000000000000000000000000011.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module $paramod\inc\width=s32'00000000000000000000000000000101.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \inc.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \pm_test1.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \pm_test2.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \pm_test3.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc. + Optimizing cells in module $paramod\inc\step=s32'00000000000000000000000000000011. + Optimizing cells in module $paramod\inc\width=s32'00000000000000000000000000000101. + Optimizing cells in module \inc. + Optimizing cells in module \pm_test1. + Optimizing cells in module \pm_test2. + Optimizing cells in module \pm_test3. +Performed a total of 0 changes. + +5.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `$paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc'. +Finding identical cells in module `$paramod\inc\step=s32'00000000000000000000000000000011'. +Finding identical cells in module `$paramod\inc\width=s32'00000000000000000000000000000101'. +Finding identical cells in module `\inc'. +Finding identical cells in module `\pm_test1'. +Finding identical cells in module `\pm_test2'. +Finding identical cells in module `\pm_test3'. +Removed a total of 0 cells. + +5.6. Executing OPT_SHARE pass. + +5.7. Executing OPT_DFF pass (perform DFF optimizations). + +5.8. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc.. +Finding unused cells or wires in module $paramod\inc\step=s32'00000000000000000000000000000011.. +Finding unused cells or wires in module $paramod\inc\width=s32'00000000000000000000000000000101.. +Finding unused cells or wires in module \inc.. +Finding unused cells or wires in module \pm_test1.. +Finding unused cells or wires in module \pm_test2.. +Finding unused cells or wires in module \pm_test3.. + +5.9. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc. +Optimizing module $paramod\inc\step=s32'00000000000000000000000000000011. +Optimizing module $paramod\inc\width=s32'00000000000000000000000000000101. +Optimizing module inc. +Optimizing module pm_test1. +Optimizing module pm_test2. +Optimizing module pm_test3. + +5.10. Finished OPT passes. (There is nothing left to do.) + +6. Executing TECHMAP pass (map to technology primitives). + +6.1. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/techmap.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +6.2. Continuing TECHMAP pass. +Using template $paramod$c3cd1564c35d873179656addd6052d7ea8b6d991\_90_alu for cells of type $alu. +Using extmapper simplemap for cells of type $xor. +Using extmapper simplemap for cells of type $and. +Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000001000 for cells of type $lcu. +Using extmapper simplemap for cells of type $pos. +Using extmapper simplemap for cells of type $mux. +Using extmapper simplemap for cells of type $not. +Using extmapper simplemap for cells of type $or. +Using template $paramod$672a140277c71df8314410f22acc08d55222c3c7\_90_alu for cells of type $alu. +Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000101 for cells of type $lcu. +Using template $paramod$a950948e19702336540a1f557d0a91306bdb9188\_90_alu for cells of type $alu. +Using template $paramod$1a3a0c35c4a4896fbfd612699525c057298e72d2\_90_alu for cells of type $alu. +Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu. +No more expansions possible. + + +7. Executing ABC9 pass. + +7.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.2. Executing ABC9_OPS pass (helper functions for ABC9). + +7.3. Executing SCC pass (detecting logic loops). +Found 0 SCCs in module $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc. +Found 0 SCCs in module $paramod\inc\step=s32'00000000000000000000000000000011. +Found 0 SCCs in module $paramod\inc\width=s32'00000000000000000000000000000101. +Found 0 SCCs in module inc. +Found 0 SCCs in module pm_test1. +Found 0 SCCs in module pm_test2. +Found 0 SCCs in module pm_test3. +Found 0 SCCs. + +7.4. Executing ABC9_OPS pass (helper functions for ABC9). + +7.5. Executing PROC pass (convert processes to netlists). + +7.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +7.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +7.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 0 assignments to connections. + +7.5.4. Executing PROC_INIT pass (extract init attributes). + +7.5.5. Executing PROC_ARST pass (detect async resets in processes). + +7.5.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + +7.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). + +7.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +7.5.9. Executing PROC_DFF pass (convert process syncs to FFs). + +7.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +7.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +7.5.12. Executing OPT_EXPR pass (perform const folding). + +7.6. Executing TECHMAP pass (map to technology primitives). + +7.6.1. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/techmap.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +7.6.2. Continuing TECHMAP pass. +No more expansions possible. + + +7.7. Executing OPT pass (performing simple optimizations). + +7.7.1. Executing OPT_EXPR pass (perform const folding). + +7.7.2. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +7.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Removed 0 multiplexer ports. + +7.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +Performed a total of 0 changes. + +7.7.5. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +7.7.6. Executing OPT_DFF pass (perform DFF optimizations). + +7.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). + +7.7.8. Executing OPT_EXPR pass (perform const folding). + +7.7.9. Finished OPT passes. (There is nothing left to do.) + +7.8. Executing TECHMAP pass (map to technology primitives). + +7.8.1. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/abc9_map.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/abc9_map.v' to AST representation. +Successfully finished Verilog frontend. + +7.8.2. Continuing TECHMAP pass. +No more expansions possible. + + +7.9. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v' to AST representation. +Replacing existing blackbox module `$__ABC9_DELAY' at /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v:2.1-7.10. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Replacing existing blackbox module `$__ABC9_SCC_BREAKER' at /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v:9.1-11.10. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Replacing existing module `$__DFF_N__$abc9_flop' at /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v:14.1-20.10. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Replacing existing module `$__DFF_P__$abc9_flop' at /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v:23.1-29.10. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +7.10. Executing ABC9_OPS pass (helper functions for ABC9). + +7.11. Executing ABC9_OPS pass (helper functions for ABC9). + + +7.12. Executing AIGMAP pass (map logic to AIG). +Module $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc: replaced 18 cells with 111 new cells, skipped 14 cells. + replaced 3 cell types: + 5 $_OR_ + 9 $_XOR_ + 4 $_MUX_ + not replaced 2 cell types: + 4 $_NOT_ + 10 $_AND_ +Module $paramod\inc\step=s32'00000000000000000000000000000011: replaced 37 cells with 223 new cells, skipped 32 cells. + replaced 3 cell types: + 12 $_OR_ + 17 $_XOR_ + 8 $_MUX_ + not replaced 2 cell types: + 8 $_NOT_ + 24 $_AND_ +Module $paramod\inc\width=s32'00000000000000000000000000000101: replaced 22 cells with 136 new cells, skipped 17 cells. + replaced 3 cell types: + 6 $_OR_ + 11 $_XOR_ + 5 $_MUX_ + not replaced 2 cell types: + 5 $_NOT_ + 12 $_AND_ +Module inc: replaced 37 cells with 223 new cells, skipped 32 cells. + replaced 3 cell types: + 12 $_OR_ + 17 $_XOR_ + 8 $_MUX_ + not replaced 2 cell types: + 8 $_NOT_ + 24 $_AND_ +Module pm_test1: replaced 0 cells with 0 new cells, skipped 2 cells. + not replaced 2 cell types: + 1 $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc + 1 $paramod\inc\step=s32'00000000000000000000000000000011 +Module pm_test2: replaced 0 cells with 0 new cells, skipped 2 cells. + not replaced 2 cell types: + 1 $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc + 1 $paramod\inc\width=s32'00000000000000000000000000000101 +Module pm_test3: replaced 0 cells with 0 new cells, skipped 2 cells. + not replaced 2 cell types: + 1 $paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc + 1 $paramod\inc\step=s32'00000000000000000000000000000011 + +7.12.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.12.2. Executing XAIGER backend. + +Extracted 54 AND gates and 112 wires from module `$paramod$13e4c40ad4eb4f9982560128338ac3e13d3e1c1d\inc' to a netlist network with 4 inputs and 4 outputs. + +7.12.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.12.4. Executing ABC9. diff --git a/tests/simple_abc9/partsel.err b/tests/simple_abc9/partsel.err new file mode 100644 index 00000000000..4f1dec33b6f --- /dev/null +++ b/tests/simple_abc9/partsel.err @@ -0,0 +1,492 @@ ++ body ++ cd partsel.out +++ basename partsel.v ++ fn=partsel.v +++ basename partsel ++ bn=partsel ++ refext=v ++ rm -f partsel_ref.fir ++ [[ v == \v ]] ++ egrep -v '^\s*`timescale' ../partsel.v +egrep: warning: egrep is obsolescent; using grep -E ++ '[' '!' -f ../partsel_tb.v ']' ++ /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../yosys -f 'verilog -noblackbox -specify -D_AUTOTB' -b 'test_autotb -n 300' -o partsel_tb.v partsel_ref.v + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2024 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) + +-- Parsing `partsel_ref.v' using frontend `verilog -noblackbox -specify -D_AUTOTB' -- + +1. Executing Verilog-2005 frontend: partsel_ref.v +Parsing Verilog input from `partsel_ref.v' to AST representation. +Generating RTLIL representation for module `\partsel_test001'. +Generating RTLIL representation for module `\partsel_test002'. +Generating RTLIL representation for module `\partsel_test003'. +Generating RTLIL representation for module `\partsel_test004'. +Generating RTLIL representation for module `\partsel_test005'. +Generating RTLIL representation for module `\partsel_test006'. +Generating RTLIL representation for module `\partsel_test007'. +Generating RTLIL representation for module `\partsel_test008'. +Successfully finished Verilog frontend. + +-- Writing to `partsel_tb.v' using backend `test_autotb -n 300' -- + +2. Executing TEST_AUTOTB backend (auto-generate pseudo-random test benches). +Generating test bench for module `\partsel_test008'. +Generating test bench for module `\partsel_test007'. +Generating test bench for module `\partsel_test006'. +Generating test bench for module `\partsel_test005'. +Generating test bench for module `\partsel_test004'. +Generating test bench for module `\partsel_test003'. +Generating test bench for module `\partsel_test002'. +Generating test bench for module `\partsel_test001'. + +End of script. Logfile hash: 312fa2a4d8, CPU: user 0.02s system 0.00s, MEM: 15.35 MB peak +Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) +Time spent: 95% 1x read_verilog (0 sec), 4% 1x test_autotb (0 sec) ++ false ++ compile_and_run partsel_tb_ref partsel_out_ref partsel_tb.v partsel_ref.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simlib.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simcells.v ++ exe=partsel_tb_ref ++ output=partsel_out_ref ++ shift 2 ++ '[' v == sv ']' ++ language_gen=-g2005 ++ false ++ false ++ iverilog -g2005 '-Doutfile="partsel_out_ref"' -s testbench -o partsel_tb_ref partsel_tb.v partsel_ref.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simlib.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simcells.v ++ vvp -n partsel_tb_ref +partsel_tb.v:766: $finish called at 962000 (1s) ++ false ++ test_count=0 ++ '[' 'verilog -noblackbox -specify' = verific -o 'verilog -noblackbox -specify' = verific_gates ']' ++ '[' -n '' ']' ++ '[' -n ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' ']' ++ test_passes -f 'verilog -noblackbox -specify ' -p ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' partsel_ref.v ++ /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../yosys -b 'verilog -noattr -noexpr -siminit' -o partsel_syn0.v -f 'verilog -noblackbox -specify ' -p ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' partsel_ref.v + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2024 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) + +-- Parsing `partsel_ref.v' using frontend `verilog -noblackbox -specify ' -- + +1. Executing Verilog-2005 frontend: partsel_ref.v +Parsing Verilog input from `partsel_ref.v' to AST representation. +Generating RTLIL representation for module `\partsel_test001'. +Generating RTLIL representation for module `\partsel_test002'. +Generating RTLIL representation for module `\partsel_test003'. +Generating RTLIL representation for module `\partsel_test004'. +Generating RTLIL representation for module `\partsel_test005'. +Generating RTLIL representation for module `\partsel_test006'. +Generating RTLIL representation for module `\partsel_test007'. +Generating RTLIL representation for module `\partsel_test008'. +Successfully finished Verilog frontend. + +-- Running command ` read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' -- + +2. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v' to AST representation. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +3. Executing HIERARCHY pass (managing design hierarchy). + +4. Executing SYNTH pass. + +4.1. Executing PROC pass (convert processes to netlists). + +4.1.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +4.1.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 2 switch rules as full_case in process $proc$partsel_ref.v:37$60 in module partsel_test002. +Removed a total of 0 dead cases. + +4.1.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 10 assignments to connections. + +4.1.4. Executing PROC_INIT pass (extract init attributes). + +4.1.5. Executing PROC_ARST pass (detect async resets in processes). + +4.1.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +4.1.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\partsel_test007.$proc$partsel_ref.v:108$116'. +Creating decoders for process `\partsel_test006.$proc$partsel_ref.v:96$98'. +Creating decoders for process `\partsel_test005.$proc$partsel_ref.v:85$86'. +Creating decoders for process `\partsel_test004.$proc$partsel_ref.v:73$72'. +Creating decoders for process `\partsel_test002.$proc$partsel_ref.v:37$60'. + 1/10: $1\r2[7:0] [7:5] + 2/10: $1\r1[7:0] [4] + 3/10: $1\r2[7:0] [3] + 4/10: $1\r2[7:0] [4] + 5/10: $1\r2[7:0] [1:0] + 6/10: $1\r1[7:0] [7] + 7/10: $1\r2[7:0] [2] + 8/10: $1\r1[7:0] [6:5] + 9/10: $1\r1[7:0] [1:0] + 10/10: $1\r1[7:0] [3:2] + +4.1.8. Executing PROC_DLATCH pass (convert process syncs to latches). +No latch inferred for signal `\partsel_test007.\dout' from process `\partsel_test007.$proc$partsel_ref.v:108$116'. +No latch inferred for signal `\partsel_test007.$bitselwrite$pos$partsel_ref.v:110$115' from process `\partsel_test007.$proc$partsel_ref.v:108$116'. +No latch inferred for signal `\partsel_test006.\dout' from process `\partsel_test006.$proc$partsel_ref.v:96$98'. +No latch inferred for signal `\partsel_test006.$bitselwrite$pos$partsel_ref.v:98$97' from process `\partsel_test006.$proc$partsel_ref.v:96$98'. +No latch inferred for signal `\partsel_test005.\dout' from process `\partsel_test005.$proc$partsel_ref.v:85$86'. +No latch inferred for signal `\partsel_test005.$bitselwrite$pos$partsel_ref.v:87$85' from process `\partsel_test005.$proc$partsel_ref.v:85$86'. +No latch inferred for signal `\partsel_test004.\dout' from process `\partsel_test004.$proc$partsel_ref.v:73$72'. +No latch inferred for signal `\partsel_test004.$bitselwrite$pos$partsel_ref.v:75$71' from process `\partsel_test004.$proc$partsel_ref.v:73$72'. + +4.1.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\partsel_test002.\r1' using process `\partsel_test002.$proc$partsel_ref.v:37$60'. + created $dff cell `$procdff$243' with positive edge clock. +Creating register for signal `\partsel_test002.\r2' using process `\partsel_test002.$proc$partsel_ref.v:37$60'. + created $dff cell `$procdff$244' with positive edge clock. + +4.1.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +4.1.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `partsel_test007.$proc$partsel_ref.v:108$116'. +Removing empty process `partsel_test006.$proc$partsel_ref.v:96$98'. +Removing empty process `partsel_test005.$proc$partsel_ref.v:85$86'. +Removing empty process `partsel_test004.$proc$partsel_ref.v:73$72'. +Found and cleaned up 2 empty switches in `\partsel_test002.$proc$partsel_ref.v:37$60'. +Removing empty process `partsel_test002.$proc$partsel_ref.v:37$60'. +Cleaned up 2 empty switches. + +4.1.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module partsel_test008. +Optimizing module partsel_test007. + +Optimizing module partsel_test006. + +Optimizing module partsel_test005. + +Optimizing module partsel_test004. + +Optimizing module partsel_test003. +Optimizing module partsel_test002. + +Optimizing module partsel_test001. + + +4.2. Executing OPT_EXPR pass (perform const folding). +Optimizing module partsel_test008. + +Optimizing module partsel_test007. +Optimizing module partsel_test006. + +Optimizing module partsel_test005. +Optimizing module partsel_test004. + +Optimizing module partsel_test003. + +Optimizing module partsel_test002. + +Optimizing module partsel_test001. + + +4.3. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \partsel_test008.. +Finding unused cells or wires in module \partsel_test007.. +Finding unused cells or wires in module \partsel_test006.. +Finding unused cells or wires in module \partsel_test005.. +Finding unused cells or wires in module \partsel_test004.. +Finding unused cells or wires in module \partsel_test003.. +Finding unused cells or wires in module \partsel_test002.. +Finding unused cells or wires in module \partsel_test001.. +Removed 14 unused cells and 130 unused wires. + + +4.4. Executing CHECK pass (checking for obvious problems). +Checking module partsel_test001... +Checking module partsel_test002... +Checking module partsel_test003... +Checking module partsel_test004... +Checking module partsel_test005... +Checking module partsel_test006... +Checking module partsel_test007... +Checking module partsel_test008... +Found and reported 0 problems. + +4.5. Executing OPT pass (performing simple optimizations). + +4.5.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module partsel_test001. +Optimizing module partsel_test002. +Optimizing module partsel_test003. +Optimizing module partsel_test004. +Optimizing module partsel_test005. +Optimizing module partsel_test006. +Optimizing module partsel_test007. +Optimizing module partsel_test008. + +4.5.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\partsel_test001'. +Finding identical cells in module `\partsel_test002'. + +Finding identical cells in module `\partsel_test003'. +Finding identical cells in module `\partsel_test004'. +Finding identical cells in module `\partsel_test005'. +Finding identical cells in module `\partsel_test006'. +Finding identical cells in module `\partsel_test007'. +Finding identical cells in module `\partsel_test008'. + +Removed a total of 54 cells. + +4.5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \partsel_test001.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \partsel_test002.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \partsel_test003.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \partsel_test004.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \partsel_test005.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \partsel_test006.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \partsel_test007.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \partsel_test008.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + + +4.5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \partsel_test001. + Optimizing cells in module \partsel_test002. + Optimizing cells in module \partsel_test003. + Optimizing cells in module \partsel_test004. + Optimizing cells in module \partsel_test005. + Optimizing cells in module \partsel_test006. + Optimizing cells in module \partsel_test007. + Optimizing cells in module \partsel_test008. +Performed a total of 0 changes. + +4.5.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\partsel_test001'. +Finding identical cells in module `\partsel_test002'. +Finding identical cells in module `\partsel_test003'. +Finding identical cells in module `\partsel_test004'. +Finding identical cells in module `\partsel_test005'. +Finding identical cells in module `\partsel_test006'. +Finding identical cells in module `\partsel_test007'. +Finding identical cells in module `\partsel_test008'. +Removed a total of 0 cells. + +4.5.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.5.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \partsel_test001.. +Finding unused cells or wires in module \partsel_test002.. +Finding unused cells or wires in module \partsel_test003.. +Finding unused cells or wires in module \partsel_test004.. +Finding unused cells or wires in module \partsel_test005.. +Finding unused cells or wires in module \partsel_test006.. +Finding unused cells or wires in module \partsel_test007.. +Finding unused cells or wires in module \partsel_test008.. +Removed 0 unused cells and 44 unused wires. + + +4.5.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module partsel_test001. +Optimizing module partsel_test002. +Optimizing module partsel_test003. +Optimizing module partsel_test004. +Optimizing module partsel_test005. +Optimizing module partsel_test006. +Optimizing module partsel_test007. +Optimizing module partsel_test008. + +4.5.9. Rerunning OPT passes. (Maybe there is more to do..) + +4.5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \partsel_test001.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \partsel_test002.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \partsel_test003.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \partsel_test004.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \partsel_test005.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \partsel_test006.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \partsel_test007.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \partsel_test008.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + + +4.5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \partsel_test001. + Optimizing cells in module \partsel_test002. + Optimizing cells in module \partsel_test003. + Optimizing cells in module \partsel_test004. + Optimizing cells in module \partsel_test005. + Optimizing cells in module \partsel_test006. + Optimizing cells in module \partsel_test007. + Optimizing cells in module \partsel_test008. +Performed a total of 0 changes. + +4.5.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\partsel_test001'. +Finding identical cells in module `\partsel_test002'. +Finding identical cells in module `\partsel_test003'. +Finding identical cells in module `\partsel_test004'. +Finding identical cells in module `\partsel_test005'. +Finding identical cells in module `\partsel_test006'. +Finding identical cells in module `\partsel_test007'. +Finding identical cells in module `\partsel_test008'. +Removed a total of 0 cells. + +4.5.13. Executing OPT_DFF pass (perform DFF optimizations). + +4.5.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \partsel_test001.. +Finding unused cells or wires in module \partsel_test002.. +Finding unused cells or wires in module \partsel_test003.. +Finding unused cells or wires in module \partsel_test004.. +Finding unused cells or wires in module \partsel_test005.. +Finding unused cells or wires in module \partsel_test006.. +Finding unused cells or wires in module \partsel_test007.. +Finding unused cells or wires in module \partsel_test008.. + +4.5.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module partsel_test001. +Optimizing module partsel_test002. +Optimizing module partsel_test003. +Optimizing module partsel_test004. +Optimizing module partsel_test005. +Optimizing module partsel_test006. +Optimizing module partsel_test007. +Optimizing module partsel_test008. + +4.5.16. Finished OPT passes. (There is nothing left to do.) + +4.6. Executing FSM pass (extract and optimize FSM). + +4.6.1. Executing FSM_DETECT pass (finding FSMs in design). + +4.6.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +4.6.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.6.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \partsel_test001.. +Finding unused cells or wires in module \partsel_test002.. +Finding unused cells or wires in module \partsel_test003.. +Finding unused cells or wires in module \partsel_test004.. +Finding unused cells or wires in module \partsel_test005.. +Finding unused cells or wires in module \partsel_test006.. +Finding unused cells or wires in module \partsel_test007.. +Finding unused cells or wires in module \partsel_test008.. + +4.6.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.6.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +4.6.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +4.6.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +4.7. Executing OPT pass (performing simple optimizations). + +4.7.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module partsel_test001. +Optimizing module partsel_test002. +Optimizing module partsel_test003. +Optimizing module partsel_test004. +Optimizing module partsel_test005. +Optimizing module partsel_test006. +Optimizing module partsel_test007. +Optimizing module partsel_test008. + +4.7.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\partsel_test001'. +Finding identical cells in module `\partsel_test002'. +Finding identical cells in module `\partsel_test003'. +Finding identical cells in module `\partsel_test004'. +Finding identical cells in module `\partsel_test005'. +Finding identical cells in module `\partsel_test006'. +Finding identical cells in module `\partsel_test007'. +Finding identical cells in module `\partsel_test008'. +Removed a total of 0 cells. + +4.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \partsel_test001.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \partsel_test002.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \partsel_test003.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \partsel_test004.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \partsel_test005.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \partsel_test006.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \partsel_test007.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \partsel_test008.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + + +4.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \partsel_test001. + Optimizing cells in module \partsel_test002. + Optimizing cells in module \partsel_test003. + Optimizing cells in module \partsel_test004. + Optimizing cells in module \partsel_test005. + Optimizing cells in module \partsel_test006. + Optimizing cells in module \partsel_test007. + Optimizing cells in module \partsel_test008. +Performed a total of 0 changes. + +4.7.5. Executing OPT_MERGE pass (detect identical cells). diff --git a/tests/simple_abc9/process.err b/tests/simple_abc9/process.err new file mode 100644 index 00000000000..41753633862 --- /dev/null +++ b/tests/simple_abc9/process.err @@ -0,0 +1,1019 @@ ++ body ++ cd process.out +++ basename process.v ++ fn=process.v +++ basename process ++ bn=process ++ refext=v ++ rm -f process_ref.fir ++ [[ v == \v ]] ++ egrep -v '^\s*`timescale' ../process.v +egrep: warning: egrep is obsolescent; using grep -E ++ '[' '!' -f ../process_tb.v ']' ++ /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../yosys -f 'verilog -noblackbox -specify -D_AUTOTB' -b 'test_autotb -n 300' -o process_tb.v process_ref.v + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2024 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) + +-- Parsing `process_ref.v' using frontend `verilog -noblackbox -specify -D_AUTOTB' -- + +1. Executing Verilog-2005 frontend: process_ref.v +Parsing Verilog input from `process_ref.v' to AST representation. +Generating RTLIL representation for module `\blocking_cond'. +Generating RTLIL representation for module `\uut'. +Generating RTLIL representation for module `\uart'. +Successfully finished Verilog frontend. + +-- Writing to `process_tb.v' using backend `test_autotb -n 300' -- + +2. Executing TEST_AUTOTB backend (auto-generate pseudo-random test benches). +Generating test bench for module `\uart'. +Generating test bench for module `\uut'. +Generating test bench for module `\blocking_cond'. + +End of script. Logfile hash: f0ba7b30c2, CPU: user 0.00s system 0.00s, MEM: 13.98 MB peak +Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) +Time spent: 90% 1x read_verilog (0 sec), 9% 1x test_autotb (0 sec) ++ false ++ compile_and_run process_tb_ref process_out_ref process_tb.v process_ref.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simlib.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simcells.v ++ exe=process_tb_ref ++ output=process_out_ref ++ shift 2 ++ '[' v == sv ']' ++ language_gen=-g2005 ++ false ++ false ++ iverilog -g2005 '-Doutfile="process_out_ref"' -s testbench -o process_tb_ref process_tb.v process_ref.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simlib.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simcells.v ++ vvp -n process_tb_ref +process_tb.v:291: $finish called at 361800 (1s) ++ false ++ test_count=0 ++ '[' 'verilog -noblackbox -specify' = verific -o 'verilog -noblackbox -specify' = verific_gates ']' ++ '[' -n '' ']' ++ '[' -n ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' ']' ++ test_passes -f 'verilog -noblackbox -specify ' -p ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' process_ref.v ++ /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../yosys -b 'verilog -noattr -noexpr -siminit' -o process_syn0.v -f 'verilog -noblackbox -specify ' -p ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' process_ref.v + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2024 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) + +-- Parsing `process_ref.v' using frontend `verilog -noblackbox -specify ' -- + +1. Executing Verilog-2005 frontend: process_ref.v +Parsing Verilog input from `process_ref.v' to AST representation. +Generating RTLIL representation for module `\blocking_cond'. +Generating RTLIL representation for module `\uut'. +Generating RTLIL representation for module `\uart'. +Successfully finished Verilog frontend. + +-- Running command ` read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' -- + +2. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v' to AST representation. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +3. Executing HIERARCHY pass (managing design hierarchy). + +4. Executing SYNTH pass. + +4.1. Executing PROC pass (convert processes to netlists). + +4.1.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 1 empty switch in `\blocking_cond.$proc$process_ref.v:8$1'. +Cleaned up 1 empty switch. + +4.1.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$process_ref.v:70$11 in module uart. +Marked 5 switch rules as full_case in process $proc$process_ref.v:26$2 in module uut. +Removed a total of 0 dead cases. + +4.1.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 4 assignments to connections. + +4.1.4. Executing PROC_INIT pass (extract init attributes). + +4.1.5. Executing PROC_ARST pass (detect async resets in processes). +Found async reset \arst in `\uut.$proc$process_ref.v:26$2'. + +4.1.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +4.1.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\uart.$proc$process_ref.v:70$11'. + 1/2: $0\tx_cnt[3:0] + 2/2: $0\tx_empty[0:0] +Creating decoders for process `\uut.$proc$process_ref.v:26$2'. + 1/5: $5\out1[3:0] + 2/5: $4\out1[3:0] + 3/5: $3\out1[3:0] + 4/5: $2\out1[3:0] + 5/5: $1\out1[3:0] +Creating decoders for process `\blocking_cond.$proc$process_ref.v:8$1'. + +4.1.8. Executing PROC_DLATCH pass (convert process syncs to latches). +No latch inferred for signal `\blocking_cond.\out' from process `\blocking_cond.$proc$process_ref.v:8$1'. +No latch inferred for signal `\blocking_cond.\tmp' from process `\blocking_cond.$proc$process_ref.v:8$1'. + +4.1.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\uart.\tx_empty' using process `\uart.$proc$process_ref.v:70$11'. + created $dff cell `$procdff$47' with positive edge clock. +Creating register for signal `\uart.\tx_cnt' using process `\uart.$proc$process_ref.v:70$11'. + created $dff cell `$procdff$48' with positive edge clock. +Creating register for signal `\uut.\out1' using process `\uut.$proc$process_ref.v:26$2'. + created $adff cell `$procdff$51' with positive edge clock and positive level reset. + +4.1.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +4.1.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 3 empty switches in `\uart.$proc$process_ref.v:70$11'. +Removing empty process `uart.$proc$process_ref.v:70$11'. +Found and cleaned up 4 empty switches in `\uut.$proc$process_ref.v:26$2'. +Removing empty process `uut.$proc$process_ref.v:26$2'. +Removing empty process `blocking_cond.$proc$process_ref.v:8$1'. +Cleaned up 7 empty switches. + +4.1.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module uart. + +Optimizing module uut. + +Optimizing module blocking_cond. + +4.2. Executing OPT_EXPR pass (perform const folding). +Optimizing module uart. +Optimizing module uut. +Optimizing module blocking_cond. + +4.3. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \uart.. +Finding unused cells or wires in module \uut.. +Finding unused cells or wires in module \blocking_cond.. +Removed 1 unused cells and 22 unused wires. + + +4.4. Executing CHECK pass (checking for obvious problems). +Checking module blocking_cond... +Checking module uart... +Checking module uut... +Found and reported 0 problems. + +4.5. Executing OPT pass (performing simple optimizations). + +4.5.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module blocking_cond. +Optimizing module uart. +Optimizing module uut. + +4.5.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\blocking_cond'. +Finding identical cells in module `\uart'. +Finding identical cells in module `\uut'. +Removed a total of 0 cells. + +4.5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \blocking_cond.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \uart.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \uut.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \blocking_cond. + Optimizing cells in module \uart. + Optimizing cells in module \uut. +Performed a total of 0 changes. + +4.5.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\blocking_cond'. +Finding identical cells in module `\uart'. +Finding identical cells in module `\uut'. +Removed a total of 0 cells. + +4.5.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.5.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \blocking_cond.. +Finding unused cells or wires in module \uart.. +Finding unused cells or wires in module \uut.. + +4.5.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module blocking_cond. +Optimizing module uart. +Optimizing module uut. + +4.5.9. Finished OPT passes. (There is nothing left to do.) + +4.6. Executing FSM pass (extract and optimize FSM). + +4.6.1. Executing FSM_DETECT pass (finding FSMs in design). + +4.6.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +4.6.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.6.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \blocking_cond.. +Finding unused cells or wires in module \uart.. +Finding unused cells or wires in module \uut.. + +4.6.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.6.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +4.6.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +4.6.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +4.7. Executing OPT pass (performing simple optimizations). + +4.7.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module blocking_cond. +Optimizing module uart. +Optimizing module uut. + +4.7.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\blocking_cond'. +Finding identical cells in module `\uart'. +Finding identical cells in module `\uut'. +Removed a total of 0 cells. + +4.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \blocking_cond.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \uart.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \uut.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \blocking_cond. + Optimizing cells in module \uart. + Optimizing cells in module \uut. +Performed a total of 0 changes. + +4.7.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\blocking_cond'. +Finding identical cells in module `\uart'. +Finding identical cells in module `\uut'. +Removed a total of 0 cells. + +4.7.6. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $procdff$48 ($dff) from module uart (D = $procmux$14_Y, Q = \tx_cnt, rval = 4'0000). +Adding EN signal on $auto$ff.cc:266:slice$54 ($sdff) from module uart (D = $add$process_ref.v:79$13_Y [3:0], Q = \tx_cnt). +Adding SRST signal on $procdff$47 ($dff) from module uart (D = $procmux$19_Y, Q = \tx_empty, rval = 1'1). +Adding EN signal on $auto$ff.cc:266:slice$56 ($sdff) from module uart (D = 1'0, Q = \tx_empty). + +4.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \blocking_cond.. +Finding unused cells or wires in module \uart.. +Finding unused cells or wires in module \uut.. +Removed 4 unused cells and 4 unused wires. + + +4.7.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module blocking_cond. +Optimizing module uart. +Optimizing module uut. + +4.7.9. Rerunning OPT passes. (Maybe there is more to do..) + +4.7.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \blocking_cond.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \uart.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \uut.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.7.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \blocking_cond. + Optimizing cells in module \uart. + Optimizing cells in module \uut. +Performed a total of 0 changes. + +4.7.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\blocking_cond'. +Finding identical cells in module `\uart'. +Finding identical cells in module `\uut'. +Removed a total of 0 cells. + +4.7.13. Executing OPT_DFF pass (perform DFF optimizations). + +4.7.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \blocking_cond.. +Finding unused cells or wires in module \uart.. +Finding unused cells or wires in module \uut.. + +4.7.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module blocking_cond. +Optimizing module uart. +Optimizing module uut. + +4.7.16. Finished OPT passes. (There is nothing left to do.) + +4.8. Executing WREDUCE pass (reducing word size of cells). +Removed top 31 bits (of 32) from port B of cell uart.$add$process_ref.v:79$13 ($add). +Removed top 28 bits (of 32) from port Y of cell uart.$add$process_ref.v:79$13 ($add). +Removed top 28 bits (of 32) from wire uart.$add$process_ref.v:79$13_Y. +Removed top 28 bits (of 32) from port B of cell uut.$add$process_ref.v:33$3 ($add). +Removed top 28 bits (of 32) from port Y of cell uut.$add$process_ref.v:33$3 ($add). +Removed top 28 bits (of 32) from port B of cell uut.$add$process_ref.v:35$4 ($add). +Removed top 28 bits (of 32) from port Y of cell uut.$add$process_ref.v:35$4 ($add). +Removed top 30 bits (of 32) from port B of cell uut.$add$process_ref.v:38$5 ($add). +Removed top 28 bits (of 32) from port Y of cell uut.$add$process_ref.v:38$5 ($add). +Removed top 31 bits (of 32) from port B of cell uut.$add$process_ref.v:39$6 ($add). +Removed top 28 bits (of 32) from port Y of cell uut.$add$process_ref.v:39$6 ($add). +Removed top 28 bits (of 32) from port B of cell uut.$add$process_ref.v:43$7 ($add). +Removed top 28 bits (of 32) from port Y of cell uut.$add$process_ref.v:43$7 ($add). +Removed top 28 bits (of 32) from port B of cell uut.$add$process_ref.v:47$8 ($add). +Removed top 28 bits (of 32) from port Y of cell uut.$add$process_ref.v:47$8 ($add). +Removed top 28 bits (of 32) from port B of cell uut.$add$process_ref.v:51$10 ($add). +Removed top 28 bits (of 32) from port Y of cell uut.$add$process_ref.v:51$10 ($add). +Removed top 1 bits (of 2) from port B of cell uut.$procmux$40_CMP0 ($eq). +Removed top 28 bits (of 32) from wire uut.$add$process_ref.v:33$3_Y. +Removed top 28 bits (of 32) from wire uut.$add$process_ref.v:38$5_Y. +Removed top 28 bits (of 32) from wire uut.$add$process_ref.v:43$7_Y. + +4.9. Executing PEEPOPT pass (run peephole optimizers). + +4.10. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \blocking_cond.. +Finding unused cells or wires in module \uart.. +Finding unused cells or wires in module \uut.. +Removed 0 unused cells and 5 unused wires. + + +4.11. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module blocking_cond: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module uart: + creating $macc model for $add$process_ref.v:79$13 ($add). + creating $alu model for $macc $add$process_ref.v:79$13. + creating $alu cell for $add$process_ref.v:79$13: $auto$alumacc.cc:485:replace_alu$62 + created 1 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module uut: + creating $macc model for $add$process_ref.v:33$3 ($add). + creating $macc model for $add$process_ref.v:35$4 ($add). + creating $macc model for $add$process_ref.v:38$5 ($add). + creating $macc model for $add$process_ref.v:39$6 ($add). + creating $macc model for $add$process_ref.v:43$7 ($add). + creating $macc model for $add$process_ref.v:47$8 ($add). + creating $macc model for $add$process_ref.v:51$10 ($add). + merging $macc model for $add$process_ref.v:38$5 into $add$process_ref.v:39$6. + creating $alu model for $macc $add$process_ref.v:47$8. + creating $alu model for $macc $add$process_ref.v:43$7. + creating $alu model for $macc $add$process_ref.v:39$6. + creating $alu model for $macc $add$process_ref.v:51$10. + creating $alu model for $macc $add$process_ref.v:35$4. + creating $alu model for $macc $add$process_ref.v:33$3. + creating $alu cell for $add$process_ref.v:33$3: $auto$alumacc.cc:485:replace_alu$65 + creating $alu cell for $add$process_ref.v:35$4: $auto$alumacc.cc:485:replace_alu$68 + creating $alu cell for $add$process_ref.v:51$10: $auto$alumacc.cc:485:replace_alu$71 + creating $alu cell for $add$process_ref.v:39$6: $auto$alumacc.cc:485:replace_alu$74 + creating $alu cell for $add$process_ref.v:43$7: $auto$alumacc.cc:485:replace_alu$77 + creating $alu cell for $add$process_ref.v:47$8: $auto$alumacc.cc:485:replace_alu$80 + created 6 $alu and 0 $macc cells. + +4.12. Executing SHARE pass (SAT-based resource sharing). + +4.13. Executing OPT pass (performing simple optimizations). + +4.13.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module blocking_cond. +Optimizing module uart. +Optimizing module uut. + +4.13.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\blocking_cond'. +Finding identical cells in module `\uart'. +Finding identical cells in module `\uut'. +Removed a total of 0 cells. + +4.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \blocking_cond.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \uart.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \uut.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \blocking_cond. + Optimizing cells in module \uart. + Optimizing cells in module \uut. +Performed a total of 0 changes. + +4.13.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\blocking_cond'. +Finding identical cells in module `\uart'. +Finding identical cells in module `\uut'. +Removed a total of 0 cells. + +4.13.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \blocking_cond.. +Finding unused cells or wires in module \uart.. +Finding unused cells or wires in module \uut.. +Removed 1 unused cells and 1 unused wires. + + +4.13.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module blocking_cond. +Optimizing module uart. +Optimizing module uut. + +4.13.9. Rerunning OPT passes. (Maybe there is more to do..) + +4.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \blocking_cond.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \uart.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \uut.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \blocking_cond. + Optimizing cells in module \uart. + Optimizing cells in module \uut. +Performed a total of 0 changes. + +4.13.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\blocking_cond'. +Finding identical cells in module `\uart'. +Finding identical cells in module `\uut'. +Removed a total of 0 cells. + +4.13.13. Executing OPT_DFF pass (perform DFF optimizations). + +4.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \blocking_cond.. +Finding unused cells or wires in module \uart.. +Finding unused cells or wires in module \uut.. + +4.13.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module blocking_cond. +Optimizing module uart. +Optimizing module uut. + +4.13.16. Finished OPT passes. (There is nothing left to do.) + +4.14. Executing MEMORY pass. + +4.14.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +4.14.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +4.14.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + +4.14.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +4.14.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). + +4.14.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \blocking_cond.. +Finding unused cells or wires in module \uart.. +Finding unused cells or wires in module \uut.. + +4.14.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +4.14.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +4.14.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \blocking_cond.. +Finding unused cells or wires in module \uart.. +Finding unused cells or wires in module \uut.. + +4.14.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +4.15. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \blocking_cond.. +Finding unused cells or wires in module \uart.. +Finding unused cells or wires in module \uut.. + +5. Executing OPT pass (performing simple optimizations). + +5.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module blocking_cond. +Optimizing module uart. +Optimizing module uut. + + +5.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\blocking_cond'. +Finding identical cells in module `\uart'. +Finding identical cells in module `\uut'. +Removed a total of 0 cells. + +5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \blocking_cond.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \uart.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \uut.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \blocking_cond. + Optimizing cells in module \uart. + Optimizing cells in module \uut. + Consolidated identical input bits for $pmux cell $procmux$26: + Old ports: A=$add$process_ref.v:47$8_Y [3:0], B={ $add$process_ref.v:43$7_Y $4\out1[3:0] }, Y=$procmux$26_Y + New ports: A=$add$process_ref.v:47$8_Y [3:1], B={ $add$process_ref.v:43$7_Y [3] $procmux$33_Y [2:1] $procmux$33_Y [3:1] }, Y=$procmux$26_Y [3:1] + New connections: $procmux$26_Y [0] = $procmux$33_Y [0] + Optimizing cells in module \uut. +Performed a total of 1 changes. + +5.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\blocking_cond'. +Finding identical cells in module `\uart'. +Finding identical cells in module `\uut'. +Removed a total of 0 cells. + +5.6. Executing OPT_SHARE pass. + Found cells that share an operand and can be merged by moving the $pmux $procmux$39 in front of them: + $auto$alumacc.cc:485:replace_alu$68 + $auto$alumacc.cc:485:replace_alu$65 + +5.7. Executing OPT_DFF pass (perform DFF optimizations). + +5.8. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \blocking_cond.. +Finding unused cells or wires in module \uart.. +Finding unused cells or wires in module \uut.. +Removed 0 unused cells and 9 unused wires. + + +5.9. Executing OPT_EXPR pass (perform const folding). +Optimizing module blocking_cond. +Optimizing module uart. +Optimizing module uut. + + +5.10. Rerunning OPT passes. (Maybe there is more to do..) + +5.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \blocking_cond.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \uart.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \uut.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +5.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \blocking_cond. + Optimizing cells in module \uart. + Optimizing cells in module \uut. + Consolidated identical input bits for $mux cell $auto$opt_share.cc:246:merge_operators$84: + Old ports: A=4'1001, B=4'1101, Y=$auto$rtlil.cc:2630:Pmux$85 + New ports: A=1'0, B=1'1, Y=$auto$rtlil.cc:2630:Pmux$85 [2] + New connections: { $auto$rtlil.cc:2630:Pmux$85 [3] $auto$rtlil.cc:2630:Pmux$85 [1:0] } = 3'101 + New ctrl vector for $pmux cell $procmux$39: $auto$opt_reduce.cc:134:opt_pmux$89 + New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$88: { $procmux$41_CMP $procmux$40_CMP } + Optimizing cells in module \uut. +Performed a total of 3 changes. + +5.13. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\blocking_cond'. +Finding identical cells in module `\uart'. +Finding identical cells in module `\uut'. +Removed a total of 0 cells. + +5.14. Executing OPT_SHARE pass. + +5.15. Executing OPT_DFF pass (perform DFF optimizations). +Adding EN signal on $procdff$51 ($adff) from module uut (D = $auto$rtlil.cc:2493:Not$53 [0], Q = \out1 [0]). + +5.16. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \blocking_cond.. +Finding unused cells or wires in module \uart.. +Finding unused cells or wires in module \uut.. + +5.17. Executing OPT_EXPR pass (perform const folding). +Optimizing module blocking_cond. +Optimizing module uart. +Optimizing module uut. + + +5.18. Rerunning OPT passes. (Maybe there is more to do..) + +5.19. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \blocking_cond.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \uart.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \uut.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +5.20. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \blocking_cond. + Optimizing cells in module \uart. + Optimizing cells in module \uut. +Performed a total of 0 changes. + +5.21. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\blocking_cond'. +Finding identical cells in module `\uart'. +Finding identical cells in module `\uut'. +Removed a total of 0 cells. + +5.22. Executing OPT_SHARE pass. + +5.23. Executing OPT_DFF pass (perform DFF optimizations). + +5.24. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \blocking_cond.. +Finding unused cells or wires in module \uart.. +Finding unused cells or wires in module \uut.. +Removed 0 unused cells and 1 unused wires. + + +5.25. Executing OPT_EXPR pass (perform const folding). +Optimizing module blocking_cond. +Optimizing module uart. +Optimizing module uut. + +5.26. Rerunning OPT passes. (Maybe there is more to do..) + +5.27. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \blocking_cond.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \uart.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \uut.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +5.28. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \blocking_cond. + Optimizing cells in module \uart. + Optimizing cells in module \uut. +Performed a total of 0 changes. + +5.29. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\blocking_cond'. +Finding identical cells in module `\uart'. +Finding identical cells in module `\uut'. +Removed a total of 0 cells. + +5.30. Executing OPT_SHARE pass. + +5.31. Executing OPT_DFF pass (perform DFF optimizations). + +5.32. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \blocking_cond.. +Finding unused cells or wires in module \uart.. +Finding unused cells or wires in module \uut.. + +5.33. Executing OPT_EXPR pass (perform const folding). +Optimizing module blocking_cond. +Optimizing module uart. +Optimizing module uut. + +5.34. Finished OPT passes. (There is nothing left to do.) + +6. Executing TECHMAP pass (map to technology primitives). + +6.1. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/techmap.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +6.2. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $not. +Using template $paramod$740b056ede97228d3eae64ea2fdc81f0a33e0fe7\_90_alu for cells of type $alu. +Using extmapper simplemap for cells of type $reduce_or. +Using template $paramod$78e969f2586efcf3a5b0b0440bcca0db83d5cca2\_90_alu for cells of type $alu. +Using template $paramod$fc972a7a46956c1788f3cb5257b53c8f1df2d0cc\_90_alu for cells of type $alu. +Using template $paramod$f85408ed1aa3d09e465edae8a7bf590332ae9f7b\_90_alu for cells of type $alu. +Using extmapper simplemap for cells of type $adffe. +Using extmapper simplemap for cells of type $adff. +Using extmapper simplemap for cells of type $logic_not. +Using template $paramod$32e7c4d6f92ff4337599ece53082d2e88a82a9f2\_90_pmux for cells of type $pmux. +Using extmapper simplemap for cells of type $eq. +Using extmapper simplemap for cells of type $mux. +Using extmapper simplemap for cells of type $xor. +Using extmapper simplemap for cells of type $and. +Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu. +Using extmapper simplemap for cells of type $pos. +Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu. +Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000001 for cells of type $lcu. +Using extmapper simplemap for cells of type $or. +Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu. +Using extmapper simplemap for cells of type $sdffe. +No more expansions possible. + + +7. Executing ABC9 pass. + +7.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.2. Executing ABC9_OPS pass (helper functions for ABC9). + +7.3. Executing SCC pass (detecting logic loops). +Found 0 SCCs in module blocking_cond. +Found 0 SCCs in module uart. +Found 0 SCCs in module uut. +Found 0 SCCs. + +7.4. Executing ABC9_OPS pass (helper functions for ABC9). + +7.5. Executing PROC pass (convert processes to netlists). + +7.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +7.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +7.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 0 assignments to connections. + +7.5.4. Executing PROC_INIT pass (extract init attributes). + +7.5.5. Executing PROC_ARST pass (detect async resets in processes). + +7.5.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + +7.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). + +7.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +7.5.9. Executing PROC_DFF pass (convert process syncs to FFs). + +7.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +7.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +7.5.12. Executing OPT_EXPR pass (perform const folding). + +7.6. Executing TECHMAP pass (map to technology primitives). + +7.6.1. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/techmap.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +7.6.2. Continuing TECHMAP pass. +No more expansions possible. + + +7.7. Executing OPT pass (performing simple optimizations). + +7.7.1. Executing OPT_EXPR pass (perform const folding). + +7.7.2. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +7.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Removed 0 multiplexer ports. + +7.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +Performed a total of 0 changes. + +7.7.5. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +7.7.6. Executing OPT_DFF pass (perform DFF optimizations). + +7.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). + +7.7.8. Executing OPT_EXPR pass (perform const folding). + +7.7.9. Finished OPT passes. (There is nothing left to do.) + +7.8. Executing TECHMAP pass (map to technology primitives). + +7.8.1. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/abc9_map.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/abc9_map.v' to AST representation. +Successfully finished Verilog frontend. + +7.8.2. Continuing TECHMAP pass. +No more expansions possible. + + +7.9. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v' to AST representation. +Replacing existing blackbox module `$__ABC9_DELAY' at /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v:2.1-7.10. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Replacing existing blackbox module `$__ABC9_SCC_BREAKER' at /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v:9.1-11.10. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Replacing existing module `$__DFF_N__$abc9_flop' at /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v:14.1-20.10. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Replacing existing module `$__DFF_P__$abc9_flop' at /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v:23.1-29.10. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +7.10. Executing ABC9_OPS pass (helper functions for ABC9). + +7.11. Executing ABC9_OPS pass (helper functions for ABC9). + + +7.12. Executing AIGMAP pass (map logic to AIG). +Module uart: replaced 18 cells with 111 new cells, skipped 19 cells. + replaced 3 cell types: + 5 $_OR_ + 9 $_XOR_ + 4 $_MUX_ + not replaced 4 cell types: + 4 $_NOT_ + 10 $_AND_ + 4 $_SDFFE_PP0N_ + 1 $_SDFFE_PP1P_ +Module uut: replaced 100 cells with 613 new cells, skipped 67 cells. + replaced 3 cell types: + 29 $_OR_ + 41 $_XOR_ + 30 $_MUX_ + not replaced 4 cell types: + 23 $_NOT_ + 40 $_AND_ + 3 $_DFF_PP0_ + 1 $_DFFE_PP0P_ + +7.12.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.12.2. Executing XAIGER backend. + +Extracted 0 AND gates and 4 wires from module `blocking_cond' to a netlist network with 1 inputs and 1 outputs. + +7.12.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.12.4. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_lut /lutdefs.txt +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 1/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f +ABC: + &ps +ABC: /input : i/o = 1/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 0 bb = 0 +ABC: + &if -v +ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 136. Set = 564. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.00 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 1/ 1 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 0 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + time +ABC: elapse: 0.00 seconds, total: 0.00 seconds + +7.12.5. Executing AIGER frontend. + +Removed 0 unused cells and 1 unused wires. + +7.12.6. Executing ABC9_OPS pass (helper functions for ABC9). +ABC RESULTS: input signals: 1 +ABC RESULTS: output signals: 1 +Removing temp directory. + +7.12.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.12.2. Executing XAIGER backend. + +Extracted 54 AND gates and 120 wires from module `uart' to a netlist network with 8 inputs and 9 outputs. + +7.12.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.12.4. Executing ABC9. diff --git a/tests/simple_abc9/realexpr.err b/tests/simple_abc9/realexpr.err new file mode 100644 index 00000000000..af9b19e971e --- /dev/null +++ b/tests/simple_abc9/realexpr.err @@ -0,0 +1,779 @@ ++ body ++ cd realexpr.out +++ basename realexpr.v ++ fn=realexpr.v +++ basename realexpr ++ bn=realexpr ++ refext=v ++ rm -f realexpr_ref.fir ++ [[ v == \v ]] ++ egrep -v '^\s*`timescale' ../realexpr.v +egrep: warning: egrep is obsolescent; using grep -E ++ '[' '!' -f ../realexpr_tb.v ']' ++ /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../yosys -f 'verilog -noblackbox -specify -D_AUTOTB' -b 'test_autotb -n 300' -o realexpr_tb.v realexpr_ref.v + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2024 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) + +-- Parsing `realexpr_ref.v' using frontend `verilog -noblackbox -specify -D_AUTOTB' -- + +1. Executing Verilog-2005 frontend: realexpr_ref.v +Parsing Verilog input from `realexpr_ref.v' to AST representation. +Generating RTLIL representation for module `\demo_001'. +realexpr_ref.v:4: Warning: converting real value 1.234500e+02 to binary 8'01111011. +realexpr_ref.v:9: Warning: converting real value 1.232000e+02 to binary 123. +realexpr_ref.v:10: Warning: converting real value 1.236500e+02 to binary 124. +realexpr_ref.v:11: Warning: converting real value 1.232000e+02 to binary 123. +realexpr_ref.v:12: Warning: converting real value 1.236500e+02 to binary 124. +Generating RTLIL representation for module `\demo_002'. +realexpr_ref.v:19: Warning: converting real value 4.294967e+09 to binary 64'0000000000000000000000000000000011111111111111111111111111111111. +realexpr_ref.v:20: Warning: converting real value -1.000000e+00 to binary 64'1111111111111111111111111111111111111111111111111111111111111111. +Generating RTLIL representation for module `\demo_003'. +Generating RTLIL representation for module `\demo_004'. +realexpr_ref.v:31: Warning: Replacing floating point parameter demo_real.$1 = 1.000000 with string. +Successfully finished Verilog frontend. + +-- Writing to `realexpr_tb.v' using backend `test_autotb -n 300' -- + +2. Executing TEST_AUTOTB backend (auto-generate pseudo-random test benches). +Generating test bench for module `\demo_004'. +Generating test bench for module `\demo_003'. +Generating test bench for module `\demo_002'. +Generating test bench for module `\demo_001'. + +Warnings: 6 unique messages, 8 total +End of script. Logfile hash: 5e7c7a8473, CPU: user 0.00s system 0.00s, MEM: 14.20 MB peak +Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) +Time spent: 86% 1x read_verilog (0 sec), 13% 1x test_autotb (0 sec) ++ false ++ compile_and_run realexpr_tb_ref realexpr_out_ref realexpr_tb.v realexpr_ref.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simlib.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simcells.v ++ exe=realexpr_tb_ref ++ output=realexpr_out_ref ++ shift 2 ++ '[' v == sv ']' ++ language_gen=-g2005 ++ false ++ false ++ iverilog -g2005 '-Doutfile="realexpr_out_ref"' -s testbench -o realexpr_tb_ref realexpr_tb.v realexpr_ref.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simlib.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simcells.v ++ vvp -n realexpr_tb_ref +realexpr_tb.v:280: $finish called at 360000 (1s) ++ false ++ test_count=0 ++ '[' 'verilog -noblackbox -specify' = verific -o 'verilog -noblackbox -specify' = verific_gates ']' ++ '[' -n '' ']' ++ '[' -n ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' ']' ++ test_passes -f 'verilog -noblackbox -specify ' -p ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' realexpr_ref.v ++ /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../yosys -b 'verilog -noattr -noexpr -siminit' -o realexpr_syn0.v -f 'verilog -noblackbox -specify ' -p ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' realexpr_ref.v + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2024 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) + +-- Parsing `realexpr_ref.v' using frontend `verilog -noblackbox -specify ' -- + +1. Executing Verilog-2005 frontend: realexpr_ref.v +Parsing Verilog input from `realexpr_ref.v' to AST representation. +Generating RTLIL representation for module `\demo_001'. +realexpr_ref.v:4: Warning: converting real value 1.234500e+02 to binary 8'01111011. +realexpr_ref.v:9: Warning: converting real value 1.232000e+02 to binary 123. +realexpr_ref.v:10: Warning: converting real value 1.236500e+02 to binary 124. +realexpr_ref.v:11: Warning: converting real value 1.232000e+02 to binary 123. +realexpr_ref.v:12: Warning: converting real value 1.236500e+02 to binary 124. +Generating RTLIL representation for module `\demo_002'. +realexpr_ref.v:19: Warning: converting real value 4.294967e+09 to binary 64'0000000000000000000000000000000011111111111111111111111111111111. +realexpr_ref.v:20: Warning: converting real value -1.000000e+00 to binary 64'1111111111111111111111111111111111111111111111111111111111111111. +Generating RTLIL representation for module `\demo_003'. +Generating RTLIL representation for module `\demo_004'. +realexpr_ref.v:31: Warning: Replacing floating point parameter demo_real.$1 = 1.000000 with string. +Successfully finished Verilog frontend. + +-- Running command ` read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' -- + +2. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v' to AST representation. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +3. Executing HIERARCHY pass (managing design hierarchy). +Parameter 1 (\p) = 1 + +3.1. Executing AST frontend in derive mode using pre-parsed AST for module `\demo_003'. +Parameter 1 (\p) = 1 +Generating RTLIL representation for module `$paramod\demo_003\p=s32'00000000000000000000000000000001'. +Parameter 1 (\p) = 64'0011000100101110001100000011000000110000001100000011000000110000 + +3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\demo_003'. +Parameter 1 (\p) = 64'0011000100101110001100000011000000110000001100000011000000110000 +Generating RTLIL representation for module `$paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003'. +Mapping positional arguments of cell demo_004.demo_int ($paramod\demo_003\p=s32'00000000000000000000000000000001). +Mapping positional arguments of cell demo_004.demo_real ($paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003). + +4. Executing SYNTH pass. + +4.1. Executing PROC pass (convert processes to netlists). + +4.1.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +4.1.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +4.1.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 0 assignments to connections. + +4.1.4. Executing PROC_INIT pass (extract init attributes). + +4.1.5. Executing PROC_ARST pass (detect async resets in processes). + +4.1.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + +4.1.7. Executing PROC_MUX pass (convert decision trees to multiplexers). + +4.1.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +4.1.9. Executing PROC_DFF pass (convert process syncs to FFs). + +4.1.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +4.1.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +4.1.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003. +Optimizing module $paramod\demo_003\p=s32'00000000000000000000000000000001. +Optimizing module demo_004. +Optimizing module demo_003. +Optimizing module demo_002. +Optimizing module demo_001. + +4.2. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003. +Optimizing module $paramod\demo_003\p=s32'00000000000000000000000000000001. +Optimizing module demo_004. +Optimizing module demo_003. +Optimizing module demo_002. +Optimizing module demo_001. + +4.3. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003.. +Finding unused cells or wires in module $paramod\demo_003\p=s32'00000000000000000000000000000001.. +Finding unused cells or wires in module \demo_004.. +Finding unused cells or wires in module \demo_003.. +Finding unused cells or wires in module \demo_002.. +Finding unused cells or wires in module \demo_001.. + +4.4. Executing CHECK pass (checking for obvious problems). +Checking module $paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003... +Checking module $paramod\demo_003\p=s32'00000000000000000000000000000001... +Checking module demo_001... +Checking module demo_002... +Checking module demo_003... +Checking module demo_004... +Found and reported 0 problems. + +4.5. Executing OPT pass (performing simple optimizations). + +4.5.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003. +Optimizing module $paramod\demo_003\p=s32'00000000000000000000000000000001. +Optimizing module demo_001. +Optimizing module demo_002. +Optimizing module demo_003. +Optimizing module demo_004. + +4.5.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `$paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003'. +Finding identical cells in module `$paramod\demo_003\p=s32'00000000000000000000000000000001'. +Finding identical cells in module `\demo_001'. +Finding identical cells in module `\demo_002'. +Finding identical cells in module `\demo_003'. +Finding identical cells in module `\demo_004'. +Removed a total of 0 cells. + +4.5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module $paramod\demo_003\p=s32'00000000000000000000000000000001.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \demo_001.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \demo_002.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \demo_003.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \demo_004.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module $paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003. + Optimizing cells in module $paramod\demo_003\p=s32'00000000000000000000000000000001. + Optimizing cells in module \demo_001. + Optimizing cells in module \demo_002. + Optimizing cells in module \demo_003. + Optimizing cells in module \demo_004. +Performed a total of 0 changes. + +4.5.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `$paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003'. +Finding identical cells in module `$paramod\demo_003\p=s32'00000000000000000000000000000001'. +Finding identical cells in module `\demo_001'. +Finding identical cells in module `\demo_002'. +Finding identical cells in module `\demo_003'. +Finding identical cells in module `\demo_004'. +Removed a total of 0 cells. + +4.5.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.5.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003.. +Finding unused cells or wires in module $paramod\demo_003\p=s32'00000000000000000000000000000001.. +Finding unused cells or wires in module \demo_001.. +Finding unused cells or wires in module \demo_002.. +Finding unused cells or wires in module \demo_003.. +Finding unused cells or wires in module \demo_004.. + +4.5.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003. +Optimizing module $paramod\demo_003\p=s32'00000000000000000000000000000001. +Optimizing module demo_001. +Optimizing module demo_002. +Optimizing module demo_003. +Optimizing module demo_004. + +4.5.9. Finished OPT passes. (There is nothing left to do.) + +4.6. Executing FSM pass (extract and optimize FSM). + +4.6.1. Executing FSM_DETECT pass (finding FSMs in design). + +4.6.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +4.6.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.6.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003.. +Finding unused cells or wires in module $paramod\demo_003\p=s32'00000000000000000000000000000001.. +Finding unused cells or wires in module \demo_001.. +Finding unused cells or wires in module \demo_002.. +Finding unused cells or wires in module \demo_003.. +Finding unused cells or wires in module \demo_004.. + +4.6.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.6.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +4.6.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +4.6.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +4.7. Executing OPT pass (performing simple optimizations). + +4.7.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003. +Optimizing module $paramod\demo_003\p=s32'00000000000000000000000000000001. +Optimizing module demo_001. +Optimizing module demo_002. +Optimizing module demo_003. +Optimizing module demo_004. + +4.7.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `$paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003'. +Finding identical cells in module `$paramod\demo_003\p=s32'00000000000000000000000000000001'. +Finding identical cells in module `\demo_001'. +Finding identical cells in module `\demo_002'. +Finding identical cells in module `\demo_003'. +Finding identical cells in module `\demo_004'. +Removed a total of 0 cells. + +4.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module $paramod\demo_003\p=s32'00000000000000000000000000000001.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \demo_001.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \demo_002.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \demo_003.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \demo_004.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module $paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003. + Optimizing cells in module $paramod\demo_003\p=s32'00000000000000000000000000000001. + Optimizing cells in module \demo_001. + Optimizing cells in module \demo_002. + Optimizing cells in module \demo_003. + Optimizing cells in module \demo_004. +Performed a total of 0 changes. + +4.7.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `$paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003'. +Finding identical cells in module `$paramod\demo_003\p=s32'00000000000000000000000000000001'. +Finding identical cells in module `\demo_001'. +Finding identical cells in module `\demo_002'. +Finding identical cells in module `\demo_003'. +Finding identical cells in module `\demo_004'. +Removed a total of 0 cells. + +4.7.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003.. +Finding unused cells or wires in module $paramod\demo_003\p=s32'00000000000000000000000000000001.. +Finding unused cells or wires in module \demo_001.. +Finding unused cells or wires in module \demo_002.. +Finding unused cells or wires in module \demo_003.. +Finding unused cells or wires in module \demo_004.. + +4.7.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003. +Optimizing module $paramod\demo_003\p=s32'00000000000000000000000000000001. +Optimizing module demo_001. +Optimizing module demo_002. +Optimizing module demo_003. +Optimizing module demo_004. + +4.7.9. Finished OPT passes. (There is nothing left to do.) + +4.8. Executing WREDUCE pass (reducing word size of cells). + +4.9. Executing PEEPOPT pass (run peephole optimizers). + +4.10. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003.. +Finding unused cells or wires in module $paramod\demo_003\p=s32'00000000000000000000000000000001.. +Finding unused cells or wires in module \demo_001.. +Finding unused cells or wires in module \demo_002.. +Finding unused cells or wires in module \demo_003.. +Finding unused cells or wires in module \demo_004.. + +4.11. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module $paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module $paramod\demo_003\p=s32'00000000000000000000000000000001: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module demo_001: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module demo_002: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module demo_003: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module demo_004: + created 0 $alu and 0 $macc cells. + +4.12. Executing SHARE pass (SAT-based resource sharing). + +4.13. Executing OPT pass (performing simple optimizations). + +4.13.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003. +Optimizing module $paramod\demo_003\p=s32'00000000000000000000000000000001. +Optimizing module demo_001. +Optimizing module demo_002. +Optimizing module demo_003. +Optimizing module demo_004. + +4.13.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `$paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003'. +Finding identical cells in module `$paramod\demo_003\p=s32'00000000000000000000000000000001'. +Finding identical cells in module `\demo_001'. +Finding identical cells in module `\demo_002'. +Finding identical cells in module `\demo_003'. +Finding identical cells in module `\demo_004'. +Removed a total of 0 cells. + +4.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module $paramod\demo_003\p=s32'00000000000000000000000000000001.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \demo_001.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \demo_002.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \demo_003.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \demo_004.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module $paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003. + Optimizing cells in module $paramod\demo_003\p=s32'00000000000000000000000000000001. + Optimizing cells in module \demo_001. + Optimizing cells in module \demo_002. + Optimizing cells in module \demo_003. + Optimizing cells in module \demo_004. +Performed a total of 0 changes. + +4.13.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `$paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003'. +Finding identical cells in module `$paramod\demo_003\p=s32'00000000000000000000000000000001'. +Finding identical cells in module `\demo_001'. +Finding identical cells in module `\demo_002'. +Finding identical cells in module `\demo_003'. +Finding identical cells in module `\demo_004'. +Removed a total of 0 cells. + +4.13.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003.. +Finding unused cells or wires in module $paramod\demo_003\p=s32'00000000000000000000000000000001.. +Finding unused cells or wires in module \demo_001.. +Finding unused cells or wires in module \demo_002.. +Finding unused cells or wires in module \demo_003.. +Finding unused cells or wires in module \demo_004.. + +4.13.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003. +Optimizing module $paramod\demo_003\p=s32'00000000000000000000000000000001. +Optimizing module demo_001. +Optimizing module demo_002. +Optimizing module demo_003. +Optimizing module demo_004. + +4.13.9. Finished OPT passes. (There is nothing left to do.) + +4.14. Executing MEMORY pass. + +4.14.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +4.14.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +4.14.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + +4.14.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +4.14.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). + +4.14.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003.. +Finding unused cells or wires in module $paramod\demo_003\p=s32'00000000000000000000000000000001.. +Finding unused cells or wires in module \demo_001.. +Finding unused cells or wires in module \demo_002.. +Finding unused cells or wires in module \demo_003.. +Finding unused cells or wires in module \demo_004.. + +4.14.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +4.14.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +4.14.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003.. +Finding unused cells or wires in module $paramod\demo_003\p=s32'00000000000000000000000000000001.. +Finding unused cells or wires in module \demo_001.. +Finding unused cells or wires in module \demo_002.. +Finding unused cells or wires in module \demo_003.. +Finding unused cells or wires in module \demo_004.. + +4.14.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +4.15. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003.. +Finding unused cells or wires in module $paramod\demo_003\p=s32'00000000000000000000000000000001.. +Finding unused cells or wires in module \demo_001.. +Finding unused cells or wires in module \demo_002.. +Finding unused cells or wires in module \demo_003.. +Finding unused cells or wires in module \demo_004.. + +5. Executing OPT pass (performing simple optimizations). + +5.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003. +Optimizing module $paramod\demo_003\p=s32'00000000000000000000000000000001. +Optimizing module demo_001. +Optimizing module demo_002. +Optimizing module demo_003. +Optimizing module demo_004. + +5.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `$paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003'. +Finding identical cells in module `$paramod\demo_003\p=s32'00000000000000000000000000000001'. +Finding identical cells in module `\demo_001'. +Finding identical cells in module `\demo_002'. +Finding identical cells in module `\demo_003'. +Finding identical cells in module `\demo_004'. +Removed a total of 0 cells. + +5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module $paramod\demo_003\p=s32'00000000000000000000000000000001.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \demo_001.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \demo_002.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \demo_003.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \demo_004.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module $paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003. + Optimizing cells in module $paramod\demo_003\p=s32'00000000000000000000000000000001. + Optimizing cells in module \demo_001. + Optimizing cells in module \demo_002. + Optimizing cells in module \demo_003. + Optimizing cells in module \demo_004. +Performed a total of 0 changes. + +5.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `$paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003'. +Finding identical cells in module `$paramod\demo_003\p=s32'00000000000000000000000000000001'. +Finding identical cells in module `\demo_001'. +Finding identical cells in module `\demo_002'. +Finding identical cells in module `\demo_003'. +Finding identical cells in module `\demo_004'. +Removed a total of 0 cells. + +5.6. Executing OPT_SHARE pass. + +5.7. Executing OPT_DFF pass (perform DFF optimizations). + +5.8. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003.. +Finding unused cells or wires in module $paramod\demo_003\p=s32'00000000000000000000000000000001.. +Finding unused cells or wires in module \demo_001.. +Finding unused cells or wires in module \demo_002.. +Finding unused cells or wires in module \demo_003.. +Finding unused cells or wires in module \demo_004.. + +5.9. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003. +Optimizing module $paramod\demo_003\p=s32'00000000000000000000000000000001. +Optimizing module demo_001. +Optimizing module demo_002. +Optimizing module demo_003. +Optimizing module demo_004. + +5.10. Finished OPT passes. (There is nothing left to do.) + +6. Executing TECHMAP pass (map to technology primitives). + +6.1. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/techmap.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +6.2. Continuing TECHMAP pass. +No more expansions possible. + + +7. Executing ABC9 pass. + +7.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.2. Executing ABC9_OPS pass (helper functions for ABC9). + +7.3. Executing SCC pass (detecting logic loops). +Found 0 SCCs in module $paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003. +Found 0 SCCs in module $paramod\demo_003\p=s32'00000000000000000000000000000001. +Found 0 SCCs in module demo_001. +Found 0 SCCs in module demo_002. +Found 0 SCCs in module demo_003. +Found 0 SCCs in module demo_004. +Found 0 SCCs. + +7.4. Executing ABC9_OPS pass (helper functions for ABC9). + +7.5. Executing PROC pass (convert processes to netlists). + +7.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +7.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +7.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 0 assignments to connections. + +7.5.4. Executing PROC_INIT pass (extract init attributes). + +7.5.5. Executing PROC_ARST pass (detect async resets in processes). + +7.5.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + +7.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). + +7.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +7.5.9. Executing PROC_DFF pass (convert process syncs to FFs). + +7.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +7.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +7.5.12. Executing OPT_EXPR pass (perform const folding). + +7.6. Executing TECHMAP pass (map to technology primitives). + +7.6.1. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/techmap.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +7.6.2. Continuing TECHMAP pass. +No more expansions possible. + + +7.7. Executing OPT pass (performing simple optimizations). + +7.7.1. Executing OPT_EXPR pass (perform const folding). + +7.7.2. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +7.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Removed 0 multiplexer ports. + +7.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +Performed a total of 0 changes. + +7.7.5. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +7.7.6. Executing OPT_DFF pass (perform DFF optimizations). + +7.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). + +7.7.8. Executing OPT_EXPR pass (perform const folding). + +7.7.9. Finished OPT passes. (There is nothing left to do.) + +7.8. Executing TECHMAP pass (map to technology primitives). + +7.8.1. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/abc9_map.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/abc9_map.v' to AST representation. +Successfully finished Verilog frontend. + +7.8.2. Continuing TECHMAP pass. +No more expansions possible. + + +7.9. Executing Verilog-2005 frontend: /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v +Parsing Verilog input from `/home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v' to AST representation. +Replacing existing blackbox module `$__ABC9_DELAY' at /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v:2.1-7.10. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Replacing existing blackbox module `$__ABC9_SCC_BREAKER' at /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v:9.1-11.10. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Replacing existing module `$__DFF_N__$abc9_flop' at /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v:14.1-20.10. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Replacing existing module `$__DFF_P__$abc9_flop' at /home/george/code_ee_temp/yosys/yosys3/share/abc9_model.v:23.1-29.10. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +7.10. Executing ABC9_OPS pass (helper functions for ABC9). + +7.11. Executing ABC9_OPS pass (helper functions for ABC9). + + +7.12. Executing AIGMAP pass (map logic to AIG). +Module demo_004: replaced 0 cells with 0 new cells, skipped 2 cells. + not replaced 2 cell types: + 1 $paramod\demo_003\p=s32'00000000000000000000000000000001 + 1 $paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003 + +7.12.1. Executing ABC9_OPS pass (helper functions for ABC9). + +7.12.2. Executing XAIGER backend. + +Extracted 0 AND gates and 4 wires from module `$paramod$9ba9697041a7ee0a7182557e576a5947aaca1a05\demo_003' to a netlist network with 0 inputs and 2 outputs. + +7.12.3. Executing ABC9_EXE pass (technology mapping using ABC9). + +7.12.4. Executing ABC9. diff --git a/tests/simple_abc9/repwhile.err b/tests/simple_abc9/repwhile.err new file mode 100644 index 00000000000..46bd8415c88 --- /dev/null +++ b/tests/simple_abc9/repwhile.err @@ -0,0 +1,609 @@ ++ body ++ cd repwhile.out +++ basename repwhile.v ++ fn=repwhile.v +++ basename repwhile ++ bn=repwhile ++ refext=v ++ rm -f repwhile_ref.fir ++ [[ v == \v ]] ++ egrep -v '^\s*`timescale' ../repwhile.v +egrep: warning: egrep is obsolescent; using grep -E ++ '[' '!' -f ../repwhile_tb.v ']' ++ /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../yosys -f 'verilog -noblackbox -specify -D_AUTOTB' -b 'test_autotb -n 300' -o repwhile_tb.v repwhile_ref.v + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2024 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) + +-- Parsing `repwhile_ref.v' using frontend `verilog -noblackbox -specify -D_AUTOTB' -- + +1. Executing Verilog-2005 frontend: repwhile_ref.v +Parsing Verilog input from `repwhile_ref.v' to AST representation. +Generating RTLIL representation for module `\repwhile_test001'. +Warning: wire '\mylog2$func$repwhile_ref.v:29$4.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$6.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$6.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$8.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$8.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$10.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$10.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$10.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$12.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$12.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$12.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$14.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$14.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$14.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$16.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$16.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$16.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$18.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$18.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$18.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$18.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$20.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$20.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$20.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$20.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$22.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$22.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$22.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$22.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$24.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$24.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$24.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$24.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$26.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$26.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$26.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$26.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$28.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$28.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$28.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$28.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$30.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$30.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$30.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$30.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$32.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$32.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$32.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$32.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$34.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$34.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$34.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$34.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$34.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$36.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$36.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$36.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$36.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$36.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$38.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$38.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$38.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$38.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$38.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$40.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$40.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$40.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$40.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$40.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$42.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$42.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$42.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$42.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$42.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$44.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$44.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$44.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$44.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$44.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$46.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$46.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$46.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$46.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$46.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$48.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$48.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$48.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$48.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$48.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$50.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$50.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$50.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$50.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$50.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$52.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$52.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$52.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$52.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$52.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$54.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$54.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$54.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$54.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$54.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$56.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$56.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$56.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$56.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$56.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$58.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$58.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$58.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$58.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$58.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$60.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$60.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$60.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$60.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$60.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$62.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$62.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$62.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$62.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$62.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$64.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$64.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$64.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$64.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$64.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$66.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$66.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$66.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$66.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$66.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$66.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$68.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$68.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$68.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$68.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$68.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$68.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$70.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$70.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$70.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$70.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$70.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$70.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$72.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$72.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$72.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$72.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$72.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$72.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$74.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$74.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$74.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$74.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$74.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$74.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$76.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$76.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$76.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$76.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$76.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$76.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$78.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$78.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$78.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$78.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$78.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$78.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$80.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$80.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$80.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$80.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$80.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$80.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$82.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$82.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$82.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$82.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$82.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$82.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$84.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$84.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$84.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$84.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$84.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$84.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$86.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$86.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$86.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$86.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$86.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$86.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$88.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$88.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$88.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$88.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$88.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$88.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$90.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$90.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$90.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$90.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$90.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$90.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$92.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$92.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$92.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$92.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$92.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$92.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$94.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$94.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$94.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$94.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$94.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$94.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$96.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$96.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$96.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$96.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$96.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$96.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$98.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$98.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$98.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$98.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$98.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$98.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$100.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$100.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$100.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$100.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$100.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$100.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$102.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$102.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$102.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$102.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$102.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$102.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$104.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$104.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$104.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$104.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$104.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$104.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$106.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$106.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$106.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$106.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$106.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$106.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$108.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$108.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$108.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$108.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$108.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$108.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$110.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$110.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$110.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$110.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$110.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$110.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$112.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$112.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$112.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$112.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$112.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$112.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$114.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$114.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$114.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$114.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$114.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$114.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$116.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$116.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$116.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$116.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$116.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$116.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$118.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$118.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$118.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$118.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$118.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$118.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$120.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$120.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$120.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$120.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$120.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$120.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$122.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$122.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$122.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$122.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$122.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$122.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$124.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$124.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$124.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$124.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$124.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$124.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$126.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$126.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$126.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$126.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$126.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$126.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$128.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$128.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$128.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$128.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$128.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$128.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Successfully finished Verilog frontend. + +-- Writing to `repwhile_tb.v' using backend `test_autotb -n 300' -- + +2. Executing TEST_AUTOTB backend (auto-generate pseudo-random test benches). +Generating test bench for module `\repwhile_test001'. + +Warnings: 63 unique messages, 321 total +End of script. Logfile hash: 5707642ad5, CPU: user 0.07s system 0.00s, MEM: 16.47 MB peak +Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) +Time spent: 99% 1x read_verilog (0 sec), 0% 1x test_autotb (0 sec) ++ false ++ compile_and_run repwhile_tb_ref repwhile_out_ref repwhile_tb.v repwhile_ref.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simlib.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simcells.v ++ exe=repwhile_tb_ref ++ output=repwhile_out_ref ++ shift 2 ++ '[' v == sv ']' ++ language_gen=-g2005 ++ false ++ false ++ iverilog -g2005 '-Doutfile="repwhile_out_ref"' -s testbench -o repwhile_tb_ref repwhile_tb.v repwhile_ref.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simlib.v /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../techlibs/common/simcells.v ++ vvp -n repwhile_tb_ref +repwhile_tb.v:101: $finish called at 120200 (1s) ++ false ++ test_count=0 ++ '[' 'verilog -noblackbox -specify' = verific -o 'verilog -noblackbox -specify' = verific_gates ']' ++ '[' -n '' ']' ++ '[' -n ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' ']' ++ test_passes -f 'verilog -noblackbox -specify ' -p ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' repwhile_ref.v ++ /home/george/code_ee_temp/yosys/yosys3/tests/tools/../../yosys -b 'verilog -noattr -noexpr -siminit' -o repwhile_syn0.v -f 'verilog -noblackbox -specify ' -p ' read_verilog -icells -lib +/abc9_model.v; hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4; clean; check -assert * abc9_test037 %d; select -assert-none t:?_NOT_ t:?_AND_ %%; setattr -mod -unset blackbox -unset whitebox' repwhile_ref.v + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2024 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.45+148 (git sha1 1bf908dea, sccache g++ 14.2.1 -fPIC -O3) + +-- Parsing `repwhile_ref.v' using frontend `verilog -noblackbox -specify ' -- + +1. Executing Verilog-2005 frontend: repwhile_ref.v +Parsing Verilog input from `repwhile_ref.v' to AST representation. +Generating RTLIL representation for module `\repwhile_test001'. +Warning: wire '\mylog2$func$repwhile_ref.v:29$4.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$6.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$6.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$8.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$8.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$10.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$10.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$10.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$12.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$12.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$12.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$14.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$14.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$14.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$16.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$16.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$16.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$18.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$18.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$18.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$18.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$20.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$20.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$20.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$20.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$22.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$22.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$22.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$22.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$24.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$24.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$24.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$24.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$26.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$26.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$26.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$26.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$28.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$28.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$28.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$28.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$30.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$30.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$30.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$30.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$32.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$32.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$32.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$32.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$34.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$34.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$34.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$34.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$34.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$36.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$36.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$36.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$36.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$36.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$38.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$38.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$38.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$38.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$38.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$40.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$40.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$40.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$40.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$40.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$42.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$42.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$42.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$42.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$42.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$44.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$44.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$44.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$44.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$44.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$46.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$46.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$46.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$46.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$46.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$48.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$48.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$48.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$48.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$48.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$50.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$50.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$50.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$50.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$50.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$52.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$52.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$52.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$52.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$52.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$54.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$54.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$54.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$54.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$54.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$56.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$56.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$56.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$56.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$56.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$58.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$58.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$58.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$58.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$58.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$60.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$60.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$60.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$60.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$60.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$62.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$62.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$62.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$62.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$62.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$64.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$64.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$64.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$64.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$64.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$66.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$66.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$66.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$66.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$66.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$66.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$68.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$68.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$68.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$68.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$68.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$68.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$70.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$70.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$70.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$70.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$70.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$70.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$72.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$72.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$72.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$72.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$72.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$72.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$74.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$74.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$74.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$74.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$74.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$74.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$76.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$76.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$76.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$76.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$76.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$76.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$78.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$78.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$78.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$78.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$78.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$78.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$80.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$80.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$80.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$80.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$80.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$80.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$82.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$82.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$82.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$82.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$82.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$82.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$84.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$84.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$84.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$84.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$84.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$84.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$86.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$86.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$86.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$86.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$86.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$86.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$88.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$88.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$88.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$88.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$88.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$88.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$90.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$90.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$90.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$90.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$90.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$90.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$92.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$92.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$92.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$92.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$92.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$92.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$94.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$94.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$94.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$94.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$94.value' is assigned in a block at repwhile_ref.v:8.5-8.23. +Warning: wire '\mylog2$func$repwhile_ref.v:29$94.value' is assigned in a block at repwhile_ref.v:8.5-8.23. diff --git a/tests/svtypes/typedef_initial_and_assign.ys b/tests/svtypes/typedef_initial_and_assign.ys index e778a49bb01..4563ca4919b 100644 --- a/tests/svtypes/typedef_initial_and_assign.ys +++ b/tests/svtypes/typedef_initial_and_assign.ys @@ -11,4 +11,4 @@ logger -expect warning "reg '\\var_19' is assigned in a continuous assignment" 1 read_verilog -sv typedef_initial_and_assign.sv hierarchy; proc; opt; async2sync select -module top -sat -verify -seq 1 -tempinduct -prove-asserts -show-all +sat -verify -tempinduct -prove-asserts -show-all diff --git a/tests/svtypes/typedef_struct_port.ys b/tests/svtypes/typedef_struct_port.ys index dd0775b9ff9..6cd61064cf7 100644 --- a/tests/svtypes/typedef_struct_port.ys +++ b/tests/svtypes/typedef_struct_port.ys @@ -1,6 +1,6 @@ read_verilog -sv typedef_struct_port.sv hierarchy; proc; opt; async2sync select -module top -sat -verify -seq 1 -tempinduct -prove-asserts -show-all +sat -verify -tempinduct -prove-asserts -show-all select -module test_parser -sat -verify -seq 1 -tempinduct -prove-asserts -show-all +sat -verify -tempinduct -prove-asserts -show-all diff --git a/tests/various/const_arg_loop.ys b/tests/various/const_arg_loop.ys index 01bea704499..21554cc0a49 100644 --- a/tests/various/const_arg_loop.ys +++ b/tests/various/const_arg_loop.ys @@ -4,4 +4,4 @@ proc opt -full select -module top async2sync -sat -verify -seq 1 -tempinduct -prove-asserts -show-all +sat -verify -tempinduct -prove-asserts -show-all diff --git a/tests/various/const_func.ys b/tests/various/const_func.ys index d982c3a43fa..e721e0e8157 100644 --- a/tests/various/const_func.ys +++ b/tests/various/const_func.ys @@ -5,4 +5,4 @@ flatten opt -full select -module top async2sync -sat -verify -seq 1 -tempinduct -prove-asserts -show-all +sat -verify -tempinduct -prove-asserts -show-all diff --git a/tests/various/countbits.ys b/tests/various/countbits.ys index f2db9cfe1f6..2d972e2d812 100644 --- a/tests/various/countbits.ys +++ b/tests/various/countbits.ys @@ -5,4 +5,4 @@ flatten opt -full select -module top async2sync -sat -verify -seq 1 -tempinduct -prove-asserts -show-all +sat -verify -tempinduct -prove-asserts -show-all diff --git a/tests/various/param_struct.ys b/tests/various/param_struct.ys index bb26b61d586..96837aafc0c 100644 --- a/tests/various/param_struct.ys +++ b/tests/various/param_struct.ys @@ -48,4 +48,4 @@ endmodule EOF hierarchy; proc; opt async2sync -sat -verify -seq 1 -tempinduct -prove-asserts -show-all +sat -verify -tempinduct -prove-asserts -show-all diff --git a/tests/verilog/atom_type_signedness.ys b/tests/verilog/atom_type_signedness.ys index c8a82f993c5..77a0bd2910a 100644 --- a/tests/verilog/atom_type_signedness.ys +++ b/tests/verilog/atom_type_signedness.ys @@ -16,4 +16,4 @@ endmodule EOT hierarchy; proc; opt; async2sync select -module dut -sat -verify -seq 1 -tempinduct -prove-asserts -show-all +sat -verify -tempinduct -prove-asserts -show-all diff --git a/tests/verilog/int_types.ys b/tests/verilog/int_types.ys index 344f3ee09aa..70c99976cad 100644 --- a/tests/verilog/int_types.ys +++ b/tests/verilog/int_types.ys @@ -5,4 +5,4 @@ flatten opt -full async2sync select -module top -sat -verify -seq 1 -tempinduct -prove-asserts -show-all +sat -verify -tempinduct -prove-asserts -show-all diff --git a/tests/verilog/mem_bounds.ys b/tests/verilog/mem_bounds.ys index 146a6f43302..2c973822a4f 100644 --- a/tests/verilog/mem_bounds.ys +++ b/tests/verilog/mem_bounds.ys @@ -4,4 +4,4 @@ flatten opt -full select -module top async2sync -sat -verify -seq 1 -tempinduct -prove-asserts -show-all -enable_undef +sat -verify -tempinduct -prove-asserts -show-all -enable_undef diff --git a/tests/verilog/param_no_default.ys b/tests/verilog/param_no_default.ys index 0509f6a1aa5..c609987e46d 100644 --- a/tests/verilog/param_no_default.ys +++ b/tests/verilog/param_no_default.ys @@ -5,4 +5,4 @@ flatten opt -full async2sync select -module top -sat -verify -seq 1 -tempinduct -prove-asserts -show-all +sat -verify -tempinduct -prove-asserts -show-all diff --git a/tests/verilog/parameters_across_files.ys b/tests/verilog/parameters_across_files.ys index 94565eb6703..3efe3e68c8c 100644 --- a/tests/verilog/parameters_across_files.ys +++ b/tests/verilog/parameters_across_files.ys @@ -18,4 +18,4 @@ flatten opt -full async2sync select -module top -sat -verify -seq 1 -tempinduct -prove-asserts -show-all +sat -verify -tempinduct -prove-asserts -show-all diff --git a/tests/verilog/typedef_across_files.ys b/tests/verilog/typedef_across_files.ys index baa4b7919dd..8cd578af43c 100644 --- a/tests/verilog/typedef_across_files.ys +++ b/tests/verilog/typedef_across_files.ys @@ -21,4 +21,4 @@ proc opt -full async2sync select -module top -sat -verify -seq 1 -tempinduct -prove-asserts -show-all +sat -verify -tempinduct -prove-asserts -show-all diff --git a/tests/verilog/typedef_legacy_conflict.ys b/tests/verilog/typedef_legacy_conflict.ys index dd1503a852c..d26cc188f81 100644 --- a/tests/verilog/typedef_legacy_conflict.ys +++ b/tests/verilog/typedef_legacy_conflict.ys @@ -35,4 +35,4 @@ flatten opt -full async2sync select -module top -sat -verify -seq 1 -tempinduct -prove-asserts -show-all +sat -verify -tempinduct -prove-asserts -show-all diff --git a/tests/verilog/unbased_unsized.ys b/tests/verilog/unbased_unsized.ys index 75d1bf5e4b5..3290650d531 100644 --- a/tests/verilog/unbased_unsized.ys +++ b/tests/verilog/unbased_unsized.ys @@ -5,4 +5,4 @@ flatten opt -full async2sync select -module top -sat -verify -seq 1 -tempinduct -prove-asserts -show-all +sat -verify -tempinduct -prove-asserts -show-all diff --git a/tests/verilog/unbased_unsized_shift.ys b/tests/verilog/unbased_unsized_shift.ys index 2b5b9d8d082..6a72560b8a1 100644 --- a/tests/verilog/unbased_unsized_shift.ys +++ b/tests/verilog/unbased_unsized_shift.ys @@ -5,4 +5,4 @@ flatten opt -full async2sync select -module top -sat -verify -seq 1 -tempinduct -prove-asserts -show-all +sat -verify -tempinduct -prove-asserts -show-all