From d5481863349e48f84d200e3d6b033abe9862a462 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Wed, 17 Apr 2024 14:58:30 +0200 Subject: [PATCH] Revert "Add simple.v" This reverts commit 94378a6260d7354a43caf91c703893aa28499ffe. --- tests/functional_backend/simple.v | 10 ---------- 1 file changed, 10 deletions(-) delete mode 100644 tests/functional_backend/simple.v diff --git a/tests/functional_backend/simple.v b/tests/functional_backend/simple.v deleted file mode 100644 index 3d55842945b..00000000000 --- a/tests/functional_backend/simple.v +++ /dev/null @@ -1,10 +0,0 @@ -// Simple pass-through Verilog module -module PassThrough( - input wire in, // Input wire - output wire out // Output wire connected directly to input -); - -// Connect the input directly to the output -assign out = in; - -endmodule