diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc
index e4e70004c0f..630f753f3b0 100644
--- a/passes/techmap/alumacc.cc
+++ b/passes/techmap/alumacc.cc
@@ -331,9 +331,6 @@ struct AlumaccWorker
 			if (GetSize(C) > 1)
 				goto next_macc;
 
-			if (!subtract_b && B < A && GetSize(B))
-				std::swap(A, B);
-
 			log("  creating $alu model for $macc %s.\n", log_id(n->cell));
 
 			alunode = new alunode_t;
@@ -405,11 +402,6 @@ struct AlumaccWorker
 			RTLIL::SigSpec B = sigmap(cell->getPort(ID::B));
 			RTLIL::SigSpec Y = sigmap(cell->getPort(ID::Y));
 
-			if (B < A && GetSize(B)) {
-				cmp_less = !cmp_less;
-				std::swap(A, B);
-			}
-
 			alunode_t *n = nullptr;
 
 			for (auto node : sig_alu[RTLIL::SigSig(A, B)])
@@ -418,6 +410,16 @@ struct AlumaccWorker
 					break;
 				}
 
+			if (n == nullptr) {
+				for (auto node : sig_alu[RTLIL::SigSig(B, A)])
+					if (node->invert_b && node->c == State::S1) {
+						n = node;
+						cmp_less = !cmp_less;
+						std::swap(A, B);
+						break;
+					}
+			}
+
 			if (n == nullptr) {
 				n = new alunode_t;
 				n->a = A;
@@ -445,9 +447,6 @@ struct AlumaccWorker
 			RTLIL::SigSpec B = sigmap(cell->getPort(ID::B));
 			RTLIL::SigSpec Y = sigmap(cell->getPort(ID::Y));
 
-			if (B < A && GetSize(B))
-				std::swap(A, B);
-
 			alunode_t *n = nullptr;
 
 			for (auto node : sig_alu[RTLIL::SigSig(A, B)])
@@ -456,6 +455,14 @@ struct AlumaccWorker
 					break;
 				}
 
+			if (n == nullptr) {
+				for (auto node : sig_alu[RTLIL::SigSig(B, A)])
+					if (node->invert_b && node->c == State::S1) {
+						n = node;
+						break;
+					}
+			}
+
 			if (n != nullptr) {
 				log("  creating $alu model for %s (%s): merged with %s.\n", log_id(cell), log_id(cell->type), log_id(n->cells.front()));
 				n->cells.push_back(cell);