Revert "cost: correct cost for single bit internal cells"

This reverts commit 2cc848a.
YosysHQ · May 7, 2024 · e747d8b · e747d8b
1 parent a31893c
commit e747d8b
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Showing 2 changed files with 2 additions and 4 deletions.
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
@@ -1722,8 +1722,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
 // create a new parametric module (when needed) and return the name of the generated module - without support for interfaces
 RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool /*mayfail*/)
 {
-	bool quiet = false;
-	log("quiet %d\n", quiet);
+	bool quiet = lib || attributes.count(ID::blackbox) || attributes.count(ID::whitebox);
 
 	AstNode *new_ast = NULL;
 	std::string modname = derive_common(design, parameters, &new_ast, quiet);

diff --git a/kernel/cost.cc b/kernel/cost.cc
@@ -135,9 +135,8 @@ unsigned int port_width_sum(RTLIL::Cell *cell)
 unsigned int CellCosts::get(RTLIL::Cell *cell)
 {
 
-	// simple 1-bit cells
 	if (gate_type_cost().count(cell->type))
-		return 1;
+		return gate_type_cost().at(cell->type);
 
 	if (design_ && design_->module(cell->type) && cell->parameters.empty()) {
 		log_debug("%s is a module, recurse\n", cell->name.c_str());