diff --git a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
index 5bd6a00681b..d6378fdd625 100644
--- a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
+++ b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
@@ -1010,19 +1010,19 @@ struct observer {
 // Default member initializers would make this a non-aggregate-type in C++11, so they are commented out.
 struct fmt_part {
 	enum {
-		STRING    = 0,
+		LITERAL   = 0,
 		INTEGER   = 1,
-		CHARACTER = 2,
+		STRING    = 2,
 		VLOG_TIME = 3,
 	} type;
 
-	// STRING type
+	// LITERAL type
 	std::string str;
 
-	// INTEGER/CHARACTER types
+	// INTEGER/STRING types
 	// + value<Bits> val;
 
-	// INTEGER/CHARACTER/VLOG_TIME types
+	// INTEGER/STRING/VLOG_TIME types
 	enum {
 		RIGHT	= 0,
 		LEFT	= 1,
@@ -1051,10 +1051,10 @@ struct fmt_part {
 		// chunk access if it turns out to be slow enough to matter.
 		std::string buf;
 		switch (type) {
-			case STRING:
+			case LITERAL:
 				return str;
 
-			case CHARACTER: {
+			case STRING: {
 				buf.reserve(Bits/8);
 				for (int i = 0; i < Bits; i += 8) {
 					char ch = 0;
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index fe67f00c692..bc7f1ddd1d6 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -790,7 +790,7 @@ struct AST_INTERNAL::ProcessGenerator
 				Fmt fmt;
 				fmt.parse_verilog(args, /*sformat_like=*/false, default_base, /*task_name=*/ast->str, current_module->name);
 				if (ast->str.substr(0, 8) == "$display")
-					fmt.append_string("\n");
+					fmt.append_literal("\n");
 				fmt.emit_rtlil(cell);
 			} else if (!ast->str.empty()) {
 				log_file_error(ast->filename, ast->location.first_line, "Found unsupported invocation of system task `%s'!\n", ast->str.c_str());
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 43a4e03a29d..3d8478ef160 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1079,7 +1079,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
 				// when $display()/$write() functions are used in an initial block, print them during synthesis
 				Fmt fmt = processFormat(stage, /*sformat_like=*/false, default_base, /*first_arg_at=*/0, /*may_fail=*/true);
 				if (str.substr(0, 8) == "$display")
-					fmt.append_string("\n");
+					fmt.append_literal("\n");
 				log("%s", fmt.render().c_str());
 			}
 
diff --git a/kernel/fmt.cc b/kernel/fmt.cc
index 4d4aecf5a81..85d903fd3d9 100644
--- a/kernel/fmt.cc
+++ b/kernel/fmt.cc
@@ -22,9 +22,9 @@
 
 USING_YOSYS_NAMESPACE
 
-void Fmt::append_string(const std::string &str) {
+void Fmt::append_literal(const std::string &str) {
 	FmtPart part = {};
-	part.type = FmtPart::STRING;
+	part.type = FmtPart::LITERAL;
 	part.str = str;
 	parts.push_back(part);
 }
@@ -46,7 +46,7 @@ void Fmt::parse_rtlil(const RTLIL::Cell *cell) {
 			log_assert(false && "Unexpected '}' in format string");
 		else if (fmt[i] == '{') {
 			if (!part.str.empty()) {
-				part.type = FmtPart::STRING;
+				part.type = FmtPart::LITERAL;
 				parts.push_back(part);
 				part = {};
 			}
@@ -112,7 +112,7 @@ void Fmt::parse_rtlil(const RTLIL::Cell *cell) {
 					part.base = 16;
 					part.hex_upper = true;
 				} else if (fmt[i] == 'c') {
-					part.type = FmtPart::CHARACTER;
+					part.type = FmtPart::STRING;
 				} else if (fmt[i] == 't') {
 					part.type = FmtPart::VLOG_TIME;
 				} else if (fmt[i] == 'r') {
@@ -154,7 +154,7 @@ void Fmt::parse_rtlil(const RTLIL::Cell *cell) {
 		}
 	}
 	if (!part.str.empty()) {
-		part.type = FmtPart::STRING;
+		part.type = FmtPart::LITERAL;
 		parts.push_back(part);
 	}
 }
@@ -165,7 +165,7 @@ void Fmt::emit_rtlil(RTLIL::Cell *cell) const {
 
 	for (auto &part : parts) {
 		switch (part.type) {
-			case FmtPart::STRING:
+			case FmtPart::LITERAL:
 				for (char c : part.str) {
 					if (c == '{')
 						fmt += "{{";
@@ -179,7 +179,7 @@ void Fmt::emit_rtlil(RTLIL::Cell *cell) const {
 			case FmtPart::VLOG_TIME:
 				log_assert(part.sig.size() == 0);
 				YS_FALLTHROUGH
-			case FmtPart::CHARACTER:
+			case FmtPart::STRING:
 				log_assert(part.sig.size() % 8 == 0);
 				YS_FALLTHROUGH
 			case FmtPart::INTEGER:
@@ -207,7 +207,7 @@ void Fmt::emit_rtlil(RTLIL::Cell *cell) const {
 					if (part.plus)
 						fmt += '+';
 					fmt += part.signed_ ? 's' : 'u';
-				} else if (part.type == FmtPart::CHARACTER) {
+				} else if (part.type == FmtPart::STRING) {
 					fmt += 'c';
 				} else if (part.type == FmtPart::VLOG_TIME) {
 					if (part.realtime)
@@ -303,12 +303,12 @@ void Fmt::apply_verilog_automatic_sizing_and_add(FmtPart &part)
 		part.width = places;
 
 		if (part.justify == FmtPart::RIGHT) {
-			append_string(gap);
+			append_literal(gap);
 			parts.push_back(part);
 		} else {
 			part.justify = FmtPart::RIGHT;
 			parts.push_back(part);
-			append_string(gap);
+			append_literal(gap);
 		}
 	}
 }
@@ -359,7 +359,7 @@ void Fmt::parse_verilog(const std::vector<VerilogFmtArg> &args, bool sformat_lik
 							part.str += module_name.str();
 						} else {
 							if (!part.str.empty()) {
-								part.type = FmtPart::STRING;
+								part.type = FmtPart::LITERAL;
 								parts.push_back(part);
 								part = {};
 							}
@@ -412,11 +412,11 @@ void Fmt::parse_verilog(const std::vector<VerilogFmtArg> &args, bool sformat_lik
 									part.type = FmtPart::INTEGER;
 									part.base = 16;
 								} else if (fmt[i] == 'c' || fmt[i] == 'C') {
-									part.type = FmtPart::CHARACTER;
+									part.type = FmtPart::STRING;
 									part.sig.extend_u0(8);
 									// %10c and %010c not fully defined in IEEE 1800-2017 and do different things in iverilog
 								} else if (fmt[i] == 's' || fmt[i] == 'S') {
-									part.type = FmtPart::CHARACTER;
+									part.type = FmtPart::STRING;
 									if ((part.sig.size() % 8) != 0)
 										part.sig.extend_u0((part.sig.size() + 7) / 8 * 8);
 									// %10s and %010s not fully defined in IEEE 1800-2017 and do the same thing in iverilog
@@ -453,12 +453,12 @@ void Fmt::parse_verilog(const std::vector<VerilogFmtArg> &args, bool sformat_lik
 						}
 					}
 					if (!part.str.empty()) {
-						part.type = FmtPart::STRING;
+						part.type = FmtPart::LITERAL;
 						parts.push_back(part);
 					}
 				} else {
 					FmtPart part = {};
-					part.type = FmtPart::STRING;
+					part.type = FmtPart::LITERAL;
 					part.str = arg->str;
 					parts.push_back(part);
 				}
@@ -478,7 +478,7 @@ std::vector<VerilogFmtArg> Fmt::emit_verilog() const
 
 	for (auto &part : parts) {
 		switch (part.type) {
-			case FmtPart::STRING:
+			case FmtPart::LITERAL:
 				for (char c : part.str) {
 					if (c == '%')
 						fmt.str += "%%";
@@ -517,7 +517,7 @@ std::vector<VerilogFmtArg> Fmt::emit_verilog() const
 				break;
 			}
 
-			case FmtPart::CHARACTER: {
+			case FmtPart::STRING: {
 				VerilogFmtArg arg;
 				arg.type = VerilogFmtArg::INTEGER;
 				arg.sig = part.sig;
@@ -603,9 +603,9 @@ void Fmt::emit_cxxrtl(std::ostream &os, std::string indent, std::function<void(c
 		os << indent << "buf += fmt_part { ";
 		os << "fmt_part::";
 		switch (part.type) {
-			case FmtPart::STRING:    os << "STRING";    break;
+			case FmtPart::LITERAL:   os << "LITERAL";   break;
 			case FmtPart::INTEGER:   os << "INTEGER";   break;
-			case FmtPart::CHARACTER: os << "CHARACTER"; break;
+			case FmtPart::STRING:    os << "STRING";    break;
 			case FmtPart::VLOG_TIME: os << "VLOG_TIME"; break;
 		}
 		os << ", ";
@@ -636,12 +636,12 @@ std::string Fmt::render() const
 
 	for (auto &part : parts) {
 		switch (part.type) {
-			case FmtPart::STRING:
+			case FmtPart::LITERAL:
 				str += part.str;
 				break;
 
 			case FmtPart::INTEGER:
-			case FmtPart::CHARACTER:
+			case FmtPart::STRING:
 			case FmtPart::VLOG_TIME: {
 				std::string buf;
 				if (part.type == FmtPart::INTEGER) {
@@ -723,7 +723,7 @@ std::string Fmt::render() const
 							std::reverse(buf.begin(), buf.end());
 						}
 					} else log_abort();
-				} else if (part.type == FmtPart::CHARACTER) {
+				} else if (part.type == FmtPart::STRING) {
 					buf = part.sig.as_const().decode_string();
 				} else if (part.type == FmtPart::VLOG_TIME) {
 					// We only render() during initial, so time is always zero.
diff --git a/kernel/fmt.h b/kernel/fmt.h
index 1609620608e..64641f8afe8 100644
--- a/kernel/fmt.h
+++ b/kernel/fmt.h
@@ -53,19 +53,19 @@ struct VerilogFmtArg {
 // Must be kept in sync with `struct fmt_part` in backends/cxxrtl/runtime/cxxrtl/cxxrtl.h!
 struct FmtPart {
 	enum {
-		STRING  	= 0,
+		LITERAL  	= 0,
 		INTEGER 	= 1,
-		CHARACTER = 2,
+		STRING    = 2,
 		VLOG_TIME = 3,
 	} type;
 
-	// STRING type
+	// LITERAL type
 	std::string str;
 
-	// INTEGER/CHARACTER types
+	// INTEGER/STRING types
 	RTLIL::SigSpec sig;
 
-	// INTEGER/CHARACTER/VLOG_TIME types
+	// INTEGER/STRING/VLOG_TIME types
 	enum {
 		RIGHT	= 0,
 		LEFT	= 1,
@@ -87,7 +87,7 @@ struct Fmt {
 public:
 	std::vector<FmtPart> parts;
 
-	void append_string(const std::string &str);
+	void append_literal(const std::string &str);
 
 	void parse_rtlil(const RTLIL::Cell *cell);
 	void emit_rtlil(RTLIL::Cell *cell) const;