From f193ebdded593c837e9f3447fddf803723f8e5f9 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 27 Sep 2023 16:57:18 +0200 Subject: [PATCH] Verific: add default parameters to modules --- frontends/verific/verific.cc | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index cd844dceeee..310e3918015 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1275,9 +1275,16 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma log("Importing module %s.\n", RTLIL::id2cstr(module->name)); } import_attributes(module->attributes, nl, nl); + const char *param_name ; + const char *param_value ; + MapIter mi; + FOREACH_PARAMETER_OF_NETLIST(nl, mi, param_name, param_value) { + module->avail_parameters(RTLIL::escape_id(param_name)); + module->parameter_default_values[RTLIL::escape_id(param_name)] = verific_const(param_value); + } SetIter si; - MapIter mi, mi2; + MapIter mi2; Port *port; PortBus *portbus; Net *net;