From fb55e3f88ad4f363e43170e2d343bec15de482a2 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Mon, 22 Jan 2024 14:42:45 +0100
Subject: [PATCH] rtlil: Add wire deletion test

---
 tests/various/bug4082.ys | 8 ++++++++
 1 file changed, 8 insertions(+)
 create mode 100644 tests/various/bug4082.ys

diff --git a/tests/various/bug4082.ys b/tests/various/bug4082.ys
new file mode 100644
index 00000000000..272be2fad27
--- /dev/null
+++ b/tests/various/bug4082.ys
@@ -0,0 +1,8 @@
+read_verilog <<EOF
+module top;
+  wire a;
+  wire b;
+  assign a = b;
+endmodule
+EOF
+delete w:a