diff --git a/tests/arch/xilinx/bug3670.ys b/tests/arch/xilinx/bug3670.ys
index 772072c1ee4..2f29596e4ba 100644
--- a/tests/arch/xilinx/bug3670.ys
+++ b/tests/arch/xilinx/bug3670.ys
@@ -1,3 +1,3 @@
 read_verilog bug3670.v
 read_verilog -lib -specify +/xilinx/cells_sim.v
-abc9
+abc9 -lutlib
diff --git a/tests/arch/xilinx/dsp_abc9.ys b/tests/arch/xilinx/dsp_abc9.ys
index 1d74cfa89b2..c77a522e415 100644
--- a/tests/arch/xilinx/dsp_abc9.ys
+++ b/tests/arch/xilinx/dsp_abc9.ys
@@ -49,7 +49,7 @@ DSP48E1 #(.AREG(1)) u2(.A(A), .B(B), .PCIN(casc), .P(P));
 endmodule
 EOT
 synth_xilinx -run :prepare
-abc9
+abc9 -lutlib
 clean
 check
 logger -expect-no-warnings
diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys
index e0add714b1b..a4c9de707f7 100644
--- a/tests/various/abc9.ys
+++ b/tests/various/abc9.ys
@@ -73,7 +73,7 @@ module abc9_test037(input [1:0] i, output o);
 LUT2 #(.mask(4'b0)) lut (.i(i), .o(o));
 endmodule
 EOT
-abc9
+abc9 -lutlib
 
 
 design -reset