How to add standard cell in Yosys

[jalcim]

Hi,

Pliz, if its for write "Don't use the primitive Yosys is here for synthesise an high level code" pass your road <3

I search a solution for adding standard cell in Yosys,
I work with spice and directly with pfet-nfet (cmos) like that :
https://github.com/google/skywater-pdk-libs-sky130_fd_pr/tree/f62031a1be9aefe902d6d54cddd6f59b57627436/cells/pfet_01v8

I want to find a solution for synthesise this exemple of Verilog (because I need te generate my code with params),
I see actually for writing a Yosys plugins.
Maybe an other idea ?
(same question about logic gate)

module serial_nmos(drain, source, gate);
   parameter SIZE = 1;
   input [SIZE-1:0] source, gate;
   output [SIZE-1:0] drain;

   if (SIZE > 0)
     nmos inst(drain[0], source[0], gate[0]);
   if (SIZE > 1)
     serial_nmos #(.SIZE(SIZE-1)) recall(drain[SIZE-1:1], source[SIZE-1:1], gate[SIZE-1:1]);
endmodule

module gate_nand(out, e1, e2);
   parameter SIZE = 3;
   input [SIZE-1:0] e1, e2;
   output           out;

   supply1          vcc;
   supply0          gnd;

   wire [0:0]       line;

   serial_pmos #(.SIZE(2)) pmos_array({out, out},
                                      {vcc, vcc},
                                      {e1[0], e2[0]});
   serial_nmos #(.SIZE(2)) nmos_array({line[0], out},
                                      {gnd, line[0]},
                                      {e1[0], e2[0]});
endmodule