D type FlipFlop with asynchronize RESET

[ashkanr65]

Hi,
I have tried to define a DFFR on lib file like this:
` cell (DFFR) {
drive_strength : 1;
area : 75852;
cell_leakage_power : 86.212780;

ff ("Q_init") {
  clocked_on: "CLK";
		next_state: "D";
		clear: "RESET";
		async_clear: true;
}

pg_pin(VDD) {
  voltage_name : VDD;
  pg_type      : primary_power;
}

pg_pin(VSS) {
  voltage_name : VSS;
  pg_type      : primary_ground;
}

pin (D) {
  direction		: input;
  related_power_pin		: "VDD";
  related_ground_pin	: "VSS";
  capacitance		: 1.128277;
  fall_capacitance	: 1.052731;
  rise_capacitance	: 1.128277;
}

pin (RESET) {
  direction		: input;
  async: true;
  related_power_pin		: "VDD";
  related_ground_pin		: "VSS";
  capacitance		: 1.778528;
  fall_capacitance	: 1.744622;
  rise_capacitance	: 1.778528;
}

pin (CLK) {
  direction		: input;
  related_power_pin		: "VDD";
  related_ground_pin		: "VSS";
  clock   		: true;
  capacitance		: 0.976605;
  fall_capacitance	: 0.880697;
  rise_capacitance	: 0.976605;
}

pin (Q) {
  direction		: output;
  related_power_pin	: "VDD";
  related_ground_pin	: "VSS";
  max_capacitance		: 60.577400;
  function		: "(RESET == 1) ? 0 : ((posedge CLK) ? D : Q_init)";
}

pin (Qbar) {
  direction		: output;
  related_power_pin	: "VDD";
  related_ground_pin	: "VSS";
  max_capacitance		: 60.272200;
  function		: "(RESET == 1) ? 1 : ((posedge CLK) ? !D : !Q_init)";
}

}`
But during the dfflibmap pass, yosys returns this error:
11.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
ERROR: FF delayed_serial_adder.$auto$ff.cc:266:slice$94 (type $DFF_PN0) cannot be legalized: dffs with async set or reset are not supported
How can I solve that?