diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index 11692b715ea..7461460fed8 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -36,7 +36,7 @@ void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
 
 	for (int i = 0; i < GetSize(sig_y); i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
-		gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+		gate->attributes[ID::src] = cell->attributes[ID::src];
 		gate->setPort(ID::A, sig_a[i]);
 		gate->setPort(ID::Y, sig_y[i]);
 	}
@@ -73,7 +73,7 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
 
 	for (int i = 0; i < GetSize(sig_y); i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-		gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+		gate->attributes[ID::src] = cell->attributes[ID::src];
 		gate->setPort(ID::A, sig_a[i]);
 		gate->setPort(ID::B, sig_b[i]);
 		gate->setPort(ID::Y, sig_y[i]);
@@ -124,7 +124,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
 			}
 
 			RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-			gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+			gate->attributes[ID::src] = cell->attributes[ID::src];
 			gate->setPort(ID::A, sig_a[i]);
 			gate->setPort(ID::B, sig_a[i+1]);
 			gate->setPort(ID::Y, sig_t[i/2]);
@@ -137,7 +137,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
 	if (cell->type == ID($reduce_xnor)) {
 		RTLIL::SigSpec sig_t = module->addWire(NEW_ID);
 		RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
-		gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+		gate->attributes[ID::src] = cell->attributes[ID::src];
 		gate->setPort(ID::A, sig_a);
 		gate->setPort(ID::Y, sig_t);
 		last_output_cell = gate;
@@ -165,7 +165,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell
 			}
 
 			RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_OR_));
-			gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+			gate->attributes[ID::src] = cell->attributes[ID::src];
 			gate->setPort(ID::A, sig[i]);
 			gate->setPort(ID::B, sig[i+1]);
 			gate->setPort(ID::Y, sig_t[i/2]);
@@ -194,7 +194,7 @@ void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
 	}
 
 	RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
-	gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+	gate->attributes[ID::src] = cell->attributes[ID::src];
 	gate->setPort(ID::A, sig_a);
 	gate->setPort(ID::Y, sig_y);
 }
@@ -223,7 +223,7 @@ void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
 	log_assert(!gate_type.empty());
 
 	RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-	gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+	gate->attributes[ID::src] = cell->attributes[ID::src];
 	gate->setPort(ID::A, sig_a);
 	gate->setPort(ID::B, sig_b);
 	gate->setPort(ID::Y, sig_y);
@@ -239,20 +239,20 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
 
 	RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b)));
 	RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed);
-	xor_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+	xor_cell->attributes[ID::src] = cell->attributes[ID::src];
 	simplemap_bitop(module, xor_cell);
 	module->remove(xor_cell);
 
 	RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID);
 	RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID, xor_out, reduce_out);
-	reduce_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+	reduce_cell->attributes[ID::src] = cell->attributes[ID::src];
 	simplemap_reduce(module, reduce_cell);
 	module->remove(reduce_cell);
 
 	if (!is_ne) {
 		RTLIL::Cell *not_cell = module->addLogicNot(NEW_ID, reduce_out, sig_y);
-		not_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
-		simplemap_lognot(module, not_cell);
+		not_cell->attributes[ID::src] = cell->attributes[ID::src];
+                simplemap_lognot(module, not_cell);
 		module->remove(not_cell);
 	}
 }
@@ -265,7 +265,7 @@ void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
 
 	for (int i = 0; i < GetSize(sig_y); i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
-		gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+		gate->attributes[ID::src] = cell->attributes[ID::src];
 		gate->setPort(ID::A, sig_a[i]);
 		gate->setPort(ID::B, sig_b[i]);
 		gate->setPort(ID::S, cell->getPort(ID::S));
@@ -282,7 +282,7 @@ void simplemap_bwmux(RTLIL::Module *module, RTLIL::Cell *cell)
 
 	for (int i = 0; i < GetSize(sig_y); i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
-		gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+		gate->attributes[ID::src] = cell->attributes[ID::src];
 		gate->setPort(ID::A, sig_a[i]);
 		gate->setPort(ID::B, sig_b[i]);
 		gate->setPort(ID::S, sig_s[i]);
@@ -298,7 +298,7 @@ void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell)
 
 	for (int i = 0; i < GetSize(sig_y); i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_TBUF_));
-		gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+		gate->attributes[ID::src] = cell->attributes[ID::src];
 		gate->setPort(ID::A, sig_a[i]);
 		gate->setPort(ID::E, sig_e);
 		gate->setPort(ID::Y, sig_y[i]);
@@ -316,7 +316,7 @@ void simplemap_bmux(RTLIL::Module *module, RTLIL::Cell *cell)
 		for (int i = 0; i < GetSize(new_data); i += width) {
 			for (int k = 0; k < width; k++) {
 				RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
-				gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+				gate->attributes[ID::src] = cell->attributes[ID::src];
 				gate->setPort(ID::A, data[i*2+k]);
 				gate->setPort(ID::B, data[i*2+width+k]);
 				gate->setPort(ID::S, sel[idx]);
@@ -339,7 +339,7 @@ void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell)
 		SigSpec new_lut_data = module->addWire(NEW_ID, GetSize(lut_data)/2);
 		for (int i = 0; i < GetSize(lut_data); i += 2) {
 			RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
-			gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+			gate->attributes[ID::src] = cell->attributes[ID::src];
 			gate->setPort(ID::A, lut_data[i]);
 			gate->setPort(ID::B, lut_data[i+1]);
 			gate->setPort(ID::S, lut_ctrl[idx]);