From d0e559a34f8be18af195c8eb15324baf28d9c2a5 Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Mon, 2 Oct 2023 16:06:26 +0200 Subject: [PATCH 1/8] celledges: support shift ops --- kernel/celledges.cc | 46 ++++++++++++++++++++++++++++++++++++++------- 1 file changed, 39 insertions(+), 7 deletions(-) diff --git a/kernel/celledges.cc b/kernel/celledges.cc index c43ba8db330..0288b62e245 100644 --- a/kernel/celledges.cc +++ b/kernel/celledges.cc @@ -172,6 +172,30 @@ void demux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) } } +void shift_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) +{ + int width = GetSize(cell->getPort(ID::A)); + int b_width = GetSize(cell->getPort(ID::B)); + + for (int i = 0; i < width; i++){ + for (int k = 0; k < b_width; k++) + db->add_edge(cell, ID::B, k, ID::Y, i, -1); + + if (cell->type.in(ID($shl), ID($sshl))) { + for (int k = i; k >= 0; k--) + db->add_edge(cell, ID::A, k, ID::Y, i, -1); + } + + if (cell->type.in(ID($shr), ID($sshr))) + for (int k = i; k < width; k++) + db->add_edge(cell, ID::A, k, ID::Y, i, -1); + + if (cell->type.in(ID($shift), ID($shiftx))) + for (int k = 0; k < width; k++) + db->add_edge(cell, ID::A, k, ID::Y, i, -1); + } +} + PRIVATE_NAMESPACE_END bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL::Cell *cell) @@ -201,11 +225,10 @@ bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL return true; } - // FIXME: - // if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) { - // shift_op(this, cell); - // return true; - // } + if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) { + shift_op(this, cell); + return true; + } if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) { compare_op(this, cell); @@ -227,8 +250,17 @@ bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL return true; } - // FIXME: $mul $div $mod $divfloor $modfloor $slice $concat - // FIXME: $lut $sop $alu $lcu $macc $fa + // FIXME: $mul $div $mod $divfloor $modfloor $pow $slice $concat $bweqx + // FIXME: $lut $sop $alu $lcu $macc $fa $logic_and $logic_or $bwmux + + // FIXME: $_BUF_ $_NOT_ $_AND_ $_NAND_ $_OR_ $_NOR_ $_XOR_ $_XNOR_ $_ANDNOT_ $_ORNOT_ + // FIXME: $_MUX_ $_NMUX_ $_MUX4_ $_MUX8_ $_MUX16_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_ + + // FIXME: $specify2 $specify3 $specrule ??? + // FIXME: $equiv $set_tag $get_tag $overwrite_tag $original_tag + + if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover), ID($initstate), ID($anyconst), ID($anyseq), ID($allconst), ID($allseq))) + return true; // no-op: these have either no inputs or no outputs return false; } From 2d6d6a8da1dd89a606bff4099e7b84404deb6e07 Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Mon, 2 Oct 2023 17:29:09 +0200 Subject: [PATCH 2/8] fix handling a_width != y_width --- kernel/celledges.cc | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/kernel/celledges.cc b/kernel/celledges.cc index 0288b62e245..fc381f35cdd 100644 --- a/kernel/celledges.cc +++ b/kernel/celledges.cc @@ -174,24 +174,25 @@ void demux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void shift_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - int width = GetSize(cell->getPort(ID::A)); + int a_width = GetSize(cell->getPort(ID::A)); int b_width = GetSize(cell->getPort(ID::B)); + int y_width = GetSize(cell->getPort(ID::Y)); - for (int i = 0; i < width; i++){ + for (int i = 0; i < y_width; i++){ for (int k = 0; k < b_width; k++) db->add_edge(cell, ID::B, k, ID::Y, i, -1); if (cell->type.in(ID($shl), ID($sshl))) { - for (int k = i; k >= 0; k--) + for (int k = min(i, a_width); k >= 0; k--) db->add_edge(cell, ID::A, k, ID::Y, i, -1); } if (cell->type.in(ID($shr), ID($sshr))) - for (int k = i; k < width; k++) + for (int k = i; k < a_width; k++) db->add_edge(cell, ID::A, k, ID::Y, i, -1); if (cell->type.in(ID($shift), ID($shiftx))) - for (int k = 0; k < width; k++) + for (int k = 0; k < a_width; k++) db->add_edge(cell, ID::A, k, ID::Y, i, -1); } } From 6c562c76bc36ea51af25c26abffe7f92ceae77bd Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Mon, 2 Oct 2023 18:32:53 +0200 Subject: [PATCH 3/8] fix handling right shifts --- kernel/celledges.cc | 61 +++++++++++++++++++++++++++++++++++++-------- passes/sat/eval.cc | 4 +-- 2 files changed, 53 insertions(+), 12 deletions(-) diff --git a/kernel/celledges.cc b/kernel/celledges.cc index fc381f35cdd..1e5a68db3a8 100644 --- a/kernel/celledges.cc +++ b/kernel/celledges.cc @@ -174,26 +174,67 @@ void demux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void shift_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { + bool is_signed = cell->getParam(ID::A_SIGNED).as_bool(); int a_width = GetSize(cell->getPort(ID::A)); int b_width = GetSize(cell->getPort(ID::B)); int y_width = GetSize(cell->getPort(ID::Y)); - for (int i = 0; i < y_width; i++){ - for (int k = 0; k < b_width; k++) - db->add_edge(cell, ID::B, k, ID::Y, i, -1); + // how far the maximum value of B is able to shift + int b_range = (1<type.in(ID($shl), ID($sshl))) { - for (int k = min(i, a_width); k >= 0; k--) - db->add_edge(cell, ID::A, k, ID::Y, i, -1); + // << and <<< + b_range_upper = a_width + b_range; + if (is_signed) b_range_upper -= 1; + a_range_lower = max(0, i - b_range); + a_range_upper = min(i+1, a_width); + } else if (cell->type.in(ID($shr), ID($sshr))){ + // >> and >>> + b_range_upper = a_width; + a_range_lower = min(i, a_width - 1); // technically the min is unneccessary as b_range_upper check already skips any i >= a_width, but let's leave the logic in since this is hard enough + a_range_upper = min(i+1 + b_range, a_width); + } else if (cell->type.in(ID($shift), ID($shiftx))) { + // can go both ways depending on sign of B + // 2's complement range is different depending on direction + int b_range_left = (1<<(b_width - 1)); + int b_range_right = (1<<(b_width - 1)) - 1; + b_range_upper = a_width + b_range_left; + a_range_lower = max(0, i - b_range_left); + a_range_upper = min(i+1 + b_range_right, a_width); } - if (cell->type.in(ID($shr), ID($sshr))) - for (int k = i; k < a_width; k++) + if (i < b_range_upper) { + for (int k = a_range_lower; k < a_range_upper; k++) db->add_edge(cell, ID::A, k, ID::Y, i, -1); + } else { + // the only possible influence value is sign extension + if (is_signed) + db->add_edge(cell, ID::A, a_width - 1, ID::Y, i, -1); + } + + for (int k = 0; k < b_width; k++) { + if (cell->type.in(ID($shl), ID($sshl)) && a_width == 1 && is_signed) { + int skip = (1<<(k+1)); + int base = skip -1; + if (i % skip != base) + db->add_edge(cell, ID::B, k, ID::Y, i, -1); + } else if (cell->type.in(ID($shr), ID($sshr)) && is_signed) { + int skip = (1<<(k+1)); + int base = 0; + if (i % skip != base || i < a_width - 1) + db->add_edge(cell, ID::B, k, ID::Y, i, -1); + } else { + db->add_edge(cell, ID::B, k, ID::Y, i, -1); + } + } - if (cell->type.in(ID($shift), ID($shiftx))) - for (int k = 0; k < a_width; k++) - db->add_edge(cell, ID::A, k, ID::Y, i, -1); } } diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 05879426e63..acebea6c568 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -543,13 +543,13 @@ struct EvalPass : public Pass { int pos = 0; for (auto &c : tabsigs.chunks()) { - tab_line.push_back(log_signal(RTLIL::SigSpec(tabvals).extract(pos, c.width))); + tab_line.push_back(log_signal(RTLIL::SigSpec(tabvals).extract(pos, c.width), false)); pos += c.width; } pos = 0; for (auto &c : signal.chunks()) { - tab_line.push_back(log_signal(value.extract(pos, c.width))); + tab_line.push_back(log_signal(value.extract(pos, c.width), false)); pos += c.width; } From bdd74e61aed2297cdd3af76da8f43432e6a0afa7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 16 Oct 2023 13:29:47 +0200 Subject: [PATCH 4/8] celledges: Account for shift down of x-bits wrt B port --- kernel/celledges.cc | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/kernel/celledges.cc b/kernel/celledges.cc index 1e5a68db3a8..c6615968f26 100644 --- a/kernel/celledges.cc +++ b/kernel/celledges.cc @@ -226,12 +226,16 @@ void shift_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) if (i % skip != base) db->add_edge(cell, ID::B, k, ID::Y, i, -1); } else if (cell->type.in(ID($shr), ID($sshr)) && is_signed) { - int skip = (1<<(k+1)); - int base = 0; - if (i % skip != base || i < a_width - 1) + bool shift_in_bulk = i < a_width - 1; + // can we jump into the ambient x-bits by toggling B[k]? + bool x_jump = (((y_width - i) & ((1 << (k + 1)) - 1)) != 0 \ + && (((y_width - i) & ~(1 << k)) < (1 << b_width))); + + if (shift_in_bulk || (cell->type == ID($shr) && x_jump)) db->add_edge(cell, ID::B, k, ID::Y, i, -1); } else { - db->add_edge(cell, ID::B, k, ID::Y, i, -1); + if (i < a_width) + db->add_edge(cell, ID::B, k, ID::Y, i, -1); } } From 4cce4916397bcc6ce9e44692f1b31f4edc9369be Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sun, 10 Dec 2023 00:27:42 +0100 Subject: [PATCH 5/8] celledges: s/x_jump/zpad_jump/ --- kernel/celledges.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/kernel/celledges.cc b/kernel/celledges.cc index c6615968f26..2d8177d31ae 100644 --- a/kernel/celledges.cc +++ b/kernel/celledges.cc @@ -227,11 +227,11 @@ void shift_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) db->add_edge(cell, ID::B, k, ID::Y, i, -1); } else if (cell->type.in(ID($shr), ID($sshr)) && is_signed) { bool shift_in_bulk = i < a_width - 1; - // can we jump into the ambient x-bits by toggling B[k]? - bool x_jump = (((y_width - i) & ((1 << (k + 1)) - 1)) != 0 \ + // can we jump into the zero-padding by toggling B[k]? + bool zpad_jump = (((y_width - i) & ((1 << (k + 1)) - 1)) != 0 \ && (((y_width - i) & ~(1 << k)) < (1 << b_width))); - if (shift_in_bulk || (cell->type == ID($shr) && x_jump)) + if (shift_in_bulk || (cell->type == ID($shr) && zpad_jump)) db->add_edge(cell, ID::B, k, ID::Y, i, -1); } else { if (i < a_width) From a96c257b3f4860534d7db2b1611c352eceb86161 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 11 Dec 2023 21:36:00 +0100 Subject: [PATCH 6/8] celledges: Add messy rules that do pass the tests This passes `test_cell -edges` on all the types of shift cells. --- kernel/celledges.cc | 55 +++++++++++++++++++++++++++++++++++++++------ 1 file changed, 48 insertions(+), 7 deletions(-) diff --git a/kernel/celledges.cc b/kernel/celledges.cc index 2d8177d31ae..a78c1ab8333 100644 --- a/kernel/celledges.cc +++ b/kernel/celledges.cc @@ -175,9 +175,16 @@ void demux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void shift_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { bool is_signed = cell->getParam(ID::A_SIGNED).as_bool(); + bool is_b_signed = cell->getParam(ID::B_SIGNED).as_bool(); int a_width = GetSize(cell->getPort(ID::A)); int b_width = GetSize(cell->getPort(ID::B)); int y_width = GetSize(cell->getPort(ID::Y)); + int effective_a_width = a_width; + + if (cell->type.in(ID($shift), ID($shiftx)) && is_signed) { + effective_a_width = std::max(y_width, a_width); + //is_signed = false; + } // how far the maximum value of B is able to shift int b_range = (1<type.in(ID($shr), ID($sshr))){ + } else if (cell->type.in(ID($shr), ID($sshr)) || (cell->type.in(ID($shift), ID($shiftx)) && !is_b_signed)){ // >> and >>> b_range_upper = a_width; a_range_lower = min(i, a_width - 1); // technically the min is unneccessary as b_range_upper check already skips any i >= a_width, but let's leave the logic in since this is hard enough a_range_upper = min(i+1 + b_range, a_width); - } else if (cell->type.in(ID($shift), ID($shiftx))) { + } else if (cell->type.in(ID($shift), ID($shiftx)) && is_b_signed) { // can go both ways depending on sign of B // 2's complement range is different depending on direction int b_range_left = (1<<(b_width - 1)); int b_range_right = (1<<(b_width - 1)) - 1; - b_range_upper = a_width + b_range_left; + b_range_upper = effective_a_width + b_range_left; a_range_lower = max(0, i - b_range_left); + if (is_signed) + a_range_lower = min(a_range_lower, a_width - 1); a_range_upper = min(i+1 + b_range_right, a_width); } @@ -223,18 +232,50 @@ void shift_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) if (cell->type.in(ID($shl), ID($sshl)) && a_width == 1 && is_signed) { int skip = (1<<(k+1)); int base = skip -1; - if (i % skip != base) + if (i % skip != base && i - a_width + 2 < 1 << b_width) db->add_edge(cell, ID::B, k, ID::Y, i, -1); - } else if (cell->type.in(ID($shr), ID($sshr)) && is_signed) { + } else if (true && cell->type.in(ID($shift), ID($shiftx)) && a_width == 1 && is_signed && is_b_signed) { + if (k != b_width - 1) { + // can we jump into the zero-padding by toggling B[k]? + bool zpad_jump = (((y_width - i) & ((1 << (k + 1)) - 1)) != 0 \ + && (((y_width - i) & ~(1 << k)) < (1 << (b_width - 1)))); + if (((~(i - 1) & ((1 << (k + 1)) - 1)) != 0 && i < 1 << (b_width - 1)) || zpad_jump) + db->add_edge(cell, ID::B, k, ID::Y, i, -1); + } else { + if ((y_width - 1 - i < (1 << (b_width - 1)) - 1) || (i < (1 << (b_width - 1)))) + db->add_edge(cell, ID::B, k, ID::Y, i, -1); + } + } else if ((cell->type.in(ID($shr), ID($sshr)) || (cell->type.in(ID($shift), ID($shiftx)) && !is_b_signed)) && is_signed) { bool shift_in_bulk = i < a_width - 1; // can we jump into the zero-padding by toggling B[k]? bool zpad_jump = (((y_width - i) & ((1 << (k + 1)) - 1)) != 0 \ && (((y_width - i) & ~(1 << k)) < (1 << b_width))); - if (shift_in_bulk || (cell->type == ID($shr) && zpad_jump)) + if (shift_in_bulk || (cell->type.in(ID($shr), ID($shift), ID($shiftx)) && zpad_jump)) + db->add_edge(cell, ID::B, k, ID::Y, i, -1); + } else if (cell->type.in(ID($sshl), ID($shl)) && is_signed) { + if (i - a_width + 2 < 1 << b_width) + db->add_edge(cell, ID::B, k, ID::Y, i, -1); + } else if (cell->type.in(ID($shl), ID($sshl))) { + if (i - a_width + 1 < 1 << b_width) + db->add_edge(cell, ID::B, k, ID::Y, i, -1); + } else if (cell->type.in(ID($shift), ID($shiftx)) && is_b_signed && !is_signed) { + if (i - a_width < (1 << (b_width - 1))) db->add_edge(cell, ID::B, k, ID::Y, i, -1); + } else if (cell->type.in(ID($shift), ID($shiftx)) && is_b_signed && is_signed) { + if (k != b_width - 1) { + bool r_shift_in_bulk = i < a_width - 1; + // can we jump into the zero-padding by toggling B[k]? + bool r_zpad_jump = (((y_width - i) & ((1 << (k + 1)) - 1)) != 0 \ + && (((y_width - i) & ~(1 << k)) < (1 << (b_width - 1)))); + if (r_shift_in_bulk || r_zpad_jump || i - a_width + 2 <= 1 << (b_width - 1)) + db->add_edge(cell, ID::B, k, ID::Y, i, -1); + } else { + if ((i - a_width + 2) <= (1 << (b_width - 1)) || (y_width - i) < (1 << (b_width - 1))) + db->add_edge(cell, ID::B, k, ID::Y, i, -1); + } } else { - if (i < a_width) + if (i < effective_a_width) db->add_edge(cell, ID::B, k, ID::Y, i, -1); } } From 134eb15c7e25816aba6570ed78b21398c539c395 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Fri, 19 Jan 2024 11:08:31 +0100 Subject: [PATCH 7/8] celledges: Clean up shift rules --- kernel/celledges.cc | 154 +++++++++++++++++++++++++------------------- 1 file changed, 89 insertions(+), 65 deletions(-) diff --git a/kernel/celledges.cc b/kernel/celledges.cc index a78c1ab8333..2ed0d503605 100644 --- a/kernel/celledges.cc +++ b/kernel/celledges.cc @@ -179,107 +179,131 @@ void shift_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) int a_width = GetSize(cell->getPort(ID::A)); int b_width = GetSize(cell->getPort(ID::B)); int y_width = GetSize(cell->getPort(ID::Y)); - int effective_a_width = a_width; - if (cell->type.in(ID($shift), ID($shiftx)) && is_signed) { - effective_a_width = std::max(y_width, a_width); - //is_signed = false; + // Behavior of the different shift cells: + // + // $shl, $sshl -- shifts left by the amount on B port, B always unsigned + // $shr, $sshr -- ditto right + // $shift, $shiftx -- shifts right by the amount on B port, B optionally signed + // + // Sign extension (if A signed): + // + // $shl, $shr, $shift -- only sign-extends up to size of Y, then shifts in zeroes + // $sshl, $sshr -- fully sign-extends + // $shiftx -- no sign extension + // + // Because $shl, $sshl only shift left, and $shl sign-extens up to size of Y, they + // are effectively the same. + + // the cap below makes sure we don't overflow in the arithmetic further down, though + // it makes the edge data invalid once a_width approaches the order of 2**30 + // (that ever happening is considered improbable) + int b_width_capped = min(b_width, 30); + + int b_high, b_low; + if (!is_b_signed) { + b_high = (1 << b_width_capped) - 1; + b_low = 0; + } else { + b_high = (1 << (b_width_capped - 1)) - 1; + b_low = -(1 << (b_width_capped - 1)); } - // how far the maximum value of B is able to shift - int b_range = (1<type.in(ID($shl), ID($sshl))) { - // << and <<< - b_range_upper = a_width + b_range; + b_range_upper = a_width + b_high; if (is_signed) b_range_upper -= 1; - a_range_lower = max(0, i - b_range); + a_range_lower = max(0, i - b_high); a_range_upper = min(i+1, a_width); - } else if (cell->type.in(ID($shr), ID($sshr)) || (cell->type.in(ID($shift), ID($shiftx)) && !is_b_signed)){ - // >> and >>> + } else if (cell->type.in(ID($shr), ID($sshr)) || (cell->type.in(ID($shift), ID($shiftx)) && !is_b_signed)) { b_range_upper = a_width; - a_range_lower = min(i, a_width - 1); // technically the min is unneccessary as b_range_upper check already skips any i >= a_width, but let's leave the logic in since this is hard enough - a_range_upper = min(i+1 + b_range, a_width); + a_range_lower = min(i, a_width - 1); + a_range_upper = min(i+1 + b_high, a_width); } else if (cell->type.in(ID($shift), ID($shiftx)) && is_b_signed) { // can go both ways depending on sign of B // 2's complement range is different depending on direction - int b_range_left = (1<<(b_width - 1)); - int b_range_right = (1<<(b_width - 1)) - 1; - b_range_upper = effective_a_width + b_range_left; - a_range_lower = max(0, i - b_range_left); + b_range_upper = a_width - b_low; + a_range_lower = max(0, i + b_low); if (is_signed) a_range_lower = min(a_range_lower, a_width - 1); - a_range_upper = min(i+1 + b_range_right, a_width); + a_range_upper = min(i+1 + b_high, a_width); + } else { + log_assert(false && "unreachable"); } if (i < b_range_upper) { for (int k = a_range_lower; k < a_range_upper; k++) db->add_edge(cell, ID::A, k, ID::Y, i, -1); } else { - // the only possible influence value is sign extension + // only influence is through sign extension if (is_signed) db->add_edge(cell, ID::A, a_width - 1, ID::Y, i, -1); } for (int k = 0; k < b_width; k++) { - if (cell->type.in(ID($shl), ID($sshl)) && a_width == 1 && is_signed) { - int skip = (1<<(k+1)); - int base = skip -1; - if (i % skip != base && i - a_width + 2 < 1 << b_width) - db->add_edge(cell, ID::B, k, ID::Y, i, -1); - } else if (true && cell->type.in(ID($shift), ID($shiftx)) && a_width == 1 && is_signed && is_b_signed) { - if (k != b_width - 1) { - // can we jump into the zero-padding by toggling B[k]? - bool zpad_jump = (((y_width - i) & ((1 << (k + 1)) - 1)) != 0 \ - && (((y_width - i) & ~(1 << k)) < (1 << (b_width - 1)))); - if (((~(i - 1) & ((1 << (k + 1)) - 1)) != 0 && i < 1 << (b_width - 1)) || zpad_jump) + // left shifts + if (cell->type.in(ID($shl), ID($sshl))) { + if (a_width == 1 && is_signed) { + int skip = 1 << (k + 1); + int base = skip -1; + if (i % skip != base && i - a_width + 2 < 1 << b_width) + db->add_edge(cell, ID::B, k, ID::Y, i, -1); + } else if (is_signed) { + if (i - a_width + 2 < 1 << b_width) db->add_edge(cell, ID::B, k, ID::Y, i, -1); } else { - if ((y_width - 1 - i < (1 << (b_width - 1)) - 1) || (i < (1 << (b_width - 1)))) + if (i - a_width + 1 < 1 << b_width) db->add_edge(cell, ID::B, k, ID::Y, i, -1); } - } else if ((cell->type.in(ID($shr), ID($sshr)) || (cell->type.in(ID($shift), ID($shiftx)) && !is_b_signed)) && is_signed) { - bool shift_in_bulk = i < a_width - 1; - // can we jump into the zero-padding by toggling B[k]? - bool zpad_jump = (((y_width - i) & ((1 << (k + 1)) - 1)) != 0 \ - && (((y_width - i) & ~(1 << k)) < (1 << b_width))); - - if (shift_in_bulk || (cell->type.in(ID($shr), ID($shift), ID($shiftx)) && zpad_jump)) - db->add_edge(cell, ID::B, k, ID::Y, i, -1); - } else if (cell->type.in(ID($sshl), ID($shl)) && is_signed) { - if (i - a_width + 2 < 1 << b_width) - db->add_edge(cell, ID::B, k, ID::Y, i, -1); - } else if (cell->type.in(ID($shl), ID($sshl))) { - if (i - a_width + 1 < 1 << b_width) - db->add_edge(cell, ID::B, k, ID::Y, i, -1); - } else if (cell->type.in(ID($shift), ID($shiftx)) && is_b_signed && !is_signed) { - if (i - a_width < (1 << (b_width - 1))) - db->add_edge(cell, ID::B, k, ID::Y, i, -1); - } else if (cell->type.in(ID($shift), ID($shiftx)) && is_b_signed && is_signed) { - if (k != b_width - 1) { - bool r_shift_in_bulk = i < a_width - 1; + // right shifts + } else if (cell->type.in(ID($shr), ID($sshr)) || (cell->type.in(ID($shift), ID($shiftx)) && !is_b_signed)) { + if (is_signed) { + bool shift_in_bulk = i < a_width - 1; // can we jump into the zero-padding by toggling B[k]? - bool r_zpad_jump = (((y_width - i) & ((1 << (k + 1)) - 1)) != 0 \ - && (((y_width - i) & ~(1 << k)) < (1 << (b_width - 1)))); - if (r_shift_in_bulk || r_zpad_jump || i - a_width + 2 <= 1 << (b_width - 1)) + bool zpad_jump = (((y_width - i) & ((1 << (k + 1)) - 1)) != 0 \ + && (((y_width - i) & ~(1 << k)) < (1 << b_width))); + + if (shift_in_bulk || (cell->type.in(ID($shr), ID($shift), ID($shiftx)) && zpad_jump)) db->add_edge(cell, ID::B, k, ID::Y, i, -1); } else { - if ((i - a_width + 2) <= (1 << (b_width - 1)) || (y_width - i) < (1 << (b_width - 1))) + if (i < a_width) + db->add_edge(cell, ID::B, k, ID::Y, i, -1); + } + // bidirectional shifts (positive B shifts right, negative left) + } else if (cell->type.in(ID($shift), ID($shiftx)) && is_b_signed) { + if (is_signed) { + if (k != b_width - 1) { + bool r_shift_in_bulk = i < a_width - 1; + // assuming B is positive, can we jump into the upper zero-padding by toggling B[k]? + bool r_zpad_jump = (((y_width - i) & ((1 << (k + 1)) - 1)) != 0 \ + && (((y_width - i) & ~(1 << k)) <= b_high)); + // assuming B is negative, can we influence Y[i] by toggling B[k]? + bool l = a_width - 2 - i >= b_low; + if (a_width == 1) { + // in case of a_width==1 we go into more detailed reasoning + l = l && (~(i - a_width) & ((1 << (k + 1)) - 1)) != 0; + } + if (r_shift_in_bulk || r_zpad_jump || l) + db->add_edge(cell, ID::B, k, ID::Y, i, -1); + } else { + if (y_width - i <= b_high || a_width - 2 - i >= b_low) + db->add_edge(cell, ID::B, k, ID::Y, i, -1); + } + } else { + if (a_width - 1 - i >= b_low) db->add_edge(cell, ID::B, k, ID::Y, i, -1); } } else { - if (i < effective_a_width) - db->add_edge(cell, ID::B, k, ID::Y, i, -1); + log_assert(false && "unreachable"); } } - } } From cb86efa50c69fd8c949c44d50dfbb81056459faa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Fri, 19 Jan 2024 11:14:10 +0100 Subject: [PATCH 8/8] celledges: Add test of shift cells edge data --- tests/various/celledges_shift.ys | 1 + 1 file changed, 1 insertion(+) create mode 100644 tests/various/celledges_shift.ys diff --git a/tests/various/celledges_shift.ys b/tests/various/celledges_shift.ys new file mode 100644 index 00000000000..753c8641e58 --- /dev/null +++ b/tests/various/celledges_shift.ys @@ -0,0 +1 @@ +test_cell -s 1705659041 -n 100 -edges $shift $shiftx $shl $shr $sshl $sshr