From d2a04cca0e422ad73efe7364b395db07e7eedd28 Mon Sep 17 00:00:00 2001 From: Ethan Mahintorabi Date: Thu, 25 Jan 2024 17:00:05 +0000 Subject: [PATCH 1/3] write_verilog: Making sure BUF cells are converted to expressions. These were previously not being converted correctly leading to yosys internal cells being written to my netlist. Signed-off-by: Ethan Mahintorabi --- backends/verilog/verilog_backend.cc | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 47f1c4c2b70..8febf0a96bf 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1053,6 +1053,16 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf(";\n"); return true; } + + if (cell->type == ID($_BUF_)) { + f << stringf("%s" "assign ", indent.c_str()); + dump_sigspec(f, cell->getPort(ID::Y)); + f << stringf(" = "); + dump_attributes(f, "", cell->attributes, ' '); + dump_cell_expr_port(f, cell, "A", false); + f << stringf(";\n"); + return true; + } if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_))) { f << stringf("%s" "assign ", indent.c_str()); From 33fe2e46138f956827bbd057b8df6ed7af57841c Mon Sep 17 00:00:00 2001 From: Ethan Mahintorabi Date: Thu, 25 Jan 2024 17:39:18 +0000 Subject: [PATCH 2/3] fixes char* to string conversion issue Signed-off-by: Ethan Mahintorabi --- backends/verilog/verilog_backend.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 8febf0a96bf..51ea14bf4c7 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1058,7 +1058,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf("%s" "assign ", indent.c_str()); dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); - dump_attributes(f, "", cell->attributes, ' '); + dump_attributes(f, "", cell->attributes, " "); dump_cell_expr_port(f, cell, "A", false); f << stringf(";\n"); return true; From 3076875fffb5fd29ca177bc9a4245f05d3636099 Mon Sep 17 00:00:00 2001 From: Ethan Mahintorabi Date: Tue, 30 Jan 2024 00:56:07 +0000 Subject: [PATCH 3/3] removing call to dump_attributes to remove possibility of generating invalid verilog Signed-off-by: Ethan Mahintorabi --- backends/verilog/verilog_backend.cc | 1 - 1 file changed, 1 deletion(-) diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 51ea14bf4c7..41e51f3289b 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1058,7 +1058,6 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf("%s" "assign ", indent.c_str()); dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); - dump_attributes(f, "", cell->attributes, " "); dump_cell_expr_port(f, cell, "A", false); f << stringf(";\n"); return true;