From a84fa0a27727490884a8795eaee8f82335b5e2be Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 1 Feb 2024 10:28:36 +0100 Subject: [PATCH] connect: Do interpret selection arguments Instead of silently ignoring what would ordinarily be the selection arguments to a pass, interpret those and mark the support in the help message. --- passes/cmds/connect.cc | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index 1bd52aab258..65292ef92e9 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -47,7 +47,7 @@ struct ConnectPass : public Pass { { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" connect [-nomap] [-nounset] -set \n"); + log(" connect [-nomap] [-nounset] -set [selection]\n"); log("\n"); log("Create a connection. This is equivalent to adding the statement 'assign\n"); log(" = ;' to the Verilog input. Per default, all existing\n"); @@ -55,12 +55,12 @@ struct ConnectPass : public Pass { log("the -nounset option.\n"); log("\n"); log("\n"); - log(" connect [-nomap] -unset \n"); + log(" connect [-nomap] -unset [selection]\n"); log("\n"); log("Unconnect all existing drivers for the specified expression.\n"); log("\n"); log("\n"); - log(" connect [-nomap] [-assert] -port \n"); + log(" connect [-nomap] [-assert] -port [selection]\n"); log("\n"); log("Connect the specified cell port to the specified cell port.\n"); log("\n"); @@ -80,17 +80,6 @@ struct ConnectPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { - RTLIL::Module *module = nullptr; - for (auto mod : design->selected_modules()) { - if (module != nullptr) - log_cmd_error("Multiple modules selected: %s, %s\n", log_id(module->name), log_id(mod->name)); - module = mod; - } - if (module == nullptr) - log_cmd_error("No modules selected.\n"); - if (!module->processes.empty()) - log_cmd_error("Found processes in selected module.\n"); - bool flag_nounset = false, flag_nomap = false, flag_assert = false; std::string set_lhs, set_rhs, unset_expr; std::string port_cell, port_port, port_expr; @@ -128,6 +117,18 @@ struct ConnectPass : public Pass { } break; } + extra_args(args, argidx, design); + + RTLIL::Module *module = nullptr; + for (auto mod : design->selected_modules()) { + if (module != nullptr) + log_cmd_error("Multiple modules selected: %s, %s\n", log_id(module->name), log_id(mod->name)); + module = mod; + } + if (module == nullptr) + log_cmd_error("No modules selected.\n"); + if (!module->processes.empty()) + log_cmd_error("Found processes in selected module.\n"); SigMap sigmap; if (!flag_nomap)