From 3f457f23887456ae6c927f6fd2147f453c267672 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sun, 4 Feb 2024 23:20:38 +0100 Subject: [PATCH 1/4] ci: Fix CXXSTD typo --- .github/workflows/test-linux.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/test-linux.yml b/.github/workflows/test-linux.yml index 5d929f581e6..cd990d7bdae 100644 --- a/.github/workflows/test-linux.yml +++ b/.github/workflows/test-linux.yml @@ -111,7 +111,7 @@ jobs: shell: bash run: | make config-${CC%%-*} - make -j${{ env.procs }} CCXXSTD=${{ matrix.cpp_std }} CC=$CC CXX=$CC LD=$CC + make -j${{ env.procs }} CXXSTD=${{ matrix.cpp_std }} CC=$CC CXX=$CC LD=$CC - name: Run tests if: (matrix.cpp_std == 'c++11') && (matrix.compiler == 'gcc-11') From 97b8ee5ab958f1f2b73a74af2d0d113e815bdc4f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sun, 4 Feb 2024 23:29:46 +0100 Subject: [PATCH 2/4] ci: Get a dump of yosys-config into the build log --- .github/workflows/test-linux.yml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/.github/workflows/test-linux.yml b/.github/workflows/test-linux.yml index cd990d7bdae..70aa1f68e4c 100644 --- a/.github/workflows/test-linux.yml +++ b/.github/workflows/test-linux.yml @@ -118,3 +118,7 @@ jobs: shell: bash run: | make -j${{ env.procs }} test CXXSTD=${{ matrix.cpp_std }} CC=$CC CXX=$CC LD=$CC + + - name: Log yosys-config output + run: | + ./yosys-config From 0cdd4273b4aa0ac98ce99a9dc888965c96fed382 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 5 Feb 2024 15:41:50 +1300 Subject: [PATCH 3/4] ci: ignore yosys-config return code --- .github/workflows/test-linux.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/test-linux.yml b/.github/workflows/test-linux.yml index 70aa1f68e4c..28c17a6c0e0 100644 --- a/.github/workflows/test-linux.yml +++ b/.github/workflows/test-linux.yml @@ -121,4 +121,4 @@ jobs: - name: Log yosys-config output run: | - ./yosys-config + ./yosys-config || true From af1a5cfeb9b6cd9ed86adf04dd5aad688392b466 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 8 Feb 2024 17:46:00 +0100 Subject: [PATCH 4/4] Address `SigBit`/`SigSpec` confusion issues under c++20 --- passes/opt/opt_dff.cc | 2 +- passes/opt/opt_ffinv.cc | 3 ++- passes/opt/opt_lut.cc | 8 ++++++-- passes/pmgen/ice40_dsp.pmg | 4 ++-- passes/pmgen/xilinx_dsp.pmg | 4 ++-- passes/pmgen/xilinx_dsp48a.pmg | 4 ++-- passes/pmgen/xilinx_dsp_CREG.pmg | 2 +- passes/pmgen/xilinx_dsp_cascade.pmg | 4 ++-- passes/techmap/extract_fa.cc | 2 +- 9 files changed, 19 insertions(+), 14 deletions(-) diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index f090d20b2e8..b77be45151b 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -353,7 +353,7 @@ struct OptDffWorker // Try a more complex conversion to plain async reset. State val_neutral = ff.pol_set ? State::S0 : State::S1; Const val_arst; - SigSpec sig_arst; + SigBit sig_arst; if (ff.sig_clr[0] == val_neutral) sig_arst = ff.sig_set[0]; else diff --git a/passes/opt/opt_ffinv.cc b/passes/opt/opt_ffinv.cc index 3f7b4bc4a71..d982ef2d239 100644 --- a/passes/opt/opt_ffinv.cc +++ b/passes/opt/opt_ffinv.cc @@ -38,6 +38,7 @@ struct OptFfInvWorker // - ... which has no other users // - all users of FF are LUTs bool push_d_inv(FfData &ff) { + log_assert(ff.width == 1); if (index.query_is_input(ff.sig_d)) return false; if (index.query_is_output(ff.sig_d)) @@ -90,7 +91,7 @@ struct OptFfInvWorker int flip_mask = 0; SigSpec sig_a = lut->getPort(ID::A); for (int i = 0; i < GetSize(sig_a); i++) { - if (index.sigmap(sig_a[i]) == index.sigmap(ff.sig_q)) { + if (index.sigmap(sig_a[i]) == index.sigmap(ff.sig_q[0])) { flip_mask |= 1 << i; } } diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc index 3907285f3e6..fbe61b6695a 100644 --- a/passes/opt/opt_lut.cc +++ b/passes/opt/opt_lut.cc @@ -167,7 +167,11 @@ struct OptLutWorker legal = false; break; } - if (sigmap(lut_input[dlogic_conn.first]) != sigmap(lut_dlogic.second->getPort(dlogic_conn.second))) + + if (lut_dlogic.second->getPort(dlogic_conn.second).size() != 1) + continue; + + if (sigmap(lut_input[dlogic_conn.first]) != sigmap(lut_dlogic.second->getPort(dlogic_conn.second)[0])) { log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type.c_str(), log_id(module), log_id(lut_dlogic.second)); log_debug(" LUT input A[%d] (wire %s) not connected to %s port %s (wire %s).\n", dlogic_conn.first, log_signal(lut_input[dlogic_conn.first]), lut_dlogic.second->type.c_str(), dlogic_conn.second.c_str(), log_signal(lut_dlogic.second->getPort(dlogic_conn.second))); @@ -314,7 +318,7 @@ struct OptLutWorker auto lutA = worklist.pop(); SigSpec lutA_input = sigmap(lutA->getPort(ID::A)); - SigSpec lutA_output = sigmap(lutA->getPort(ID::Y)[0]); + SigBit lutA_output = sigmap(lutA->getPort(ID::Y)[0]); int lutA_width = lutA->getParam(ID::WIDTH).as_int(); int lutA_arity = luts_arity[lutA]; pool &lutA_dlogic_inputs = luts_dlogic_inputs[lutA]; diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg index 4de4791228e..9099dd3c470 100644 --- a/passes/pmgen/ice40_dsp.pmg +++ b/passes/pmgen/ice40_dsp.pmg @@ -346,7 +346,7 @@ endmatch code argQ argD { if (clock != SigBit()) { - if (port(ff, \CLK) != clock) + if (port(ff, \CLK)[0] != clock) reject; if (param(ff, \CLK_POLARITY).as_bool() != clock_pol) reject; @@ -393,7 +393,7 @@ endmatch code argQ if (ff) { if (clock != SigBit()) { - if (port(ff, \CLK) != clock) + if (port(ff, \CLK)[0] != clock) reject; if (param(ff, \CLK_POLARITY).as_bool() != clock_pol) reject; diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index 0cd23c09da0..817a15a1e8f 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -415,7 +415,7 @@ match ff filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ) filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ - filter clock == SigBit() || port(ff, \CLK) == clock + filter clock == SigBit() || port(ff, \CLK)[0] == clock endmatch code argQ @@ -465,7 +465,7 @@ match ff filter GetSize(port(ff, \D)) >= offset + GetSize(argD) filter port(ff, \D).extract(offset, GetSize(argD)) == argD - filter clock == SigBit() || port(ff, \CLK) == clock + filter clock == SigBit() || port(ff, \CLK)[0] == clock endmatch code argQ diff --git a/passes/pmgen/xilinx_dsp48a.pmg b/passes/pmgen/xilinx_dsp48a.pmg index dce1b61b005..f3bd9bc9567 100644 --- a/passes/pmgen/xilinx_dsp48a.pmg +++ b/passes/pmgen/xilinx_dsp48a.pmg @@ -354,7 +354,7 @@ match ff filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ) filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ - filter clock == SigBit() || port(ff, \CLK) == clock + filter clock == SigBit() || port(ff, \CLK)[0] == clock endmatch code argQ @@ -404,7 +404,7 @@ match ff filter GetSize(port(ff, \D)) >= offset + GetSize(argD) filter port(ff, \D).extract(offset, GetSize(argD)) == argD - filter clock == SigBit() || port(ff, \CLK) == clock + filter clock == SigBit() || port(ff, \CLK)[0] == clock endmatch code argQ diff --git a/passes/pmgen/xilinx_dsp_CREG.pmg b/passes/pmgen/xilinx_dsp_CREG.pmg index 95379771a2d..49e79dd8723 100644 --- a/passes/pmgen/xilinx_dsp_CREG.pmg +++ b/passes/pmgen/xilinx_dsp_CREG.pmg @@ -135,7 +135,7 @@ match ff filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ) filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ - filter clock == SigBit() || port(ff, \CLK) == clock + filter clock == SigBit() || port(ff, \CLK)[0] == clock endmatch code argQ diff --git a/passes/pmgen/xilinx_dsp_cascade.pmg b/passes/pmgen/xilinx_dsp_cascade.pmg index 06601554c6b..29fc27dfed6 100644 --- a/passes/pmgen/xilinx_dsp_cascade.pmg +++ b/passes/pmgen/xilinx_dsp_cascade.pmg @@ -46,7 +46,7 @@ pattern xilinx_dsp_cascade udata > unextend udata >> chain longest_chain state next -state clock +state clock state AREG BREG // Variables used for subpatterns @@ -395,7 +395,7 @@ match ff filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ) filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ - filter clock == SigBit() || port(ff, \CLK) == clock + filter clock == SigBit() || port(ff, \CLK)[0] == clock endmatch code argQ diff --git a/passes/techmap/extract_fa.cc b/passes/techmap/extract_fa.cc index 117fdd54cf6..ec1979f3b6d 100644 --- a/passes/techmap/extract_fa.cc +++ b/passes/techmap/extract_fa.cc @@ -281,7 +281,7 @@ struct ExtractFaWorker void assign_new_driver(SigBit bit, SigBit new_driver) { Cell *cell = driver.at(bit); - if (sigmap(cell->getPort(ID::Y)) == bit) { + if (sigmap(cell->getPort(ID::Y)) == SigSpec(bit)) { cell->setPort(ID::Y, module->addWire(NEW_ID)); module->connect(bit, new_driver); }