From 75f517426f6255951a23964bc16468b8a4b45920 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Mon, 15 Apr 2024 13:55:54 +0200 Subject: [PATCH 01/51] Add generic topological sort and SCC detection This adds a generic non-recursive implementation of Tarjan's linear time SCC algorithm that produces components in topological order. It can be instantiated to work directly on any graph representation for which the enumerate_nodes and enumerate_successors interface can be implemented. --- kernel/topo_scc.h | 328 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 328 insertions(+) create mode 100644 kernel/topo_scc.h diff --git a/kernel/topo_scc.h b/kernel/topo_scc.h new file mode 100644 index 00000000000..0ae0e696b47 --- /dev/null +++ b/kernel/topo_scc.h @@ -0,0 +1,328 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2024 Jannis Harder + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef TOPO_SCC_H +#define TOPO_SCC_H + +#include "kernel/yosys.h" + +YOSYS_NAMESPACE_BEGIN + +class SigCellGraph { +public: + typedef int node_type; + + struct successor_enumerator { + std::vector>::const_iterator current, end; + bool finished() const { return current == end; } + node_type next() { + log_assert(!finished()); + node_type result = current->second; + ++current; + return result; + } + }; + + struct node_enumerator { + int current, end; + bool finished() const { return current == end; } + node_type next() { + log_assert(!finished()); + node_type result = current; + ++current; + return result; + } + }; + +private: + idict cell_ids; + idict sig_ids; + std::vector> edges; + std::vector> edge_ranges; + std::vector indices_; + int offset; + bool computed = false; + + void compute() { + offset = GetSize(sig_ids); + edge_ranges.clear(); + indices_.clear(); + indices_.resize(GetSize(sig_ids) + GetSize(cell_ids), -1); + + std::sort(edges.begin(), edges.end()); + auto last = std::unique(edges.begin(), edges.end()); + edges.erase(last, edges.end()); + auto edge = edges.begin(); + auto edge_end = edges.end(); + int range_begin = 0; + for (int node = -offset, node_end = GetSize(cell_ids); node != node_end; ++node) { + while (edge != edge_end && edge->first <= node) + ++edge; + int range_end = edge - edges.begin(); + edge_ranges.emplace_back(std::make_pair(range_begin, range_end)); + range_begin = range_end; + } + } + +public: + node_type node(RTLIL::Cell *cell) { return cell_ids(cell); } + node_type node(SigBit const &bit) { return ~sig_ids(bit); } + + bool is_cell(node_type node) { return node >= 0; } + bool is_sig(node_type node) { return node < 0; } + + Cell *cell(node_type node) { return node >= 0 ? cell_ids[node] : nullptr; } + SigBit sig(node_type node) { return node < 0 ? sig_ids[~node] : SigBit(); } + + template + void add_edge(Src &&src, Dst &&dst) { + computed = false; + node_type src_node = node(std::forward(src)); + node_type dst_node = node(std::forward(dst)); + edges.emplace_back(std::make_pair(src_node, dst_node)); + } + + node_enumerator enumerate_nodes() { + if (!computed) compute(); + return {-GetSize(sig_ids), GetSize(cell_ids)}; + } + + successor_enumerator enumerate_successors(node_type const &node) const { + auto range = edge_ranges[node + offset]; + return {edges.begin() + range.first, edges.begin() + range.second}; + } + + int &dfs_index(node_type const &node) { + return indices_[node + offset]; + } +}; + + +class IntGraph { +public: + typedef int node_type; + + struct successor_enumerator { + std::vector>::const_iterator current, end; + bool finished() const { return current == end; } + node_type next() { + log_assert(!finished()); + node_type result = current->second; + ++current; + return result; + } + }; + + struct node_enumerator { + int current, end; + bool finished() const { return current == end; } + node_type next() { + log_assert(!finished()); + node_type result = current; + ++current; + return result; + } + }; + +private: + std::vector> edges; + std::vector> edge_ranges; + std::vector indices_; + bool computed = false; + + void compute() { + edge_ranges.clear(); + + int node_end = 0; + for (auto const &edge : edges) + node_end = std::max(node_end, std::max(edge.first, edge.second) + 1); + indices_.clear(); + indices_.resize(node_end, -1); + + std::sort(edges.begin(), edges.end()); + auto last = std::unique(edges.begin(), edges.end()); + edges.erase(last, edges.end()); + auto edge = edges.begin(); + auto edge_end = edges.end(); + int range_begin = 0; + for (int node = 0; node != node_end; ++node) { + while (edge != edge_end && edge->first <= node) + ++edge; + int range_end = edge - edges.begin(); + edge_ranges.emplace_back(std::make_pair(range_begin, range_end)); + range_begin = range_end; + } + } + +public: + void add_edge(int src, int dst) { + log_assert(src >= 0); + log_assert(dst >= 0); + computed = false; + edges.emplace_back(std::make_pair(src, dst)); + } + + node_enumerator enumerate_nodes() { + if (!computed) compute(); + return {0, GetSize(indices_)}; + } + + successor_enumerator enumerate_successors(int node) const { + auto range = edge_ranges[node]; + return {edges.begin() + range.first, edges.begin() + range.second}; + } + + int &dfs_index(node_type const &node) { + return indices_[node]; + } +}; + +template +void topo_sorted_sccs(G &graph, ComponentCallback component) +{ + typedef typename G::node_enumerator node_enumerator; + typedef typename G::successor_enumerator successor_enumerator; + typedef typename G::node_type node_type; + + struct dfs_entry { + node_type node; + successor_enumerator successors; + int lowlink; + + dfs_entry(node_type node, successor_enumerator successors, int lowlink) : + node(node), successors(successors), lowlink(lowlink) + {} + }; + + std::vector dfs_stack; + std::vector component_stack; + int next_index = 0; + + + node_enumerator nodes = graph.enumerate_nodes(); + + // iterate over all nodes to ensure we process the whole graph + while (!nodes.finished()) { + node_type node = nodes.next(); + // only start a new search if the node wasn't visited yet + if (graph.dfs_index(node) >= 0) + continue; + + while (true) { + // at this point we're visiting the node for the first time during + // the DFS search + + // we record the timestamp of when we first visited the node as the + // dfs_index + int lowlink = next_index; + next_index++; + graph.dfs_index(node) = lowlink; + + // and we add the node to the component stack where it will remain + // until all nodes of the component containing this node are popped + component_stack.push_back(node); + + // then we start iterating over the successors of this node + successor_enumerator successors = graph.enumerate_successors(node); + while (true) { + if (successors.finished()) { + // when we processed all successors, i.e. when we visited + // the complete DFS subtree rooted at the current node, we + // first check whether the current node is a SCC root + // + // (why this check identifies SCC roots is out of scope for + // this comment, see other material on Tarjan's SCC + // algorithm) + if (lowlink == graph.dfs_index(node)) { + // the SCC containing the current node is at the top of + // the component stack, with the current node at the bottom + int current = GetSize(component_stack); + do { + --current; + } while (component_stack[current] != node); + + // we invoke the callback with a pointer range of the + // nodes in the SCC + + node_type *stack_ptr = component_stack.data(); + node_type *component_begin = stack_ptr + current; + node_type *component_end = stack_ptr + component_stack.size(); + + // note that we allow the callback to permute the nodes + // in this range as well as to modify dfs_index of the + // nodes in the SCC. + component(component_begin, component_end); + + // by setting the dfs_index of all already emitted + // nodes to INT_MAX, we don't need a separate check for + // whether successor nodes are still on the component + // stack before updating the lowlink value + for (; component_begin != component_end; ++component_begin) + graph.dfs_index(*component_begin) = INT_MAX; + component_stack.resize(current); + } + + // after checking for a completed SCC the DFS either + // continues the search at the parent node or returns to + // the outer loop if we already are at the root node. + if (dfs_stack.empty()) + goto next_search; + auto &dfs_top = dfs_stack.back(); + + node = dfs_top.node; + successors = std::move(dfs_top.successors); + + // the parent's lowlink is updated when returning + lowlink = min(lowlink, dfs_top.lowlink); + dfs_stack.pop_back(); + // continue checking the remaining successors of the parent node. + } else { + node_type succ = successors.next(); + if (graph.dfs_index(succ) < 0) { + // if the successor wasn't visted yet, the DFS recurses + // into the successor + + // we save the state for this node and make the + // successor the current node. + dfs_stack.emplace_back(node, std::move(successors), lowlink); + node = succ; + + // this break gets us to the section corresponding to + // the function entry in the recursive version + break; + } else { + // the textbook version guards this update with a check + // whether the successor is still on the component + // stack. If the successor node was already visisted + // but is not on the component stack, it must be part + // of an already emitted SCC. We can avoid this check + // by setting the DFS index of all nodes in a SCC to + // INT_MAX when the SCC is emitted. + lowlink = min(lowlink, graph.dfs_index(succ)); + } + } + } + } + next_search:; + } +} + +YOSYS_NAMESPACE_END + +#endif From 5e874dd95833a1c88fb2cc34300680f745efaf7e Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Mon, 15 Apr 2024 14:01:10 +0200 Subject: [PATCH 02/51] kernel/log: Add log_str helper for custom log_* functions/overloads When implementing custom log_... functions or custom overloads for the core log functions like log_signal it is necessary to return `char *` that are valid long enough. The log_... functions implemented in log.cc use either `log_id_cache` or `string_buf` which both are cleared on log_pop. This commit adds a public `log_str` function which stores its argument in the `log_id_cache` and returns the stored copy, such that custom log functions outside of log.cc can also create strings that remain valid until the next `log_pop`. --- kernel/log.cc | 10 ++++++++++ kernel/log.h | 2 ++ 2 files changed, 12 insertions(+) diff --git a/kernel/log.cc b/kernel/log.cc index 9a61e8f08b3..55895da06d7 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -662,6 +662,16 @@ const char *log_id(const RTLIL::IdString &str) return p+1; } +const char *log_str(const char *str) +{ + log_id_cache.push_back(strdup(str)); + return log_id_cache.back(); +} + +const char *log_str(std::string const &str) { + return log_str(str.c_str()); +} + void log_module(RTLIL::Module *module, std::string indent) { std::stringstream buf; diff --git a/kernel/log.h b/kernel/log.h index 53aae58c6bc..4b90cf9dceb 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -206,6 +206,8 @@ void log_check_expected(); const char *log_signal(const RTLIL::SigSpec &sig, bool autoint = true); const char *log_const(const RTLIL::Const &value, bool autoint = true); const char *log_id(const RTLIL::IdString &id); +const char *log_str(const char *str); +const char *log_str(std::string const &str); template static inline const char *log_id(T *obj, const char *nullstr = nullptr) { if (nullstr && obj == nullptr) From 71fbf0b48cc9831ef31bbc35e885f87923c78794 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Mon, 15 Apr 2024 14:08:58 +0200 Subject: [PATCH 03/51] kernel/rtlil: Add `SigBit operator[](int offset)` to `SigChunk` This is already supported by `SigSpec` and since both `SigChunk` and `SigSpec` implement `extract` which is the multi-bit variant of this, there is no good reason for `SigChunk` to not support `SigBit operator[](int offset)`. --- kernel/rtlil.cc | 14 ++++++++++++++ kernel/rtlil.h | 1 + 2 files changed, 15 insertions(+) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index a6aebaa4258..07fb4a1b91c 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3733,6 +3733,20 @@ RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const return ret; } +RTLIL::SigBit RTLIL::SigChunk::operator[](int offset) const +{ + log_assert(offset >= 0); + log_assert(offset <= width); + RTLIL::SigBit ret; + if (wire) { + ret.wire = wire; + ret.offset = this->offset + offset; + } else { + ret.data = data[offset]; + } + return ret; +} + bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const { if (wire && other.wire) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index f9da2949508..685acf90426 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -769,6 +769,7 @@ struct RTLIL::SigChunk SigChunk(const RTLIL::SigBit &bit); RTLIL::SigChunk extract(int offset, int length) const; + RTLIL::SigBit operator[](int offset) const; inline int size() const { return width; } inline bool is_wire() const { return wire != NULL; } From 1f0ddf4d3684bf58f7ed99ab0c56d89b3df8b04c Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Mon, 15 Apr 2024 14:12:16 +0200 Subject: [PATCH 04/51] drivertools: Utility code for indexing and traversing signal drivers It adds `DriveBit`, `DriveChunk` and `DriveSpec` types which are similar to `SigBit`, `SigChunk` and `SigSpec` but can also directly represent cell ports, undriven bits and multiple drivers. For indexing an RTLIL module and for querying signal drivers it comes with a `DriverMap` type which is somewhat similar to a `SigMap` but is guaranteed to produce signal drivers as returned representatives. A `DriverMap` can also optionally preserve connections via intermediate wires (e.g. querying the driver of a cell input port will return a connected intermediate wire, querying the driver of that wire will return the cell output port that's driving the wire). --- Makefile | 2 + kernel/drivertools.cc | 946 +++++++++++++++++++++++++++++ kernel/drivertools.h | 1317 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 2265 insertions(+) create mode 100644 kernel/drivertools.cc create mode 100644 kernel/drivertools.h diff --git a/Makefile b/Makefile index cbf834007fc..a4c8680b8c8 100644 --- a/Makefile +++ b/Makefile @@ -558,6 +558,7 @@ $(eval $(call add_include_file,kernel/celltypes.h)) $(eval $(call add_include_file,kernel/consteval.h)) $(eval $(call add_include_file,kernel/constids.inc)) $(eval $(call add_include_file,kernel/cost.h)) +$(eval $(call add_include_file,kernel/drivertools.h)) $(eval $(call add_include_file,kernel/ff.h)) $(eval $(call add_include_file,kernel/ffinit.h)) $(eval $(call add_include_file,kernel/ffmerge.h)) @@ -598,6 +599,7 @@ $(eval $(call add_include_file,backends/rtlil/rtlil_backend.h)) OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o OBJS += kernel/binding.o OBJS += kernel/cellaigs.o kernel/celledges.o kernel/satgen.o kernel/scopeinfo.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o kernel/fmt.o +OBJS += kernel/drivertools.o ifeq ($(ENABLE_ZLIB),1) OBJS += kernel/fstdata.o endif diff --git a/kernel/drivertools.cc b/kernel/drivertools.cc new file mode 100644 index 00000000000..499a9399c46 --- /dev/null +++ b/kernel/drivertools.cc @@ -0,0 +1,946 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2024 Jannis Harder + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/drivertools.h" + +YOSYS_NAMESPACE_BEGIN + +DriveBit::DriveBit(SigBit const &bit) +{ + if (bit.is_wire()) + *this = DriveBitWire(bit.wire, bit.offset); + else + *this = bit.data; +} + +void DriveBit::merge(DriveBit const &other) +{ + if (other.type_ == DriveType::NONE) + return; + if (type_ == DriveType::NONE) { + *this = other; + return; + } + if (type_ != DriveType::MULTIPLE) { + DriveBitMultiple multi(std::move(*this)); + *this = std::move(multi); + } + multiple().merge(other); +} + + +void DriveBitMultiple::merge(DriveBit const &single) +{ + if (single.type() == DriveType::NONE) + return; + if (single.type() == DriveType::MULTIPLE) { + merge(single.multiple()); + return; + } + multiple_.emplace(single); +} + +void DriveBitMultiple::merge(DriveBit &&single) +{ + if (single.type() == DriveType::NONE) + return; + if (single.type() == DriveType::MULTIPLE) { + merge(std::move(single.multiple())); + return; + } + multiple_.emplace(std::move(single)); +} + +DriveBitMultiple DriveChunkMultiple::operator[](int i) const +{ + DriveBitMultiple result; + for (auto const &single : multiple_) + result.merge(single[i]); + return result; +} + + +bool DriveChunkWire::can_append(DriveBitWire const &bit) const +{ + return bit.wire == wire && bit.offset == offset + width; +} + +bool DriveChunkWire::try_append(DriveBitWire const &bit) +{ + if (!can_append(bit)) + return false; + width += 1; + return true; +} + +bool DriveChunkWire::try_append(DriveChunkWire const &chunk) +{ + if (chunk.wire != wire || chunk.offset != offset + width) + return false; + width += chunk.width; + return true; +} + +bool DriveChunkPort::can_append(DriveBitPort const &bit) const +{ + return bit.cell == cell && bit.port == port && bit.offset == offset + width; +} + +bool DriveChunkPort::try_append(DriveBitPort const &bit) +{ + if (!can_append(bit)) + return false; + width += 1; + return true; +} + +bool DriveChunkPort::try_append(DriveChunkPort const &chunk) +{ + if (chunk.cell != cell || chunk.port != port || chunk.offset != offset + width) + return false; + width += chunk.width; + return true; +} + +bool DriveChunkMarker::can_append(DriveBitMarker const &bit) const +{ + return bit.marker == marker && bit.offset == offset + width; +} + +bool DriveChunkMarker::try_append(DriveBitMarker const &bit) +{ + if (!can_append(bit)) + return false; + width += 1; + return true; +} + +bool DriveChunkMarker::try_append(DriveChunkMarker const &chunk) +{ + if (chunk.marker != marker || chunk.offset != offset + width) + return false; + width += chunk.width; + return true; +} + + +bool DriveChunkMultiple::can_append(DriveBitMultiple const &bit) const +{ + if (bit.multiple().size() != multiple_.size()) + return false; + + int const_drivers = 0; + for (DriveChunk const &single : multiple_) + if (single.is_constant()) + const_drivers += 1; + + if (const_drivers > 1) + return false; + + for (DriveBit const &single : bit.multiple()) + if (single.is_constant()) + const_drivers -= 1; + + if (const_drivers != 0) + return false; + + for (DriveChunk const &single : multiple_) + { + switch (single.type()) + { + case DriveType::CONSTANT: { + } break; + case DriveType::WIRE: { + auto const &wire = single.wire(); + DriveBit next = DriveBitWire(wire.wire, wire.offset + wire.width); + if (!bit.multiple().count(next)) + return false; + } break; + case DriveType::PORT: { + auto const &port = single.port(); + DriveBit next = DriveBitPort(port.cell, port.port, port.offset + port.width); + if (!bit.multiple().count(next)) + return false; + } break; + case DriveType::MARKER: { + auto const &marker = single.marker(); + DriveBit next = DriveBitMarker(marker.marker, marker.offset + marker.width); + if (!bit.multiple().count(next)) + return false; + } break; + default: + return false; + } + } + + return true; +} + +bool DriveChunkMultiple::can_append(DriveChunkMultiple const &chunk) const +{ + if (chunk.multiple().size() != multiple_.size()) + return false; + + int const_drivers = 0; + for (DriveChunk const &single : multiple_) + if (single.is_constant()) + const_drivers += 1; + + if (const_drivers > 1) + return false; + + for (DriveChunk const &single : chunk.multiple()) + if (single.is_constant()) + const_drivers -= 1; + + if (const_drivers != 0) + return false; + + for (DriveChunk const &single : multiple_) + { + switch (single.type()) + { + case DriveType::CONSTANT: { + } break; + case DriveType::WIRE: { + auto const &wire = single.wire(); + DriveChunk next = DriveChunkWire(wire.wire, wire.offset + wire.width, chunk.size()); + if (!chunk.multiple().count(next)) + return false; + } break; + case DriveType::PORT: { + auto const &port = single.port(); + DriveChunk next = DriveChunkPort(port.cell, port.port, port.offset + port.width, chunk.size()); + if (!chunk.multiple().count(next)) + return false; + } break; + case DriveType::MARKER: { + auto const &marker = single.marker(); + DriveChunk next = DriveChunkMarker(marker.marker, marker.offset + marker.width, chunk.size()); + if (!chunk.multiple().count(next)) + return false; + } break; + default: + return false; + } + } + + return true; +} + +bool DriveChunkMultiple::try_append(DriveBitMultiple const &bit) +{ + if (!can_append(bit)) + return false; + width_ += 1; + State constant; + + for (DriveBit const &single : bit.multiple()) + if (single.is_constant()) + constant = single.constant(); + + for (DriveChunk &single : multiple_) + { + switch (single.type()) + { + case DriveType::CONSTANT: { + single.constant().bits.push_back(constant); + } break; + case DriveType::WIRE: { + single.wire().width += 1; + } break; + case DriveType::PORT: { + single.port().width += 1; + } break; + case DriveType::MARKER: { + single.marker().width += 1; + } break; + default: + log_abort(); + } + } + return true; +} + +bool DriveChunkMultiple::try_append(DriveChunkMultiple const &chunk) +{ + if (!can_append(chunk)) + return false; + int width = chunk.size(); + width_ += width; + Const constant; + + for (DriveChunk const &single : chunk.multiple()) + if (single.is_constant()) + constant = single.constant(); + + for (DriveChunk &single : multiple_) + { + switch (single.type()) + { + case DriveType::CONSTANT: { + auto &bits = single.constant().bits; + bits.insert(bits.end(), constant.bits.begin(), constant.bits.end()); + } break; + case DriveType::WIRE: { + single.wire().width += width; + } break; + case DriveType::PORT: { + single.port().width += width; + } break; + case DriveType::MARKER: { + single.marker().width += width; + } break; + default: + log_abort(); + } + } + return true; +} + +bool DriveChunk::can_append(DriveBit const &bit) const +{ + if (size() == 0) + return true; + if (bit.type() != type_) + return false; + switch (type_) + { + case DriveType::NONE: + return true; + case DriveType::CONSTANT: + return true; + case DriveType::WIRE: + return wire_.can_append(bit.wire()); + case DriveType::PORT: + return port_.can_append(bit.port()); + case DriveType::MULTIPLE: + return multiple_.can_append(bit.multiple()); + default: + log_abort(); + } +} + +bool DriveChunk::try_append(DriveBit const &bit) +{ + if (size() == 0) + *this = bit; + if (bit.type() != type_) + return false; + switch (type_) + { + case DriveType::NONE: + none_ += 1; + return true; + case DriveType::CONSTANT: + constant_.bits.push_back(bit.constant()); + return true; + case DriveType::WIRE: + return wire_.try_append(bit.wire()); + case DriveType::PORT: + return port_.try_append(bit.port()); + case DriveType::MULTIPLE: + return multiple_.try_append(bit.multiple()); + default: + log_abort(); + } +} + + +bool DriveChunk::try_append(DriveChunk const &chunk) +{ + if (size() == 0) + *this = chunk; + if (chunk.type_ != type_) + return false; + switch (type_) + { + case DriveType::NONE: + none_ += chunk.none_; + return true; + case DriveType::CONSTANT: + constant_.bits.insert(constant_.bits.end(), chunk.constant_.bits.begin(), chunk.constant_.bits.end()); + return true; + case DriveType::WIRE: + return wire_.try_append(chunk.wire()); + case DriveType::PORT: + return port_.try_append(chunk.port()); + case DriveType::MARKER: + return marker_.try_append(chunk.marker()); + case DriveType::MULTIPLE: + return multiple_.try_append(chunk.multiple()); + } + log_abort(); +} + +void DriveSpec::append(DriveBit const &bit) +{ + hash_ = 0; + if (!packed()) { + bits_.push_back(bit); + width_ += 1; + return; + } + + if (chunks_.empty() || !chunks_.back().try_append(bit)) + chunks_.emplace_back(bit); + width_ += 1; +} + +void DriveSpec::append(DriveChunk const &chunk) +{ + hash_ = 0; + pack(); + if (chunks_.empty() || !chunks_.back().try_append(chunk)) + chunks_.emplace_back(chunk); + width_ += chunk.size(); +} + +void DriveSpec::pack() const { + if (bits_.empty()) + return; + std::vector bits(std::move(bits_)); + for (auto &bit : bits) + if (chunks_.empty() || !chunks_.back().try_append(bit)) + chunks_.emplace_back(std::move(bit)); +} + +void DriveSpec::unpack() const { + if (chunks_.empty()) + return; + for (auto &chunk : chunks_) + { + for (int i = 0, width = chunk.size(); i != width; ++i) + { + bits_.emplace_back(chunk[i]); + } + } + chunks_.clear(); +} + +void DriveSpec::compute_width() +{ + width_ = 0; + for (auto const &chunk : chunks_) + width_ += chunk.size(); +} + +void DriverMap::DriveBitGraph::add_edge(DriveBitId src, DriveBitId dst) +{ + if (first_edges.emplace(src, dst).first->second == dst) + return; + if (second_edges.emplace(src, dst).first->second == dst) + return; + more_edges[src].emplace(dst); +} + +DriverMap::DriveBitId DriverMap::DriveBitGraph::pop_edge(DriveBitId src) +{ + // TODO unused I think? + auto found_more = more_edges.find(src); + if (found_more != more_edges.end()) { + auto result = found_more->second.pop(); + if (found_more->second.empty()) + more_edges.erase(found_more); + return result; + } + + auto found_second = second_edges.find(src); + if (found_second != second_edges.end()) { + auto result = found_second->second; + second_edges.erase(found_second); + return result; + } + + auto found_first = first_edges.find(src); + if (found_first != first_edges.end()) { + auto result = found_first->second; + first_edges.erase(found_first); + return result; + } + + return DriveBitId(); +} + +void DriverMap::DriveBitGraph::clear(DriveBitId src) +{ + first_edges.erase(src); + second_edges.erase(src); + more_edges.erase(src); +} + +bool DriverMap::DriveBitGraph::contains(DriveBitId src) +{ + return first_edges.count(src); +} + +int DriverMap::DriveBitGraph::count(DriveBitId src) +{ + if (!first_edges.count(src)) + return 0; + if (!second_edges.count(src)) + return 1; + auto found = more_edges.find(src); + if (found == more_edges.end()) + return 2; + return GetSize(found->second); +} + +DriverMap::DriveBitId DriverMap::DriveBitGraph::at(DriveBitId src, int index) +{ + if (index == 0) + return first_edges.at(src); + else if (index == 1) + return second_edges.at(src); + else + return *more_edges.at(src).element(index - 2); +} + + +DriverMap::BitMode DriverMap::bit_mode(DriveBit const &bit) +{ + switch (bit.type()) + { + case DriveType::NONE: + return BitMode::NONE; + case DriveType::CONSTANT: + // TODO how to handle Sx here? + return bit.constant() == State::Sz ? BitMode::NONE : BitMode::DRIVER; + case DriveType::WIRE: { + auto const &wire = bit.wire(); + bool driver = wire.wire->port_input; + bool driven = wire.wire->port_output; + + if (driver && !driven) + return BitMode::DRIVER; + else if (driven && !driver) + return BitMode::DRIVEN; + else if (driver && driven) + return BitMode::TRISTATE; + else + return keep_wire(bit.wire().wire) ? BitMode::KEEP : BitMode::NONE; + } + case DriveType::PORT: { + auto const &port = bit.port(); + bool driver = celltypes.cell_output(port.cell->type, port.port); + bool driven = celltypes.cell_input(port.cell->type, port.port); + if (driver && !driven) + return BitMode::DRIVER; + else if (driven && !driver) + return BitMode::DRIVEN_UNIQUE; + else + return BitMode::TRISTATE; + } + case DriveType::MARKER: { + // TODO user supplied classification + log_abort(); + } + default: + log_abort(); + } +} + +DriverMap::DriveBitId DriverMap::id_from_drive_bit(DriveBit const &bit) +{ + switch (bit.type()) + { + case DriveType::NONE: + return -1; + case DriveType::CONSTANT: + return (int)bit.constant(); + case DriveType::WIRE: { + auto const &wire_bit = bit.wire(); + int offset = next_offset; + auto insertion = wire_offsets.emplace(wire_bit.wire, offset); + if (insertion.second) { + if (wire_bit.wire->width == 1) { + log_assert(wire_bit.offset == 0); + isolated_drive_bits.emplace(offset, bit); + } else + drive_bits.emplace(offset, DriveBitWire(wire_bit.wire, 0)); + next_offset += wire_bit.wire->width; + } + return insertion.first->second.id + wire_bit.offset; + } + case DriveType::PORT: { + auto const &port_bit = bit.port(); + auto key = std::make_pair(port_bit.cell, port_bit.port); + int offset = next_offset; + auto insertion = port_offsets.emplace(key, offset); + if (insertion.second) { + int width = port_bit.cell->connections().at(port_bit.port).size(); + if (width == 1 && offset == 0) { + log_assert(port_bit.offset == 0); + isolated_drive_bits.emplace(offset, bit); + } else + drive_bits.emplace(offset, DriveBitPort(port_bit.cell, port_bit.port, 0)); + next_offset += width; + } + return insertion.first->second.id + port_bit.offset; + } + default: + log_assert(false && "unsupported DriveType in DriverMap"); + } + log_abort(); +} + +DriveBit DriverMap::drive_bit_from_id(DriveBitId id) +{ + auto found_isolated = isolated_drive_bits.find(id); + if (found_isolated != isolated_drive_bits.end()) + return found_isolated->second; + + auto found = drive_bits.upper_bound(id); + if (found == drive_bits.begin()) { + return id < 0 ? DriveBit() : DriveBit((State) id.id); + } + --found; + DriveBit result = found->second; + if (result.is_wire()) { + result.wire().offset += id.id - found->first.id; + } else { + log_assert(result.is_port()); + result.port().offset += id.id - found->first.id; + } + return result; +} + +void DriverMap::connect_directed_merge(DriveBitId driven_id, DriveBitId driver_id) +{ + if (driven_id == driver_id) + return; + + same_driver.merge(driven_id, driver_id); + + for (int i = 0, end = connected_drivers.count(driven_id); i != end; ++i) + connected_drivers.add_edge(driver_id, connected_drivers.at(driven_id, i)); + + connected_drivers.clear(driven_id); + + for (int i = 0, end = connected_undirected.count(driven_id); i != end; ++i) + connected_undirected.add_edge(driver_id, connected_undirected.at(driven_id, i)); + + connected_undirected.clear(driven_id); +} + +void DriverMap::connect_directed_buffer(DriveBitId driven_id, DriveBitId driver_id) +{ + connected_drivers.add_edge(driven_id, driver_id); +} + +void DriverMap::connect_undirected(DriveBitId a_id, DriveBitId b_id) +{ + connected_undirected.add_edge(a_id, b_id); + connected_undirected.add_edge(b_id, a_id); +} + +void DriverMap::add(Module *module) +{ + for (auto const &conn : module->connections()) + add(conn.first, conn.second); + + for (auto cell : module->cells()) + for (auto const &conn : cell->connections()) + add_port(cell, conn.first, conn.second); +} + +// Add a single bit connection to the driver map. +void DriverMap::add(DriveBit const &a, DriveBit const &b) +{ + DriveBitId a_id = id_from_drive_bit(a); + DriveBitId b_id = id_from_drive_bit(b); + + DriveBitId orig_a_id = a_id; + DriveBitId orig_b_id = b_id; + + a_id = same_driver.find(a_id); + b_id = same_driver.find(b_id); + + if (a_id == b_id) + return; + + BitMode a_mode = bit_mode(orig_a_id == a_id ? a : drive_bit_from_id(a_id)); + BitMode b_mode = bit_mode(orig_b_id == b_id ? b : drive_bit_from_id(b_id)); + + // If either bit is just a wire that we don't need to keep, merge and + // use the other end as representative bit. + if (a_mode == BitMode::NONE) + connect_directed_merge(a_id, b_id); + else if (b_mode == BitMode::NONE) + connect_directed_merge(b_id, a_id); + // If either bit requires a driven value and has a unique driver, merge + // and use the other end as representative bit. + else if (a_mode == BitMode::DRIVEN_UNIQUE && !(b_mode == BitMode::DRIVEN_UNIQUE || b_mode == BitMode::DRIVEN)) + connect_directed_buffer(a_id, b_id); + else if (b_mode == BitMode::DRIVEN_UNIQUE && !(b_mode == BitMode::DRIVEN_UNIQUE || b_mode == BitMode::DRIVEN)) + connect_directed_buffer(b_id, a_id); + // If either bit only drives a value, store a directed connection from + // it to the other bit. + else if (a_mode == BitMode::DRIVER) + connect_directed_buffer(b_id, a_id); + else if (b_mode == BitMode::DRIVER) + connect_directed_buffer(a_id, b_id); + // Otherwise we store an undirected connection which we will resolve + // during querying. + else + connect_undirected(a_id, b_id); + + return; +} + +// Specialized version that avoids unpacking +void DriverMap::add(SigSpec const &a, SigSpec const &b) +{ + log_assert(a.size() == b.size()); + auto const &a_chunks = a.chunks(); + auto const &b_chunks = b.chunks(); + + auto a_chunk = a_chunks.begin(); + auto a_end = a_chunks.end(); + int a_offset = 0; + + auto b_chunk = b_chunks.begin(); + int b_offset = 0; + + SigChunk tmp_a, tmp_b; + while (a_chunk != a_end) { + int a_width = a_chunk->width - a_offset; + if (a_width == 0) { + a_offset = 0; + ++a_chunk; + continue; + } + int b_width = b_chunk->width - b_offset; + if (b_width == 0) { + b_offset = 0; + ++b_chunk; + continue; + } + int width = std::min(a_width, b_width); + log_assert(width > 0); + + SigChunk const &a_subchunk = + a_offset == 0 && a_width == width ? *a_chunk : a_chunk->extract(a_offset, width); + SigChunk const &b_subchunk = + b_offset == 0 && b_width == width ? *b_chunk : b_chunk->extract(b_offset, width); + + add(a_subchunk, b_subchunk); + + a_offset += width; + b_offset += width; + } +} + +void DriverMap::add_port(Cell *cell, IdString const &port, SigSpec const &b) +{ + int offset = 0; + for (auto const &chunk : b.chunks()) { + add(chunk, DriveChunkPort(cell, port, offset, chunk.width)); + offset += chunk.size(); + } +} + +void DriverMap::orient_undirected(DriveBitId id) +{ + pool &seen = orient_undirected_seen; + pool &drivers = orient_undirected_drivers; + dict &distance = orient_undirected_distance; + seen.clear(); + drivers.clear(); + + seen.emplace(id); + + for (int pos = 0; pos < GetSize(seen); ++pos) { + DriveBitId current = *seen.element(seen.size() - 1 - pos); + DriveBit bit = drive_bit_from_id(current); + + BitMode mode = bit_mode(bit); + + if (mode == BitMode::DRIVER || mode == BitMode::TRISTATE) + drivers.emplace(current); + + if (connected_drivers.contains(current)) + drivers.emplace(current); + + int undirected_driver_count = connected_undirected.count(current); + + for (int i = 0; i != undirected_driver_count; ++i) + seen.emplace(same_driver.find(connected_undirected.at(current, i))); + } + + if (drivers.empty()) + for (auto seen_id : seen) + drivers.emplace(seen_id); + + for (auto driver : drivers) + { + distance.clear(); + distance.emplace(driver, 0); + + for (int pos = 0; pos < GetSize(distance); ++pos) { + auto current_it = distance.element(distance.size() - 1 - pos); + + DriveBitId current = current_it->first; + int undirected_driver_count = connected_undirected.count(current); + + for (int i = 0; i != undirected_driver_count; ++i) + { + DriveBitId next = same_driver.find(connected_undirected.at(current, i)); + auto emplaced = distance.emplace(next, current_it->second + 1); + if (emplaced.first->second == current_it->second + 1) + connected_oriented.add_edge(next, current); + } + } + } + + for (auto seen_id : seen) + oriented_present.emplace(seen_id); +} + +DriveBit DriverMap::operator()(DriveBit const &bit) +{ + if (bit.type() == DriveType::MARKER || bit.type() == DriveType::NONE) + return bit; + if (bit.type() == DriveType::MULTIPLE) + { + DriveBit result; + for (auto const &inner : bit.multiple().multiple()) + result.merge((*this)(inner)); + return result; + } + + DriveBitId bit_id = id_from_drive_bit(bit); + + bit_id = same_driver.find(bit_id); + + DriveBit bit_repr = drive_bit_from_id(bit_id); + + BitMode mode = bit_mode(bit_repr); + + int implicit_driver_count = connected_drivers.count(bit_id); + if (connected_undirected.contains(bit_id) && !oriented_present.count(bit_id)) + orient_undirected(bit_id); + + DriveBit driver; + + if (mode == BitMode::DRIVER || mode == BitMode::TRISTATE) + driver = bit_repr; + + for (int i = 0; i != implicit_driver_count; ++i) + driver.merge(drive_bit_from_id(connected_drivers.at(bit_id, i))); + + int oriented_driver_count = connected_oriented.count(bit_id); + for (int i = 0; i != oriented_driver_count; ++i) + driver.merge(drive_bit_from_id(connected_oriented.at(bit_id, i))); + + return driver; +} + +DriveSpec DriverMap::operator()(DriveSpec spec) +{ + DriveSpec result; + + for (int i = 0, width = spec.size(); i != width; ++i) + result.append((*this)(spec[i])); + + return result; +} + +const char *log_signal(DriveChunkWire const &chunk) +{ + const char *id = log_id(chunk.wire->name); + if (chunk.is_whole()) + return id; + if (chunk.width == 1) + return log_str(stringf("%s [%d]", id, chunk.offset)); + return log_str(stringf("%s [%d:%d]", id, chunk.offset + chunk.width - 1, chunk.offset)); +} + + +const char *log_signal(DriveChunkPort const &chunk) +{ + const char *cell_id = log_id(chunk.cell->name); + const char *port_id = log_id(chunk.port); + if (chunk.is_whole()) + return log_str(stringf("%s <%s>", cell_id, port_id)); + if (chunk.width == 1) + return log_str(stringf("%s <%s> [%d]", cell_id, port_id, chunk.offset)); + return log_str(stringf("%s <%s> [%d:%d]", cell_id, port_id, chunk.offset + chunk.width - 1, chunk.offset)); +} + +const char *log_signal(DriveChunkMarker const &chunk) +{ + if (chunk.width == 1) + return log_str(stringf(" [%d]", chunk.marker, chunk.offset)); + return log_str(stringf(" [%d:%d]", chunk.marker, chunk.offset + chunk.width - 1, chunk.offset)); +} + +const char *log_signal(DriveChunk const &chunk) +{ + switch (chunk.type()) + { + case DriveType::NONE: + return log_str(stringf("", chunk.size())); + case DriveType::CONSTANT: + return log_const(chunk.constant()); + case DriveType::WIRE: + return log_signal(chunk.wire()); + case DriveType::PORT: + return log_signal(chunk.port()); + case DriveType::MARKER: + return log_signal(chunk.marker()); + case DriveType::MULTIPLE: { + std::string str = " + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef DRIVERTOOLS_H +#define DRIVERTOOLS_H + +#include + +#include "kernel/rtlil.h" +#include "kernel/sigtools.h" +#include "kernel/celltypes.h" + +YOSYS_NAMESPACE_BEGIN + +// TODO move implementation into a .cc file + +struct DriveBit; + +struct DriveChunkWire; +struct DriveChunkPort; +struct DriveChunkMarker; +struct DriveChunk; + +struct DriveSpec; + +const char *log_signal(DriveChunkWire const &chunk); +const char *log_signal(DriveChunkPort const &chunk); +const char *log_signal(DriveChunkMarker const &chunk); +const char *log_signal(DriveChunk const &chunk); +const char *log_signal(DriveSpec const &chunk); + +enum class DriveType : unsigned char +{ + NONE, + CONSTANT, + WIRE, + PORT, + MULTIPLE, + MARKER, +}; + +struct DriveBitWire +{ + Wire *wire; + int offset; + + DriveBitWire(Wire *wire, int offset) : wire(wire), offset(offset) {} + + bool operator==(const DriveBitWire &other) const + { + return wire == other.wire && offset == other.offset; + } + + bool operator<(const DriveBitWire &other) const + { + if (wire != other.wire) + return wire->name < other.wire->name; + return offset < other.offset; + } + + unsigned int hash() const + { + return mkhash_add(wire->name.hash(), offset); + } + + operator SigBit() const + { + return SigBit(wire, offset); + } +}; + +struct DriveBitPort +{ + Cell *cell; + IdString port; + int offset; + + DriveBitPort(Cell *cell, IdString port, int offset) : cell(cell), port(port), offset(offset) {} + + bool operator==(const DriveBitPort &other) const + { + return cell == other.cell && port == other.port && offset == other.offset; + } + + bool operator<(const DriveBitPort &other) const + { + if (cell != other.cell) + return cell->name < other.cell->name; + if (port != other.port) + return port < other.port; + return offset < other.offset; + } + + unsigned int hash() const + { + return mkhash_add(mkhash(cell->name.hash(), port.hash()), offset); + } +}; + + +struct DriveBitMarker +{ + int marker; + int offset; + + DriveBitMarker(int marker, int offset) : marker(marker), offset(offset) {} + + bool operator==(const DriveBitMarker &other) const + { + return marker == other.marker && offset == other.offset; + } + + bool operator<(const DriveBitMarker &other) const + { + if (marker != other.marker) + return marker < other.marker; + return offset < other.offset; + } + + unsigned int hash() const + { + return mkhash_add(marker, offset); + } + +}; + +struct DriveBitMultiple +{ +private: + pool multiple_; + +public: + DriveBitMultiple() {} + DriveBitMultiple(DriveBit const &single) + { + multiple_.emplace(single); + } + + pool const &multiple() const { return multiple_; } + + void merge(DriveBitMultiple const &other) + { + for (DriveBit const &single : other.multiple_) + merge(single); + } + + void merge(DriveBitMultiple &&other) + { + for (DriveBit &single : other.multiple_) + merge(std::move(single)); + } + + void merge(DriveBit const &single); + void merge(DriveBit &&single); + + bool operator==(const DriveBitMultiple &other) const + { + return multiple_ == other.multiple_; + } + + unsigned int hash() const + { + return multiple_.hash(); + } +}; + +struct DriveBit +{ +private: + DriveType type_ = DriveType::NONE; + union + { + State constant_; + DriveBitWire wire_; + DriveBitPort port_; + DriveBitMarker marker_; + DriveBitMultiple multiple_; + }; +public: + DriveBit() {} + + DriveBit(SigBit const &bit); + + DriveBit(DriveBit const &other) { *this = other; } + DriveBit(DriveBit &&other) { *this = other; } + + + DriveBit(State constant) { *this = constant; } + DriveBit(DriveBitWire const &wire) { *this = wire; } + DriveBit(DriveBitWire &&wire) { *this = wire; } + DriveBit(DriveBitPort const &port) { *this = port; } + DriveBit(DriveBitPort &&port) { *this = port; } + DriveBit(DriveBitMarker const &marker) { *this = marker; } + DriveBit(DriveBitMarker &&marker) { *this = marker; } + DriveBit(DriveBitMultiple const &multiple) { *this = multiple; } + DriveBit(DriveBitMultiple &&multiple) { *this = multiple; } + + ~DriveBit() { set_none(); } + + void set_none() + { + switch (type_) + { + case DriveType::NONE: + break; + case DriveType::CONSTANT: + break; + case DriveType::WIRE: + wire_.~DriveBitWire(); + break; + case DriveType::PORT: + port_.~DriveBitPort(); + break; + case DriveType::MARKER: + marker_.~DriveBitMarker(); + break; + case DriveType::MULTIPLE: + multiple_.~DriveBitMultiple(); + break; + } + type_ = DriveType::NONE; + } + + DriveBit &operator=(DriveBit const &other) + { + switch (other.type_) + { + case DriveType::NONE: + set_none(); + break; + case DriveType::CONSTANT: + *this = other.constant_; + break; + case DriveType::WIRE: + *this = other.wire_; + break; + case DriveType::PORT: + *this = other.port_; + break; + case DriveType::MARKER: + *this = other.marker_; + break; + case DriveType::MULTIPLE: + *this = other.multiple_; + break; + } + return *this; + } + + DriveBit &operator=(DriveBit &&other) + { + switch (other.type_) + { + case DriveType::NONE: + set_none(); + break; + case DriveType::CONSTANT: + *this = std::move(other.constant_); + break; + case DriveType::WIRE: + *this = std::move(other.wire_); + break; + case DriveType::PORT: + *this = std::move(other.port_); + break; + case DriveType::MARKER: + *this = std::move(other.marker_); + break; + case DriveType::MULTIPLE: + *this = std::move(other.multiple_); + break; + } + return *this; + } + + DriveBit &operator=(State constant) + { + set_none(); + constant_ = constant; + type_ = DriveType::CONSTANT; + return *this; + } + + DriveBit &operator=(DriveBitWire const &wire) + { + set_none(); + new (&wire_) DriveBitWire(wire); + type_ = DriveType::WIRE; + return *this; + } + + DriveBit &operator=(DriveBitWire &&wire) + { + set_none(); + new (&wire_) DriveBitWire(wire); + type_ = DriveType::WIRE; + return *this; + } + + DriveBit &operator=(DriveBitPort const &port) + { + set_none(); + new (&port_) DriveBitPort(port); + type_ = DriveType::PORT; + return *this; + } + + DriveBit &operator=(DriveBitPort &&port) + { + set_none(); + new (&port_) DriveBitPort(port); + type_ = DriveType::PORT; + return *this; + } + + DriveBit &operator=(DriveBitMarker const &marker) + { + set_none(); + new (&marker_) DriveBitMarker(marker); + type_ = DriveType::MARKER; + return *this; + } + + DriveBit &operator=(DriveBitMarker &&marker) + { + set_none(); + new (&marker_) DriveBitMarker(marker); + type_ = DriveType::MARKER; + return *this; + } + + DriveBit &operator=(DriveBitMultiple const &multiple) + { + set_none(); + if (multiple.multiple().empty()) + return *this; + new (&multiple_) DriveBitMultiple(multiple); + type_ = DriveType::MULTIPLE; + return *this; + } + + DriveBit &operator=(DriveBitMultiple &&multiple) + { + set_none(); + if (multiple.multiple().empty()) + return *this; + new (&multiple_) DriveBitMultiple(multiple); + type_ = DriveType::MULTIPLE; + return *this; + } + + unsigned int hash() const + { + unsigned int inner; + switch (type_) + { + case DriveType::NONE: + inner = 0; + break; + case DriveType::CONSTANT: + inner = constant_; + break; + case DriveType::WIRE: + inner = wire_.hash(); + break; + case DriveType::PORT: + inner = port_.hash(); + break; + case DriveType::MARKER: + inner = marker_.hash(); + break; + case DriveType::MULTIPLE: + inner = multiple_.hash(); + break; + } + return mkhash((unsigned int)type_, inner); + } + + bool operator==(const DriveBit &other) const + { + if (type_ != other.type_) + return false; + + switch (type_) + { + case DriveType::NONE: + return true; + case DriveType::CONSTANT: + return constant_ == other.constant_; + case DriveType::WIRE: + return wire_ == other.wire_; + case DriveType::PORT: + return port_ == other.port_; + case DriveType::MARKER: + return marker_ == other.marker_; + case DriveType::MULTIPLE: + return multiple_ == other.multiple_; + } + log_assert(false); + } + + bool operator!=(const DriveBit &other) const + { + return !(*this == other); + } + + bool operator<(const DriveBit &other) const + { + if (type_ != other.type_) + return type_ < other.type_; + switch (type_) + { + case DriveType::NONE: + return false; + case DriveType::CONSTANT: + return constant_ < other.constant_; + case DriveType::WIRE: + return wire_ < other.wire_; + case DriveType::PORT: + return port_ < other.port_; + case DriveType::MARKER: + return marker_ < other.marker_; + case DriveType::MULTIPLE: + log_assert(!"TODO"); + } + log_abort(); + } + + + DriveType type() const { return type_; } + + bool is_none() const { return type_ == DriveType::NONE; } + bool is_constant() const { return type_ == DriveType::CONSTANT; } + bool is_wire() const { return type_ == DriveType::WIRE; } + bool is_port() const { return type_ == DriveType::PORT; } + bool is_marker() const { return type_ == DriveType::MARKER; } + bool is_multiple() const { return type_ == DriveType::MULTIPLE; } + + State &constant() { log_assert(is_constant()); return constant_; } + State const &constant() const { log_assert(is_constant()); return constant_; } + DriveBitWire &wire() { log_assert(is_wire()); return wire_; } + DriveBitWire const &wire() const { log_assert(is_wire()); return wire_; } + DriveBitPort &port() { log_assert(is_port()); return port_; } + DriveBitPort const &port() const { log_assert(is_port()); return port_; } + DriveBitMarker &marker() { log_assert(is_marker()); return marker_; } + DriveBitMarker const &marker() const { log_assert(is_marker()); return marker_; } + DriveBitMultiple &multiple() { log_assert(is_multiple()); return multiple_; } + DriveBitMultiple const &multiple() const { log_assert(is_multiple()); return multiple_; } + + void merge(DriveBit const &other); + +}; + + +struct DriveChunkWire +{ + Wire *wire; + int offset; + int width; + + DriveChunkWire(Wire *wire, int offset, int width) : wire(wire), offset(offset), width(width) {} + DriveChunkWire(DriveBitWire const &bit) : wire(bit.wire), offset(bit.offset), width(1) {} + + int size() const { return width; } + + DriveBitWire operator[](int i) const + { + log_assert(i >= 0 && i < width); + return DriveBitWire(wire, offset + i); + } + + bool can_append(DriveBitWire const &bit) const; + bool try_append(DriveBitWire const &bit); + bool try_append(DriveChunkWire const &chunk); + + // Whether this chunk is a whole wire + bool is_whole() const { return offset == 0 && width == wire->width; } + + bool operator==(const DriveChunkWire &other) const + { + return wire == other.wire && offset == other.offset && width == other.width; + } + + bool operator<(const DriveChunkWire &other) const + { + if (wire != other.wire) + return wire->name < other.wire->name; + if (width != other.width) + return width < other.width; + return offset < other.offset; + } + + unsigned int hash() const + { + return mkhash_add(mkhash(wire->name.hash(), width), offset); + } + + explicit operator SigChunk() const + { + return SigChunk(wire, offset, width); + } +}; + +struct DriveChunkPort +{ + Cell *cell; + IdString port; + int offset; + int width; + + DriveChunkPort(Cell *cell, IdString port, int offset, int width) : + cell(cell), port(port), offset(offset), width(width) { } + DriveChunkPort(Cell *cell, IdString port) : + cell(cell), port(port), offset(0), width(GetSize(cell->connections().at(port))) { } + DriveChunkPort(Cell *cell, std::pair const &conn) : + cell(cell), port(conn.first), offset(0), width(GetSize(conn.second)) { } + DriveChunkPort(DriveBitPort const &bit) : + cell(bit.cell), port(bit.port), offset(bit.offset), width(1) { } + + int size() const { return width; } + + DriveBitPort operator[](int i) const + { + log_assert(i >= 0 && i < width); + return DriveBitPort(cell, port, offset + i); + } + + bool can_append(DriveBitPort const &bit) const; + bool try_append(DriveBitPort const &bit); + bool try_append(DriveChunkPort const &chunk); + + // Whether this chunk is a whole port + bool is_whole() const + { + return offset == 0 && width == cell->connections().at(port).size(); + } + + bool operator==(const DriveChunkPort &other) const + { + return cell == other.cell && port == other.port && offset == other.offset && width == other.width; + } + + bool operator<(const DriveChunkPort &other) const + { + if (cell != other.cell) + return cell->name < other.cell->name; + if (port != other.port) + return port < other.port; + if (width != other.width) + return width < other.width; + return offset < other.offset; + } + + unsigned int hash() const + { + return mkhash_add(mkhash(mkhash(cell->name.hash(), port.hash()), width), offset); + } +}; + + +struct DriveChunkMarker +{ + int marker; + int offset; + int width; + + DriveChunkMarker(int marker, int offset, int width) : + marker(marker), offset(offset), width(width) {} + DriveChunkMarker(DriveBitMarker const &bit) : + marker(bit.marker), offset(bit.offset), width(1) {} + + int size() const { return width; } + + DriveBitMarker operator[](int i) const + { + log_assert(i >= 0 && i < width); + return DriveBitMarker(marker, offset + i); + } + + bool can_append(DriveBitMarker const &bit) const; + bool try_append(DriveBitMarker const &bit); + bool try_append(DriveChunkMarker const &chunk); + + bool operator==(const DriveChunkMarker &other) const + { + return marker == other.marker && offset == other.offset && width == other.width; + } + + bool operator<(const DriveChunkMarker &other) const + { + if (marker != other.marker) + return marker < other.marker; + if (width != other.width) + return width < other.width; + return offset < other.offset; + } + + unsigned int hash() const + { + return mkhash_add(mkhash(marker, width), offset); + } +}; + +struct DriveChunkMultiple +{ +private: + mutable pool multiple_; + int width_; + +public: + pool const &multiple() const { return multiple_; } + + DriveChunkMultiple(DriveBitMultiple const &bit) : width_(1) { + for (auto const &bit : bit.multiple()) + multiple_.emplace(bit); + } + + int size() const { return width_; } + + DriveBitMultiple operator[](int i) const; + + bool can_append(DriveBitMultiple const &bit) const; + + bool try_append(DriveBitMultiple const &bit); + + + bool can_append(DriveChunkMultiple const &bit) const; + + bool try_append(DriveChunkMultiple const &bit); + + bool operator==(const DriveChunkMultiple &other) const + { + return width_ == other.width_ && multiple_ == other.multiple_; + } + + bool operator<(const DriveChunkMultiple &other) const + { + if (multiple_.size() < other.multiple_.size()) + + multiple_.sort(); + return false; // TODO implement, canonicalize order + } + + unsigned int hash() const + { + return mkhash(width_, multiple_.hash()); + } +}; + +struct DriveChunk +{ +private: + DriveType type_ = DriveType::NONE; + union + { + int none_; + Const constant_; + DriveChunkWire wire_; + DriveChunkPort port_; + DriveChunkMarker marker_; + DriveChunkMultiple multiple_; + }; + +public: + DriveChunk() { set_none(); } + + DriveChunk(DriveChunk const &other) { *this = other; } + DriveChunk(DriveChunk &&other) { *this = other; } + + DriveChunk(DriveBit const &other) { *this = other; } + + DriveChunk(Const const &constant) { *this = constant; } + DriveChunk(Const &&constant) { *this = constant; } + DriveChunk(DriveChunkWire const &wire) { *this = wire; } + DriveChunk(DriveChunkWire &&wire) { *this = wire; } + DriveChunk(DriveChunkPort const &port) { *this = port; } + DriveChunk(DriveChunkPort &&port) { *this = port; } + DriveChunk(DriveChunkMarker const &marker) { *this = marker; } + DriveChunk(DriveChunkMarker &&marker) { *this = marker; } + DriveChunk(DriveChunkMultiple const &multiple) { *this = multiple; } + DriveChunk(DriveChunkMultiple &&multiple) { *this = multiple; } + + ~DriveChunk() { set_none(); } + + DriveBit operator[](int i) const + { + switch (type_) + { + case DriveType::NONE: + return DriveBit(); + case DriveType::CONSTANT: + return constant_[i]; + case DriveType::WIRE: + return wire_[i]; + case DriveType::PORT: + return port_[i]; + case DriveType::MARKER: + return marker_[i]; + case DriveType::MULTIPLE: + return multiple_[i]; + } + log_abort(); + } + + void set_none(int width = 0) + { + switch (type_) + { + case DriveType::NONE: + none_ = width; + break; + case DriveType::CONSTANT: + constant_.~Const(); + break; + case DriveType::WIRE: + wire_.~DriveChunkWire(); + break; + case DriveType::PORT: + port_.~DriveChunkPort(); + break; + case DriveType::MARKER: + marker_.~DriveChunkMarker(); + break; + case DriveType::MULTIPLE: + multiple_.~DriveChunkMultiple(); + break; + } + type_ = DriveType::NONE; + none_ = width; + } + + DriveChunk &operator=(DriveChunk const &other) + { + switch (other.type_) + { + case DriveType::NONE: + set_none(other.none_); + break; + case DriveType::CONSTANT: + *this = other.constant_; + break; + case DriveType::WIRE: + *this = other.wire_; + break; + case DriveType::PORT: + *this = other.port_; + break; + case DriveType::MARKER: + *this = other.marker_; + break; + case DriveType::MULTIPLE: + *this = other.multiple_; + break; + } + return *this; + } + + DriveChunk &operator=(DriveChunk &&other) + { + switch (other.type_) + { + case DriveType::NONE: + set_none(other.none_); + break; + case DriveType::CONSTANT: + *this = std::move(other.constant_); + break; + case DriveType::WIRE: + *this = std::move(other.wire_); + break; + case DriveType::PORT: + *this = std::move(other.port_); + break; + case DriveType::MARKER: + *this = std::move(other.marker_); + break; + case DriveType::MULTIPLE: + *this = std::move(other.multiple_); + break; + } + return *this; + } + + DriveChunk &operator=(Const const &constant) + { + set_none(); + new (&constant_) Const(constant); + type_ = DriveType::CONSTANT; + return *this; + } + + DriveChunk &operator=(Const &&constant) + { + set_none(); + new (&constant_) Const(std::move(constant)); + type_ = DriveType::CONSTANT; + return *this; + } + + DriveChunk &operator=(DriveChunkWire const &wire) + { + set_none(); + new (&wire_) DriveChunkWire(wire); + type_ = DriveType::WIRE; + return *this; + } + + DriveChunk &operator=(DriveChunkWire &&wire) + { + set_none(); + new (&wire_) DriveChunkWire(wire); + type_ = DriveType::WIRE; + return *this; + } + + DriveChunk &operator=(DriveChunkPort const &port) + { + set_none(); + new (&port_) DriveChunkPort(port); + type_ = DriveType::PORT; + return *this; + } + + DriveChunk &operator=(DriveChunkPort &&port) + { + set_none(); + new (&port_) DriveChunkPort(port); + type_ = DriveType::PORT; + return *this; + } + + DriveChunk &operator=(DriveChunkMarker const &marker) + { + set_none(); + new (&marker_) DriveChunkMarker(marker); + type_ = DriveType::MARKER; + return *this; + } + + DriveChunk &operator=(DriveChunkMarker &&marker) + { + set_none(); + new (&marker_) DriveChunkMarker(marker); + type_ = DriveType::MARKER; + return *this; + } + + DriveChunk &operator=(DriveChunkMultiple const &multiple) + { + set_none(multiple.size()); + if (multiple.multiple().empty()) + return *this; + new (&multiple_) DriveChunkMultiple(multiple); + type_ = DriveType::MULTIPLE; + return *this; + } + + DriveChunk &operator=(DriveChunkMultiple &&multiple) + { + set_none(multiple.size()); + if (multiple.multiple().empty()) + return *this; + new (&multiple_) DriveChunkMultiple(multiple); + type_ = DriveType::MULTIPLE; + return *this; + } + + DriveChunk &operator=(DriveBit const &other) + { + switch (other.type()) + { + case DriveType::NONE: + set_none(1); + break; + case DriveType::CONSTANT: + *this = Const(other.constant()); + break; + case DriveType::WIRE: + *this = DriveChunkWire(other.wire()); + break; + case DriveType::PORT: + *this = DriveChunkPort(other.port()); + break; + case DriveType::MARKER: + *this = DriveChunkMarker(other.marker()); + break; + case DriveType::MULTIPLE: + *this = DriveChunkMultiple(other.multiple()); + break; + } + return *this; + } + + bool can_append(DriveBit const &bit) const; + bool try_append(DriveBit const &bit); + bool try_append(DriveChunk const &chunk); + + unsigned int hash() const + { + unsigned int inner; + switch (type_) + { + case DriveType::NONE: + inner = 0; + break; + case DriveType::CONSTANT: + inner = constant_.hash(); + break; + case DriveType::WIRE: + inner = wire_.hash(); + break; + case DriveType::PORT: + inner = port_.hash(); + break; + case DriveType::MARKER: + inner = marker_.hash(); + break; + case DriveType::MULTIPLE: + inner = multiple_.hash(); + break; + } + return mkhash((unsigned int)type_, inner); + } + + bool operator==(const DriveChunk &other) const + { + if (type_ != other.type_) + return false; + + switch (type_) + { + case DriveType::NONE: + return true; + case DriveType::CONSTANT: + return constant_ == other.constant_; + case DriveType::WIRE: + return wire_ == other.wire_; + case DriveType::PORT: + return port_ == other.port_; + case DriveType::MARKER: + return marker_ == other.marker_; + case DriveType::MULTIPLE: + return multiple_ == other.multiple_; + } + log_assert(false); + } + + bool operator!=(const DriveChunk &other) const + { + return !(*this == other); + } + + bool operator<(const DriveChunk &other) const + { + if (type_ != other.type_) + return type_ < other.type_; + switch (type_) + { + case DriveType::NONE: + return false; + case DriveType::CONSTANT: + return constant_ < other.constant_; + case DriveType::WIRE: + return wire_ < other.wire_; + case DriveType::PORT: + return port_ < other.port_; + case DriveType::MARKER: + return marker_ < other.marker_; + case DriveType::MULTIPLE: + return multiple_ < other.multiple_; + } + log_assert(false); + } + + DriveType type() const { return type_; } + + bool is_none() const { return type_ == DriveType::NONE; } + bool is_constant() const { return type_ == DriveType::CONSTANT; } + bool is_wire() const { return type_ == DriveType::WIRE; } + bool is_port() const { return type_ == DriveType::PORT; } + bool is_marker() const { return type_ == DriveType::MARKER; } + bool is_multiple() const { return type_ == DriveType::MULTIPLE; } + + Const &constant() { log_assert(is_constant()); return constant_; } + Const const &constant() const { log_assert(is_constant()); return constant_; } + DriveChunkWire &wire() { log_assert(is_wire()); return wire_; } + DriveChunkWire const &wire() const { log_assert(is_wire()); return wire_; } + DriveChunkPort &port() { log_assert(is_port()); return port_; } + DriveChunkPort const &port() const { log_assert(is_port()); return port_; } + DriveChunkMarker &marker() { log_assert(is_marker()); return marker_; } + DriveChunkMarker const &marker() const { log_assert(is_marker()); return marker_; } + DriveChunkMultiple &multiple() { log_assert(is_multiple()); return multiple_; } + DriveChunkMultiple const &multiple() const { log_assert(is_multiple()); return multiple_; } + + + int size() const + { + switch (type_) + { + case DriveType::NONE: + return none_; + case DriveType::CONSTANT: + return constant_.size(); + case DriveType::WIRE: + return wire_.size(); + case DriveType::PORT: + return port_.size(); + case DriveType::MARKER: + return marker_.size(); + case DriveType::MULTIPLE: + return multiple_.size(); + } + } +}; + +struct DriveSpec +{ +private: + int width_ = 0; + mutable std::vector chunks_; + mutable std::vector bits_; + mutable unsigned int hash_ = 0; +public: + + inline bool packed() const { + return bits_.empty(); + } + + DriveSpec() {} + + DriveSpec(DriveChunk const &chunk) { *this = chunk; } + DriveSpec(DriveChunkWire const &chunk) { *this = chunk; } + DriveSpec(DriveChunkPort const &chunk) { *this = chunk; } + DriveSpec(DriveChunkMarker const &chunk) { *this = chunk; } + DriveSpec(DriveChunkMultiple const &chunk) { *this = chunk; } + + DriveSpec(DriveBit const &bit) { *this = bit; } + DriveSpec(DriveBitWire const &bit) { *this = bit; } + DriveSpec(DriveBitPort const &bit) { *this = bit; } + DriveSpec(DriveBitMarker const &bit) { *this = bit; } + DriveSpec(DriveBitMultiple const &bit) { *this = bit; } + + DriveSpec(std::vector const &chunks) : chunks_(chunks) { compute_width(); } + + DriveSpec(std::vector const &bits) + { + for (auto const &bit : bits) + append(bit); + } + + std::vector const &chunks() const { pack(); return chunks_; } + std::vector const &bits() const { unpack(); return bits_; } + + int size() const { return width_; } + + void append(DriveBit const &bit); + + void append(DriveChunk const &chunk); + + void pack() const; + + void unpack() const; + + DriveBit &operator[](int index) + { + log_assert(index >= 0 && index < size()); + unpack(); + return bits_[index]; + } + + const DriveBit &operator[](int index) const + { + log_assert(index >= 0 && index < size()); + unpack(); + return bits_[index]; + } + + void clear() + { + chunks_.clear(); + bits_.clear(); + width_ = 0; + } + + DriveSpec &operator=(DriveChunk const &chunk) + { + chunks_.clear(); + bits_.clear(); + append(chunk); + return *this; + } + + DriveSpec &operator=(DriveChunkWire const &chunk) { return *this = DriveChunk(chunk); } + DriveSpec &operator=(DriveChunkPort const &chunk) { return *this = DriveChunk(chunk); } + DriveSpec &operator=(DriveChunkMarker const &chunk) { return *this = DriveChunk(chunk); } + DriveSpec &operator=(DriveChunkMultiple const &chunk) { return *this = DriveChunk(chunk); } + + DriveSpec &operator=(DriveBit const &bit) + { + chunks_.clear(); + bits_.clear(); + append(bit); + return *this; + } + + DriveSpec &operator=(DriveBitWire const &bit) { return *this = DriveBit(bit); } + DriveSpec &operator=(DriveBitPort const &bit) { return *this = DriveBit(bit); } + DriveSpec &operator=(DriveBitMarker const &bit) { return *this = DriveBit(bit); } + DriveSpec &operator=(DriveBitMultiple const &bit) { return *this = DriveBit(bit); } + + unsigned int hash() const { + if (hash_ != 0) return hash_; + + pack(); + hash_ = hash_ops>().hash(chunks_); + hash_ |= (hash_ == 0); + return hash_; + } + + bool operator==(DriveSpec const &other) const { + if (size() != other.size() || hash() != other.hash()) + return false; + return chunks() == other.chunks(); + } + +private: + void compute_width(); +}; + + + +struct DriverMap +{ + CellTypes celltypes; + + DriverMap() { celltypes.setup(); } + DriverMap(Design *design) { celltypes.setup(); celltypes.setup_design(design); } + +private: + + // Internally we represent all DriveBits by mapping them to DriveBitIds + // which use less memory and are cheaper to compare. + struct DriveBitId + { + int id = -1; + + DriveBitId() {}; + + DriveBitId(int id) : id(id) { } + + bool operator==(const DriveBitId &other) const { return id == other.id; } + bool operator<(const DriveBitId &other) const { return id < other.id; } + unsigned int hash() const { return id; } + }; + // Essentially a dict> but using less memory + // and fewer allocations + struct DriveBitGraph { + dict first_edges; + dict second_edges; + dict> more_edges; + + void add_edge(DriveBitId src, DriveBitId dst); + DriveBitId pop_edge(DriveBitId src); + void clear(DriveBitId src); + bool contains(DriveBitId src); + int count(DriveBitId src); + + DriveBitId at(DriveBitId src, int index); + }; + + // The following two maps maintain a sparse DriveBit to DriveBitId mapping. + // This saves a lot of memory compared to a `dict` or + // `idict`. + + // Maps wires to the first DriveBitId of the consecutive range used for + // that wire. + dict wire_offsets; + + // Maps cell ports to a the first DriveBitId of the consecutive range used + // for that cell port. + dict, DriveBitId> port_offsets; + + // For the inverse map that maps DriveBitIds back to DriveBits we use a + // sorted map containing only the first DriveBit for each wire and cell + // port. + std::map drive_bits; + + // As a memory optimization for gate level net lists we store single-bit + // wires and cell ports in a `dict` which requires less memory and fewer + // allocations than `std::map` but doesn't support the kind of lookups we + // need for a sparse coarse grained mapping. + dict isolated_drive_bits; + + // Used for allocating DriveBitIds, none and constant states use a fixewd + // mapping to the first few ids, which we need to skip. + int next_offset = 1 + (int)State::Sm; + + // Union-Find over directly connected bits that share the same single + // driver or are undriven. We never merge connections between drivers + // and/or kept wires. + mfp same_driver; + + // For each bit, store a set of connected driver bits for which the + // explicit connection should be preserved and the driving direction is + // locally unambiguous (one side only drives or requires a driven value). + DriveBitGraph connected_drivers; + + // For each bit, store a set of connected driver bits for which the + // explicit connection should be preserved and the driving direction is + // locally ambiguous. Every such ambiguous connection is also present in + // the reverse direction and has to be resolved when querying drivers. + DriveBitGraph connected_undirected; + + // Subset of `connected_undirected` for caching the resolved driving + // direction. In case multiple drivers are present this can still contain + // both orientations of a single connection, but for a single driver only + // one will be present. + DriveBitGraph connected_oriented; + + // Stores for which bits we already resolved the orientation (cached in + // `connected_oriented`). + pool oriented_present; + + + enum class BitMode { + NONE = 0, // Not driven, no need to keep wire + DRIVEN = 1, // Not driven, uses a value driven elsewhere + DRIVEN_UNIQUE = 2, // Uses a value driven elsewhere, has at most one direct connection + KEEP = 3, // Wire that should be kept + TRISTATE = 4, // Can drive a value but can also use a value driven elsewhere + DRIVER = 5, // Drives a value + }; + + BitMode bit_mode(DriveBit const &bit); + DriveBitId id_from_drive_bit(DriveBit const &bit); + DriveBit drive_bit_from_id(DriveBitId id); + + void connect_directed_merge(DriveBitId driven_id, DriveBitId driver_id); + void connect_directed_buffer(DriveBitId driven_id, DriveBitId driver_id); + void connect_undirected(DriveBitId a_id, DriveBitId b_id); + +public: + + void add(Module *module); + + // Add a single bit connection to the driver map. + void add(DriveBit const &a, DriveBit const &b); + + template + static constexpr bool is_sig_type() { + return + std::is_same::value || + std::is_same::value || + std::is_same::value || + std::is_same::value || + std::is_same::value || + std::is_same::value || + std::is_same::value; + } + + // We use the enable_if to produce better compiler errors when unsupported + // types are used + template + typename std::enable_if() && is_sig_type()>::type + add(T const &a, U const &b) + { + log_assert(a.size() == b.size()); + for (int i = 0; i != GetSize(a); ++i) + add(DriveBit(a[i]), DriveBit(b[i])); + } + + + // Specialized version that avoids unpacking + void add(SigSpec const &a, SigSpec const &b); + +private: + void add_port(Cell *cell, IdString const &port, SigSpec const &b); + + // Only used a local variables in `orient_undirected`, always cleared, only + // stored to reduce allocations. + pool orient_undirected_seen; + pool orient_undirected_drivers; + dict orient_undirected_distance; + + void orient_undirected(DriveBitId id); + +public: + DriveBit operator()(DriveBit const &bit); + + DriveSpec operator()(DriveSpec spec); + +private: + bool keep_wire(Wire *wire) { + // TODO configurable + return wire->has_attribute(ID(keep)); + } +}; + +YOSYS_NAMESPACE_END + +#endif From 0460a1693302ac9f2741c87a047a0acda5d85ebd Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Mon, 15 Apr 2024 14:14:50 +0200 Subject: [PATCH 05/51] WIP temporary drivertools example --- passes/cmds/Makefile.inc | 1 + passes/cmds/example_dt.cc | 140 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 141 insertions(+) create mode 100644 passes/cmds/example_dt.cc diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc index d7e572462b0..caea266c397 100644 --- a/passes/cmds/Makefile.inc +++ b/passes/cmds/Makefile.inc @@ -48,3 +48,4 @@ OBJS += passes/cmds/clean_zerowidth.o OBJS += passes/cmds/xprop.o OBJS += passes/cmds/dft_tag.o OBJS += passes/cmds/future.o +OBJS += passes/cmds/example_dt.o diff --git a/passes/cmds/example_dt.cc b/passes/cmds/example_dt.cc new file mode 100644 index 00000000000..de84fa3cda8 --- /dev/null +++ b/passes/cmds/example_dt.cc @@ -0,0 +1,140 @@ +#include "kernel/yosys.h" +#include "kernel/drivertools.h" +#include "kernel/topo_scc.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + + + + +struct ExampleWorker +{ + DriverMap dm; + Module *module; + + ExampleWorker(Module *module) : module(module) { + dm.celltypes.setup(); + } +}; + +struct ExampleDtPass : public Pass +{ + ExampleDtPass() : Pass("example_dt", "drivertools example") {} + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + } + + + void execute(std::vector args, RTLIL::Design *design) override + { + size_t argidx = 1; + extra_args(args, argidx, design); + + for (auto module : design->selected_modules()) { + ExampleWorker worker(module); + DriverMap dm; + + dm.add(module); + + idict queue; + idict cells; + + IntGraph edges; + + + for (auto cell : module->cells()) { + if (cell->type.in(ID($assert), ID($assume), ID($cover), ID($check))) + queue(DriveBitMarker(cells(cell), 0)); + } + + for (auto wire : module->wires()) { + if (!wire->port_output) + continue; + queue(DriveChunk(DriveChunkWire(wire, 0, wire->width))); + } + +#define emit log +// #define emit(X...) do {} while (false) + + for (int i = 0; i != GetSize(queue); ++i) + { + emit("n%d: ", i); + DriveSpec spec = queue[i]; + if (spec.chunks().size() > 1) { + emit("concat %s <-\n", log_signal(spec)); + for (auto const &chunk : spec.chunks()) { + emit(" * %s\n", log_signal(chunk)); + edges.add_edge(i, queue(chunk)); + } + } else if (spec.chunks().size() == 1) { + DriveChunk chunk = spec.chunks()[0]; + if (chunk.is_wire()) { + DriveChunkWire wire_chunk = chunk.wire(); + if (wire_chunk.is_whole()) { + if (wire_chunk.wire->port_input) { + emit("input %s\n", log_signal(spec)); + } else { + DriveSpec driver = dm(DriveSpec(wire_chunk)); + edges.add_edge(i, queue(driver)); + emit("wire driver %s <- %s\n", log_signal(spec), log_signal(driver)); + } + } else { + DriveChunkWire whole_wire(wire_chunk.wire, 0, wire_chunk.width); + edges.add_edge(i, queue(whole_wire)); + emit("wire slice %s <- %s\n", log_signal(spec), log_signal(DriveSpec(whole_wire))); + } + } else if (chunk.is_port()) { + DriveChunkPort port_chunk = chunk.port(); + if (port_chunk.is_whole()) { + if (dm.celltypes.cell_output(port_chunk.cell->type, port_chunk.port)) { + int cell_marker = queue(DriveBitMarker(cells(port_chunk.cell), 0)); + if (!port_chunk.cell->type.in(ID($dff), ID($ff))) + edges.add_edge(i, cell_marker); + emit("cell output %s %s\n", log_id(port_chunk.cell), log_id(port_chunk.port)); + } else { + DriveSpec driver = dm(DriveSpec(port_chunk)); + edges.add_edge(i, queue(driver)); + emit("cell port driver %s <- %s\n", log_signal(spec), log_signal(driver)); + } + + } else { + DriveChunkPort whole_port(port_chunk.cell, port_chunk.port, 0, GetSize(port_chunk.cell->connections().at(port_chunk.port))); + edges.add_edge(i, queue(whole_port)); + emit("port slice %s <- %s\n", log_signal(spec), log_signal(DriveSpec(whole_port))); + } + } else if (chunk.is_constant()) { + emit("constant %s <- %s\n", log_signal(spec), log_const(chunk.constant())); + } else if (chunk.is_marker()) { + Cell *cell = cells[chunk.marker().marker]; + emit("cell %s %s\n", log_id(cell->type), log_id(cell)); + for (auto const &conn : cell->connections()) { + if (!dm.celltypes.cell_input(cell->type, conn.first)) + continue; + emit(" * %s <- %s\n", log_id(conn.first), log_signal(conn.second)); + edges.add_edge(i, queue(DriveChunkPort(cell, conn))); + } + } else { + log_abort(); + } + } else { + log_abort(); + } + } + + topo_sorted_sccs(edges, [&](int *begin, int *end) { + emit("scc:"); + for (int *i = begin; i != end; ++i) + emit(" n%d", *i); + emit("\n"); + }); + + } + log("Plugin test passed!\n"); + } +} ExampleDtPass; + +PRIVATE_NAMESPACE_END From 2971cf384a9b90ddbf5f3ad38bf2842a45fb7f58 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Thu, 11 Apr 2024 13:47:14 +0200 Subject: [PATCH 06/51] topo_scc: Add sources_first option --- kernel/topo_scc.h | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/kernel/topo_scc.h b/kernel/topo_scc.h index 0ae0e696b47..89df8928aa2 100644 --- a/kernel/topo_scc.h +++ b/kernel/topo_scc.h @@ -194,7 +194,7 @@ class IntGraph { }; template -void topo_sorted_sccs(G &graph, ComponentCallback component) +void topo_sorted_sccs(G &graph, ComponentCallback component, bool sources_first = false) { typedef typename G::node_enumerator node_enumerator; typedef typename G::successor_enumerator successor_enumerator; @@ -217,6 +217,23 @@ void topo_sorted_sccs(G &graph, ComponentCallback component) node_enumerator nodes = graph.enumerate_nodes(); + if (sources_first) { + while (!nodes.finished()) { + node_type node = nodes.next(); + successor_enumerator successors = graph.enumerate_successors(node); + if (successors.finished()) + { + graph.dfs_index(node) = next_index; + next_index++; + component_stack.push_back(node); + component(component_stack.data(), component_stack.data() + 1); + component_stack.clear(); + graph.dfs_index(node) = INT_MAX; + } + } + nodes = graph.enumerate_nodes(); + } + // iterate over all nodes to ensure we process the whole graph while (!nodes.finished()) { node_type node = nodes.next(); From b21d9d296bf10b6c9e2028197231abe00ee316d5 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Thu, 11 Apr 2024 13:48:25 +0200 Subject: [PATCH 07/51] ComputeGraph datatype for the upcoming functional backend --- kernel/functional.h | 369 ++++++++++++++++++++++++++++++++++++++ passes/cmds/example_dt.cc | 178 ++++++++++++++---- 2 files changed, 515 insertions(+), 32 deletions(-) create mode 100644 kernel/functional.h diff --git a/kernel/functional.h b/kernel/functional.h new file mode 100644 index 00000000000..e5ee8824099 --- /dev/null +++ b/kernel/functional.h @@ -0,0 +1,369 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2024 Jannis Harder + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef FUNCTIONAL_H +#define FUNCTIONAL_H + +#include +#include "kernel/yosys.h" + +YOSYS_NAMESPACE_BEGIN + +template< + typename Fn, // Function type (deduplicated across whole graph) + typename Attr = std::tuple<>, // Call attributes (present in every node) + typename SparseAttr = std::tuple<>, // Sparse call attributes (optional per node) + typename Key = std::tuple<> // Stable keys to refer to nodes +> +struct ComputeGraph +{ + struct Ref; +private: + + // Functions are deduplicated by assigning unique ids + idict functions; + + struct Node { + int fn_index; + int arg_offset; + int arg_count; + Attr attr; + + Node(int fn_index, Attr &&attr, int arg_offset, int arg_count = 0) + : fn_index(fn_index), arg_offset(arg_offset), arg_count(arg_count), attr(std::move(attr)) {} + + Node(int fn_index, Attr const &attr, int arg_offset, int arg_count = 0) + : fn_index(fn_index), arg_offset(arg_offset), arg_count(arg_count), attr(attr) {} + }; + + + std::vector nodes; + std::vector args; + dict keys_; + dict sparse_attrs; + +public: + template + struct BaseRef + { + protected: + friend struct ComputeGraph; + Graph *graph_; + int index_; + BaseRef(Graph *graph, int index) : graph_(graph), index_(index) { + log_assert(index_ >= 0); + check(); + } + + void check() const { log_assert(index_ < graph_->size()); } + + Node const &deref() const { check(); return graph_->nodes[index_]; } + + public: + ComputeGraph const &graph() const { return graph_; } + int index() const { return index_; } + + int size() const { return deref().arg_count; } + + BaseRef arg(int n) const + { + Node const &node = deref(); + log_assert(n >= 0 && n < node.arg_count); + return BaseRef(graph_, graph_->args[node.arg_offset + n]); + } + + std::vector::const_iterator arg_indices_cbegin() const + { + Node const &node = deref(); + return graph_->args.cbegin() + node.arg_offset; + } + + std::vector::const_iterator arg_indices_cend() const + { + Node const &node = deref(); + return graph_->args.cbegin() + node.arg_offset + node.arg_count; + } + + Fn const &function() const { return graph_->functions[deref().fn_index]; } + Attr const &attr() const { return deref().attr; } + + bool has_sparse_attr() const { return graph_->sparse_attrs.count(index_); } + + SparseAttr const &sparse_attr() const + { + auto found = graph_->sparse_attrs.find(index_); + log_assert(found != graph_->sparse_attrs.end()); + return *found; + } + }; + + using ConstRef = BaseRef; + + struct Ref : public BaseRef + { + private: + friend struct ComputeGraph; + Ref(ComputeGraph *graph, int index) : BaseRef(graph, index) {} + Node &deref() const { this->check(); return this->graph_->nodes[this->index_]; } + + public: + void set_function(Fn const &function) const + { + deref().fn_index = this->graph_->functions(function); + } + + Attr &attr() const { return deref().attr; } + + void append_arg(ConstRef arg) const + { + log_assert(arg.graph_ == this->graph_); + append_arg(arg.index()); + } + + void append_arg(int arg) const + { + log_assert(arg >= 0 && arg < this->graph_->size()); + Node &node = deref(); + if (node.arg_offset + node.arg_count != GetSize(this->graph_->args)) + move_args(node); + this->graph_->args.push_back(arg); + node.arg_count++; + } + + operator ConstRef() const + { + return ConstRef(this->graph_, this->index_); + } + + SparseAttr &sparse_attr() const + { + return this->graph_->sparse_attrs[this->index_]; + } + + void clear_sparse_attr() const + { + this->graph_->sparse_attrs.erase(this->index_); + } + + void assign_key(Key const &key) const + { + this->graph_->keys_.emplace(key, this->index_); + } + + private: + void move_args(Node &node) const + { + auto &args = this->graph_->args; + int old_offset = node.arg_offset; + node.arg_offset = GetSize(args); + for (int i = 0; i != node.arg_count; ++i) + args.push_back(args[old_offset + i]); + } + + }; + + bool has_key(Key const &key) const + { + return keys_.count(key); + } + + dict const &keys() const + { + return keys_; + } + + ConstRef operator()(Key const &key) const + { + auto it = keys_.find(key); + log_assert(it != keys_.end()); + return (*this)[it->second]; + } + + Ref operator()(Key const &key) + { + auto it = keys_.find(key); + log_assert(it != keys_.end()); + return (*this)[it->second]; + } + + int size() const { return GetSize(nodes); } + + ConstRef operator[](int index) const { return ConstRef(this, index); } + Ref operator[](int index) { return Ref(this, index); } + + Ref add(Fn const &function, Attr &&attr) + { + int index = GetSize(nodes); + int fn_index = functions(function); + nodes.emplace_back(fn_index, std::move(attr), GetSize(args)); + return Ref(this, index); + } + + Ref add(Fn const &function, Attr const &attr) + { + int index = GetSize(nodes); + int fn_index = functions(function); + nodes.emplace_back(fn_index, attr, GetSize(args)); + return Ref(this, index); + } + + template + Ref add(Fn const &function, Attr const &attr, T const &args) + { + Ref added = add(function, attr); + for (auto arg : args) + added.append_arg(arg); + return added; + } + + template + Ref add(Fn const &function, Attr &&attr, T const &args) + { + Ref added = add(function, std::move(attr)); + for (auto arg : args) + added.append_arg(arg); + return added; + } + + template + Ref add(Fn const &function, Attr const &attr, T begin, T end) + { + Ref added = add(function, attr); + for (; begin != end; ++begin) + added.append_arg(*begin); + return added; + } + + void permute(std::vector const &perm) + { + log_assert(perm.size() <= nodes.size()); + std::vector inv_perm; + inv_perm.resize(nodes.size(), -1); + for (int i = 0; i < GetSize(perm); ++i) + { + int j = perm[i]; + log_assert(j >= 0 && j < GetSize(perm)); + log_assert(inv_perm[j] == -1); + inv_perm[j] = i; + } + permute(perm, inv_perm); + } + + void permute(std::vector const &perm, std::vector const &inv_perm) + { + log_assert(inv_perm.size() == nodes.size()); + std::vector new_nodes; + new_nodes.reserve(perm.size()); + dict new_sparse_attrs; + for (int i : perm) + { + int j = GetSize(new_nodes); + new_nodes.emplace_back(std::move(nodes[i])); + auto found = sparse_attrs.find(i); + if (found != sparse_attrs.end()) + new_sparse_attrs.emplace(j, std::move(found->second)); + } + + std::swap(nodes, new_nodes); + std::swap(sparse_attrs, new_sparse_attrs); + + for (int &arg : args) + { + log_assert(arg < GetSize(inv_perm)); + arg = inv_perm[arg]; + } + + for (auto &key : keys_) + { + log_assert(key.second < GetSize(inv_perm)); + key.second = inv_perm[key.second]; + } + } + + struct SccAdaptor + { + private: + ComputeGraph const &graph_; + std::vector indices_; + public: + SccAdaptor(ComputeGraph const &graph) : graph_(graph) + { + indices_.resize(graph.size(), -1); + } + + + typedef int node_type; + + struct node_enumerator { + private: + friend struct SccAdaptor; + int current, end; + node_enumerator(int current, int end) : current(current), end(end) {} + + public: + + bool finished() const { return current == end; } + node_type next() { + log_assert(!finished()); + node_type result = current; + ++current; + return result; + } + }; + + node_enumerator enumerate_nodes() { + return node_enumerator(0, GetSize(indices_)); + } + + + struct successor_enumerator { + private: + friend struct SccAdaptor; + std::vector::const_iterator current, end; + successor_enumerator(std::vector::const_iterator current, std::vector::const_iterator end) : + current(current), end(end) {} + + public: + bool finished() const { return current == end; } + node_type next() { + log_assert(!finished()); + node_type result = *current; + ++current; + return result; + } + }; + + successor_enumerator enumerate_successors(int index) const { + auto const &ref = graph_[index]; + return successor_enumerator(ref.arg_indices_cbegin(), ref.arg_indices_cend()); + } + + int &dfs_index(node_type const &node) { return indices_[node]; } + + std::vector const &dfs_indices() { return indices_; } + }; + +}; + + + +YOSYS_NAMESPACE_END + + +#endif diff --git a/passes/cmds/example_dt.cc b/passes/cmds/example_dt.cc index de84fa3cda8..dec554d6c71 100644 --- a/passes/cmds/example_dt.cc +++ b/passes/cmds/example_dt.cc @@ -1,6 +1,7 @@ #include "kernel/yosys.h" #include "kernel/drivertools.h" #include "kernel/topo_scc.h" +#include "kernel/functional.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -38,86 +39,137 @@ struct ExampleDtPass : public Pass ExampleWorker worker(module); DriverMap dm; + struct ExampleFn { + IdString name; + dict parameters; + + ExampleFn(IdString name) : name(name) {} + ExampleFn(IdString name, dict parameters) : name(name), parameters(parameters) {} + + bool operator==(ExampleFn const &other) const { + return name == other.name && parameters == other.parameters; + } + + unsigned int hash() const { + return mkhash(name.hash(), parameters.hash()); + } + }; + + typedef ComputeGraph ExampleGraph; + + ExampleGraph compute_graph; + + dm.add(module); idict queue; idict cells; IntGraph edges; + std::vector graph_nodes; + auto enqueue = [&](DriveSpec const &spec) { + int index = queue(spec); + if (index == GetSize(graph_nodes)) + graph_nodes.emplace_back(compute_graph.add(ID($pending), index).index()); + //if (index >= GetSize(graph_nodes)) + return compute_graph[graph_nodes[index]]; + }; for (auto cell : module->cells()) { if (cell->type.in(ID($assert), ID($assume), ID($cover), ID($check))) - queue(DriveBitMarker(cells(cell), 0)); + enqueue(DriveBitMarker(cells(cell), 0)); } for (auto wire : module->wires()) { if (!wire->port_output) continue; - queue(DriveChunk(DriveChunkWire(wire, 0, wire->width))); + enqueue(DriveChunk(DriveChunkWire(wire, 0, wire->width))).assign_key(wire->name); } -#define emit log -// #define emit(X...) do {} while (false) - for (int i = 0; i != GetSize(queue); ++i) { - emit("n%d: ", i); DriveSpec spec = queue[i]; + ExampleGraph::Ref node = compute_graph[i]; + if (spec.chunks().size() > 1) { - emit("concat %s <-\n", log_signal(spec)); + node.set_function(ID($$concat)); + for (auto const &chunk : spec.chunks()) { - emit(" * %s\n", log_signal(chunk)); - edges.add_edge(i, queue(chunk)); + node.append_arg(enqueue(chunk)); } } else if (spec.chunks().size() == 1) { DriveChunk chunk = spec.chunks()[0]; if (chunk.is_wire()) { DriveChunkWire wire_chunk = chunk.wire(); if (wire_chunk.is_whole()) { + node.sparse_attr() = wire_chunk.wire->name; if (wire_chunk.wire->port_input) { - emit("input %s\n", log_signal(spec)); + node.set_function(ExampleFn(ID($$input), {{wire_chunk.wire->name, {}}})); } else { DriveSpec driver = dm(DriveSpec(wire_chunk)); - edges.add_edge(i, queue(driver)); - emit("wire driver %s <- %s\n", log_signal(spec), log_signal(driver)); + node.set_function(ID($$buf)); + + node.append_arg(enqueue(driver)); } } else { DriveChunkWire whole_wire(wire_chunk.wire, 0, wire_chunk.width); - edges.add_edge(i, queue(whole_wire)); - emit("wire slice %s <- %s\n", log_signal(spec), log_signal(DriveSpec(whole_wire))); + node.set_function(ExampleFn(ID($$slice), {{ID(offset), wire_chunk.offset}, {ID(width), wire_chunk.width}})); + node.append_arg(enqueue(whole_wire)); } } else if (chunk.is_port()) { DriveChunkPort port_chunk = chunk.port(); if (port_chunk.is_whole()) { if (dm.celltypes.cell_output(port_chunk.cell->type, port_chunk.port)) { - int cell_marker = queue(DriveBitMarker(cells(port_chunk.cell), 0)); - if (!port_chunk.cell->type.in(ID($dff), ID($ff))) - edges.add_edge(i, cell_marker); - emit("cell output %s %s\n", log_id(port_chunk.cell), log_id(port_chunk.port)); + if (port_chunk.cell->type.in(ID($dff), ID($ff))) + { + Cell *cell = port_chunk.cell; + node.set_function(ExampleFn(ID($$state), {{cell->name, {}}})); + for (auto const &conn : cell->connections()) { + if (!dm.celltypes.cell_input(cell->type, conn.first)) + continue; + enqueue(DriveChunkPort(cell, conn)).assign_key(cell->name); + } + } + else + { + node.set_function(ExampleFn(ID($$cell_output), {{port_chunk.port, {}}})); + node.append_arg(enqueue(DriveBitMarker(cells(port_chunk.cell), 0))); + } } else { + node.set_function(ID($$buf)); + DriveSpec driver = dm(DriveSpec(port_chunk)); - edges.add_edge(i, queue(driver)); - emit("cell port driver %s <- %s\n", log_signal(spec), log_signal(driver)); + node.append_arg(enqueue(driver)); } } else { DriveChunkPort whole_port(port_chunk.cell, port_chunk.port, 0, GetSize(port_chunk.cell->connections().at(port_chunk.port))); - edges.add_edge(i, queue(whole_port)); - emit("port slice %s <- %s\n", log_signal(spec), log_signal(DriveSpec(whole_port))); + node.set_function(ID($$buf)); + node.append_arg(enqueue(whole_port)); } } else if (chunk.is_constant()) { - emit("constant %s <- %s\n", log_signal(spec), log_const(chunk.constant())); + node.set_function(ExampleFn(ID($$const), {{ID(value), chunk.constant()}})); + + } else if (chunk.is_multiple()) { + node.set_function(ID($$multi)); + for (auto const &driver : chunk.multiple().multiple()) + node.append_arg(enqueue(driver)); } else if (chunk.is_marker()) { Cell *cell = cells[chunk.marker().marker]; - emit("cell %s %s\n", log_id(cell->type), log_id(cell)); + + node.set_function(ExampleFn(cell->type, cell->parameters)); for (auto const &conn : cell->connections()) { if (!dm.celltypes.cell_input(cell->type, conn.first)) continue; - emit(" * %s <- %s\n", log_id(conn.first), log_signal(conn.second)); - edges.add_edge(i, queue(DriveChunkPort(cell, conn))); + + node.append_arg(enqueue(DriveChunkPort(cell, conn))); } + } else if (chunk.is_none()) { + node.set_function(ID($$undriven)); + } else { + log_error("unhandled drivespec: %s\n", log_signal(chunk)); log_abort(); } } else { @@ -125,13 +177,75 @@ struct ExampleDtPass : public Pass } } - topo_sorted_sccs(edges, [&](int *begin, int *end) { - emit("scc:"); - for (int *i = begin; i != end; ++i) - emit(" n%d", *i); - emit("\n"); - }); + // Perform topo sort and detect SCCs + ExampleGraph::SccAdaptor compute_graph_scc(compute_graph); + + + std::vector perm; + topo_sorted_sccs(compute_graph_scc, [&](int *begin, int *end) { + perm.insert(perm.end(), begin, end); + if (end > begin + 1) + { + log_warning("SCC:"); + for (int *i = begin; i != end; ++i) + log(" %d", *i); + log("\n"); + } + }, /* sources_first */ true); + compute_graph.permute(perm); + + + // Forward $$buf unless we have a name in the sparse attribute + std::vector alias; + perm.clear(); + + for (int i = 0; i < compute_graph.size(); ++i) + { + if (compute_graph[i].function().name == ID($$buf) && !compute_graph[i].has_sparse_attr() && compute_graph[i].arg(0).index() < i) + { + + alias.push_back(alias[compute_graph[i].arg(0).index()]); + } + else + { + alias.push_back(GetSize(perm)); + perm.push_back(i); + } + } + compute_graph.permute(perm, alias); + + // Dump the compute graph + for (int i = 0; i < compute_graph.size(); ++i) + { + auto ref = compute_graph[i]; + log("n%d ", i); + log("%s", log_id(ref.function().name)); + for (auto const ¶m : ref.function().parameters) + { + if (param.second.empty()) + log("[%s]", log_id(param.first)); + else + log("[%s=%s]", log_id(param.first), log_const(param.second)); + } + log("("); + + for (int i = 0, end = ref.size(); i != end; ++i) + { + if (i > 0) + log(", "); + log("n%d", ref.arg(i).index()); + } + log(")\n"); + if (ref.has_sparse_attr()) + log("// wire %s\n", log_id(ref.sparse_attr())); + log("// was #%d %s\n", ref.attr(), log_signal(queue[ref.attr()])); + } + + for (auto const &key : compute_graph.keys()) + { + log("return %d as %s \n", key.second, log_id(key.first)); + } } log("Plugin test passed!\n"); } From 07907ad5a5e8c97a119dd528d1ffe1d0188d00de Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Wed, 17 Apr 2024 14:52:36 +0200 Subject: [PATCH 08/51] fixup! drivertools: Utility code for indexing and traversing signal drivers --- kernel/drivertools.cc | 23 +++++++++++++---------- kernel/drivertools.h | 1 + 2 files changed, 14 insertions(+), 10 deletions(-) diff --git a/kernel/drivertools.cc b/kernel/drivertools.cc index 499a9399c46..286c913a246 100644 --- a/kernel/drivertools.cc +++ b/kernel/drivertools.cc @@ -499,7 +499,7 @@ int DriverMap::DriveBitGraph::count(DriveBitId src) auto found = more_edges.find(src); if (found == more_edges.end()) return 2; - return GetSize(found->second); + return GetSize(found->second) + 2; } DriverMap::DriveBitId DriverMap::DriveBitGraph::at(DriveBitId src, int index) @@ -688,7 +688,7 @@ void DriverMap::add(DriveBit const &a, DriveBit const &b) // and use the other end as representative bit. else if (a_mode == BitMode::DRIVEN_UNIQUE && !(b_mode == BitMode::DRIVEN_UNIQUE || b_mode == BitMode::DRIVEN)) connect_directed_buffer(a_id, b_id); - else if (b_mode == BitMode::DRIVEN_UNIQUE && !(b_mode == BitMode::DRIVEN_UNIQUE || b_mode == BitMode::DRIVEN)) + else if (b_mode == BitMode::DRIVEN_UNIQUE && !(a_mode == BitMode::DRIVEN_UNIQUE || a_mode == BitMode::DRIVEN)) connect_directed_buffer(b_id, a_id); // If either bit only drives a value, store a directed connection from // it to the other bit. @@ -827,15 +827,18 @@ DriveBit DriverMap::operator()(DriveBit const &bit) DriveBitId bit_id = id_from_drive_bit(bit); - bit_id = same_driver.find(bit_id); + DriveBitId bit_repr_id = same_driver.find(bit_id); - DriveBit bit_repr = drive_bit_from_id(bit_id); + DriveBit bit_repr = drive_bit_from_id(bit_repr_id); BitMode mode = bit_mode(bit_repr); - int implicit_driver_count = connected_drivers.count(bit_id); - if (connected_undirected.contains(bit_id) && !oriented_present.count(bit_id)) - orient_undirected(bit_id); + if (mode == BitMode::KEEP && bit_repr_id != bit_id) + return bit_repr; + + int implicit_driver_count = connected_drivers.count(bit_repr_id); + if (connected_undirected.contains(bit_repr_id) && !oriented_present.count(bit_repr_id)) + orient_undirected(bit_repr_id); DriveBit driver; @@ -843,11 +846,11 @@ DriveBit DriverMap::operator()(DriveBit const &bit) driver = bit_repr; for (int i = 0; i != implicit_driver_count; ++i) - driver.merge(drive_bit_from_id(connected_drivers.at(bit_id, i))); + driver.merge(drive_bit_from_id(connected_drivers.at(bit_repr_id, i))); - int oriented_driver_count = connected_oriented.count(bit_id); + int oriented_driver_count = connected_oriented.count(bit_repr_id); for (int i = 0; i != oriented_driver_count; ++i) - driver.merge(drive_bit_from_id(connected_oriented.at(bit_id, i))); + driver.merge(drive_bit_from_id(connected_oriented.at(bit_repr_id, i))); return driver; } diff --git a/kernel/drivertools.h b/kernel/drivertools.h index b440afddaa2..1cb835df2cc 100644 --- a/kernel/drivertools.h +++ b/kernel/drivertools.h @@ -1165,6 +1165,7 @@ struct DriverMap DriveBitId(int id) : id(id) { } bool operator==(const DriveBitId &other) const { return id == other.id; } + bool operator!=(const DriveBitId &other) const { return id != other.id; } bool operator<(const DriveBitId &other) const { return id < other.id; } unsigned int hash() const { return id; } }; From 8a30f0351deb28fdb4ab77bee6ba7fa561b33f2d Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Wed, 1 May 2024 11:47:16 +0100 Subject: [PATCH 09/51] fix bugs in drivertools --- kernel/drivertools.cc | 4 ++-- passes/cmds/example_dt.cc | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/kernel/drivertools.cc b/kernel/drivertools.cc index 286c913a246..9627a467015 100644 --- a/kernel/drivertools.cc +++ b/kernel/drivertools.cc @@ -680,9 +680,9 @@ void DriverMap::add(DriveBit const &a, DriveBit const &b) // If either bit is just a wire that we don't need to keep, merge and // use the other end as representative bit. - if (a_mode == BitMode::NONE) + if (a_mode == BitMode::NONE && !(b_mode == BitMode::DRIVEN_UNIQUE || b_mode == BitMode::DRIVEN)) connect_directed_merge(a_id, b_id); - else if (b_mode == BitMode::NONE) + else if (b_mode == BitMode::NONE && !(a_mode == BitMode::DRIVEN_UNIQUE || a_mode == BitMode::DRIVEN)) connect_directed_merge(b_id, a_id); // If either bit requires a driven value and has a unique driver, merge // and use the other end as representative bit. diff --git a/passes/cmds/example_dt.cc b/passes/cmds/example_dt.cc index dec554d6c71..859b0b7ba4b 100644 --- a/passes/cmds/example_dt.cc +++ b/passes/cmds/example_dt.cc @@ -113,7 +113,7 @@ struct ExampleDtPass : public Pass node.append_arg(enqueue(driver)); } } else { - DriveChunkWire whole_wire(wire_chunk.wire, 0, wire_chunk.width); + DriveChunkWire whole_wire(wire_chunk.wire, 0, wire_chunk.wire->width); node.set_function(ExampleFn(ID($$slice), {{ID(offset), wire_chunk.offset}, {ID(width), wire_chunk.width}})); node.append_arg(enqueue(whole_wire)); } @@ -145,7 +145,7 @@ struct ExampleDtPass : public Pass } else { DriveChunkPort whole_port(port_chunk.cell, port_chunk.port, 0, GetSize(port_chunk.cell->connections().at(port_chunk.port))); - node.set_function(ID($$buf)); + node.set_function(ExampleFn(ID($$slice), {{ID(offset), port_chunk.offset}})); node.append_arg(enqueue(whole_port)); } } else if (chunk.is_constant()) { From d4e3430d224989022f3e1f76bbc234c4d217c324 Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Wed, 1 May 2024 11:48:04 +0100 Subject: [PATCH 10/51] add initial version of functional C++ backend --- backends/functional/Makefile.inc | 1 + backends/functional/cxx.cc | 417 ++++++++++++++++++++++++++ backends/functional/cxx_runtime/sim.h | 366 ++++++++++++++++++++++ kernel/graphtools.h | 332 ++++++++++++++++++++ 4 files changed, 1116 insertions(+) create mode 100644 backends/functional/Makefile.inc create mode 100644 backends/functional/cxx.cc create mode 100644 backends/functional/cxx_runtime/sim.h create mode 100644 kernel/graphtools.h diff --git a/backends/functional/Makefile.inc b/backends/functional/Makefile.inc new file mode 100644 index 00000000000..011e662646c --- /dev/null +++ b/backends/functional/Makefile.inc @@ -0,0 +1 @@ +OBJS += backends/functional/cxx.o diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc new file mode 100644 index 00000000000..46ce88bd62c --- /dev/null +++ b/backends/functional/cxx.cc @@ -0,0 +1,417 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2024 Emily Schmidt + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/drivertools.h" +#include "kernel/topo_scc.h" +#include "kernel/functional.h" +#include "kernel/graphtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +const char *reserved_keywords[] = { + "alignas","alignof","and","and_eq","asm","atomic_cancel","atomic_commit", + "atomic_noexcept","auto","bitand","bitor","bool","break","case", + "catch","char","char16_t","char32_t","char8_t","class","co_await", + "co_return","co_yield","compl","concept","const","const_cast","consteval", + "constexpr","constinit","continue","decltype","default","delete", + "do","double","dynamic_cast","else","enum","explicit","export", + "extern","false","float","for","friend","goto","if","inline", + "int","long","mutable","namespace","new","noexcept","not","not_eq", + "nullptr","operator","or","or_eq","private","protected","public", + "reflexpr","register","reinterpret_cast","requires","return","short", + "signed","sizeof","static","static_assert","static_cast","struct", + "switch","synchronized","template","this","thread_local","throw", + "true","try","typedef","typeid","typename","union","unsigned", + "using","virtual","void","volatile","wchar_t","while","xor","xor_eq", + nullptr +}; + +struct CxxScope { + pool used_names; + dict name_map; + + CxxScope() { + for(const char **p = reserved_keywords; *p != nullptr; p++) + reserve(*p); + } + void reserve(std::string name) { + used_names.insert(name); + } + std::string insert(IdString id) { + std::string str = RTLIL::unescape_id(id); + for(size_t i = 0; i < str.size(); i++) + if(strchr("!\"#%&'()*+,-./:;<=>?@[]\\^`{|}~ ", str[i])) + str[i] = '_'; + if(used_names.count(str) == 0){ + used_names.insert(str); + name_map.insert({id, str}); + return str; + } + for (int idx = 0 ; ; idx++){ + std::string suffixed = str + "_" + std::to_string(idx); + if (used_names.count(suffixed) == 0) { + used_names.insert(suffixed); + if(name_map.count(id) == 0) + name_map.insert({id, suffixed}); + return suffixed; + } + } + } + std::string operator[](IdString id) { + if(name_map.count(id) > 0) + return name_map[id]; + else + return insert(id); + } +}; + +struct CxxWriter { + std::ostream &f; + CxxWriter(std::ostream &out) : f(out) {} + void printf(const char *fmt, ...) + { + va_list va; + va_start(va, fmt); + f << vstringf(fmt, va); + va_end(va); + } +}; + +struct CxxStruct { + std::string name; + dict types; + CxxScope scope; + CxxStruct(std::string name) : name(name) { + scope.reserve("out"); + scope.reserve("dump"); + } + void insert(IdString name, std::string type) { + scope.insert(name); + types.insert({name, type}); + } + void print(CxxWriter &f) { + f.printf("struct %s {\n", name.c_str()); + for (auto p : types) { + f.printf("\t%s %s;\n", p.second.c_str(), scope[p.first].c_str()); + } + f.printf("\n\ttemplate void dump(T &out) {\n"); + for (auto p : types) { + f.printf("\t\tout(\"%s\", %s);\n", RTLIL::unescape_id(p.first).c_str(), scope[p.first].c_str()); + } + f.printf("\t}\n};\n\n"); + } + std::string operator[](IdString field) { + return scope[field]; + } +}; + +struct CxxFunction { + IdString name; + int width; + dict parameters; + + CxxFunction(IdString name, int width) : name(name), width(width) {} + CxxFunction(IdString name, int width, dict parameters) : name(name), width(width), parameters(parameters) {} + + bool operator==(CxxFunction const &other) const { + return name == other.name && parameters == other.parameters && width == other.width; + } + + unsigned int hash() const { + return mkhash(name.hash(), parameters.hash()); + } +}; + +typedef ComputeGraph CxxComputeGraph; + +class CxxComputeGraphFactory { + CxxComputeGraph &graph; + using T = CxxComputeGraph::Ref; + static bool is_single_output(IdString type) + { + auto it = yosys_celltypes.cell_types.find(type); + return it != yosys_celltypes.cell_types.end() && it->second.outputs.size() <= 1; + } +public: + CxxComputeGraphFactory(CxxComputeGraph &g) : graph(g) {} + T slice(T a, int in_width, int offset, int out_width) { + assert(offset + out_width <= in_width); + return graph.add(CxxFunction(ID($$slice), out_width, {{ID(offset), offset}}), 0, std::array{a}); + } + T extend(T a, int in_width, int out_width, bool is_signed) { + assert(in_width < out_width); + if(is_signed) + return graph.add(CxxFunction(ID($sign_extend), out_width, {{ID(WIDTH), out_width}}), 0, std::array{a}); + else + return graph.add(CxxFunction(ID($zero_extend), out_width, {{ID(WIDTH), out_width}}), 0, std::array{a}); + } + T concat(T a, int a_width, T b, int b_width) { + return graph.add(CxxFunction(ID($$concat), a_width + b_width), 0, std::array{a, b}); + } + T add(T a, T b, int width) { return graph.add(CxxFunction(ID($add), width), 0, std::array{a, b}); } + T sub(T a, T b, int width) { return graph.add(CxxFunction(ID($sub), width), 0, std::array{a, b}); } + T bitwise_and(T a, T b, int width) { return graph.add(CxxFunction(ID($and), width), 0, std::array{a, b}); } + T bitwise_or(T a, T b, int width) { return graph.add(CxxFunction(ID($or), width), 0, std::array{a, b}); } + T bitwise_xor(T a, T b, int width) { return graph.add(CxxFunction(ID($xor), width), 0, std::array{a, b}); } + T bitwise_not(T a, int width) { return graph.add(CxxFunction(ID($not), width), 0, std::array{a}); } + T neg(T a, int width) { return graph.add(CxxFunction(ID($neg), width), 0, std::array{a}); } + T mux(T a, T b, T s, int width) { return graph.add(CxxFunction(ID($mux), width), 0, std::array{a, b, s}); } + T pmux(T a, T b, T s, int width, int) { return graph.add(CxxFunction(ID($pmux), width), 0, std::array{a, b, s}); } + T reduce_and(T a, int) { return graph.add(CxxFunction(ID($reduce_and), 1), 0, std::array{a}); } + T reduce_or(T a, int) { return graph.add(CxxFunction(ID($reduce_or), 1), 0, std::array{a}); } + T reduce_xor(T a, int) { return graph.add(CxxFunction(ID($reduce_xor), 1), 0, std::array{a}); } + T eq(T a, T b, int) { return graph.add(CxxFunction(ID($eq), 1), 0, std::array{a, b}); } + T ne(T a, T b, int) { return graph.add(CxxFunction(ID($ne), 1), 0, std::array{a, b}); } + T gt(T a, T b, int) { return graph.add(CxxFunction(ID($gt), 1), 0, std::array{a, b}); } + T ge(T a, T b, int) { return graph.add(CxxFunction(ID($ge), 1), 0, std::array{a, b}); } + T ugt(T a, T b, int) { return graph.add(CxxFunction(ID($ugt), 1), 0, std::array{a, b}); } + T uge(T a, T b, int) { return graph.add(CxxFunction(ID($uge), 1), 0, std::array{a, b}); } + T logical_shift_left(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($shl), y_width, {{ID(WIDTH), y_width}}), 0, std::array{a, b}); } + T logical_shift_right(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($shr), y_width, {{ID(WIDTH), y_width}}), 0, std::array{a, b}); } + T arithmetic_shift_right(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($asr), y_width, {{ID(WIDTH), y_width}}), 0, std::array{a, b}); } + + T constant(RTLIL::Const value) { + return graph.add(CxxFunction(ID($$const), value.size(), {{ID(value), value}}), 0); + } + T input(IdString name, int width) { return graph.add(CxxFunction(ID($$input), width, {{name, {}}}), 0); } + T state(IdString name, int width) { return graph.add(CxxFunction(ID($$state), width, {{name, {}}}), 0); } + T cell_output(T cell, IdString type, IdString name, int width) { + if (is_single_output(type)) + return cell; + else + return graph.add(CxxFunction(ID($$cell_output), width, {{name, {}}}), 0, std::array{cell}); + } + T multiple(vector args, int width) { + return graph.add(CxxFunction(ID($$multiple), width), 0, args); + } + T undriven(int width) { + return graph.add(CxxFunction(ID($$undriven), width), 0); + } + + T create_pending(int width) { + return graph.add(CxxFunction(ID($$pending), width), 0); + } + void update_pending(T pending, T node) { + assert(pending.function().name == ID($$pending)); + pending.set_function(CxxFunction(ID($$buf), pending.function().width)); + pending.append_arg(node); + } + void declare_output(T node, IdString name) { + node.assign_key(name); + } + void declare_state(T node, IdString name) { + node.assign_key(name); + } + void suggest_name(T node, IdString name) { + node.sparse_attr() = name; + } +}; + +struct FunctionalCxxBackend : public Backend +{ + FunctionalCxxBackend() : Backend("functional_cxx", "convert design to C++ using the functional backend") {} + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + } + + CxxComputeGraph calculate_compute_graph(RTLIL::Module *module) + { + CxxComputeGraph compute_graph; + CxxComputeGraphFactory factory(compute_graph); + ComputeGraphConstruction construction(factory); + construction.add_module(module); + construction.process_queue(); + + // Perform topo sort and detect SCCs + CxxComputeGraph::SccAdaptor compute_graph_scc(compute_graph); + + bool scc = false; + std::vector perm; + topo_sorted_sccs(compute_graph_scc, [&](int *begin, int *end) { + perm.insert(perm.end(), begin, end); + if (end > begin + 1) + { + log_warning("SCC:"); + for (int *i = begin; i != end; ++i) + log(" %d(%s)(%s)", *i, compute_graph[*i].function().name.c_str(), compute_graph[*i].has_sparse_attr() ? compute_graph[*i].sparse_attr().c_str() : ""); + log("\n"); + scc = true; + } + }, /* sources_first */ true); + compute_graph.permute(perm); + if(scc) log_error("combinational loops, aborting\n"); + + // Forward $$buf + std::vector alias; + perm.clear(); + + for (int i = 0; i < compute_graph.size(); ++i) + { + auto node = compute_graph[i]; + if (node.function().name == ID($$buf) && node.arg(0).index() < i) + { + int target_index = alias[node.arg(0).index()]; + auto target_node = compute_graph[perm[target_index]]; + if(!target_node.has_sparse_attr() && node.has_sparse_attr()) + target_node.sparse_attr() = node.sparse_attr(); + alias.push_back(target_index); + } + else + { + alias.push_back(GetSize(perm)); + perm.push_back(i); + } + } + compute_graph.permute(perm, alias); + return compute_graph; + } + + void printCxx(std::ostream &stream, std::string, std::string const & name, CxxComputeGraph &compute_graph) + { + dict inputs, state; + CxxWriter f(stream); + + // Dump the compute graph + for (int i = 0; i < compute_graph.size(); ++i) + { + auto ref = compute_graph[i]; + if(ref.function().name == ID($$input)) + inputs[ref.function().parameters.begin()->first] = ref.function().width; + if(ref.function().name == ID($$state)) + state[ref.function().parameters.begin()->first] = ref.function().width; + } + f.printf("#include \"sim.h\"\n"); + CxxStruct input_struct(name + "_Inputs"); + for (auto const &input : inputs) + input_struct.insert(input.first, "Signal<" + std::to_string(input.second) + ">"); + CxxStruct output_struct(name + "_Outputs"); + for (auto const &key : compute_graph.keys()) + if(state.count(key.first) == 0) + output_struct.insert(key.first, "Signal<" + std::to_string(compute_graph[key.second].function().width) + ">"); + CxxStruct state_struct(name + "_State"); + for (auto const &state_var : state) + state_struct.insert(state_var.first, "Signal<" + std::to_string(state_var.second) + ">"); + + idict node_names; + CxxScope locals; + + input_struct.print(f); + output_struct.print(f); + state_struct.print(f); + + f.printf("void %s(%s_Inputs const &input, %s_Outputs &output, %s_State const ¤t_state, %s_State &next_state)\n{\n", name.c_str(), name.c_str(), name.c_str(), name.c_str(), name.c_str()); + locals.reserve("input"); + locals.reserve("output"); + locals.reserve("current_state"); + locals.reserve("next_state"); + for (int i = 0; i < compute_graph.size(); ++i) + { + auto ref = compute_graph[i]; + int width = ref.function().width; + std::string name; + if(ref.has_sparse_attr()) + name = locals.insert(ref.sparse_attr()); + else + name = locals.insert("\\n" + std::to_string(i)); + node_names(name); + if(ref.function().name == ID($$input)) + f.printf("\tSignal<%d> %s = input.%s;\n", width, name.c_str(), input_struct[ref.function().parameters.begin()->first].c_str()); + else if(ref.function().name == ID($$state)) + f.printf("\tSignal<%d> %s = current_state.%s;\n", width, name.c_str(), state_struct[ref.function().parameters.begin()->first].c_str()); + else if(ref.function().name == ID($$buf)) + f.printf("\tSignal<%d> %s = %s;\n", width, name.c_str(), node_names[ref.arg(0).index()].c_str()); + else if(ref.function().name == ID($$cell_output)) + f.printf("\tSignal<%d> %s = %s.%s;\n", width, name.c_str(), node_names[ref.arg(0).index()].c_str(), RTLIL::unescape_id(ref.function().parameters.begin()->first).c_str()); + else if(ref.function().name == ID($$const)){ + auto c = ref.function().parameters.begin()->second; + if(c.size() <= 32){ + f.printf("\tSignal<%d> %s = $const<%d>(%#x);\n", width, name.c_str(), width, (uint32_t) c.as_int()); + }else{ + f.printf("\tSignal<%d> %s = $const<%d>({%#x", width, name.c_str(), width, (uint32_t) c.as_int()); + while(c.size() > 32){ + c = c.extract(32, c.size() - 32); + f.printf(", %#x", c.as_int()); + } + f.printf("});\n"); + } + }else if(ref.function().name == ID($$undriven)) + f.printf("\tSignal<%d> %s; //undriven\n", width, name.c_str()); + else if(ref.function().name == ID($$slice)) + f.printf("\tSignal<%d> %s = slice<%d>(%s, %d);\n", width, name.c_str(), width, node_names[ref.arg(0).index()].c_str(), ref.function().parameters.at(ID(offset)).as_int()); + else if(ref.function().name == ID($$concat)){ + f.printf("\tauto %s = concat(", name.c_str()); + for (int i = 0, end = ref.size(); i != end; ++i){ + if(i > 0) + f.printf(", "); + f.printf("%s", node_names[ref.arg(i).index()].c_str()); + } + f.printf(");\n"); + }else{ + f.printf("\t"); + if(ref.function().width > 0) + f.printf("Signal<%d>", ref.function().width); + else + f.printf("%s_Outputs", log_id(ref.function().name)); + f.printf(" %s = %s", name.c_str(), log_id(ref.function().name)); + if(ref.function().parameters.count(ID(WIDTH))){ + f.printf("<%d>", ref.function().parameters.at(ID(WIDTH)).as_int()); + } + f.printf("("); + for (int i = 0, end = ref.size(); i != end; ++i) + f.printf("%s%s", i>0?", ":"", node_names[ref.arg(i).index()].c_str()); + f.printf("); //"); + for (auto const ¶m : ref.function().parameters) + { + if (param.second.empty()) + f.printf("[%s]", log_id(param.first)); + else + f.printf("[%s=%s]", log_id(param.first), log_const(param.second)); + } + f.printf("\n"); + } + } + + for (auto const &key : compute_graph.keys()) + { + f.printf("\t%s.%s = %s;\n", state.count(key.first) > 0 ? "next_state" : "output", state_struct[key.first].c_str(), node_names[key.second].c_str()); + } + f.printf("}\n"); + } + + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing Functional C++ backend.\n"); + + size_t argidx = 1; + extra_args(f, filename, args, argidx, design); + + for (auto module : design->selected_modules()) { + log("Dumping module `%s'.\n", module->name.c_str()); + auto compute_graph = calculate_compute_graph(module); + printCxx(*f, filename, RTLIL::unescape_id(module->name), compute_graph); + } + } +} FunctionalCxxBackend; + +PRIVATE_NAMESPACE_END diff --git a/backends/functional/cxx_runtime/sim.h b/backends/functional/cxx_runtime/sim.h new file mode 100644 index 00000000000..4e7d9b60142 --- /dev/null +++ b/backends/functional/cxx_runtime/sim.h @@ -0,0 +1,366 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2024 Emily Schmidt + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef SIM_H +#define SIM_H + +#include + +template +using Signal = std::array; + +template +Signal slice(Signal const& a, size_t offset) +{ + Signal ret; + + std::copy(a.begin() + offset, a.begin() + offset + n, ret.begin()); + return ret; +} + +template +Signal $const(uint32_t val) +{ + size_t i; + Signal ret; + + for(i = 0; i < n; i++) + if(i < 32) + ret[i] = val & (1< +Signal $const(std::initializer_list vals) +{ + size_t k, i; + Signal ret; + + k = 0; + for (auto val : vals) { + for(i = 0; i < 32; i++) + if(i + k < n) + ret[i + k] = val & (1< +bool as_bool(Signal sig) +{ + for(int i = 0; i < n; i++) + if(sig[i]) + return true; + return false; +} + +template +uint32_t as_int(Signal sig) +{ + uint32_t ret = 0; + for(int i = 0; i < n; i++) + if(sig[i] && i < 32) + ret |= 1< +Signal $mux(Signal const& a, Signal const &b, Signal<1> const &s) +{ + return s[0] ? b : a; +} + +template +Signal $not(Signal const& a) +{ + Signal ret; + for(size_t i = 0; i < n; i++) + ret[i] = !a[i]; + return ret; +} + +template +Signal $neg(Signal const& a) +{ + Signal ret; + bool carry = true; + for(size_t i = 0; i < n; i++) { + int r = !a[i] + carry; + ret[i] = (r & 1) != 0; + carry = (r >> 1) != 0; + } + return ret; +} + +template +Signal<1> $reduce_or(Signal const& a) +{ + return { as_bool(a) }; +} + +template +Signal<1> $reduce_and(Signal const& a) +{ + for(size_t i = 0; i < n; i++) + if(!a[i]) + return { false }; + return { true }; +} + +template +Signal<1> $reduce_bool(Signal const& a) +{ + return { as_bool(a) }; +} + +template +Signal<1> $logic_and(Signal const& a, Signal const& b) +{ + return { as_bool(a) && as_bool(b) }; +} + +template +Signal<1> $logic_or(Signal const& a, Signal const& b) +{ + return { as_bool(a) || as_bool(b) }; +} + +template +Signal<1> $logic_not(Signal const& a) +{ + return { !as_bool(a) }; +} + +template +Signal $add(Signal const& a, Signal const &b) +{ + Signal ret; + size_t i; + int x = 0; + for(i = 0; i < n; i++){ + x += (int)a[i] + (int)b[i]; + ret[i] = x & 1; + x >>= 1; + } + return ret; +} +template +Signal $sub(Signal const& a, Signal const &b) +{ + Signal ret; + int x = 1; + for(size_t i = 0; i < n; i++){ + x += (int)a[i] + (int)!b[i]; + ret[i] = x & 1; + x >>= 1; + } + return ret; +} + +template +Signal<1> $uge(Signal const& a, Signal const &b) +{ + for(size_t i = n; i-- != 0; ) + if(a[i] != b[i]) + return { a[i] }; + return { true }; +} + +template +Signal<1> $ugt(Signal const& a, Signal const &b) +{ + for(size_t i = n; i-- != 0; ) + if(a[i] != b[i]) + return { a[i] }; + return { false }; +} + +template +Signal<1> $ge(Signal const& a, Signal const &b) +{ + if(a[n-1] != b[n-1]) + return { b[n-1] }; + return $uge(a, b); +} + +template +Signal<1> $gt(Signal const& a, Signal const &b) +{ + if(a[n-1] != b[n-1]) + return { b[n-1] }; + return $ugt(a, b); +} + +template Signal<1> $ule(Signal const& a, Signal const &b) { return $uge(b, a); } +template Signal<1> $ult(Signal const& a, Signal const &b) { return $ugt(b, a); } +template Signal<1> $le(Signal const& a, Signal const &b) { return $ge(b, a); } +template Signal<1> $lt(Signal const& a, Signal const &b) { return $gt(b, a); } + +template +Signal $and(Signal const& a, Signal const &b) +{ + Signal ret; + for(size_t i = 0; i < n; i++) + ret[i] = a[i] && b[i]; + return ret; +} + +template +Signal $or(Signal const& a, Signal const &b) +{ + Signal ret; + for(size_t i = 0; i < n; i++) + ret[i] = a[i] || b[i]; + return ret; +} + +template +Signal $xor(Signal const& a, Signal const &b) +{ + Signal ret; + for(size_t i = 0; i < n; i++) + ret[i] = a[i] != b[i]; + return ret; +} + +template +Signal $shl(Signal const& a, Signal const &b) +{ + if(nb >= sizeof(int) * 8 - 1) + for(size_t i = sizeof(int) * 8 - 1; i < nb; i++) + assert(!b[i]); + size_t amount = as_int(b); + Signal ret = $const(0); + if(amount < n){ + if(amount + na > n) + std::copy(a.begin(), a.begin() + (n - amount), ret.begin() + amount); + else + std::copy(a.begin(), a.end(), ret.begin() + amount); + } + return ret; +} + +template +Signal $shr(Signal const& a, Signal const &b) +{ + if(nb >= sizeof(int) * 8 - 1) + for(size_t i = sizeof(int) * 8 - 1; i < nb; i++) + assert(!b[i]); + size_t amount = as_int(b); + Signal ret; + for (size_t i = 0; i < n; i++) { + if(i + amount < n) + ret[i] = a[i + amount]; + else + ret[i] = false; + } + return ret; +} + +template +Signal $asr(Signal const& a, Signal const &b) +{ + if(nb >= sizeof(int) * 8 - 1) + for(size_t i = sizeof(int) * 8 - 1; i < nb; i++) + assert(!b[i]); + size_t amount = as_int(b); + Signal ret; + for (size_t i = 0; i < n; i++) { + if(i + amount < n) + ret[i] = a[i + amount]; + else + ret[i] = a[n - 1]; + } + return ret; +} + +template +Signal<1> $eq(Signal const& a, Signal const &b) +{ + for(size_t i = 0; i < n; i++) + if(a[i] != b[i]) + return { false }; + return { true }; +} + +template +Signal<1> $ne(Signal const& a, Signal const &b) +{ + for(size_t i = 0; i < n; i++) + if(a[i] != b[i]) + return { true }; + return { false }; +} + +template +Signal $pmux(Signal const& a, Signal const &b, Signal const &s) +{ + bool found; + Signal ret; + + found = false; + ret = a; + for(size_t i = 0; i < ns; i++){ + if(s[i]){ + if(found) + return $const(0); + found = true; + ret = slice(b, n * i); + } + } + return ret; +} + +template +Signal concat(Signal const& a, Signal const& b) +{ + Signal ret; + std::copy(a.begin(), a.end(), ret.begin()); + std::copy(b.begin(), b.end(), ret.begin() + n); + return ret; +} + +template +Signal $zero_extend(Signal const& a) +{ + assert(n >= m); + Signal ret; + std::copy(a.begin(), a.end(), ret.begin()); + for(size_t i = m; i < n; i++) + ret[i] = false; + return ret; +} + +template +Signal $sign_extend(Signal const& a) +{ + assert(n >= m); + Signal ret; + std::copy(a.begin(), a.end(), ret.begin()); + for(size_t i = m; i < n; i++) + ret[i] = a[m-1]; + return ret; +} + +#endif diff --git a/kernel/graphtools.h b/kernel/graphtools.h new file mode 100644 index 00000000000..1a59ef1b537 --- /dev/null +++ b/kernel/graphtools.h @@ -0,0 +1,332 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2024 Emily Schmidt + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef GRAPHTOOLS_H +#define GRAPHTOOLS_H + +#include "kernel/yosys.h" +#include "kernel/drivertools.h" +#include "kernel/functional.h" + +USING_YOSYS_NAMESPACE +YOSYS_NAMESPACE_BEGIN + +template +class CellSimplifier { + Factory &factory; + T reduce_shift_width(T b, int b_width, int y_width, int &reduced_b_width) { + log_assert(y_width > 0); + int new_width = sizeof(int) * 8 - __builtin_clz(y_width); + if (b_width <= new_width) { + reduced_b_width = b_width; + return b; + } else { + reduced_b_width = new_width; + T lower_b = factory.slice(b, b_width, 0, new_width); + T overflow = factory.gt(b, factory.constant(RTLIL::Const(y_width, b_width)), b_width); + return factory.mux(lower_b, factory.constant(RTLIL::Const(y_width, new_width)), overflow, new_width); + } + } +public: + T reduce_or(T a, int width) { + if (width == 1) + return a; + return factory.reduce_or(a, width); + } + T extend(T a, int in_width, int out_width, bool is_signed) { + if(in_width == out_width) + return a; + if(in_width > out_width) + return factory.slice(a, in_width, 0, out_width); + return factory.extend(a, in_width, out_width, is_signed); + } + T logical_shift_left(T a, T b, int y_width, int b_width) { + int reduced_b_width; + T reduced_b = reduce_shift_width(b, b_width, y_width, reduced_b_width); + return factory.logical_shift_left(a, reduced_b, y_width, reduced_b_width); + } + T logical_shift_right(T a, T b, int y_width, int b_width) { + int reduced_b_width; + T reduced_b = reduce_shift_width(b, b_width, y_width, reduced_b_width); + return factory.logical_shift_right(a, reduced_b, y_width, reduced_b_width); + } + T arithmetic_shift_right(T a, T b, int y_width, int b_width) { + int reduced_b_width; + T reduced_b = reduce_shift_width(b, b_width, y_width, reduced_b_width); + return factory.arithmetic_shift_right(a, reduced_b, y_width, reduced_b_width); + } + CellSimplifier(Factory &f) : factory(f) {} + T handle(IdString cellType, dict parameters, dict inputs) + { + int a_width = parameters.at(ID(A_WIDTH), Const(-1)).as_int(); + int b_width = parameters.at(ID(B_WIDTH), Const(-1)).as_int(); + int y_width = parameters.at(ID(Y_WIDTH), Const(-1)).as_int(); + bool a_signed = parameters.at(ID(A_SIGNED), Const(0)).as_bool(); + bool b_signed = parameters.at(ID(B_SIGNED), Const(0)).as_bool(); + if(cellType.in({ID($add), ID($sub), ID($and), ID($or), ID($xor), ID($xnor)})){ + bool is_signed = a_signed && b_signed; + T a = extend(inputs.at(ID(A)), a_width, y_width, is_signed); + T b = extend(inputs.at(ID(B)), b_width, y_width, is_signed); + if(cellType == ID($add)) + return factory.add(a, b, y_width); + else if(cellType == ID($sub)) + return factory.sub(a, b, y_width); + else if(cellType == ID($and)) + return factory.bitwise_and(a, b, y_width); + else if(cellType == ID($or)) + return factory.bitwise_or(a, b, y_width); + else if(cellType == ID($xor)) + return factory.bitwise_xor(a, b, y_width); + else if(cellType == ID($xnor)) + return factory.bitwise_not(factory.bitwise_xor(a, b, y_width), y_width); + else + log_abort(); + }else if(cellType.in({ID($eq), ID($ne), ID($eqx), ID($nex), ID($le), ID($lt), ID($ge), ID($gt)})){ + bool is_signed = a_signed && b_signed; + int width = max(a_width, b_width); + T a = extend(inputs.at(ID(A)), a_width, width, is_signed); + T b = extend(inputs.at(ID(B)), b_width, width, is_signed); + if(cellType.in({ID($eq), ID($eqx)})) + return extend(factory.eq(a, b, width), 1, y_width, false); + if(cellType.in({ID($ne), ID($nex)})) + return extend(factory.ne(a, b, width), 1, y_width, false); + else if(cellType == ID($lt)) + return extend(is_signed ? factory.gt(b, a, width) : factory.ugt(b, a, width), 1, y_width, false); + else if(cellType == ID($le)) + return extend(is_signed ? factory.ge(b, a, width) : factory.uge(b, a, width), 1, y_width, false); + else if(cellType == ID($gt)) + return extend(is_signed ? factory.gt(a, b, width) : factory.ugt(a, b, width), 1, y_width, false); + else if(cellType == ID($ge)) + return extend(is_signed ? factory.ge(a, b, width) : factory.uge(a, b, width), 1, y_width, false); + else + log_abort(); + }else if(cellType.in({ID($logic_or), ID($logic_and)})){ + T a = reduce_or(inputs.at(ID(A)), a_width); + T b = reduce_or(inputs.at(ID(B)), b_width); + T y = cellType == ID($logic_and) ? factory.bitwise_and(a, b, 1) : factory.bitwise_or(a, b, 1); + return extend(y, 1, y_width, false); + }else if(cellType == ID($not)){ + T a = extend(inputs.at(ID(A)), a_width, y_width, a_signed); + return factory.bitwise_not(a, y_width); + }else if(cellType == ID($pos)){ + return extend(inputs.at(ID(A)), a_width, y_width, a_signed); + }else if(cellType == ID($neg)){ + T a = extend(inputs.at(ID(A)), a_width, y_width, a_signed); + return factory.neg(a, y_width); + }else if(cellType == ID($logic_not)){ + T a = reduce_or(inputs.at(ID(A)), a_width); + T y = factory.bitwise_not(a, 1); + return extend(y, 1, y_width, false); + }else if(cellType.in({ID($reduce_or), ID($reduce_bool)})){ + T a = reduce_or(inputs.at(ID(A)), a_width); + return extend(a, 1, y_width, false); + }else if(cellType == ID($reduce_and)){ + T a = factory.reduce_and(inputs.at(ID(A)), a_width); + return extend(a, 1, y_width, false); + }else if(cellType.in({ID($reduce_xor), ID($reduce_xnor)})){ + T a = factory.reduce_xor(inputs.at(ID(A)), a_width); + T y = cellType == ID($reduce_xnor) ? factory.bitwise_not(a, 1) : a; + return extend(y, 1, y_width, false); + }else if(cellType == ID($shl) || cellType == ID($sshl)){ + T a = extend(inputs.at(ID(A)), a_width, y_width, a_signed); + T b = inputs.at(ID(B)); + return logical_shift_left(a, b, y_width, b_width); + }else if(cellType == ID($shr) || cellType == ID($sshr)){ + int width = max(a_width, y_width); + T a = extend(inputs.at(ID(A)), a_width, width, a_signed); + T b = inputs.at(ID(B)); + T y = a_signed && cellType == ID($sshr) ? + arithmetic_shift_right(a, b, width, b_width) : + logical_shift_right(a, b, width, b_width); + return extend(y, width, y_width, a_signed); + }else if(cellType == ID($shiftx) || cellType == ID($shift)){ + int width = max(a_width, y_width); + T a = extend(inputs.at(ID(A)), a_width, width, cellType == ID($shift) && a_signed); + T b = inputs.at(ID(B)); + T shr = logical_shift_right(a, b, width, b_width); + if(b_signed) { + T sign_b = factory.slice(b, b_width, b_width - 1, 1); + T shl = logical_shift_left(a, factory.neg(b, b_width), width, b_width); + T y = factory.mux(shr, shl, sign_b, width); + return extend(y, width, y_width, false); + } else { + return extend(shr, width, y_width, false); + } + }else if(cellType == ID($mux)){ + int width = parameters.at(ID(WIDTH)).as_int(); + return factory.mux(inputs.at(ID(A)), inputs.at(ID(B)), inputs.at(ID(S)), width); + }else if(cellType == ID($pmux)){ + int width = parameters.at(ID(WIDTH)).as_int(); + int s_width = parameters.at(ID(S_WIDTH)).as_int(); + return factory.pmux(inputs.at(ID(A)), inputs.at(ID(B)), inputs.at(ID(S)), width, s_width); + }else if(cellType == ID($concat)){ + T a = inputs.at(ID(A)); + T b = inputs.at(ID(B)); + return factory.concat(a, a_width, b, b_width); + }else if(cellType == ID($slice)){ + int offset = parameters.at(ID(OFFSET)).as_int(); + T a = inputs.at(ID(A)); + return factory.slice(a, a_width, offset, y_width); + }else{ + log_error("unhandled cell in CellSimplifier %s\n", cellType.c_str()); + } + } +}; + +template +class ComputeGraphConstruction { + std::deque queue; + dict graph_nodes; + idict cells; + DriverMap driver_map; + Factory& factory; + CellSimplifier simplifier; + + T enqueue(DriveSpec const &spec) + { + auto it = graph_nodes.find(spec); + if(it == graph_nodes.end()){ + auto node = factory.create_pending(spec.size()); + graph_nodes.insert({spec, node}); + queue.emplace_back(spec); + return node; + }else + return it->second; + } +public: + ComputeGraphConstruction(Factory &f) : factory(f), simplifier(f) {} + void add_module(Module *module) + { + driver_map.add(module); + for (auto cell : module->cells()) { + if (cell->type.in(ID($assert), ID($assume), ID($cover), ID($check))) + enqueue(DriveBitMarker(cells(cell), 0)); + } + for (auto wire : module->wires()) { + if (wire->port_output) { + T node = enqueue(DriveChunk(DriveChunkWire(wire, 0, wire->width))); + factory.declare_output(node, wire->name); + } + } + } + void process_queue() + { + for (; !queue.empty(); queue.pop_front()) { + DriveSpec spec = queue.front(); + T pending = graph_nodes.at(spec); + + if (spec.chunks().size() > 1) { + auto chunks = spec.chunks(); + T node = enqueue(chunks[0]); + int width = chunks[0].size(); + for(size_t i = 1; i < chunks.size(); i++) { + node = factory.concat(node, width, enqueue(chunks[i]), chunks[i].size()); + width += chunks[i].size(); + } + factory.update_pending(pending, node); + } else if (spec.chunks().size() == 1) { + DriveChunk chunk = spec.chunks()[0]; + if (chunk.is_wire()) { + DriveChunkWire wire_chunk = chunk.wire(); + if (wire_chunk.is_whole()) { + if (wire_chunk.wire->port_input) { + T node = factory.input(wire_chunk.wire->name, wire_chunk.width); + factory.suggest_name(node, wire_chunk.wire->name); + factory.update_pending(pending, node); + } else { + DriveSpec driver = driver_map(DriveSpec(wire_chunk)); + T node = enqueue(driver); + factory.suggest_name(node, wire_chunk.wire->name); + factory.update_pending(pending, node); + } + } else { + DriveChunkWire whole_wire(wire_chunk.wire, 0, wire_chunk.wire->width); + T node = factory.slice(enqueue(whole_wire), wire_chunk.wire->width, wire_chunk.offset, wire_chunk.width); + factory.update_pending(pending, node); + } + } else if (chunk.is_port()) { + DriveChunkPort port_chunk = chunk.port(); + if (port_chunk.is_whole()) { + if (driver_map.celltypes.cell_output(port_chunk.cell->type, port_chunk.port)) { + if (port_chunk.cell->type.in(ID($dff), ID($ff))) + { + Cell *cell = port_chunk.cell; + T node = factory.state(cell->name, port_chunk.width); + factory.suggest_name(node, port_chunk.cell->name); + factory.update_pending(pending, node); + for (auto const &conn : cell->connections()) { + if (driver_map.celltypes.cell_input(cell->type, conn.first)) { + T node = enqueue(DriveChunkPort(cell, conn)); + factory.declare_state(node, cell->name); + } + } + } + else + { + T cell = enqueue(DriveChunkMarker(cells(port_chunk.cell), 0, port_chunk.width)); + factory.suggest_name(cell, port_chunk.cell->name); + T node = factory.cell_output(cell, port_chunk.cell->type, port_chunk.port, port_chunk.width); + factory.suggest_name(node, port_chunk.cell->name.str() + "$" + port_chunk.port.str()); + factory.update_pending(pending, node); + } + } else { + DriveSpec driver = driver_map(DriveSpec(port_chunk)); + factory.update_pending(pending, enqueue(driver)); + } + } else { + DriveChunkPort whole_port(port_chunk.cell, port_chunk.port, 0, GetSize(port_chunk.cell->connections().at(port_chunk.port))); + T node = factory.slice(enqueue(whole_port), whole_port.width, port_chunk.offset, port_chunk.width); + factory.update_pending(pending, node); + } + } else if (chunk.is_constant()) { + T node = factory.constant(chunk.constant()); + factory.suggest_name(node, "$const" + std::to_string(chunk.size()) + "b" + chunk.constant().as_string()); + factory.update_pending(pending, node); + } else if (chunk.is_multiple()) { + vector args; + for (auto const &driver : chunk.multiple().multiple()) + args.push_back(enqueue(driver)); + T node = factory.multiple(args, chunk.size()); + factory.update_pending(pending, node); + } else if (chunk.is_marker()) { + Cell *cell = cells[chunk.marker().marker]; + dict connections; + for(auto const &conn : cell->connections()) { + if(driver_map.celltypes.cell_input(cell->type, conn.first)) + connections.insert({ conn.first, enqueue(DriveChunkPort(cell, conn)) }); + } + T node = simplifier.handle(cell->type, cell->parameters, connections); + factory.update_pending(pending, node); + } else if (chunk.is_none()) { + T node = factory.undriven(chunk.size()); + factory.update_pending(pending, node); + } else { + log_error("unhandled drivespec: %s\n", log_signal(chunk)); + log_abort(); + } + } else { + log_abort(); + } + } + } +}; + +YOSYS_NAMESPACE_END + +#endif From e8f510113e6217a148d84b406fcf7fb84b8786a3 Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Thu, 23 May 2024 11:40:41 +0100 Subject: [PATCH 11/51] add initial version of functional smtlib backend --- backends/functional/Makefile.inc | 1 + backends/functional/cxx.cc | 4 +- backends/functional/smtlib.cc | 541 +++++++++++++++++++++++++++++++ kernel/graphtools.h | 6 +- 4 files changed, 547 insertions(+), 5 deletions(-) create mode 100644 backends/functional/smtlib.cc diff --git a/backends/functional/Makefile.inc b/backends/functional/Makefile.inc index 011e662646c..c712d2aefe5 100644 --- a/backends/functional/Makefile.inc +++ b/backends/functional/Makefile.inc @@ -1 +1,2 @@ OBJS += backends/functional/cxx.o +OBJS += backends/functional/smtlib.o diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index 46ce88bd62c..c0444e7fe5a 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -214,10 +214,10 @@ class CxxComputeGraphFactory { pending.set_function(CxxFunction(ID($$buf), pending.function().width)); pending.append_arg(node); } - void declare_output(T node, IdString name) { + void declare_output(T node, IdString name, int) { node.assign_key(name); } - void declare_state(T node, IdString name) { + void declare_state(T node, IdString name, int) { node.assign_key(name); } void suggest_name(T node, IdString name) { diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc new file mode 100644 index 00000000000..f6af797919b --- /dev/null +++ b/backends/functional/smtlib.cc @@ -0,0 +1,541 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2024 Emily Schmidt + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/drivertools.h" +#include "kernel/topo_scc.h" +#include "kernel/functional.h" +#include "kernel/graphtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct SmtlibScope { + pool used_names; + dict name_map; + + SmtlibScope() { + /*for(const char **p = reserved_keywords; *p != nullptr; p++) + reserve(*p);*/ + } + void reserve(std::string name) { + used_names.insert(name); + } + std::string insert(IdString id) { + std::string str = RTLIL::unescape_id(id); + for(size_t i = 0; i < str.size(); i++) + if(!((unsigned char)str[i] < 0x80 && (isalnum(str[i]) || strchr("~!@$%^&*_-+=<>.?/", str[i])))) + str[i] = '_'; + if(used_names.count(str) == 0){ + used_names.insert(str); + name_map.insert({id, str}); + return str; + } + for (int idx = 0 ; ; idx++){ + std::string suffixed = str + "_" + std::to_string(idx); + if (used_names.count(suffixed) == 0) { + used_names.insert(suffixed); + if(name_map.count(id) == 0) + name_map.insert({id, suffixed}); + return suffixed; + } + } + } + std::string operator[](IdString id) { + if(name_map.count(id) > 0) + return name_map[id]; + else + return insert(id); + } +}; + +struct SmtlibWriter { + std::ostream &f; + SmtlibWriter(std::ostream &out) : f(out) {} + void printf(const char *fmt, ...) + { + va_list va; + va_start(va, fmt); + f << vstringf(fmt, va); + va_end(va); + } + template + SmtlibWriter & operator <<(T &&arg) { + f << std::forward(arg); + return *this; + } +}; + +struct Arg { + int n; + explicit Arg(int n_) : n(n_) {} + bool operator ==(Arg const &other) const { return n == other.n; } +}; + +class SExpr { + enum class Type { + None, + List, + Atom, + Arg, + }; + Type type = Type::None; + union { + std::string atom_; + vector list_; + Arg arg_; + }; + void set_none() { + switch(type) { + case Type::None: break; + case Type::Atom: atom_.~basic_string(); break; + case Type::List: list_.~vector(); break; + case Type::Arg: arg_.~Arg(); break; + } + type = Type::None; + } +public: + SExpr() {} + SExpr(const char *atom) : type(Type::Atom), atom_(atom) {} + SExpr(std::string atom) : type(Type::Atom), atom_(atom) {} + SExpr(int n) : type(Type::Atom), atom_(std::to_string(n)) {} + SExpr(RTLIL::Const const & n) : type(Type::Atom) { + new(&atom_) std::string("#b"); + atom_.reserve(n.size() + 2); + for (size_t i = n.size(); i > 0; i--) + if(n[i-1] == State::S1) + atom_ += "1"; + else + atom_ += "0"; + } + SExpr(vector &&list) : type(Type::List), list_(list) {} + SExpr(std::initializer_list list) : type(Type::List), list_(list) {} + SExpr(Arg arg) : type(Type::Arg), arg_(arg) {} + SExpr(SExpr const &other) { *this = other; } + SExpr(SExpr &&other) { *this = std::move(other); } + SExpr &operator =(SExpr const &other) { + set_none(); + switch(other.type) { + case Type::None: break; + case Type::Atom: new(&atom_) std::string(other.atom_); break; + case Type::List: new(&list_) vector(other.list_); break; + case Type::Arg: new(&arg_) Arg(other.arg_); break; + } + type = other.type; + return *this; + } + SExpr &operator =(SExpr &&other) { + set_none(); + switch(other.type) { + case Type::None: break; + case Type::Atom: new(&atom_) std::string(std::move(other.atom_)); break; + case Type::List: new(&list_) vector(std::move(other.list_)); break; + case Type::Arg: new(&arg_) Arg(std::move(other.arg_)); break; + } + type = other.type; + return *this; + } + ~SExpr() { set_none(); } + bool operator==(SExpr const &other) const { + if(type != other.type) return false; + switch(type) { + case Type::None: return true; + case Type::Atom: return atom_ == other.atom_; + case Type::List: return list_ == other.list_; + case Type::Arg: return arg_ == other.arg_; + } + } + bool is_none() const { return type == Type::None; } + bool is_atom() const { return type == Type::Atom; } + bool is_list() const { return type == Type::List; } + bool is_arg() const { return type == Type::Arg; } + std::string const &atom() const { log_assert(is_atom()); return atom_; } + std::vector const &list() const { log_assert(is_list()); return list_; } + Arg const &arg() const { log_assert(is_arg()); return arg_; } + unsigned int hash() const { + unsigned int inner; + switch(type) { + case Type::None: inner = 0; break; + case Type::Atom: inner = mkhash(atom_); break; + case Type::List: inner = mkhash(list_); break; + case Type::Arg: inner = arg_.n; break; + } + return mkhash((unsigned int) type, inner); + } + SExpr subst_args(std::vector const & args) const { + switch(type) { + case Type::None: + case Type::Atom: + return *this; + case Type::List: { + vector ret; + for(auto & a : list_) + ret.emplace_back(a.subst_args(args)); + return SExpr(std::move(ret)); + } + case Type::Arg: + if(arg_.n >= 1 && (size_t)arg_.n <= args.size()) + return args[arg_.n - 1]; + else + return *this; + } + } +}; + +std::ostream& operator << (std::ostream &os, SExpr const &s) { + if(s.is_atom()) + os << s.atom(); + else if(s.is_list()){ + os << "("; + bool first = true; + for(auto &el: s.list()) { + if(!first) os << " "; + else first = false; + os << el; + } + os << ")"; + }else if(s.is_arg()) + os << "#" << s.arg().n; + else if(s.is_none()) + os << ""; + else + os << "???"; + return os; +} + +struct SmtlibStruct { + SmtlibScope &scope; + std::string name; + idict members; + vector widths; + vector accessors; + SmtlibStruct(std::string name, SmtlibScope &scope) : scope(scope), name(name) { + } + std::string insert(IdString field, int width) { + if(members.at(field, -1) == -1){ + members(field); + scope.insert(field); + widths.push_back(width); + accessors.push_back(scope.insert(std::string("\\") + name + "_" + RTLIL::unescape_id(field))); + } + return scope[field]; + } + void print(SmtlibWriter &f) { + f.printf("(declare-datatype %s ((%s\n", name.c_str(), name.c_str()); + for (size_t i = 0; i < members.size(); i++) + f.printf(" (%s (_ BitVec %d))\n", accessors[i].c_str(), widths[i]); + f.printf(")))\n"); + } + void print_value(SmtlibWriter &f, dict values, int indentation) { + std::string spaces(indentation, ' '); + f << spaces << "(" << name << "\n"; + for (size_t i = 0; i < members.size(); i++) + f << spaces << " " << values[members[i]] << " ; " << RTLIL::unescape_id(members[i]) << "\n"; + f << spaces << ")\n"; + } + SExpr access(SExpr record, IdString member) { + int i = members.at(member); + return SExpr{accessors[i], record}; + } + std::string operator[](IdString field) { + return scope[field]; + } +}; + +struct Node { + SExpr expr; + int width; + + Node(SExpr &&expr, int width) : expr(std::move(expr)), width(width) {} + + bool operator==(Node const &other) const { + return expr == other.expr && width == other.width; + } + + unsigned int hash() const { + return mkhash(expr.hash(), width); + } +}; + +typedef ComputeGraph SmtlibComputeGraph; + +struct SmtlibModule { + std::string name; + SmtlibScope global_scope; + SmtlibStruct input_struct; + SmtlibStruct output_struct; + SmtlibStruct state_struct; + SmtlibComputeGraph compute_graph; + + SmtlibModule(std::string const &name) : + name(name), + input_struct(name + "_inputs", global_scope), + output_struct(name + "_outputs", global_scope), + state_struct(name + "_state", global_scope) + { } + void calculate_compute_graph(RTLIL::Module *module); + void write(std::ostream &stream); +}; + +class SmtlibComputeGraphFactory { + SmtlibModule &module; + SmtlibComputeGraph &graph; + using T = SmtlibComputeGraph::Ref; + static bool is_single_output(IdString type) + { + auto it = yosys_celltypes.cell_types.find(type); + return it != yosys_celltypes.cell_types.end() && it->second.outputs.size() <= 1; + } + T node(SExpr &&expr, int width, std::initializer_list args) { + return graph.add(Node(std::move(expr), width), 0, args); + } + T shift(const char *name, T a, T b, int y_width, int b_width, bool a_signed = false) { + int width = max(y_width, b_width); + T a_ = y_width < width ? extend(a, y_width, width, a_signed) : a; + T b_ = b_width < width ? extend(b, b_width, width, false) : b; + T y_ = node(SExpr {name, Arg(1), Arg(2)}, width, {a_, b_}); + if(y_width < width) + return slice(y_, width, 0, y_width); + else + return y_; + } + SExpr from_bool(SExpr &&arg) { + return SExpr{"ite", std::move(arg), RTLIL::Const(State::S1), RTLIL::Const(State::S0)}; + } + SExpr to_bool(SExpr &&arg) { + return SExpr{"=", std::move(arg), RTLIL::Const(State::S1)}; + } + SExpr extract(SExpr &&arg, int offset, int out_width) { + return SExpr {SExpr {"_", "extract", offset + out_width - 1, offset}, std::move(arg)}; + } +public: + SmtlibComputeGraphFactory(SmtlibModule &mod) : module(mod), graph(mod.compute_graph) {} + T slice(T a, int in_width, int offset, int out_width) { + assert(offset + out_width <= in_width); + return node(extract(Arg(1), offset, out_width), out_width, {a}); + } + T extend(T a, int in_width, int out_width, bool is_signed) { + assert(in_width < out_width); + if(is_signed) + return node(SExpr {SExpr {"_", "sign_extend", out_width - in_width}, Arg(1)}, out_width, {a}); + else + return node(SExpr {SExpr {"_", "zero_extend", out_width - in_width}, Arg(1)}, out_width, {a}); + } + T concat(T a, int a_width, T b, int b_width) { + return node(SExpr {"concat", Arg(1), Arg(2)}, a_width + b_width, {a, b}); + } + T add(T a, T b, int width) { return node(SExpr {"bvadd", Arg(1), Arg(2)}, width, {a, b}); } + T sub(T a, T b, int width) { return node(SExpr {"bvsub", Arg(1), Arg(2)}, width, {a, b}); } + T bitwise_and(T a, T b, int width) { return node(SExpr {"bvand", Arg(1), Arg(2)}, width, {a, b}); } + T bitwise_or(T a, T b, int width) { return node(SExpr {"bvor", Arg(1), Arg(2)}, width, {a, b}); } + T bitwise_xor(T a, T b, int width) { return node(SExpr {"bvxor", Arg(1), Arg(2)}, width, {a, b}); } + T bitwise_not(T a, int width) { return node(SExpr {"bvnot", Arg(1)}, width, {a}); } + T neg(T a, int width) { return node(SExpr {"bvneg", Arg(1)}, width, {a}); } + T mux(T a, T b, T s, int width) { return node(SExpr {"ite", to_bool(Arg(1)), Arg(2), Arg(3)}, width, {s, a, b}); } + T pmux(T a, T b, T s, int width, int s_width) { + T rv = a; + for(int i = 0; i < s_width; i++) + rv = node(SExpr {"ite", to_bool(extract(Arg(1), i, 1)), extract(Arg(2), width * i, width), Arg(3)}, width, {s, b, rv}); + return rv; + } + T reduce_and(T a, int width) { return node(from_bool(SExpr {"=", Arg(1), RTLIL::Const(State::S1, width)}), 1, {a}); } + T reduce_or(T a, int width) { return node(from_bool(SExpr {"distinct", Arg(1), RTLIL::Const(State::S0, width)}), 1, {a}); } + T reduce_xor(T a, int) { return node(SExpr {"reduce_xor", Arg(1)}, 1, {a}); } + T eq(T a, T b, int) { return node(from_bool(SExpr {"=", Arg(1), Arg(2)}), 1, {a, b}); } + T ne(T a, T b, int) { return node(from_bool(SExpr {"distinct", Arg(1), Arg(2)}), 1, {a, b}); } + T gt(T a, T b, int) { return node(from_bool(SExpr {"bvsgt", Arg(1), Arg(2)}), 1, {a, b}); } + T ge(T a, T b, int) { return node(from_bool(SExpr {"bvsge", Arg(1), Arg(2)}), 1, {a, b}); } + T ugt(T a, T b, int) { return node(from_bool(SExpr {"bvugt", Arg(1), Arg(2)}), 1, {a, b}); } + T uge(T a, T b, int) { return node(from_bool(SExpr {"bvuge", Arg(1), Arg(2)}), 1, {a, b}); } + T logical_shift_left(T a, T b, int y_width, int b_width) { return shift("bvshl", a, b, y_width, b_width); } + T logical_shift_right(T a, T b, int y_width, int b_width) { return shift("bvlshl", a, b, y_width, b_width); } + T arithmetic_shift_right(T a, T b, int y_width, int b_width) { return shift("bvashr", a, b, y_width, b_width, true); } + + T constant(RTLIL::Const value) { return node(SExpr(value), value.size(), {}); } + T input(IdString name, int width) { + module.input_struct.insert(name, width); + return node(module.input_struct.access("inputs", name), width, {}); + } + T state(IdString name, int width) { + module.state_struct.insert(name, width); + return node(module.state_struct.access("current_state", name), width, {}); + } + T cell_output(T cell, IdString type, IdString name, int width) { + if (is_single_output(type)) + return cell; + else + return node(SExpr {"cell_output", Arg(1), RTLIL::unescape_id(name)}, width, {cell}); + } + T multiple(vector args, int width) { + vector expr; + expr.reserve(args.size() + 1); + expr.push_back("multiple"); + for(size_t i = 1; i <= args.size(); i++) + expr.push_back(Arg(i)); + return graph.add(Node(SExpr(std::move(expr)), width), 0, args); + } + T undriven(int width) { + return constant(RTLIL::Const(State::S0, width)); + //return node(SExpr {"undriven"}, width, {}); + } + T create_pending(int width) { + return node(SExpr(), width, {}); + } + void update_pending(T pending, T node) { + assert(pending.function().expr.is_none()); + pending.set_function(Node(Arg(1), pending.function().width)); + pending.append_arg(node); + } + void declare_output(T node, IdString name, int width) { + module.output_struct.insert(name, width); + node.assign_key(name); + } + void declare_state(T node, IdString name, int width) { + module.state_struct.insert(name, width); + node.assign_key(name); + } + void suggest_name(T node, IdString name) { + node.sparse_attr() = name; + } +}; + +void SmtlibModule::calculate_compute_graph(RTLIL::Module *module) +{ + SmtlibComputeGraphFactory factory(*this); + ComputeGraphConstruction construction(factory); + construction.add_module(module); + construction.process_queue(); + + // Perform topo sort and detect SCCs + SmtlibComputeGraph::SccAdaptor compute_graph_scc(compute_graph); + + bool scc = false; + std::vector perm; + topo_sorted_sccs(compute_graph_scc, [&](int *begin, int *end) { + perm.insert(perm.end(), begin, end); + if (end > begin + 1) + { + log_warning("SCC:"); + for (int *i = begin; i != end; ++i) + log(" %d", *i); + log("\n"); + scc = true; + } + }, /* sources_first */ true); + compute_graph.permute(perm); + if(scc) log_error("combinational loops, aborting\n"); + + // Forward $$buf + std::vector alias; + perm.clear(); + + for (int i = 0; i < compute_graph.size(); ++i) + { + auto node = compute_graph[i]; + if (node.function().expr == Arg(1) && node.arg(0).index() < i) + { + int target_index = alias[node.arg(0).index()]; + auto target_node = compute_graph[perm[target_index]]; + if(!target_node.has_sparse_attr() && node.has_sparse_attr()) + target_node.sparse_attr() = node.sparse_attr(); + alias.push_back(target_index); + } + else + { + alias.push_back(GetSize(perm)); + perm.push_back(i); + } + } + compute_graph.permute(perm, alias); +} + +void SmtlibModule::write(std::ostream &stream) +{ + SmtlibWriter f(stream); + + idict node_names; + SmtlibScope locals; + int paren_count = 0; + + input_struct.print(f); + output_struct.print(f); + state_struct.print(f); + + f << "(declare-datatypes ((Pair 2)) ((par (X Y) ((pair (first X) (second Y))))))\n"; + f.printf("(define-fun %s_step ((inputs %s_inputs) (current_state %s_state)) (Pair %s_outputs %s_state)\n", + name.c_str(), name.c_str(), name.c_str(), name.c_str(), name.c_str()); + + for (int i = 0; i < compute_graph.size(); ++i) + { + auto ref = compute_graph[i]; + std::string name; + if(ref.has_sparse_attr()) + name = locals.insert(ref.sparse_attr()); + else + name = locals.insert("\\n" + std::to_string(i)); + node_names(name); + vector args; + args.reserve(ref.size()); + for (int i = 0, end = ref.size(); i != end; ++i) + args.push_back(node_names[ref.arg(i).index()]); + f << " (let " << SExpr{{SExpr{name, ref.function().expr.subst_args(args)}}} << "\n"; + paren_count++; + } + dict outputs; + for(auto &a: compute_graph.keys()) + outputs.insert({a.first, node_names[a.second]}); + f.printf(" (pair \n"); + output_struct.print_value(f, outputs, 6); + state_struct.print_value(f, outputs, 6); + f.printf(" )\n"); + while(paren_count > 0){ + int n = min(paren_count, 80); + f << " " << std::string(n, ')') << "\n"; + paren_count -= n; + } + f.printf(")\n"); +} + +struct FunctionalSmtlibBackend : public Backend +{ + FunctionalSmtlibBackend() : Backend("functional_smtlib", "convert design to SMTLIB using the functional backend") {} + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + } + + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing Functional SMTLIB backend.\n"); + + size_t argidx = 1; + extra_args(f, filename, args, argidx, design); + + for (auto module : design->selected_modules()) { + log("Dumping module `%s'.\n", module->name.c_str()); + SmtlibModule smt(RTLIL::unescape_id(module->name)); + smt.calculate_compute_graph(module); + smt.write(*f); + } + } +} FunctionalSmtlibBackend; + +PRIVATE_NAMESPACE_END diff --git a/kernel/graphtools.h b/kernel/graphtools.h index 1a59ef1b537..adf4764c201 100644 --- a/kernel/graphtools.h +++ b/kernel/graphtools.h @@ -32,7 +32,7 @@ class CellSimplifier { Factory &factory; T reduce_shift_width(T b, int b_width, int y_width, int &reduced_b_width) { log_assert(y_width > 0); - int new_width = sizeof(int) * 8 - __builtin_clz(y_width); + int new_width = ceil_log2(y_width + 1); if (b_width <= new_width) { reduced_b_width = b_width; return b; @@ -221,7 +221,7 @@ class ComputeGraphConstruction { for (auto wire : module->wires()) { if (wire->port_output) { T node = enqueue(DriveChunk(DriveChunkWire(wire, 0, wire->width))); - factory.declare_output(node, wire->name); + factory.declare_output(node, wire->name, wire->width); } } } @@ -273,7 +273,7 @@ class ComputeGraphConstruction { for (auto const &conn : cell->connections()) { if (driver_map.celltypes.cell_input(cell->type, conn.first)) { T node = enqueue(DriveChunkPort(cell, conn)); - factory.declare_state(node, cell->name); + factory.declare_state(node, cell->name, port_chunk.width); } } } From a852d0c4cad8506101a18760ae2cdcfe93364880 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Fri, 24 May 2024 12:17:10 +0200 Subject: [PATCH 12/51] Some missing includes --- backends/functional/cxx.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index c0444e7fe5a..5038a9af252 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -17,6 +17,8 @@ * */ +#include +#include #include "kernel/yosys.h" #include "kernel/drivertools.h" #include "kernel/topo_scc.h" From 596f6dee7b8f13ce20aa6cdf33c375c305277dc8 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Fri, 24 May 2024 12:21:26 +0200 Subject: [PATCH 13/51] Move Driver* implementation to drivertools.cc --- kernel/drivertools.cc | 2633 ++++++++++++++++++++++++++++++----------- kernel/drivertools.h | 1639 +++++++------------------ 2 files changed, 2396 insertions(+), 1876 deletions(-) diff --git a/kernel/drivertools.cc b/kernel/drivertools.cc index 9627a467015..c3936277978 100644 --- a/kernel/drivertools.cc +++ b/kernel/drivertools.cc @@ -21,929 +21,2190 @@ YOSYS_NAMESPACE_BEGIN +DriveBitWire::DriveBitWire(Wire *wire, int offset) : wire(wire), offset(offset) {} + +bool DriveBitWire::operator==(const DriveBitWire &other) const +{ + return wire == other.wire && offset == other.offset; +} + +bool DriveBitWire::operator<(const DriveBitWire &other) const +{ + if (wire != other.wire) + return wire->name < other.wire->name; + return offset < other.offset; +} + +unsigned int DriveBitWire::hash() const +{ + return mkhash_add(wire->name.hash(), offset); +} + +DriveBitWire::operator SigBit() const +{ + return SigBit(wire, offset); +} + +DriveBitPort::DriveBitPort(Cell *cell, IdString port, int offset) + : cell(cell), port(port), offset(offset) {} + +bool DriveBitPort::operator==(const DriveBitPort &other) const +{ + return cell == other.cell && port == other.port && offset == other.offset; +} + +bool DriveBitPort::operator<(const DriveBitPort &other) const +{ + if (cell != other.cell) + return cell->name < other.cell->name; + if (port != other.port) + return port < other.port; + return offset < other.offset; +} + +unsigned int DriveBitPort::hash() const +{ + return mkhash_add(mkhash(cell->name.hash(), port.hash()), offset); +} + +DriveBitMarker::DriveBitMarker(int marker, int offset) : marker(marker), offset(offset) {} + +bool DriveBitMarker::operator==(const DriveBitMarker &other) const +{ + return marker == other.marker && offset == other.offset; +} + +bool DriveBitMarker::operator<(const DriveBitMarker &other) const +{ + if (marker != other.marker) + return marker < other.marker; + return offset < other.offset; +} + +unsigned int DriveBitMarker::hash() const +{ + return mkhash_add(marker, offset); +} + DriveBit::DriveBit(SigBit const &bit) { - if (bit.is_wire()) - *this = DriveBitWire(bit.wire, bit.offset); - else - *this = bit.data; + if (bit.is_wire()) + *this = DriveBitWire(bit.wire, bit.offset); + else + *this = bit.data; +} + +void DriveBit::merge(DriveBit const &other) +{ + if (other.type_ == DriveType::NONE) + return; + if (type_ == DriveType::NONE) { + *this = other; + return; + } + if (type_ != DriveType::MULTIPLE) { + DriveBitMultiple multi(std::move(*this)); + *this = std::move(multi); + } + multiple().merge(other); +} + +DriveBitMultiple::DriveBitMultiple() {} + +DriveBitMultiple::DriveBitMultiple(DriveBit const &single) +{ + multiple_.emplace(single); +} + +pool const &DriveBitMultiple::multiple() const +{ + return multiple_; +} + +void DriveBitMultiple::merge(DriveBitMultiple const &other) +{ + for (DriveBit const &single : other.multiple_) + merge(single); +} + +void DriveBitMultiple::merge(DriveBitMultiple &&other) +{ + for (DriveBit &single : other.multiple_) + merge(std::move(single)); +} + +void DriveBitMultiple::merge(DriveBit const &single) +{ + multiple_.emplace(single); +} + +void DriveBitMultiple::merge(DriveBit &&single) +{ + multiple_.emplace(std::move(single)); +} + +bool DriveBitMultiple::operator==(const DriveBitMultiple &other) const +{ + return multiple_ == other.multiple_; +} + +unsigned int DriveBitMultiple::hash() const +{ + return multiple_.hash(); +} + +DriveBit::DriveBit() {} + +DriveBit::DriveBit(DriveBit const &other) +{ + *this = other; +} + +DriveBit::DriveBit(DriveBit &&other) +{ + *this = std::move(other); +} + +DriveBit::DriveBit(State constant) +{ + *this = constant; +} + +DriveBit::DriveBit(DriveBitWire const &wire) +{ + *this = wire; +} + +DriveBit::DriveBit(DriveBitWire &&wire) +{ + *this = std::move(wire); +} + +DriveBit::DriveBit(DriveBitPort const &port) +{ + *this = port; +} + +DriveBit::DriveBit(DriveBitPort &&port) +{ + *this = std::move(port); +} + +DriveBit::DriveBit(DriveBitMarker const &marker) +{ + *this = marker; +} + +DriveBit::DriveBit(DriveBitMarker &&marker) +{ + *this = std::move(marker); +} + +DriveBit::DriveBit(DriveBitMultiple const &multiple) +{ + *this = multiple; +} + +DriveBit::DriveBit(DriveBitMultiple &&multiple) +{ + *this = std::move(multiple); +} + +DriveBit::~DriveBit() +{ + set_none(); +} + +void DriveBit::set_none() +{ + switch (type_) + { + case DriveType::NONE: + break; + case DriveType::CONSTANT: + break; + case DriveType::WIRE: + wire_.~DriveBitWire(); + break; + case DriveType::PORT: + port_.~DriveBitPort(); + break; + case DriveType::MARKER: + marker_.~DriveBitMarker(); + break; + case DriveType::MULTIPLE: + multiple_.~DriveBitMultiple(); + break; + } + type_ = DriveType::NONE; +} + +DriveBit &DriveBit::operator=(DriveBit const &other) +{ + switch (other.type_) + { + case DriveType::NONE: + set_none(); + break; + case DriveType::CONSTANT: + *this = other.constant_; + break; + case DriveType::WIRE: + *this = other.wire_; + break; + case DriveType::PORT: + *this = other.port_; + break; + case DriveType::MARKER: + *this = other.marker_; + break; + case DriveType::MULTIPLE: + *this = other.multiple_; + break; + } + return *this; +} + +DriveBit &DriveBit::operator=(DriveBit &&other) +{ + switch (other.type_) + { + case DriveType::NONE: + set_none(); + break; + case DriveType::CONSTANT: + *this = std::move(other.constant_); + break; + case DriveType::WIRE: + *this = std::move(other.wire_); + break; + case DriveType::PORT: + *this = std::move(other.port_); + break; + case DriveType::MARKER: + *this = std::move(other.marker_); + break; + case DriveType::MULTIPLE: + *this = std::move(other.multiple_); + break; + } + return *this; +} + +DriveBit &DriveBit::operator=(State constant) +{ + set_none(); + constant_ = constant; + type_ = DriveType::CONSTANT; + return *this; +} + +DriveBit &DriveBit::operator=(DriveBitWire const &wire) +{ + set_none(); + new (&wire_) DriveBitWire(wire); + type_ = DriveType::WIRE; + return *this; +} + +DriveBit &DriveBit::operator=(DriveBitWire &&wire) +{ + set_none(); + new (&wire_) DriveBitWire(std::move(wire)); + type_ = DriveType::WIRE; + return *this; +} + +DriveBit &DriveBit::operator=(DriveBitPort const &port) +{ + set_none(); + new (&port_) DriveBitPort(port); + type_ = DriveType::PORT; + return *this; +} + +DriveBit &DriveBit::operator=(DriveBitPort &&port) +{ + set_none(); + new (&port_) DriveBitPort(std::move(port)); + type_ = DriveType::PORT; + return *this; +} + +DriveBit &DriveBit::operator=(DriveBitMarker const &marker) +{ + set_none(); + new (&marker_) DriveBitMarker(marker); + type_ = DriveType::MARKER; + return *this; +} + +DriveBit &DriveBit::operator=(DriveBitMarker &&marker) +{ + set_none(); + new (&marker_) DriveBitMarker(std::move(marker)); + type_ = DriveType::MARKER; + return *this; +} + +DriveBit &DriveBit::operator=(DriveBitMultiple const &multiple) +{ + set_none(); + if (multiple.multiple().empty()) + return *this; + new (&multiple_) DriveBitMultiple(multiple); + type_ = DriveType::MULTIPLE; + return *this; +} + +DriveBit &DriveBit::operator=(DriveBitMultiple &&multiple) +{ + set_none(); + if (multiple.multiple().empty()) + return *this; + new (&multiple_) DriveBitMultiple(std::move(multiple)); + type_ = DriveType::MULTIPLE; + return *this; +} + +unsigned int DriveBit::hash() const +{ + unsigned int inner; + switch (type_) + { + case DriveType::NONE: + inner = 0; + break; + case DriveType::CONSTANT: + inner = constant_; + break; + case DriveType::WIRE: + inner = wire_.hash(); + break; + case DriveType::PORT: + inner = port_.hash(); + break; + case DriveType::MARKER: + inner = marker_.hash(); + break; + case DriveType::MULTIPLE: + inner = multiple_.hash(); + break; + } + return mkhash((unsigned int)type_, inner); +} + +bool DriveBit::operator==(const DriveBit &other) const +{ + if (type_ != other.type_) + return false; + + switch (type_) + { + case DriveType::NONE: + return true; + case DriveType::CONSTANT: + return constant_ == other.constant_; + case DriveType::WIRE: + return wire_ == other.wire_; + case DriveType::PORT: + return port_ == other.port_; + case DriveType::MARKER: + return marker_ == other.marker_; + case DriveType::MULTIPLE: + return multiple_ == other.multiple_; + } + log_assert(false); +} + +bool DriveBit::operator!=(const DriveBit &other) const +{ + return !(*this == other); +} + +bool DriveBit::operator<(const DriveBit &other) const +{ + if (type_ != other.type_) + return type_ < other.type_; + switch (type_) + { + case DriveType::NONE: + return false; + case DriveType::CONSTANT: + return constant_ < other.constant_; + case DriveType::WIRE: + return wire_ < other.wire_; + case DriveType::PORT: + return port_ < other.port_; + case DriveType::MARKER: + return marker_ < other.marker_; + case DriveType::MULTIPLE: + log_assert(!"TODO"); + } + log_abort(); +} + +DriveType DriveBit::type() const +{ + return type_; +} + +bool DriveBit::is_none() const +{ + return type_ == DriveType::NONE; +} + +bool DriveBit::is_constant() const +{ + return type_ == DriveType::CONSTANT; +} + +bool DriveBit::is_wire() const +{ + return type_ == DriveType::WIRE; +} + +bool DriveBit::is_port() const +{ + return type_ == DriveType::PORT; +} + +bool DriveBit::is_marker() const +{ + return type_ == DriveType::MARKER; +} + +bool DriveBit::is_multiple() const +{ + return type_ == DriveType::MULTIPLE; +} + +State &DriveBit::constant() +{ + log_assert(is_constant()); + return constant_; +} + +State const &DriveBit::constant() const +{ + log_assert(is_constant()); + return constant_; +} + +DriveBitWire &DriveBit::wire() +{ + log_assert(is_wire()); + return wire_; +} + +DriveBitWire const &DriveBit::wire() const +{ + log_assert(is_wire()); + return wire_; +} + +DriveBitPort &DriveBit::port() +{ + log_assert(is_port()); + return port_; +} + +DriveBitPort const &DriveBit::port() const +{ + log_assert(is_port()); + return port_; +} + +DriveBitMarker &DriveBit::marker() +{ + log_assert(is_marker()); + return marker_; +} + +DriveBitMarker const &DriveBit::marker() const +{ + log_assert(is_marker()); + return marker_; +} + +DriveBitMultiple &DriveBit::multiple() +{ + log_assert(is_multiple()); + return multiple_; +} + +DriveBitMultiple const &DriveBit::multiple() const +{ + log_assert(is_multiple()); + return multiple_; +} + +DriveBitMultiple DriveChunkMultiple::operator[](int i) const +{ + DriveBitMultiple result; + for (auto const &single : multiple_) + result.merge(single[i]); + return result; +} + +DriveChunkWire::DriveChunkWire(Wire *wire, int offset, int width) + : wire(wire), offset(offset), width(width) {} + +DriveChunkWire::DriveChunkWire(DriveBitWire const &bit) + : wire(bit.wire), offset(bit.offset), width(1) {} + +int DriveChunkWire::size() const { return width; } + +DriveBitWire DriveChunkWire::operator[](int i) const +{ + log_assert(i >= 0 && i < width); + return DriveBitWire(wire, offset + i); +} + +bool DriveChunkWire::is_whole() const +{ + return offset == 0 && width == wire->width; +} + +bool DriveChunkWire::operator==(const DriveChunkWire &other) const +{ + return wire == other.wire && offset == other.offset && width == other.width; +} + +bool DriveChunkWire::operator<(const DriveChunkWire &other) const +{ + if (wire != other.wire) + return wire->name < other.wire->name; + if (width != other.width) + return width < other.width; + return offset < other.offset; +} + +unsigned int DriveChunkWire::hash() const +{ + return mkhash_add(mkhash(wire->name.hash(), width), offset); +} + +DriveChunkWire::operator SigChunk() const +{ + return SigChunk(wire, offset, width); +} + +bool DriveChunkWire::can_append(DriveBitWire const &bit) const +{ + return bit.wire == wire && bit.offset == offset + width; +} + + + +bool DriveChunkWire::try_append(DriveBitWire const &bit) +{ + if (!can_append(bit)) + return false; + width += 1; + return true; +} + +bool DriveChunkWire::try_append(DriveChunkWire const &chunk) +{ + if (chunk.wire != wire || chunk.offset != offset + width) + return false; + width += chunk.width; + return true; +} + + + +bool DriveChunkPort::can_append(DriveBitPort const &bit) const +{ + return bit.cell == cell && bit.port == port && bit.offset == offset + width; +} + +bool DriveChunkPort::try_append(DriveBitPort const &bit) +{ + if (!can_append(bit)) + return false; + width += 1; + return true; +} + +bool DriveChunkPort::try_append(DriveChunkPort const &chunk) +{ + if (chunk.cell != cell || chunk.port != port || chunk.offset != offset + width) + return false; + width += chunk.width; + return true; +} + +DriveChunkPort::DriveChunkPort(Cell *cell, IdString port, int offset, int width) + : cell(cell), port(port), offset(offset), width(width) {} + +DriveChunkPort::DriveChunkPort(Cell *cell, IdString port) + : cell(cell), port(port), offset(0), width(GetSize(cell->connections().at(port))) {} + +DriveChunkPort::DriveChunkPort(Cell *cell, std::pair const &conn) + : cell(cell), port(conn.first), offset(0), width(GetSize(conn.second)) {} + +DriveChunkPort::DriveChunkPort(DriveBitPort const &bit) + : cell(bit.cell), port(bit.port), offset(bit.offset), width(1) {} + +int DriveChunkPort::size() const { return width; } + +DriveBitPort DriveChunkPort::operator[](int i) const +{ + log_assert(i >= 0 && i < width); + return DriveBitPort(cell, port, offset + i); +} + +bool DriveChunkPort::is_whole() const +{ + return offset == 0 && width == cell->connections().at(port).size(); +} + +bool DriveChunkPort::operator==(const DriveChunkPort &other) const +{ + return cell == other.cell && port == other.port && offset == other.offset && width == other.width; +} + +bool DriveChunkPort::operator<(const DriveChunkPort &other) const +{ + if (cell != other.cell) + return cell->name < other.cell->name; + if (port != other.port) + return port < other.port; + if (width != other.width) + return width < other.width; + return offset < other.offset; +} + +unsigned int DriveChunkPort::hash() const +{ + return mkhash_add(mkhash(mkhash(cell->name.hash(), port.hash()), width), offset); +} + +bool DriveChunkMarker::can_append(DriveBitMarker const &bit) const +{ + return bit.marker == marker && bit.offset == offset + width; +} + +bool DriveChunkMarker::try_append(DriveBitMarker const &bit) +{ + if (!can_append(bit)) + return false; + width += 1; + return true; +} + +bool DriveChunkMarker::try_append(DriveChunkMarker const &chunk) +{ + if (chunk.marker != marker || chunk.offset != offset + width) + return false; + width += chunk.width; + return true; +} + +DriveChunkMarker::DriveChunkMarker(int marker, int offset, int width) + : marker(marker), offset(offset), width(width) {} + +DriveChunkMarker::DriveChunkMarker(DriveBitMarker const &bit) + : marker(bit.marker), offset(bit.offset), width(1) {} + +int DriveChunkMarker::size() const { return width; } + +DriveBitMarker DriveChunkMarker::operator[](int i) const +{ + log_assert(i >= 0 && i < width); + return DriveBitMarker(marker, offset + i); +} + +bool DriveChunkMarker::operator==(const DriveChunkMarker &other) const +{ + return marker == other.marker && offset == other.offset && width == other.width; +} + +bool DriveChunkMarker::operator<(const DriveChunkMarker &other) const +{ + if (marker != other.marker) + return marker < other.marker; + if (width != other.width) + return width < other.width; + return offset < other.offset; +} + +unsigned int DriveChunkMarker::hash() const +{ + return mkhash_add(mkhash(marker, width), offset); +} + +bool DriveChunkMultiple::can_append(DriveBitMultiple const &bit) const +{ + if (bit.multiple().size() != multiple_.size()) + return false; + + int const_drivers = 0; + for (DriveChunk const &single : multiple_) + if (single.is_constant()) + const_drivers += 1; + + if (const_drivers > 1) + return false; + + for (DriveBit const &single : bit.multiple()) + if (single.is_constant()) + const_drivers -= 1; + + if (const_drivers != 0) + return false; + + for (DriveChunk const &single : multiple_) + { + switch (single.type()) + { + case DriveType::CONSTANT: { + } break; + case DriveType::WIRE: { + auto const &wire = single.wire(); + DriveBit next = DriveBitWire(wire.wire, wire.offset + wire.width); + if (!bit.multiple().count(next)) + return false; + } break; + case DriveType::PORT: { + auto const &port = single.port(); + DriveBit next = DriveBitPort(port.cell, port.port, port.offset + port.width); + if (!bit.multiple().count(next)) + return false; + } break; + case DriveType::MARKER: { + auto const &marker = single.marker(); + DriveBit next = DriveBitMarker(marker.marker, marker.offset + marker.width); + if (!bit.multiple().count(next)) + return false; + } break; + default: + return false; + } + } + + return true; +} + +bool DriveChunkMultiple::can_append(DriveChunkMultiple const &chunk) const +{ + if (chunk.multiple().size() != multiple_.size()) + return false; + + int const_drivers = 0; + for (DriveChunk const &single : multiple_) + if (single.is_constant()) + const_drivers += 1; + + if (const_drivers > 1) + return false; + + for (DriveChunk const &single : chunk.multiple()) + if (single.is_constant()) + const_drivers -= 1; + + if (const_drivers != 0) + return false; + + for (DriveChunk const &single : multiple_) + { + switch (single.type()) + { + case DriveType::CONSTANT: { + } break; + case DriveType::WIRE: { + auto const &wire = single.wire(); + DriveChunk next = DriveChunkWire(wire.wire, wire.offset + wire.width, chunk.size()); + if (!chunk.multiple().count(next)) + return false; + } break; + case DriveType::PORT: { + auto const &port = single.port(); + DriveChunk next = DriveChunkPort(port.cell, port.port, port.offset + port.width, chunk.size()); + if (!chunk.multiple().count(next)) + return false; + } break; + case DriveType::MARKER: { + auto const &marker = single.marker(); + DriveChunk next = DriveChunkMarker(marker.marker, marker.offset + marker.width, chunk.size()); + if (!chunk.multiple().count(next)) + return false; + } break; + default: + return false; + } + } + + return true; } -void DriveBit::merge(DriveBit const &other) +bool DriveChunkMultiple::try_append(DriveBitMultiple const &bit) { - if (other.type_ == DriveType::NONE) - return; - if (type_ == DriveType::NONE) { - *this = other; - return; + if (!can_append(bit)) + return false; + width_ += 1; + State constant; + + for (DriveBit const &single : bit.multiple()) + if (single.is_constant()) + constant = single.constant(); + + for (DriveChunk &single : multiple_) + { + switch (single.type()) + { + case DriveType::CONSTANT: { + single.constant().bits.push_back(constant); + } break; + case DriveType::WIRE: { + single.wire().width += 1; + } break; + case DriveType::PORT: { + single.port().width += 1; + } break; + case DriveType::MARKER: { + single.marker().width += 1; + } break; + default: + log_abort(); } - if (type_ != DriveType::MULTIPLE) { - DriveBitMultiple multi(std::move(*this)); - *this = std::move(multi); + } + return true; +} + +bool DriveChunkMultiple::try_append(DriveChunkMultiple const &chunk) +{ + if (!can_append(chunk)) + return false; + int width = chunk.size(); + width_ += width; + Const constant; + + for (DriveChunk const &single : chunk.multiple()) + if (single.is_constant()) + constant = single.constant(); + + for (DriveChunk &single : multiple_) + { + switch (single.type()) + { + case DriveType::CONSTANT: { + auto &bits = single.constant().bits; + bits.insert(bits.end(), constant.bits.begin(), constant.bits.end()); + } break; + case DriveType::WIRE: { + single.wire().width += width; + } break; + case DriveType::PORT: { + single.port().width += width; + } break; + case DriveType::MARKER: { + single.marker().width += width; + } break; + default: + log_abort(); } - multiple().merge(other); + } + return true; } +DriveChunkMultiple::DriveChunkMultiple(DriveBitMultiple const &bit) + : width_(1) +{ + for (auto const &bit : bit.multiple()) + multiple_.emplace(bit); +} -void DriveBitMultiple::merge(DriveBit const &single) +pool const &DriveChunkMultiple::multiple() const { - if (single.type() == DriveType::NONE) - return; - if (single.type() == DriveType::MULTIPLE) { - merge(single.multiple()); - return; - } - multiple_.emplace(single); + return multiple_; } -void DriveBitMultiple::merge(DriveBit &&single) +int DriveChunkMultiple::size() const { return width_; } + + +bool DriveChunkMultiple::operator==(const DriveChunkMultiple &other) const { - if (single.type() == DriveType::NONE) - return; - if (single.type() == DriveType::MULTIPLE) { - merge(std::move(single.multiple())); - return; - } - multiple_.emplace(std::move(single)); + return width_ == other.width_ && multiple_ == other.multiple_; } -DriveBitMultiple DriveChunkMultiple::operator[](int i) const +bool DriveChunkMultiple::operator<(const DriveChunkMultiple &other) const { - DriveBitMultiple result; - for (auto const &single : multiple_) - result.merge(single[i]); - return result; + if (multiple_.size() < other.multiple_.size()) + multiple_.sort(); + return false; // TODO: implement, canonicalize order } +unsigned int DriveChunkMultiple::hash() const +{ + return mkhash(width_, multiple_.hash()); +} -bool DriveChunkWire::can_append(DriveBitWire const &bit) const +bool DriveChunk::can_append(DriveBit const &bit) const { - return bit.wire == wire && bit.offset == offset + width; + if (size() == 0) + return true; + if (bit.type() != type_) + return false; + switch (type_) + { + case DriveType::NONE: + return true; + case DriveType::CONSTANT: + return true; + case DriveType::WIRE: + return wire_.can_append(bit.wire()); + case DriveType::PORT: + return port_.can_append(bit.port()); + case DriveType::MULTIPLE: + return multiple_.can_append(bit.multiple()); + default: + log_abort(); + } } -bool DriveChunkWire::try_append(DriveBitWire const &bit) +bool DriveChunk::try_append(DriveBit const &bit) { - if (!can_append(bit)) - return false; - width += 1; - return true; + if (size() == 0) + *this = bit; + if (bit.type() != type_) + return false; + switch (type_) + { + case DriveType::NONE: + none_ += 1; + return true; + case DriveType::CONSTANT: + constant_.bits.push_back(bit.constant()); + return true; + case DriveType::WIRE: + return wire_.try_append(bit.wire()); + case DriveType::PORT: + return port_.try_append(bit.port()); + case DriveType::MULTIPLE: + return multiple_.try_append(bit.multiple()); + default: + log_abort(); + } } -bool DriveChunkWire::try_append(DriveChunkWire const &chunk) + +bool DriveChunk::try_append(DriveChunk const &chunk) { - if (chunk.wire != wire || chunk.offset != offset + width) - return false; - width += chunk.width; - return true; + if (size() == 0) + *this = chunk; + if (chunk.type_ != type_) + return false; + switch (type_) + { + case DriveType::NONE: + none_ += chunk.none_; + return true; + case DriveType::CONSTANT: + constant_.bits.insert(constant_.bits.end(), chunk.constant_.bits.begin(), chunk.constant_.bits.end()); + return true; + case DriveType::WIRE: + return wire_.try_append(chunk.wire()); + case DriveType::PORT: + return port_.try_append(chunk.port()); + case DriveType::MARKER: + return marker_.try_append(chunk.marker()); + case DriveType::MULTIPLE: + return multiple_.try_append(chunk.multiple()); + } + log_abort(); } -bool DriveChunkPort::can_append(DriveBitPort const &bit) const +DriveChunk::DriveChunk() { set_none(); } + +DriveChunk::DriveChunk(DriveChunk const &other) { *this = other; } + +DriveChunk::DriveChunk(DriveChunk &&other) { *this = std::move(other); } + +DriveChunk::DriveChunk(DriveBit const &other) { *this = other; } + +DriveChunk::DriveChunk(Const const &constant) { *this = constant; } + +DriveChunk::DriveChunk(Const &&constant) { *this = std::move(constant); } + +DriveChunk::DriveChunk(DriveChunkWire const &wire) { *this = wire; } + +DriveChunk::DriveChunk(DriveChunkWire &&wire) { *this = std::move(wire); } + +DriveChunk::DriveChunk(DriveChunkPort const &port) { *this = port; } + +DriveChunk::DriveChunk(DriveChunkPort &&port) { *this = std::move(port); } + +DriveChunk::DriveChunk(DriveChunkMarker const &marker) { *this = marker; } + +DriveChunk::DriveChunk(DriveChunkMarker &&marker) { *this = std::move(marker); } + +DriveChunk::DriveChunk(DriveChunkMultiple const &multiple) { *this = multiple; } + +DriveChunk::DriveChunk(DriveChunkMultiple &&multiple) { *this = std::move(multiple); } + +DriveChunk::~DriveChunk() { set_none(); } + +DriveBit DriveChunk::operator[](int i) const { - return bit.cell == cell && bit.port == port && bit.offset == offset + width; + switch (type_) + { + case DriveType::NONE: + return DriveBit(); + case DriveType::CONSTANT: + return constant_[i]; + case DriveType::WIRE: + return wire_[i]; + case DriveType::PORT: + return port_[i]; + case DriveType::MARKER: + return marker_[i]; + case DriveType::MULTIPLE: + return multiple_[i]; + } + log_abort(); } -bool DriveChunkPort::try_append(DriveBitPort const &bit) +void DriveChunk::set_none(int width) { - if (!can_append(bit)) - return false; - width += 1; - return true; + switch (type_) + { + case DriveType::NONE: + none_ = width; + break; + case DriveType::CONSTANT: + constant_.~Const(); + break; + case DriveType::WIRE: + wire_.~DriveChunkWire(); + break; + case DriveType::PORT: + port_.~DriveChunkPort(); + break; + case DriveType::MARKER: + marker_.~DriveChunkMarker(); + break; + case DriveType::MULTIPLE: + multiple_.~DriveChunkMultiple(); + break; + } + type_ = DriveType::NONE; + none_ = width; } -bool DriveChunkPort::try_append(DriveChunkPort const &chunk) +DriveChunk &DriveChunk::operator=(DriveChunk const &other) { - if (chunk.cell != cell || chunk.port != port || chunk.offset != offset + width) - return false; - width += chunk.width; - return true; + switch (other.type_) + { + case DriveType::NONE: + set_none(other.none_); + break; + case DriveType::CONSTANT: + *this = other.constant_; + break; + case DriveType::WIRE: + *this = other.wire_; + break; + case DriveType::PORT: + *this = other.port_; + break; + case DriveType::MARKER: + *this = other.marker_; + break; + case DriveType::MULTIPLE: + *this = other.multiple_; + break; + } + return *this; } -bool DriveChunkMarker::can_append(DriveBitMarker const &bit) const +DriveChunk &DriveChunk::operator=(DriveChunk &&other) { - return bit.marker == marker && bit.offset == offset + width; + switch (other.type_) + { + case DriveType::NONE: + set_none(other.none_); + break; + case DriveType::CONSTANT: + *this = std::move(other.constant_); + break; + case DriveType::WIRE: + *this = std::move(other.wire_); + break; + case DriveType::PORT: + *this = std::move(other.port_); + break; + case DriveType::MARKER: + *this = std::move(other.marker_); + break; + case DriveType::MULTIPLE: + *this = std::move(other.multiple_); + break; + } + return *this; } -bool DriveChunkMarker::try_append(DriveBitMarker const &bit) +DriveChunk &DriveChunk::operator=(Const const &constant) { - if (!can_append(bit)) - return false; - width += 1; - return true; + set_none(); + new (&constant_) Const(constant); + type_ = DriveType::CONSTANT; + return *this; } -bool DriveChunkMarker::try_append(DriveChunkMarker const &chunk) +DriveChunk &DriveChunk::operator=(Const &&constant) { - if (chunk.marker != marker || chunk.offset != offset + width) - return false; - width += chunk.width; - return true; + set_none(); + new (&constant_) Const(std::move(constant)); + type_ = DriveType::CONSTANT; + return *this; } +DriveChunk &DriveChunk::operator=(DriveChunkWire const &wire) +{ + set_none(); + new (&wire_) DriveChunkWire(wire); + type_ = DriveType::WIRE; + return *this; +} -bool DriveChunkMultiple::can_append(DriveBitMultiple const &bit) const +DriveChunk &DriveChunk::operator=(DriveChunkWire &&wire) +{ + set_none(); + new (&wire_) DriveChunkWire(std::move(wire)); + type_ = DriveType::WIRE; + return *this; +} + +DriveChunk &DriveChunk::operator=(DriveChunkPort const &port) +{ + set_none(); + new (&port_) DriveChunkPort(port); + type_ = DriveType::PORT; + return *this; +} + +DriveChunk &DriveChunk::operator=(DriveChunkPort &&port) +{ + set_none(); + new (&port_) DriveChunkPort(std::move(port)); + type_ = DriveType::PORT; + return *this; +} + +DriveChunk &DriveChunk::operator=(DriveChunkMarker const &marker) { - if (bit.multiple().size() != multiple_.size()) - return false; + set_none(); + new (&marker_) DriveChunkMarker(marker); + type_ = DriveType::MARKER; + return *this; +} - int const_drivers = 0; - for (DriveChunk const &single : multiple_) - if (single.is_constant()) - const_drivers += 1; +DriveChunk &DriveChunk::operator=(DriveChunkMarker &&marker) +{ + set_none(); + new (&marker_) DriveChunkMarker(std::move(marker)); + type_ = DriveType::MARKER; + return *this; +} - if (const_drivers > 1) - return false; +DriveChunk &DriveChunk::operator=(DriveChunkMultiple const &multiple) +{ + set_none(multiple.size()); + if (multiple.multiple().empty()) + return *this; + new (&multiple_) DriveChunkMultiple(multiple); + type_ = DriveType::MULTIPLE; + return *this; +} - for (DriveBit const &single : bit.multiple()) - if (single.is_constant()) - const_drivers -= 1; +DriveChunk &DriveChunk::operator=(DriveChunkMultiple &&multiple) +{ + set_none(multiple.size()); + if (multiple.multiple().empty()) + return *this; + new (&multiple_) DriveChunkMultiple(std::move(multiple)); + type_ = DriveType::MULTIPLE; + return *this; +} - if (const_drivers != 0) - return false; +DriveChunk &DriveChunk::operator=(DriveBit const &other) +{ + switch (other.type()) + { + case DriveType::NONE: + set_none(1); + break; + case DriveType::CONSTANT: + *this = Const(other.constant()); + break; + case DriveType::WIRE: + *this = DriveChunkWire(other.wire()); + break; + case DriveType::PORT: + *this = DriveChunkPort(other.port()); + break; + case DriveType::MARKER: + *this = DriveChunkMarker(other.marker()); + break; + case DriveType::MULTIPLE: + *this = DriveChunkMultiple(other.multiple()); + break; + } + return *this; +} - for (DriveChunk const &single : multiple_) - { - switch (single.type()) - { - case DriveType::CONSTANT: { - } break; - case DriveType::WIRE: { - auto const &wire = single.wire(); - DriveBit next = DriveBitWire(wire.wire, wire.offset + wire.width); - if (!bit.multiple().count(next)) - return false; - } break; - case DriveType::PORT: { - auto const &port = single.port(); - DriveBit next = DriveBitPort(port.cell, port.port, port.offset + port.width); - if (!bit.multiple().count(next)) - return false; - } break; - case DriveType::MARKER: { - auto const &marker = single.marker(); - DriveBit next = DriveBitMarker(marker.marker, marker.offset + marker.width); - if (!bit.multiple().count(next)) - return false; - } break; - default: - return false; - } - } +unsigned int DriveChunk::hash() const +{ + unsigned int inner; + switch (type_) + { + case DriveType::NONE: + inner = 0; + break; + case DriveType::CONSTANT: + inner = constant_.hash(); + break; + case DriveType::WIRE: + inner = wire_.hash(); + break; + case DriveType::PORT: + inner = port_.hash(); + break; + case DriveType::MARKER: + inner = marker_.hash(); + break; + case DriveType::MULTIPLE: + inner = multiple_.hash(); + break; + } + return mkhash((unsigned int)type_, inner); +} - return true; +bool DriveChunk::operator==(const DriveChunk &other) const +{ + if (type_ != other.type_) + return false; + + switch (type_) + { + case DriveType::NONE: + return true; + case DriveType::CONSTANT: + return constant_ == other.constant_; + case DriveType::WIRE: + return wire_ == other.wire_; + case DriveType::PORT: + return port_ == other.port_; + case DriveType::MARKER: + return marker_ == other.marker_; + case DriveType::MULTIPLE: + return multiple_ == other.multiple_; + } + log_assert(false); } -bool DriveChunkMultiple::can_append(DriveChunkMultiple const &chunk) const +bool DriveChunk::operator!=(const DriveChunk &other) const +{ + return !(*this == other); +} + +bool DriveChunk::operator<(const DriveChunk &other) const { - if (chunk.multiple().size() != multiple_.size()) - return false; + if (type_ != other.type_) + return type_ < other.type_; + switch (type_) + { + case DriveType::NONE: + return false; + case DriveType::CONSTANT: + return constant_ < other.constant_; + case DriveType::WIRE: + return wire_ < other.wire_; + case DriveType::PORT: + return port_ < other.port_; + case DriveType::MARKER: + return marker_ < other.marker_; + case DriveType::MULTIPLE: + return multiple_ < other.multiple_; + } + log_assert(false); +} - int const_drivers = 0; - for (DriveChunk const &single : multiple_) - if (single.is_constant()) - const_drivers += 1; +DriveType DriveChunk::type() const { return type_; } - if (const_drivers > 1) - return false; +bool DriveChunk::is_none() const { return type_ == DriveType::NONE; } - for (DriveChunk const &single : chunk.multiple()) - if (single.is_constant()) - const_drivers -= 1; +bool DriveChunk::is_constant() const { return type_ == DriveType::CONSTANT; } - if (const_drivers != 0) - return false; +bool DriveChunk::is_wire() const { return type_ == DriveType::WIRE; } - for (DriveChunk const &single : multiple_) - { - switch (single.type()) - { - case DriveType::CONSTANT: { - } break; - case DriveType::WIRE: { - auto const &wire = single.wire(); - DriveChunk next = DriveChunkWire(wire.wire, wire.offset + wire.width, chunk.size()); - if (!chunk.multiple().count(next)) - return false; - } break; - case DriveType::PORT: { - auto const &port = single.port(); - DriveChunk next = DriveChunkPort(port.cell, port.port, port.offset + port.width, chunk.size()); - if (!chunk.multiple().count(next)) - return false; - } break; - case DriveType::MARKER: { - auto const &marker = single.marker(); - DriveChunk next = DriveChunkMarker(marker.marker, marker.offset + marker.width, chunk.size()); - if (!chunk.multiple().count(next)) - return false; - } break; - default: - return false; - } - } +bool DriveChunk::is_port() const { return type_ == DriveType::PORT; } + +bool DriveChunk::is_marker() const { return type_ == DriveType::MARKER; } - return true; +bool DriveChunk::is_multiple() const { return type_ == DriveType::MULTIPLE; } + +Const &DriveChunk::constant() +{ + log_assert(is_constant()); + return constant_; } -bool DriveChunkMultiple::try_append(DriveBitMultiple const &bit) +Const const &DriveChunk::constant() const { - if (!can_append(bit)) - return false; - width_ += 1; - State constant; + log_assert(is_constant()); + return constant_; +} - for (DriveBit const &single : bit.multiple()) - if (single.is_constant()) - constant = single.constant(); +DriveChunkWire &DriveChunk::wire() +{ + log_assert(is_wire()); + return wire_; +} - for (DriveChunk &single : multiple_) - { - switch (single.type()) - { - case DriveType::CONSTANT: { - single.constant().bits.push_back(constant); - } break; - case DriveType::WIRE: { - single.wire().width += 1; - } break; - case DriveType::PORT: { - single.port().width += 1; - } break; - case DriveType::MARKER: { - single.marker().width += 1; - } break; - default: - log_abort(); - } - } - return true; +DriveChunkWire const &DriveChunk::wire() const +{ + log_assert(is_wire()); + return wire_; } -bool DriveChunkMultiple::try_append(DriveChunkMultiple const &chunk) +DriveChunkPort &DriveChunk::port() { - if (!can_append(chunk)) - return false; - int width = chunk.size(); - width_ += width; - Const constant; + log_assert(is_port()); + return port_; +} - for (DriveChunk const &single : chunk.multiple()) - if (single.is_constant()) - constant = single.constant(); +DriveChunkPort const &DriveChunk::port() const +{ + log_assert(is_port()); + return port_; +} - for (DriveChunk &single : multiple_) - { - switch (single.type()) - { - case DriveType::CONSTANT: { - auto &bits = single.constant().bits; - bits.insert(bits.end(), constant.bits.begin(), constant.bits.end()); - } break; - case DriveType::WIRE: { - single.wire().width += width; - } break; - case DriveType::PORT: { - single.port().width += width; - } break; - case DriveType::MARKER: { - single.marker().width += width; - } break; - default: - log_abort(); - } - } - return true; +DriveChunkMarker &DriveChunk::marker() +{ + log_assert(is_marker()); + return marker_; } -bool DriveChunk::can_append(DriveBit const &bit) const +DriveChunkMarker const &DriveChunk::marker() const { - if (size() == 0) - return true; - if (bit.type() != type_) - return false; - switch (type_) - { - case DriveType::NONE: - return true; - case DriveType::CONSTANT: - return true; - case DriveType::WIRE: - return wire_.can_append(bit.wire()); - case DriveType::PORT: - return port_.can_append(bit.port()); - case DriveType::MULTIPLE: - return multiple_.can_append(bit.multiple()); - default: - log_abort(); - } + log_assert(is_marker()); + return marker_; } -bool DriveChunk::try_append(DriveBit const &bit) +DriveChunkMultiple &DriveChunk::multiple() { - if (size() == 0) - *this = bit; - if (bit.type() != type_) - return false; - switch (type_) - { - case DriveType::NONE: - none_ += 1; - return true; - case DriveType::CONSTANT: - constant_.bits.push_back(bit.constant()); - return true; - case DriveType::WIRE: - return wire_.try_append(bit.wire()); - case DriveType::PORT: - return port_.try_append(bit.port()); - case DriveType::MULTIPLE: - return multiple_.try_append(bit.multiple()); - default: - log_abort(); - } + log_assert(is_multiple()); + return multiple_; } +DriveChunkMultiple const &DriveChunk::multiple() const +{ + log_assert(is_multiple()); + return multiple_; +} -bool DriveChunk::try_append(DriveChunk const &chunk) +int DriveChunk::size() const { - if (size() == 0) - *this = chunk; - if (chunk.type_ != type_) - return false; - switch (type_) - { - case DriveType::NONE: - none_ += chunk.none_; - return true; - case DriveType::CONSTANT: - constant_.bits.insert(constant_.bits.end(), chunk.constant_.bits.begin(), chunk.constant_.bits.end()); - return true; - case DriveType::WIRE: - return wire_.try_append(chunk.wire()); - case DriveType::PORT: - return port_.try_append(chunk.port()); - case DriveType::MARKER: - return marker_.try_append(chunk.marker()); - case DriveType::MULTIPLE: - return multiple_.try_append(chunk.multiple()); - } - log_abort(); + switch (type_) + { + case DriveType::NONE: + return none_; + case DriveType::CONSTANT: + return constant_.size(); + case DriveType::WIRE: + return wire_.size(); + case DriveType::PORT: + return port_.size(); + case DriveType::MARKER: + return marker_.size(); + case DriveType::MULTIPLE: + return multiple_.size(); + default: + log_assert(false && "unsupported type"); + } } void DriveSpec::append(DriveBit const &bit) { - hash_ = 0; - if (!packed()) { - bits_.push_back(bit); - width_ += 1; - return; - } - - if (chunks_.empty() || !chunks_.back().try_append(bit)) - chunks_.emplace_back(bit); - width_ += 1; + hash_ = 0; + if (!packed()) { + bits_.push_back(bit); + width_ += 1; + return; + } + + if (chunks_.empty() || !chunks_.back().try_append(bit)) + chunks_.emplace_back(bit); + width_ += 1; } void DriveSpec::append(DriveChunk const &chunk) { - hash_ = 0; - pack(); - if (chunks_.empty() || !chunks_.back().try_append(chunk)) - chunks_.emplace_back(chunk); - width_ += chunk.size(); + hash_ = 0; + pack(); + if (chunks_.empty() || !chunks_.back().try_append(chunk)) + chunks_.emplace_back(chunk); + width_ += chunk.size(); } void DriveSpec::pack() const { - if (bits_.empty()) - return; - std::vector bits(std::move(bits_)); - for (auto &bit : bits) - if (chunks_.empty() || !chunks_.back().try_append(bit)) - chunks_.emplace_back(std::move(bit)); + if (bits_.empty()) + return; + std::vector bits(std::move(bits_)); + for (auto &bit : bits) + if (chunks_.empty() || !chunks_.back().try_append(bit)) + chunks_.emplace_back(std::move(bit)); } void DriveSpec::unpack() const { - if (chunks_.empty()) - return; - for (auto &chunk : chunks_) + if (chunks_.empty()) + return; + for (auto &chunk : chunks_) + { + for (int i = 0, width = chunk.size(); i != width; ++i) { - for (int i = 0, width = chunk.size(); i != width; ++i) - { - bits_.emplace_back(chunk[i]); - } + bits_.emplace_back(chunk[i]); } - chunks_.clear(); + } + chunks_.clear(); } void DriveSpec::compute_width() { - width_ = 0; - for (auto const &chunk : chunks_) - width_ += chunk.size(); + width_ = 0; + for (auto const &chunk : chunks_) + width_ += chunk.size(); } -void DriverMap::DriveBitGraph::add_edge(DriveBitId src, DriveBitId dst) + +inline bool DriveSpec::packed() const { - if (first_edges.emplace(src, dst).first->second == dst) - return; - if (second_edges.emplace(src, dst).first->second == dst) - return; - more_edges[src].emplace(dst); + return bits_.empty(); } -DriverMap::DriveBitId DriverMap::DriveBitGraph::pop_edge(DriveBitId src) +DriveSpec::DriveSpec() {} + +DriveSpec::DriveSpec(DriveChunk const &chunk) { - // TODO unused I think? - auto found_more = more_edges.find(src); - if (found_more != more_edges.end()) { - auto result = found_more->second.pop(); - if (found_more->second.empty()) - more_edges.erase(found_more); - return result; - } + *this = chunk; +} - auto found_second = second_edges.find(src); - if (found_second != second_edges.end()) { - auto result = found_second->second; - second_edges.erase(found_second); - return result; - } +DriveSpec::DriveSpec(DriveChunkWire const &chunk) +{ + *this = chunk; +} - auto found_first = first_edges.find(src); - if (found_first != first_edges.end()) { - auto result = found_first->second; - first_edges.erase(found_first); - return result; - } +DriveSpec::DriveSpec(DriveChunkPort const &chunk) +{ + *this = chunk; +} + +DriveSpec::DriveSpec(DriveChunkMarker const &chunk) +{ + *this = chunk; +} + +DriveSpec::DriveSpec(DriveChunkMultiple const &chunk) +{ + *this = chunk; +} + +DriveSpec::DriveSpec(DriveBit const &bit) +{ + *this = bit; +} + +DriveSpec::DriveSpec(DriveBitWire const &bit) +{ + *this = bit; +} + +DriveSpec::DriveSpec(DriveBitPort const &bit) +{ + *this = bit; +} + +DriveSpec::DriveSpec(DriveBitMarker const &bit) +{ + *this = bit; +} + +DriveSpec::DriveSpec(DriveBitMultiple const &bit) +{ + *this = bit; +} + +DriveSpec::DriveSpec(std::vector const &chunks) : chunks_(chunks) +{ + compute_width(); +} + +DriveSpec::DriveSpec(std::vector const &bits) +{ + for (auto const &bit : bits) + append(bit); +} + +std::vector const &DriveSpec::chunks() const +{ + pack(); + return chunks_; +} + +std::vector const &DriveSpec::bits() const +{ + unpack(); + return bits_; +} + +int DriveSpec::size() const +{ + return width_; +} + +DriveBit &DriveSpec::operator[](int index) +{ + log_assert(index >= 0 && index < size()); + unpack(); + return bits_[index]; +} + +const DriveBit &DriveSpec::operator[](int index) const +{ + log_assert(index >= 0 && index < size()); + unpack(); + return bits_[index]; +} + +void DriveSpec::clear() +{ + chunks_.clear(); + bits_.clear(); + width_ = 0; +} + +DriveSpec &DriveSpec::operator=(DriveChunk const &chunk) +{ + chunks_.clear(); + bits_.clear(); + append(chunk); + return *this; +} + +DriveSpec &DriveSpec::operator=(DriveChunkWire const &chunk) +{ + return *this = DriveChunk(chunk); +} + +DriveSpec &DriveSpec::operator=(DriveChunkPort const &chunk) +{ + return *this = DriveChunk(chunk); +} + +DriveSpec &DriveSpec::operator=(DriveChunkMarker const &chunk) +{ + return *this = DriveChunk(chunk); +} + +DriveSpec &DriveSpec::operator=(DriveChunkMultiple const &chunk) +{ + return *this = DriveChunk(chunk); +} + +DriveSpec &DriveSpec::operator=(DriveBit const &bit) +{ + chunks_.clear(); + bits_.clear(); + append(bit); + return *this; +} + +DriveSpec &DriveSpec::operator=(DriveBitWire const &bit) +{ + return *this = DriveBit(bit); +} + +DriveSpec &DriveSpec::operator=(DriveBitPort const &bit) +{ + return *this = DriveBit(bit); +} + +DriveSpec &DriveSpec::operator=(DriveBitMarker const &bit) +{ + return *this = DriveBit(bit); +} + +DriveSpec &DriveSpec::operator=(DriveBitMultiple const &bit) +{ + return *this = DriveBit(bit); +} + +unsigned int DriveSpec::hash() const +{ + if (hash_ != 0) + return hash_; + + pack(); + hash_ = hash_ops>().hash(chunks_); + hash_ |= (hash_ == 0); + return hash_; +} + +bool DriveSpec::operator==(DriveSpec const &other) const +{ + if (size() != other.size() || hash() != other.hash()) + return false; + return chunks() == other.chunks(); +} + +void DriverMap::DriveBitGraph::add_edge(DriveBitId src, DriveBitId dst) +{ + if (first_edges.emplace(src, dst).first->second == dst) + return; + if (second_edges.emplace(src, dst).first->second == dst) + return; + more_edges[src].emplace(dst); +} - return DriveBitId(); +DriverMap::DriveBitId DriverMap::DriveBitGraph::pop_edge(DriveBitId src) +{ + // TODO unused I think? + auto found_more = more_edges.find(src); + if (found_more != more_edges.end()) { + auto result = found_more->second.pop(); + if (found_more->second.empty()) + more_edges.erase(found_more); + return result; + } + + auto found_second = second_edges.find(src); + if (found_second != second_edges.end()) { + auto result = found_second->second; + second_edges.erase(found_second); + return result; + } + + auto found_first = first_edges.find(src); + if (found_first != first_edges.end()) { + auto result = found_first->second; + first_edges.erase(found_first); + return result; + } + + return DriveBitId(); } void DriverMap::DriveBitGraph::clear(DriveBitId src) { - first_edges.erase(src); - second_edges.erase(src); - more_edges.erase(src); + first_edges.erase(src); + second_edges.erase(src); + more_edges.erase(src); } bool DriverMap::DriveBitGraph::contains(DriveBitId src) { - return first_edges.count(src); + return first_edges.count(src); } int DriverMap::DriveBitGraph::count(DriveBitId src) { - if (!first_edges.count(src)) - return 0; - if (!second_edges.count(src)) - return 1; - auto found = more_edges.find(src); - if (found == more_edges.end()) - return 2; - return GetSize(found->second) + 2; + if (!first_edges.count(src)) + return 0; + if (!second_edges.count(src)) + return 1; + auto found = more_edges.find(src); + if (found == more_edges.end()) + return 2; + return GetSize(found->second) + 2; } DriverMap::DriveBitId DriverMap::DriveBitGraph::at(DriveBitId src, int index) { - if (index == 0) - return first_edges.at(src); - else if (index == 1) - return second_edges.at(src); - else - return *more_edges.at(src).element(index - 2); + if (index == 0) + return first_edges.at(src); + else if (index == 1) + return second_edges.at(src); + else + return *more_edges.at(src).element(index - 2); } DriverMap::BitMode DriverMap::bit_mode(DriveBit const &bit) { - switch (bit.type()) - { - case DriveType::NONE: - return BitMode::NONE; - case DriveType::CONSTANT: - // TODO how to handle Sx here? - return bit.constant() == State::Sz ? BitMode::NONE : BitMode::DRIVER; - case DriveType::WIRE: { - auto const &wire = bit.wire(); - bool driver = wire.wire->port_input; - bool driven = wire.wire->port_output; - - if (driver && !driven) - return BitMode::DRIVER; - else if (driven && !driver) - return BitMode::DRIVEN; - else if (driver && driven) - return BitMode::TRISTATE; - else - return keep_wire(bit.wire().wire) ? BitMode::KEEP : BitMode::NONE; - } - case DriveType::PORT: { - auto const &port = bit.port(); - bool driver = celltypes.cell_output(port.cell->type, port.port); - bool driven = celltypes.cell_input(port.cell->type, port.port); - if (driver && !driven) - return BitMode::DRIVER; - else if (driven && !driver) - return BitMode::DRIVEN_UNIQUE; - else - return BitMode::TRISTATE; - } - case DriveType::MARKER: { - // TODO user supplied classification - log_abort(); - } - default: - log_abort(); - } + switch (bit.type()) + { + case DriveType::NONE: + return BitMode::NONE; + case DriveType::CONSTANT: + // TODO how to handle Sx here? + return bit.constant() == State::Sz ? BitMode::NONE : BitMode::DRIVER; + case DriveType::WIRE: { + auto const &wire = bit.wire(); + bool driver = wire.wire->port_input; + bool driven = wire.wire->port_output; + + if (driver && !driven) + return BitMode::DRIVER; + else if (driven && !driver) + return BitMode::DRIVEN; + else if (driver && driven) + return BitMode::TRISTATE; + else + return keep_wire(bit.wire().wire) ? BitMode::KEEP : BitMode::NONE; + } + case DriveType::PORT: { + auto const &port = bit.port(); + bool driver = celltypes.cell_output(port.cell->type, port.port); + bool driven = celltypes.cell_input(port.cell->type, port.port); + if (driver && !driven) + return BitMode::DRIVER; + else if (driven && !driver) + return BitMode::DRIVEN_UNIQUE; + else + return BitMode::TRISTATE; + } + case DriveType::MARKER: { + // TODO user supplied classification + log_abort(); + } + default: + log_abort(); + } } DriverMap::DriveBitId DriverMap::id_from_drive_bit(DriveBit const &bit) { - switch (bit.type()) - { - case DriveType::NONE: - return -1; - case DriveType::CONSTANT: - return (int)bit.constant(); - case DriveType::WIRE: { - auto const &wire_bit = bit.wire(); - int offset = next_offset; - auto insertion = wire_offsets.emplace(wire_bit.wire, offset); - if (insertion.second) { - if (wire_bit.wire->width == 1) { - log_assert(wire_bit.offset == 0); - isolated_drive_bits.emplace(offset, bit); - } else - drive_bits.emplace(offset, DriveBitWire(wire_bit.wire, 0)); - next_offset += wire_bit.wire->width; - } - return insertion.first->second.id + wire_bit.offset; - } - case DriveType::PORT: { - auto const &port_bit = bit.port(); - auto key = std::make_pair(port_bit.cell, port_bit.port); - int offset = next_offset; - auto insertion = port_offsets.emplace(key, offset); - if (insertion.second) { - int width = port_bit.cell->connections().at(port_bit.port).size(); - if (width == 1 && offset == 0) { - log_assert(port_bit.offset == 0); - isolated_drive_bits.emplace(offset, bit); - } else - drive_bits.emplace(offset, DriveBitPort(port_bit.cell, port_bit.port, 0)); - next_offset += width; - } - return insertion.first->second.id + port_bit.offset; - } - default: - log_assert(false && "unsupported DriveType in DriverMap"); - } - log_abort(); + switch (bit.type()) + { + case DriveType::NONE: + return -1; + case DriveType::CONSTANT: + return (int)bit.constant(); + case DriveType::WIRE: { + auto const &wire_bit = bit.wire(); + int offset = next_offset; + auto insertion = wire_offsets.emplace(wire_bit.wire, offset); + if (insertion.second) { + if (wire_bit.wire->width == 1) { + log_assert(wire_bit.offset == 0); + isolated_drive_bits.emplace(offset, bit); + } else + drive_bits.emplace(offset, DriveBitWire(wire_bit.wire, 0)); + next_offset += wire_bit.wire->width; + } + return insertion.first->second.id + wire_bit.offset; + } + case DriveType::PORT: { + auto const &port_bit = bit.port(); + auto key = std::make_pair(port_bit.cell, port_bit.port); + int offset = next_offset; + auto insertion = port_offsets.emplace(key, offset); + if (insertion.second) { + int width = port_bit.cell->connections().at(port_bit.port).size(); + if (width == 1 && offset == 0) { + log_assert(port_bit.offset == 0); + isolated_drive_bits.emplace(offset, bit); + } else + drive_bits.emplace(offset, DriveBitPort(port_bit.cell, port_bit.port, 0)); + next_offset += width; + } + return insertion.first->second.id + port_bit.offset; + } + default: + log_assert(false && "unsupported DriveType in DriverMap"); + } + log_abort(); } DriveBit DriverMap::drive_bit_from_id(DriveBitId id) { - auto found_isolated = isolated_drive_bits.find(id); - if (found_isolated != isolated_drive_bits.end()) - return found_isolated->second; - - auto found = drive_bits.upper_bound(id); - if (found == drive_bits.begin()) { - return id < 0 ? DriveBit() : DriveBit((State) id.id); - } - --found; - DriveBit result = found->second; - if (result.is_wire()) { - result.wire().offset += id.id - found->first.id; - } else { - log_assert(result.is_port()); - result.port().offset += id.id - found->first.id; - } - return result; + auto found_isolated = isolated_drive_bits.find(id); + if (found_isolated != isolated_drive_bits.end()) + return found_isolated->second; + + auto found = drive_bits.upper_bound(id); + if (found == drive_bits.begin()) { + return id < 0 ? DriveBit() : DriveBit((State) id.id); + } + --found; + DriveBit result = found->second; + if (result.is_wire()) { + result.wire().offset += id.id - found->first.id; + } else { + log_assert(result.is_port()); + result.port().offset += id.id - found->first.id; + } + return result; } void DriverMap::connect_directed_merge(DriveBitId driven_id, DriveBitId driver_id) { - if (driven_id == driver_id) - return; + if (driven_id == driver_id) + return; - same_driver.merge(driven_id, driver_id); + same_driver.merge(driven_id, driver_id); - for (int i = 0, end = connected_drivers.count(driven_id); i != end; ++i) - connected_drivers.add_edge(driver_id, connected_drivers.at(driven_id, i)); + for (int i = 0, end = connected_drivers.count(driven_id); i != end; ++i) + connected_drivers.add_edge(driver_id, connected_drivers.at(driven_id, i)); - connected_drivers.clear(driven_id); + connected_drivers.clear(driven_id); - for (int i = 0, end = connected_undirected.count(driven_id); i != end; ++i) - connected_undirected.add_edge(driver_id, connected_undirected.at(driven_id, i)); + for (int i = 0, end = connected_undirected.count(driven_id); i != end; ++i) + connected_undirected.add_edge(driver_id, connected_undirected.at(driven_id, i)); - connected_undirected.clear(driven_id); + connected_undirected.clear(driven_id); } void DriverMap::connect_directed_buffer(DriveBitId driven_id, DriveBitId driver_id) { - connected_drivers.add_edge(driven_id, driver_id); + connected_drivers.add_edge(driven_id, driver_id); } void DriverMap::connect_undirected(DriveBitId a_id, DriveBitId b_id) { - connected_undirected.add_edge(a_id, b_id); - connected_undirected.add_edge(b_id, a_id); + connected_undirected.add_edge(a_id, b_id); + connected_undirected.add_edge(b_id, a_id); } void DriverMap::add(Module *module) { - for (auto const &conn : module->connections()) - add(conn.first, conn.second); + for (auto const &conn : module->connections()) + add(conn.first, conn.second); - for (auto cell : module->cells()) - for (auto const &conn : cell->connections()) - add_port(cell, conn.first, conn.second); + for (auto cell : module->cells()) + for (auto const &conn : cell->connections()) + add_port(cell, conn.first, conn.second); } // Add a single bit connection to the driver map. void DriverMap::add(DriveBit const &a, DriveBit const &b) { - DriveBitId a_id = id_from_drive_bit(a); - DriveBitId b_id = id_from_drive_bit(b); - - DriveBitId orig_a_id = a_id; - DriveBitId orig_b_id = b_id; - - a_id = same_driver.find(a_id); - b_id = same_driver.find(b_id); - - if (a_id == b_id) - return; - - BitMode a_mode = bit_mode(orig_a_id == a_id ? a : drive_bit_from_id(a_id)); - BitMode b_mode = bit_mode(orig_b_id == b_id ? b : drive_bit_from_id(b_id)); - - // If either bit is just a wire that we don't need to keep, merge and - // use the other end as representative bit. - if (a_mode == BitMode::NONE && !(b_mode == BitMode::DRIVEN_UNIQUE || b_mode == BitMode::DRIVEN)) - connect_directed_merge(a_id, b_id); - else if (b_mode == BitMode::NONE && !(a_mode == BitMode::DRIVEN_UNIQUE || a_mode == BitMode::DRIVEN)) - connect_directed_merge(b_id, a_id); - // If either bit requires a driven value and has a unique driver, merge - // and use the other end as representative bit. - else if (a_mode == BitMode::DRIVEN_UNIQUE && !(b_mode == BitMode::DRIVEN_UNIQUE || b_mode == BitMode::DRIVEN)) - connect_directed_buffer(a_id, b_id); - else if (b_mode == BitMode::DRIVEN_UNIQUE && !(a_mode == BitMode::DRIVEN_UNIQUE || a_mode == BitMode::DRIVEN)) - connect_directed_buffer(b_id, a_id); - // If either bit only drives a value, store a directed connection from - // it to the other bit. - else if (a_mode == BitMode::DRIVER) - connect_directed_buffer(b_id, a_id); - else if (b_mode == BitMode::DRIVER) - connect_directed_buffer(a_id, b_id); - // Otherwise we store an undirected connection which we will resolve - // during querying. - else - connect_undirected(a_id, b_id); - - return; + DriveBitId a_id = id_from_drive_bit(a); + DriveBitId b_id = id_from_drive_bit(b); + + DriveBitId orig_a_id = a_id; + DriveBitId orig_b_id = b_id; + + a_id = same_driver.find(a_id); + b_id = same_driver.find(b_id); + + if (a_id == b_id) + return; + + BitMode a_mode = bit_mode(orig_a_id == a_id ? a : drive_bit_from_id(a_id)); + BitMode b_mode = bit_mode(orig_b_id == b_id ? b : drive_bit_from_id(b_id)); + + // If either bit is just a wire that we don't need to keep, merge and + // use the other end as representative bit. + if (a_mode == BitMode::NONE && !(b_mode == BitMode::DRIVEN_UNIQUE || b_mode == BitMode::DRIVEN)) + connect_directed_merge(a_id, b_id); + else if (b_mode == BitMode::NONE && !(a_mode == BitMode::DRIVEN_UNIQUE || a_mode == BitMode::DRIVEN)) + connect_directed_merge(b_id, a_id); + // If either bit requires a driven value and has a unique driver, merge + // and use the other end as representative bit. + else if (a_mode == BitMode::DRIVEN_UNIQUE && !(b_mode == BitMode::DRIVEN_UNIQUE || b_mode == BitMode::DRIVEN)) + connect_directed_buffer(a_id, b_id); + else if (b_mode == BitMode::DRIVEN_UNIQUE && !(a_mode == BitMode::DRIVEN_UNIQUE || a_mode == BitMode::DRIVEN)) + connect_directed_buffer(b_id, a_id); + // If either bit only drives a value, store a directed connection from + // it to the other bit. + else if (a_mode == BitMode::DRIVER) + connect_directed_buffer(b_id, a_id); + else if (b_mode == BitMode::DRIVER) + connect_directed_buffer(a_id, b_id); + // Otherwise we store an undirected connection which we will resolve + // during querying. + else + connect_undirected(a_id, b_id); + + return; } // Specialized version that avoids unpacking void DriverMap::add(SigSpec const &a, SigSpec const &b) { - log_assert(a.size() == b.size()); - auto const &a_chunks = a.chunks(); - auto const &b_chunks = b.chunks(); - - auto a_chunk = a_chunks.begin(); - auto a_end = a_chunks.end(); - int a_offset = 0; - - auto b_chunk = b_chunks.begin(); - int b_offset = 0; - - SigChunk tmp_a, tmp_b; - while (a_chunk != a_end) { - int a_width = a_chunk->width - a_offset; - if (a_width == 0) { - a_offset = 0; - ++a_chunk; - continue; - } - int b_width = b_chunk->width - b_offset; - if (b_width == 0) { - b_offset = 0; - ++b_chunk; - continue; - } - int width = std::min(a_width, b_width); - log_assert(width > 0); - - SigChunk const &a_subchunk = - a_offset == 0 && a_width == width ? *a_chunk : a_chunk->extract(a_offset, width); - SigChunk const &b_subchunk = - b_offset == 0 && b_width == width ? *b_chunk : b_chunk->extract(b_offset, width); - - add(a_subchunk, b_subchunk); - - a_offset += width; - b_offset += width; - } + log_assert(a.size() == b.size()); + auto const &a_chunks = a.chunks(); + auto const &b_chunks = b.chunks(); + + auto a_chunk = a_chunks.begin(); + auto a_end = a_chunks.end(); + int a_offset = 0; + + auto b_chunk = b_chunks.begin(); + int b_offset = 0; + + SigChunk tmp_a, tmp_b; + while (a_chunk != a_end) { + int a_width = a_chunk->width - a_offset; + if (a_width == 0) { + a_offset = 0; + ++a_chunk; + continue; + } + int b_width = b_chunk->width - b_offset; + if (b_width == 0) { + b_offset = 0; + ++b_chunk; + continue; + } + int width = std::min(a_width, b_width); + log_assert(width > 0); + + SigChunk const &a_subchunk = + a_offset == 0 && a_width == width ? *a_chunk : a_chunk->extract(a_offset, width); + SigChunk const &b_subchunk = + b_offset == 0 && b_width == width ? *b_chunk : b_chunk->extract(b_offset, width); + + add(a_subchunk, b_subchunk); + + a_offset += width; + b_offset += width; + } } void DriverMap::add_port(Cell *cell, IdString const &port, SigSpec const &b) { - int offset = 0; - for (auto const &chunk : b.chunks()) { - add(chunk, DriveChunkPort(cell, port, offset, chunk.width)); - offset += chunk.size(); - } + int offset = 0; + for (auto const &chunk : b.chunks()) { + add(chunk, DriveChunkPort(cell, port, offset, chunk.width)); + offset += chunk.size(); + } } void DriverMap::orient_undirected(DriveBitId id) { - pool &seen = orient_undirected_seen; - pool &drivers = orient_undirected_drivers; - dict &distance = orient_undirected_distance; - seen.clear(); - drivers.clear(); + pool &seen = orient_undirected_seen; + pool &drivers = orient_undirected_drivers; + dict &distance = orient_undirected_distance; + seen.clear(); + drivers.clear(); - seen.emplace(id); + seen.emplace(id); - for (int pos = 0; pos < GetSize(seen); ++pos) { - DriveBitId current = *seen.element(seen.size() - 1 - pos); - DriveBit bit = drive_bit_from_id(current); + for (int pos = 0; pos < GetSize(seen); ++pos) { + DriveBitId current = *seen.element(seen.size() - 1 - pos); + DriveBit bit = drive_bit_from_id(current); - BitMode mode = bit_mode(bit); + BitMode mode = bit_mode(bit); - if (mode == BitMode::DRIVER || mode == BitMode::TRISTATE) - drivers.emplace(current); + if (mode == BitMode::DRIVER || mode == BitMode::TRISTATE) + drivers.emplace(current); - if (connected_drivers.contains(current)) - drivers.emplace(current); + if (connected_drivers.contains(current)) + drivers.emplace(current); - int undirected_driver_count = connected_undirected.count(current); + int undirected_driver_count = connected_undirected.count(current); - for (int i = 0; i != undirected_driver_count; ++i) - seen.emplace(same_driver.find(connected_undirected.at(current, i))); - } + for (int i = 0; i != undirected_driver_count; ++i) + seen.emplace(same_driver.find(connected_undirected.at(current, i))); + } - if (drivers.empty()) - for (auto seen_id : seen) - drivers.emplace(seen_id); + if (drivers.empty()) + for (auto seen_id : seen) + drivers.emplace(seen_id); - for (auto driver : drivers) - { - distance.clear(); - distance.emplace(driver, 0); - - for (int pos = 0; pos < GetSize(distance); ++pos) { - auto current_it = distance.element(distance.size() - 1 - pos); - - DriveBitId current = current_it->first; - int undirected_driver_count = connected_undirected.count(current); - - for (int i = 0; i != undirected_driver_count; ++i) - { - DriveBitId next = same_driver.find(connected_undirected.at(current, i)); - auto emplaced = distance.emplace(next, current_it->second + 1); - if (emplaced.first->second == current_it->second + 1) - connected_oriented.add_edge(next, current); - } - } - } + for (auto driver : drivers) + { + distance.clear(); + distance.emplace(driver, 0); + + for (int pos = 0; pos < GetSize(distance); ++pos) { + auto current_it = distance.element(distance.size() - 1 - pos); - for (auto seen_id : seen) - oriented_present.emplace(seen_id); + DriveBitId current = current_it->first; + int undirected_driver_count = connected_undirected.count(current); + + for (int i = 0; i != undirected_driver_count; ++i) + { + DriveBitId next = same_driver.find(connected_undirected.at(current, i)); + auto emplaced = distance.emplace(next, current_it->second + 1); + if (emplaced.first->second == current_it->second + 1) + connected_oriented.add_edge(next, current); + } + } + } + + for (auto seen_id : seen) + oriented_present.emplace(seen_id); } DriveBit DriverMap::operator()(DriveBit const &bit) { - if (bit.type() == DriveType::MARKER || bit.type() == DriveType::NONE) - return bit; - if (bit.type() == DriveType::MULTIPLE) - { - DriveBit result; - for (auto const &inner : bit.multiple().multiple()) - result.merge((*this)(inner)); - return result; - } + if (bit.type() == DriveType::MARKER || bit.type() == DriveType::NONE) + return bit; + if (bit.type() == DriveType::MULTIPLE) + { + DriveBit result; + for (auto const &inner : bit.multiple().multiple()) + result.merge((*this)(inner)); + return result; + } - DriveBitId bit_id = id_from_drive_bit(bit); + DriveBitId bit_id = id_from_drive_bit(bit); - DriveBitId bit_repr_id = same_driver.find(bit_id); + DriveBitId bit_repr_id = same_driver.find(bit_id); - DriveBit bit_repr = drive_bit_from_id(bit_repr_id); + DriveBit bit_repr = drive_bit_from_id(bit_repr_id); - BitMode mode = bit_mode(bit_repr); + BitMode mode = bit_mode(bit_repr); - if (mode == BitMode::KEEP && bit_repr_id != bit_id) - return bit_repr; + if (mode == BitMode::KEEP && bit_repr_id != bit_id) + return bit_repr; - int implicit_driver_count = connected_drivers.count(bit_repr_id); - if (connected_undirected.contains(bit_repr_id) && !oriented_present.count(bit_repr_id)) - orient_undirected(bit_repr_id); + int implicit_driver_count = connected_drivers.count(bit_repr_id); + if (connected_undirected.contains(bit_repr_id) && !oriented_present.count(bit_repr_id)) + orient_undirected(bit_repr_id); - DriveBit driver; + DriveBit driver; - if (mode == BitMode::DRIVER || mode == BitMode::TRISTATE) - driver = bit_repr; + if (mode == BitMode::DRIVER || mode == BitMode::TRISTATE) + driver = bit_repr; - for (int i = 0; i != implicit_driver_count; ++i) - driver.merge(drive_bit_from_id(connected_drivers.at(bit_repr_id, i))); + for (int i = 0; i != implicit_driver_count; ++i) + driver.merge(drive_bit_from_id(connected_drivers.at(bit_repr_id, i))); - int oriented_driver_count = connected_oriented.count(bit_repr_id); - for (int i = 0; i != oriented_driver_count; ++i) - driver.merge(drive_bit_from_id(connected_oriented.at(bit_repr_id, i))); + int oriented_driver_count = connected_oriented.count(bit_repr_id); + for (int i = 0; i != oriented_driver_count; ++i) + driver.merge(drive_bit_from_id(connected_oriented.at(bit_repr_id, i))); - return driver; + return driver; } DriveSpec DriverMap::operator()(DriveSpec spec) { - DriveSpec result; + DriveSpec result; - for (int i = 0, width = spec.size(); i != width; ++i) - result.append((*this)(spec[i])); + for (int i = 0, width = spec.size(); i != width; ++i) + result.append((*this)(spec[i])); - return result; + return result; } const char *log_signal(DriveChunkWire const &chunk) { - const char *id = log_id(chunk.wire->name); - if (chunk.is_whole()) - return id; - if (chunk.width == 1) - return log_str(stringf("%s [%d]", id, chunk.offset)); - return log_str(stringf("%s [%d:%d]", id, chunk.offset + chunk.width - 1, chunk.offset)); + const char *id = log_id(chunk.wire->name); + if (chunk.is_whole()) + return id; + if (chunk.width == 1) + return log_str(stringf("%s [%d]", id, chunk.offset)); + return log_str(stringf("%s [%d:%d]", id, chunk.offset + chunk.width - 1, chunk.offset)); } const char *log_signal(DriveChunkPort const &chunk) { - const char *cell_id = log_id(chunk.cell->name); - const char *port_id = log_id(chunk.port); - if (chunk.is_whole()) - return log_str(stringf("%s <%s>", cell_id, port_id)); - if (chunk.width == 1) - return log_str(stringf("%s <%s> [%d]", cell_id, port_id, chunk.offset)); - return log_str(stringf("%s <%s> [%d:%d]", cell_id, port_id, chunk.offset + chunk.width - 1, chunk.offset)); + const char *cell_id = log_id(chunk.cell->name); + const char *port_id = log_id(chunk.port); + if (chunk.is_whole()) + return log_str(stringf("%s <%s>", cell_id, port_id)); + if (chunk.width == 1) + return log_str(stringf("%s <%s> [%d]", cell_id, port_id, chunk.offset)); + return log_str(stringf("%s <%s> [%d:%d]", cell_id, port_id, chunk.offset + chunk.width - 1, chunk.offset)); } const char *log_signal(DriveChunkMarker const &chunk) { - if (chunk.width == 1) - return log_str(stringf(" [%d]", chunk.marker, chunk.offset)); - return log_str(stringf(" [%d:%d]", chunk.marker, chunk.offset + chunk.width - 1, chunk.offset)); + if (chunk.width == 1) + return log_str(stringf(" [%d]", chunk.marker, chunk.offset)); + return log_str(stringf(" [%d:%d]", chunk.marker, chunk.offset + chunk.width - 1, chunk.offset)); } const char *log_signal(DriveChunk const &chunk) { - switch (chunk.type()) - { - case DriveType::NONE: - return log_str(stringf("", chunk.size())); - case DriveType::CONSTANT: - return log_const(chunk.constant()); - case DriveType::WIRE: - return log_signal(chunk.wire()); - case DriveType::PORT: - return log_signal(chunk.port()); - case DriveType::MARKER: - return log_signal(chunk.marker()); - case DriveType::MULTIPLE: { - std::string str = "", chunk.size())); + case DriveType::CONSTANT: + return log_const(chunk.constant()); + case DriveType::WIRE: + return log_signal(chunk.wire()); + case DriveType::PORT: + return log_signal(chunk.port()); + case DriveType::MARKER: + return log_signal(chunk.marker()); + case DriveType::MULTIPLE: { + std::string str = "(State::Sm)) +{ + celltypes.setup(); +} - for (auto i = chunks.rbegin(), end = chunks.rend(); i != end; ++i) - { - str += sep; - sep = " "; - str += log_signal(*i); - } - str += " }"; +DriverMap::DriverMap(Design *design) : next_offset(1 + static_cast(State::Sm)) +{ + celltypes.setup(); + celltypes.setup_design(design); +} + +DriverMap::DriveBitId::DriveBitId() : id(-1) {} + +DriverMap::DriveBitId::DriveBitId(int id) : id(id) {} + +bool DriverMap::DriveBitId::operator==(const DriveBitId &other) const +{ + return id == other.id; +} + +bool DriverMap::DriveBitId::operator!=(const DriveBitId &other) const +{ + return id != other.id; +} + +bool DriverMap::DriveBitId::operator<(const DriveBitId &other) const +{ + return id < other.id; +} - return log_str(str); +unsigned int DriverMap::DriveBitId::hash() const +{ + return id; +} + +bool DriverMap::keep_wire(Wire *wire) { + // TODO configurable + return wire->has_attribute(ID(keep)); } + YOSYS_NAMESPACE_END diff --git a/kernel/drivertools.h b/kernel/drivertools.h index 1cb835df2cc..cd0ac5399bd 100644 --- a/kernel/drivertools.h +++ b/kernel/drivertools.h @@ -28,8 +28,6 @@ YOSYS_NAMESPACE_BEGIN -// TODO move implementation into a .cc file - struct DriveBit; struct DriveChunkWire; @@ -46,1271 +44,532 @@ const char *log_signal(DriveChunk const &chunk); const char *log_signal(DriveSpec const &chunk); enum class DriveType : unsigned char -{ - NONE, - CONSTANT, - WIRE, - PORT, - MULTIPLE, - MARKER, -}; + { + NONE, + CONSTANT, + WIRE, + PORT, + MULTIPLE, + MARKER, + }; struct DriveBitWire { - Wire *wire; - int offset; - - DriveBitWire(Wire *wire, int offset) : wire(wire), offset(offset) {} - - bool operator==(const DriveBitWire &other) const - { - return wire == other.wire && offset == other.offset; - } - - bool operator<(const DriveBitWire &other) const - { - if (wire != other.wire) - return wire->name < other.wire->name; - return offset < other.offset; - } - - unsigned int hash() const - { - return mkhash_add(wire->name.hash(), offset); - } - - operator SigBit() const - { - return SigBit(wire, offset); - } + Wire *wire; + int offset; + + DriveBitWire(Wire *wire, int offset); + + bool operator==(const DriveBitWire &other) const; + + bool operator<(const DriveBitWire &other) const; + + unsigned int hash() const; + + operator SigBit() const; }; struct DriveBitPort { - Cell *cell; - IdString port; - int offset; - - DriveBitPort(Cell *cell, IdString port, int offset) : cell(cell), port(port), offset(offset) {} - - bool operator==(const DriveBitPort &other) const - { - return cell == other.cell && port == other.port && offset == other.offset; - } - - bool operator<(const DriveBitPort &other) const - { - if (cell != other.cell) - return cell->name < other.cell->name; - if (port != other.port) - return port < other.port; - return offset < other.offset; - } - - unsigned int hash() const - { - return mkhash_add(mkhash(cell->name.hash(), port.hash()), offset); - } -}; + Cell *cell; + IdString port; + int offset; + + DriveBitPort(Cell *cell, IdString port, int offset); + + bool operator==(const DriveBitPort &other) const; + + bool operator<(const DriveBitPort &other) const; + unsigned int hash() const; +}; struct DriveBitMarker { - int marker; - int offset; - - DriveBitMarker(int marker, int offset) : marker(marker), offset(offset) {} + int marker; + int offset; - bool operator==(const DriveBitMarker &other) const - { - return marker == other.marker && offset == other.offset; - } + DriveBitMarker(int marker, int offset); - bool operator<(const DriveBitMarker &other) const - { - if (marker != other.marker) - return marker < other.marker; - return offset < other.offset; - } + bool operator==(const DriveBitMarker &other) const; - unsigned int hash() const - { - return mkhash_add(marker, offset); - } + bool operator<(const DriveBitMarker &other) const; + unsigned int hash() const; }; struct DriveBitMultiple { private: - pool multiple_; + pool multiple_; public: - DriveBitMultiple() {} - DriveBitMultiple(DriveBit const &single) - { - multiple_.emplace(single); - } - - pool const &multiple() const { return multiple_; } - - void merge(DriveBitMultiple const &other) - { - for (DriveBit const &single : other.multiple_) - merge(single); - } - - void merge(DriveBitMultiple &&other) - { - for (DriveBit &single : other.multiple_) - merge(std::move(single)); - } - - void merge(DriveBit const &single); - void merge(DriveBit &&single); - - bool operator==(const DriveBitMultiple &other) const - { - return multiple_ == other.multiple_; - } - - unsigned int hash() const - { - return multiple_.hash(); - } + DriveBitMultiple(); + DriveBitMultiple(DriveBit const &single); + + pool const &multiple() const; + + void merge(DriveBitMultiple const &other); + void merge(DriveBitMultiple &&other); + void merge(DriveBit const &single); + void merge(DriveBit &&single); + + bool operator==(const DriveBitMultiple &other) const; + + unsigned int hash() const; }; struct DriveBit { private: - DriveType type_ = DriveType::NONE; - union - { - State constant_; - DriveBitWire wire_; - DriveBitPort port_; - DriveBitMarker marker_; - DriveBitMultiple multiple_; - }; -public: - DriveBit() {} - - DriveBit(SigBit const &bit); - - DriveBit(DriveBit const &other) { *this = other; } - DriveBit(DriveBit &&other) { *this = other; } - - - DriveBit(State constant) { *this = constant; } - DriveBit(DriveBitWire const &wire) { *this = wire; } - DriveBit(DriveBitWire &&wire) { *this = wire; } - DriveBit(DriveBitPort const &port) { *this = port; } - DriveBit(DriveBitPort &&port) { *this = port; } - DriveBit(DriveBitMarker const &marker) { *this = marker; } - DriveBit(DriveBitMarker &&marker) { *this = marker; } - DriveBit(DriveBitMultiple const &multiple) { *this = multiple; } - DriveBit(DriveBitMultiple &&multiple) { *this = multiple; } - - ~DriveBit() { set_none(); } - - void set_none() - { - switch (type_) - { - case DriveType::NONE: - break; - case DriveType::CONSTANT: - break; - case DriveType::WIRE: - wire_.~DriveBitWire(); - break; - case DriveType::PORT: - port_.~DriveBitPort(); - break; - case DriveType::MARKER: - marker_.~DriveBitMarker(); - break; - case DriveType::MULTIPLE: - multiple_.~DriveBitMultiple(); - break; - } - type_ = DriveType::NONE; - } - - DriveBit &operator=(DriveBit const &other) - { - switch (other.type_) - { - case DriveType::NONE: - set_none(); - break; - case DriveType::CONSTANT: - *this = other.constant_; - break; - case DriveType::WIRE: - *this = other.wire_; - break; - case DriveType::PORT: - *this = other.port_; - break; - case DriveType::MARKER: - *this = other.marker_; - break; - case DriveType::MULTIPLE: - *this = other.multiple_; - break; - } - return *this; - } - - DriveBit &operator=(DriveBit &&other) - { - switch (other.type_) - { - case DriveType::NONE: - set_none(); - break; - case DriveType::CONSTANT: - *this = std::move(other.constant_); - break; - case DriveType::WIRE: - *this = std::move(other.wire_); - break; - case DriveType::PORT: - *this = std::move(other.port_); - break; - case DriveType::MARKER: - *this = std::move(other.marker_); - break; - case DriveType::MULTIPLE: - *this = std::move(other.multiple_); - break; - } - return *this; - } - - DriveBit &operator=(State constant) - { - set_none(); - constant_ = constant; - type_ = DriveType::CONSTANT; - return *this; - } - - DriveBit &operator=(DriveBitWire const &wire) - { - set_none(); - new (&wire_) DriveBitWire(wire); - type_ = DriveType::WIRE; - return *this; - } - - DriveBit &operator=(DriveBitWire &&wire) - { - set_none(); - new (&wire_) DriveBitWire(wire); - type_ = DriveType::WIRE; - return *this; - } - - DriveBit &operator=(DriveBitPort const &port) - { - set_none(); - new (&port_) DriveBitPort(port); - type_ = DriveType::PORT; - return *this; - } - - DriveBit &operator=(DriveBitPort &&port) - { - set_none(); - new (&port_) DriveBitPort(port); - type_ = DriveType::PORT; - return *this; - } - - DriveBit &operator=(DriveBitMarker const &marker) - { - set_none(); - new (&marker_) DriveBitMarker(marker); - type_ = DriveType::MARKER; - return *this; - } - - DriveBit &operator=(DriveBitMarker &&marker) - { - set_none(); - new (&marker_) DriveBitMarker(marker); - type_ = DriveType::MARKER; - return *this; - } - - DriveBit &operator=(DriveBitMultiple const &multiple) - { - set_none(); - if (multiple.multiple().empty()) - return *this; - new (&multiple_) DriveBitMultiple(multiple); - type_ = DriveType::MULTIPLE; - return *this; - } - - DriveBit &operator=(DriveBitMultiple &&multiple) - { - set_none(); - if (multiple.multiple().empty()) - return *this; - new (&multiple_) DriveBitMultiple(multiple); - type_ = DriveType::MULTIPLE; - return *this; - } - - unsigned int hash() const - { - unsigned int inner; - switch (type_) - { - case DriveType::NONE: - inner = 0; - break; - case DriveType::CONSTANT: - inner = constant_; - break; - case DriveType::WIRE: - inner = wire_.hash(); - break; - case DriveType::PORT: - inner = port_.hash(); - break; - case DriveType::MARKER: - inner = marker_.hash(); - break; - case DriveType::MULTIPLE: - inner = multiple_.hash(); - break; - } - return mkhash((unsigned int)type_, inner); - } - - bool operator==(const DriveBit &other) const - { - if (type_ != other.type_) - return false; - - switch (type_) - { - case DriveType::NONE: - return true; - case DriveType::CONSTANT: - return constant_ == other.constant_; - case DriveType::WIRE: - return wire_ == other.wire_; - case DriveType::PORT: - return port_ == other.port_; - case DriveType::MARKER: - return marker_ == other.marker_; - case DriveType::MULTIPLE: - return multiple_ == other.multiple_; - } - log_assert(false); - } - - bool operator!=(const DriveBit &other) const - { - return !(*this == other); - } - - bool operator<(const DriveBit &other) const - { - if (type_ != other.type_) - return type_ < other.type_; - switch (type_) - { - case DriveType::NONE: - return false; - case DriveType::CONSTANT: - return constant_ < other.constant_; - case DriveType::WIRE: - return wire_ < other.wire_; - case DriveType::PORT: - return port_ < other.port_; - case DriveType::MARKER: - return marker_ < other.marker_; - case DriveType::MULTIPLE: - log_assert(!"TODO"); - } - log_abort(); - } - - - DriveType type() const { return type_; } - - bool is_none() const { return type_ == DriveType::NONE; } - bool is_constant() const { return type_ == DriveType::CONSTANT; } - bool is_wire() const { return type_ == DriveType::WIRE; } - bool is_port() const { return type_ == DriveType::PORT; } - bool is_marker() const { return type_ == DriveType::MARKER; } - bool is_multiple() const { return type_ == DriveType::MULTIPLE; } - - State &constant() { log_assert(is_constant()); return constant_; } - State const &constant() const { log_assert(is_constant()); return constant_; } - DriveBitWire &wire() { log_assert(is_wire()); return wire_; } - DriveBitWire const &wire() const { log_assert(is_wire()); return wire_; } - DriveBitPort &port() { log_assert(is_port()); return port_; } - DriveBitPort const &port() const { log_assert(is_port()); return port_; } - DriveBitMarker &marker() { log_assert(is_marker()); return marker_; } - DriveBitMarker const &marker() const { log_assert(is_marker()); return marker_; } - DriveBitMultiple &multiple() { log_assert(is_multiple()); return multiple_; } - DriveBitMultiple const &multiple() const { log_assert(is_multiple()); return multiple_; } - - void merge(DriveBit const &other); + DriveType type_ = DriveType::NONE; + union + { + State constant_; + DriveBitWire wire_; + DriveBitPort port_; + DriveBitMarker marker_; + DriveBitMultiple multiple_; + }; +public: + DriveBit(); + + DriveBit(SigBit const &bit); + + DriveBit(DriveBit const &other); + DriveBit(DriveBit &&other); + + DriveBit(State constant); + DriveBit(DriveBitWire const &wire); + DriveBit(DriveBitWire &&wire); + DriveBit(DriveBitPort const &port); + DriveBit(DriveBitPort &&port); + DriveBit(DriveBitMarker const &marker); + DriveBit(DriveBitMarker &&marker); + DriveBit(DriveBitMultiple const &multiple); + DriveBit(DriveBitMultiple &&multiple); + + ~DriveBit(); + + void set_none(); + + DriveBit &operator=(DriveBit const &other); + DriveBit &operator=(DriveBit &&other); + + DriveBit &operator=(State constant); + DriveBit &operator=(DriveBitWire const &wire); + DriveBit &operator=(DriveBitWire &&wire); + DriveBit &operator=(DriveBitPort const &port); + DriveBit &operator=(DriveBitPort &&port); + DriveBit &operator=(DriveBitMarker const &marker); + DriveBit &operator=(DriveBitMarker &&marker); + DriveBit &operator=(DriveBitMultiple const &multiple); + DriveBit &operator=(DriveBitMultiple &&multiple); + + unsigned int hash() const; + + bool operator==(const DriveBit &other) const; + bool operator!=(const DriveBit &other) const; + + bool operator<(const DriveBit &other) const; + + DriveType type() const; + + bool is_none() const; + bool is_constant() const; + bool is_wire() const; + bool is_port() const; + bool is_marker() const; + bool is_multiple() const; + + State &constant(); + State const &constant() const; + DriveBitWire &wire(); + DriveBitWire const &wire() const; + DriveBitPort &port(); + DriveBitPort const &port() const; + DriveBitMarker &marker(); + DriveBitMarker const &marker() const; + DriveBitMultiple &multiple(); + DriveBitMultiple const &multiple() const; + + void merge(DriveBit const &other); }; - struct DriveChunkWire { - Wire *wire; - int offset; - int width; - - DriveChunkWire(Wire *wire, int offset, int width) : wire(wire), offset(offset), width(width) {} - DriveChunkWire(DriveBitWire const &bit) : wire(bit.wire), offset(bit.offset), width(1) {} - - int size() const { return width; } - - DriveBitWire operator[](int i) const - { - log_assert(i >= 0 && i < width); - return DriveBitWire(wire, offset + i); - } - - bool can_append(DriveBitWire const &bit) const; - bool try_append(DriveBitWire const &bit); - bool try_append(DriveChunkWire const &chunk); - - // Whether this chunk is a whole wire - bool is_whole() const { return offset == 0 && width == wire->width; } - - bool operator==(const DriveChunkWire &other) const - { - return wire == other.wire && offset == other.offset && width == other.width; - } - - bool operator<(const DriveChunkWire &other) const - { - if (wire != other.wire) - return wire->name < other.wire->name; - if (width != other.width) - return width < other.width; - return offset < other.offset; - } - - unsigned int hash() const - { - return mkhash_add(mkhash(wire->name.hash(), width), offset); - } - - explicit operator SigChunk() const - { - return SigChunk(wire, offset, width); - } + Wire *wire; + int offset; + int width; + + DriveChunkWire(Wire *wire, int offset, int width); + DriveChunkWire(DriveBitWire const &bit); + + int size() const; + DriveBitWire operator[](int i) const; + bool can_append(DriveBitWire const &bit) const; + bool try_append(DriveBitWire const &bit); + bool try_append(DriveChunkWire const &chunk); + bool is_whole() const; + bool operator==(const DriveChunkWire &other) const; + bool operator<(const DriveChunkWire &other) const; + unsigned int hash() const; + explicit operator SigChunk() const; }; struct DriveChunkPort { - Cell *cell; - IdString port; - int offset; - int width; - - DriveChunkPort(Cell *cell, IdString port, int offset, int width) : - cell(cell), port(port), offset(offset), width(width) { } - DriveChunkPort(Cell *cell, IdString port) : - cell(cell), port(port), offset(0), width(GetSize(cell->connections().at(port))) { } - DriveChunkPort(Cell *cell, std::pair const &conn) : - cell(cell), port(conn.first), offset(0), width(GetSize(conn.second)) { } - DriveChunkPort(DriveBitPort const &bit) : - cell(bit.cell), port(bit.port), offset(bit.offset), width(1) { } - - int size() const { return width; } - - DriveBitPort operator[](int i) const - { - log_assert(i >= 0 && i < width); - return DriveBitPort(cell, port, offset + i); - } - - bool can_append(DriveBitPort const &bit) const; - bool try_append(DriveBitPort const &bit); - bool try_append(DriveChunkPort const &chunk); - - // Whether this chunk is a whole port - bool is_whole() const - { - return offset == 0 && width == cell->connections().at(port).size(); - } - - bool operator==(const DriveChunkPort &other) const - { - return cell == other.cell && port == other.port && offset == other.offset && width == other.width; - } - - bool operator<(const DriveChunkPort &other) const - { - if (cell != other.cell) - return cell->name < other.cell->name; - if (port != other.port) - return port < other.port; - if (width != other.width) - return width < other.width; - return offset < other.offset; - } - - unsigned int hash() const - { - return mkhash_add(mkhash(mkhash(cell->name.hash(), port.hash()), width), offset); - } + Cell *cell; + IdString port; + int offset; + int width; + + DriveChunkPort(Cell *cell, IdString port, int offset, int width); + DriveChunkPort(Cell *cell, IdString port); + DriveChunkPort(Cell *cell, std::pair const &conn); + DriveChunkPort(DriveBitPort const &bit); + + int size() const; + DriveBitPort operator[](int i) const; + bool can_append(DriveBitPort const &bit) const; + bool try_append(DriveBitPort const &bit); + bool try_append(DriveChunkPort const &chunk); + bool is_whole() const; + bool operator==(const DriveChunkPort &other) const; + bool operator<(const DriveChunkPort &other) const; + unsigned int hash() const; }; - struct DriveChunkMarker { - int marker; - int offset; - int width; - - DriveChunkMarker(int marker, int offset, int width) : - marker(marker), offset(offset), width(width) {} - DriveChunkMarker(DriveBitMarker const &bit) : - marker(bit.marker), offset(bit.offset), width(1) {} - - int size() const { return width; } - - DriveBitMarker operator[](int i) const - { - log_assert(i >= 0 && i < width); - return DriveBitMarker(marker, offset + i); - } - - bool can_append(DriveBitMarker const &bit) const; - bool try_append(DriveBitMarker const &bit); - bool try_append(DriveChunkMarker const &chunk); - - bool operator==(const DriveChunkMarker &other) const - { - return marker == other.marker && offset == other.offset && width == other.width; - } - - bool operator<(const DriveChunkMarker &other) const - { - if (marker != other.marker) - return marker < other.marker; - if (width != other.width) - return width < other.width; - return offset < other.offset; - } - - unsigned int hash() const - { - return mkhash_add(mkhash(marker, width), offset); - } + int marker; + int offset; + int width; + + DriveChunkMarker(int marker, int offset, int width); + DriveChunkMarker(DriveBitMarker const &bit); + + int size() const; + DriveBitMarker operator[](int i) const; + bool can_append(DriveBitMarker const &bit) const; + bool try_append(DriveBitMarker const &bit); + bool try_append(DriveChunkMarker const &chunk); + bool operator==(const DriveChunkMarker &other) const; + bool operator<(const DriveChunkMarker &other) const; + unsigned int hash() const; }; struct DriveChunkMultiple { private: - mutable pool multiple_; - int width_; + mutable pool multiple_; + int width_; public: - pool const &multiple() const { return multiple_; } - - DriveChunkMultiple(DriveBitMultiple const &bit) : width_(1) { - for (auto const &bit : bit.multiple()) - multiple_.emplace(bit); - } - - int size() const { return width_; } - - DriveBitMultiple operator[](int i) const; - - bool can_append(DriveBitMultiple const &bit) const; - - bool try_append(DriveBitMultiple const &bit); - - - bool can_append(DriveChunkMultiple const &bit) const; - - bool try_append(DriveChunkMultiple const &bit); - - bool operator==(const DriveChunkMultiple &other) const - { - return width_ == other.width_ && multiple_ == other.multiple_; - } - - bool operator<(const DriveChunkMultiple &other) const - { - if (multiple_.size() < other.multiple_.size()) - - multiple_.sort(); - return false; // TODO implement, canonicalize order - } - - unsigned int hash() const - { - return mkhash(width_, multiple_.hash()); - } + pool const &multiple() const; + + DriveChunkMultiple(DriveBitMultiple const &bit); + + int size() const; + DriveBitMultiple operator[](int i) const; + bool can_append(DriveBitMultiple const &bit) const; + bool try_append(DriveBitMultiple const &bit); + bool can_append(DriveChunkMultiple const &bit) const; + bool try_append(DriveChunkMultiple const &bit); + bool operator==(const DriveChunkMultiple &other) const; + bool operator<(const DriveChunkMultiple &other) const; + unsigned int hash() const; }; struct DriveChunk { private: - DriveType type_ = DriveType::NONE; - union - { - int none_; - Const constant_; - DriveChunkWire wire_; - DriveChunkPort port_; - DriveChunkMarker marker_; - DriveChunkMultiple multiple_; - }; + DriveType type_ = DriveType::NONE; + union + { + int none_; + Const constant_; + DriveChunkWire wire_; + DriveChunkPort port_; + DriveChunkMarker marker_; + DriveChunkMultiple multiple_; + }; public: - DriveChunk() { set_none(); } - - DriveChunk(DriveChunk const &other) { *this = other; } - DriveChunk(DriveChunk &&other) { *this = other; } - - DriveChunk(DriveBit const &other) { *this = other; } - - DriveChunk(Const const &constant) { *this = constant; } - DriveChunk(Const &&constant) { *this = constant; } - DriveChunk(DriveChunkWire const &wire) { *this = wire; } - DriveChunk(DriveChunkWire &&wire) { *this = wire; } - DriveChunk(DriveChunkPort const &port) { *this = port; } - DriveChunk(DriveChunkPort &&port) { *this = port; } - DriveChunk(DriveChunkMarker const &marker) { *this = marker; } - DriveChunk(DriveChunkMarker &&marker) { *this = marker; } - DriveChunk(DriveChunkMultiple const &multiple) { *this = multiple; } - DriveChunk(DriveChunkMultiple &&multiple) { *this = multiple; } - - ~DriveChunk() { set_none(); } - - DriveBit operator[](int i) const - { - switch (type_) - { - case DriveType::NONE: - return DriveBit(); - case DriveType::CONSTANT: - return constant_[i]; - case DriveType::WIRE: - return wire_[i]; - case DriveType::PORT: - return port_[i]; - case DriveType::MARKER: - return marker_[i]; - case DriveType::MULTIPLE: - return multiple_[i]; - } - log_abort(); - } - - void set_none(int width = 0) - { - switch (type_) - { - case DriveType::NONE: - none_ = width; - break; - case DriveType::CONSTANT: - constant_.~Const(); - break; - case DriveType::WIRE: - wire_.~DriveChunkWire(); - break; - case DriveType::PORT: - port_.~DriveChunkPort(); - break; - case DriveType::MARKER: - marker_.~DriveChunkMarker(); - break; - case DriveType::MULTIPLE: - multiple_.~DriveChunkMultiple(); - break; - } - type_ = DriveType::NONE; - none_ = width; - } - - DriveChunk &operator=(DriveChunk const &other) - { - switch (other.type_) - { - case DriveType::NONE: - set_none(other.none_); - break; - case DriveType::CONSTANT: - *this = other.constant_; - break; - case DriveType::WIRE: - *this = other.wire_; - break; - case DriveType::PORT: - *this = other.port_; - break; - case DriveType::MARKER: - *this = other.marker_; - break; - case DriveType::MULTIPLE: - *this = other.multiple_; - break; - } - return *this; - } - - DriveChunk &operator=(DriveChunk &&other) - { - switch (other.type_) - { - case DriveType::NONE: - set_none(other.none_); - break; - case DriveType::CONSTANT: - *this = std::move(other.constant_); - break; - case DriveType::WIRE: - *this = std::move(other.wire_); - break; - case DriveType::PORT: - *this = std::move(other.port_); - break; - case DriveType::MARKER: - *this = std::move(other.marker_); - break; - case DriveType::MULTIPLE: - *this = std::move(other.multiple_); - break; - } - return *this; - } - - DriveChunk &operator=(Const const &constant) - { - set_none(); - new (&constant_) Const(constant); - type_ = DriveType::CONSTANT; - return *this; - } - - DriveChunk &operator=(Const &&constant) - { - set_none(); - new (&constant_) Const(std::move(constant)); - type_ = DriveType::CONSTANT; - return *this; - } - - DriveChunk &operator=(DriveChunkWire const &wire) - { - set_none(); - new (&wire_) DriveChunkWire(wire); - type_ = DriveType::WIRE; - return *this; - } - - DriveChunk &operator=(DriveChunkWire &&wire) - { - set_none(); - new (&wire_) DriveChunkWire(wire); - type_ = DriveType::WIRE; - return *this; - } - - DriveChunk &operator=(DriveChunkPort const &port) - { - set_none(); - new (&port_) DriveChunkPort(port); - type_ = DriveType::PORT; - return *this; - } - - DriveChunk &operator=(DriveChunkPort &&port) - { - set_none(); - new (&port_) DriveChunkPort(port); - type_ = DriveType::PORT; - return *this; - } - - DriveChunk &operator=(DriveChunkMarker const &marker) - { - set_none(); - new (&marker_) DriveChunkMarker(marker); - type_ = DriveType::MARKER; - return *this; - } - - DriveChunk &operator=(DriveChunkMarker &&marker) - { - set_none(); - new (&marker_) DriveChunkMarker(marker); - type_ = DriveType::MARKER; - return *this; - } - - DriveChunk &operator=(DriveChunkMultiple const &multiple) - { - set_none(multiple.size()); - if (multiple.multiple().empty()) - return *this; - new (&multiple_) DriveChunkMultiple(multiple); - type_ = DriveType::MULTIPLE; - return *this; - } - - DriveChunk &operator=(DriveChunkMultiple &&multiple) - { - set_none(multiple.size()); - if (multiple.multiple().empty()) - return *this; - new (&multiple_) DriveChunkMultiple(multiple); - type_ = DriveType::MULTIPLE; - return *this; - } - - DriveChunk &operator=(DriveBit const &other) - { - switch (other.type()) - { - case DriveType::NONE: - set_none(1); - break; - case DriveType::CONSTANT: - *this = Const(other.constant()); - break; - case DriveType::WIRE: - *this = DriveChunkWire(other.wire()); - break; - case DriveType::PORT: - *this = DriveChunkPort(other.port()); - break; - case DriveType::MARKER: - *this = DriveChunkMarker(other.marker()); - break; - case DriveType::MULTIPLE: - *this = DriveChunkMultiple(other.multiple()); - break; - } - return *this; - } - - bool can_append(DriveBit const &bit) const; - bool try_append(DriveBit const &bit); - bool try_append(DriveChunk const &chunk); - - unsigned int hash() const - { - unsigned int inner; - switch (type_) - { - case DriveType::NONE: - inner = 0; - break; - case DriveType::CONSTANT: - inner = constant_.hash(); - break; - case DriveType::WIRE: - inner = wire_.hash(); - break; - case DriveType::PORT: - inner = port_.hash(); - break; - case DriveType::MARKER: - inner = marker_.hash(); - break; - case DriveType::MULTIPLE: - inner = multiple_.hash(); - break; - } - return mkhash((unsigned int)type_, inner); - } - - bool operator==(const DriveChunk &other) const - { - if (type_ != other.type_) - return false; - - switch (type_) - { - case DriveType::NONE: - return true; - case DriveType::CONSTANT: - return constant_ == other.constant_; - case DriveType::WIRE: - return wire_ == other.wire_; - case DriveType::PORT: - return port_ == other.port_; - case DriveType::MARKER: - return marker_ == other.marker_; - case DriveType::MULTIPLE: - return multiple_ == other.multiple_; - } - log_assert(false); - } - - bool operator!=(const DriveChunk &other) const - { - return !(*this == other); - } - - bool operator<(const DriveChunk &other) const - { - if (type_ != other.type_) - return type_ < other.type_; - switch (type_) - { - case DriveType::NONE: - return false; - case DriveType::CONSTANT: - return constant_ < other.constant_; - case DriveType::WIRE: - return wire_ < other.wire_; - case DriveType::PORT: - return port_ < other.port_; - case DriveType::MARKER: - return marker_ < other.marker_; - case DriveType::MULTIPLE: - return multiple_ < other.multiple_; - } - log_assert(false); - } - - DriveType type() const { return type_; } - - bool is_none() const { return type_ == DriveType::NONE; } - bool is_constant() const { return type_ == DriveType::CONSTANT; } - bool is_wire() const { return type_ == DriveType::WIRE; } - bool is_port() const { return type_ == DriveType::PORT; } - bool is_marker() const { return type_ == DriveType::MARKER; } - bool is_multiple() const { return type_ == DriveType::MULTIPLE; } - - Const &constant() { log_assert(is_constant()); return constant_; } - Const const &constant() const { log_assert(is_constant()); return constant_; } - DriveChunkWire &wire() { log_assert(is_wire()); return wire_; } - DriveChunkWire const &wire() const { log_assert(is_wire()); return wire_; } - DriveChunkPort &port() { log_assert(is_port()); return port_; } - DriveChunkPort const &port() const { log_assert(is_port()); return port_; } - DriveChunkMarker &marker() { log_assert(is_marker()); return marker_; } - DriveChunkMarker const &marker() const { log_assert(is_marker()); return marker_; } - DriveChunkMultiple &multiple() { log_assert(is_multiple()); return multiple_; } - DriveChunkMultiple const &multiple() const { log_assert(is_multiple()); return multiple_; } - - - int size() const - { - switch (type_) - { - case DriveType::NONE: - return none_; - case DriveType::CONSTANT: - return constant_.size(); - case DriveType::WIRE: - return wire_.size(); - case DriveType::PORT: - return port_.size(); - case DriveType::MARKER: - return marker_.size(); - case DriveType::MULTIPLE: - return multiple_.size(); - } - } + DriveChunk(); + DriveChunk(DriveChunk const &other); + DriveChunk(DriveChunk &&other); + DriveChunk(DriveBit const &other); + DriveChunk(Const const &constant); + DriveChunk(Const &&constant); + DriveChunk(DriveChunkWire const &wire); + DriveChunk(DriveChunkWire &&wire); + DriveChunk(DriveChunkPort const &port); + DriveChunk(DriveChunkPort &&port); + DriveChunk(DriveChunkMarker const &marker); + DriveChunk(DriveChunkMarker &&marker); + DriveChunk(DriveChunkMultiple const &multiple); + DriveChunk(DriveChunkMultiple &&multiple); + ~DriveChunk(); + + DriveBit operator[](int i) const; + void set_none(int width = 0); + DriveChunk &operator=(DriveChunk const &other); + DriveChunk &operator=(DriveChunk &&other); + DriveChunk &operator=(Const const &constant); + DriveChunk &operator=(Const &&constant); + DriveChunk &operator=(DriveChunkWire const &wire); + DriveChunk &operator=(DriveChunkWire &&wire); + DriveChunk &operator=(DriveChunkPort const &port); + DriveChunk &operator=(DriveChunkPort &&port); + DriveChunk &operator=(DriveChunkMarker const &marker); + DriveChunk &operator=(DriveChunkMarker &&marker); + DriveChunk &operator=(DriveChunkMultiple const &multiple); + DriveChunk &operator=(DriveChunkMultiple &&multiple); + DriveChunk &operator=(DriveBit const &other); + bool can_append(DriveBit const &bit) const; + bool try_append(DriveBit const &bit); + bool try_append(DriveChunk const &chunk); + unsigned int hash() const; + bool operator==(const DriveChunk &other) const; + bool operator!=(const DriveChunk &other) const; + bool operator<(const DriveChunk &other) const; + DriveType type() const; + bool is_none() const; + bool is_constant() const; + bool is_wire() const; + bool is_port() const; + bool is_marker() const; + bool is_multiple() const; + Const &constant(); + Const const &constant() const; + DriveChunkWire &wire(); + DriveChunkWire const &wire() const; + DriveChunkPort &port(); + DriveChunkPort const &port() const; + DriveChunkMarker &marker(); + DriveChunkMarker const &marker() const; + DriveChunkMultiple &multiple(); + DriveChunkMultiple const &multiple() const; + int size() const; }; struct DriveSpec { private: - int width_ = 0; - mutable std::vector chunks_; - mutable std::vector bits_; - mutable unsigned int hash_ = 0; + int width_ = 0; + mutable std::vector chunks_; + mutable std::vector bits_; + mutable unsigned int hash_ = 0; + public: + inline bool packed() const; + + DriveSpec(); + DriveSpec(DriveChunk const &chunk); + DriveSpec(DriveChunkWire const &chunk); + DriveSpec(DriveChunkPort const &chunk); + DriveSpec(DriveChunkMarker const &chunk); + DriveSpec(DriveChunkMultiple const &chunk); - inline bool packed() const { - return bits_.empty(); - } - - DriveSpec() {} - - DriveSpec(DriveChunk const &chunk) { *this = chunk; } - DriveSpec(DriveChunkWire const &chunk) { *this = chunk; } - DriveSpec(DriveChunkPort const &chunk) { *this = chunk; } - DriveSpec(DriveChunkMarker const &chunk) { *this = chunk; } - DriveSpec(DriveChunkMultiple const &chunk) { *this = chunk; } - - DriveSpec(DriveBit const &bit) { *this = bit; } - DriveSpec(DriveBitWire const &bit) { *this = bit; } - DriveSpec(DriveBitPort const &bit) { *this = bit; } - DriveSpec(DriveBitMarker const &bit) { *this = bit; } - DriveSpec(DriveBitMultiple const &bit) { *this = bit; } - - DriveSpec(std::vector const &chunks) : chunks_(chunks) { compute_width(); } - - DriveSpec(std::vector const &bits) - { - for (auto const &bit : bits) - append(bit); - } - - std::vector const &chunks() const { pack(); return chunks_; } - std::vector const &bits() const { unpack(); return bits_; } - - int size() const { return width_; } - - void append(DriveBit const &bit); - - void append(DriveChunk const &chunk); - - void pack() const; - - void unpack() const; - - DriveBit &operator[](int index) - { - log_assert(index >= 0 && index < size()); - unpack(); - return bits_[index]; - } - - const DriveBit &operator[](int index) const - { - log_assert(index >= 0 && index < size()); - unpack(); - return bits_[index]; - } - - void clear() - { - chunks_.clear(); - bits_.clear(); - width_ = 0; - } - - DriveSpec &operator=(DriveChunk const &chunk) - { - chunks_.clear(); - bits_.clear(); - append(chunk); - return *this; - } - - DriveSpec &operator=(DriveChunkWire const &chunk) { return *this = DriveChunk(chunk); } - DriveSpec &operator=(DriveChunkPort const &chunk) { return *this = DriveChunk(chunk); } - DriveSpec &operator=(DriveChunkMarker const &chunk) { return *this = DriveChunk(chunk); } - DriveSpec &operator=(DriveChunkMultiple const &chunk) { return *this = DriveChunk(chunk); } - - DriveSpec &operator=(DriveBit const &bit) - { - chunks_.clear(); - bits_.clear(); - append(bit); - return *this; - } - - DriveSpec &operator=(DriveBitWire const &bit) { return *this = DriveBit(bit); } - DriveSpec &operator=(DriveBitPort const &bit) { return *this = DriveBit(bit); } - DriveSpec &operator=(DriveBitMarker const &bit) { return *this = DriveBit(bit); } - DriveSpec &operator=(DriveBitMultiple const &bit) { return *this = DriveBit(bit); } - - unsigned int hash() const { - if (hash_ != 0) return hash_; - - pack(); - hash_ = hash_ops>().hash(chunks_); - hash_ |= (hash_ == 0); - return hash_; - } - - bool operator==(DriveSpec const &other) const { - if (size() != other.size() || hash() != other.hash()) - return false; - return chunks() == other.chunks(); - } + DriveSpec(DriveBit const &bit); + DriveSpec(DriveBitWire const &bit); + DriveSpec(DriveBitPort const &bit); + DriveSpec(DriveBitMarker const &bit); + DriveSpec(DriveBitMultiple const &bit); -private: - void compute_width(); -}; + DriveSpec(std::vector const &chunks); + DriveSpec(std::vector const &bits); + std::vector const &chunks() const; + std::vector const &bits() const; + int size() const; -struct DriverMap -{ - CellTypes celltypes; + void append(DriveBit const &bit); + void append(DriveChunk const &chunk); - DriverMap() { celltypes.setup(); } - DriverMap(Design *design) { celltypes.setup(); celltypes.setup_design(design); } + void pack() const; + void unpack() const; -private: + DriveBit &operator[](int index); + const DriveBit &operator[](int index) const; - // Internally we represent all DriveBits by mapping them to DriveBitIds - // which use less memory and are cheaper to compare. - struct DriveBitId - { - int id = -1; - - DriveBitId() {}; - - DriveBitId(int id) : id(id) { } - - bool operator==(const DriveBitId &other) const { return id == other.id; } - bool operator!=(const DriveBitId &other) const { return id != other.id; } - bool operator<(const DriveBitId &other) const { return id < other.id; } - unsigned int hash() const { return id; } - }; - // Essentially a dict> but using less memory - // and fewer allocations - struct DriveBitGraph { - dict first_edges; - dict second_edges; - dict> more_edges; - - void add_edge(DriveBitId src, DriveBitId dst); - DriveBitId pop_edge(DriveBitId src); - void clear(DriveBitId src); - bool contains(DriveBitId src); - int count(DriveBitId src); - - DriveBitId at(DriveBitId src, int index); - }; - - // The following two maps maintain a sparse DriveBit to DriveBitId mapping. - // This saves a lot of memory compared to a `dict` or - // `idict`. - - // Maps wires to the first DriveBitId of the consecutive range used for - // that wire. - dict wire_offsets; - - // Maps cell ports to a the first DriveBitId of the consecutive range used - // for that cell port. - dict, DriveBitId> port_offsets; - - // For the inverse map that maps DriveBitIds back to DriveBits we use a - // sorted map containing only the first DriveBit for each wire and cell - // port. - std::map drive_bits; - - // As a memory optimization for gate level net lists we store single-bit - // wires and cell ports in a `dict` which requires less memory and fewer - // allocations than `std::map` but doesn't support the kind of lookups we - // need for a sparse coarse grained mapping. - dict isolated_drive_bits; - - // Used for allocating DriveBitIds, none and constant states use a fixewd - // mapping to the first few ids, which we need to skip. - int next_offset = 1 + (int)State::Sm; - - // Union-Find over directly connected bits that share the same single - // driver or are undriven. We never merge connections between drivers - // and/or kept wires. - mfp same_driver; - - // For each bit, store a set of connected driver bits for which the - // explicit connection should be preserved and the driving direction is - // locally unambiguous (one side only drives or requires a driven value). - DriveBitGraph connected_drivers; - - // For each bit, store a set of connected driver bits for which the - // explicit connection should be preserved and the driving direction is - // locally ambiguous. Every such ambiguous connection is also present in - // the reverse direction and has to be resolved when querying drivers. - DriveBitGraph connected_undirected; - - // Subset of `connected_undirected` for caching the resolved driving - // direction. In case multiple drivers are present this can still contain - // both orientations of a single connection, but for a single driver only - // one will be present. - DriveBitGraph connected_oriented; - - // Stores for which bits we already resolved the orientation (cached in - // `connected_oriented`). - pool oriented_present; - - - enum class BitMode { - NONE = 0, // Not driven, no need to keep wire - DRIVEN = 1, // Not driven, uses a value driven elsewhere - DRIVEN_UNIQUE = 2, // Uses a value driven elsewhere, has at most one direct connection - KEEP = 3, // Wire that should be kept - TRISTATE = 4, // Can drive a value but can also use a value driven elsewhere - DRIVER = 5, // Drives a value - }; - - BitMode bit_mode(DriveBit const &bit); - DriveBitId id_from_drive_bit(DriveBit const &bit); - DriveBit drive_bit_from_id(DriveBitId id); - - void connect_directed_merge(DriveBitId driven_id, DriveBitId driver_id); - void connect_directed_buffer(DriveBitId driven_id, DriveBitId driver_id); - void connect_undirected(DriveBitId a_id, DriveBitId b_id); + void clear(); -public: + DriveSpec &operator=(DriveChunk const &chunk); + DriveSpec &operator=(DriveChunkWire const &chunk); + DriveSpec &operator=(DriveChunkPort const &chunk); + DriveSpec &operator=(DriveChunkMarker const &chunk); + DriveSpec &operator=(DriveChunkMultiple const &chunk); - void add(Module *module); - - // Add a single bit connection to the driver map. - void add(DriveBit const &a, DriveBit const &b); - - template - static constexpr bool is_sig_type() { - return - std::is_same::value || - std::is_same::value || - std::is_same::value || - std::is_same::value || - std::is_same::value || - std::is_same::value || - std::is_same::value; - } - - // We use the enable_if to produce better compiler errors when unsupported - // types are used - template - typename std::enable_if() && is_sig_type()>::type - add(T const &a, U const &b) - { - log_assert(a.size() == b.size()); - for (int i = 0; i != GetSize(a); ++i) - add(DriveBit(a[i]), DriveBit(b[i])); - } - - - // Specialized version that avoids unpacking - void add(SigSpec const &a, SigSpec const &b); + DriveSpec &operator=(DriveBit const &bit); + DriveSpec &operator=(DriveBitWire const &bit); + DriveSpec &operator=(DriveBitPort const &bit); + DriveSpec &operator=(DriveBitMarker const &bit); + DriveSpec &operator=(DriveBitMultiple const &bit); -private: - void add_port(Cell *cell, IdString const &port, SigSpec const &b); + unsigned int hash() const; - // Only used a local variables in `orient_undirected`, always cleared, only - // stored to reduce allocations. - pool orient_undirected_seen; - pool orient_undirected_drivers; - dict orient_undirected_distance; + bool operator==(DriveSpec const &other) const; - void orient_undirected(DriveBitId id); +private: + void compute_width(); +}; -public: - DriveBit operator()(DriveBit const &bit); +struct DriverMap +{ + CellTypes celltypes; - DriveSpec operator()(DriveSpec spec); + DriverMap(); + DriverMap(Design *design); private: - bool keep_wire(Wire *wire) { - // TODO configurable - return wire->has_attribute(ID(keep)); - } + + // Internally we represent all DriveBits by mapping them to DriveBitIds + // which use less memory and are cheaper to compare. + struct DriveBitId + { + int id; + + DriveBitId(); + DriveBitId(int id); + + bool operator==(const DriveBitId &other) const; + bool operator!=(const DriveBitId &other) const; + bool operator<(const DriveBitId &other) const; + unsigned int hash() const; + }; + + // Essentially a dict> but using less memory + // and fewer allocations + struct DriveBitGraph + { + dict first_edges; + dict second_edges; + dict> more_edges; + + void add_edge(DriveBitId src, DriveBitId dst); + DriveBitId pop_edge(DriveBitId src); + void clear(DriveBitId src); + bool contains(DriveBitId src); + int count(DriveBitId src); + DriveBitId at(DriveBitId src, int index); + }; + + + // The following two maps maintain a sparse DriveBit to DriveBitId mapping. + // This saves a lot of memory compared to a `dict` or + // `idict`. + + // Maps wires to the first DriveBitId of the consecutive range used for + // that wire. + dict wire_offsets; + + // Maps cell ports to a the first DriveBitId of the consecutive range used + // for that cell port. + dict, DriveBitId> port_offsets; + + // For the inverse map that maps DriveBitIds back to DriveBits we use a + // sorted map containing only the first DriveBit for each wire and cell + // port. + std::map drive_bits; + + // As a memory optimization for gate level net lists we store single-bit + // wires and cell ports in a `dict` which requires less memory and fewer + // allocations than `std::map` but doesn't support the kind of lookups we + // need for a sparse coarse grained mapping. + dict isolated_drive_bits; + + // Used for allocating DriveBitIds, none and constant states use a fixewd + // mapping to the first few ids, which we need to skip. + int next_offset = 1 + (int)State::Sm; + + // Union-Find over directly connected bits that share the same single + // driver or are undriven. We never merge connections between drivers + // and/or kept wires. + mfp same_driver; + + // For each bit, store a set of connected driver bits for which the + // explicit connection should be preserved and the driving direction is + // locally unambiguous (one side only drives or requires a driven value). + DriveBitGraph connected_drivers; + + // For each bit, store a set of connected driver bits for which the + // explicit connection should be preserved and the driving direction is + // locally ambiguous. Every such ambiguous connection is also present in + // the reverse direction and has to be resolved when querying drivers. + DriveBitGraph connected_undirected; + + // Subset of `connected_undirected` for caching the resolved driving + // direction. In case multiple drivers are present this can still contain + // both orientations of a single connection, but for a single driver only + // one will be present. + DriveBitGraph connected_oriented; + + // Stores for which bits we already resolved the orientation (cached in + // `connected_oriented`). + pool oriented_present; + + enum class BitMode { + NONE = 0, // Not driven, no need to keep wire + DRIVEN = 1, // Not driven, uses a value driven elsewhere + DRIVEN_UNIQUE = 2, // Uses a value driven elsewhere, has at most one direct connection + KEEP = 3, // Wire that should be kept + TRISTATE = 4, // Can drive a value but can also use a value driven elsewhere + DRIVER = 5, // Drives a value + }; + + BitMode bit_mode(DriveBit const &bit); + DriveBitId id_from_drive_bit(DriveBit const &bit); + DriveBit drive_bit_from_id(DriveBitId id); + void connect_directed_merge(DriveBitId driven_id, DriveBitId driver_id); + void connect_directed_buffer(DriveBitId driven_id, DriveBitId driver_id); + void connect_undirected(DriveBitId a_id, DriveBitId b_id); + void add_port(Cell *cell, IdString const &port, SigSpec const &b); + void orient_undirected(DriveBitId id); + bool keep_wire(Wire *wire); + + // Only used a local variables in `orient_undirected`, always cleared, only + // stored to reduce allocations. + pool orient_undirected_seen; + pool orient_undirected_drivers; + dict orient_undirected_distance; + + +public: + void add(Module *module); + void add(DriveBit const &a, DriveBit const &b); + + + template + static constexpr bool is_sig_type() { + return + std::is_same::value || + std::is_same::value || + std::is_same::value || + std::is_same::value || + std::is_same::value || + std::is_same::value || + std::is_same::value; + } + + // We use the enable_if to produce better compiler errors when unsupported + // types are used + template + typename std::enable_if() && is_sig_type()>::type + add(T const &a, U const &b) + { + log_assert(a.size() == b.size()); + for (int i = 0; i != GetSize(a); ++i) + add(DriveBit(a[i]), DriveBit(b[i])); + } + + // Specialized version that avoids unpacking + void add(SigSpec const &a, SigSpec const &b); + DriveBit operator()(DriveBit const &bit); + DriveSpec operator()(DriveSpec spec); }; YOSYS_NAMESPACE_END From 4828e8d860840c48c5db7c73a6861abcc477c4bd Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Fri, 24 May 2024 13:49:39 +0200 Subject: [PATCH 14/51] Include cassert --- backends/functional/smtlib.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index f6af797919b..cd11111b9d8 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -17,6 +17,7 @@ * */ +#include #include "kernel/yosys.h" #include "kernel/drivertools.h" #include "kernel/topo_scc.h" From 2eb24db8c3c5d79cbcbbe474c0c908710b9b4353 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Sat, 25 May 2024 10:39:18 +0200 Subject: [PATCH 15/51] Created tests for functional C++ backend, comparing its VCD output to CXXRTL VCD output, using vcdiff from CERN --- backends/functional/cxx.cc | 714 +++++++++++++------------- backends/functional/cxx_runtime/sim.h | 2 + flake.nix | 27 +- tests/functional/.gitignore | 5 + tests/functional/run-test.sh | 7 + tests/functional/vcd_harness.cpp | 140 +++++ tests/functional/verilog/and.v | 9 + 7 files changed, 546 insertions(+), 358 deletions(-) create mode 100644 tests/functional/.gitignore create mode 100755 tests/functional/run-test.sh create mode 100644 tests/functional/vcd_harness.cpp create mode 100644 tests/functional/verilog/and.v diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index 5038a9af252..a1060c58d79 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -29,391 +29,391 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN const char *reserved_keywords[] = { - "alignas","alignof","and","and_eq","asm","atomic_cancel","atomic_commit", - "atomic_noexcept","auto","bitand","bitor","bool","break","case", - "catch","char","char16_t","char32_t","char8_t","class","co_await", - "co_return","co_yield","compl","concept","const","const_cast","consteval", - "constexpr","constinit","continue","decltype","default","delete", - "do","double","dynamic_cast","else","enum","explicit","export", - "extern","false","float","for","friend","goto","if","inline", - "int","long","mutable","namespace","new","noexcept","not","not_eq", - "nullptr","operator","or","or_eq","private","protected","public", - "reflexpr","register","reinterpret_cast","requires","return","short", - "signed","sizeof","static","static_assert","static_cast","struct", - "switch","synchronized","template","this","thread_local","throw", - "true","try","typedef","typeid","typename","union","unsigned", - "using","virtual","void","volatile","wchar_t","while","xor","xor_eq", - nullptr + "alignas","alignof","and","and_eq","asm","atomic_cancel","atomic_commit", + "atomic_noexcept","auto","bitand","bitor","bool","break","case", + "catch","char","char16_t","char32_t","char8_t","class","co_await", + "co_return","co_yield","compl","concept","const","const_cast","consteval", + "constexpr","constinit","continue","decltype","default","delete", + "do","double","dynamic_cast","else","enum","explicit","export", + "extern","false","float","for","friend","goto","if","inline", + "int","long","mutable","namespace","new","noexcept","not","not_eq", + "nullptr","operator","or","or_eq","private","protected","public", + "reflexpr","register","reinterpret_cast","requires","return","short", + "signed","sizeof","static","static_assert","static_cast","struct", + "switch","synchronized","template","this","thread_local","throw", + "true","try","typedef","typeid","typename","union","unsigned", + "using","virtual","void","volatile","wchar_t","while","xor","xor_eq", + nullptr }; struct CxxScope { - pool used_names; - dict name_map; - - CxxScope() { - for(const char **p = reserved_keywords; *p != nullptr; p++) - reserve(*p); - } - void reserve(std::string name) { - used_names.insert(name); - } - std::string insert(IdString id) { - std::string str = RTLIL::unescape_id(id); - for(size_t i = 0; i < str.size(); i++) - if(strchr("!\"#%&'()*+,-./:;<=>?@[]\\^`{|}~ ", str[i])) - str[i] = '_'; - if(used_names.count(str) == 0){ - used_names.insert(str); - name_map.insert({id, str}); - return str; - } - for (int idx = 0 ; ; idx++){ - std::string suffixed = str + "_" + std::to_string(idx); - if (used_names.count(suffixed) == 0) { - used_names.insert(suffixed); - if(name_map.count(id) == 0) - name_map.insert({id, suffixed}); - return suffixed; - } - } - } - std::string operator[](IdString id) { - if(name_map.count(id) > 0) - return name_map[id]; - else - return insert(id); - } + pool used_names; + dict name_map; + + CxxScope() { + for(const char **p = reserved_keywords; *p != nullptr; p++) + reserve(*p); + } + void reserve(std::string name) { + used_names.insert(name); + } + std::string insert(IdString id) { + std::string str = RTLIL::unescape_id(id); + for(size_t i = 0; i < str.size(); i++) + if(strchr("!\"#%&'()*+,-./:;<=>?@[]\\^`{|}~ ", str[i])) + str[i] = '_'; + if(used_names.count(str) == 0){ + used_names.insert(str); + name_map.insert({id, str}); + return str; + } + for (int idx = 0 ; ; idx++){ + std::string suffixed = str + "_" + std::to_string(idx); + if (used_names.count(suffixed) == 0) { + used_names.insert(suffixed); + if(name_map.count(id) == 0) + name_map.insert({id, suffixed}); + return suffixed; + } + } + } + std::string operator[](IdString id) { + if(name_map.count(id) > 0) + return name_map[id]; + else + return insert(id); + } }; struct CxxWriter { - std::ostream &f; - CxxWriter(std::ostream &out) : f(out) {} - void printf(const char *fmt, ...) - { - va_list va; - va_start(va, fmt); - f << vstringf(fmt, va); - va_end(va); - } + std::ostream &f; + CxxWriter(std::ostream &out) : f(out) {} + void printf(const char *fmt, ...) + { + va_list va; + va_start(va, fmt); + f << vstringf(fmt, va); + va_end(va); + } }; struct CxxStruct { - std::string name; - dict types; - CxxScope scope; - CxxStruct(std::string name) : name(name) { - scope.reserve("out"); - scope.reserve("dump"); - } - void insert(IdString name, std::string type) { - scope.insert(name); - types.insert({name, type}); - } - void print(CxxWriter &f) { - f.printf("struct %s {\n", name.c_str()); - for (auto p : types) { - f.printf("\t%s %s;\n", p.second.c_str(), scope[p.first].c_str()); - } - f.printf("\n\ttemplate void dump(T &out) {\n"); - for (auto p : types) { - f.printf("\t\tout(\"%s\", %s);\n", RTLIL::unescape_id(p.first).c_str(), scope[p.first].c_str()); - } - f.printf("\t}\n};\n\n"); - } - std::string operator[](IdString field) { - return scope[field]; - } + std::string name; + dict types; + CxxScope scope; + CxxStruct(std::string name) : name(name) { + scope.reserve("out"); + scope.reserve("dump"); + } + void insert(IdString name, std::string type) { + scope.insert(name); + types.insert({name, type}); + } + void print(CxxWriter &f) { + f.printf("struct %s {\n", name.c_str()); + for (auto p : types) { + f.printf("\t%s %s;\n", p.second.c_str(), scope[p.first].c_str()); + } + f.printf("\n\ttemplate void dump(T &out) {\n"); + for (auto p : types) { + f.printf("\t\tout(\"%s\", %s);\n", RTLIL::unescape_id(p.first).c_str(), scope[p.first].c_str()); + } + f.printf("\t}\n};\n\n"); + } + std::string operator[](IdString field) { + return scope[field]; + } }; struct CxxFunction { - IdString name; - int width; - dict parameters; + IdString name; + int width; + dict parameters; - CxxFunction(IdString name, int width) : name(name), width(width) {} - CxxFunction(IdString name, int width, dict parameters) : name(name), width(width), parameters(parameters) {} + CxxFunction(IdString name, int width) : name(name), width(width) {} + CxxFunction(IdString name, int width, dict parameters) : name(name), width(width), parameters(parameters) {} - bool operator==(CxxFunction const &other) const { - return name == other.name && parameters == other.parameters && width == other.width; - } + bool operator==(CxxFunction const &other) const { + return name == other.name && parameters == other.parameters && width == other.width; + } - unsigned int hash() const { - return mkhash(name.hash(), parameters.hash()); - } + unsigned int hash() const { + return mkhash(name.hash(), parameters.hash()); + } }; typedef ComputeGraph CxxComputeGraph; class CxxComputeGraphFactory { - CxxComputeGraph &graph; - using T = CxxComputeGraph::Ref; - static bool is_single_output(IdString type) - { - auto it = yosys_celltypes.cell_types.find(type); - return it != yosys_celltypes.cell_types.end() && it->second.outputs.size() <= 1; - } + CxxComputeGraph &graph; + using T = CxxComputeGraph::Ref; + static bool is_single_output(IdString type) + { + auto it = yosys_celltypes.cell_types.find(type); + return it != yosys_celltypes.cell_types.end() && it->second.outputs.size() <= 1; + } public: - CxxComputeGraphFactory(CxxComputeGraph &g) : graph(g) {} - T slice(T a, int in_width, int offset, int out_width) { - assert(offset + out_width <= in_width); - return graph.add(CxxFunction(ID($$slice), out_width, {{ID(offset), offset}}), 0, std::array{a}); - } - T extend(T a, int in_width, int out_width, bool is_signed) { - assert(in_width < out_width); - if(is_signed) - return graph.add(CxxFunction(ID($sign_extend), out_width, {{ID(WIDTH), out_width}}), 0, std::array{a}); - else - return graph.add(CxxFunction(ID($zero_extend), out_width, {{ID(WIDTH), out_width}}), 0, std::array{a}); - } - T concat(T a, int a_width, T b, int b_width) { - return graph.add(CxxFunction(ID($$concat), a_width + b_width), 0, std::array{a, b}); - } - T add(T a, T b, int width) { return graph.add(CxxFunction(ID($add), width), 0, std::array{a, b}); } - T sub(T a, T b, int width) { return graph.add(CxxFunction(ID($sub), width), 0, std::array{a, b}); } - T bitwise_and(T a, T b, int width) { return graph.add(CxxFunction(ID($and), width), 0, std::array{a, b}); } - T bitwise_or(T a, T b, int width) { return graph.add(CxxFunction(ID($or), width), 0, std::array{a, b}); } - T bitwise_xor(T a, T b, int width) { return graph.add(CxxFunction(ID($xor), width), 0, std::array{a, b}); } - T bitwise_not(T a, int width) { return graph.add(CxxFunction(ID($not), width), 0, std::array{a}); } - T neg(T a, int width) { return graph.add(CxxFunction(ID($neg), width), 0, std::array{a}); } - T mux(T a, T b, T s, int width) { return graph.add(CxxFunction(ID($mux), width), 0, std::array{a, b, s}); } - T pmux(T a, T b, T s, int width, int) { return graph.add(CxxFunction(ID($pmux), width), 0, std::array{a, b, s}); } - T reduce_and(T a, int) { return graph.add(CxxFunction(ID($reduce_and), 1), 0, std::array{a}); } - T reduce_or(T a, int) { return graph.add(CxxFunction(ID($reduce_or), 1), 0, std::array{a}); } - T reduce_xor(T a, int) { return graph.add(CxxFunction(ID($reduce_xor), 1), 0, std::array{a}); } - T eq(T a, T b, int) { return graph.add(CxxFunction(ID($eq), 1), 0, std::array{a, b}); } - T ne(T a, T b, int) { return graph.add(CxxFunction(ID($ne), 1), 0, std::array{a, b}); } - T gt(T a, T b, int) { return graph.add(CxxFunction(ID($gt), 1), 0, std::array{a, b}); } - T ge(T a, T b, int) { return graph.add(CxxFunction(ID($ge), 1), 0, std::array{a, b}); } - T ugt(T a, T b, int) { return graph.add(CxxFunction(ID($ugt), 1), 0, std::array{a, b}); } - T uge(T a, T b, int) { return graph.add(CxxFunction(ID($uge), 1), 0, std::array{a, b}); } - T logical_shift_left(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($shl), y_width, {{ID(WIDTH), y_width}}), 0, std::array{a, b}); } - T logical_shift_right(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($shr), y_width, {{ID(WIDTH), y_width}}), 0, std::array{a, b}); } - T arithmetic_shift_right(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($asr), y_width, {{ID(WIDTH), y_width}}), 0, std::array{a, b}); } - - T constant(RTLIL::Const value) { - return graph.add(CxxFunction(ID($$const), value.size(), {{ID(value), value}}), 0); - } - T input(IdString name, int width) { return graph.add(CxxFunction(ID($$input), width, {{name, {}}}), 0); } - T state(IdString name, int width) { return graph.add(CxxFunction(ID($$state), width, {{name, {}}}), 0); } - T cell_output(T cell, IdString type, IdString name, int width) { - if (is_single_output(type)) - return cell; - else - return graph.add(CxxFunction(ID($$cell_output), width, {{name, {}}}), 0, std::array{cell}); - } - T multiple(vector args, int width) { - return graph.add(CxxFunction(ID($$multiple), width), 0, args); - } - T undriven(int width) { - return graph.add(CxxFunction(ID($$undriven), width), 0); - } - - T create_pending(int width) { - return graph.add(CxxFunction(ID($$pending), width), 0); - } - void update_pending(T pending, T node) { - assert(pending.function().name == ID($$pending)); - pending.set_function(CxxFunction(ID($$buf), pending.function().width)); - pending.append_arg(node); - } - void declare_output(T node, IdString name, int) { - node.assign_key(name); - } - void declare_state(T node, IdString name, int) { - node.assign_key(name); - } - void suggest_name(T node, IdString name) { - node.sparse_attr() = name; - } + CxxComputeGraphFactory(CxxComputeGraph &g) : graph(g) {} + T slice(T a, int in_width, int offset, int out_width) { + assert(offset + out_width <= in_width); + return graph.add(CxxFunction(ID($$slice), out_width, {{ID(offset), offset}}), 0, std::array{a}); + } + T extend(T a, int in_width, int out_width, bool is_signed) { + assert(in_width < out_width); + if(is_signed) + return graph.add(CxxFunction(ID($sign_extend), out_width, {{ID(WIDTH), out_width}}), 0, std::array{a}); + else + return graph.add(CxxFunction(ID($zero_extend), out_width, {{ID(WIDTH), out_width}}), 0, std::array{a}); + } + T concat(T a, int a_width, T b, int b_width) { + return graph.add(CxxFunction(ID($$concat), a_width + b_width), 0, std::array{a, b}); + } + T add(T a, T b, int width) { return graph.add(CxxFunction(ID($add), width), 0, std::array{a, b}); } + T sub(T a, T b, int width) { return graph.add(CxxFunction(ID($sub), width), 0, std::array{a, b}); } + T bitwise_and(T a, T b, int width) { return graph.add(CxxFunction(ID($and), width), 0, std::array{a, b}); } + T bitwise_or(T a, T b, int width) { return graph.add(CxxFunction(ID($or), width), 0, std::array{a, b}); } + T bitwise_xor(T a, T b, int width) { return graph.add(CxxFunction(ID($xor), width), 0, std::array{a, b}); } + T bitwise_not(T a, int width) { return graph.add(CxxFunction(ID($not), width), 0, std::array{a}); } + T neg(T a, int width) { return graph.add(CxxFunction(ID($neg), width), 0, std::array{a}); } + T mux(T a, T b, T s, int width) { return graph.add(CxxFunction(ID($mux), width), 0, std::array{a, b, s}); } + T pmux(T a, T b, T s, int width, int) { return graph.add(CxxFunction(ID($pmux), width), 0, std::array{a, b, s}); } + T reduce_and(T a, int) { return graph.add(CxxFunction(ID($reduce_and), 1), 0, std::array{a}); } + T reduce_or(T a, int) { return graph.add(CxxFunction(ID($reduce_or), 1), 0, std::array{a}); } + T reduce_xor(T a, int) { return graph.add(CxxFunction(ID($reduce_xor), 1), 0, std::array{a}); } + T eq(T a, T b, int) { return graph.add(CxxFunction(ID($eq), 1), 0, std::array{a, b}); } + T ne(T a, T b, int) { return graph.add(CxxFunction(ID($ne), 1), 0, std::array{a, b}); } + T gt(T a, T b, int) { return graph.add(CxxFunction(ID($gt), 1), 0, std::array{a, b}); } + T ge(T a, T b, int) { return graph.add(CxxFunction(ID($ge), 1), 0, std::array{a, b}); } + T ugt(T a, T b, int) { return graph.add(CxxFunction(ID($ugt), 1), 0, std::array{a, b}); } + T uge(T a, T b, int) { return graph.add(CxxFunction(ID($uge), 1), 0, std::array{a, b}); } + T logical_shift_left(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($shl), y_width, {{ID(WIDTH), y_width}}), 0, std::array{a, b}); } + T logical_shift_right(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($shr), y_width, {{ID(WIDTH), y_width}}), 0, std::array{a, b}); } + T arithmetic_shift_right(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($asr), y_width, {{ID(WIDTH), y_width}}), 0, std::array{a, b}); } + + T constant(RTLIL::Const value) { + return graph.add(CxxFunction(ID($$const), value.size(), {{ID(value), value}}), 0); + } + T input(IdString name, int width) { return graph.add(CxxFunction(ID($$input), width, {{name, {}}}), 0); } + T state(IdString name, int width) { return graph.add(CxxFunction(ID($$state), width, {{name, {}}}), 0); } + T cell_output(T cell, IdString type, IdString name, int width) { + if (is_single_output(type)) + return cell; + else + return graph.add(CxxFunction(ID($$cell_output), width, {{name, {}}}), 0, std::array{cell}); + } + T multiple(vector args, int width) { + return graph.add(CxxFunction(ID($$multiple), width), 0, args); + } + T undriven(int width) { + return graph.add(CxxFunction(ID($$undriven), width), 0); + } + + T create_pending(int width) { + return graph.add(CxxFunction(ID($$pending), width), 0); + } + void update_pending(T pending, T node) { + assert(pending.function().name == ID($$pending)); + pending.set_function(CxxFunction(ID($$buf), pending.function().width)); + pending.append_arg(node); + } + void declare_output(T node, IdString name, int) { + node.assign_key(name); + } + void declare_state(T node, IdString name, int) { + node.assign_key(name); + } + void suggest_name(T node, IdString name) { + node.sparse_attr() = name; + } }; struct FunctionalCxxBackend : public Backend { - FunctionalCxxBackend() : Backend("functional_cxx", "convert design to C++ using the functional backend") {} - - void help() override + FunctionalCxxBackend() : Backend("functional_cxx", "convert design to C++ using the functional backend") {} + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + } + + CxxComputeGraph calculate_compute_graph(RTLIL::Module *module) + { + CxxComputeGraph compute_graph; + CxxComputeGraphFactory factory(compute_graph); + ComputeGraphConstruction construction(factory); + construction.add_module(module); + construction.process_queue(); + + // Perform topo sort and detect SCCs + CxxComputeGraph::SccAdaptor compute_graph_scc(compute_graph); + + bool scc = false; + std::vector perm; + topo_sorted_sccs(compute_graph_scc, [&](int *begin, int *end) { + perm.insert(perm.end(), begin, end); + if (end > begin + 1) { - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); - } - - CxxComputeGraph calculate_compute_graph(RTLIL::Module *module) - { - CxxComputeGraph compute_graph; - CxxComputeGraphFactory factory(compute_graph); - ComputeGraphConstruction construction(factory); - construction.add_module(module); - construction.process_queue(); - - // Perform topo sort and detect SCCs - CxxComputeGraph::SccAdaptor compute_graph_scc(compute_graph); - - bool scc = false; - std::vector perm; - topo_sorted_sccs(compute_graph_scc, [&](int *begin, int *end) { - perm.insert(perm.end(), begin, end); - if (end > begin + 1) - { - log_warning("SCC:"); - for (int *i = begin; i != end; ++i) - log(" %d(%s)(%s)", *i, compute_graph[*i].function().name.c_str(), compute_graph[*i].has_sparse_attr() ? compute_graph[*i].sparse_attr().c_str() : ""); - log("\n"); - scc = true; - } - }, /* sources_first */ true); - compute_graph.permute(perm); - if(scc) log_error("combinational loops, aborting\n"); - - // Forward $$buf - std::vector alias; - perm.clear(); - - for (int i = 0; i < compute_graph.size(); ++i) - { - auto node = compute_graph[i]; - if (node.function().name == ID($$buf) && node.arg(0).index() < i) - { - int target_index = alias[node.arg(0).index()]; - auto target_node = compute_graph[perm[target_index]]; - if(!target_node.has_sparse_attr() && node.has_sparse_attr()) - target_node.sparse_attr() = node.sparse_attr(); - alias.push_back(target_index); - } - else - { - alias.push_back(GetSize(perm)); - perm.push_back(i); - } - } - compute_graph.permute(perm, alias); - return compute_graph; - } - - void printCxx(std::ostream &stream, std::string, std::string const & name, CxxComputeGraph &compute_graph) - { - dict inputs, state; - CxxWriter f(stream); - - // Dump the compute graph - for (int i = 0; i < compute_graph.size(); ++i) - { - auto ref = compute_graph[i]; - if(ref.function().name == ID($$input)) - inputs[ref.function().parameters.begin()->first] = ref.function().width; - if(ref.function().name == ID($$state)) - state[ref.function().parameters.begin()->first] = ref.function().width; - } - f.printf("#include \"sim.h\"\n"); - CxxStruct input_struct(name + "_Inputs"); - for (auto const &input : inputs) - input_struct.insert(input.first, "Signal<" + std::to_string(input.second) + ">"); - CxxStruct output_struct(name + "_Outputs"); - for (auto const &key : compute_graph.keys()) - if(state.count(key.first) == 0) - output_struct.insert(key.first, "Signal<" + std::to_string(compute_graph[key.second].function().width) + ">"); - CxxStruct state_struct(name + "_State"); - for (auto const &state_var : state) - state_struct.insert(state_var.first, "Signal<" + std::to_string(state_var.second) + ">"); - - idict node_names; - CxxScope locals; - - input_struct.print(f); - output_struct.print(f); - state_struct.print(f); - - f.printf("void %s(%s_Inputs const &input, %s_Outputs &output, %s_State const ¤t_state, %s_State &next_state)\n{\n", name.c_str(), name.c_str(), name.c_str(), name.c_str(), name.c_str()); - locals.reserve("input"); - locals.reserve("output"); - locals.reserve("current_state"); - locals.reserve("next_state"); - for (int i = 0; i < compute_graph.size(); ++i) - { - auto ref = compute_graph[i]; - int width = ref.function().width; - std::string name; - if(ref.has_sparse_attr()) - name = locals.insert(ref.sparse_attr()); - else - name = locals.insert("\\n" + std::to_string(i)); - node_names(name); - if(ref.function().name == ID($$input)) - f.printf("\tSignal<%d> %s = input.%s;\n", width, name.c_str(), input_struct[ref.function().parameters.begin()->first].c_str()); - else if(ref.function().name == ID($$state)) - f.printf("\tSignal<%d> %s = current_state.%s;\n", width, name.c_str(), state_struct[ref.function().parameters.begin()->first].c_str()); - else if(ref.function().name == ID($$buf)) - f.printf("\tSignal<%d> %s = %s;\n", width, name.c_str(), node_names[ref.arg(0).index()].c_str()); - else if(ref.function().name == ID($$cell_output)) - f.printf("\tSignal<%d> %s = %s.%s;\n", width, name.c_str(), node_names[ref.arg(0).index()].c_str(), RTLIL::unescape_id(ref.function().parameters.begin()->first).c_str()); - else if(ref.function().name == ID($$const)){ - auto c = ref.function().parameters.begin()->second; - if(c.size() <= 32){ - f.printf("\tSignal<%d> %s = $const<%d>(%#x);\n", width, name.c_str(), width, (uint32_t) c.as_int()); - }else{ - f.printf("\tSignal<%d> %s = $const<%d>({%#x", width, name.c_str(), width, (uint32_t) c.as_int()); - while(c.size() > 32){ - c = c.extract(32, c.size() - 32); - f.printf(", %#x", c.as_int()); - } - f.printf("});\n"); - } - }else if(ref.function().name == ID($$undriven)) - f.printf("\tSignal<%d> %s; //undriven\n", width, name.c_str()); - else if(ref.function().name == ID($$slice)) - f.printf("\tSignal<%d> %s = slice<%d>(%s, %d);\n", width, name.c_str(), width, node_names[ref.arg(0).index()].c_str(), ref.function().parameters.at(ID(offset)).as_int()); - else if(ref.function().name == ID($$concat)){ - f.printf("\tauto %s = concat(", name.c_str()); - for (int i = 0, end = ref.size(); i != end; ++i){ - if(i > 0) - f.printf(", "); - f.printf("%s", node_names[ref.arg(i).index()].c_str()); - } - f.printf(");\n"); - }else{ - f.printf("\t"); - if(ref.function().width > 0) - f.printf("Signal<%d>", ref.function().width); - else - f.printf("%s_Outputs", log_id(ref.function().name)); - f.printf(" %s = %s", name.c_str(), log_id(ref.function().name)); - if(ref.function().parameters.count(ID(WIDTH))){ - f.printf("<%d>", ref.function().parameters.at(ID(WIDTH)).as_int()); - } - f.printf("("); - for (int i = 0, end = ref.size(); i != end; ++i) - f.printf("%s%s", i>0?", ":"", node_names[ref.arg(i).index()].c_str()); - f.printf("); //"); - for (auto const ¶m : ref.function().parameters) - { - if (param.second.empty()) - f.printf("[%s]", log_id(param.first)); - else - f.printf("[%s=%s]", log_id(param.first), log_const(param.second)); - } - f.printf("\n"); - } - } - - for (auto const &key : compute_graph.keys()) - { - f.printf("\t%s.%s = %s;\n", state.count(key.first) > 0 ? "next_state" : "output", state_struct[key.first].c_str(), node_names[key.second].c_str()); - } - f.printf("}\n"); + log_warning("SCC:"); + for (int *i = begin; i != end; ++i) + log(" %d(%s)(%s)", *i, compute_graph[*i].function().name.c_str(), compute_graph[*i].has_sparse_attr() ? compute_graph[*i].sparse_attr().c_str() : ""); + log("\n"); + scc = true; } - - void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override - { - log_header(design, "Executing Functional C++ backend.\n"); - - size_t argidx = 1; - extra_args(f, filename, args, argidx, design); - - for (auto module : design->selected_modules()) { - log("Dumping module `%s'.\n", module->name.c_str()); - auto compute_graph = calculate_compute_graph(module); - printCxx(*f, filename, RTLIL::unescape_id(module->name), compute_graph); - } + }, /* sources_first */ true); + compute_graph.permute(perm); + if(scc) log_error("combinational loops, aborting\n"); + + // Forward $$buf + std::vector alias; + perm.clear(); + + for (int i = 0; i < compute_graph.size(); ++i) + { + auto node = compute_graph[i]; + if (node.function().name == ID($$buf) && node.arg(0).index() < i) + { + int target_index = alias[node.arg(0).index()]; + auto target_node = compute_graph[perm[target_index]]; + if(!target_node.has_sparse_attr() && node.has_sparse_attr()) + target_node.sparse_attr() = node.sparse_attr(); + alias.push_back(target_index); + } + else + { + alias.push_back(GetSize(perm)); + perm.push_back(i); + } + } + compute_graph.permute(perm, alias); + return compute_graph; + } + + void printCxx(std::ostream &stream, std::string, std::string const & name, CxxComputeGraph &compute_graph) + { + dict inputs, state; + CxxWriter f(stream); + + // Dump the compute graph + for (int i = 0; i < compute_graph.size(); ++i) + { + auto ref = compute_graph[i]; + if(ref.function().name == ID($$input)) + inputs[ref.function().parameters.begin()->first] = ref.function().width; + if(ref.function().name == ID($$state)) + state[ref.function().parameters.begin()->first] = ref.function().width; + } + f.printf("#include \"sim.h\"\n"); + CxxStruct input_struct(name + "_Inputs"); + for (auto const &input : inputs) + input_struct.insert(input.first, "Signal<" + std::to_string(input.second) + ">"); + CxxStruct output_struct(name + "_Outputs"); + for (auto const &key : compute_graph.keys()) + if(state.count(key.first) == 0) + output_struct.insert(key.first, "Signal<" + std::to_string(compute_graph[key.second].function().width) + ">"); + CxxStruct state_struct(name + "_State"); + for (auto const &state_var : state) + state_struct.insert(state_var.first, "Signal<" + std::to_string(state_var.second) + ">"); + + idict node_names; + CxxScope locals; + + input_struct.print(f); + output_struct.print(f); + state_struct.print(f); + + f.printf("void %s(%s_Inputs const &input, %s_Outputs &output, %s_State const ¤t_state, %s_State &next_state)\n{\n", name.c_str(), name.c_str(), name.c_str(), name.c_str(), name.c_str()); + locals.reserve("input"); + locals.reserve("output"); + locals.reserve("current_state"); + locals.reserve("next_state"); + for (int i = 0; i < compute_graph.size(); ++i) + { + auto ref = compute_graph[i]; + int width = ref.function().width; + std::string name; + if(ref.has_sparse_attr()) + name = locals.insert(ref.sparse_attr()); + else + name = locals.insert("\\n" + std::to_string(i)); + node_names(name); + if(ref.function().name == ID($$input)) + f.printf("\tSignal<%d> %s = input.%s;\n", width, name.c_str(), input_struct[ref.function().parameters.begin()->first].c_str()); + else if(ref.function().name == ID($$state)) + f.printf("\tSignal<%d> %s = current_state.%s;\n", width, name.c_str(), state_struct[ref.function().parameters.begin()->first].c_str()); + else if(ref.function().name == ID($$buf)) + f.printf("\tSignal<%d> %s = %s;\n", width, name.c_str(), node_names[ref.arg(0).index()].c_str()); + else if(ref.function().name == ID($$cell_output)) + f.printf("\tSignal<%d> %s = %s.%s;\n", width, name.c_str(), node_names[ref.arg(0).index()].c_str(), RTLIL::unescape_id(ref.function().parameters.begin()->first).c_str()); + else if(ref.function().name == ID($$const)){ + auto c = ref.function().parameters.begin()->second; + if(c.size() <= 32){ + f.printf("\tSignal<%d> %s = $const<%d>(%#x);\n", width, name.c_str(), width, (uint32_t) c.as_int()); + }else{ + f.printf("\tSignal<%d> %s = $const<%d>({%#x", width, name.c_str(), width, (uint32_t) c.as_int()); + while(c.size() > 32){ + c = c.extract(32, c.size() - 32); + f.printf(", %#x", c.as_int()); + } + f.printf("});\n"); + } + }else if(ref.function().name == ID($$undriven)) + f.printf("\tSignal<%d> %s; //undriven\n", width, name.c_str()); + else if(ref.function().name == ID($$slice)) + f.printf("\tSignal<%d> %s = slice<%d>(%s, %d);\n", width, name.c_str(), width, node_names[ref.arg(0).index()].c_str(), ref.function().parameters.at(ID(offset)).as_int()); + else if(ref.function().name == ID($$concat)){ + f.printf("\tauto %s = concat(", name.c_str()); + for (int i = 0, end = ref.size(); i != end; ++i){ + if(i > 0) + f.printf(", "); + f.printf("%s", node_names[ref.arg(i).index()].c_str()); + } + f.printf(");\n"); + }else{ + f.printf("\t"); + if(ref.function().width > 0) + f.printf("Signal<%d>", ref.function().width); + else + f.printf("%s_Outputs", log_id(ref.function().name)); + f.printf(" %s = %s", name.c_str(), log_id(ref.function().name)); + if(ref.function().parameters.count(ID(WIDTH))){ + f.printf("<%d>", ref.function().parameters.at(ID(WIDTH)).as_int()); + } + f.printf("("); + for (int i = 0, end = ref.size(); i != end; ++i) + f.printf("%s%s", i>0?", ":"", node_names[ref.arg(i).index()].c_str()); + f.printf("); //"); + for (auto const ¶m : ref.function().parameters) + { + if (param.second.empty()) + f.printf("[%s]", log_id(param.first)); + else + f.printf("[%s=%s]", log_id(param.first), log_const(param.second)); + } + f.printf("\n"); } + } + + for (auto const &key : compute_graph.keys()) + { + f.printf("\t%s.%s = %s;\n", state.count(key.first) > 0 ? "next_state" : "output", state_struct[key.first].c_str(), node_names[key.second].c_str()); + } + f.printf("}\n"); + } + + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing Functional C++ backend.\n"); + + size_t argidx = 1; + extra_args(f, filename, args, argidx, design); + + for (auto module : design->selected_modules()) { + log("Dumping module `%s'.\n", module->name.c_str()); + auto compute_graph = calculate_compute_graph(module); + printCxx(*f, filename, RTLIL::unescape_id(module->name), compute_graph); + } + } } FunctionalCxxBackend; PRIVATE_NAMESPACE_END diff --git a/backends/functional/cxx_runtime/sim.h b/backends/functional/cxx_runtime/sim.h index 4e7d9b60142..829266da0e6 100644 --- a/backends/functional/cxx_runtime/sim.h +++ b/backends/functional/cxx_runtime/sim.h @@ -21,6 +21,8 @@ #define SIM_H #include +#include +#include template using Signal = std::array; diff --git a/flake.nix b/flake.nix index 1e202324647..63c1e13720d 100644 --- a/flake.nix +++ b/flake.nix @@ -37,11 +37,36 @@ maintainers = with maintainers; [ ]; }; }; + vcdiff = pkgs.stdenv.mkDerivation { + pname = "vcdiff"; + version = "1.1"; + + src = pkgs.fetchFromGitHub { + owner = "orsonmmz"; + repo = "vcdiff"; + rev = "master"; + hash = "sha256-jTuok3TjuGW7+ATc11R9osKDPxbhRtuEbM8tRE4+AAI="; + }; + + buildInputs = [ pkgs.gcc ]; + + installPhase = '' + mkdir -p $out/bin + cp vcdiff $out/bin/ + ''; + + meta = with pkgs.lib; { + description = "The ultimate VCD files comparator"; + license = licenses.gpl3; + maintainers = with maintainers; [ orsonmmz ]; + }; + }; in { packages.default = yosys; defaultPackage = yosys; + packages.vcdiff = vcdiff; devShell = pkgs.mkShell { - buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git gtest abc-verifier ]; + buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git gtest abc-verifier gtkwave vcdiff ]; }; } ); diff --git a/tests/functional/.gitignore b/tests/functional/.gitignore new file mode 100644 index 00000000000..06af41869c9 --- /dev/null +++ b/tests/functional/.gitignore @@ -0,0 +1,5 @@ +and_cxxrtl.cc +and_functional_cxx.cc +vcd_harness +cxxrtl.vcd +functional_cxx.vcd \ No newline at end of file diff --git a/tests/functional/run-test.sh b/tests/functional/run-test.sh new file mode 100755 index 00000000000..be4bef9c32b --- /dev/null +++ b/tests/functional/run-test.sh @@ -0,0 +1,7 @@ +#!/bin/bash + +set -ex + +../../yosys -p "read_verilog verilog/and.v; write_cxxrtl and_cxxrtl.cc; write_functional_cxx and_functional_cxx.cc" +${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cpp -I ../../backends/functional/cxx_runtime/ -I ../../backends/cxxrtl/runtime/ -o vcd_harness +./vcd_harness diff --git a/tests/functional/vcd_harness.cpp b/tests/functional/vcd_harness.cpp new file mode 100644 index 00000000000..dc3ad3b9c2b --- /dev/null +++ b/tests/functional/vcd_harness.cpp @@ -0,0 +1,140 @@ +#include +#include +#include +#include + +#include + +#include "and_cxxrtl.cc" +#include "and_functional_cxx.cc" + +struct DumpHeader { + std::ofstream &ofs; + DumpHeader(std::ofstream &ofs) : ofs(ofs) {} + template + void operator()(const char *name, Signal value) { + ofs << "$var wire " << n << " " << name[0] << " " << name << " $end\n"; + } +}; + +struct Dump { + std::ofstream &ofs; + Dump(std::ofstream &ofs) : ofs(ofs) {} + template + void operator()(const char *name, Signal value) { + // Bit + if (n == 1) { + ofs << (value[0] ? '1' : '0'); + ofs << name[0] << "\n"; + return; + } + // vector (multi-bit) signals + ofs << "b"; + for (size_t i = n; i-- > 0;) + ofs << (value[i] ? '1' : '0'); + ofs << " " << name[0] << "\n"; + } +}; + +int main(int argc, char **argv) +{ + constexpr int steps = 10; + constexpr int number_timescale = 1; + const std::string units_timescale = "us"; + Adder_Inputs inputs; + Adder_Outputs outputs; + Adder_State state; + Adder_State next_state; + + std::ofstream vcd_file("functional_cxx.vcd"); + + vcd_file << "$timescale " << number_timescale << " " << units_timescale << " $end\n"; //$scope module logic $end\n"; + { + DumpHeader d(vcd_file); + inputs.dump(d); + outputs.dump(d); + // vcd_file << "$scope module state $end\n"; + state.dump(d); + } + vcd_file << "$enddefinitions $end\n$dumpvars\n"; + + cxxrtl_design::p_Adder top; + + // debug_items maps the hierarchical names of signals and memories in the design + // to a cxxrtl_object (a value, a wire, or a memory) + cxxrtl::debug_items all_debug_items; + cxxrtl::debug_scope debug_scope; + // Load the debug items of the top down the whole design hierarchy + top.debug_info(&all_debug_items, nullptr, ""); + + // vcd_writer is the CXXRTL object that's responsible for creating a string with + // the VCD file contents. + cxxrtl::vcd_writer vcd; + vcd.timescale(number_timescale, units_timescale); + + // Here we tell the vcd writer to dump all the signals of the design, except for the + // memories, to the VCD file. + // + // It's not necessary to load all debug objects to the VCD. There is, for example, + // a vcd.add(, )) method which allows creating your custom filter to decide + // what to add and what not. + vcd.add_without_memories(all_debug_items); + + std::ofstream waves("cxxrtl.vcd"); + + top.p_a.set(false); + top.p_b.set(false); + top.step(); + + // We need to manually tell the VCD writer when to sample and write out the traced items. + // This is only a slight inconvenience and allows for complete flexibility. + // E.g. you could only start waveform tracing when an internal signal has reached some specific + // value etc. + vcd.sample(0); + vcd_file << "#0\n"; + inputs.a = $const<1>(false); + inputs.b = $const<1>(false); + { + Dump d(vcd_file); + inputs.dump(d); + outputs.dump(d); + state.dump(d); + } + + // Initialize random number generator + std::random_device rd; + std::mt19937 gen(rd()); + std::bernoulli_distribution dist(0.5); // 50% chance for true or false + + for (int step = 0; step < steps; ++step) { + const bool a_value = dist(gen); + const bool b_value = dist(gen); + + // cxxrtl + top.p_a.set(a_value); + top.p_b.set(b_value); + top.step(); + vcd.sample(step + 1); + + waves << vcd.buffer; + vcd.buffer.clear(); + + // Functional backend cxx + vcd_file << "#" << (step + 1) << "\n"; + inputs.a = $const<1>(a_value); + inputs.b = $const<1>(b_value); + Adder(inputs, outputs, state, next_state); + { + Dump d(vcd_file); + inputs.dump(d); + outputs.dump(d); + state.dump(d); + } + state = next_state; + } + + vcd_file.close(); + waves.close(); + + return 0; +} diff --git a/tests/functional/verilog/and.v b/tests/functional/verilog/and.v new file mode 100644 index 00000000000..11cf481e96b --- /dev/null +++ b/tests/functional/verilog/and.v @@ -0,0 +1,9 @@ +module Adder( + input a, + input b, + output sum + ); + // Perform addition + assign sum = a + b; + +endmodule From ad63997829ed5875ab222081e4c7f4c7b84010e3 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Sat, 25 May 2024 10:47:56 +0200 Subject: [PATCH 16/51] Check vcdiff output --- tests/functional/run-test.sh | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/tests/functional/run-test.sh b/tests/functional/run-test.sh index be4bef9c32b..3e9de003fc2 100755 --- a/tests/functional/run-test.sh +++ b/tests/functional/run-test.sh @@ -4,4 +4,17 @@ set -ex ../../yosys -p "read_verilog verilog/and.v; write_cxxrtl and_cxxrtl.cc; write_functional_cxx and_functional_cxx.cc" ${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cpp -I ../../backends/functional/cxx_runtime/ -I ../../backends/cxxrtl/runtime/ -o vcd_harness +# Generate VCD files cxxrtl.vcd and functional_cxx.vcd ./vcd_harness +# Run vcdiff and capture the output +output=$(vcdiff cxxrtl.vcd functional_cxx.vcd) + +# Check if there is any output +if [ -n "$output" ]; then + echo "Differences detected:" + echo "$output" + exit 1 +else + echo "No differences detected." + exit 0 +fi From 6644127c6d301571c05961f882efa959e5dc5e0c Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Sat, 25 May 2024 11:35:31 +0200 Subject: [PATCH 17/51] Test all files in verilog dir --- flake.nix | 2 +- tests/functional/.gitignore | 4 +- tests/functional/coverage_report/amber.png | Bin 0 -> 141 bytes tests/functional/coverage_report/emerald.png | Bin 0 -> 141 bytes .../functional/and_cxxrtl.cc.func-sort-c.html | 100 + .../functional/and_cxxrtl.cc.func.html | 100 + .../functional/and_cxxrtl.cc.gcov.html | 161 ++ .../and_functional_cxx.cc.func-sort-c.html | 84 + .../and_functional_cxx.cc.func.html | 84 + .../and_functional_cxx.cc.gcov.html | 108 + .../functional/index-sort-f.html | 113 + .../functional/index-sort-l.html | 113 + .../coverage_report/functional/index.html | 113 + .../vcd_harness.cpp.func-sort-c.html | 84 + .../functional/vcd_harness.cpp.func.html | 84 + .../functional/vcd_harness.cpp.gcov.html | 216 ++ tests/functional/coverage_report/gcov.css | 519 ++++ tests/functional/coverage_report/glass.png | Bin 0 -> 167 bytes .../runtime/cxxrtl/cxxrtl.h.func-sort-c.html | 108 + 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.../and_functional_cxx.cc.gcov.html | 108 + .../tests/functional/index-sort-f.html | 113 + .../tests/functional/index-sort-l.html | 113 + .../my_yosys/tests/functional/index.html | 113 + .../vcd_harness.cpp.func-sort-c.html | 84 + .../functional/vcd_harness.cpp.func.html | 84 + .../functional/vcd_harness.cpp.gcov.html | 216 ++ .../coverage_report/index-sort-f.html | 93 + .../coverage_report/index-sort-l.html | 93 + tests/functional/coverage_report/index.html | 93 + .../include/bits/string_fortified.h.gcov.html | 54 + tests/functional/coverage_report/ruby.png | Bin 0 -> 141 bytes tests/functional/coverage_report/snow.png | Bin 0 -> 141 bytes tests/functional/coverage_report/updown.png | Bin 0 -> 117 bytes .../coverage_report/vcd_harness.info | 0 tests/functional/generate_coverage.sh | 19 + tests/functional/run-test.sh | 40 +- tests/functional/vcd_harness.cpp | 16 +- tests/functional/verilog/add.v | 9 + tests/functional/verilog/and.v | 14 +- tests/functional/verilog/my_module_div.v | 9 + tests/functional/verilog/my_module_eqx.v | 9 + tests/functional/verilog/my_module_ge.v | 9 + tests/functional/verilog/my_module_gt.v | 9 + tests/functional/verilog/my_module_le.v | 9 + .../functional/verilog/my_module_logic_and.v | 9 + tests/functional/verilog/my_module_logic_or.v | 9 + tests/functional/verilog/my_module_lt.v | 9 + tests/functional/verilog/my_module_mod.v | 9 + tests/functional/verilog/my_module_mul.v | 9 + tests/functional/verilog/my_module_ne.v | 9 + tests/functional/verilog/my_module_nex.v | 9 + tests/functional/verilog/my_module_or.v | 9 + tests/functional/verilog/my_module_pow.v | 9 + tests/functional/verilog/my_module_shl.v | 9 + tests/functional/verilog/my_module_shr.v | 9 + tests/functional/verilog/my_module_sshl.v | 9 + tests/functional/verilog/my_module_sshr.v | 9 + tests/functional/verilog/my_module_sub.v | 9 + tests/functional/verilog/my_module_xnor.v | 9 + tests/functional/verilog/my_module_xor.v | 9 + 79 files changed, 8029 insertions(+), 33 deletions(-) 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tests/functional/coverage_report/home/roland/my_yosys/tests/functional/and_functional_cxx.cc.gcov.html create mode 100644 tests/functional/coverage_report/home/roland/my_yosys/tests/functional/index-sort-f.html create mode 100644 tests/functional/coverage_report/home/roland/my_yosys/tests/functional/index-sort-l.html create mode 100644 tests/functional/coverage_report/home/roland/my_yosys/tests/functional/index.html create mode 100644 tests/functional/coverage_report/home/roland/my_yosys/tests/functional/vcd_harness.cpp.func-sort-c.html create mode 100644 tests/functional/coverage_report/home/roland/my_yosys/tests/functional/vcd_harness.cpp.func.html create mode 100644 tests/functional/coverage_report/home/roland/my_yosys/tests/functional/vcd_harness.cpp.gcov.html create mode 100644 tests/functional/coverage_report/index-sort-f.html create mode 100644 tests/functional/coverage_report/index-sort-l.html create mode 100644 tests/functional/coverage_report/index.html create mode 100644 tests/functional/coverage_report/nix/store/B0S2LKF593R3585038WS4JD3LYLF2WDX-glibc-2.38-44-dev/include/bits/string_fortified.h.gcov.html create mode 100644 tests/functional/coverage_report/ruby.png create mode 100644 tests/functional/coverage_report/snow.png create mode 100644 tests/functional/coverage_report/updown.png create mode 100644 tests/functional/coverage_report/vcd_harness.info create mode 100755 tests/functional/generate_coverage.sh create mode 100644 tests/functional/verilog/add.v create mode 100755 tests/functional/verilog/my_module_div.v create mode 100755 tests/functional/verilog/my_module_eqx.v create mode 100755 tests/functional/verilog/my_module_ge.v create mode 100755 tests/functional/verilog/my_module_gt.v create mode 100755 tests/functional/verilog/my_module_le.v create mode 100755 tests/functional/verilog/my_module_logic_and.v create mode 100755 tests/functional/verilog/my_module_logic_or.v create mode 100755 tests/functional/verilog/my_module_lt.v create mode 100755 tests/functional/verilog/my_module_mod.v create mode 100755 tests/functional/verilog/my_module_mul.v create mode 100755 tests/functional/verilog/my_module_ne.v create mode 100755 tests/functional/verilog/my_module_nex.v create mode 100755 tests/functional/verilog/my_module_or.v create mode 100755 tests/functional/verilog/my_module_pow.v create mode 100755 tests/functional/verilog/my_module_shl.v create mode 100755 tests/functional/verilog/my_module_shr.v create mode 100755 tests/functional/verilog/my_module_sshl.v create mode 100755 tests/functional/verilog/my_module_sshr.v create mode 100755 tests/functional/verilog/my_module_sub.v create mode 100755 tests/functional/verilog/my_module_xnor.v create mode 100755 tests/functional/verilog/my_module_xor.v diff --git a/flake.nix b/flake.nix index 63c1e13720d..6ed167dab80 100644 --- a/flake.nix +++ b/flake.nix @@ -66,7 +66,7 @@ defaultPackage = yosys; packages.vcdiff = vcdiff; devShell = pkgs.mkShell { - buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git gtest abc-verifier gtkwave vcdiff ]; + buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git gtest abc-verifier gtkwave vcdiff lcov ]; }; } ); diff --git a/tests/functional/.gitignore b/tests/functional/.gitignore index 06af41869c9..6ee14e70604 100644 --- a/tests/functional/.gitignore +++ b/tests/functional/.gitignore @@ -1,5 +1,5 @@ -and_cxxrtl.cc -and_functional_cxx.cc +my_module_cxxrtl.cc +my_module_functional_cxx.cc vcd_harness cxxrtl.vcd functional_cxx.vcd \ No newline at end of file diff --git a/tests/functional/coverage_report/amber.png b/tests/functional/coverage_report/amber.png new file mode 100644 index 0000000000000000000000000000000000000000..2cab170d8359081983a4e343848dfe06bc490f12 GIT binary patch literal 141 zcmeAS@N?(olHy`uVBq!ia0vp^j3CU&3?x-=hn)ga>?NMQuI!iC1^G2tW}LqE04T&+ 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LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - functional - and_cxxrtl.cc (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:222975.9 %
Date:1980-01-01 00:00:00Functions:5771.4 %
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN13cxxrtl_design7p_Adder10debug_evalEv0
cxxrtl_design_create0
_ZN13cxxrtl_design7p_Adder10debug_infoEPN6cxxrtl11debug_itemsEPNS1_12debug_scopesENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEOSt3mapISB_NS1_8metadataESt4lessISB_ESaISt4pairIKSB_SD_EEE3
_ZN13cxxrtl_design7p_Adder5resetEv3
_ZN13cxxrtl_design7p_AdderC2Ev3
_ZN13cxxrtl_design7p_Adder4evalEPN6cxxrtl9performerE33
_ZN13cxxrtl_design7p_Adder6commitEv33
+
+
+ + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/functional/and_cxxrtl.cc.func.html b/tests/functional/coverage_report/functional/and_cxxrtl.cc.func.html new file mode 100644 index 00000000000..c7717a2dc84 --- /dev/null +++ b/tests/functional/coverage_report/functional/and_cxxrtl.cc.func.html @@ -0,0 +1,100 @@ + + + + + + + LCOV - vcd_harness.info - functional/and_cxxrtl.cc - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - functional - and_cxxrtl.cc (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:222975.9 %
Date:1980-01-01 00:00:00Functions:5771.4 %
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN13cxxrtl_design7p_Adder10debug_evalEv0
_ZN13cxxrtl_design7p_Adder10debug_infoEPN6cxxrtl11debug_itemsEPNS1_12debug_scopesENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEOSt3mapISB_NS1_8metadataESt4lessISB_ESaISt4pairIKSB_SD_EEE3
_ZN13cxxrtl_design7p_Adder4evalEPN6cxxrtl9performerE33
_ZN13cxxrtl_design7p_Adder5resetEv3
_ZN13cxxrtl_design7p_Adder6commitEv33
_ZN13cxxrtl_design7p_AdderC2Ev3
cxxrtl_design_create0
+
+
+ + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/functional/and_cxxrtl.cc.gcov.html b/tests/functional/coverage_report/functional/and_cxxrtl.cc.gcov.html new file mode 100644 index 00000000000..796a2e71920 --- /dev/null +++ b/tests/functional/coverage_report/functional/and_cxxrtl.cc.gcov.html @@ -0,0 +1,161 @@ + + + + + + + LCOV - vcd_harness.info - functional/and_cxxrtl.cc + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - functional - and_cxxrtl.cc (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:222975.9 %
Date:1980-01-01 00:00:00Functions:5771.4 %
+
+ + + + + + + + +

+
          Line data    Source code
+
+       1             : #include <cxxrtl/cxxrtl.h>
+       2             : 
+       3             : #if defined(CXXRTL_INCLUDE_CAPI_IMPL) || \
+       4             :     defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)
+       5             : #include <cxxrtl/capi/cxxrtl_capi.cc>
+       6             : #endif
+       7             : 
+       8             : #if defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)
+       9             : #include <cxxrtl/capi/cxxrtl_capi_vcd.cc>
+      10             : #endif
+      11             : 
+      12             : using namespace cxxrtl_yosys;
+      13             : 
+      14             : namespace cxxrtl_design {
+      15             : 
+      16             : // \top: 1
+      17             : // \src: verilog/and.v:1.1-9.10
+      18           3 : struct p_Adder : public module {
+      19             :         // \src: verilog/and.v:4.14-4.17
+      20             :         /*output*/ value<1> p_sum;
+      21             :         // \src: verilog/and.v:3.14-3.15
+      22             :         /*input*/ value<1> p_b;
+      23             :         // \src: verilog/and.v:2.14-2.15
+      24             :         /*input*/ value<1> p_a;
+      25             :         p_Adder(interior) {}
+      26           3 :         p_Adder() {
+      27           3 :                 reset();
+      28           3 :         };
+      29             : 
+      30             :         void reset() override;
+      31             : 
+      32             :         bool eval(performer *performer = nullptr) override;
+      33             : 
+      34             :         template<class ObserverT>
+      35             :         bool commit(ObserverT &observer) {
+      36          33 :                 bool changed = false;
+      37             :                 return changed;
+      38             :         }
+      39             : 
+      40          33 :         bool commit() override {
+      41          33 :                 observer observer;
+      42          33 :                 return commit<>(observer);
+      43             :         }
+      44             : 
+      45             :         void debug_eval();
+      46             : 
+      47             :         void debug_info(debug_items *items, debug_scopes *scopes, std::string path, metadata_map &&cell_attrs = {}) override;
+      48             : }; // struct p_Adder
+      49             : 
+      50           3 : void p_Adder::reset() {
+      51           3 : }
+      52             : 
+      53          33 : bool p_Adder::eval(performer *performer) {
+      54          33 :         bool converged = true;
+      55             :         // \src: verilog/and.v:7.17-7.22
+      56             :         // cell $add$verilog/and.v:7$1
+      57          33 :         p_sum = add_uu<1>(p_a, p_b);
+      58          33 :         return converged;
+      59             : }
+      60             : 
+      61           0 : void p_Adder::debug_eval() {
+      62           0 : }
+      63             : 
+      64             : CXXRTL_EXTREMELY_COLD
+      65           3 : void p_Adder::debug_info(debug_items *items, debug_scopes *scopes, std::string path, metadata_map &&cell_attrs) {
+      66           3 :         assert(path.empty() || path[path.size() - 1] == ' ');
+      67           3 :         if (scopes) {
+      68           0 :                 scopes->add(path.empty() ? path : path.substr(0, path.size() - 1), "Adder", metadata_map({
+      69           0 :                         { "top", UINT64_C(1) },
+      70             :                         { "src", "verilog/and.v:1.1-9.10" },
+      71           0 :                 }), std::move(cell_attrs));
+      72             :         }
+      73           3 :         if (items) {
+      74           3 :                 items->add(path, "sum", "src\000sverilog/and.v:4.14-4.17\000", p_sum, 0, debug_item::OUTPUT|debug_item::DRIVEN_COMB);
+      75           3 :                 items->add(path, "b", "src\000sverilog/and.v:3.14-3.15\000", p_b, 0, debug_item::INPUT|debug_item::UNDRIVEN);
+      76           3 :                 items->add(path, "a", "src\000sverilog/and.v:2.14-2.15\000", p_a, 0, debug_item::INPUT|debug_item::UNDRIVEN);
+      77             :         }
+      78           3 : }
+      79             : 
+      80             : } // namespace cxxrtl_design
+      81             : 
+      82             : extern "C"
+      83           0 : cxxrtl_toplevel cxxrtl_design_create() {
+      84           0 :         return new _cxxrtl_toplevel { std::unique_ptr<cxxrtl_design::p_Adder>(new cxxrtl_design::p_Adder) };
+      85             : }
+
+
+
+ + + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/functional/and_functional_cxx.cc.func-sort-c.html b/tests/functional/coverage_report/functional/and_functional_cxx.cc.func-sort-c.html new file mode 100644 index 00000000000..5c1ad8cc617 --- /dev/null +++ b/tests/functional/coverage_report/functional/and_functional_cxx.cc.func-sort-c.html @@ -0,0 +1,84 @@ + + + + + + + LCOV - vcd_harness.info - functional/and_functional_cxx.cc - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - functional - and_functional_cxx.cc (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:1313100.0 %
Date:1980-01-01 00:00:00Functions:33100.0 %
+
+ +
+ + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN12Adder_Inputs4dumpI10DumpHeaderEEvRT_3
_Z5AdderRK12Adder_InputsR13Adder_OutputsRK11Adder_StateRS4_30
_ZN12Adder_Inputs4dumpI4DumpEEvRT_33
+
+
+ + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/functional/and_functional_cxx.cc.func.html b/tests/functional/coverage_report/functional/and_functional_cxx.cc.func.html new file mode 100644 index 00000000000..bd54f13143e --- /dev/null +++ b/tests/functional/coverage_report/functional/and_functional_cxx.cc.func.html @@ -0,0 +1,84 @@ + + + + + + + LCOV - vcd_harness.info - functional/and_functional_cxx.cc - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - functional - and_functional_cxx.cc (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:1313100.0 %
Date:1980-01-01 00:00:00Functions:33100.0 %
+
+ +
+ + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_Z5AdderRK12Adder_InputsR13Adder_OutputsRK11Adder_StateRS4_30
_ZN12Adder_Inputs4dumpI10DumpHeaderEEvRT_3
_ZN12Adder_Inputs4dumpI4DumpEEvRT_33
+
+
+ + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/functional/and_functional_cxx.cc.gcov.html b/tests/functional/coverage_report/functional/and_functional_cxx.cc.gcov.html new file mode 100644 index 00000000000..46ae8931131 --- /dev/null +++ b/tests/functional/coverage_report/functional/and_functional_cxx.cc.gcov.html @@ -0,0 +1,108 @@ + + + + + + + LCOV - vcd_harness.info - functional/and_functional_cxx.cc + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - functional - and_functional_cxx.cc (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:1313100.0 %
Date:1980-01-01 00:00:00Functions:33100.0 %
+
+ + + + + + + + +

+
          Line data    Source code
+
+       1             : #include "sim.h"
+       2             : struct Adder_Inputs {
+       3             :         Signal<1> b;
+       4             :         Signal<1> a;
+       5             : 
+       6          36 :         template <typename T> void dump(T &out) {
+       7          36 :                 out("b", b);
+       8          36 :                 out("a", a);
+       9          36 :         }
+      10             : };
+      11             : 
+      12             : struct Adder_Outputs {
+      13             :         Signal<1> sum;
+      14             : 
+      15          36 :         template <typename T> void dump(T &out) {
+      16          36 :                 out("sum", sum);
+      17          36 :         }
+      18             : };
+      19             : 
+      20             : struct Adder_State {
+      21             : 
+      22             :         template <typename T> void dump(T &out) {
+      23             :         }
+      24             : };
+      25             : 
+      26          30 : void Adder(Adder_Inputs const &input, Adder_Outputs &output, Adder_State const &current_state, Adder_State &next_state)
+      27             : {
+      28          30 :         Signal<1> b = input.b;
+      29          30 :         Signal<1> a = input.a;
+      30          30 :         Signal<1> $add$verilog_and_v_7$1$_Y = $add(a, b); //
+      31          30 :         output.sum = $add$verilog_and_v_7$1$_Y;
+      32          30 : }
+
+
+
+ + + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/functional/index-sort-f.html b/tests/functional/coverage_report/functional/index-sort-f.html new file mode 100644 index 00000000000..c6f3150f801 --- /dev/null +++ b/tests/functional/coverage_report/functional/index-sort-f.html @@ -0,0 +1,113 @@ + + + + + + + LCOV - vcd_harness.info - functional + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - functionalHitTotalCoverage
Test:vcd_harness.infoLines:10511293.8 %
Date:1980-01-01 00:00:00Functions:111384.6 %
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
and_cxxrtl.cc +
75.9%75.9%
+ 		75.9 %22 / 2971.4 %5 / 7
and_functional_cxx.cc +
100.0%
+ 		100.0 %13 / 13100.0 %3 / 3
vcd_harness.cpp +
100.0%
+ 		100.0 %70 / 70100.0 %3 / 3
+
+
+ + + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/functional/index-sort-l.html b/tests/functional/coverage_report/functional/index-sort-l.html new file mode 100644 index 00000000000..85e33c02ae9 --- /dev/null +++ b/tests/functional/coverage_report/functional/index-sort-l.html @@ -0,0 +1,113 @@ + + + + + + + LCOV - vcd_harness.info - functional + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - functionalHitTotalCoverage
Test:vcd_harness.infoLines:10511293.8 %
Date:1980-01-01 00:00:00Functions:111384.6 %
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
and_cxxrtl.cc +
75.9%75.9%
+ 		75.9 %22 / 2971.4 %5 / 7
and_functional_cxx.cc +
100.0%
+ 		100.0 %13 / 13100.0 %3 / 3
vcd_harness.cpp +
100.0%
+ 		100.0 %70 / 70100.0 %3 / 3
+
+
+ + + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/functional/index.html b/tests/functional/coverage_report/functional/index.html new file mode 100644 index 00000000000..3b31f9d7e6e --- /dev/null +++ b/tests/functional/coverage_report/functional/index.html @@ -0,0 +1,113 @@ + + + + + + + LCOV - vcd_harness.info - functional + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - functionalHitTotalCoverage
Test:vcd_harness.infoLines:10511293.8 %
Date:1980-01-01 00:00:00Functions:111384.6 %
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
and_cxxrtl.cc +
75.9%75.9%
+ 		75.9 %22 / 2971.4 %5 / 7
and_functional_cxx.cc +
100.0%
+ 		100.0 %13 / 13100.0 %3 / 3
vcd_harness.cpp +
100.0%
+ 		100.0 %70 / 70100.0 %3 / 3
+
+
+ + + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/functional/vcd_harness.cpp.func-sort-c.html b/tests/functional/coverage_report/functional/vcd_harness.cpp.func-sort-c.html new file mode 100644 index 00000000000..36a518367b0 --- /dev/null +++ b/tests/functional/coverage_report/functional/vcd_harness.cpp.func-sort-c.html @@ -0,0 +1,84 @@ + + + + + + + LCOV - vcd_harness.info - functional/vcd_harness.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - functional - vcd_harness.cpp (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:7070100.0 %
Date:1980-01-01 00:00:00Functions:33100.0 %
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+ +
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Function Name Sort by function nameHit count Sort by hit count
main3
_ZN10DumpHeaderclILm1EEEvPKcSt5arrayIbXT_EE9
_ZN4DumpclILm1EEEvPKcSt5arrayIbXT_EE99
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+ + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/functional/vcd_harness.cpp.func.html b/tests/functional/coverage_report/functional/vcd_harness.cpp.func.html new file mode 100644 index 00000000000..351dd96a848 --- /dev/null +++ b/tests/functional/coverage_report/functional/vcd_harness.cpp.func.html @@ -0,0 +1,84 @@ + + + + + + + LCOV - vcd_harness.info - functional/vcd_harness.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - functional - vcd_harness.cpp (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:7070100.0 %
Date:1980-01-01 00:00:00Functions:33100.0 %
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+ +
+ + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN10DumpHeaderclILm1EEEvPKcSt5arrayIbXT_EE9
_ZN4DumpclILm1EEEvPKcSt5arrayIbXT_EE99
main3
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+
+ + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/functional/vcd_harness.cpp.gcov.html b/tests/functional/coverage_report/functional/vcd_harness.cpp.gcov.html new file mode 100644 index 00000000000..d5c0afbc10c --- /dev/null +++ b/tests/functional/coverage_report/functional/vcd_harness.cpp.gcov.html @@ -0,0 +1,216 @@ + + + + + + + LCOV - vcd_harness.info - functional/vcd_harness.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - functional - vcd_harness.cpp (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:7070100.0 %
Date:1980-01-01 00:00:00Functions:33100.0 %
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+ + + + + + + + +

+
          Line data    Source code
+
+       1             : #include <cstdio>
+       2             : #include <iostream>
+       3             : #include <fstream>
+       4             : #include <random>
+       5             : 
+       6             : #include <cxxrtl/cxxrtl_vcd.h>
+       7             : 
+       8             : #include "and_cxxrtl.cc"
+       9             : #include "and_functional_cxx.cc"
+      10             : 
+      11             : struct DumpHeader {
+      12             :     std::ofstream &ofs;
+      13           3 :     DumpHeader(std::ofstream &ofs) : ofs(ofs) {}
+      14             :     template <size_t n>
+      15           9 :     void operator()(const char *name, Signal<n> value) {
+      16           9 :         ofs << "$var wire " << n << " " << name[0] << " " << name << " $end\n";
+      17           9 :     }
+      18             : };
+      19             : 
+      20             : struct Dump {
+      21             :     std::ofstream &ofs;
+      22          33 :     Dump(std::ofstream &ofs) : ofs(ofs) {}
+      23             :     template <size_t n>
+      24          99 :     void operator()(const char *name, Signal<n> value) {
+      25             :         // Bit
+      26             :         if (n == 1) {
+      27         156 :             ofs << (value[0] ? '1' : '0');
+      28          99 :             ofs << name[0] << "\n";
+      29             :             return;
+      30             :         }
+      31             :         // vector (multi-bit) signals
+      32             :         ofs << "b";
+      33             :         for (size_t i = n; i-- > 0;)
+      34             :             ofs << (value[i] ? '1' : '0');
+      35             :         ofs << " " << name[0] << "\n";
+      36             :     }
+      37             : };
+      38             : 
+      39           3 : int main(int argc, char **argv)
+      40             : {
+      41           3 :     constexpr int steps = 10;
+      42           3 :     constexpr int number_timescale = 1;
+      43           3 :     const std::string units_timescale = "us";
+      44           3 :     Adder_Inputs inputs;
+      45           3 :     Adder_Outputs outputs;
+      46           3 :     Adder_State state;
+      47           3 :     Adder_State next_state;
+      48             : 
+      49           3 :     std::ofstream vcd_file("functional_cxx.vcd");
+      50             : 
+      51           3 :     vcd_file << "$timescale " << number_timescale << " " << units_timescale << " $end\n"; //$scope module logic $end\n";
+      52           3 :     {
+      53           3 :         DumpHeader d(vcd_file);
+      54           3 :         inputs.dump(d);
+      55           3 :         outputs.dump(d);
+      56             :         // vcd_file << "$scope module state $end\n";
+      57           3 :         state.dump(d);
+      58             :     }
+      59           3 :     vcd_file << "$enddefinitions $end\n$dumpvars\n";
+      60             : 
+      61           3 :     cxxrtl_design::p_Adder top;
+      62             : 
+      63             :     // debug_items maps the hierarchical names of signals and memories in the design
+      64             :     // to a cxxrtl_object (a value, a wire, or a memory)
+      65           3 :     cxxrtl::debug_items all_debug_items;
+      66           3 :     cxxrtl::debug_scope debug_scope;
+      67             :     // Load the debug items of the top down the whole design hierarchy
+      68           6 :     top.debug_info(&all_debug_items, nullptr, "");
+      69             : 
+      70             :     // vcd_writer is the CXXRTL object that's responsible for creating a string with
+      71             :     // the VCD file contents.
+      72           3 :     cxxrtl::vcd_writer vcd;
+      73           3 :     vcd.timescale(number_timescale, units_timescale);
+      74             : 
+      75             :     // Here we tell the vcd writer to dump all the signals of the design, except for the
+      76             :     // memories, to the VCD file.
+      77             :     //
+      78             :     // It's not necessary to load all debug objects to the VCD. There is, for example,
+      79             :     // a  vcd.add(<debug items>, <filter>)) method which allows creating your custom filter to decide
+      80             :     // what to add and what not.
+      81           3 :     vcd.add_without_memories(all_debug_items);
+      82             : 
+      83           3 :     std::ofstream waves("cxxrtl.vcd");
+      84             : 
+      85           3 :     top.p_a.set<bool>(false);
+      86           3 :     top.p_b.set<bool>(false);
+      87           3 :     top.step();
+      88             : 
+      89             :     // We need to manually tell the VCD writer when to sample and write out the traced items.
+      90             :     // This is only a slight inconvenience and allows for complete flexibility.
+      91             :     // E.g. you could only start waveform tracing when an internal signal has reached some specific
+      92             :     // value etc.
+      93           3 :     vcd.sample(0);
+      94           3 :     vcd_file << "#0\n";
+      95           3 :     inputs.a = $const<1>(false);
+      96           3 :     inputs.b = $const<1>(false);
+      97           3 :     {
+      98           3 :         Dump d(vcd_file);
+      99           3 :         inputs.dump(d);
+     100           3 :         outputs.dump(d);
+     101           3 :         state.dump(d);
+     102             :     }
+     103             : 
+     104             :     // Initialize random number generator
+     105           3 :     std::random_device rd;
+     106           3 :     std::mt19937 gen(rd());
+     107           3 :     std::bernoulli_distribution dist(0.5); // 50% chance for true or false
+     108             :     
+     109          33 :     for (int step = 0; step < steps; ++step) {
+     110          30 :       const bool a_value = dist(gen);
+     111          30 :       const bool b_value = dist(gen);
+     112             : 
+     113             :         // cxxrtl
+     114          30 :         top.p_a.set<bool>(a_value);
+     115          30 :         top.p_b.set<bool>(b_value);
+     116          30 :         top.step();
+     117          30 :         vcd.sample(step + 1);
+     118             : 
+     119          30 :         waves << vcd.buffer;
+     120          30 :         vcd.buffer.clear();
+     121             : 
+     122             :         // Functional backend cxx
+     123          30 :         vcd_file << "#" << (step + 1) << "\n";
+     124          30 :         inputs.a = $const<1>(a_value);
+     125          30 :         inputs.b = $const<1>(b_value);
+     126          30 :         Adder(inputs, outputs, state, next_state);
+     127          30 :         {
+     128          30 :             Dump d(vcd_file);
+     129          30 :             inputs.dump(d);
+     130          30 :             outputs.dump(d);
+     131          30 :             state.dump(d);
+     132             :         }
+     133          30 :         state = next_state;
+     134             :     }
+     135             : 
+     136           3 :     vcd_file.close();
+     137           3 :     waves.close();
+     138             : 
+     139           3 :     return 0;
+     140           3 : }
+
+
+
+ + + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/gcov.css b/tests/functional/coverage_report/gcov.css new file mode 100644 index 00000000000..0fcdff13cea --- /dev/null +++ b/tests/functional/coverage_report/gcov.css @@ -0,0 +1,519 @@ +/* All views: initial background and text color */ +body +{ + color: #000000; + background-color: #ffffff; +} + +/* All views: standard link format*/ +a:link +{ + color: #284fa8; + text-decoration: underline; +} + +/* All views: standard link - visited format */ +a:visited +{ + color: #00cb40; + text-decoration: underline; +} + +/* All views: standard link - activated format */ +a:active +{ + color: #ff0040; + text-decoration: underline; +} + +/* All views: main title format */ +td.title +{ + text-align: center; + padding-bottom: 10px; + font-family: sans-serif; + font-size: 20pt; + font-style: italic; + font-weight: bold; +} + +/* All views: header item format */ +td.headerItem +{ + text-align: right; + padding-right: 6px; + font-family: sans-serif; + font-weight: bold; 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+} + +/* All views: header item coverage table entry for medium coverage rate */ +td.headerCovTableEntryMed +{ + text-align: right; + color: #000000; + font-family: sans-serif; + font-weight: bold; + white-space: nowrap; + padding-left: 12px; + padding-right: 4px; + background-color: #ffea20; +} + +/* All views: header item coverage table entry for ow coverage rate */ +td.headerCovTableEntryLo +{ + text-align: right; + color: #000000; + font-family: sans-serif; + font-weight: bold; + white-space: nowrap; + padding-left: 12px; + padding-right: 4px; + background-color: #ff0000; +} + +/* All views: header legend value for legend entry */ +td.headerValueLeg +{ + text-align: left; + color: #000000; + font-family: sans-serif; + font-size: 80%; + white-space: nowrap; + padding-top: 4px; +} + +/* All views: color of horizontal ruler */ +td.ruler +{ + background-color: #6688d4; +} + +/* All views: version string format */ +td.versionInfo +{ + text-align: center; + padding-top: 2px; + font-family: sans-serif; + font-style: italic; +} + +/* Directory view/File view (all)/Test case descriptions: + table headline format */ +td.tableHead +{ + text-align: center; + color: #ffffff; + background-color: #6688d4; + font-family: sans-serif; + font-size: 120%; + font-weight: bold; + white-space: nowrap; + padding-left: 4px; + padding-right: 4px; +} + +span.tableHeadSort +{ + padding-right: 4px; +} + +/* Directory view/File view (all): filename entry format */ +td.coverFile +{ + text-align: left; + padding-left: 10px; + padding-right: 20px; + color: #284fa8; + background-color: #dae7fe; + font-family: monospace; +} + +/* Directory view/File view (all): bar-graph entry format*/ +td.coverBar +{ + padding-left: 10px; + padding-right: 10px; + background-color: #dae7fe; +} + +/* Directory view/File view (all): bar-graph outline color */ +td.coverBarOutline +{ + background-color: #000000; +} + +/* Directory view/File view (all): percentage entry for files with + high coverage rate */ +td.coverPerHi +{ + text-align: right; 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LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl - cxxrtl.h (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:9011876.3 %
Date:1980-01-01 00:00:00Functions:7977.8 %
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
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_ZN6cxxrtl8metadata11deserializeB5cxx11EPKc9
_ZN6cxxrtl8metadataC2ERKS0_18
_ZN6cxxrtl6module4stepEPNS_9performerE33
_ZNK6cxxrtl5valueILm1EE3addERKS1_33
_ZNK6cxxrtl5valueILm1EE3aluILb0ELb0EEESt4pairIS1_bERKS1_33
+
+
+ + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h.func.html b/tests/functional/coverage_report/home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h.func.html new file mode 100644 index 00000000000..c7d08356953 --- /dev/null +++ b/tests/functional/coverage_report/home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h.func.html @@ -0,0 +1,108 @@ + + + + + + + LCOV - vcd_harness.info - /home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl - cxxrtl.h (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:9011876.3 %
Date:1980-01-01 00:00:00Functions:7977.8 %
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Function Name Sort by function nameHit count Sort by hit count
_ZN6cxxrtl11debug_items3addERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEONS_10debug_itemEOSt3mapIS6_NS_8metadataESt4lessIS6_ESaISt4pairIS7_SC_EEE9
_ZN6cxxrtl11debug_items3addIJRNS_5valueILm1EEEijEEEvRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPKcSE_DpOT_9
_ZN6cxxrtl12debug_scopes3addERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEES8_OSt3mapIS6_NS_8metadataESt4lessIS6_ESaISt4pairIS7_SA_EEESH_0
_ZN6cxxrtl6module4stepEPNS_9performerE33
_ZN6cxxrtl8metadata11deserializeB5cxx11EPKc9
_ZN6cxxrtl8metadataC2ERKS0_18
_ZNK6cxxrtl5valueILm1EE3addERKS1_33
_ZNK6cxxrtl5valueILm1EE3aluILb0ELb0EEESt4pairIS1_bERKS1_33
_ZZN6cxxrtl8metadata11deserializeB5cxx11EPKcENKUlvE_clEv0
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Generated by: LCOV version 1.0
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+ + + diff --git a/tests/functional/coverage_report/home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h.gcov.html b/tests/functional/coverage_report/home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h.gcov.html new file mode 100644 index 00000000000..699d0521133 --- /dev/null +++ b/tests/functional/coverage_report/home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h.gcov.html @@ -0,0 +1,2182 @@ + + + + + + + LCOV - vcd_harness.info - /home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl - cxxrtl.h (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:9011876.3 %
Date:1980-01-01 00:00:00Functions:7977.8 %
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          Line data    Source code
+
+       1             : /*
+       2             :  *  yosys -- Yosys Open SYnthesis Suite
+       3             :  *
+       4             :  *  Copyright (C) 2019-2020  whitequark <whitequark@whitequark.org>
+       5             :  *
+       6             :  *  Permission to use, copy, modify, and/or distribute this software for any
+       7             :  *  purpose with or without fee is hereby granted.
+       8             :  *
+       9             :  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+      10             :  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+      11             :  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+      12             :  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+      13             :  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+      14             :  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+      15             :  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+      16             :  *
+      17             :  */
+      18             : 
+      19             : // This file is included by the designs generated with `write_cxxrtl`. It is not used in Yosys itself.
+      20             : //
+      21             : // The CXXRTL support library implements compile time specialized arbitrary width arithmetics, as well as provides
+      22             : // composite lvalues made out of bit slices and concatenations of lvalues. This allows the `write_cxxrtl` pass
+      23             : // to perform a straightforward translation of RTLIL structures to readable C++, relying on the C++ compiler
+      24             : // to unwrap the abstraction and generate efficient code.
+      25             : 
+      26             : #ifndef CXXRTL_H
+      27             : #define CXXRTL_H
+      28             : 
+      29             : #include <cstddef>
+      30             : #include <cstdint>
+      31             : #include <cstring>
+      32             : #include <cassert>
+      33             : #include <limits>
+      34             : #include <type_traits>
+      35             : #include <tuple>
+      36             : #include <vector>
+      37             : #include <map>
+      38             : #include <algorithm>
+      39             : #include <memory>
+      40             : #include <functional>
+      41             : #include <sstream>
+      42             : #include <iostream>
+      43             : 
+      44             : // `cxxrtl::debug_item` has to inherit from `cxxrtl_object` to satisfy strict aliasing requirements.
+      45             : #include <cxxrtl/capi/cxxrtl_capi.h>
+      46             : 
+      47             : #ifndef __has_attribute
+      48             : #       define __has_attribute(x) 0
+      49             : #endif
+      50             : 
+      51             : // CXXRTL essentially uses the C++ compiler as a hygienic macro engine that feeds an instruction selector.
+      52             : // It generates a lot of specialized template functions with relatively large bodies that, when inlined
+      53             : // into the caller and (for those with loops) unrolled, often expose many new optimization opportunities.
+      54             : // Because of this, most of the CXXRTL runtime must be always inlined for best performance.
+      55             : #if __has_attribute(always_inline)
+      56             : #define CXXRTL_ALWAYS_INLINE inline __attribute__((__always_inline__))
+      57             : #else
+      58             : #define CXXRTL_ALWAYS_INLINE inline
+      59             : #endif
+      60             : // Conversely, some functions in the generated code are extremely large yet very cold, with both of these
+      61             : // properties being extreme enough to confuse C++ compilers into spending pathological amounts of time
+      62             : // on a futile (the code becomes worse) attempt to optimize the least important parts of code.
+      63             : #if __has_attribute(optnone)
+      64             : #define CXXRTL_EXTREMELY_COLD __attribute__((__optnone__))
+      65             : #elif __has_attribute(optimize)
+      66             : #define CXXRTL_EXTREMELY_COLD __attribute__((__optimize__(0)))
+      67             : #else
+      68             : #define CXXRTL_EXTREMELY_COLD
+      69             : #endif
+      70             : 
+      71             : // CXXRTL uses assert() to check for C++ contract violations (which may result in e.g. undefined behavior
+      72             : // of the simulation code itself), and CXXRTL_ASSERT to check for RTL contract violations (which may at
+      73             : // most result in undefined simulation results).
+      74             : //
+      75             : // Though by default, CXXRTL_ASSERT() expands to assert(), it may be overridden e.g. when integrating
+      76             : // the simulation into another process that should survive violating RTL contracts.
+      77             : #ifndef CXXRTL_ASSERT
+      78             : #ifndef CXXRTL_NDEBUG
+      79             : #define CXXRTL_ASSERT(x) assert(x)
+      80             : #else
+      81             : #define CXXRTL_ASSERT(x)
+      82             : #endif
+      83             : #endif
+      84             : 
+      85             : namespace cxxrtl {
+      86             : 
+      87             : // All arbitrary-width values in CXXRTL are backed by arrays of unsigned integers called chunks. The chunk size
+      88             : // is the same regardless of the value width to simplify manipulating values via FFI interfaces, e.g. driving
+      89             : // and introspecting the simulation in Python.
+      90             : //
+      91             : // It is practical to use chunk sizes between 32 bits and platform register size because when arithmetics on
+      92             : // narrower integer types is legalized by the C++ compiler, it inserts code to clear the high bits of the register.
+      93             : // However, (a) most of our operations do not change those bits in the first place because of invariants that are
+      94             : // invisible to the compiler, (b) we often operate on non-power-of-2 values and have to clear the high bits anyway.
+      95             : // Therefore, using relatively wide chunks and clearing the high bits explicitly and only when we know they may be
+      96             : // clobbered results in simpler generated code.
+      97             : typedef uint32_t chunk_t;
+      98             : typedef uint64_t wide_chunk_t;
+      99             : 
+     100             : template<typename T>
+     101             : struct chunk_traits {
+     102             :         static_assert(std::is_integral<T>::value && std::is_unsigned<T>::value,
+     103             :                       "chunk type must be an unsigned integral type");
+     104             :         using type = T;
+     105             :         static constexpr size_t bits = std::numeric_limits<T>::digits;
+     106             :         static constexpr T mask = std::numeric_limits<T>::max();
+     107             : };
+     108             : 
+     109             : template<class T>
+     110             : struct expr_base;
+     111             : 
+     112             : template<size_t Bits>
+     113             : struct value : public expr_base<value<Bits>> {
+     114             :         static constexpr size_t bits = Bits;
+     115             : 
+     116             :         using chunk = chunk_traits<chunk_t>;
+     117             :         static constexpr chunk::type msb_mask = (Bits % chunk::bits == 0) ? chunk::mask
+     118             :                 : chunk::mask >> (chunk::bits - (Bits % chunk::bits));
+     119             : 
+     120             :         static constexpr size_t chunks = (Bits + chunk::bits - 1) / chunk::bits;
+     121             :         chunk::type data[chunks] = {};
+     122             : 
+     123           3 :         value() = default;
+     124             :         template<typename... Init>
+     125             :         explicit constexpr value(Init ...init) : data{init...} {}
+     126             : 
+     127             :         value(const value<Bits> &) = default;
+     128             :         value<Bits> &operator=(const value<Bits> &) = default;
+     129             : 
+     130             :         value(value<Bits> &&) = default;
+     131             :         value<Bits> &operator=(value<Bits> &&) = default;
+     132             : 
+     133             :         // A (no-op) helper that forces the cast to value<>.
+     134             :         CXXRTL_ALWAYS_INLINE
+     135             :         const value<Bits> &val() const {
+     136             :                 return *this;
+     137             :         }
+     138             : 
+     139             :         std::string str() const {
+     140             :                 std::stringstream ss;
+     141             :                 ss << *this;
+     142             :                 return ss.str();
+     143             :         }
+     144             : 
+     145             :         // Conversion operations.
+     146             :         //
+     147             :         // These functions ensure that a conversion is never out of range, and should be always used, if at all
+     148             :         // possible, instead of direct manipulation of the `data` member. For very large types, .slice() and
+     149             :         // .concat() can be used to split them into more manageable parts.
+     150             :         template<class IntegerT, typename std::enable_if<!std::is_signed<IntegerT>::value, int>::type = 0>
+     151             :         CXXRTL_ALWAYS_INLINE
+     152             :         IntegerT get() const {
+     153             :                 static_assert(std::numeric_limits<IntegerT>::is_integer && !std::numeric_limits<IntegerT>::is_signed,
+     154             :                               "get<T>() requires T to be an unsigned integral type");
+     155             :                 static_assert(std::numeric_limits<IntegerT>::digits >= Bits,
+     156             :                               "get<T>() requires T to be at least as wide as the value is");
+     157             :                 IntegerT result = 0;
+     158             :                 for (size_t n = 0; n < chunks; n++)
+     159             :                         result |= IntegerT(data[n]) << (n * chunk::bits);
+     160             :                 return result;
+     161             :         }
+     162             : 
+     163             :         template<class IntegerT, typename std::enable_if<std::is_signed<IntegerT>::value, int>::type = 0>
+     164             :         CXXRTL_ALWAYS_INLINE
+     165             :         IntegerT get() const {
+     166             :                 auto unsigned_result = get<typename std::make_unsigned<IntegerT>::type>();
+     167             :                 IntegerT result;
+     168             :                 memcpy(&result, &unsigned_result, sizeof(IntegerT));
+     169             :                 return result;
+     170             :         }
+     171             : 
+     172             :         template<class IntegerT, typename std::enable_if<!std::is_signed<IntegerT>::value, int>::type = 0>
+     173             :         CXXRTL_ALWAYS_INLINE
+     174          30 :         void set(IntegerT value) {
+     175             :                 static_assert(std::numeric_limits<IntegerT>::is_integer && !std::numeric_limits<IntegerT>::is_signed,
+     176             :                               "set<T>() requires T to be an unsigned integral type");
+     177             :                 static_assert(std::numeric_limits<IntegerT>::digits >= Bits,
+     178             :                               "set<T>() requires the value to be at least as wide as T is");
+     179           6 :                 for (size_t n = 0; n < chunks; n++)
+     180          36 :                         data[n] = (value >> (n * chunk::bits)) & chunk::mask;
+     181             :         }
+     182             : 
+     183             :         template<class IntegerT, typename std::enable_if<std::is_signed<IntegerT>::value, int>::type = 0>
+     184             :         CXXRTL_ALWAYS_INLINE
+     185             :         void set(IntegerT value) {
+     186             :                 typename std::make_unsigned<IntegerT>::type unsigned_value;
+     187             :                 memcpy(&unsigned_value, &value, sizeof(IntegerT));
+     188             :                 set(unsigned_value);
+     189             :         }
+     190             : 
+     191             :         // Operations with compile-time parameters.
+     192             :         //
+     193             :         // These operations are used to implement slicing, concatenation, and blitting.
+     194             :         // The trunc, zext and sext operations add or remove most significant bits (i.e. on the left);
+     195             :         // the rtrunc and rzext operations add or remove least significant bits (i.e. on the right).
+     196             :         template<size_t NewBits>
+     197             :         CXXRTL_ALWAYS_INLINE
+     198             :         value<NewBits> trunc() const {
+     199             :                 static_assert(NewBits <= Bits, "trunc() may not increase width");
+     200             :                 value<NewBits> result;
+     201             :                 for (size_t n = 0; n < result.chunks; n++)
+     202             :                         result.data[n] = data[n];
+     203             :                 result.data[result.chunks - 1] &= result.msb_mask;
+     204             :                 return result;
+     205             :         }
+     206             : 
+     207             :         template<size_t NewBits>
+     208             :         CXXRTL_ALWAYS_INLINE
+     209          33 :         value<NewBits> zext() const {
+     210             :                 static_assert(NewBits >= Bits, "zext() may not decrease width");
+     211             :                 value<NewBits> result;
+     212          33 :                 for (size_t n = 0; n < chunks; n++)
+     213          33 :                         result.data[n] = data[n];
+     214             :                 return result;
+     215             :         }
+     216             : 
+     217             :         template<size_t NewBits>
+     218             :         CXXRTL_ALWAYS_INLINE
+     219             :         value<NewBits> sext() const {
+     220             :                 static_assert(NewBits >= Bits, "sext() may not decrease width");
+     221             :                 value<NewBits> result;
+     222             :                 for (size_t n = 0; n < chunks; n++)
+     223             :                         result.data[n] = data[n];
+     224             :                 if (is_neg()) {
+     225             :                         result.data[chunks - 1] |= ~msb_mask;
+     226             :                         for (size_t n = chunks; n < result.chunks; n++)
+     227             :                                 result.data[n] = chunk::mask;
+     228             :                         result.data[result.chunks - 1] &= result.msb_mask;
+     229             :                 }
+     230             :                 return result;
+     231             :         }
+     232             : 
+     233             :         template<size_t NewBits>
+     234             :         CXXRTL_ALWAYS_INLINE
+     235             :         value<NewBits> rtrunc() const {
+     236             :                 static_assert(NewBits <= Bits, "rtrunc() may not increase width");
+     237             :                 value<NewBits> result;
+     238             :                 constexpr size_t shift_chunks = (Bits - NewBits) / chunk::bits;
+     239             :                 constexpr size_t shift_bits   = (Bits - NewBits) % chunk::bits;
+     240             :                 chunk::type carry = 0;
+     241             :                 if (shift_chunks + result.chunks < chunks) {
+     242             :                         carry = (shift_bits == 0) ? 0
+     243             :                                 : data[shift_chunks + result.chunks] << (chunk::bits - shift_bits);
+     244             :                 }
+     245             :                 for (size_t n = result.chunks; n > 0; n--) {
+     246             :                         result.data[n - 1] = carry | (data[shift_chunks + n - 1] >> shift_bits);
+     247             :                         carry = (shift_bits == 0) ? 0
+     248             :                                 : data[shift_chunks + n - 1] << (chunk::bits - shift_bits);
+     249             :                 }
+     250             :                 return result;
+     251             :         }
+     252             : 
+     253             :         template<size_t NewBits>
+     254             :         CXXRTL_ALWAYS_INLINE
+     255             :         value<NewBits> rzext() const {
+     256             :                 static_assert(NewBits >= Bits, "rzext() may not decrease width");
+     257             :                 value<NewBits> result;
+     258             :                 constexpr size_t shift_chunks = (NewBits - Bits) / chunk::bits;
+     259             :                 constexpr size_t shift_bits   = (NewBits - Bits) % chunk::bits;
+     260             :                 chunk::type carry = 0;
+     261             :                 for (size_t n = 0; n < chunks; n++) {
+     262             :                         result.data[shift_chunks + n] = (data[n] << shift_bits) | carry;
+     263             :                         carry = (shift_bits == 0) ? 0
+     264             :                                 : data[n] >> (chunk::bits - shift_bits);
+     265             :                 }
+     266             :                 if (shift_chunks + chunks < result.chunks)
+     267             :                         result.data[shift_chunks + chunks] = carry;
+     268             :                 return result;
+     269             :         }
+     270             : 
+     271             :         // Bit blit operation, i.e. a partial read-modify-write.
+     272             :         template<size_t Stop, size_t Start>
+     273             :         CXXRTL_ALWAYS_INLINE
+     274             :         value<Bits> blit(const value<Stop - Start + 1> &source) const {
+     275             :                 static_assert(Stop >= Start, "blit() may not reverse bit order");
+     276             :                 constexpr chunk::type start_mask = ~(chunk::mask << (Start % chunk::bits));
+     277             :                 constexpr chunk::type stop_mask = (Stop % chunk::bits + 1 == chunk::bits) ? 0
+     278             :                         : (chunk::mask << (Stop % chunk::bits + 1));
+     279             :                 value<Bits> masked = *this;
+     280             :                 if (Start / chunk::bits == Stop / chunk::bits) {
+     281             :                         masked.data[Start / chunk::bits] &= stop_mask | start_mask;
+     282             :                 } else {
+     283             :                         masked.data[Start / chunk::bits] &= start_mask;
+     284             :                         for (size_t n = Start / chunk::bits + 1; n < Stop / chunk::bits; n++)
+     285             :                                 masked.data[n] = 0;
+     286             :                         masked.data[Stop / chunk::bits] &= stop_mask;
+     287             :                 }
+     288             :                 value<Bits> shifted = source
+     289             :                         .template rzext<Stop + 1>()
+     290             :                         .template zext<Bits>();
+     291             :                 return masked.bit_or(shifted);
+     292             :         }
+     293             : 
+     294             :         // Helpers for selecting extending or truncating operation depending on whether the result is wider or narrower
+     295             :         // than the operand. In C++17 these can be replaced with `if constexpr`.
+     296             :         template<size_t NewBits, typename = void>
+     297             :         struct zext_cast {
+     298             :                 CXXRTL_ALWAYS_INLINE
+     299          33 :                 value<NewBits> operator()(const value<Bits> &val) {
+     300          33 :                         return val.template zext<NewBits>();
+     301             :                 }
+     302             :         };
+     303             : 
+     304             :         template<size_t NewBits>
+     305             :         struct zext_cast<NewBits, typename std::enable_if<(NewBits < Bits)>::type> {
+     306             :                 CXXRTL_ALWAYS_INLINE
+     307             :                 value<NewBits> operator()(const value<Bits> &val) {
+     308             :                         return val.template trunc<NewBits>();
+     309             :                 }
+     310             :         };
+     311             : 
+     312             :         template<size_t NewBits, typename = void>
+     313             :         struct sext_cast {
+     314             :                 CXXRTL_ALWAYS_INLINE
+     315             :                 value<NewBits> operator()(const value<Bits> &val) {
+     316             :                         return val.template sext<NewBits>();
+     317             :                 }
+     318             :         };
+     319             : 
+     320             :         template<size_t NewBits>
+     321             :         struct sext_cast<NewBits, typename std::enable_if<(NewBits < Bits)>::type> {
+     322             :                 CXXRTL_ALWAYS_INLINE
+     323             :                 value<NewBits> operator()(const value<Bits> &val) {
+     324             :                         return val.template trunc<NewBits>();
+     325             :                 }
+     326             :         };
+     327             : 
+     328             :         template<size_t NewBits>
+     329             :         CXXRTL_ALWAYS_INLINE
+     330          33 :         value<NewBits> zcast() const {
+     331          33 :                 return zext_cast<NewBits>()(*this);
+     332             :         }
+     333             : 
+     334             :         template<size_t NewBits>
+     335             :         CXXRTL_ALWAYS_INLINE
+     336             :         value<NewBits> scast() const {
+     337             :                 return sext_cast<NewBits>()(*this);
+     338             :         }
+     339             : 
+     340             :         // Bit replication is far more efficient than the equivalent concatenation.
+     341             :         template<size_t Count>
+     342             :         CXXRTL_ALWAYS_INLINE
+     343             :         value<Bits * Count> repeat() const {
+     344             :                 static_assert(Bits == 1, "repeat() is implemented only for 1-bit values");
+     345             :                 return *this ? value<Bits * Count>().bit_not() : value<Bits * Count>();
+     346             :         }
+     347             : 
+     348             :         // Operations with run-time parameters (offsets, amounts, etc).
+     349             :         //
+     350             :         // These operations are used for computations.
+     351             :         bool bit(size_t offset) const {
+     352             :                 return data[offset / chunk::bits] & (1 << (offset % chunk::bits));
+     353             :         }
+     354             : 
+     355             :         void set_bit(size_t offset, bool value = true) {
+     356             :                 size_t offset_chunks = offset / chunk::bits;
+     357             :                 size_t offset_bits = offset % chunk::bits;
+     358             :                 data[offset_chunks] &= ~(1 << offset_bits);
+     359             :                 data[offset_chunks] |= value ? 1 << offset_bits : 0;
+     360             :         }
+     361             : 
+     362             :         explicit operator bool() const {
+     363             :                 return !is_zero();
+     364             :         }
+     365             : 
+     366             :         bool is_zero() const {
+     367             :                 for (size_t n = 0; n < chunks; n++)
+     368             :                         if (data[n] != 0)
+     369             :                                 return false;
+     370             :                 return true;
+     371             :         }
+     372             : 
+     373             :         bool is_neg() const {
+     374             :                 return data[chunks - 1] & (1 << ((Bits - 1) % chunk::bits));
+     375             :         }
+     376             : 
+     377             :         bool operator ==(const value<Bits> &other) const {
+     378             :                 for (size_t n = 0; n < chunks; n++)
+     379             :                         if (data[n] != other.data[n])
+     380             :                                 return false;
+     381             :                 return true;
+     382             :         }
+     383             : 
+     384             :         bool operator !=(const value<Bits> &other) const {
+     385             :                 return !(*this == other);
+     386             :         }
+     387             : 
+     388             :         value<Bits> bit_not() const {
+     389             :                 value<Bits> result;
+     390             :                 for (size_t n = 0; n < chunks; n++)
+     391             :                         result.data[n] = ~data[n];
+     392             :                 result.data[chunks - 1] &= msb_mask;
+     393             :                 return result;
+     394             :         }
+     395             : 
+     396             :         value<Bits> bit_and(const value<Bits> &other) const {
+     397             :                 value<Bits> result;
+     398             :                 for (size_t n = 0; n < chunks; n++)
+     399             :                         result.data[n] = data[n] & other.data[n];
+     400             :                 return result;
+     401             :         }
+     402             : 
+     403             :         value<Bits> bit_or(const value<Bits> &other) const {
+     404             :                 value<Bits> result;
+     405             :                 for (size_t n = 0; n < chunks; n++)
+     406             :                         result.data[n] = data[n] | other.data[n];
+     407             :                 return result;
+     408             :         }
+     409             : 
+     410             :         value<Bits> bit_xor(const value<Bits> &other) const {
+     411             :                 value<Bits> result;
+     412             :                 for (size_t n = 0; n < chunks; n++)
+     413             :                         result.data[n] = data[n] ^ other.data[n];
+     414             :                 return result;
+     415             :         }
+     416             : 
+     417             :         value<Bits> update(const value<Bits> &val, const value<Bits> &mask) const {
+     418             :                 return bit_and(mask.bit_not()).bit_or(val.bit_and(mask));
+     419             :         }
+     420             : 
+     421             :         template<size_t AmountBits>
+     422             :         value<Bits> shl(const value<AmountBits> &amount) const {
+     423             :                 // Ensure our early return is correct by prohibiting values larger than 4 Gbit.
+     424             :                 static_assert(Bits <= chunk::mask, "shl() of unreasonably large values is not supported");
+     425             :                 // Detect shifts definitely large than Bits early.
+     426             :                 for (size_t n = 1; n < amount.chunks; n++)
+     427             :                         if (amount.data[n] != 0)
+     428             :                                 return {};
+     429             :                 // Past this point we can use the least significant chunk as the shift size.
+     430             :                 size_t shift_chunks = amount.data[0] / chunk::bits;
+     431             :                 size_t shift_bits   = amount.data[0] % chunk::bits;
+     432             :                 if (shift_chunks >= chunks)
+     433             :                         return {};
+     434             :                 value<Bits> result;
+     435             :                 chunk::type carry = 0;
+     436             :                 for (size_t n = 0; n < chunks - shift_chunks; n++) {
+     437             :                         result.data[shift_chunks + n] = (data[n] << shift_bits) | carry;
+     438             :                         carry = (shift_bits == 0) ? 0
+     439             :                                 : data[n] >> (chunk::bits - shift_bits);
+     440             :                 }
+     441             :                 result.data[result.chunks - 1] &= result.msb_mask;
+     442             :                 return result;
+     443             :         }
+     444             : 
+     445             :         template<size_t AmountBits, bool Signed = false>
+     446             :         value<Bits> shr(const value<AmountBits> &amount) const {
+     447             :                 // Ensure our early return is correct by prohibiting values larger than 4 Gbit.
+     448             :                 static_assert(Bits <= chunk::mask, "shr() of unreasonably large values is not supported");
+     449             :                 // Detect shifts definitely large than Bits early.
+     450             :                 for (size_t n = 1; n < amount.chunks; n++)
+     451             :                         if (amount.data[n] != 0)
+     452             :                                 return (Signed && is_neg()) ? value<Bits>().bit_not() : value<Bits>();
+     453             :                 // Past this point we can use the least significant chunk as the shift size.
+     454             :                 size_t shift_chunks = amount.data[0] / chunk::bits;
+     455             :                 size_t shift_bits   = amount.data[0] % chunk::bits;
+     456             :                 if (shift_chunks >= chunks)
+     457             :                         return (Signed && is_neg()) ? value<Bits>().bit_not() : value<Bits>();
+     458             :                 value<Bits> result;
+     459             :                 chunk::type carry = 0;
+     460             :                 for (size_t n = 0; n < chunks - shift_chunks; n++) {
+     461             :                         result.data[chunks - shift_chunks - 1 - n] = carry | (data[chunks - 1 - n] >> shift_bits);
+     462             :                         carry = (shift_bits == 0) ? 0
+     463             :                                 : data[chunks - 1 - n] << (chunk::bits - shift_bits);
+     464             :                 }
+     465             :                 if (Signed && is_neg()) {
+     466             :                         size_t top_chunk_idx  = amount.data[0] > Bits ? 0 : (Bits - amount.data[0]) / chunk::bits;
+     467             :                         size_t top_chunk_bits = amount.data[0] > Bits ? 0 : (Bits - amount.data[0]) % chunk::bits;
+     468             :                         for (size_t n = top_chunk_idx + 1; n < chunks; n++)
+     469             :                                 result.data[n] = chunk::mask;
+     470             :                         if (amount.data[0] != 0)
+     471             :                                 result.data[top_chunk_idx] |= chunk::mask << top_chunk_bits;
+     472             :                         result.data[result.chunks - 1] &= result.msb_mask;
+     473             :                 }
+     474             :                 return result;
+     475             :         }
+     476             : 
+     477             :         template<size_t AmountBits>
+     478             :         value<Bits> sshr(const value<AmountBits> &amount) const {
+     479             :                 return shr<AmountBits, /*Signed=*/true>(amount);
+     480             :         }
+     481             : 
+     482             :         template<size_t ResultBits, size_t SelBits>
+     483             :         value<ResultBits> bmux(const value<SelBits> &sel) const {
+     484             :                 static_assert(ResultBits << SelBits == Bits, "invalid sizes used in bmux()");
+     485             :                 size_t amount = sel.data[0] * ResultBits;
+     486             :                 size_t shift_chunks = amount / chunk::bits;
+     487             :                 size_t shift_bits   = amount % chunk::bits;
+     488             :                 value<ResultBits> result;
+     489             :                 chunk::type carry = 0;
+     490             :                 if (ResultBits % chunk::bits + shift_bits > chunk::bits)
+     491             :                         carry = data[result.chunks + shift_chunks] << (chunk::bits - shift_bits);
+     492             :                 for (size_t n = 0; n < result.chunks; n++) {
+     493             :                         result.data[result.chunks - 1 - n] = carry | (data[result.chunks + shift_chunks - 1 - n] >> shift_bits);
+     494             :                         carry = (shift_bits == 0) ? 0
+     495             :                                 : data[result.chunks + shift_chunks - 1 - n] << (chunk::bits - shift_bits);
+     496             :                 }
+     497             :                 result.data[result.chunks - 1] &= result.msb_mask;
+     498             :                 return result;
+     499             :         }
+     500             : 
+     501             :         template<size_t ResultBits, size_t SelBits>
+     502             :         value<ResultBits> demux(const value<SelBits> &sel) const {
+     503             :                 static_assert(Bits << SelBits == ResultBits, "invalid sizes used in demux()");
+     504             :                 size_t amount = sel.data[0] * Bits;
+     505             :                 size_t shift_chunks = amount / chunk::bits;
+     506             :                 size_t shift_bits   = amount % chunk::bits;
+     507             :                 value<ResultBits> result;
+     508             :                 chunk::type carry = 0;
+     509             :                 for (size_t n = 0; n < chunks; n++) {
+     510             :                         result.data[shift_chunks + n] = (data[n] << shift_bits) | carry;
+     511             :                         carry = (shift_bits == 0) ? 0
+     512             :                                 : data[n] >> (chunk::bits - shift_bits);
+     513             :                 }
+     514             :                 if (Bits % chunk::bits + shift_bits > chunk::bits)
+     515             :                         result.data[shift_chunks + chunks] = carry;
+     516             :                 return result;
+     517             :         }
+     518             : 
+     519             :         size_t ctpop() const {
+     520             :                 size_t count = 0;
+     521             :                 for (size_t n = 0; n < chunks; n++) {
+     522             :                         // This loop implements the population count idiom as recognized by LLVM and GCC.
+     523             :                         for (chunk::type x = data[n]; x != 0; count++)
+     524             :                                 x = x & (x - 1);
+     525             :                 }
+     526             :                 return count;
+     527             :         }
+     528             : 
+     529             :         size_t ctlz() const {
+     530             :                 size_t count = 0;
+     531             :                 for (size_t n = 0; n < chunks; n++) {
+     532             :                         chunk::type x = data[chunks - 1 - n];
+     533             :                         // First add to `count` as if the chunk is zero
+     534             :                         constexpr size_t msb_chunk_bits = Bits % chunk::bits != 0 ? Bits % chunk::bits : chunk::bits;
+     535             :                         count += (n == 0 ? msb_chunk_bits : chunk::bits);
+     536             :                         // If the chunk isn't zero, correct the `count` value and return
+     537             :                         if (x != 0) {
+     538             :                                 for (; x != 0; count--)
+     539             :                                         x >>= 1;
+     540             :                                 break;
+     541             :                         }
+     542             :                 }
+     543             :                 return count;
+     544             :         }
+     545             : 
+     546             :         template<bool Invert, bool CarryIn>
+     547          33 :         std::pair<value<Bits>, bool /*CarryOut*/> alu(const value<Bits> &other) const {
+     548          33 :                 value<Bits> result;
+     549          33 :                 bool carry = CarryIn;
+     550          66 :                 for (size_t n = 0; n < result.chunks; n++) {
+     551          33 :                         result.data[n] = data[n] + (Invert ? ~other.data[n] : other.data[n]) + carry;
+     552             :                         if (result.chunks - 1 == n)
+     553          33 :                                 result.data[result.chunks - 1] &= result.msb_mask;
+     554          33 :                         carry = (result.data[n] <  data[n]) ||
+     555             :                                 (result.data[n] == data[n] && carry);
+     556             :                 }
+     557          33 :                 return {result, carry};
+     558             :         }
+     559             : 
+     560          33 :         value<Bits> add(const value<Bits> &other) const {
+     561          33 :                 return alu</*Invert=*/false, /*CarryIn=*/false>(other).first;
+     562             :         }
+     563             : 
+     564             :         value<Bits> sub(const value<Bits> &other) const {
+     565             :                 return alu</*Invert=*/true, /*CarryIn=*/true>(other).first;
+     566             :         }
+     567             : 
+     568             :         value<Bits> neg() const {
+     569             :                 return value<Bits>().sub(*this);
+     570             :         }
+     571             : 
+     572             :         bool ucmp(const value<Bits> &other) const {
+     573             :                 bool carry;
+     574             :                 std::tie(std::ignore, carry) = alu</*Invert=*/true, /*CarryIn=*/true>(other);
+     575             :                 return !carry; // a.ucmp(b) ≡ a u< b
+     576             :         }
+     577             : 
+     578             :         bool scmp(const value<Bits> &other) const {
+     579             :                 value<Bits> result;
+     580             :                 bool carry;
+     581             :                 std::tie(result, carry) = alu</*Invert=*/true, /*CarryIn=*/true>(other);
+     582             :                 bool overflow = (is_neg() == !other.is_neg()) && (is_neg() != result.is_neg());
+     583             :                 return result.is_neg() ^ overflow; // a.scmp(b) ≡ a s< b
+     584             :         }
+     585             : 
+     586             :         template<size_t ResultBits>
+     587             :         value<ResultBits> mul(const value<Bits> &other) const {
+     588             :                 value<ResultBits> result;
+     589             :                 wide_chunk_t wide_result[result.chunks + 1] = {};
+     590             :                 for (size_t n = 0; n < chunks; n++) {
+     591             :                         for (size_t m = 0; m < chunks && n + m < result.chunks; m++) {
+     592             :                                 wide_result[n + m] += wide_chunk_t(data[n]) * wide_chunk_t(other.data[m]);
+     593             :                                 wide_result[n + m + 1] += wide_result[n + m] >> chunk::bits;
+     594             :                                 wide_result[n + m] &= chunk::mask;
+     595             :                         }
+     596             :                 }
+     597             :                 for (size_t n = 0; n < result.chunks; n++) {
+     598             :                         result.data[n] = wide_result[n];
+     599             :                 }
+     600             :                 result.data[result.chunks - 1] &= result.msb_mask;
+     601             :                 return result;
+     602             :         }
+     603             : 
+     604             :         std::pair<value<Bits>, value<Bits>> udivmod(value<Bits> divisor) const {
+     605             :                 value<Bits> quotient;
+     606             :                 value<Bits> dividend = *this;
+     607             :                 if (dividend.ucmp(divisor))
+     608             :                         return {/*quotient=*/value<Bits>{0u}, /*remainder=*/dividend};
+     609             :                 int64_t divisor_shift = divisor.ctlz() - dividend.ctlz();
+     610             :                 assert(divisor_shift >= 0);
+     611             :                 divisor = divisor.shl(value<Bits>{(chunk::type) divisor_shift});
+     612             :                 for (size_t step = 0; step <= divisor_shift; step++) {
+     613             :                         quotient = quotient.shl(value<Bits>{1u});
+     614             :                         if (!dividend.ucmp(divisor)) {
+     615             :                                 dividend = dividend.sub(divisor);
+     616             :                                 quotient.set_bit(0, true);
+     617             :                         }
+     618             :                         divisor = divisor.shr(value<Bits>{1u});
+     619             :                 }
+     620             :                 return {quotient, /*remainder=*/dividend};
+     621             :         }
+     622             : 
+     623             :         std::pair<value<Bits>, value<Bits>> sdivmod(const value<Bits> &other) const {
+     624             :                 value<Bits + 1> quotient;
+     625             :                 value<Bits + 1> remainder;
+     626             :                 value<Bits + 1> dividend = sext<Bits + 1>();
+     627             :                 value<Bits + 1> divisor = other.template sext<Bits + 1>();
+     628             :                 if (is_neg()) dividend = dividend.neg();
+     629             :                 if (other.is_neg()) divisor = divisor.neg();
+     630             :                 std::tie(quotient, remainder) = dividend.udivmod(divisor);
+     631             :                 if (is_neg() != other.is_neg()) quotient = quotient.neg();
+     632             :                 if (is_neg()) remainder = remainder.neg();
+     633             :                 return {quotient.template trunc<Bits>(), remainder.template trunc<Bits>()};
+     634             :         }
+     635             : };
+     636             : 
+     637             : // Expression template for a slice, usable as lvalue or rvalue, and composable with other expression templates here.
+     638             : template<class T, size_t Stop, size_t Start>
+     639             : struct slice_expr : public expr_base<slice_expr<T, Stop, Start>> {
+     640             :         static_assert(Stop >= Start, "slice_expr() may not reverse bit order");
+     641             :         static_assert(Start < T::bits && Stop < T::bits, "slice_expr() must be within bounds");
+     642             :         static constexpr size_t bits = Stop - Start + 1;
+     643             : 
+     644             :         T &expr;
+     645             : 
+     646             :         slice_expr(T &expr) : expr(expr) {}
+     647             :         slice_expr(const slice_expr<T, Stop, Start> &) = delete;
+     648             : 
+     649             :         CXXRTL_ALWAYS_INLINE
+     650             :         operator value<bits>() const {
+     651             :                 return static_cast<const value<T::bits> &>(expr)
+     652             :                         .template rtrunc<T::bits - Start>()
+     653             :                         .template trunc<bits>();
+     654             :         }
+     655             : 
+     656             :         CXXRTL_ALWAYS_INLINE
+     657             :         slice_expr<T, Stop, Start> &operator=(const value<bits> &rhs) {
+     658             :                 // Generic partial assignment implemented using a read-modify-write operation on the sliced expression.
+     659             :                 expr = static_cast<const value<T::bits> &>(expr)
+     660             :                         .template blit<Stop, Start>(rhs);
+     661             :                 return *this;
+     662             :         }
+     663             : 
+     664             :         // A helper that forces the cast to value<>, which allows deduction to work.
+     665             :         CXXRTL_ALWAYS_INLINE
+     666             :         value<bits> val() const {
+     667             :                 return static_cast<const value<bits> &>(*this);
+     668             :         }
+     669             : };
+     670             : 
+     671             : // Expression template for a concatenation, usable as lvalue or rvalue, and composable with other expression templates here.
+     672             : template<class T, class U>
+     673             : struct concat_expr : public expr_base<concat_expr<T, U>> {
+     674             :         static constexpr size_t bits = T::bits + U::bits;
+     675             : 
+     676             :         T &ms_expr;
+     677             :         U &ls_expr;
+     678             : 
+     679             :         concat_expr(T &ms_expr, U &ls_expr) : ms_expr(ms_expr), ls_expr(ls_expr) {}
+     680             :         concat_expr(const concat_expr<T, U> &) = delete;
+     681             : 
+     682             :         CXXRTL_ALWAYS_INLINE
+     683             :         operator value<bits>() const {
+     684             :                 value<bits> ms_shifted = static_cast<const value<T::bits> &>(ms_expr)
+     685             :                         .template rzext<bits>();
+     686             :                 value<bits> ls_extended = static_cast<const value<U::bits> &>(ls_expr)
+     687             :                         .template zext<bits>();
+     688             :                 return ms_shifted.bit_or(ls_extended);
+     689             :         }
+     690             : 
+     691             :         CXXRTL_ALWAYS_INLINE
+     692             :         concat_expr<T, U> &operator=(const value<bits> &rhs) {
+     693             :                 ms_expr = rhs.template rtrunc<T::bits>();
+     694             :                 ls_expr = rhs.template trunc<U::bits>();
+     695             :                 return *this;
+     696             :         }
+     697             : 
+     698             :         // A helper that forces the cast to value<>, which allows deduction to work.
+     699             :         CXXRTL_ALWAYS_INLINE
+     700             :         value<bits> val() const {
+     701             :                 return static_cast<const value<bits> &>(*this);
+     702             :         }
+     703             : };
+     704             : 
+     705             : // Base class for expression templates, providing helper methods for operations that are valid on both rvalues and lvalues.
+     706             : //
+     707             : // Note that expression objects (slices and concatenations) constructed in this way should NEVER be captured because
+     708             : // they refer to temporaries that will, in general, only live until the end of the statement. For example, both of
+     709             : // these snippets perform use-after-free:
+     710             : //
+     711             : //    const auto &a = val.slice<7,0>().slice<1>();
+     712             : //    value<1> b = a;
+     713             : //
+     714             : //    auto &&c = val.slice<7,0>().slice<1>();
+     715             : //    c = value<1>{1u};
+     716             : //
+     717             : // An easy way to write code using slices and concatenations safely is to follow two simple rules:
+     718             : //   * Never explicitly name any type except `value<W>` or `const value<W> &`.
+     719             : //   * Never use a `const auto &` or `auto &&` in any such expression.
+     720             : // Then, any code that compiles will be well-defined.
+     721             : template<class T>
+     722             : struct expr_base {
+     723             :         template<size_t Stop, size_t Start = Stop>
+     724             :         CXXRTL_ALWAYS_INLINE
+     725             :         slice_expr<const T, Stop, Start> slice() const {
+     726             :                 return {*static_cast<const T *>(this)};
+     727             :         }
+     728             : 
+     729             :         template<size_t Stop, size_t Start = Stop>
+     730             :         CXXRTL_ALWAYS_INLINE
+     731             :         slice_expr<T, Stop, Start> slice() {
+     732             :                 return {*static_cast<T *>(this)};
+     733             :         }
+     734             : 
+     735             :         template<class U>
+     736             :         CXXRTL_ALWAYS_INLINE
+     737             :         concat_expr<const T, typename std::remove_reference<const U>::type> concat(const U &other) const {
+     738             :                 return {*static_cast<const T *>(this), other};
+     739             :         }
+     740             : 
+     741             :         template<class U>
+     742             :         CXXRTL_ALWAYS_INLINE
+     743             :         concat_expr<T, typename std::remove_reference<U>::type> concat(U &&other) {
+     744             :                 return {*static_cast<T *>(this), other};
+     745             :         }
+     746             : };
+     747             : 
+     748             : template<size_t Bits>
+     749             : std::ostream &operator<<(std::ostream &os, const value<Bits> &val) {
+     750             :         auto old_flags = os.flags(std::ios::right);
+     751             :         auto old_width = os.width(0);
+     752             :         auto old_fill  = os.fill('0');
+     753             :         os << val.bits << '\'' << std::hex;
+     754             :         for (size_t n = val.chunks - 1; n != (size_t)-1; n--) {
+     755             :                 if (n == val.chunks - 1 && Bits % value<Bits>::chunk::bits != 0)
+     756             :                         os.width((Bits % value<Bits>::chunk::bits + 3) / 4);
+     757             :                 else
+     758             :                         os.width((value<Bits>::chunk::bits + 3) / 4);
+     759             :                 os << val.data[n];
+     760             :         }
+     761             :         os.fill(old_fill);
+     762             :         os.width(old_width);
+     763             :         os.flags(old_flags);
+     764             :         return os;
+     765             : }
+     766             : 
+     767             : template<size_t Bits>
+     768             : struct wire {
+     769             :         static constexpr size_t bits = Bits;
+     770             : 
+     771             :         value<Bits> curr;
+     772             :         value<Bits> next;
+     773             : 
+     774             :         wire() = default;
+     775             :         explicit constexpr wire(const value<Bits> &init) : curr(init), next(init) {}
+     776             :         template<typename... Init>
+     777             :         explicit constexpr wire(Init ...init) : curr{init...}, next{init...} {}
+     778             : 
+     779             :         // Copying and copy-assigning values is natural. If, however, a value is replaced with a wire,
+     780             :         // e.g. because a module is built with a different optimization level, then existing code could
+     781             :         // unintentionally copy a wire instead, which would create a subtle but serious bug. To make sure
+     782             :         // this doesn't happen, prohibit copying and copy-assigning wires.
+     783             :         wire(const wire<Bits> &) = delete;
+     784             :         wire<Bits> &operator=(const wire<Bits> &) = delete;
+     785             : 
+     786             :         wire(wire<Bits> &&) = default;
+     787             :         wire<Bits> &operator=(wire<Bits> &&) = default;
+     788             : 
+     789             :         template<class IntegerT>
+     790             :         CXXRTL_ALWAYS_INLINE
+     791             :         IntegerT get() const {
+     792             :                 return curr.template get<IntegerT>();
+     793             :         }
+     794             : 
+     795             :         template<class IntegerT>
+     796             :         CXXRTL_ALWAYS_INLINE
+     797             :         void set(IntegerT other) {
+     798             :                 next.template set<IntegerT>(other);
+     799             :         }
+     800             : 
+     801             :         // This method intentionally takes a mandatory argument (to make it more difficult to misuse in
+     802             :         // black box implementations, leading to missed observer events). It is generic over its argument
+     803             :         // to allow the `on_update` method to be non-virtual.
+     804             :         template<class ObserverT>
+     805             :         bool commit(ObserverT &observer) {
+     806             :                 if (curr != next) {
+     807             :                         observer.on_update(curr.chunks, curr.data, next.data);
+     808             :                         curr = next;
+     809             :                         return true;
+     810             :                 }
+     811             :                 return false;
+     812             :         }
+     813             : };
+     814             : 
+     815             : template<size_t Bits>
+     816             : std::ostream &operator<<(std::ostream &os, const wire<Bits> &val) {
+     817             :         os << val.curr;
+     818             :         return os;
+     819             : }
+     820             : 
+     821             : template<size_t Width>
+     822             : struct memory {
+     823             :         const size_t depth;
+     824             :         std::unique_ptr<value<Width>[]> data;
+     825             : 
+     826             :         explicit memory(size_t depth) : depth(depth), data(new value<Width>[depth]) {}
+     827             : 
+     828             :         memory(const memory<Width> &) = delete;
+     829             :         memory<Width> &operator=(const memory<Width> &) = delete;
+     830             : 
+     831             :         memory(memory<Width> &&) = default;
+     832             :         memory<Width> &operator=(memory<Width> &&other) {
+     833             :                 assert(depth == other.depth);
+     834             :                 data = std::move(other.data);
+     835             :                 write_queue = std::move(other.write_queue);
+     836             :                 return *this;
+     837             :         }
+     838             : 
+     839             :         // An operator for direct memory reads. May be used at any time during the simulation.
+     840             :         const value<Width> &operator [](size_t index) const {
+     841             :                 assert(index < depth);
+     842             :                 return data[index];
+     843             :         }
+     844             : 
+     845             :         // An operator for direct memory writes. May only be used before the simulation is started. If used
+     846             :         // after the simulation is started, the design may malfunction.
+     847             :         value<Width> &operator [](size_t index) {
+     848             :                 assert(index < depth);
+     849             :                 return data[index];
+     850             :         }
+     851             : 
+     852             :         // A simple way to make a writable memory would be to use an array of wires instead of an array of values.
+     853             :         // However, there are two significant downsides to this approach: first, it has large overhead (2× space
+     854             :         // overhead, and O(depth) time overhead during commit); second, it does not simplify handling write port
+     855             :         // priorities. Although in principle write ports could be ordered or conditionally enabled in generated
+     856             :         // code based on their priorities and selected addresses, the feedback arc set problem is computationally
+     857             :         // expensive, and the heuristic based algorithms are not easily modified to guarantee (rather than prefer)
+     858             :         // a particular write port evaluation order.
+     859             :         //
+     860             :         // The approach used here instead is to queue writes into a buffer during the eval phase, then perform
+     861             :         // the writes during the commit phase in the priority order. This approach has low overhead, with both space
+     862             :         // and time proportional to the amount of write ports. Because virtually every memory in a practical design
+     863             :         // has at most two write ports, linear search is used on every write, being the fastest and simplest approach.
+     864             :         struct write {
+     865             :                 size_t index;
+     866             :                 value<Width> val;
+     867             :                 value<Width> mask;
+     868             :                 int priority;
+     869             :         };
+     870             :         std::vector<write> write_queue;
+     871             : 
+     872             :         void update(size_t index, const value<Width> &val, const value<Width> &mask, int priority = 0) {
+     873             :                 assert(index < depth);
+     874             :                 // Queue up the write while keeping the queue sorted by priority.
+     875             :                 write_queue.insert(
+     876             :                         std::upper_bound(write_queue.begin(), write_queue.end(), priority,
+     877             :                                 [](const int a, const write& b) { return a < b.priority; }),
+     878             :                         write { index, val, mask, priority });
+     879             :         }
+     880             : 
+     881             :         // See the note for `wire::commit()`.
+     882             :         template<class ObserverT>
+     883             :         bool commit(ObserverT &observer) {
+     884             :                 bool changed = false;
+     885             :                 for (const write &entry : write_queue) {
+     886             :                         value<Width> elem = data[entry.index];
+     887             :                         elem = elem.update(entry.val, entry.mask);
+     888             :                         if (data[entry.index] != elem) {
+     889             :                                 observer.on_update(value<Width>::chunks, data[0].data, elem.data, entry.index);
+     890             :                                 changed |= true;
+     891             :                         }
+     892             :                         data[entry.index] = elem;
+     893             :                 }
+     894             :                 write_queue.clear();
+     895             :                 return changed;
+     896             :         }
+     897             : };
+     898             : 
+     899          27 : struct metadata {
+     900             :         const enum {
+     901             :                 MISSING = 0,
+     902             :                 UINT    = 1,
+     903             :                 SINT    = 2,
+     904             :                 STRING  = 3,
+     905             :                 DOUBLE  = 4,
+     906             :         } value_type;
+     907             : 
+     908             :         // In debug mode, using the wrong .as_*() function will assert.
+     909             :         // In release mode, using the wrong .as_*() function will safely return a default value.
+     910             :         const uint64_t    uint_value = 0;
+     911             :         const int64_t     sint_value = 0;
+     912             :         const std::string string_value = "";
+     913             :         const double      double_value = 0.0;
+     914             : 
+     915             :         metadata() : value_type(MISSING) {}
+     916           0 :         metadata(uint64_t value) : value_type(UINT), uint_value(value) {}
+     917           0 :         metadata(int64_t value) : value_type(SINT), sint_value(value) {}
+     918           9 :         metadata(const std::string &value) : value_type(STRING), string_value(value) {}
+     919           0 :         metadata(const char *value) : value_type(STRING), string_value(value) {}
+     920           0 :         metadata(double value) : value_type(DOUBLE), double_value(value) {}
+     921             : 
+     922          18 :         metadata(const metadata &) = default;
+     923             :         metadata &operator=(const metadata &) = delete;
+     924             : 
+     925             :         uint64_t as_uint() const {
+     926             :                 assert(value_type == UINT);
+     927             :                 return uint_value;
+     928             :         }
+     929             : 
+     930             :         int64_t as_sint() const {
+     931             :                 assert(value_type == SINT);
+     932             :                 return sint_value;
+     933             :         }
+     934             : 
+     935             :         const std::string &as_string() const {
+     936             :                 assert(value_type == STRING);
+     937             :                 return string_value;
+     938             :         }
+     939             : 
+     940             :         double as_double() const {
+     941             :                 assert(value_type == DOUBLE);
+     942             :                 return double_value;
+     943             :         }
+     944             : 
+     945             :         // Internal CXXRTL use only.
+     946           9 :         static std::map<std::string, metadata> deserialize(const char *ptr) {
+     947           9 :                 std::map<std::string, metadata> result;
+     948           9 :                 std::string name;
+     949             :                 // Grammar:
+     950             :                 // string   ::= [^\0]+ \0
+     951             :                 // metadata ::= [uid] .{8} | s <string>
+     952             :                 // map      ::= ( <string> <metadata> )* \0
+     953          45 :                 for (;;) {
+     954          45 :                         if (*ptr) {
+     955          45 :                                 name += *ptr++;
+     956          18 :                         } else if (!name.empty()) {
+     957           9 :                                 ptr++;
+     958           9 :                                 auto get_u64 = [&]() {
+     959           0 :                                         uint64_t result = 0;
+     960           0 :                                         for (size_t count = 0; count < 8; count++)
+     961           0 :                                                 result = (result << 8) | *ptr++;
+     962           0 :                                         return result;
+     963           9 :                                 };
+     964           9 :                                 char type = *ptr++;
+     965           9 :                                 if (type == 'u') {
+     966           0 :                                         uint64_t value = get_u64();
+     967           0 :                                         result.emplace(name, value);
+     968           9 :                                 } else if (type == 'i') {
+     969           0 :                                         int64_t value = (int64_t)get_u64();
+     970           0 :                                         result.emplace(name, value);
+     971           9 :                                 } else if (type == 'd') {
+     972           0 :                                         double dvalue;
+     973           0 :                                         uint64_t uvalue = get_u64();
+     974           0 :                                         static_assert(sizeof(dvalue) == sizeof(uvalue), "double must be 64 bits in size");
+     975           0 :                                         memcpy(&dvalue, &uvalue, sizeof(dvalue));
+     976           0 :                                         result.emplace(name, dvalue);
+     977           9 :                                 } else if (type == 's') {
+     978           9 :                                         std::string value;
+     979           9 :                                         while (*ptr)
+     980         216 :                                                 value += *ptr++;
+     981           9 :                                         ptr++;
+     982           9 :                                         result.emplace(name, value);
+     983           9 :                                 } else {
+     984           0 :                                         assert(false && "Unknown type specifier");
+     985           9 :                                         return result;
+     986             :                                 }
+     987           9 :                                 name.clear();
+     988             :                         } else {
+     989           9 :                                 return result;
+     990             :                         }
+     991             :                 }
+     992           9 :         }
+     993             : };
+     994             : 
+     995             : typedef std::map<std::string, metadata> metadata_map;
+     996             : 
+     997             : struct performer;
+     998             : 
+     999             : // An object that allows formatting a string lazily.
+    1000             : struct lazy_fmt {
+    1001             :         virtual std::string operator() () const = 0;
+    1002             : };
+    1003             : 
+    1004             : // Flavor of a `$check` cell.
+    1005             : enum class flavor {
+    1006             :         // Corresponds to a `$assert` cell in other flows, and a Verilog `assert ()` statement.
+    1007             :         ASSERT,
+    1008             :         // Corresponds to a `$assume` cell in other flows, and a Verilog `assume ()` statement.
+    1009             :         ASSUME,
+    1010             :         // Corresponds to a `$live` cell in other flows, and a Verilog `assert (eventually)` statement.
+    1011             :         ASSERT_EVENTUALLY,
+    1012             :         // Corresponds to a `$fair` cell in other flows, and a Verilog `assume (eventually)` statement.
+    1013             :         ASSUME_EVENTUALLY,
+    1014             :         // Corresponds to a `$cover` cell in other flows, and a Verilog `cover ()` statement.
+    1015             :         COVER,
+    1016             : };
+    1017             : 
+    1018             : // An object that can be passed to a `eval()` method in order to act on side effects. The default behavior implemented
+    1019             : // below is the same as the behavior of `eval(nullptr)`, except that `-print-output` option of `write_cxxrtl` is not
+    1020             : // taken into account.
+    1021             : struct performer {
+    1022             :         // Called by generated formatting code to evaluate a Verilog `$time` expression.
+    1023             :         virtual int64_t vlog_time() const { return 0; }
+    1024             : 
+    1025             :         // Called by generated formatting code to evaluate a Verilog `$realtime` expression.
+    1026             :         virtual double vlog_realtime() const { return vlog_time(); }
+    1027             : 
+    1028             :         // Called when a `$print` cell is triggered.
+    1029             :         virtual void on_print(const lazy_fmt &formatter, const metadata_map &attributes) {
+    1030             :                 std::cout << formatter();
+    1031             :         }
+    1032             : 
+    1033             :         // Called when a `$check` cell is triggered.
+    1034             :         virtual void on_check(flavor type, bool condition, const lazy_fmt &formatter, const metadata_map &attributes) {
+    1035             :                 if (type == flavor::ASSERT || type == flavor::ASSUME) {
+    1036             :                         if (!condition)
+    1037             :                                 std::cerr << formatter();
+    1038             :                         CXXRTL_ASSERT(condition && "Check failed");
+    1039             :                 }
+    1040             :         }
+    1041             : };
+    1042             : 
+    1043             : // An object that can be passed to a `commit()` method in order to produce a replay log of every state change in
+    1044             : // the simulation. Unlike `performer`, `observer` does not use virtual calls as their overhead is unacceptable, and
+    1045             : // a comparatively heavyweight template-based solution is justified.
+    1046             : struct observer {
+    1047             :         // Called when the `commit()` method for a wire is about to update the `chunks` chunks at `base` with `chunks` chunks
+    1048             :         // at `value` that have a different bit pattern. It is guaranteed that `chunks` is equal to the wire chunk count and
+    1049             :         // `base` points to the first chunk.
+    1050             :         void on_update(size_t chunks, const chunk_t *base, const chunk_t *value) {}
+    1051             : 
+    1052             :         // Called when the `commit()` method for a memory is about to update the `chunks` chunks at `&base[chunks * index]`
+    1053             :         // with `chunks` chunks at `value` that have a different bit pattern. It is guaranteed that `chunks` is equal to
+    1054             :         // the memory element chunk count and `base` points to the first chunk of the first element of the memory.
+    1055             :         void on_update(size_t chunks, const chunk_t *base, const chunk_t *value, size_t index) {}
+    1056             : };
+    1057             : 
+    1058             : // Must be kept in sync with `struct FmtPart` in kernel/fmt.h!
+    1059             : // Default member initializers would make this a non-aggregate-type in C++11, so they are commented out.
+    1060             : struct fmt_part {
+    1061             :         enum {
+    1062             :                 LITERAL   = 0,
+    1063             :                 INTEGER   = 1,
+    1064             :                 STRING    = 2,
+    1065             :                 UNICHAR   = 3,
+    1066             :                 VLOG_TIME = 4,
+    1067             :         } type;
+    1068             : 
+    1069             :         // LITERAL type
+    1070             :         std::string str;
+    1071             : 
+    1072             :         // INTEGER/STRING/UNICHAR types
+    1073             :         // + value<Bits> val;
+    1074             : 
+    1075             :         // INTEGER/STRING/VLOG_TIME types
+    1076             :         enum {
+    1077             :                 RIGHT   = 0,
+    1078             :                 LEFT    = 1,
+    1079             :                 NUMERIC = 2,
+    1080             :         } justify; // = RIGHT;
+    1081             :         char padding; // = '\0';
+    1082             :         size_t width; // = 0;
+    1083             : 
+    1084             :         // INTEGER type
+    1085             :         unsigned base; // = 10;
+    1086             :         bool signed_; // = false;
+    1087             :         enum {
+    1088             :                 MINUS           = 0,
+    1089             :                 PLUS_MINUS      = 1,
+    1090             :                 SPACE_MINUS     = 2,
+    1091             :         } sign; // = MINUS;
+    1092             :         bool hex_upper; // = false;
+    1093             :         bool show_base; // = false;
+    1094             :         bool group; // = false;
+    1095             : 
+    1096             :         // VLOG_TIME type
+    1097             :         bool realtime; // = false;
+    1098             :         // + int64_t itime;
+    1099             :         // + double ftime;
+    1100             : 
+    1101             :         // Format the part as a string.
+    1102             :         //
+    1103             :         // The values of `vlog_time` and `vlog_realtime` are used for Verilog `$time` and `$realtime`, correspondingly.
+    1104             :         template<size_t Bits>
+    1105             :         std::string render(value<Bits> val, performer *performer = nullptr)
+    1106             :         {
+    1107             :                 // We might want to replace some of these bit() calls with direct
+    1108             :                 // chunk access if it turns out to be slow enough to matter.
+    1109             :                 std::string buf;
+    1110             :                 std::string prefix;
+    1111             :                 switch (type) {
+    1112             :                         case LITERAL:
+    1113             :                                 return str;
+    1114             : 
+    1115             :                         case STRING: {
+    1116             :                                 buf.reserve(Bits/8);
+    1117             :                                 for (int i = 0; i < Bits; i += 8) {
+    1118             :                                         char ch = 0;
+    1119             :                                         for (int j = 0; j < 8 && i + j < int(Bits); j++)
+    1120             :                                                 if (val.bit(i + j))
+    1121             :                                                         ch |= 1 << j;
+    1122             :                                         if (ch != 0)
+    1123             :                                                 buf.append({ch});
+    1124             :                                 }
+    1125             :                                 std::reverse(buf.begin(), buf.end());
+    1126             :                                 break;
+    1127             :                         }
+    1128             : 
+    1129             :                         case UNICHAR: {
+    1130             :                                 uint32_t codepoint = val.template get<uint32_t>();
+    1131             :                                 if (codepoint >= 0x10000)
+    1132             :                                         buf += (char)(0xf0 |  (codepoint >> 18));
+    1133             :                                 else if (codepoint >= 0x800)
+    1134             :                                         buf += (char)(0xe0 |  (codepoint >> 12));
+    1135             :                                 else if (codepoint >= 0x80)
+    1136             :                                         buf += (char)(0xc0 |  (codepoint >>  6));
+    1137             :                                 else
+    1138             :                                         buf += (char)codepoint;
+    1139             :                                 if (codepoint >= 0x10000)
+    1140             :                                         buf += (char)(0x80 | ((codepoint >> 12) & 0x3f));
+    1141             :                                 if (codepoint >= 0x800)
+    1142             :                                         buf += (char)(0x80 | ((codepoint >>  6) & 0x3f));
+    1143             :                                 if (codepoint >= 0x80)
+    1144             :                                         buf += (char)(0x80 | ((codepoint >>  0) & 0x3f));
+    1145             :                                 break;
+    1146             :                         }
+    1147             : 
+    1148             :                         case INTEGER: {
+    1149             :                                 bool negative = signed_ && val.is_neg();
+    1150             :                                 if (negative) {
+    1151             :                                         prefix = "-";
+    1152             :                                         val = val.neg();
+    1153             :                                 } else {
+    1154             :                                         switch (sign) {
+    1155             :                                                 case MINUS:       break;
+    1156             :                                                 case PLUS_MINUS:  prefix = "+"; break;
+    1157             :                                                 case SPACE_MINUS: prefix = " "; break;
+    1158             :                                         }
+    1159             :                                 }
+    1160             : 
+    1161             :                                 size_t val_width = Bits;
+    1162             :                                 if (base != 10) {
+    1163             :                                         val_width = 1;
+    1164             :                                         for (size_t index = 0; index < Bits; index++)
+    1165             :                                                 if (val.bit(index))
+    1166             :                                                         val_width = index + 1;
+    1167             :                                 }
+    1168             : 
+    1169             :                                 if (base == 2) {
+    1170             :                                         if (show_base)
+    1171             :                                                 prefix += "0b";
+    1172             :                                         for (size_t index = 0; index < val_width; index++) {
+    1173             :                                                 if (group && index > 0 && index % 4 == 0)
+    1174             :                                                         buf += '_';
+    1175             :                                                 buf += (val.bit(index) ? '1' : '0');
+    1176             :                                         }
+    1177             :                                 } else if (base == 8 || base == 16) {
+    1178             :                                         if (show_base)
+    1179             :                                                 prefix += (base == 16) ? (hex_upper ? "0X" : "0x") : "0o";
+    1180             :                                         size_t step = (base == 16) ? 4 : 3;
+    1181             :                                         for (size_t index = 0; index < val_width; index += step) {
+    1182             :                                                 if (group && index > 0 && index % (4 * step) == 0)
+    1183             :                                                         buf += '_';
+    1184             :                                                 uint8_t value = val.bit(index) | (val.bit(index + 1) << 1) | (val.bit(index + 2) << 2);
+    1185             :                                                 if (step == 4)
+    1186             :                                                         value |= val.bit(index + 3) << 3;
+    1187             :                                                 buf += (hex_upper ? "0123456789ABCDEF" : "0123456789abcdef")[value];
+    1188             :                                         }
+    1189             :                                 } else if (base == 10) {
+    1190             :                                         if (show_base)
+    1191             :                                                 prefix += "0d";
+    1192             :                                         if (val.is_zero())
+    1193             :                                                 buf += '0';
+    1194             :                                         value<(Bits > 4 ? Bits : 4)> xval = val.template zext<(Bits > 4 ? Bits : 4)>();
+    1195             :                                         size_t index = 0;
+    1196             :                                         while (!xval.is_zero()) {
+    1197             :                                                 if (group && index > 0 && index % 3 == 0)
+    1198             :                                                         buf += '_';
+    1199             :                                                 value<(Bits > 4 ? Bits : 4)> quotient, remainder;
+    1200             :                                                 if (Bits >= 4)
+    1201             :                                                         std::tie(quotient, remainder) = xval.udivmod(value<(Bits > 4 ? Bits : 4)>{10u});
+    1202             :                                                 else
+    1203             :                                                         std::tie(quotient, remainder) = std::make_pair(value<(Bits > 4 ? Bits : 4)>{0u}, xval);
+    1204             :                                                 buf += '0' + remainder.template trunc<4>().template get<uint8_t>();
+    1205             :                                                 xval = quotient;
+    1206             :                                                 index++;
+    1207             :                                         }
+    1208             :                                 } else assert(false && "Unsupported base for fmt_part");
+    1209             :                                 if (justify == NUMERIC && group && padding == '0') {
+    1210             :                                         int group_size = base == 10 ? 3 : 4;
+    1211             :                                         while (prefix.size() + buf.size() < width) {
+    1212             :                                                 if (buf.size() % (group_size + 1) == group_size)
+    1213             :                                                         buf += '_';
+    1214             :                                                 buf += '0';
+    1215             :                                         }
+    1216             :                                 }
+    1217             :                                 std::reverse(buf.begin(), buf.end());
+    1218             :                                 break;
+    1219             :                         }
+    1220             : 
+    1221             :                         case VLOG_TIME: {
+    1222             :                                 if (performer) {
+    1223             :                                         buf = realtime ? std::to_string(performer->vlog_realtime()) : std::to_string(performer->vlog_time());
+    1224             :                                 } else {
+    1225             :                                         buf = realtime ? std::to_string(0.0) : std::to_string(0);
+    1226             :                                 }
+    1227             :                                 break;
+    1228             :                         }
+    1229             :                 }
+    1230             : 
+    1231             :                 std::string str;
+    1232             :                 assert(width == 0 || padding != '\0');
+    1233             :                 if (prefix.size() + buf.size() < width) {
+    1234             :                         size_t pad_width = width - prefix.size() - buf.size();
+    1235             :                         switch (justify) {
+    1236             :                                 case LEFT:
+    1237             :                                         str += prefix;
+    1238             :                                         str += buf;
+    1239             :                                         str += std::string(pad_width, padding);
+    1240             :                                         break;
+    1241             :                                 case RIGHT:
+    1242             :                                         str += std::string(pad_width, padding);
+    1243             :                                         str += prefix;
+    1244             :                                         str += buf;
+    1245             :                                         break;
+    1246             :                                 case NUMERIC:
+    1247             :                                         str += prefix;
+    1248             :                                         str += std::string(pad_width, padding);
+    1249             :                                         str += buf;
+    1250             :                                         break;
+    1251             :                                 }
+    1252             :                 } else {
+    1253             :                         str += prefix;
+    1254             :                         str += buf;
+    1255             :                 }
+    1256             :                 return str;
+    1257             :         }
+    1258             : };
+    1259             : 
+    1260             : // Tag class to disambiguate values/wires and their aliases.
+    1261             : struct debug_alias {};
+    1262             : 
+    1263             : // Tag declaration to disambiguate values and debug outlines.
+    1264             : using debug_outline = ::_cxxrtl_outline;
+    1265             : 
+    1266             : // This structure is intended for consumption via foreign function interfaces, like Python's ctypes.
+    1267             : // Because of this it uses a C-style layout that is easy to parse rather than more idiomatic C++.
+    1268             : //
+    1269             : // To avoid violating strict aliasing rules, this structure has to be a subclass of the one used
+    1270             : // in the C API, or it would not be possible to cast between the pointers to these.
+    1271             : //
+    1272             : // The `attrs` member cannot be owned by this structure because a `cxxrtl_object` can be created
+    1273             : // from external C code.
+    1274             : struct debug_item : ::cxxrtl_object {
+    1275             :         // Object types.
+    1276             :         enum : uint32_t {
+    1277             :                 VALUE   = CXXRTL_VALUE,
+    1278             :                 WIRE    = CXXRTL_WIRE,
+    1279             :                 MEMORY  = CXXRTL_MEMORY,
+    1280             :                 ALIAS   = CXXRTL_ALIAS,
+    1281             :                 OUTLINE = CXXRTL_OUTLINE,
+    1282             :         };
+    1283             : 
+    1284             :         // Object flags.
+    1285             :         enum : uint32_t {
+    1286             :                 INPUT  = CXXRTL_INPUT,
+    1287             :                 OUTPUT = CXXRTL_OUTPUT,
+    1288             :                 INOUT  = CXXRTL_INOUT,
+    1289             :                 DRIVEN_SYNC = CXXRTL_DRIVEN_SYNC,
+    1290             :                 DRIVEN_COMB = CXXRTL_DRIVEN_COMB,
+    1291             :                 UNDRIVEN    = CXXRTL_UNDRIVEN,
+    1292             :         };
+    1293             : 
+    1294             :         debug_item(const ::cxxrtl_object &object) : cxxrtl_object(object) {}
+    1295             : 
+    1296             :         template<size_t Bits>
+    1297           9 :         debug_item(value<Bits> &item, size_t lsb_offset = 0, uint32_t flags_ = 0) {
+    1298             :                 static_assert(Bits == 0 || sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),
+    1299             :                               "value<Bits> is not compatible with C layout");
+    1300           9 :                 type    = VALUE;
+    1301           9 :                 flags   = flags_;
+    1302           9 :                 width   = Bits;
+    1303           9 :                 lsb_at  = lsb_offset;
+    1304           9 :                 depth   = 1;
+    1305           9 :                 zero_at = 0;
+    1306           9 :                 curr    = item.data;
+    1307           9 :                 next    = item.data;
+    1308           9 :                 outline = nullptr;
+    1309           9 :                 attrs   = nullptr;
+    1310             :         }
+    1311             : 
+    1312             :         template<size_t Bits>
+    1313             :         debug_item(const value<Bits> &item, size_t lsb_offset = 0) {
+    1314             :                 static_assert(Bits == 0 || sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),
+    1315             :                               "value<Bits> is not compatible with C layout");
+    1316             :                 type    = VALUE;
+    1317             :                 flags   = DRIVEN_COMB;
+    1318             :                 width   = Bits;
+    1319             :                 lsb_at  = lsb_offset;
+    1320             :                 depth   = 1;
+    1321             :                 zero_at = 0;
+    1322             :                 curr    = const_cast<chunk_t*>(item.data);
+    1323             :                 next    = nullptr;
+    1324             :                 outline = nullptr;
+    1325             :                 attrs   = nullptr;
+    1326             :         }
+    1327             : 
+    1328             :         template<size_t Bits>
+    1329             :         debug_item(wire<Bits> &item, size_t lsb_offset = 0, uint32_t flags_ = 0) {
+    1330             :                 static_assert(Bits == 0 ||
+    1331             :                               (sizeof(item.curr) == value<Bits>::chunks * sizeof(chunk_t) &&
+    1332             :                                sizeof(item.next) == value<Bits>::chunks * sizeof(chunk_t)),
+    1333             :                               "wire<Bits> is not compatible with C layout");
+    1334             :                 type    = WIRE;
+    1335             :                 flags   = flags_;
+    1336             :                 width   = Bits;
+    1337             :                 lsb_at  = lsb_offset;
+    1338             :                 depth   = 1;
+    1339             :                 zero_at = 0;
+    1340             :                 curr    = item.curr.data;
+    1341             :                 next    = item.next.data;
+    1342             :                 outline = nullptr;
+    1343             :                 attrs   = nullptr;
+    1344             :         }
+    1345             : 
+    1346             :         template<size_t Width>
+    1347             :         debug_item(memory<Width> &item, size_t zero_offset = 0) {
+    1348             :                 static_assert(Width == 0 || sizeof(item.data[0]) == value<Width>::chunks * sizeof(chunk_t),
+    1349             :                               "memory<Width> is not compatible with C layout");
+    1350             :                 type    = MEMORY;
+    1351             :                 flags   = 0;
+    1352             :                 width   = Width;
+    1353             :                 lsb_at  = 0;
+    1354             :                 depth   = item.depth;
+    1355             :                 zero_at = zero_offset;
+    1356             :                 curr    = item.data ? item.data[0].data : nullptr;
+    1357             :                 next    = nullptr;
+    1358             :                 outline = nullptr;
+    1359             :                 attrs   = nullptr;
+    1360             :         }
+    1361             : 
+    1362             :         template<size_t Bits>
+    1363             :         debug_item(debug_alias, const value<Bits> &item, size_t lsb_offset = 0) {
+    1364             :                 static_assert(Bits == 0 || sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),
+    1365             :                               "value<Bits> is not compatible with C layout");
+    1366             :                 type    = ALIAS;
+    1367             :                 flags   = DRIVEN_COMB;
+    1368             :                 width   = Bits;
+    1369             :                 lsb_at  = lsb_offset;
+    1370             :                 depth   = 1;
+    1371             :                 zero_at = 0;
+    1372             :                 curr    = const_cast<chunk_t*>(item.data);
+    1373             :                 next    = nullptr;
+    1374             :                 outline = nullptr;
+    1375             :                 attrs   = nullptr;
+    1376             :         }
+    1377             : 
+    1378             :         template<size_t Bits>
+    1379             :         debug_item(debug_alias, const wire<Bits> &item, size_t lsb_offset = 0) {
+    1380             :                 static_assert(Bits == 0 ||
+    1381             :                               (sizeof(item.curr) == value<Bits>::chunks * sizeof(chunk_t) &&
+    1382             :                                sizeof(item.next) == value<Bits>::chunks * sizeof(chunk_t)),
+    1383             :                               "wire<Bits> is not compatible with C layout");
+    1384             :                 type    = ALIAS;
+    1385             :                 flags   = DRIVEN_COMB;
+    1386             :                 width   = Bits;
+    1387             :                 lsb_at  = lsb_offset;
+    1388             :                 depth   = 1;
+    1389             :                 zero_at = 0;
+    1390             :                 curr    = const_cast<chunk_t*>(item.curr.data);
+    1391             :                 next    = nullptr;
+    1392             :                 outline = nullptr;
+    1393             :                 attrs   = nullptr;
+    1394             :         }
+    1395             : 
+    1396             :         template<size_t Bits>
+    1397             :         debug_item(debug_outline &group, const value<Bits> &item, size_t lsb_offset = 0) {
+    1398             :                 static_assert(Bits == 0 || sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),
+    1399             :                               "value<Bits> is not compatible with C layout");
+    1400             :                 type    = OUTLINE;
+    1401             :                 flags   = DRIVEN_COMB;
+    1402             :                 width   = Bits;
+    1403             :                 lsb_at  = lsb_offset;
+    1404             :                 depth   = 1;
+    1405             :                 zero_at = 0;
+    1406             :                 curr    = const_cast<chunk_t*>(item.data);
+    1407             :                 next    = nullptr;
+    1408             :                 outline = &group;
+    1409             :                 attrs   = nullptr;
+    1410             :         }
+    1411             : 
+    1412             :         template<size_t Bits, class IntegerT>
+    1413             :         IntegerT get() const {
+    1414             :                 assert(width == Bits && depth == 1);
+    1415             :                 value<Bits> item;
+    1416             :                 std::copy(curr, curr + value<Bits>::chunks, item.data);
+    1417             :                 return item.template get<IntegerT>();
+    1418             :         }
+    1419             : 
+    1420             :         template<size_t Bits, class IntegerT>
+    1421             :         void set(IntegerT other) const {
+    1422             :                 assert(width == Bits && depth == 1);
+    1423             :                 value<Bits> item;
+    1424             :                 item.template set<IntegerT>(other);
+    1425             :                 std::copy(item.data, item.data + value<Bits>::chunks, next);
+    1426             :         }
+    1427             : };
+    1428             : static_assert(std::is_standard_layout<debug_item>::value, "debug_item is not compatible with C layout");
+    1429             : 
+    1430             : } // namespace cxxrtl
+    1431             : 
+    1432           9 : typedef struct _cxxrtl_attr_set {
+    1433             :         cxxrtl::metadata_map map;
+    1434             : } *cxxrtl_attr_set;
+    1435             : 
+    1436             : namespace cxxrtl {
+    1437             : 
+    1438             : // Representation of an attribute set in the C++ interface.
+    1439             : using debug_attrs = ::_cxxrtl_attr_set;
+    1440             : 
+    1441           3 : struct debug_items {
+    1442             :         // Debug items may be composed of multiple parts, but the attributes are shared between all of them.
+    1443             :         // There are additional invariants, not all of which are not checked by this code:
+    1444             :         // - Memories and non-memories cannot be mixed together.
+    1445             :         // - Bit indices (considering `lsb_at` and `width`) must not overlap.
+    1446             :         // - Row indices (considering `depth` and `zero_at`) must be the same.
+    1447             :         // - The `INPUT` and `OUTPUT` flags must be the same for all parts.
+    1448             :         // Other than that, the parts can be quite different, e.g. it is OK to mix a value, a wire, an alias,
+    1449             :         // and an outline, in the debug information for a single name in four parts.
+    1450             :         std::map<std::string, std::vector<debug_item>> table;
+    1451             :         std::map<std::string, std::unique_ptr<debug_attrs>> attrs_table;
+    1452             : 
+    1453           9 :         void add(const std::string &path, debug_item &&item, metadata_map &&item_attrs = {}) {
+    1454           9 :                 assert((path.empty() || path[path.size() - 1] != ' ') && path.find("  ") == std::string::npos);
+    1455           9 :                 std::unique_ptr<debug_attrs> &attrs = attrs_table[path];
+    1456           9 :                 if (attrs.get() == nullptr)
+    1457           9 :                         attrs = std::unique_ptr<debug_attrs>(new debug_attrs);
+    1458          18 :                 for (auto attr : item_attrs)
+    1459          18 :                         attrs->map.insert(attr);
+    1460           9 :                 item.attrs = attrs.get();
+    1461           9 :                 std::vector<debug_item> &parts = table[path];
+    1462           9 :                 parts.emplace_back(item);
+    1463           9 :                 std::sort(parts.begin(), parts.end(),
+    1464           0 :                         [](const debug_item &a, const debug_item &b) {
+    1465           0 :                                 return a.lsb_at < b.lsb_at;
+    1466             :                         });
+    1467           9 :         }
+    1468             : 
+    1469             :         // This overload exists to reduce excessive stack slot allocation in `CXXRTL_EXTREMELY_COLD void debug_info()`.
+    1470             :         template<class... T>
+    1471           9 :         void add(const std::string &base_path, const char *path, const char *serialized_item_attrs, T&&... args) {
+    1472          18 :                 add(base_path + path, debug_item(std::forward<T>(args)...), metadata::deserialize(serialized_item_attrs));
+    1473           9 :         }
+    1474             : 
+    1475             :         size_t count(const std::string &path) const {
+    1476             :                 if (table.count(path) == 0)
+    1477             :                         return 0;
+    1478             :                 return table.at(path).size();
+    1479             :         }
+    1480             : 
+    1481             :         const std::vector<debug_item> &at(const std::string &path) const {
+    1482             :                 return table.at(path);
+    1483             :         }
+    1484             : 
+    1485             :         // Like `at()`, but operates only on single-part debug items.
+    1486             :         const debug_item &operator [](const std::string &path) const {
+    1487             :                 const std::vector<debug_item> &parts = table.at(path);
+    1488             :                 assert(parts.size() == 1);
+    1489             :                 return parts.at(0);
+    1490             :         }
+    1491             : 
+    1492             :         bool is_memory(const std::string &path) const {
+    1493             :                 return at(path).at(0).type == debug_item::MEMORY;
+    1494             :         }
+    1495             : 
+    1496             :         const metadata_map &attrs(const std::string &path) const {
+    1497             :                 return attrs_table.at(path)->map;
+    1498             :         }
+    1499             : };
+    1500             : 
+    1501             : // Only `module` scopes are defined. The type is implicit, since Yosys does not currently support
+    1502             : // any other scope types.
+    1503           3 : struct debug_scope {
+    1504             :         std::string module_name;
+    1505             :         std::unique_ptr<debug_attrs> module_attrs;
+    1506             :         std::unique_ptr<debug_attrs> cell_attrs;
+    1507             : };
+    1508             : 
+    1509             : struct debug_scopes {
+    1510             :         std::map<std::string, debug_scope> table;
+    1511             : 
+    1512           0 :         void add(const std::string &path, const std::string &module_name, metadata_map &&module_attrs, metadata_map &&cell_attrs) {
+    1513           0 :                 assert((path.empty() || path[path.size() - 1] != ' ') && path.find("  ") == std::string::npos);
+    1514           0 :                 assert(table.count(path) == 0);
+    1515           0 :                 debug_scope &scope = table[path];
+    1516           0 :                 scope.module_name = module_name;
+    1517           0 :                 scope.module_attrs = std::unique_ptr<debug_attrs>(new debug_attrs { module_attrs });
+    1518           0 :                 scope.cell_attrs = std::unique_ptr<debug_attrs>(new debug_attrs { cell_attrs });
+    1519           0 :         }
+    1520             : 
+    1521             :         // This overload exists to reduce excessive stack slot allocation in `CXXRTL_EXTREMELY_COLD void debug_info()`.
+    1522             :         void add(const std::string &base_path, const char *path, const char *module_name, const char *serialized_module_attrs, const char *serialized_cell_attrs) {
+    1523             :                 add(base_path + path, module_name, metadata::deserialize(serialized_module_attrs), metadata::deserialize(serialized_cell_attrs));
+    1524             :         }
+    1525             : 
+    1526             :         size_t contains(const std::string &path) const {
+    1527             :                 return table.count(path);
+    1528             :         }
+    1529             : 
+    1530             :         const debug_scope &operator [](const std::string &path) const {
+    1531             :                 return table.at(path);
+    1532             :         }
+    1533             : };
+    1534             : 
+    1535             : // Tag class to disambiguate the default constructor used by the toplevel module that calls `reset()`,
+    1536             : // and the constructor of interior modules that should not call it.
+    1537             : struct interior {};
+    1538             : 
+    1539             : // The core API of the `module` class consists of only four virtual methods: `reset()`, `eval()`,
+    1540             : // `commit`, and `debug_info()`. (The virtual destructor is made necessary by C++.) Every other method
+    1541             : // is a convenience method, and exists solely to simplify some common pattern for C++ API consumers.
+    1542             : // No behavior may be added to such convenience methods that other parts of CXXRTL can rely on, since
+    1543             : // there is no guarantee they will be called (and, for example, other CXXRTL libraries will often call
+    1544             : // the `eval()` and `commit()` directly instead, as well as being exposed in the C API).
+    1545             : struct module {
+    1546           3 :         module() {}
+    1547           3 :         virtual ~module() {}
+    1548             : 
+    1549             :         // Modules with black boxes cannot be copied. Although not all designs include black boxes,
+    1550             :         // delete the copy constructor and copy assignment operator to make sure that any downstream
+    1551             :         // code that manipulates modules doesn't accidentally depend on their availability.
+    1552             :         module(const module &) = delete;
+    1553             :         module &operator=(const module &) = delete;
+    1554             : 
+    1555             :         module(module &&) = default;
+    1556             :         module &operator=(module &&) = default;
+    1557             : 
+    1558             :         virtual void reset() = 0;
+    1559             : 
+    1560             :         // The `eval()` callback object, `performer`, is included in the virtual call signature since
+    1561             :         // the generated code has broadly identical performance properties.
+    1562             :         virtual bool eval(performer *performer = nullptr) = 0;
+    1563             : 
+    1564             :         // The `commit()` callback object, `observer`, is not included in the virtual call signature since
+    1565             :         // the generated code is severely pessimized by it. To observe commit events, the non-virtual
+    1566             :         // `commit(observer *)` overload must be called directly on a `module` subclass.
+    1567             :         virtual bool commit() = 0;
+    1568             : 
+    1569          33 :         size_t step(performer *performer = nullptr) {
+    1570          33 :                 size_t deltas = 0;
+    1571          33 :                 bool converged = false;
+    1572          33 :                 do {
+    1573          33 :                         converged = eval(performer);
+    1574          33 :                         deltas++;
+    1575          66 :                 } while (commit() && !converged);
+    1576          33 :                 return deltas;
+    1577             :         }
+    1578             : 
+    1579             :         virtual void debug_info(debug_items *items, debug_scopes *scopes, std::string path, metadata_map &&cell_attrs = {}) {
+    1580             :                 (void)items, (void)scopes, (void)path, (void)cell_attrs;
+    1581             :         }
+    1582             : 
+    1583             :         // Compatibility method.
+    1584             : #if __has_attribute(deprecated)
+    1585             :         __attribute__((deprecated("Use `debug_info(path, &items, /*scopes=*/nullptr);` instead. (`path` could be \"top \".)")))
+    1586             : #endif
+    1587             :         void debug_info(debug_items &items, std::string path) {
+    1588             :                 debug_info(&items, /*scopes=*/nullptr, path);
+    1589             :         }
+    1590             : };
+    1591             : 
+    1592             : } // namespace cxxrtl
+    1593             : 
+    1594             : // Internal structures used to communicate with the implementation of the C interface.
+    1595             : 
+    1596             : typedef struct _cxxrtl_toplevel {
+    1597             :         std::unique_ptr<cxxrtl::module> module;
+    1598             : } *cxxrtl_toplevel;
+    1599             : 
+    1600             : typedef struct _cxxrtl_outline {
+    1601             :         std::function<void()> eval;
+    1602             : } *cxxrtl_outline;
+    1603             : 
+    1604             : // Definitions of internal Yosys cells. Other than the functions in this namespace, CXXRTL is fully generic
+    1605             : // and indepenent of Yosys implementation details.
+    1606             : //
+    1607             : // The `write_cxxrtl` pass translates internal cells (cells with names that start with `$`) to calls of these
+    1608             : // functions. All of Yosys arithmetic and logical cells perform sign or zero extension on their operands,
+    1609             : // whereas basic operations on arbitrary width values require operands to be of the same width. These functions
+    1610             : // bridge the gap by performing the necessary casts. They are named similar to `cell_A[B]`, where A and B are `u`
+    1611             : // if the corresponding operand is unsigned, and `s` if it is signed.
+    1612             : namespace cxxrtl_yosys {
+    1613             : 
+    1614             : using namespace cxxrtl;
+    1615             : 
+    1616             : // std::max isn't constexpr until C++14 for no particular reason (it's an oversight), so we define our own.
+    1617             : template<class T>
+    1618             : CXXRTL_ALWAYS_INLINE
+    1619             : constexpr T max(const T &a, const T &b) {
+    1620             :         return a > b ? a : b;
+    1621             : }
+    1622             : 
+    1623             : // Logic operations
+    1624             : template<size_t BitsY, size_t BitsA>
+    1625             : CXXRTL_ALWAYS_INLINE
+    1626             : value<BitsY> logic_not(const value<BitsA> &a) {
+    1627             :         return value<BitsY> { a ? 0u : 1u };
+    1628             : }
+    1629             : 
+    1630             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1631             : CXXRTL_ALWAYS_INLINE
+    1632             : value<BitsY> logic_and(const value<BitsA> &a, const value<BitsB> &b) {
+    1633             :         return value<BitsY> { (bool(a) && bool(b)) ? 1u : 0u };
+    1634             : }
+    1635             : 
+    1636             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1637             : CXXRTL_ALWAYS_INLINE
+    1638             : value<BitsY> logic_or(const value<BitsA> &a, const value<BitsB> &b) {
+    1639             :         return value<BitsY> { (bool(a) || bool(b)) ? 1u : 0u };
+    1640             : }
+    1641             : 
+    1642             : // Reduction operations
+    1643             : template<size_t BitsY, size_t BitsA>
+    1644             : CXXRTL_ALWAYS_INLINE
+    1645             : value<BitsY> reduce_and(const value<BitsA> &a) {
+    1646             :         return value<BitsY> { a.bit_not().is_zero() ? 1u : 0u };
+    1647             : }
+    1648             : 
+    1649             : template<size_t BitsY, size_t BitsA>
+    1650             : CXXRTL_ALWAYS_INLINE
+    1651             : value<BitsY> reduce_or(const value<BitsA> &a) {
+    1652             :         return value<BitsY> { a ? 1u : 0u };
+    1653             : }
+    1654             : 
+    1655             : template<size_t BitsY, size_t BitsA>
+    1656             : CXXRTL_ALWAYS_INLINE
+    1657             : value<BitsY> reduce_xor(const value<BitsA> &a) {
+    1658             :         return value<BitsY> { (a.ctpop() % 2) ? 1u : 0u };
+    1659             : }
+    1660             : 
+    1661             : template<size_t BitsY, size_t BitsA>
+    1662             : CXXRTL_ALWAYS_INLINE
+    1663             : value<BitsY> reduce_xnor(const value<BitsA> &a) {
+    1664             :         return value<BitsY> { (a.ctpop() % 2) ? 0u : 1u };
+    1665             : }
+    1666             : 
+    1667             : template<size_t BitsY, size_t BitsA>
+    1668             : CXXRTL_ALWAYS_INLINE
+    1669             : value<BitsY> reduce_bool(const value<BitsA> &a) {
+    1670             :         return value<BitsY> { a ? 1u : 0u };
+    1671             : }
+    1672             : 
+    1673             : // Bitwise operations
+    1674             : template<size_t BitsY, size_t BitsA>
+    1675             : CXXRTL_ALWAYS_INLINE
+    1676             : value<BitsY> not_u(const value<BitsA> &a) {
+    1677             :         return a.template zcast<BitsY>().bit_not();
+    1678             : }
+    1679             : 
+    1680             : template<size_t BitsY, size_t BitsA>
+    1681             : CXXRTL_ALWAYS_INLINE
+    1682             : value<BitsY> not_s(const value<BitsA> &a) {
+    1683             :         return a.template scast<BitsY>().bit_not();
+    1684             : }
+    1685             : 
+    1686             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1687             : CXXRTL_ALWAYS_INLINE
+    1688             : value<BitsY> and_uu(const value<BitsA> &a, const value<BitsB> &b) {
+    1689             :         return a.template zcast<BitsY>().bit_and(b.template zcast<BitsY>());
+    1690             : }
+    1691             : 
+    1692             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1693             : CXXRTL_ALWAYS_INLINE
+    1694             : value<BitsY> and_ss(const value<BitsA> &a, const value<BitsB> &b) {
+    1695             :         return a.template scast<BitsY>().bit_and(b.template scast<BitsY>());
+    1696             : }
+    1697             : 
+    1698             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1699             : CXXRTL_ALWAYS_INLINE
+    1700             : value<BitsY> or_uu(const value<BitsA> &a, const value<BitsB> &b) {
+    1701             :         return a.template zcast<BitsY>().bit_or(b.template zcast<BitsY>());
+    1702             : }
+    1703             : 
+    1704             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1705             : CXXRTL_ALWAYS_INLINE
+    1706             : value<BitsY> or_ss(const value<BitsA> &a, const value<BitsB> &b) {
+    1707             :         return a.template scast<BitsY>().bit_or(b.template scast<BitsY>());
+    1708             : }
+    1709             : 
+    1710             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1711             : CXXRTL_ALWAYS_INLINE
+    1712             : value<BitsY> xor_uu(const value<BitsA> &a, const value<BitsB> &b) {
+    1713             :         return a.template zcast<BitsY>().bit_xor(b.template zcast<BitsY>());
+    1714             : }
+    1715             : 
+    1716             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1717             : CXXRTL_ALWAYS_INLINE
+    1718             : value<BitsY> xor_ss(const value<BitsA> &a, const value<BitsB> &b) {
+    1719             :         return a.template scast<BitsY>().bit_xor(b.template scast<BitsY>());
+    1720             : }
+    1721             : 
+    1722             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1723             : CXXRTL_ALWAYS_INLINE
+    1724             : value<BitsY> xnor_uu(const value<BitsA> &a, const value<BitsB> &b) {
+    1725             :         return a.template zcast<BitsY>().bit_xor(b.template zcast<BitsY>()).bit_not();
+    1726             : }
+    1727             : 
+    1728             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1729             : CXXRTL_ALWAYS_INLINE
+    1730             : value<BitsY> xnor_ss(const value<BitsA> &a, const value<BitsB> &b) {
+    1731             :         return a.template scast<BitsY>().bit_xor(b.template scast<BitsY>()).bit_not();
+    1732             : }
+    1733             : 
+    1734             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1735             : CXXRTL_ALWAYS_INLINE
+    1736             : value<BitsY> shl_uu(const value<BitsA> &a, const value<BitsB> &b) {
+    1737             :         return a.template zcast<BitsY>().shl(b);
+    1738             : }
+    1739             : 
+    1740             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1741             : CXXRTL_ALWAYS_INLINE
+    1742             : value<BitsY> shl_su(const value<BitsA> &a, const value<BitsB> &b) {
+    1743             :         return a.template scast<BitsY>().shl(b);
+    1744             : }
+    1745             : 
+    1746             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1747             : CXXRTL_ALWAYS_INLINE
+    1748             : value<BitsY> sshl_uu(const value<BitsA> &a, const value<BitsB> &b) {
+    1749             :         return a.template zcast<BitsY>().shl(b);
+    1750             : }
+    1751             : 
+    1752             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1753             : CXXRTL_ALWAYS_INLINE
+    1754             : value<BitsY> sshl_su(const value<BitsA> &a, const value<BitsB> &b) {
+    1755             :         return a.template scast<BitsY>().shl(b);
+    1756             : }
+    1757             : 
+    1758             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1759             : CXXRTL_ALWAYS_INLINE
+    1760             : value<BitsY> shr_uu(const value<BitsA> &a, const value<BitsB> &b) {
+    1761             :         return a.shr(b).template zcast<BitsY>();
+    1762             : }
+    1763             : 
+    1764             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1765             : CXXRTL_ALWAYS_INLINE
+    1766             : value<BitsY> shr_su(const value<BitsA> &a, const value<BitsB> &b) {
+    1767             :         return a.shr(b).template scast<BitsY>();
+    1768             : }
+    1769             : 
+    1770             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1771             : CXXRTL_ALWAYS_INLINE
+    1772             : value<BitsY> sshr_uu(const value<BitsA> &a, const value<BitsB> &b) {
+    1773             :         return a.shr(b).template zcast<BitsY>();
+    1774             : }
+    1775             : 
+    1776             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1777             : CXXRTL_ALWAYS_INLINE
+    1778             : value<BitsY> sshr_su(const value<BitsA> &a, const value<BitsB> &b) {
+    1779             :         return a.sshr(b).template scast<BitsY>();
+    1780             : }
+    1781             : 
+    1782             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1783             : CXXRTL_ALWAYS_INLINE
+    1784             : value<BitsY> shift_uu(const value<BitsA> &a, const value<BitsB> &b) {
+    1785             :         return shr_uu<BitsY>(a, b);
+    1786             : }
+    1787             : 
+    1788             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1789             : CXXRTL_ALWAYS_INLINE
+    1790             : value<BitsY> shift_su(const value<BitsA> &a, const value<BitsB> &b) {
+    1791             :         return shr_su<BitsY>(a, b);
+    1792             : }
+    1793             : 
+    1794             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1795             : CXXRTL_ALWAYS_INLINE
+    1796             : value<BitsY> shift_us(const value<BitsA> &a, const value<BitsB> &b) {
+    1797             :         return b.is_neg() ? shl_uu<BitsY>(a, b.template sext<BitsB + 1>().neg()) : shr_uu<BitsY>(a, b);
+    1798             : }
+    1799             : 
+    1800             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1801             : CXXRTL_ALWAYS_INLINE
+    1802             : value<BitsY> shift_ss(const value<BitsA> &a, const value<BitsB> &b) {
+    1803             :         return b.is_neg() ? shl_su<BitsY>(a, b.template sext<BitsB + 1>().neg()) : shr_su<BitsY>(a, b);
+    1804             : }
+    1805             : 
+    1806             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1807             : CXXRTL_ALWAYS_INLINE
+    1808             : value<BitsY> shiftx_uu(const value<BitsA> &a, const value<BitsB> &b) {
+    1809             :         return shift_uu<BitsY>(a, b);
+    1810             : }
+    1811             : 
+    1812             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1813             : CXXRTL_ALWAYS_INLINE
+    1814             : value<BitsY> shiftx_su(const value<BitsA> &a, const value<BitsB> &b) {
+    1815             :         return shift_su<BitsY>(a, b);
+    1816             : }
+    1817             : 
+    1818             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1819             : CXXRTL_ALWAYS_INLINE
+    1820             : value<BitsY> shiftx_us(const value<BitsA> &a, const value<BitsB> &b) {
+    1821             :         return shift_us<BitsY>(a, b);
+    1822             : }
+    1823             : 
+    1824             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1825             : CXXRTL_ALWAYS_INLINE
+    1826             : value<BitsY> shiftx_ss(const value<BitsA> &a, const value<BitsB> &b) {
+    1827             :         return shift_ss<BitsY>(a, b);
+    1828             : }
+    1829             : 
+    1830             : // Comparison operations
+    1831             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1832             : CXXRTL_ALWAYS_INLINE
+    1833             : value<BitsY> eq_uu(const value<BitsA> &a, const value<BitsB> &b) {
+    1834             :         constexpr size_t BitsExt = max(BitsA, BitsB);
+    1835             :         return value<BitsY>{ a.template zext<BitsExt>() == b.template zext<BitsExt>() ? 1u : 0u };
+    1836             : }
+    1837             : 
+    1838             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1839             : CXXRTL_ALWAYS_INLINE
+    1840             : value<BitsY> eq_ss(const value<BitsA> &a, const value<BitsB> &b) {
+    1841             :         constexpr size_t BitsExt = max(BitsA, BitsB);
+    1842             :         return value<BitsY>{ a.template sext<BitsExt>() == b.template sext<BitsExt>() ? 1u : 0u };
+    1843             : }
+    1844             : 
+    1845             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1846             : CXXRTL_ALWAYS_INLINE
+    1847             : value<BitsY> ne_uu(const value<BitsA> &a, const value<BitsB> &b) {
+    1848             :         constexpr size_t BitsExt = max(BitsA, BitsB);
+    1849             :         return value<BitsY>{ a.template zext<BitsExt>() != b.template zext<BitsExt>() ? 1u : 0u };
+    1850             : }
+    1851             : 
+    1852             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1853             : CXXRTL_ALWAYS_INLINE
+    1854             : value<BitsY> ne_ss(const value<BitsA> &a, const value<BitsB> &b) {
+    1855             :         constexpr size_t BitsExt = max(BitsA, BitsB);
+    1856             :         return value<BitsY>{ a.template sext<BitsExt>() != b.template sext<BitsExt>() ? 1u : 0u };
+    1857             : }
+    1858             : 
+    1859             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1860             : CXXRTL_ALWAYS_INLINE
+    1861             : value<BitsY> eqx_uu(const value<BitsA> &a, const value<BitsB> &b) {
+    1862             :         return eq_uu<BitsY>(a, b);
+    1863             : }
+    1864             : 
+    1865             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1866             : CXXRTL_ALWAYS_INLINE
+    1867             : value<BitsY> eqx_ss(const value<BitsA> &a, const value<BitsB> &b) {
+    1868             :         return eq_ss<BitsY>(a, b);
+    1869             : }
+    1870             : 
+    1871             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1872             : CXXRTL_ALWAYS_INLINE
+    1873             : value<BitsY> nex_uu(const value<BitsA> &a, const value<BitsB> &b) {
+    1874             :         return ne_uu<BitsY>(a, b);
+    1875             : }
+    1876             : 
+    1877             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1878             : CXXRTL_ALWAYS_INLINE
+    1879             : value<BitsY> nex_ss(const value<BitsA> &a, const value<BitsB> &b) {
+    1880             :         return ne_ss<BitsY>(a, b);
+    1881             : }
+    1882             : 
+    1883             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1884             : CXXRTL_ALWAYS_INLINE
+    1885             : value<BitsY> gt_uu(const value<BitsA> &a, const value<BitsB> &b) {
+    1886             :         constexpr size_t BitsExt = max(BitsA, BitsB);
+    1887             :         return value<BitsY> { b.template zext<BitsExt>().ucmp(a.template zext<BitsExt>()) ? 1u : 0u };
+    1888             : }
+    1889             : 
+    1890             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1891             : CXXRTL_ALWAYS_INLINE
+    1892             : value<BitsY> gt_ss(const value<BitsA> &a, const value<BitsB> &b) {
+    1893             :         constexpr size_t BitsExt = max(BitsA, BitsB);
+    1894             :         return value<BitsY> { b.template sext<BitsExt>().scmp(a.template sext<BitsExt>()) ? 1u : 0u };
+    1895             : }
+    1896             : 
+    1897             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1898             : CXXRTL_ALWAYS_INLINE
+    1899             : value<BitsY> ge_uu(const value<BitsA> &a, const value<BitsB> &b) {
+    1900             :         constexpr size_t BitsExt = max(BitsA, BitsB);
+    1901             :         return value<BitsY> { !a.template zext<BitsExt>().ucmp(b.template zext<BitsExt>()) ? 1u : 0u };
+    1902             : }
+    1903             : 
+    1904             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1905             : CXXRTL_ALWAYS_INLINE
+    1906             : value<BitsY> ge_ss(const value<BitsA> &a, const value<BitsB> &b) {
+    1907             :         constexpr size_t BitsExt = max(BitsA, BitsB);
+    1908             :         return value<BitsY> { !a.template sext<BitsExt>().scmp(b.template sext<BitsExt>()) ? 1u : 0u };
+    1909             : }
+    1910             : 
+    1911             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1912             : CXXRTL_ALWAYS_INLINE
+    1913             : value<BitsY> lt_uu(const value<BitsA> &a, const value<BitsB> &b) {
+    1914             :         constexpr size_t BitsExt = max(BitsA, BitsB);
+    1915             :         return value<BitsY> { a.template zext<BitsExt>().ucmp(b.template zext<BitsExt>()) ? 1u : 0u };
+    1916             : }
+    1917             : 
+    1918             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1919             : CXXRTL_ALWAYS_INLINE
+    1920             : value<BitsY> lt_ss(const value<BitsA> &a, const value<BitsB> &b) {
+    1921             :         constexpr size_t BitsExt = max(BitsA, BitsB);
+    1922             :         return value<BitsY> { a.template sext<BitsExt>().scmp(b.template sext<BitsExt>()) ? 1u : 0u };
+    1923             : }
+    1924             : 
+    1925             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1926             : CXXRTL_ALWAYS_INLINE
+    1927             : value<BitsY> le_uu(const value<BitsA> &a, const value<BitsB> &b) {
+    1928             :         constexpr size_t BitsExt = max(BitsA, BitsB);
+    1929             :         return value<BitsY> { !b.template zext<BitsExt>().ucmp(a.template zext<BitsExt>()) ? 1u : 0u };
+    1930             : }
+    1931             : 
+    1932             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1933             : CXXRTL_ALWAYS_INLINE
+    1934             : value<BitsY> le_ss(const value<BitsA> &a, const value<BitsB> &b) {
+    1935             :         constexpr size_t BitsExt = max(BitsA, BitsB);
+    1936             :         return value<BitsY> { !b.template sext<BitsExt>().scmp(a.template sext<BitsExt>()) ? 1u : 0u };
+    1937             : }
+    1938             : 
+    1939             : // Arithmetic operations
+    1940             : template<size_t BitsY, size_t BitsA>
+    1941             : CXXRTL_ALWAYS_INLINE
+    1942             : value<BitsY> pos_u(const value<BitsA> &a) {
+    1943             :         return a.template zcast<BitsY>();
+    1944             : }
+    1945             : 
+    1946             : template<size_t BitsY, size_t BitsA>
+    1947             : CXXRTL_ALWAYS_INLINE
+    1948             : value<BitsY> pos_s(const value<BitsA> &a) {
+    1949             :         return a.template scast<BitsY>();
+    1950             : }
+    1951             : 
+    1952             : template<size_t BitsY, size_t BitsA>
+    1953             : CXXRTL_ALWAYS_INLINE
+    1954             : value<BitsY> neg_u(const value<BitsA> &a) {
+    1955             :         return a.template zcast<BitsY>().neg();
+    1956             : }
+    1957             : 
+    1958             : template<size_t BitsY, size_t BitsA>
+    1959             : CXXRTL_ALWAYS_INLINE
+    1960             : value<BitsY> neg_s(const value<BitsA> &a) {
+    1961             :         return a.template scast<BitsY>().neg();
+    1962             : }
+    1963             : 
+    1964             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1965             : CXXRTL_ALWAYS_INLINE
+    1966          33 : value<BitsY> add_uu(const value<BitsA> &a, const value<BitsB> &b) {
+    1967          33 :         return a.template zcast<BitsY>().add(b.template zcast<BitsY>());
+    1968             : }
+    1969             : 
+    1970             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1971             : CXXRTL_ALWAYS_INLINE
+    1972             : value<BitsY> add_ss(const value<BitsA> &a, const value<BitsB> &b) {
+    1973             :         return a.template scast<BitsY>().add(b.template scast<BitsY>());
+    1974             : }
+    1975             : 
+    1976             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1977             : CXXRTL_ALWAYS_INLINE
+    1978             : value<BitsY> sub_uu(const value<BitsA> &a, const value<BitsB> &b) {
+    1979             :         return a.template zcast<BitsY>().sub(b.template zcast<BitsY>());
+    1980             : }
+    1981             : 
+    1982             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1983             : CXXRTL_ALWAYS_INLINE
+    1984             : value<BitsY> sub_ss(const value<BitsA> &a, const value<BitsB> &b) {
+    1985             :         return a.template scast<BitsY>().sub(b.template scast<BitsY>());
+    1986             : }
+    1987             : 
+    1988             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1989             : CXXRTL_ALWAYS_INLINE
+    1990             : value<BitsY> mul_uu(const value<BitsA> &a, const value<BitsB> &b) {
+    1991             :         constexpr size_t BitsM = BitsA >= BitsB ? BitsA : BitsB;
+    1992             :         return a.template zcast<BitsM>().template mul<BitsY>(b.template zcast<BitsM>());
+    1993             : }
+    1994             : 
+    1995             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    1996             : CXXRTL_ALWAYS_INLINE
+    1997             : value<BitsY> mul_ss(const value<BitsA> &a, const value<BitsB> &b) {
+    1998             :         return a.template scast<BitsY>().template mul<BitsY>(b.template scast<BitsY>());
+    1999             : }
+    2000             : 
+    2001             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    2002             : CXXRTL_ALWAYS_INLINE
+    2003             : std::pair<value<BitsY>, value<BitsY>> divmod_uu(const value<BitsA> &a, const value<BitsB> &b) {
+    2004             :         constexpr size_t Bits = max(BitsY, max(BitsA, BitsB));
+    2005             :         value<Bits> quotient;
+    2006             :         value<Bits> remainder;
+    2007             :         value<Bits> dividend = a.template zext<Bits>();
+    2008             :         value<Bits> divisor = b.template zext<Bits>();
+    2009             :         std::tie(quotient, remainder) = dividend.udivmod(divisor);
+    2010             :         return {quotient.template trunc<BitsY>(), remainder.template trunc<BitsY>()};
+    2011             : }
+    2012             : 
+    2013             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    2014             : CXXRTL_ALWAYS_INLINE
+    2015             : std::pair<value<BitsY>, value<BitsY>> divmod_ss(const value<BitsA> &a, const value<BitsB> &b) {
+    2016             :         constexpr size_t Bits = max(BitsY, max(BitsA, BitsB));
+    2017             :         value<Bits> quotient;
+    2018             :         value<Bits> remainder;
+    2019             :         value<Bits> dividend = a.template sext<Bits>();
+    2020             :         value<Bits> divisor = b.template sext<Bits>();
+    2021             :         std::tie(quotient, remainder) = dividend.sdivmod(divisor);
+    2022             :         return {quotient.template trunc<BitsY>(), remainder.template trunc<BitsY>()};
+    2023             : }
+    2024             : 
+    2025             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    2026             : CXXRTL_ALWAYS_INLINE
+    2027             : value<BitsY> div_uu(const value<BitsA> &a, const value<BitsB> &b) {
+    2028             :         return divmod_uu<BitsY>(a, b).first;
+    2029             : }
+    2030             : 
+    2031             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    2032             : CXXRTL_ALWAYS_INLINE
+    2033             : value<BitsY> div_ss(const value<BitsA> &a, const value<BitsB> &b) {
+    2034             :         return divmod_ss<BitsY>(a, b).first;
+    2035             : }
+    2036             : 
+    2037             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    2038             : CXXRTL_ALWAYS_INLINE
+    2039             : value<BitsY> mod_uu(const value<BitsA> &a, const value<BitsB> &b) {
+    2040             :         return divmod_uu<BitsY>(a, b).second;
+    2041             : }
+    2042             : 
+    2043             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    2044             : CXXRTL_ALWAYS_INLINE
+    2045             : value<BitsY> mod_ss(const value<BitsA> &a, const value<BitsB> &b) {
+    2046             :         return divmod_ss<BitsY>(a, b).second;
+    2047             : }
+    2048             : 
+    2049             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    2050             : CXXRTL_ALWAYS_INLINE
+    2051             : value<BitsY> modfloor_uu(const value<BitsA> &a, const value<BitsB> &b) {
+    2052             :         return divmod_uu<BitsY>(a, b).second;
+    2053             : }
+    2054             : 
+    2055             : // GHDL Modfloor operator. Returns r=a mod b, such that r has the same sign as b and
+    2056             : // a=b*N+r where N is some integer
+    2057             : // In practical terms, when a and b have different signs and the remainder returned by divmod_ss is not 0
+    2058             : // then return the remainder + b
+    2059             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    2060             : CXXRTL_ALWAYS_INLINE
+    2061             : value<BitsY> modfloor_ss(const value<BitsA> &a, const value<BitsB> &b) {
+    2062             :         value<BitsY> r;
+    2063             :         r = divmod_ss<BitsY>(a, b).second;
+    2064             :         if((b.is_neg() != a.is_neg()) && !r.is_zero())
+    2065             :                 return add_ss<BitsY>(b, r);
+    2066             :         return r;
+    2067             : }
+    2068             : 
+    2069             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    2070             : CXXRTL_ALWAYS_INLINE
+    2071             : value<BitsY> divfloor_uu(const value<BitsA> &a, const value<BitsB> &b) {
+    2072             :         return divmod_uu<BitsY>(a, b).first;
+    2073             : }
+    2074             : 
+    2075             : // Divfloor. Similar to above: returns q=a//b, where q has the sign of a*b and a=b*q+N.
+    2076             : // In other words, returns (truncating) a/b, except if a and b have different signs
+    2077             : // and there's non-zero remainder, subtract one more towards floor.
+    2078             : template<size_t BitsY, size_t BitsA, size_t BitsB>
+    2079             : CXXRTL_ALWAYS_INLINE
+    2080             : value<BitsY> divfloor_ss(const value<BitsA> &a, const value<BitsB> &b) {
+    2081             :         value<BitsY> q, r;
+    2082             :         std::tie(q, r) = divmod_ss<BitsY>(a, b);
+    2083             :         if ((b.is_neg() != a.is_neg()) && !r.is_zero())
+    2084             :                 return sub_uu<BitsY>(q, value<1> { 1u });
+    2085             :         return q;
+    2086             : 
+    2087             : }
+    2088             : 
+    2089             : // Memory helper
+    2090             : struct memory_index {
+    2091             :         bool valid;
+    2092             :         size_t index;
+    2093             : 
+    2094             :         template<size_t BitsAddr>
+    2095             :         memory_index(const value<BitsAddr> &addr, size_t offset, size_t depth) {
+    2096             :                 static_assert(value<BitsAddr>::chunks <= 1, "memory address is too wide");
+    2097             :                 size_t offset_index = addr.data[0];
+    2098             : 
+    2099             :                 valid = (offset_index >= offset && offset_index < offset + depth);
+    2100             :                 index = offset_index - offset;
+    2101             :         }
+    2102             : };
+    2103             : 
+    2104             : } // namespace cxxrtl_yosys
+    2105             : 
+    2106             : #endif
+
+
+
+ + + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h.func-sort-c.html b/tests/functional/coverage_report/home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h.func-sort-c.html new file mode 100644 index 00000000000..cf6db54ca95 --- /dev/null +++ b/tests/functional/coverage_report/home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h.func-sort-c.html @@ -0,0 +1,136 @@ + + + + + + + LCOV - vcd_harness.info - /home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl - cxxrtl_vcd.h (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:11216070.0 %
Date:1980-01-01 00:00:00Functions:151693.8 %
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN6cxxrtl10vcd_writer11emit_vectorERKNS0_8variableE0
_ZN6cxxrtl10vcd_writer14emit_timescaleEjRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE3
_ZN6cxxrtl10vcd_writer19emit_enddefinitionsEv3
_ZN6cxxrtl10vcd_writer3addIZNS0_20add_without_memoriesERKNS_11debug_itemsEEUlRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKNS_10debug_itemEE_EEvS4_RKT_3
_ZN6cxxrtl10vcd_writer15split_hierarchyERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE9
_ZN6cxxrtl10vcd_writer17register_variableEmPjbP15_cxxrtl_outline9
_ZN6cxxrtl10vcd_writer3addERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKNS_10debug_itemEb9
_ZN6cxxrtl10vcd_writer8emit_varERKNS0_8variableERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESB_mb9
_ZN6cxxrtl10vcd_writer9emit_nameERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE9
_ZN6cxxrtl10vcd_writer10emit_scopeERKSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS7_EE12
_ZN6cxxrtl10vcd_writer14reset_outlinesEv33
_ZN6cxxrtl10vcd_writer6sampleEm33
_ZN6cxxrtl10vcd_writer9emit_timeEm33
_ZN6cxxrtl10vcd_writer11emit_scalarERKNS0_8variableE51
_ZN6cxxrtl10vcd_writer10emit_identEm60
_ZN6cxxrtl10vcd_writer13test_variableERKNS0_8variableE99
+
+
+ + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h.func.html b/tests/functional/coverage_report/home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h.func.html new file mode 100644 index 00000000000..5ceeb75a190 --- /dev/null +++ b/tests/functional/coverage_report/home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h.func.html @@ -0,0 +1,136 @@ + + + + + + + LCOV - vcd_harness.info - /home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl - cxxrtl_vcd.h (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:11216070.0 %
Date:1980-01-01 00:00:00Functions:151693.8 %
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN6cxxrtl10vcd_writer10emit_identEm60
_ZN6cxxrtl10vcd_writer10emit_scopeERKSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS7_EE12
_ZN6cxxrtl10vcd_writer11emit_scalarERKNS0_8variableE51
_ZN6cxxrtl10vcd_writer11emit_vectorERKNS0_8variableE0
_ZN6cxxrtl10vcd_writer13test_variableERKNS0_8variableE99
_ZN6cxxrtl10vcd_writer14emit_timescaleEjRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE3
_ZN6cxxrtl10vcd_writer14reset_outlinesEv33
_ZN6cxxrtl10vcd_writer15split_hierarchyERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE9
_ZN6cxxrtl10vcd_writer17register_variableEmPjbP15_cxxrtl_outline9
_ZN6cxxrtl10vcd_writer19emit_enddefinitionsEv3
_ZN6cxxrtl10vcd_writer3addERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKNS_10debug_itemEb9
_ZN6cxxrtl10vcd_writer3addIZNS0_20add_without_memoriesERKNS_11debug_itemsEEUlRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKNS_10debug_itemEE_EEvS4_RKT_3
_ZN6cxxrtl10vcd_writer6sampleEm33
_ZN6cxxrtl10vcd_writer8emit_varERKNS0_8variableERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESB_mb9
_ZN6cxxrtl10vcd_writer9emit_nameERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE9
_ZN6cxxrtl10vcd_writer9emit_timeEm33
+
+
+ + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h.gcov.html b/tests/functional/coverage_report/home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h.gcov.html new file mode 100644 index 00000000000..79fb13319cd --- /dev/null +++ b/tests/functional/coverage_report/home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h.gcov.html @@ -0,0 +1,351 @@ + + + + + + + LCOV - vcd_harness.info - /home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl - cxxrtl_vcd.h (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:11216070.0 %
Date:1980-01-01 00:00:00Functions:151693.8 %
+
+ + + + + + + + +

+
          Line data    Source code
+
+       1             : /*
+       2             :  *  yosys -- Yosys Open SYnthesis Suite
+       3             :  *
+       4             :  *  Copyright (C) 2020  whitequark <whitequark@whitequark.org>
+       5             :  *
+       6             :  *  Permission to use, copy, modify, and/or distribute this software for any
+       7             :  *  purpose with or without fee is hereby granted.
+       8             :  *
+       9             :  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+      10             :  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+      11             :  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+      12             :  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+      13             :  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+      14             :  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+      15             :  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+      16             :  *
+      17             :  */
+      18             : 
+      19             : #ifndef CXXRTL_VCD_H
+      20             : #define CXXRTL_VCD_H
+      21             : 
+      22             : #include <cxxrtl/cxxrtl.h>
+      23             : 
+      24             : namespace cxxrtl {
+      25             : 
+      26             : class vcd_writer {
+      27             :         struct variable {
+      28             :                 size_t ident;
+      29             :                 size_t width;
+      30             :                 chunk_t *curr;
+      31             :                 size_t cache_offset;
+      32             :                 debug_outline *outline;
+      33             :                 bool *outline_warm;
+      34             :         };
+      35             : 
+      36             :         std::vector<std::string> current_scope;
+      37             :         std::map<debug_outline*, bool> outlines;
+      38             :         std::vector<variable> variables;
+      39             :         std::vector<chunk_t> cache;
+      40             :         std::map<chunk_t*, size_t> aliases;
+      41             :         bool streaming = false;
+      42             : 
+      43           3 :         void emit_timescale(unsigned number, const std::string &unit) {
+      44           3 :                 assert(!streaming);
+      45           3 :                 assert(number == 1 || number == 10 || number == 100);
+      46           3 :                 assert(unit == "s" || unit == "ms" || unit == "us" ||
+      47             :                        unit == "ns" || unit == "ps" || unit == "fs");
+      48          12 :                 buffer += "$timescale " + std::to_string(number) + " " + unit + " $end\n";
+      49           3 :         }
+      50             : 
+      51          12 :         void emit_scope(const std::vector<std::string> &scope) {
+      52          12 :                 assert(!streaming);
+      53          12 :                 while (current_scope.size() > scope.size() ||
+      54          12 :                        (current_scope.size() > 0 &&
+      55           0 :                         current_scope[current_scope.size() - 1] != scope[current_scope.size() - 1])) {
+      56           0 :                         buffer += "$upscope $end\n";
+      57           0 :                         current_scope.pop_back();
+      58             :                 }
+      59          12 :                 while (current_scope.size() < scope.size()) {
+      60           0 :                         buffer += "$scope module " + scope[current_scope.size()] + " $end\n";
+      61           0 :                         current_scope.push_back(scope[current_scope.size()]);
+      62             :                 }
+      63          12 :         }
+      64             : 
+      65          60 :         void emit_ident(size_t ident) {
+      66          60 :                 do {
+      67          60 :                         buffer += '!' + ident % 94; // "base94"
+      68          60 :                         ident /= 94;
+      69          60 :                 } while (ident != 0);
+      70          60 :         }
+      71             : 
+      72           9 :         void emit_name(const std::string &name) {
+      73          24 :                 for (char c : name) {
+      74          15 :                         if (c == ':') {
+      75             :                                 // Due to a bug, GTKWave cannot parse a colon in the variable name, causing the VCD file
+      76             :                                 // to be unreadable. It cannot be escaped either, so replace it with the sideways colon.
+      77           0 :                                 buffer += "..";
+      78             :                         } else {
+      79          30 :                                 buffer += c;
+      80             :                         }
+      81             :                 }
+      82           9 :         }
+      83             : 
+      84           9 :         void emit_var(const variable &var, const std::string &type, const std::string &name,
+      85             :                       size_t lsb_at, bool multipart) {
+      86           9 :                 assert(!streaming);
+      87          36 :                 buffer += "$var " + type + " " + std::to_string(var.width) + " ";
+      88           9 :                 emit_ident(var.ident);
+      89           9 :                 buffer += " ";
+      90           9 :                 emit_name(name);
+      91           9 :                 if (multipart || name.back() == ']' || lsb_at != 0) {
+      92           0 :                         if (var.width == 1)
+      93           0 :                                 buffer += " [" + std::to_string(lsb_at) + "]";
+      94             :                         else
+      95           0 :                                 buffer += " [" + std::to_string(lsb_at + var.width - 1) + ":" + std::to_string(lsb_at) + "]";
+      96             :                 }
+      97           9 :                 buffer += " $end\n";
+      98           9 :         }
+      99             : 
+     100           3 :         void emit_enddefinitions() {
+     101           3 :                 assert(!streaming);
+     102           3 :                 buffer += "$enddefinitions $end\n";
+     103           3 :                 streaming = true;
+     104           3 :         }
+     105             : 
+     106          33 :         void emit_time(uint64_t timestamp) {
+     107          33 :                 assert(streaming);
+     108          99 :                 buffer += "#" + std::to_string(timestamp) + "\n";
+     109          33 :         }
+     110             : 
+     111          51 :         void emit_scalar(const variable &var) {
+     112          51 :                 assert(streaming);
+     113          51 :                 assert(var.width == 1);
+     114          78 :                 buffer += (*var.curr ? '1' : '0');
+     115          51 :                 emit_ident(var.ident);
+     116          51 :                 buffer += '\n';
+     117          51 :         }
+     118             : 
+     119           0 :         void emit_vector(const variable &var) {
+     120           0 :                 assert(streaming);
+     121           0 :                 buffer += 'b';
+     122           0 :                 for (size_t bit = var.width - 1; bit != (size_t)-1; bit--) {
+     123           0 :                         bool bit_curr = var.curr[bit / (8 * sizeof(chunk_t))] & (1 << (bit % (8 * sizeof(chunk_t))));
+     124           0 :                         buffer += (bit_curr ? '1' : '0');
+     125             :                 }
+     126           0 :                 buffer += ' ';
+     127           0 :                 emit_ident(var.ident);
+     128           0 :                 buffer += '\n';
+     129           0 :         }
+     130             : 
+     131          33 :         void reset_outlines() {
+     132          66 :                 for (auto &outline_it : outlines)
+     133          33 :                         outline_it.second = /*warm=*/(outline_it.first == nullptr);
+     134          33 :         }
+     135             : 
+     136           9 :         variable &register_variable(size_t width, chunk_t *curr, bool constant = false, debug_outline *outline = nullptr) {
+     137           9 :                 if (aliases.count(curr)) {
+     138           0 :                         return variables[aliases[curr]];
+     139             :                 } else {
+     140           9 :                         auto outline_it = outlines.emplace(outline, /*warm=*/(outline == nullptr)).first;
+     141           9 :                         const size_t chunks = (width + (sizeof(chunk_t) * 8 - 1)) / (sizeof(chunk_t) * 8);
+     142           9 :                         aliases[curr] = variables.size();
+     143           9 :                         if (constant) {
+     144           0 :                                 variables.emplace_back(variable { variables.size(), width, curr, (size_t)-1, outline_it->first, &outline_it->second });
+     145             :                         } else {
+     146           9 :                                 variables.emplace_back(variable { variables.size(), width, curr, cache.size(), outline_it->first, &outline_it->second });
+     147           9 :                                 cache.insert(cache.end(), &curr[0], &curr[chunks]);
+     148             :                         }
+     149           9 :                         return variables.back();
+     150             :                 }
+     151             :         }
+     152             : 
+     153          99 :         bool test_variable(const variable &var) {
+     154          99 :                 if (var.cache_offset == (size_t)-1)
+     155             :                         return false; // constant
+     156          99 :                 if (!*var.outline_warm) {
+     157           0 :                         var.outline->eval();
+     158           0 :                         *var.outline_warm = true;
+     159             :                 }
+     160          99 :                 const size_t chunks = (var.width + (sizeof(chunk_t) * 8 - 1)) / (sizeof(chunk_t) * 8);
+     161          99 :                 if (std::equal(&var.curr[0], &var.curr[chunks], &cache[var.cache_offset])) {
+     162             :                         return false;
+     163             :                 } else {
+     164          42 :                         std::copy(&var.curr[0], &var.curr[chunks], &cache[var.cache_offset]);
+     165          42 :                         return true;
+     166             :                 }
+     167             :         }
+     168             : 
+     169           9 :         static std::vector<std::string> split_hierarchy(const std::string &hier_name) {
+     170           9 :                 std::vector<std::string> hierarchy;
+     171           9 :                 size_t prev = 0;
+     172           9 :                 while (true) {
+     173           9 :                         size_t curr = hier_name.find_first_of(' ', prev);
+     174           9 :                         if (curr == std::string::npos) {
+     175          18 :                                 hierarchy.push_back(hier_name.substr(prev));
+     176           9 :                                 break;
+     177             :                         } else {
+     178           0 :                                 hierarchy.push_back(hier_name.substr(prev, curr - prev));
+     179           0 :                                 prev = curr + 1;
+     180             :                         }
+     181           0 :                 }
+     182           9 :                 return hierarchy;
+     183           0 :         }
+     184             : 
+     185             : public:
+     186             :         std::string buffer;
+     187             : 
+     188           3 :         void timescale(unsigned number, const std::string &unit) {
+     189           3 :                 emit_timescale(number, unit);
+     190           3 :         }
+     191             : 
+     192           9 :         void add(const std::string &hier_name, const debug_item &item, bool multipart = false) {
+     193           9 :                 std::vector<std::string> scope = split_hierarchy(hier_name);
+     194           9 :                 std::string name = scope.back();
+     195           9 :                 scope.pop_back();
+     196             : 
+     197           9 :                 emit_scope(scope);
+     198           9 :                 switch (item.type) {
+     199             :                         // Not the best naming but oh well...
+     200           9 :                         case debug_item::VALUE:
+     201          18 :                                 emit_var(register_variable(item.width, item.curr, /*constant=*/item.next == nullptr),
+     202           9 :                                          "wire", name, item.lsb_at, multipart);
+     203           9 :                                 break;
+     204           0 :                         case debug_item::WIRE:
+     205           0 :                                 emit_var(register_variable(item.width, item.curr),
+     206           0 :                                          "reg", name, item.lsb_at, multipart);
+     207           0 :                                 break;
+     208           0 :                         case debug_item::MEMORY: {
+     209           0 :                                 const size_t stride = (item.width + (sizeof(chunk_t) * 8 - 1)) / (sizeof(chunk_t) * 8);
+     210           0 :                                 for (size_t index = 0; index < item.depth; index++) {
+     211           0 :                                         chunk_t *nth_curr = &item.curr[stride * index];
+     212           0 :                                         std::string nth_name = name + '[' + std::to_string(index) + ']';
+     213           0 :                                         emit_var(register_variable(item.width, nth_curr),
+     214           0 :                                                  "reg", nth_name, item.lsb_at, multipart);
+     215           0 :                                 }
+     216             :                                 break;
+     217             :                         }
+     218           0 :                         case debug_item::ALIAS:
+     219             :                                 // Like VALUE, but, even though `item.next == nullptr` always holds, the underlying value
+     220             :                                 // can actually change, and must be tracked. In most cases the VCD identifier will be
+     221             :                                 // unified with the aliased reg, but we should handle the case where only the alias is
+     222             :                                 // added to the VCD writer, too.
+     223           0 :                                 emit_var(register_variable(item.width, item.curr),
+     224           0 :                                          "wire", name, item.lsb_at, multipart);
+     225           0 :                                 break;
+     226           0 :                         case debug_item::OUTLINE:
+     227           0 :                                 emit_var(register_variable(item.width, item.curr, /*constant=*/false, item.outline),
+     228           0 :                                          "wire", name, item.lsb_at, multipart);
+     229           0 :                                 break;
+     230             :                 }
+     231           9 :         }
+     232             : 
+     233             :         template<class Filter>
+     234           3 :         void add(const debug_items &items, const Filter &filter) {
+     235             :                 // `debug_items` is a map, so the items are already sorted in an order optimal for emitting
+     236             :                 // VCD scope sections.
+     237          12 :                 for (auto &it : items.table)
+     238          18 :                         for (auto &part : it.second)
+     239           9 :                                 if (filter(it.first, part))
+     240           9 :                                         add(it.first, part, it.second.size() > 1);
+     241           3 :         }
+     242             : 
+     243             :         void add(const debug_items &items) {
+     244             :                 this->add(items, [](const std::string &, const debug_item &) {
+     245             :                         return true;
+     246             :                 });
+     247             :         }
+     248             : 
+     249           3 :         void add_without_memories(const debug_items &items) {
+     250           3 :                 this->add(items, [](const std::string &, const debug_item &item) {
+     251           9 :                         return item.type != debug_item::MEMORY;
+     252             :                 });
+     253             :         }
+     254             : 
+     255          33 :         void sample(uint64_t timestamp) {
+     256          33 :                 bool first_sample = !streaming;
+     257          33 :                 if (first_sample) {
+     258           3 :                         emit_scope({});
+     259           3 :                         emit_enddefinitions();
+     260             :                 }
+     261          33 :                 reset_outlines();
+     262          33 :                 emit_time(timestamp);
+     263         132 :                 for (auto var : variables)
+     264          99 :                         if (test_variable(var) || first_sample) {
+     265          51 :                                 if (var.width == 1)
+     266          51 :                                         emit_scalar(var);
+     267             :                                 else
+     268           0 :                                         emit_vector(var);
+     269             :                         }
+     270          33 :         }
+     271             : };
+     272             : 
+     273             : }
+     274             : 
+     275             : #endif
+
+
+
+ + + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl/index-sort-f.html b/tests/functional/coverage_report/home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl/index-sort-f.html new file mode 100644 index 00000000000..c99c203f1d4 --- /dev/null +++ b/tests/functional/coverage_report/home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl/index-sort-f.html @@ -0,0 +1,103 @@ + + + + + + + LCOV - vcd_harness.info - /home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - /home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtlHitTotalCoverage
Test:vcd_harness.infoLines:20227872.7 %
Date:1980-01-01 00:00:00Functions:222588.0 %
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
cxxrtl.h +
76.3%76.3%
+ 		76.3 %90 / 11877.8 %7 / 9
cxxrtl_vcd.h +
70.0%70.0%
+ 		70.0 %112 / 16093.8 %15 / 16
+
+
+ + + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl/index-sort-l.html b/tests/functional/coverage_report/home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl/index-sort-l.html new file mode 100644 index 00000000000..540500d9b36 --- /dev/null +++ b/tests/functional/coverage_report/home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl/index-sort-l.html @@ -0,0 +1,103 @@ + + + + + + + LCOV - vcd_harness.info - /home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - /home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtlHitTotalCoverage
Test:vcd_harness.infoLines:20227872.7 %
Date:1980-01-01 00:00:00Functions:222588.0 %
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
cxxrtl_vcd.h +
70.0%70.0%
+ 		70.0 %112 / 16093.8 %15 / 16
cxxrtl.h +
76.3%76.3%
+ 		76.3 %90 / 11877.8 %7 / 9
+
+
+ + + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl/index.html b/tests/functional/coverage_report/home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl/index.html new file mode 100644 index 00000000000..cb7c4a6f2f4 --- /dev/null +++ b/tests/functional/coverage_report/home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl/index.html @@ -0,0 +1,103 @@ + + + + + + + LCOV - vcd_harness.info - /home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - /home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtlHitTotalCoverage
Test:vcd_harness.infoLines:20227872.7 %
Date:1980-01-01 00:00:00Functions:222588.0 %
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
cxxrtl.h +
76.3%76.3%
+ 		76.3 %90 / 11877.8 %7 / 9
cxxrtl_vcd.h +
70.0%70.0%
+ 		70.0 %112 / 16093.8 %15 / 16
+
+
+ + + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/home/roland/my_yosys/backends/functional/cxx_runtime/index-sort-f.html b/tests/functional/coverage_report/home/roland/my_yosys/backends/functional/cxx_runtime/index-sort-f.html new file mode 100644 index 00000000000..d2049083e2e --- /dev/null +++ b/tests/functional/coverage_report/home/roland/my_yosys/backends/functional/cxx_runtime/index-sort-f.html @@ -0,0 +1,93 @@ + + + + + + + LCOV - vcd_harness.info - /home/roland/my_yosys/backends/functional/cxx_runtime + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - /home/roland/my_yosys/backends/functional/cxx_runtimeHitTotalCoverage
Test:vcd_harness.infoLines:88100.0 %
Date:1980-01-01 00:00:00Functions:00-
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+ +
+ + + + + + + + + + + + + + + + + + + + + + + + +

Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
sim.h +
100.0%
+ 		100.0 %8 / 8-0 / 0
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+
+ + + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/home/roland/my_yosys/backends/functional/cxx_runtime/index-sort-l.html b/tests/functional/coverage_report/home/roland/my_yosys/backends/functional/cxx_runtime/index-sort-l.html new file mode 100644 index 00000000000..9b62553938b --- /dev/null +++ b/tests/functional/coverage_report/home/roland/my_yosys/backends/functional/cxx_runtime/index-sort-l.html @@ -0,0 +1,93 @@ + + + + + + + LCOV - vcd_harness.info - /home/roland/my_yosys/backends/functional/cxx_runtime + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - /home/roland/my_yosys/backends/functional/cxx_runtimeHitTotalCoverage
Test:vcd_harness.infoLines:88100.0 %
Date:1980-01-01 00:00:00Functions:00-
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
sim.h +
100.0%
+ 		100.0 %8 / 8-0 / 0
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+
+ + + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/home/roland/my_yosys/backends/functional/cxx_runtime/index.html b/tests/functional/coverage_report/home/roland/my_yosys/backends/functional/cxx_runtime/index.html new file mode 100644 index 00000000000..fdffcc1bd9d --- /dev/null +++ b/tests/functional/coverage_report/home/roland/my_yosys/backends/functional/cxx_runtime/index.html @@ -0,0 +1,93 @@ + + + + + + + LCOV - vcd_harness.info - /home/roland/my_yosys/backends/functional/cxx_runtime + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - /home/roland/my_yosys/backends/functional/cxx_runtimeHitTotalCoverage
Test:vcd_harness.infoLines:88100.0 %
Date:1980-01-01 00:00:00Functions:00-
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
sim.h +
100.0%
+ 		100.0 %8 / 8-0 / 0
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+
+ + + + +
Generated by: LCOV version 1.0
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+ + + diff --git a/tests/functional/coverage_report/home/roland/my_yosys/backends/functional/cxx_runtime/sim.h.func-sort-c.html b/tests/functional/coverage_report/home/roland/my_yosys/backends/functional/cxx_runtime/sim.h.func-sort-c.html new file mode 100644 index 00000000000..f4433ccc8b5 --- /dev/null +++ b/tests/functional/coverage_report/home/roland/my_yosys/backends/functional/cxx_runtime/sim.h.func-sort-c.html @@ -0,0 +1,72 @@ + + + + + + + LCOV - vcd_harness.info - /home/roland/my_yosys/backends/functional/cxx_runtime/sim.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - home/roland/my_yosys/backends/functional/cxx_runtime - sim.h (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:88100.0 %
Date:1980-01-01 00:00:00Functions:00-
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Function Name Sort by function nameHit count Sort by hit count
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Generated by: LCOV version 1.0
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+ + + diff --git a/tests/functional/coverage_report/home/roland/my_yosys/backends/functional/cxx_runtime/sim.h.func.html b/tests/functional/coverage_report/home/roland/my_yosys/backends/functional/cxx_runtime/sim.h.func.html new file mode 100644 index 00000000000..27443d08173 --- /dev/null +++ b/tests/functional/coverage_report/home/roland/my_yosys/backends/functional/cxx_runtime/sim.h.func.html @@ -0,0 +1,72 @@ + + + + + + + LCOV - vcd_harness.info - /home/roland/my_yosys/backends/functional/cxx_runtime/sim.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - home/roland/my_yosys/backends/functional/cxx_runtime - sim.h (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:88100.0 %
Date:1980-01-01 00:00:00Functions:00-
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+ + + + + + +

Function Name Sort by function nameHit count Sort by hit count
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Generated by: LCOV version 1.0
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+ + + diff --git a/tests/functional/coverage_report/home/roland/my_yosys/backends/functional/cxx_runtime/sim.h.gcov.html b/tests/functional/coverage_report/home/roland/my_yosys/backends/functional/cxx_runtime/sim.h.gcov.html new file mode 100644 index 00000000000..7f21dcee36c --- /dev/null +++ b/tests/functional/coverage_report/home/roland/my_yosys/backends/functional/cxx_runtime/sim.h.gcov.html @@ -0,0 +1,444 @@ + + + + + + + LCOV - vcd_harness.info - /home/roland/my_yosys/backends/functional/cxx_runtime/sim.h + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - home/roland/my_yosys/backends/functional/cxx_runtime - sim.h (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:88100.0 %
Date:1980-01-01 00:00:00Functions:00-
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+
          Line data    Source code
+
+       1             : /*
+       2             :  *  yosys -- Yosys Open SYnthesis Suite
+       3             :  *
+       4             :  *  Copyright (C) 2024  Emily Schmidt <emily@yosyshq.com>
+       5             :  *
+       6             :  *  Permission to use, copy, modify, and/or distribute this software for any
+       7             :  *  purpose with or without fee is hereby granted, provided that the above
+       8             :  *  copyright notice and this permission notice appear in all copies.
+       9             :  *
+      10             :  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+      11             :  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+      12             :  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+      13             :  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+      14             :  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+      15             :  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+      16             :  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+      17             :  *
+      18             :  */
+      19             : 
+      20             : #ifndef SIM_H
+      21             : #define SIM_H
+      22             : 
+      23             : #include <array>
+      24             : #include <cstdint>
+      25             : #include <cassert>
+      26             : 
+      27             : template<size_t n>
+      28             : using Signal = std::array<bool, n>;
+      29             : 
+      30             : template<size_t n, size_t m>
+      31             : Signal<n> slice(Signal<m> const& a, size_t offset)
+      32             : {
+      33             :     Signal<n> ret;
+      34             : 
+      35             :     std::copy(a.begin() + offset, a.begin() + offset + n, ret.begin());
+      36             :     return ret;
+      37             : }
+      38             : 
+      39             : template<size_t n>
+      40          30 : Signal<n> $const(uint32_t val)
+      41             : {
+      42             :     size_t i;
+      43             :     Signal<n> ret;
+      44             : 
+      45          30 :     for(i = 0; i < n; i++)
+      46             :         if(i < 32)
+      47          33 :             ret[i] = val & (1<<i);
+      48             :         else
+      49             :             ret[i] = false;
+      50             :     return ret;
+      51             : }
+      52             : 
+      53             : template<size_t n>
+      54             : Signal<n> $const(std::initializer_list<uint32_t> vals)
+      55             : {
+      56             :     size_t k, i;
+      57             :     Signal<n> ret;
+      58             : 
+      59             :     k = 0;
+      60             :     for (auto val : vals) {
+      61             :         for(i = 0; i < 32; i++)
+      62             :             if(i + k < n)
+      63             :                 ret[i + k] = val & (1<<i);
+      64             :         k += 32;
+      65             :     }
+      66             :     for(; k < n; k++)
+      67             :         ret[k] = false;
+      68             :     return ret;
+      69             : }
+      70             : 
+      71             : template<size_t n>
+      72             : bool as_bool(Signal<n> sig)
+      73             : {
+      74             :     for(int i = 0; i < n; i++)
+      75             :         if(sig[i])
+      76             :             return true;
+      77             :     return false;
+      78             : }
+      79             : 
+      80             : template<size_t n>
+      81             : uint32_t as_int(Signal<n> sig)
+      82             : {
+      83             :     uint32_t ret = 0;
+      84             :     for(int i = 0; i < n; i++)
+      85             :         if(sig[i] && i < 32)
+      86             :             ret |= 1<<i;
+      87             :     return ret;
+      88             : }
+      89             : 
+      90             : template<size_t n>
+      91             : Signal<n> $mux(Signal<n> const& a, Signal<n> const &b, Signal<1> const &s)
+      92             : {
+      93             :     return s[0] ? b : a;
+      94             : }
+      95             : 
+      96             : template<size_t n>
+      97             : Signal<n> $not(Signal<n> const& a)
+      98             : {
+      99             :     Signal<n> ret;
+     100             :     for(size_t i = 0; i < n; i++)
+     101             :         ret[i] = !a[i];
+     102             :     return ret;
+     103             : }
+     104             : 
+     105             : template<size_t n>
+     106             : Signal<n> $neg(Signal<n> const& a)
+     107             : {
+     108             :     Signal<n> ret;
+     109             :     bool carry = true;
+     110             :     for(size_t i = 0; i < n; i++) {
+     111             :         int r = !a[i] + carry;
+     112             :         ret[i] = (r & 1) != 0;
+     113             :         carry = (r >> 1) != 0;
+     114             :     }
+     115             :     return ret;
+     116             : }
+     117             : 
+     118             : template<size_t n>
+     119             : Signal<1> $reduce_or(Signal<n> const& a)
+     120             : {
+     121             :     return { as_bool(a) };
+     122             : }
+     123             : 
+     124             : template<size_t n>
+     125             : Signal<1> $reduce_and(Signal<n> const& a)
+     126             : {
+     127             :     for(size_t i = 0; i < n; i++)
+     128             :         if(!a[i])
+     129             :             return { false };
+     130             :     return { true };
+     131             : }
+     132             : 
+     133             : template<size_t n>
+     134             : Signal<1> $reduce_bool(Signal<n> const& a)
+     135             : {
+     136             :     return { as_bool(a) };
+     137             : }
+     138             : 
+     139             : template<size_t n>
+     140             : Signal<1> $logic_and(Signal<n> const& a, Signal<n> const& b)
+     141             : {
+     142             :     return { as_bool(a) && as_bool(b) };
+     143             : }
+     144             : 
+     145             : template<size_t n>
+     146             : Signal<1> $logic_or(Signal<n> const& a, Signal<n> const& b)
+     147             : {
+     148             :     return { as_bool(a) || as_bool(b) };
+     149             : }
+     150             : 
+     151             : template<size_t n>
+     152             : Signal<1> $logic_not(Signal<n> const& a)
+     153             : {
+     154             :     return { !as_bool(a) };
+     155             : }
+     156             : 
+     157             : template<size_t n>
+     158          30 : Signal<n> $add(Signal<n> const& a, Signal<n> const &b)
+     159             : {
+     160             :     Signal<n> ret;
+     161             :     size_t i;
+     162             :     int x = 0;
+     163          30 :     for(i = 0; i < n; i++){
+     164          30 :         x += (int)a[i] + (int)b[i];
+     165          30 :         ret[i] = x & 1;
+     166          30 :         x >>= 1;
+     167             :     }
+     168             :     return ret;
+     169             : }
+     170             : template<size_t n>
+     171             : Signal<n> $sub(Signal<n> const& a, Signal<n> const &b)
+     172             : {
+     173             :     Signal<n> ret;
+     174             :     int x = 1;
+     175             :     for(size_t i = 0; i < n; i++){
+     176             :         x += (int)a[i] + (int)!b[i];
+     177             :         ret[i] = x & 1;
+     178             :         x >>= 1;
+     179             :     }
+     180             :     return ret;
+     181             : }
+     182             : 
+     183             : template<size_t n>
+     184             : Signal<1> $uge(Signal<n> const& a, Signal<n> const &b)
+     185             : {
+     186             :     for(size_t i = n; i-- != 0; )
+     187             :         if(a[i] != b[i])
+     188             :             return { a[i] };
+     189             :     return { true };
+     190             : }
+     191             : 
+     192             : template<size_t n>
+     193             : Signal<1> $ugt(Signal<n> const& a, Signal<n> const &b)
+     194             : {
+     195             :     for(size_t i = n; i-- != 0; )
+     196             :         if(a[i] != b[i])
+     197             :             return { a[i] };
+     198             :     return { false };
+     199             : }
+     200             : 
+     201             : template<size_t n>
+     202             : Signal<1> $ge(Signal<n> const& a, Signal<n> const &b)
+     203             : {
+     204             :     if(a[n-1] != b[n-1])
+     205             :         return { b[n-1] };
+     206             :     return $uge(a, b);
+     207             : }
+     208             : 
+     209             : template<size_t n>
+     210             : Signal<1> $gt(Signal<n> const& a, Signal<n> const &b)
+     211             : {
+     212             :     if(a[n-1] != b[n-1])
+     213             :         return { b[n-1] };
+     214             :     return $ugt(a, b);
+     215             : }
+     216             : 
+     217             : template<size_t n> Signal<1> $ule(Signal<n> const& a, Signal<n> const &b) { return $uge(b, a); }
+     218             : template<size_t n> Signal<1> $ult(Signal<n> const& a, Signal<n> const &b) { return $ugt(b, a); }
+     219             : template<size_t n> Signal<1> $le(Signal<n> const& a, Signal<n> const &b) { return $ge(b, a); }
+     220             : template<size_t n> Signal<1> $lt(Signal<n> const& a, Signal<n> const &b) { return $gt(b, a); }
+     221             : 
+     222             : template<size_t n>
+     223             : Signal<n> $and(Signal<n> const& a, Signal<n> const &b)
+     224             : {
+     225             :     Signal<n> ret;
+     226             :     for(size_t i = 0; i < n; i++)
+     227             :         ret[i] = a[i] && b[i];
+     228             :     return ret;
+     229             : }
+     230             : 
+     231             : template<size_t n>
+     232             : Signal<n> $or(Signal<n> const& a, Signal<n> const &b)
+     233             : {
+     234             :     Signal<n> ret;
+     235             :     for(size_t i = 0; i < n; i++)
+     236             :         ret[i] = a[i] || b[i];
+     237             :     return ret;
+     238             : }
+     239             : 
+     240             : template<size_t n>
+     241             : Signal<n> $xor(Signal<n> const& a, Signal<n> const &b)
+     242             : {
+     243             :     Signal<n> ret;
+     244             :     for(size_t i = 0; i < n; i++)
+     245             :         ret[i] = a[i] != b[i];
+     246             :     return ret;
+     247             : }
+     248             : 
+     249             : template<size_t n, size_t na, size_t nb>
+     250             : Signal<n> $shl(Signal<na> const& a, Signal<nb> const &b)
+     251             : {
+     252             :     if(nb >= sizeof(int) * 8 - 1)
+     253             :         for(size_t i = sizeof(int) * 8 - 1; i < nb; i++)
+     254             :             assert(!b[i]);
+     255             :     size_t amount = as_int(b);
+     256             :     Signal<n> ret = $const<n>(0);
+     257             :     if(amount < n){
+     258             :         if(amount + na > n)
+     259             :             std::copy(a.begin(), a.begin() + (n - amount), ret.begin() + amount);
+     260             :         else
+     261             :             std::copy(a.begin(), a.end(), ret.begin() + amount);
+     262             :     }
+     263             :     return ret;
+     264             : }
+     265             : 
+     266             : template<size_t n, size_t nb>
+     267             : Signal<n> $shr(Signal<n> const& a, Signal<nb> const &b)
+     268             : {
+     269             :     if(nb >= sizeof(int) * 8 - 1)
+     270             :         for(size_t i = sizeof(int) * 8 - 1; i < nb; i++)
+     271             :             assert(!b[i]);
+     272             :     size_t amount = as_int(b);
+     273             :     Signal<n> ret;
+     274             :     for (size_t i = 0; i < n; i++) {
+     275             :         if(i + amount < n)
+     276             :             ret[i] = a[i + amount];
+     277             :         else
+     278             :             ret[i] = false;
+     279             :     }
+     280             :     return ret;
+     281             : }
+     282             : 
+     283             : template<size_t n, size_t nb>
+     284             : Signal<n> $asr(Signal<n> const& a, Signal<nb> const &b)
+     285             : {
+     286             :     if(nb >= sizeof(int) * 8 - 1)
+     287             :         for(size_t i = sizeof(int) * 8 - 1; i < nb; i++)
+     288             :             assert(!b[i]);
+     289             :     size_t amount = as_int(b);
+     290             :     Signal<n> ret;
+     291             :     for (size_t i = 0; i < n; i++) {
+     292             :         if(i + amount < n)
+     293             :             ret[i] = a[i + amount];
+     294             :         else
+     295             :             ret[i] = a[n - 1];
+     296             :     }
+     297             :     return ret;
+     298             : }
+     299             : 
+     300             : template<size_t n>
+     301             : Signal<1> $eq(Signal<n> const& a, Signal<n> const &b)
+     302             : {
+     303             :     for(size_t i = 0; i < n; i++)
+     304             :         if(a[i] != b[i])
+     305             :             return { false };
+     306             :     return { true };
+     307             : }
+     308             : 
+     309             : template<size_t n>
+     310             : Signal<1> $ne(Signal<n> const& a, Signal<n> const &b)
+     311             : {
+     312             :     for(size_t i = 0; i < n; i++)
+     313             :         if(a[i] != b[i])
+     314             :             return { true };
+     315             :     return { false };
+     316             : }
+     317             : 
+     318             : template<size_t n, size_t ns>
+     319             : Signal<n> $pmux(Signal<n> const& a, Signal<n*ns> const &b, Signal<ns> const &s)
+     320             : {
+     321             :     bool found;
+     322             :     Signal<n> ret;
+     323             : 
+     324             :     found = false;
+     325             :     ret = a;
+     326             :     for(size_t i = 0; i < ns; i++){
+     327             :         if(s[i]){
+     328             :             if(found)
+     329             :                 return $const<n>(0);
+     330             :             found = true;
+     331             :             ret = slice<n>(b, n * i);
+     332             :         }
+     333             :     }
+     334             :     return ret;
+     335             : }
+     336             : 
+     337             : template<size_t n, size_t m>
+     338             : Signal<n+m> concat(Signal<n> const& a, Signal<m> const& b)
+     339             : {
+     340             :     Signal<n + m> ret;
+     341             :     std::copy(a.begin(), a.end(), ret.begin());
+     342             :     std::copy(b.begin(), b.end(), ret.begin() + n);
+     343             :     return ret;
+     344             : }
+     345             : 
+     346             : template<size_t n, size_t m>
+     347             : Signal<n> $zero_extend(Signal<m> const& a)
+     348             : {
+     349             :     assert(n >= m);
+     350             :     Signal<n> ret;
+     351             :     std::copy(a.begin(), a.end(), ret.begin());
+     352             :     for(size_t i = m; i < n; i++)
+     353             :         ret[i] = false;
+     354             :     return ret;
+     355             : }
+     356             : 
+     357             : template<size_t n, size_t m>
+     358             : Signal<n> $sign_extend(Signal<m> const& a)
+     359             : {
+     360             :     assert(n >= m);
+     361             :     Signal<n> ret;
+     362             :     std::copy(a.begin(), a.end(), ret.begin());
+     363             :     for(size_t i = m; i < n; i++)
+     364             :         ret[i] = a[m-1];
+     365             :     return ret;
+     366             : }
+     367             : 
+     368             : #endif
+
+
+
+ + + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/and_cxxrtl.cc.func-sort-c.html b/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/and_cxxrtl.cc.func-sort-c.html new file mode 100644 index 00000000000..e325523d6be --- /dev/null +++ b/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/and_cxxrtl.cc.func-sort-c.html @@ -0,0 +1,100 @@ + + + + + + + LCOV - vcd_harness.info - /home/roland/my_yosys/tests/functional/and_cxxrtl.cc - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - home/roland/my_yosys/tests/functional - and_cxxrtl.cc (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:222975.9 %
Date:1980-01-01 00:00:00Functions:5771.4 %
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN13cxxrtl_design7p_Adder10debug_evalEv0
cxxrtl_design_create0
_ZN13cxxrtl_design7p_Adder10debug_infoEPN6cxxrtl11debug_itemsEPNS1_12debug_scopesENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEOSt3mapISB_NS1_8metadataESt4lessISB_ESaISt4pairIKSB_SD_EEE3
_ZN13cxxrtl_design7p_Adder5resetEv3
_ZN13cxxrtl_design7p_AdderC2Ev3
_ZN13cxxrtl_design7p_Adder4evalEPN6cxxrtl9performerE33
_ZN13cxxrtl_design7p_Adder6commitEv33
+
+
+ + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/and_cxxrtl.cc.func.html b/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/and_cxxrtl.cc.func.html new file mode 100644 index 00000000000..61a536bc000 --- /dev/null +++ b/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/and_cxxrtl.cc.func.html @@ -0,0 +1,100 @@ + + + + + + + LCOV - vcd_harness.info - /home/roland/my_yosys/tests/functional/and_cxxrtl.cc - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - home/roland/my_yosys/tests/functional - and_cxxrtl.cc (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:222975.9 %
Date:1980-01-01 00:00:00Functions:5771.4 %
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN13cxxrtl_design7p_Adder10debug_evalEv0
_ZN13cxxrtl_design7p_Adder10debug_infoEPN6cxxrtl11debug_itemsEPNS1_12debug_scopesENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEOSt3mapISB_NS1_8metadataESt4lessISB_ESaISt4pairIKSB_SD_EEE3
_ZN13cxxrtl_design7p_Adder4evalEPN6cxxrtl9performerE33
_ZN13cxxrtl_design7p_Adder5resetEv3
_ZN13cxxrtl_design7p_Adder6commitEv33
_ZN13cxxrtl_design7p_AdderC2Ev3
cxxrtl_design_create0
+
+
+ + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/and_cxxrtl.cc.gcov.html b/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/and_cxxrtl.cc.gcov.html new file mode 100644 index 00000000000..83033d50085 --- /dev/null +++ b/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/and_cxxrtl.cc.gcov.html @@ -0,0 +1,161 @@ + + + + + + + LCOV - vcd_harness.info - /home/roland/my_yosys/tests/functional/and_cxxrtl.cc + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - home/roland/my_yosys/tests/functional - and_cxxrtl.cc (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:222975.9 %
Date:1980-01-01 00:00:00Functions:5771.4 %
+
+ + + + + + + + +

+
          Line data    Source code
+
+       1             : #include <cxxrtl/cxxrtl.h>
+       2             : 
+       3             : #if defined(CXXRTL_INCLUDE_CAPI_IMPL) || \
+       4             :     defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)
+       5             : #include <cxxrtl/capi/cxxrtl_capi.cc>
+       6             : #endif
+       7             : 
+       8             : #if defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)
+       9             : #include <cxxrtl/capi/cxxrtl_capi_vcd.cc>
+      10             : #endif
+      11             : 
+      12             : using namespace cxxrtl_yosys;
+      13             : 
+      14             : namespace cxxrtl_design {
+      15             : 
+      16             : // \top: 1
+      17             : // \src: verilog/and.v:1.1-9.10
+      18           3 : struct p_Adder : public module {
+      19             :         // \src: verilog/and.v:4.14-4.17
+      20             :         /*output*/ value<1> p_sum;
+      21             :         // \src: verilog/and.v:3.14-3.15
+      22             :         /*input*/ value<1> p_b;
+      23             :         // \src: verilog/and.v:2.14-2.15
+      24             :         /*input*/ value<1> p_a;
+      25             :         p_Adder(interior) {}
+      26           3 :         p_Adder() {
+      27           3 :                 reset();
+      28           3 :         };
+      29             : 
+      30             :         void reset() override;
+      31             : 
+      32             :         bool eval(performer *performer = nullptr) override;
+      33             : 
+      34             :         template<class ObserverT>
+      35             :         bool commit(ObserverT &observer) {
+      36          33 :                 bool changed = false;
+      37             :                 return changed;
+      38             :         }
+      39             : 
+      40          33 :         bool commit() override {
+      41          33 :                 observer observer;
+      42          33 :                 return commit<>(observer);
+      43             :         }
+      44             : 
+      45             :         void debug_eval();
+      46             : 
+      47             :         void debug_info(debug_items *items, debug_scopes *scopes, std::string path, metadata_map &&cell_attrs = {}) override;
+      48             : }; // struct p_Adder
+      49             : 
+      50           3 : void p_Adder::reset() {
+      51           3 : }
+      52             : 
+      53          33 : bool p_Adder::eval(performer *performer) {
+      54          33 :         bool converged = true;
+      55             :         // \src: verilog/and.v:7.17-7.22
+      56             :         // cell $add$verilog/and.v:7$1
+      57          33 :         p_sum = add_uu<1>(p_a, p_b);
+      58          33 :         return converged;
+      59             : }
+      60             : 
+      61           0 : void p_Adder::debug_eval() {
+      62           0 : }
+      63             : 
+      64             : CXXRTL_EXTREMELY_COLD
+      65           3 : void p_Adder::debug_info(debug_items *items, debug_scopes *scopes, std::string path, metadata_map &&cell_attrs) {
+      66           3 :         assert(path.empty() || path[path.size() - 1] == ' ');
+      67           3 :         if (scopes) {
+      68           0 :                 scopes->add(path.empty() ? path : path.substr(0, path.size() - 1), "Adder", metadata_map({
+      69           0 :                         { "top", UINT64_C(1) },
+      70             :                         { "src", "verilog/and.v:1.1-9.10" },
+      71           0 :                 }), std::move(cell_attrs));
+      72             :         }
+      73           3 :         if (items) {
+      74           3 :                 items->add(path, "sum", "src\000sverilog/and.v:4.14-4.17\000", p_sum, 0, debug_item::OUTPUT|debug_item::DRIVEN_COMB);
+      75           3 :                 items->add(path, "b", "src\000sverilog/and.v:3.14-3.15\000", p_b, 0, debug_item::INPUT|debug_item::UNDRIVEN);
+      76           3 :                 items->add(path, "a", "src\000sverilog/and.v:2.14-2.15\000", p_a, 0, debug_item::INPUT|debug_item::UNDRIVEN);
+      77             :         }
+      78           3 : }
+      79             : 
+      80             : } // namespace cxxrtl_design
+      81             : 
+      82             : extern "C"
+      83           0 : cxxrtl_toplevel cxxrtl_design_create() {
+      84           0 :         return new _cxxrtl_toplevel { std::unique_ptr<cxxrtl_design::p_Adder>(new cxxrtl_design::p_Adder) };
+      85             : }
+
+
+
+ + + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/and_functional_cxx.cc.func-sort-c.html b/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/and_functional_cxx.cc.func-sort-c.html new file mode 100644 index 00000000000..1ff7fb0d449 --- /dev/null +++ b/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/and_functional_cxx.cc.func-sort-c.html @@ -0,0 +1,84 @@ + + + + + + + LCOV - vcd_harness.info - /home/roland/my_yosys/tests/functional/and_functional_cxx.cc - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - home/roland/my_yosys/tests/functional - and_functional_cxx.cc (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:1313100.0 %
Date:1980-01-01 00:00:00Functions:33100.0 %
+
+ +
+ + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN12Adder_Inputs4dumpI10DumpHeaderEEvRT_3
_Z5AdderRK12Adder_InputsR13Adder_OutputsRK11Adder_StateRS4_30
_ZN12Adder_Inputs4dumpI4DumpEEvRT_33
+
+
+ + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/and_functional_cxx.cc.func.html b/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/and_functional_cxx.cc.func.html new file mode 100644 index 00000000000..8a02bda164c --- /dev/null +++ b/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/and_functional_cxx.cc.func.html @@ -0,0 +1,84 @@ + + + + + + + LCOV - vcd_harness.info - /home/roland/my_yosys/tests/functional/and_functional_cxx.cc - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - home/roland/my_yosys/tests/functional - and_functional_cxx.cc (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:1313100.0 %
Date:1980-01-01 00:00:00Functions:33100.0 %
+
+ +
+ + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_Z5AdderRK12Adder_InputsR13Adder_OutputsRK11Adder_StateRS4_30
_ZN12Adder_Inputs4dumpI10DumpHeaderEEvRT_3
_ZN12Adder_Inputs4dumpI4DumpEEvRT_33
+
+
+ + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/and_functional_cxx.cc.gcov.html b/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/and_functional_cxx.cc.gcov.html new file mode 100644 index 00000000000..57e77268202 --- /dev/null +++ b/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/and_functional_cxx.cc.gcov.html @@ -0,0 +1,108 @@ + + + + + + + LCOV - vcd_harness.info - /home/roland/my_yosys/tests/functional/and_functional_cxx.cc + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - home/roland/my_yosys/tests/functional - and_functional_cxx.cc (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:1313100.0 %
Date:1980-01-01 00:00:00Functions:33100.0 %
+
+ + + + + + + + +

+
          Line data    Source code
+
+       1             : #include "sim.h"
+       2             : struct Adder_Inputs {
+       3             :         Signal<1> b;
+       4             :         Signal<1> a;
+       5             : 
+       6          36 :         template <typename T> void dump(T &out) {
+       7          36 :                 out("b", b);
+       8          36 :                 out("a", a);
+       9          36 :         }
+      10             : };
+      11             : 
+      12             : struct Adder_Outputs {
+      13             :         Signal<1> sum;
+      14             : 
+      15          36 :         template <typename T> void dump(T &out) {
+      16          36 :                 out("sum", sum);
+      17          36 :         }
+      18             : };
+      19             : 
+      20             : struct Adder_State {
+      21             : 
+      22             :         template <typename T> void dump(T &out) {
+      23             :         }
+      24             : };
+      25             : 
+      26          30 : void Adder(Adder_Inputs const &input, Adder_Outputs &output, Adder_State const &current_state, Adder_State &next_state)
+      27             : {
+      28          30 :         Signal<1> b = input.b;
+      29          30 :         Signal<1> a = input.a;
+      30          30 :         Signal<1> $add$verilog_and_v_7$1$_Y = $add(a, b); //
+      31          30 :         output.sum = $add$verilog_and_v_7$1$_Y;
+      32          30 : }
+
+
+
+ + + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/index-sort-f.html b/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/index-sort-f.html new file mode 100644 index 00000000000..476b5417b52 --- /dev/null +++ b/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/index-sort-f.html @@ -0,0 +1,113 @@ + + + + + + + LCOV - vcd_harness.info - /home/roland/my_yosys/tests/functional + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - /home/roland/my_yosys/tests/functionalHitTotalCoverage
Test:vcd_harness.infoLines:10511293.8 %
Date:1980-01-01 00:00:00Functions:111384.6 %
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
and_cxxrtl.cc +
75.9%75.9%
+ 		75.9 %22 / 2971.4 %5 / 7
vcd_harness.cpp +
100.0%
+ 		100.0 %70 / 70100.0 %3 / 3
and_functional_cxx.cc +
100.0%
+ 		100.0 %13 / 13100.0 %3 / 3
+
+
+ + + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/index-sort-l.html b/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/index-sort-l.html new file mode 100644 index 00000000000..aad1a23666d --- /dev/null +++ b/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/index-sort-l.html @@ -0,0 +1,113 @@ + + + + + + + LCOV - vcd_harness.info - /home/roland/my_yosys/tests/functional + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - /home/roland/my_yosys/tests/functionalHitTotalCoverage
Test:vcd_harness.infoLines:10511293.8 %
Date:1980-01-01 00:00:00Functions:111384.6 %
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
and_cxxrtl.cc +
75.9%75.9%
+ 		75.9 %22 / 2971.4 %5 / 7
and_functional_cxx.cc +
100.0%
+ 		100.0 %13 / 13100.0 %3 / 3
vcd_harness.cpp +
100.0%
+ 		100.0 %70 / 70100.0 %3 / 3
+
+
+ + + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/index.html b/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/index.html new file mode 100644 index 00000000000..548ec95fffd --- /dev/null +++ b/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/index.html @@ -0,0 +1,113 @@ + + + + + + + LCOV - vcd_harness.info - /home/roland/my_yosys/tests/functional + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - /home/roland/my_yosys/tests/functionalHitTotalCoverage
Test:vcd_harness.infoLines:10511293.8 %
Date:1980-01-01 00:00:00Functions:111384.6 %
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
and_cxxrtl.cc +
75.9%75.9%
+ 		75.9 %22 / 2971.4 %5 / 7
and_functional_cxx.cc +
100.0%
+ 		100.0 %13 / 13100.0 %3 / 3
vcd_harness.cpp +
100.0%
+ 		100.0 %70 / 70100.0 %3 / 3
+
+
+ + + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/vcd_harness.cpp.func-sort-c.html b/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/vcd_harness.cpp.func-sort-c.html new file mode 100644 index 00000000000..07fdc01e640 --- /dev/null +++ b/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/vcd_harness.cpp.func-sort-c.html @@ -0,0 +1,84 @@ + + + + + + + LCOV - vcd_harness.info - /home/roland/my_yosys/tests/functional/vcd_harness.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - home/roland/my_yosys/tests/functional - vcd_harness.cpp (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:7070100.0 %
Date:1980-01-01 00:00:00Functions:33100.0 %
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+ + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
main3
_ZN10DumpHeaderclILm1EEEvPKcSt5arrayIbXT_EE9
_ZN4DumpclILm1EEEvPKcSt5arrayIbXT_EE99
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+
+ + + +
Generated by: LCOV version 1.0
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+ + + diff --git a/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/vcd_harness.cpp.func.html b/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/vcd_harness.cpp.func.html new file mode 100644 index 00000000000..6a9159b0109 --- /dev/null +++ b/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/vcd_harness.cpp.func.html @@ -0,0 +1,84 @@ + + + + + + + LCOV - vcd_harness.info - /home/roland/my_yosys/tests/functional/vcd_harness.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - home/roland/my_yosys/tests/functional - vcd_harness.cpp (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:7070100.0 %
Date:1980-01-01 00:00:00Functions:33100.0 %
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+ +
+ + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN10DumpHeaderclILm1EEEvPKcSt5arrayIbXT_EE9
_ZN4DumpclILm1EEEvPKcSt5arrayIbXT_EE99
main3
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+
+ + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/vcd_harness.cpp.gcov.html b/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/vcd_harness.cpp.gcov.html new file mode 100644 index 00000000000..805ab98d73e --- /dev/null +++ b/tests/functional/coverage_report/home/roland/my_yosys/tests/functional/vcd_harness.cpp.gcov.html @@ -0,0 +1,216 @@ + + + + + + + LCOV - vcd_harness.info - /home/roland/my_yosys/tests/functional/vcd_harness.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - home/roland/my_yosys/tests/functional - vcd_harness.cpp (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:7070100.0 %
Date:1980-01-01 00:00:00Functions:33100.0 %
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+ + + + + + + + +

+
          Line data    Source code
+
+       1             : #include <cstdio>
+       2             : #include <iostream>
+       3             : #include <fstream>
+       4             : #include <random>
+       5             : 
+       6             : #include <cxxrtl/cxxrtl_vcd.h>
+       7             : 
+       8             : #include "and_cxxrtl.cc"
+       9             : #include "and_functional_cxx.cc"
+      10             : 
+      11             : struct DumpHeader {
+      12             :     std::ofstream &ofs;
+      13           3 :     DumpHeader(std::ofstream &ofs) : ofs(ofs) {}
+      14             :     template <size_t n>
+      15           9 :     void operator()(const char *name, Signal<n> value) {
+      16           9 :         ofs << "$var wire " << n << " " << name[0] << " " << name << " $end\n";
+      17           9 :     }
+      18             : };
+      19             : 
+      20             : struct Dump {
+      21             :     std::ofstream &ofs;
+      22          33 :     Dump(std::ofstream &ofs) : ofs(ofs) {}
+      23             :     template <size_t n>
+      24          99 :     void operator()(const char *name, Signal<n> value) {
+      25             :         // Bit
+      26             :         if (n == 1) {
+      27         156 :             ofs << (value[0] ? '1' : '0');
+      28          99 :             ofs << name[0] << "\n";
+      29             :             return;
+      30             :         }
+      31             :         // vector (multi-bit) signals
+      32             :         ofs << "b";
+      33             :         for (size_t i = n; i-- > 0;)
+      34             :             ofs << (value[i] ? '1' : '0');
+      35             :         ofs << " " << name[0] << "\n";
+      36             :     }
+      37             : };
+      38             : 
+      39           3 : int main(int argc, char **argv)
+      40             : {
+      41           3 :     constexpr int steps = 10;
+      42           3 :     constexpr int number_timescale = 1;
+      43           3 :     const std::string units_timescale = "us";
+      44           3 :     Adder_Inputs inputs;
+      45           3 :     Adder_Outputs outputs;
+      46           3 :     Adder_State state;
+      47           3 :     Adder_State next_state;
+      48             : 
+      49           3 :     std::ofstream vcd_file("functional_cxx.vcd");
+      50             : 
+      51           3 :     vcd_file << "$timescale " << number_timescale << " " << units_timescale << " $end\n"; //$scope module logic $end\n";
+      52           3 :     {
+      53           3 :         DumpHeader d(vcd_file);
+      54           3 :         inputs.dump(d);
+      55           3 :         outputs.dump(d);
+      56             :         // vcd_file << "$scope module state $end\n";
+      57           3 :         state.dump(d);
+      58             :     }
+      59           3 :     vcd_file << "$enddefinitions $end\n$dumpvars\n";
+      60             : 
+      61           3 :     cxxrtl_design::p_Adder top;
+      62             : 
+      63             :     // debug_items maps the hierarchical names of signals and memories in the design
+      64             :     // to a cxxrtl_object (a value, a wire, or a memory)
+      65           3 :     cxxrtl::debug_items all_debug_items;
+      66           3 :     cxxrtl::debug_scope debug_scope;
+      67             :     // Load the debug items of the top down the whole design hierarchy
+      68           6 :     top.debug_info(&all_debug_items, nullptr, "");
+      69             : 
+      70             :     // vcd_writer is the CXXRTL object that's responsible for creating a string with
+      71             :     // the VCD file contents.
+      72           3 :     cxxrtl::vcd_writer vcd;
+      73           3 :     vcd.timescale(number_timescale, units_timescale);
+      74             : 
+      75             :     // Here we tell the vcd writer to dump all the signals of the design, except for the
+      76             :     // memories, to the VCD file.
+      77             :     //
+      78             :     // It's not necessary to load all debug objects to the VCD. There is, for example,
+      79             :     // a  vcd.add(<debug items>, <filter>)) method which allows creating your custom filter to decide
+      80             :     // what to add and what not.
+      81           3 :     vcd.add_without_memories(all_debug_items);
+      82             : 
+      83           3 :     std::ofstream waves("cxxrtl.vcd");
+      84             : 
+      85           3 :     top.p_a.set<bool>(false);
+      86           3 :     top.p_b.set<bool>(false);
+      87           3 :     top.step();
+      88             : 
+      89             :     // We need to manually tell the VCD writer when to sample and write out the traced items.
+      90             :     // This is only a slight inconvenience and allows for complete flexibility.
+      91             :     // E.g. you could only start waveform tracing when an internal signal has reached some specific
+      92             :     // value etc.
+      93           3 :     vcd.sample(0);
+      94           3 :     vcd_file << "#0\n";
+      95           3 :     inputs.a = $const<1>(false);
+      96           3 :     inputs.b = $const<1>(false);
+      97           3 :     {
+      98           3 :         Dump d(vcd_file);
+      99           3 :         inputs.dump(d);
+     100           3 :         outputs.dump(d);
+     101           3 :         state.dump(d);
+     102             :     }
+     103             : 
+     104             :     // Initialize random number generator
+     105           3 :     std::random_device rd;
+     106           3 :     std::mt19937 gen(rd());
+     107           3 :     std::bernoulli_distribution dist(0.5); // 50% chance for true or false
+     108             :     
+     109          33 :     for (int step = 0; step < steps; ++step) {
+     110          30 :       const bool a_value = dist(gen);
+     111          30 :       const bool b_value = dist(gen);
+     112             : 
+     113             :         // cxxrtl
+     114          30 :         top.p_a.set<bool>(a_value);
+     115          30 :         top.p_b.set<bool>(b_value);
+     116          30 :         top.step();
+     117          30 :         vcd.sample(step + 1);
+     118             : 
+     119          30 :         waves << vcd.buffer;
+     120          30 :         vcd.buffer.clear();
+     121             : 
+     122             :         // Functional backend cxx
+     123          30 :         vcd_file << "#" << (step + 1) << "\n";
+     124          30 :         inputs.a = $const<1>(a_value);
+     125          30 :         inputs.b = $const<1>(b_value);
+     126          30 :         Adder(inputs, outputs, state, next_state);
+     127          30 :         {
+     128          30 :             Dump d(vcd_file);
+     129          30 :             inputs.dump(d);
+     130          30 :             outputs.dump(d);
+     131          30 :             state.dump(d);
+     132             :         }
+     133          30 :         state = next_state;
+     134             :     }
+     135             : 
+     136           3 :     vcd_file.close();
+     137           3 :     waves.close();
+     138             : 
+     139           3 :     return 0;
+     140           3 : }
+
+
+
+ + + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/index-sort-f.html b/tests/functional/coverage_report/index-sort-f.html new file mode 100644 index 00000000000..e83963227e1 --- /dev/null +++ b/tests/functional/coverage_report/index-sort-f.html @@ -0,0 +1,93 @@ + + + + + + + LCOV - vcd_harness.info + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top levelHitTotalCoverage
Test:vcd_harness.infoLines:10511293.8 %
Date:1980-01-01 00:00:00Functions:111384.6 %
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + +

Directory Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
functional +
93.8%93.8%
+ 		93.8 %105 / 11284.6 %11 / 13
+
+
+ + + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/index-sort-l.html b/tests/functional/coverage_report/index-sort-l.html new file mode 100644 index 00000000000..ddc964eb34a --- /dev/null +++ b/tests/functional/coverage_report/index-sort-l.html @@ -0,0 +1,93 @@ + + + + + + + LCOV - vcd_harness.info + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top levelHitTotalCoverage
Test:vcd_harness.infoLines:10511293.8 %
Date:1980-01-01 00:00:00Functions:111384.6 %
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + +

Directory Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
functional +
93.8%93.8%
+ 		93.8 %105 / 11284.6 %11 / 13
+
+
+ + + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/index.html b/tests/functional/coverage_report/index.html new file mode 100644 index 00000000000..65d715c439e --- /dev/null +++ b/tests/functional/coverage_report/index.html @@ -0,0 +1,93 @@ + + + + + + + LCOV - vcd_harness.info + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top levelHitTotalCoverage
Test:vcd_harness.infoLines:10511293.8 %
Date:1980-01-01 00:00:00Functions:111384.6 %
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + +

Directory Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
functional +
93.8%93.8%
+ 		93.8 %105 / 11284.6 %11 / 13
+
+
+ + + + +
Generated by: LCOV version 1.0
+
+ + + diff --git a/tests/functional/coverage_report/nix/store/B0S2LKF593R3585038WS4JD3LYLF2WDX-glibc-2.38-44-dev/include/bits/string_fortified.h.gcov.html b/tests/functional/coverage_report/nix/store/B0S2LKF593R3585038WS4JD3LYLF2WDX-glibc-2.38-44-dev/include/bits/string_fortified.h.gcov.html new file mode 100644 index 00000000000..7c9e3ccdcd7 --- /dev/null +++ b/tests/functional/coverage_report/nix/store/B0S2LKF593R3585038WS4JD3LYLF2WDX-glibc-2.38-44-dev/include/bits/string_fortified.h.gcov.html @@ -0,0 +1,54 @@ + + + + + + + LCOV - vcd_harness.info - /nix/store/B0S2LKF593R3585038WS4JD3LYLF2WDX-glibc-2.38-44-dev/include/bits/string_fortified.h + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - nix/store/B0S2LKF593R3585038WS4JD3LYLF2WDX-glibc-2.38-44-dev/include/bits - string_fortified.h (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:020.0 %
Date:1980-01-01 00:00:00Functions:00-
+
+ diff --git a/tests/functional/coverage_report/ruby.png b/tests/functional/coverage_report/ruby.png new file mode 100644 index 0000000000000000000000000000000000000000..991b6d4ec9e78be165e3ef757eed1aada287364d GIT binary patch literal 141 zcmeAS@N?(olHy`uVBq!ia0vp^j3CU&3?x-=hn)ga>?NMQuI!iC1^FceV#7`HfI^%F z9+AZi4BSE>%y{W;-5;PJOS+@4BLl<6e(pbstUx|nfKQ0)e^Y%R^MdiLxj>4`)5S5Q b;#P73kj=!v_*DHKNFRfztDnm{r-UW|iOwIS literal 0 HcmV?d00001 diff --git a/tests/functional/coverage_report/snow.png b/tests/functional/coverage_report/snow.png new file mode 100644 index 0000000000000000000000000000000000000000..2cdae107fceec6e7f02ac7acb4a34a82a540caa5 GIT binary patch literal 141 zcmeAS@N?(olHy`uVBq!ia0vp^j3CU&3?x-=hn)ga>?NMQuI!iC1^MM!lvI6;R0X`wF|Ns97GD8ntt^-nBo-U3d c6}OTTfNUlP#;5A{K>8RwUHx3vIVCg!071?oo&W#< literal 0 HcmV?d00001 diff --git a/tests/functional/coverage_report/updown.png b/tests/functional/coverage_report/updown.png new file mode 100644 index 0000000000000000000000000000000000000000..aa56a238b3e6c435265250f9266cd1b8caba0f20 GIT binary patch literal 117 zcmeAS@N?(olHy`uVBq!ia0vp^AT}Qd8;}%R+`Ae`*?77*hG?8mPH5^{)z4*}Q$iB}huR`+ literal 0 HcmV?d00001 diff --git a/tests/functional/coverage_report/vcd_harness.info b/tests/functional/coverage_report/vcd_harness.info new file mode 100644 index 00000000000..e69de29bb2d diff --git a/tests/functional/generate_coverage.sh b/tests/functional/generate_coverage.sh new file mode 100755 index 00000000000..016e22ea269 --- /dev/null +++ b/tests/functional/generate_coverage.sh @@ -0,0 +1,19 @@ +#!/bin/bash + +# Ensure you have compiled with coverage flags +# g++ -o vcd_harness -fprofile-arcs -ftest-coverage vcd_harness.cpp + +# Define the directory two levels below the current directory +coverage_dir="../../" + +# Create directory for coverage report +mkdir -p coverage_report + +# Capture coverage data from the specified directory, excluding external libraries +lcov --capture --directory "$coverage_dir" --output-file coverage_report/vcd_harness.info --no-external + +# Generate HTML report +genhtml coverage_report/vcd_harness.info --output-directory coverage_report + +# Open the HTML report in the default web browser +xdg-open coverage_report/index.html diff --git a/tests/functional/run-test.sh b/tests/functional/run-test.sh index 3e9de003fc2..09ee5e0f9a3 100755 --- a/tests/functional/run-test.sh +++ b/tests/functional/run-test.sh @@ -2,19 +2,29 @@ set -ex -../../yosys -p "read_verilog verilog/and.v; write_cxxrtl and_cxxrtl.cc; write_functional_cxx and_functional_cxx.cc" -${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cpp -I ../../backends/functional/cxx_runtime/ -I ../../backends/cxxrtl/runtime/ -o vcd_harness -# Generate VCD files cxxrtl.vcd and functional_cxx.vcd -./vcd_harness -# Run vcdiff and capture the output -output=$(vcdiff cxxrtl.vcd functional_cxx.vcd) +# Loop through all Verilog files in the verilog directory +for verilog_file in verilog/*.v; do + # Run yosys to process each Verilog file + ../../yosys -p "read_verilog $verilog_file; write_cxxrtl my_module_cxxrtl.cc; write_functional_cxx my_module_functional_cxx.cc" -# Check if there is any output -if [ -n "$output" ]; then - echo "Differences detected:" - echo "$output" - exit 1 -else - echo "No differences detected." - exit 0 -fi + # Compile the generated C++ files with vcd_harness.cpp + ${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cpp -I ../../backends/functional/cxx_runtime/ -I ../../backends/cxxrtl/runtime/ -o vcd_harness + + # Generate VCD files cxxrtl.vcd and functional_cxx.vcd + ./vcd_harness + + # Run vcdiff and capture the output + output=$(vcdiff cxxrtl.vcd functional_cxx.vcd) + + # Check if there is any output + if [ -n "$output" ]; then + echo "Differences detected in $verilog_file:" + echo "$output" + exit 1 + else + echo "No differences detected in $verilog_file." + fi +done + +# If all files are processed without differences +exit 0 diff --git a/tests/functional/vcd_harness.cpp b/tests/functional/vcd_harness.cpp index dc3ad3b9c2b..76d078b7103 100644 --- a/tests/functional/vcd_harness.cpp +++ b/tests/functional/vcd_harness.cpp @@ -5,8 +5,8 @@ #include -#include "and_cxxrtl.cc" -#include "and_functional_cxx.cc" +#include "my_module_cxxrtl.cc" +#include "my_module_functional_cxx.cc" struct DumpHeader { std::ofstream &ofs; @@ -41,10 +41,10 @@ int main(int argc, char **argv) constexpr int steps = 10; constexpr int number_timescale = 1; const std::string units_timescale = "us"; - Adder_Inputs inputs; - Adder_Outputs outputs; - Adder_State state; - Adder_State next_state; + my_module_Inputs inputs; + my_module_Outputs outputs; + my_module_State state; + my_module_State next_state; std::ofstream vcd_file("functional_cxx.vcd"); @@ -58,7 +58,7 @@ int main(int argc, char **argv) } vcd_file << "$enddefinitions $end\n$dumpvars\n"; - cxxrtl_design::p_Adder top; + cxxrtl_design::p_my__module top; // debug_items maps the hierarchical names of signals and memories in the design // to a cxxrtl_object (a value, a wire, or a memory) @@ -123,7 +123,7 @@ int main(int argc, char **argv) vcd_file << "#" << (step + 1) << "\n"; inputs.a = $const<1>(a_value); inputs.b = $const<1>(b_value); - Adder(inputs, outputs, state, next_state); + my_module(inputs, outputs, state, next_state); { Dump d(vcd_file); inputs.dump(d); diff --git a/tests/functional/verilog/add.v b/tests/functional/verilog/add.v new file mode 100644 index 00000000000..95bae7b3544 --- /dev/null +++ b/tests/functional/verilog/add.v @@ -0,0 +1,9 @@ +module my_module( + input a, + input b, + output sum + ); + // Perform addition + assign sum = a + b; + +endmodule diff --git a/tests/functional/verilog/and.v b/tests/functional/verilog/and.v index 11cf481e96b..ae07de221ff 100644 --- a/tests/functional/verilog/and.v +++ b/tests/functional/verilog/and.v @@ -1,9 +1,9 @@ -module Adder( - input a, - input b, - output sum - ); - // Perform addition - assign sum = a + b; +module my_module( + input a, + input b, + output y +); + // Perform AND + assign y = a & b; endmodule diff --git a/tests/functional/verilog/my_module_div.v b/tests/functional/verilog/my_module_div.v new file mode 100755 index 00000000000..d9a5d372a40 --- /dev/null +++ b/tests/functional/verilog/my_module_div.v @@ -0,0 +1,9 @@ +module my_module( + input a, + input b, + output y +); + // Perform operation + assign y = a / b; + +endmodule diff --git a/tests/functional/verilog/my_module_eqx.v b/tests/functional/verilog/my_module_eqx.v new file mode 100755 index 00000000000..09a2d9dd680 --- /dev/null +++ b/tests/functional/verilog/my_module_eqx.v @@ -0,0 +1,9 @@ +module my_module( + input a, + input b, + output y +); + // Perform operation + assign y = a === b; + +endmodule diff --git a/tests/functional/verilog/my_module_ge.v b/tests/functional/verilog/my_module_ge.v new file mode 100755 index 00000000000..8fcfc8b7f6d --- /dev/null +++ b/tests/functional/verilog/my_module_ge.v @@ -0,0 +1,9 @@ +module my_module( + input a, + input b, + output y +); + // Perform operation + assign y = a >= b; + +endmodule diff --git a/tests/functional/verilog/my_module_gt.v b/tests/functional/verilog/my_module_gt.v new file mode 100755 index 00000000000..5667db3e746 --- /dev/null +++ b/tests/functional/verilog/my_module_gt.v @@ -0,0 +1,9 @@ +module my_module( + input a, + input b, + output y +); + // Perform operation + assign y = a > b; + +endmodule diff --git a/tests/functional/verilog/my_module_le.v b/tests/functional/verilog/my_module_le.v new file mode 100755 index 00000000000..a4b7c482089 --- /dev/null +++ b/tests/functional/verilog/my_module_le.v @@ -0,0 +1,9 @@ +module my_module( + input a, + input b, + output y +); + // Perform operation + assign y = a <= b; + +endmodule diff --git a/tests/functional/verilog/my_module_logic_and.v b/tests/functional/verilog/my_module_logic_and.v new file mode 100755 index 00000000000..3028d8361da --- /dev/null +++ b/tests/functional/verilog/my_module_logic_and.v @@ -0,0 +1,9 @@ +module my_module( + input a, + input b, + output y +); + // Perform operation + assign y = a && b; + +endmodule diff --git a/tests/functional/verilog/my_module_logic_or.v b/tests/functional/verilog/my_module_logic_or.v new file mode 100755 index 00000000000..ca37346d91f --- /dev/null +++ b/tests/functional/verilog/my_module_logic_or.v @@ -0,0 +1,9 @@ +module my_module( + input a, + input b, + output y +); + // Perform operation + assign y = a || b; + +endmodule diff --git a/tests/functional/verilog/my_module_lt.v b/tests/functional/verilog/my_module_lt.v new file mode 100755 index 00000000000..c702433d4f8 --- /dev/null +++ b/tests/functional/verilog/my_module_lt.v @@ -0,0 +1,9 @@ +module my_module( + input a, + input b, + output y +); + // Perform operation + assign y = a < b; + +endmodule diff --git a/tests/functional/verilog/my_module_mod.v b/tests/functional/verilog/my_module_mod.v new file mode 100755 index 00000000000..84c8c91884f --- /dev/null +++ b/tests/functional/verilog/my_module_mod.v @@ -0,0 +1,9 @@ +module my_module( + input a, + input b, + output y +); + // Perform operation + assign y = a % b; + +endmodule diff --git a/tests/functional/verilog/my_module_mul.v b/tests/functional/verilog/my_module_mul.v new file mode 100755 index 00000000000..8eff36abce1 --- /dev/null +++ b/tests/functional/verilog/my_module_mul.v @@ -0,0 +1,9 @@ +module my_module( + input a, + input b, + output y +); + // Perform operation + assign y = a * b; + +endmodule diff --git a/tests/functional/verilog/my_module_ne.v b/tests/functional/verilog/my_module_ne.v new file mode 100755 index 00000000000..c4e0dc1c916 --- /dev/null +++ b/tests/functional/verilog/my_module_ne.v @@ -0,0 +1,9 @@ +module my_module( + input a, + input b, + output y +); + // Perform operation + assign y = a != b; + +endmodule diff --git a/tests/functional/verilog/my_module_nex.v b/tests/functional/verilog/my_module_nex.v new file mode 100755 index 00000000000..630dce4e915 --- /dev/null +++ b/tests/functional/verilog/my_module_nex.v @@ -0,0 +1,9 @@ +module my_module( + input a, + input b, + output y +); + // Perform operation + assign y = a !== b; + +endmodule diff --git a/tests/functional/verilog/my_module_or.v b/tests/functional/verilog/my_module_or.v new file mode 100755 index 00000000000..ada39ee49ce --- /dev/null +++ b/tests/functional/verilog/my_module_or.v @@ -0,0 +1,9 @@ +module my_module( + input a, + input b, + output y +); + // Perform operation + assign y = a | b; + +endmodule diff --git a/tests/functional/verilog/my_module_pow.v b/tests/functional/verilog/my_module_pow.v new file mode 100755 index 00000000000..d9f09638510 --- /dev/null +++ b/tests/functional/verilog/my_module_pow.v @@ -0,0 +1,9 @@ +module my_module( + input a, + input b, + output y +); + // Perform operation + assign y = a ** b; + +endmodule diff --git a/tests/functional/verilog/my_module_shl.v b/tests/functional/verilog/my_module_shl.v new file mode 100755 index 00000000000..66a435ad474 --- /dev/null +++ b/tests/functional/verilog/my_module_shl.v @@ -0,0 +1,9 @@ +module my_module( + input a, + input b, + output y +); + // Perform operation + assign y = a << b; + +endmodule diff --git a/tests/functional/verilog/my_module_shr.v b/tests/functional/verilog/my_module_shr.v new file mode 100755 index 00000000000..791a2ab423a --- /dev/null +++ b/tests/functional/verilog/my_module_shr.v @@ -0,0 +1,9 @@ +module my_module( + input a, + input b, + output y +); + // Perform operation + assign y = a >> b; + +endmodule diff --git a/tests/functional/verilog/my_module_sshl.v b/tests/functional/verilog/my_module_sshl.v new file mode 100755 index 00000000000..8a2f5fe5e95 --- /dev/null +++ b/tests/functional/verilog/my_module_sshl.v @@ -0,0 +1,9 @@ +module my_module( + input a, + input b, + output y +); + // Perform operation + assign y = a <<< b; + +endmodule diff --git a/tests/functional/verilog/my_module_sshr.v b/tests/functional/verilog/my_module_sshr.v new file mode 100755 index 00000000000..9fc46102305 --- /dev/null +++ b/tests/functional/verilog/my_module_sshr.v @@ -0,0 +1,9 @@ +module my_module( + input a, + input b, + output y +); + // Perform operation + assign y = a >>> b; + +endmodule diff --git a/tests/functional/verilog/my_module_sub.v b/tests/functional/verilog/my_module_sub.v new file mode 100755 index 00000000000..2f4e4380e89 --- /dev/null +++ b/tests/functional/verilog/my_module_sub.v @@ -0,0 +1,9 @@ +module my_module( + input a, + input b, + output y +); + // Perform operation + assign y = a - b; + +endmodule diff --git a/tests/functional/verilog/my_module_xnor.v b/tests/functional/verilog/my_module_xnor.v new file mode 100755 index 00000000000..4f1b0148ddb --- /dev/null +++ b/tests/functional/verilog/my_module_xnor.v @@ -0,0 +1,9 @@ +module my_module( + input a, + input b, + output y +); + // Perform operation + assign y = a ~^ b; + +endmodule diff --git a/tests/functional/verilog/my_module_xor.v b/tests/functional/verilog/my_module_xor.v new file mode 100755 index 00000000000..6e241186f97 --- /dev/null +++ b/tests/functional/verilog/my_module_xor.v @@ -0,0 +1,9 @@ +module my_module( + input a, + input b, + output y +); + // Perform operation + assign y = a ^ b; + +endmodule From 59e6c947275220d5f60a585ca25a15db492bbf76 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Sat, 25 May 2024 11:51:00 +0200 Subject: [PATCH 18/51] Check the return code of yosys and of vcd_harness --- tests/functional/run-test.sh | 56 ++++++++++++++++++++++++------------ 1 file changed, 38 insertions(+), 18 deletions(-) diff --git a/tests/functional/run-test.sh b/tests/functional/run-test.sh index 09ee5e0f9a3..b427ee32d12 100755 --- a/tests/functional/run-test.sh +++ b/tests/functional/run-test.sh @@ -2,29 +2,49 @@ set -ex +# Initialize an array to store the names of failing Verilog files +failing_files=() + # Loop through all Verilog files in the verilog directory for verilog_file in verilog/*.v; do # Run yosys to process each Verilog file - ../../yosys -p "read_verilog $verilog_file; write_cxxrtl my_module_cxxrtl.cc; write_functional_cxx my_module_functional_cxx.cc" - - # Compile the generated C++ files with vcd_harness.cpp - ${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cpp -I ../../backends/functional/cxx_runtime/ -I ../../backends/cxxrtl/runtime/ -o vcd_harness - - # Generate VCD files cxxrtl.vcd and functional_cxx.vcd - ./vcd_harness - - # Run vcdiff and capture the output - output=$(vcdiff cxxrtl.vcd functional_cxx.vcd) + if ../../yosys -p "read_verilog $verilog_file; write_cxxrtl my_module_cxxrtl.cc; write_functional_cxx my_module_functional_cxx.cc"; then + echo "Yosys processed $verilog_file successfully." + + # Compile the generated C++ files with vcd_harness.cpp + ${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cpp -I ../../backends/functional/cxx_runtime/ -I ../../backends/cxxrtl/runtime/ -o vcd_harness + + # Generate VCD files cxxrtl.vcd and functional_cxx.vcd + if ./vcd_harness; then + # Run vcdiff and capture the output + output=$(vcdiff cxxrtl.vcd functional_cxx.vcd) - # Check if there is any output - if [ -n "$output" ]; then - echo "Differences detected in $verilog_file:" - echo "$output" - exit 1 + # Check if there is any output + if [ -n "$output" ]; then + echo "Differences detected in $verilog_file:" + echo "$output" + failing_files+=("$verilog_file") + else + echo "No differences detected in $verilog_file." + fi + else + echo "Failed to generate VCD files for $verilog_file." + failing_files+=("$verilog_file") + fi else - echo "No differences detected in $verilog_file." + echo "Yosys failed to process $verilog_file." + failing_files+=("$verilog_file") fi done -# If all files are processed without differences -exit 0 +# Check if the array of failing files is empty +if [ ${#failing_files[@]} -eq 0 ]; then + echo "All files passed." + exit 0 +else + echo "The following files failed:" + for file in "${failing_files[@]}"; do + echo "$file" + done + exit 1 +fi From 83d98c59aa6d99408d52fe6af72667d9f3a100cb Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Sat, 25 May 2024 12:16:58 +0200 Subject: [PATCH 19/51] Specify VCD names to dump --- tests/functional/.gitignore | 3 +-- tests/functional/run-test.sh | 6 +++-- tests/functional/vcd_harness.cpp | 40 ++++++++++++-------------------- 3 files changed, 20 insertions(+), 29 deletions(-) diff --git a/tests/functional/.gitignore b/tests/functional/.gitignore index 6ee14e70604..543226b49dc 100644 --- a/tests/functional/.gitignore +++ b/tests/functional/.gitignore @@ -1,5 +1,4 @@ my_module_cxxrtl.cc my_module_functional_cxx.cc vcd_harness -cxxrtl.vcd -functional_cxx.vcd \ No newline at end of file +*.vcd \ No newline at end of file diff --git a/tests/functional/run-test.sh b/tests/functional/run-test.sh index b427ee32d12..978ae53b919 100755 --- a/tests/functional/run-test.sh +++ b/tests/functional/run-test.sh @@ -7,6 +7,8 @@ failing_files=() # Loop through all Verilog files in the verilog directory for verilog_file in verilog/*.v; do + # Extract the base name without extension + base_name=$(basename "$verilog_file" .v) # Run yosys to process each Verilog file if ../../yosys -p "read_verilog $verilog_file; write_cxxrtl my_module_cxxrtl.cc; write_functional_cxx my_module_functional_cxx.cc"; then echo "Yosys processed $verilog_file successfully." @@ -15,9 +17,9 @@ for verilog_file in verilog/*.v; do ${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cpp -I ../../backends/functional/cxx_runtime/ -I ../../backends/cxxrtl/runtime/ -o vcd_harness # Generate VCD files cxxrtl.vcd and functional_cxx.vcd - if ./vcd_harness; then + if ./vcd_harness ${base_name}_functional_cxx.vcd ${base_name}_cxxrtl.vcd ; then # Run vcdiff and capture the output - output=$(vcdiff cxxrtl.vcd functional_cxx.vcd) + output=$(vcdiff ${base_name}_functional_cxx.vcd ${base_name}_cxxrtl.vcd) # Check if there is any output if [ -n "$output" ]; then diff --git a/tests/functional/vcd_harness.cpp b/tests/functional/vcd_harness.cpp index 76d078b7103..17297962f1d 100644 --- a/tests/functional/vcd_harness.cpp +++ b/tests/functional/vcd_harness.cpp @@ -38,6 +38,14 @@ struct Dump { int main(int argc, char **argv) { + if (argc != 3) { + std::cerr << "Usage: " << argv[0] << " \n"; + return 1; + } + + const std::string functional_vcd_filename = argv[1]; + const std::string cxxrtl_vcd_filename = argv[2]; + constexpr int steps = 10; constexpr int number_timescale = 1; const std::string units_timescale = "us"; @@ -46,50 +54,33 @@ int main(int argc, char **argv) my_module_State state; my_module_State next_state; - std::ofstream vcd_file("functional_cxx.vcd"); + std::ofstream vcd_file(functional_vcd_filename); - vcd_file << "$timescale " << number_timescale << " " << units_timescale << " $end\n"; //$scope module logic $end\n"; + vcd_file << "$timescale " << number_timescale << " " << units_timescale << " $end\n"; { DumpHeader d(vcd_file); inputs.dump(d); outputs.dump(d); - // vcd_file << "$scope module state $end\n"; state.dump(d); } vcd_file << "$enddefinitions $end\n$dumpvars\n"; cxxrtl_design::p_my__module top; - // debug_items maps the hierarchical names of signals and memories in the design - // to a cxxrtl_object (a value, a wire, or a memory) cxxrtl::debug_items all_debug_items; cxxrtl::debug_scope debug_scope; - // Load the debug items of the top down the whole design hierarchy top.debug_info(&all_debug_items, nullptr, ""); - // vcd_writer is the CXXRTL object that's responsible for creating a string with - // the VCD file contents. cxxrtl::vcd_writer vcd; vcd.timescale(number_timescale, units_timescale); - - // Here we tell the vcd writer to dump all the signals of the design, except for the - // memories, to the VCD file. - // - // It's not necessary to load all debug objects to the VCD. There is, for example, - // a vcd.add(, )) method which allows creating your custom filter to decide - // what to add and what not. vcd.add_without_memories(all_debug_items); - std::ofstream waves("cxxrtl.vcd"); + std::ofstream waves(cxxrtl_vcd_filename); top.p_a.set(false); top.p_b.set(false); top.step(); - // We need to manually tell the VCD writer when to sample and write out the traced items. - // This is only a slight inconvenience and allows for complete flexibility. - // E.g. you could only start waveform tracing when an internal signal has reached some specific - // value etc. vcd.sample(0); vcd_file << "#0\n"; inputs.a = $const<1>(false); @@ -101,14 +92,13 @@ int main(int argc, char **argv) state.dump(d); } - // Initialize random number generator std::random_device rd; std::mt19937 gen(rd()); - std::bernoulli_distribution dist(0.5); // 50% chance for true or false - + std::bernoulli_distribution dist(0.5); + for (int step = 0; step < steps; ++step) { - const bool a_value = dist(gen); - const bool b_value = dist(gen); + const bool a_value = dist(gen); + const bool b_value = dist(gen); // cxxrtl top.p_a.set(a_value); From 905db0a17a13a1d92ff32be962ad6e759a251274 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Sat, 25 May 2024 12:26:04 +0200 Subject: [PATCH 20/51] Print type of error --- tests/functional/run-test.sh | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/tests/functional/run-test.sh b/tests/functional/run-test.sh index 978ae53b919..7dc842a797a 100755 --- a/tests/functional/run-test.sh +++ b/tests/functional/run-test.sh @@ -2,13 +2,14 @@ set -ex -# Initialize an array to store the names of failing Verilog files -failing_files=() +# Initialize an array to store the names of failing Verilog files and their failure types +declare -A failing_files # Loop through all Verilog files in the verilog directory for verilog_file in verilog/*.v; do # Extract the base name without extension base_name=$(basename "$verilog_file" .v) + # Run yosys to process each Verilog file if ../../yosys -p "read_verilog $verilog_file; write_cxxrtl my_module_cxxrtl.cc; write_functional_cxx my_module_functional_cxx.cc"; then echo "Yosys processed $verilog_file successfully." @@ -16,7 +17,7 @@ for verilog_file in verilog/*.v; do # Compile the generated C++ files with vcd_harness.cpp ${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cpp -I ../../backends/functional/cxx_runtime/ -I ../../backends/cxxrtl/runtime/ -o vcd_harness - # Generate VCD files cxxrtl.vcd and functional_cxx.vcd + # Generate VCD files with base_name if ./vcd_harness ${base_name}_functional_cxx.vcd ${base_name}_cxxrtl.vcd ; then # Run vcdiff and capture the output output=$(vcdiff ${base_name}_functional_cxx.vcd ${base_name}_cxxrtl.vcd) @@ -25,17 +26,17 @@ for verilog_file in verilog/*.v; do if [ -n "$output" ]; then echo "Differences detected in $verilog_file:" echo "$output" - failing_files+=("$verilog_file") + failing_files["$verilog_file"]="Differences detected" else echo "No differences detected in $verilog_file." fi else echo "Failed to generate VCD files for $verilog_file." - failing_files+=("$verilog_file") + failing_files["$verilog_file"]="VCD generation failure" fi else echo "Yosys failed to process $verilog_file." - failing_files+=("$verilog_file") + failing_files["$verilog_file"]="Yosys failure" fi done @@ -45,8 +46,8 @@ if [ ${#failing_files[@]} -eq 0 ]; then exit 0 else echo "The following files failed:" - for file in "${failing_files[@]}"; do - echo "$file" + for file in "${!failing_files[@]}"; do + echo "$file: ${failing_files[$file]}" done exit 1 fi From 7cbbcaf246126ff66ff64809f7efa833ce9fc60c Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Mon, 27 May 2024 18:12:13 +0200 Subject: [PATCH 21/51] Dump first state only after module is initialized --- tests/functional/vcd_harness.cpp | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/tests/functional/vcd_harness.cpp b/tests/functional/vcd_harness.cpp index 17297962f1d..b12bc54e311 100644 --- a/tests/functional/vcd_harness.cpp +++ b/tests/functional/vcd_harness.cpp @@ -85,13 +85,14 @@ int main(int argc, char **argv) vcd_file << "#0\n"; inputs.a = $const<1>(false); inputs.b = $const<1>(false); + my_module(inputs, outputs, state, next_state); { - Dump d(vcd_file); - inputs.dump(d); - outputs.dump(d); - state.dump(d); + Dump d(vcd_file); + inputs.dump(d); + outputs.dump(d); + state.dump(d); } - + std::random_device rd; std::mt19937 gen(rd()); std::bernoulli_distribution dist(0.5); @@ -113,6 +114,7 @@ int main(int argc, char **argv) vcd_file << "#" << (step + 1) << "\n"; inputs.a = $const<1>(a_value); inputs.b = $const<1>(b_value); + my_module(inputs, outputs, state, next_state); { Dump d(vcd_file); @@ -120,6 +122,7 @@ int main(int argc, char **argv) outputs.dump(d); state.dump(d); } + state = next_state; } From c18d99c250e936301c21b784a41b6b8afe0d07d0 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Mon, 27 May 2024 22:15:00 +0200 Subject: [PATCH 22/51] Implement and test $mul. Use return, not exit in tests --- backends/functional/cxx.cc | 3 +- backends/functional/cxx_runtime/sim.h | 14 ++ backends/functional/smtlib.cc | 3 +- kernel/graphtools.h | 6 + tests/functional/{ => multi_bit}/run-test.sh | 7 +- tests/functional/multi_bit/vcd_harness.cpp | 133 ++++++++++++++++++ tests/functional/multi_bit/verilog/and.v | 9 ++ tests/functional/single_bit/run-test.sh | 69 +++++++++ .../{ => single_bit}/vcd_harness.cpp | 0 .../functional/{ => single_bit}/verilog/add.v | 0 .../functional/{ => single_bit}/verilog/and.v | 0 .../{ => single_bit}/verilog/my_module_div.v | 0 .../{ => single_bit}/verilog/my_module_eqx.v | 0 .../{ => single_bit}/verilog/my_module_ge.v | 0 .../{ => single_bit}/verilog/my_module_gt.v | 0 .../{ => single_bit}/verilog/my_module_le.v | 0 .../verilog/my_module_logic_and.v | 0 .../verilog/my_module_logic_or.v | 0 .../{ => single_bit}/verilog/my_module_lt.v | 0 .../{ => single_bit}/verilog/my_module_mod.v | 0 .../{ => single_bit}/verilog/my_module_mul.v | 0 .../{ => single_bit}/verilog/my_module_ne.v | 0 .../{ => single_bit}/verilog/my_module_nex.v | 0 .../{ => single_bit}/verilog/my_module_or.v | 0 .../{ => single_bit}/verilog/my_module_pow.v | 0 .../{ => single_bit}/verilog/my_module_shl.v | 0 .../{ => single_bit}/verilog/my_module_shr.v | 0 .../{ => single_bit}/verilog/my_module_sshl.v | 0 .../{ => single_bit}/verilog/my_module_sshr.v | 0 .../{ => single_bit}/verilog/my_module_sub.v | 0 .../{ => single_bit}/verilog/my_module_xnor.v | 0 .../{ => single_bit}/verilog/my_module_xor.v | 0 tests/verismith/yosys_all.toml | 33 +++++ 33 files changed, 273 insertions(+), 4 deletions(-) rename tests/functional/{ => multi_bit}/run-test.sh (84%) create mode 100644 tests/functional/multi_bit/vcd_harness.cpp create mode 100644 tests/functional/multi_bit/verilog/and.v create mode 100755 tests/functional/single_bit/run-test.sh rename tests/functional/{ => single_bit}/vcd_harness.cpp (100%) rename tests/functional/{ => single_bit}/verilog/add.v (100%) rename tests/functional/{ => single_bit}/verilog/and.v (100%) rename tests/functional/{ => single_bit}/verilog/my_module_div.v (100%) rename tests/functional/{ => single_bit}/verilog/my_module_eqx.v (100%) rename tests/functional/{ => single_bit}/verilog/my_module_ge.v (100%) rename tests/functional/{ => single_bit}/verilog/my_module_gt.v (100%) rename tests/functional/{ => single_bit}/verilog/my_module_le.v (100%) rename tests/functional/{ => single_bit}/verilog/my_module_logic_and.v (100%) rename tests/functional/{ => single_bit}/verilog/my_module_logic_or.v (100%) rename tests/functional/{ => single_bit}/verilog/my_module_lt.v (100%) rename tests/functional/{ => single_bit}/verilog/my_module_mod.v (100%) rename tests/functional/{ => single_bit}/verilog/my_module_mul.v (100%) rename tests/functional/{ => single_bit}/verilog/my_module_ne.v (100%) rename tests/functional/{ => single_bit}/verilog/my_module_nex.v (100%) rename tests/functional/{ => single_bit}/verilog/my_module_or.v (100%) rename tests/functional/{ => single_bit}/verilog/my_module_pow.v (100%) rename tests/functional/{ => single_bit}/verilog/my_module_shl.v (100%) rename tests/functional/{ => single_bit}/verilog/my_module_shr.v (100%) rename tests/functional/{ => single_bit}/verilog/my_module_sshl.v (100%) rename tests/functional/{ => single_bit}/verilog/my_module_sshr.v (100%) rename tests/functional/{ => single_bit}/verilog/my_module_sub.v (100%) rename tests/functional/{ => single_bit}/verilog/my_module_xnor.v (100%) rename tests/functional/{ => single_bit}/verilog/my_module_xor.v (100%) create mode 100644 tests/verismith/yosys_all.toml diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index a1060c58d79..5623e795bc1 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -189,7 +189,8 @@ class CxxComputeGraphFactory { T logical_shift_left(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($shl), y_width, {{ID(WIDTH), y_width}}), 0, std::array{a, b}); } T logical_shift_right(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($shr), y_width, {{ID(WIDTH), y_width}}), 0, std::array{a, b}); } T arithmetic_shift_right(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($asr), y_width, {{ID(WIDTH), y_width}}), 0, std::array{a, b}); } - + T mul(T a, T b, int width) {return graph.add(CxxFunction(ID($mul), width), 0, std::array{a, b}); } + T constant(RTLIL::Const value) { return graph.add(CxxFunction(ID($$const), value.size(), {{ID(value), value}}), 0); } diff --git a/backends/functional/cxx_runtime/sim.h b/backends/functional/cxx_runtime/sim.h index 829266da0e6..0cbbe9831a1 100644 --- a/backends/functional/cxx_runtime/sim.h +++ b/backends/functional/cxx_runtime/sim.h @@ -365,4 +365,18 @@ Signal $sign_extend(Signal const& a) return ret; } +template +Signal $mul(Signal const& a, Signal const& b) +{ + Signal ret = $const(0); + + for(size_t i = 0; i < n; i++) { + if(b[i]) { + Signal shifted_a = $shl($zero_extend(a), $const(i)); + ret = $add(ret, shifted_a); + } + } + return ret; +} + #endif diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index cd11111b9d8..2811d0bea7e 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -367,7 +367,8 @@ class SmtlibComputeGraphFactory { T logical_shift_left(T a, T b, int y_width, int b_width) { return shift("bvshl", a, b, y_width, b_width); } T logical_shift_right(T a, T b, int y_width, int b_width) { return shift("bvlshl", a, b, y_width, b_width); } T arithmetic_shift_right(T a, T b, int y_width, int b_width) { return shift("bvashr", a, b, y_width, b_width, true); } - + T mul(T a, T b, int width) { return node(SExpr {"bvmul", Arg(1), Arg(2)}, width, {a, b}); } + T constant(RTLIL::Const value) { return node(SExpr(value), value.size(), {}); } T input(IdString name, int width) { module.input_struct.insert(name, width); diff --git a/kernel/graphtools.h b/kernel/graphtools.h index adf4764c201..1c6b927739d 100644 --- a/kernel/graphtools.h +++ b/kernel/graphtools.h @@ -183,6 +183,12 @@ class CellSimplifier { int offset = parameters.at(ID(OFFSET)).as_int(); T a = inputs.at(ID(A)); return factory.slice(a, a_width, offset, y_width); + }else if(cellType == ID($mul)){ + bool is_signed = a_signed && b_signed; + int width = a_width + b_width; + T a = extend(inputs.at(ID(A)), a_width, width, is_signed); + T b = extend(inputs.at(ID(B)), b_width, width, is_signed); + return extend(factory.mul(a, b, width), width, y_width, is_signed); }else{ log_error("unhandled cell in CellSimplifier %s\n", cellType.c_str()); } diff --git a/tests/functional/run-test.sh b/tests/functional/multi_bit/run-test.sh similarity index 84% rename from tests/functional/run-test.sh rename to tests/functional/multi_bit/run-test.sh index 7dc842a797a..421630d5be5 100755 --- a/tests/functional/run-test.sh +++ b/tests/functional/multi_bit/run-test.sh @@ -2,6 +2,9 @@ set -ex +# Define the common variable for the relative path +BASE_PATH="../../../" + # Initialize an array to store the names of failing Verilog files and their failure types declare -A failing_files @@ -11,11 +14,11 @@ for verilog_file in verilog/*.v; do base_name=$(basename "$verilog_file" .v) # Run yosys to process each Verilog file - if ../../yosys -p "read_verilog $verilog_file; write_cxxrtl my_module_cxxrtl.cc; write_functional_cxx my_module_functional_cxx.cc"; then + if ${BASE_PATH}yosys -p "read_verilog $verilog_file; write_cxxrtl my_module_cxxrtl.cc; write_functional_cxx my_module_functional_cxx.cc"; then echo "Yosys processed $verilog_file successfully." # Compile the generated C++ files with vcd_harness.cpp - ${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cpp -I ../../backends/functional/cxx_runtime/ -I ../../backends/cxxrtl/runtime/ -o vcd_harness + ${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cpp -I ${BASE_PATH}backends/functional/cxx_runtime/ -I ${BASE_PATH}backends/cxxrtl/runtime/ -o vcd_harness # Generate VCD files with base_name if ./vcd_harness ${base_name}_functional_cxx.vcd ${base_name}_cxxrtl.vcd ; then diff --git a/tests/functional/multi_bit/vcd_harness.cpp b/tests/functional/multi_bit/vcd_harness.cpp new file mode 100644 index 00000000000..bb8cca6fc8d --- /dev/null +++ b/tests/functional/multi_bit/vcd_harness.cpp @@ -0,0 +1,133 @@ +#include +#include +#include +#include + +#include + +#include "my_module_cxxrtl.cc" +#include "my_module_functional_cxx.cc" + +struct DumpHeader { + std::ofstream &ofs; + DumpHeader(std::ofstream &ofs) : ofs(ofs) {} + template + void operator()(const char *name, Signal value) { + ofs << "$var wire " << n << " " << name[0] << " " << name << " $end\n"; + } +}; + +struct Dump { + std::ofstream &ofs; + Dump(std::ofstream &ofs) : ofs(ofs) {} + template + void operator()(const char *name, Signal value) { + // Bit + if (n == 1) { + ofs << (value[0] ? '1' : '0'); + ofs << name[0] << "\n"; + return; + } + // vector (multi-bit) signals + ofs << "b"; + for (size_t i = n; i-- > 0;) + ofs << (value[i] ? '1' : '0'); + ofs << " " << name[0] << "\n"; + } +}; + +int main(int argc, char **argv) +{ + if (argc != 3) { + std::cerr << "Usage: " << argv[0] << " \n"; + return 1; + } + + const std::string functional_vcd_filename = argv[1]; + const std::string cxxrtl_vcd_filename = argv[2]; + + constexpr int steps = 10; + constexpr int number_timescale = 1; + const std::string units_timescale = "us"; + my_module_Inputs inputs; + my_module_Outputs outputs; + my_module_State state; + my_module_State next_state; + + std::ofstream vcd_file(functional_vcd_filename); + + vcd_file << "$timescale " << number_timescale << " " << units_timescale << " $end\n"; + { + DumpHeader d(vcd_file); + inputs.dump(d); + outputs.dump(d); + state.dump(d); + } + vcd_file << "$enddefinitions $end\n$dumpvars\n"; + + cxxrtl_design::p_my__module top; + + cxxrtl::debug_items all_debug_items; + cxxrtl::debug_scope debug_scope; + top.debug_info(&all_debug_items, nullptr, ""); + + cxxrtl::vcd_writer vcd; + vcd.timescale(number_timescale, units_timescale); + vcd.add_without_memories(all_debug_items); + + std::ofstream waves(cxxrtl_vcd_filename); + + top.p_a.set<8>(false); + top.p_b.set<8>(false); + top.step(); + + vcd.sample(0); + vcd_file << "#0\n"; + inputs.a = $const<8>(false); + inputs.b = $const<8>(false); + my_module(inputs, outputs, state, next_state); + { + Dump d(vcd_file); + inputs.dump(d); + outputs.dump(d); + state.dump(d); + } + + std::random_device rd; + std::mt19937 gen(rd()); + std::bernoulli_distribution dist(0.5); + + for (int step = 0; step < steps; ++step) { + const bool a_value = dist(gen); + const bool b_value = dist(gen); + + // cxxrtl + top.p_a.set(a_value); + top.p_b.set(b_value); + top.step(); + vcd.sample(step + 1); + + waves << vcd.buffer; + vcd.buffer.clear(); + + // Functional backend cxx + vcd_file << "#" << (step + 1) << "\n"; + inputs.a = $const<8>(a_value); + inputs.b = $const<8>(b_value); + + my_module(inputs, outputs, state, next_state); + { + Dump d(vcd_file); + inputs.dump(d); + outputs.dump(d); + state.dump(d); + } + + state = next_state; + } + + vcd_file.close(); + waves.close(); + + return 0; +} diff --git a/tests/functional/multi_bit/verilog/and.v b/tests/functional/multi_bit/verilog/and.v new file mode 100644 index 00000000000..be20c778e65 --- /dev/null +++ b/tests/functional/multi_bit/verilog/and.v @@ -0,0 +1,9 @@ +module my_module( + input [7:0] a, + input [7:0] b, + output [7:0] y +); + // Perform bitwise AND + assign y = a & b; + +endmodule diff --git a/tests/functional/single_bit/run-test.sh b/tests/functional/single_bit/run-test.sh new file mode 100755 index 00000000000..ff5636f93f9 --- /dev/null +++ b/tests/functional/single_bit/run-test.sh @@ -0,0 +1,69 @@ +#!/bin/bash + +# Initialize an array to store the names of failing Verilog files and their failure types +declare -A failing_files + +# Function to run the test on a given Verilog file +run_test() { + # Define the common variable for the relative path + BASE_PATH="../../../" + + local verilog_file=$1 + + # Extract the base name without extension + local base_name=$(basename "$verilog_file" .v) + + # Run yosys to process each Verilog file + if ${BASE_PATH}yosys -p "read_verilog $verilog_file; write_cxxrtl my_module_cxxrtl.cc; write_functional_cxx my_module_functional_cxx.cc"; then + echo "Yosys processed $verilog_file successfully." + + # Compile the generated C++ files with vcd_harness.cpp + ${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cpp -I ${BASE_PATH}backends/functional/cxx_runtime/ -I ${BASE_PATH}backends/cxxrtl/runtime/ -o vcd_harness + + # Generate VCD files with base_name + if ./vcd_harness ${base_name}_functional_cxx.vcd ${base_name}_cxxrtl.vcd ; then + # Run vcdiff and capture the output + local output=$(vcdiff ${base_name}_functional_cxx.vcd ${base_name}_cxxrtl.vcd) + + # Check if there is any output + if [ -n "$output" ]; then + echo "Differences detected in $verilog_file:" + echo "$output" + failing_files["$verilog_file"]="Differences detected" + else + echo "No differences detected in $verilog_file." + fi + else + echo "Failed to generate VCD files for $verilog_file." + failing_files["$verilog_file"]="VCD generation failure" + fi + else + echo "Yosys failed to process $verilog_file." + failing_files["$verilog_file"]="Yosys failure" + fi +} + +# Main function to run all tests +run_all_tests() { + # Loop through all Verilog files in the verilog directory + for verilog_file in verilog/*.v; do + run_test "$verilog_file" + done + + # Check if the array of failing files is empty + if [ ${#failing_files[@]} -eq 0 ]; then + echo "All files passed." + return 0 + else + echo "The following files failed:" + for file in "${!failing_files[@]}"; do + echo "$file: ${failing_files[$file]}" + done + return 1 + fi +} + +# If the script is being sourced, do not execute the tests +if [[ "${BASH_SOURCE[0]}" == "${0}" ]]; then + run_all_tests +fi diff --git a/tests/functional/vcd_harness.cpp b/tests/functional/single_bit/vcd_harness.cpp similarity index 100% rename from tests/functional/vcd_harness.cpp rename to tests/functional/single_bit/vcd_harness.cpp diff --git a/tests/functional/verilog/add.v b/tests/functional/single_bit/verilog/add.v similarity index 100% rename from tests/functional/verilog/add.v rename to tests/functional/single_bit/verilog/add.v diff --git a/tests/functional/verilog/and.v b/tests/functional/single_bit/verilog/and.v similarity index 100% rename from tests/functional/verilog/and.v rename to tests/functional/single_bit/verilog/and.v diff --git a/tests/functional/verilog/my_module_div.v b/tests/functional/single_bit/verilog/my_module_div.v similarity index 100% rename from tests/functional/verilog/my_module_div.v rename to tests/functional/single_bit/verilog/my_module_div.v diff --git a/tests/functional/verilog/my_module_eqx.v b/tests/functional/single_bit/verilog/my_module_eqx.v similarity index 100% rename from tests/functional/verilog/my_module_eqx.v rename to tests/functional/single_bit/verilog/my_module_eqx.v diff --git a/tests/functional/verilog/my_module_ge.v b/tests/functional/single_bit/verilog/my_module_ge.v similarity index 100% rename from tests/functional/verilog/my_module_ge.v rename to tests/functional/single_bit/verilog/my_module_ge.v diff --git a/tests/functional/verilog/my_module_gt.v b/tests/functional/single_bit/verilog/my_module_gt.v similarity index 100% rename from tests/functional/verilog/my_module_gt.v rename to tests/functional/single_bit/verilog/my_module_gt.v diff --git a/tests/functional/verilog/my_module_le.v b/tests/functional/single_bit/verilog/my_module_le.v similarity index 100% rename from tests/functional/verilog/my_module_le.v rename to tests/functional/single_bit/verilog/my_module_le.v diff --git a/tests/functional/verilog/my_module_logic_and.v b/tests/functional/single_bit/verilog/my_module_logic_and.v similarity index 100% rename from tests/functional/verilog/my_module_logic_and.v rename to tests/functional/single_bit/verilog/my_module_logic_and.v diff --git a/tests/functional/verilog/my_module_logic_or.v b/tests/functional/single_bit/verilog/my_module_logic_or.v similarity index 100% rename from tests/functional/verilog/my_module_logic_or.v rename to tests/functional/single_bit/verilog/my_module_logic_or.v diff --git a/tests/functional/verilog/my_module_lt.v b/tests/functional/single_bit/verilog/my_module_lt.v similarity index 100% rename from tests/functional/verilog/my_module_lt.v rename to tests/functional/single_bit/verilog/my_module_lt.v diff --git a/tests/functional/verilog/my_module_mod.v b/tests/functional/single_bit/verilog/my_module_mod.v similarity index 100% rename from tests/functional/verilog/my_module_mod.v rename to tests/functional/single_bit/verilog/my_module_mod.v diff --git a/tests/functional/verilog/my_module_mul.v b/tests/functional/single_bit/verilog/my_module_mul.v similarity index 100% rename from tests/functional/verilog/my_module_mul.v rename to tests/functional/single_bit/verilog/my_module_mul.v diff --git a/tests/functional/verilog/my_module_ne.v b/tests/functional/single_bit/verilog/my_module_ne.v similarity index 100% rename from tests/functional/verilog/my_module_ne.v rename to tests/functional/single_bit/verilog/my_module_ne.v diff --git a/tests/functional/verilog/my_module_nex.v b/tests/functional/single_bit/verilog/my_module_nex.v similarity index 100% rename from tests/functional/verilog/my_module_nex.v rename to tests/functional/single_bit/verilog/my_module_nex.v diff --git a/tests/functional/verilog/my_module_or.v b/tests/functional/single_bit/verilog/my_module_or.v similarity index 100% rename from tests/functional/verilog/my_module_or.v rename to tests/functional/single_bit/verilog/my_module_or.v diff --git a/tests/functional/verilog/my_module_pow.v b/tests/functional/single_bit/verilog/my_module_pow.v similarity index 100% rename from tests/functional/verilog/my_module_pow.v rename to tests/functional/single_bit/verilog/my_module_pow.v diff --git a/tests/functional/verilog/my_module_shl.v b/tests/functional/single_bit/verilog/my_module_shl.v similarity index 100% rename from tests/functional/verilog/my_module_shl.v rename to tests/functional/single_bit/verilog/my_module_shl.v diff --git a/tests/functional/verilog/my_module_shr.v b/tests/functional/single_bit/verilog/my_module_shr.v similarity index 100% rename from tests/functional/verilog/my_module_shr.v rename to tests/functional/single_bit/verilog/my_module_shr.v diff --git a/tests/functional/verilog/my_module_sshl.v b/tests/functional/single_bit/verilog/my_module_sshl.v similarity index 100% rename from tests/functional/verilog/my_module_sshl.v rename to tests/functional/single_bit/verilog/my_module_sshl.v diff --git a/tests/functional/verilog/my_module_sshr.v b/tests/functional/single_bit/verilog/my_module_sshr.v similarity index 100% rename from tests/functional/verilog/my_module_sshr.v rename to tests/functional/single_bit/verilog/my_module_sshr.v diff --git a/tests/functional/verilog/my_module_sub.v b/tests/functional/single_bit/verilog/my_module_sub.v similarity index 100% rename from tests/functional/verilog/my_module_sub.v rename to tests/functional/single_bit/verilog/my_module_sub.v diff --git a/tests/functional/verilog/my_module_xnor.v b/tests/functional/single_bit/verilog/my_module_xnor.v similarity index 100% rename from tests/functional/verilog/my_module_xnor.v rename to tests/functional/single_bit/verilog/my_module_xnor.v diff --git a/tests/functional/verilog/my_module_xor.v b/tests/functional/single_bit/verilog/my_module_xor.v similarity index 100% rename from tests/functional/verilog/my_module_xor.v rename to tests/functional/single_bit/verilog/my_module_xor.v diff --git a/tests/verismith/yosys_all.toml b/tests/verismith/yosys_all.toml new file mode 100644 index 00000000000..a60a8371db5 --- /dev/null +++ b/tests/verismith/yosys_all.toml @@ -0,0 +1,33 @@ +[probability] + expr.binary = 5 + expr.concatenation = 5 + expr.number = 1 + expr.rangeselect = 5 + expr.signed = 5 + expr.string = 0 + expr.ternary = 5 + expr.unary = 5 + expr.unsigned = 5 + expr.variable = 5 + moditem.assign = 2 + moditem.combinational = 0 + moditem.instantiation = 0 + moditem.sequential = 3 + statement.blocking = 0 + statement.conditional = 1 + statement.forloop = 0 + statement.nonblocking = 2 + +[property] + module.depth = 2 + module.max = 5 + size = 20 + statement.depth = 7 + sample.method = "hat" + sample.size = 10 + +[[synthesiser]] + name = "yosys" + description = "yosys_nix" + output = "yosys_nix.v" + bin = "/nix/store/fzqckbn2ajj6illgrbcja6fj8qzrbacb-yosys/bin/" \ No newline at end of file From 4bfb50e56edaf421fe787dce66818c48315bbca3 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Tue, 28 May 2024 06:11:27 +0200 Subject: [PATCH 23/51] vcdiff gives error output on stderr --- tests/functional/single_bit/run-test.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/functional/single_bit/run-test.sh b/tests/functional/single_bit/run-test.sh index ff5636f93f9..4d5d8747f6e 100755 --- a/tests/functional/single_bit/run-test.sh +++ b/tests/functional/single_bit/run-test.sh @@ -21,9 +21,9 @@ run_test() { ${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cpp -I ${BASE_PATH}backends/functional/cxx_runtime/ -I ${BASE_PATH}backends/cxxrtl/runtime/ -o vcd_harness # Generate VCD files with base_name - if ./vcd_harness ${base_name}_functional_cxx.vcd ${base_name}_cxxrtl.vcd ; then + if ./vcd_harness ${base_name}_functional_cxx.vcd ${base_name}_cxxrtl.vcd; then # Run vcdiff and capture the output - local output=$(vcdiff ${base_name}_functional_cxx.vcd ${base_name}_cxxrtl.vcd) + local output=$(vcdiff ${base_name}_functional_cxx.vcd ${base_name}_cxxrtl.vcd 2>&1) # Check if there is any output if [ -n "$output" ]; then From 44e073fee9656119c12b8dc2a8d88d76954e2e7c Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Tue, 28 May 2024 11:52:50 +0200 Subject: [PATCH 24/51] Compare with sim -sim-cmp, not vcdiff --- backends/functional/cxx.cc | 2 +- tests/functional/single_bit/run-test.sh | 20 +++++++++----------- tests/functional/single_bit/vcd_harness.cpp | 1 + 3 files changed, 11 insertions(+), 12 deletions(-) diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index 5623e795bc1..a4153035dad 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -189,7 +189,7 @@ class CxxComputeGraphFactory { T logical_shift_left(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($shl), y_width, {{ID(WIDTH), y_width}}), 0, std::array{a, b}); } T logical_shift_right(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($shr), y_width, {{ID(WIDTH), y_width}}), 0, std::array{a, b}); } T arithmetic_shift_right(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($asr), y_width, {{ID(WIDTH), y_width}}), 0, std::array{a, b}); } - T mul(T a, T b, int width) {return graph.add(CxxFunction(ID($mul), width), 0, std::array{a, b}); } + T mul(T a, T b, int width) { return graph.add(CxxFunction(ID($mul), width), 0, std::array{a, b}); } T constant(RTLIL::Const value) { return graph.add(CxxFunction(ID($$const), value.size(), {{ID(value), value}}), 0); diff --git a/tests/functional/single_bit/run-test.sh b/tests/functional/single_bit/run-test.sh index 4d5d8747f6e..2eba8367483 100755 --- a/tests/functional/single_bit/run-test.sh +++ b/tests/functional/single_bit/run-test.sh @@ -22,17 +22,15 @@ run_test() { # Generate VCD files with base_name if ./vcd_harness ${base_name}_functional_cxx.vcd ${base_name}_cxxrtl.vcd; then - # Run vcdiff and capture the output - local output=$(vcdiff ${base_name}_functional_cxx.vcd ${base_name}_cxxrtl.vcd 2>&1) - - # Check if there is any output - if [ -n "$output" ]; then - echo "Differences detected in $verilog_file:" - echo "$output" - failing_files["$verilog_file"]="Differences detected" - else - echo "No differences detected in $verilog_file." - fi + + # Run yosys to process each Verilog file + if ${BASE_PATH}yosys -p "read_verilog $verilog_file; sim -r ${base_name}_functional_cxx.vcd -scope my_module -timescale 1us -sim-cmp"; then + echo "Yosys sim $verilog_file successfully." + else + echo "Yosys simulation of $verilog_file failed. There is a discrepancy with functional cxx" + failing_files["$verilog_file"]="Yosys sim failure" + fi + else echo "Failed to generate VCD files for $verilog_file." failing_files["$verilog_file"]="VCD generation failure" diff --git a/tests/functional/single_bit/vcd_harness.cpp b/tests/functional/single_bit/vcd_harness.cpp index b12bc54e311..7e474eea985 100644 --- a/tests/functional/single_bit/vcd_harness.cpp +++ b/tests/functional/single_bit/vcd_harness.cpp @@ -57,6 +57,7 @@ int main(int argc, char **argv) std::ofstream vcd_file(functional_vcd_filename); vcd_file << "$timescale " << number_timescale << " " << units_timescale << " $end\n"; + vcd_file << "$scope module my_module $end\n"; { DumpHeader d(vcd_file); inputs.dump(d); From 1628ac38c51c82b388267c73e0f4cc05b7e8cd13 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Tue, 28 May 2024 12:20:39 +0200 Subject: [PATCH 25/51] Copy test to cxxrtl to not forget --- tests/cxxrtl/sim_test.sh | 67 +++++++++ .../vcd_harness.cpp => cxxrtl/vcd_harness.cc} | 0 tests/functional/single_bit/vcd_harness.cc | 134 ++++++++++++++++++ 3 files changed, 201 insertions(+) create mode 100755 tests/cxxrtl/sim_test.sh rename tests/{functional/single_bit/vcd_harness.cpp => cxxrtl/vcd_harness.cc} (100%) create mode 100644 tests/functional/single_bit/vcd_harness.cc diff --git a/tests/cxxrtl/sim_test.sh b/tests/cxxrtl/sim_test.sh new file mode 100755 index 00000000000..2eba8367483 --- /dev/null +++ b/tests/cxxrtl/sim_test.sh @@ -0,0 +1,67 @@ +#!/bin/bash + +# Initialize an array to store the names of failing Verilog files and their failure types +declare -A failing_files + +# Function to run the test on a given Verilog file +run_test() { + # Define the common variable for the relative path + BASE_PATH="../../../" + + local verilog_file=$1 + + # Extract the base name without extension + local base_name=$(basename "$verilog_file" .v) + + # Run yosys to process each Verilog file + if ${BASE_PATH}yosys -p "read_verilog $verilog_file; write_cxxrtl my_module_cxxrtl.cc; write_functional_cxx my_module_functional_cxx.cc"; then + echo "Yosys processed $verilog_file successfully." + + # Compile the generated C++ files with vcd_harness.cpp + ${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cpp -I ${BASE_PATH}backends/functional/cxx_runtime/ -I ${BASE_PATH}backends/cxxrtl/runtime/ -o vcd_harness + + # Generate VCD files with base_name + if ./vcd_harness ${base_name}_functional_cxx.vcd ${base_name}_cxxrtl.vcd; then + + # Run yosys to process each Verilog file + if ${BASE_PATH}yosys -p "read_verilog $verilog_file; sim -r ${base_name}_functional_cxx.vcd -scope my_module -timescale 1us -sim-cmp"; then + echo "Yosys sim $verilog_file successfully." + else + echo "Yosys simulation of $verilog_file failed. There is a discrepancy with functional cxx" + failing_files["$verilog_file"]="Yosys sim failure" + fi + + else + echo "Failed to generate VCD files for $verilog_file." + failing_files["$verilog_file"]="VCD generation failure" + fi + else + echo "Yosys failed to process $verilog_file." + failing_files["$verilog_file"]="Yosys failure" + fi +} + +# Main function to run all tests +run_all_tests() { + # Loop through all Verilog files in the verilog directory + for verilog_file in verilog/*.v; do + run_test "$verilog_file" + done + + # Check if the array of failing files is empty + if [ ${#failing_files[@]} -eq 0 ]; then + echo "All files passed." + return 0 + else + echo "The following files failed:" + for file in "${!failing_files[@]}"; do + echo "$file: ${failing_files[$file]}" + done + return 1 + fi +} + +# If the script is being sourced, do not execute the tests +if [[ "${BASH_SOURCE[0]}" == "${0}" ]]; then + run_all_tests +fi diff --git a/tests/functional/single_bit/vcd_harness.cpp b/tests/cxxrtl/vcd_harness.cc similarity index 100% rename from tests/functional/single_bit/vcd_harness.cpp rename to tests/cxxrtl/vcd_harness.cc diff --git a/tests/functional/single_bit/vcd_harness.cc b/tests/functional/single_bit/vcd_harness.cc new file mode 100644 index 00000000000..7e474eea985 --- /dev/null +++ b/tests/functional/single_bit/vcd_harness.cc @@ -0,0 +1,134 @@ +#include +#include +#include +#include + +#include + +#include "my_module_cxxrtl.cc" +#include "my_module_functional_cxx.cc" + +struct DumpHeader { + std::ofstream &ofs; + DumpHeader(std::ofstream &ofs) : ofs(ofs) {} + template + void operator()(const char *name, Signal value) { + ofs << "$var wire " << n << " " << name[0] << " " << name << " $end\n"; + } +}; + +struct Dump { + std::ofstream &ofs; + Dump(std::ofstream &ofs) : ofs(ofs) {} + template + void operator()(const char *name, Signal value) { + // Bit + if (n == 1) { + ofs << (value[0] ? '1' : '0'); + ofs << name[0] << "\n"; + return; + } + // vector (multi-bit) signals + ofs << "b"; + for (size_t i = n; i-- > 0;) + ofs << (value[i] ? '1' : '0'); + ofs << " " << name[0] << "\n"; + } +}; + +int main(int argc, char **argv) +{ + if (argc != 3) { + std::cerr << "Usage: " << argv[0] << " \n"; + return 1; + } + + const std::string functional_vcd_filename = argv[1]; + const std::string cxxrtl_vcd_filename = argv[2]; + + constexpr int steps = 10; + constexpr int number_timescale = 1; + const std::string units_timescale = "us"; + my_module_Inputs inputs; + my_module_Outputs outputs; + my_module_State state; + my_module_State next_state; + + std::ofstream vcd_file(functional_vcd_filename); + + vcd_file << "$timescale " << number_timescale << " " << units_timescale << " $end\n"; + vcd_file << "$scope module my_module $end\n"; + { + DumpHeader d(vcd_file); + inputs.dump(d); + outputs.dump(d); + state.dump(d); + } + vcd_file << "$enddefinitions $end\n$dumpvars\n"; + + cxxrtl_design::p_my__module top; + + cxxrtl::debug_items all_debug_items; + cxxrtl::debug_scope debug_scope; + top.debug_info(&all_debug_items, nullptr, ""); + + cxxrtl::vcd_writer vcd; + vcd.timescale(number_timescale, units_timescale); + vcd.add_without_memories(all_debug_items); + + std::ofstream waves(cxxrtl_vcd_filename); + + top.p_a.set(false); + top.p_b.set(false); + top.step(); + + vcd.sample(0); + vcd_file << "#0\n"; + inputs.a = $const<1>(false); + inputs.b = $const<1>(false); + my_module(inputs, outputs, state, next_state); + { + Dump d(vcd_file); + inputs.dump(d); + outputs.dump(d); + state.dump(d); + } + + std::random_device rd; + std::mt19937 gen(rd()); + std::bernoulli_distribution dist(0.5); + + for (int step = 0; step < steps; ++step) { + const bool a_value = dist(gen); + const bool b_value = dist(gen); + + // cxxrtl + top.p_a.set(a_value); + top.p_b.set(b_value); + top.step(); + vcd.sample(step + 1); + + waves << vcd.buffer; + vcd.buffer.clear(); + + // Functional backend cxx + vcd_file << "#" << (step + 1) << "\n"; + inputs.a = $const<1>(a_value); + inputs.b = $const<1>(b_value); + + my_module(inputs, outputs, state, next_state); + { + Dump d(vcd_file); + inputs.dump(d); + outputs.dump(d); + state.dump(d); + } + + state = next_state; + } + + vcd_file.close(); + waves.close(); + + return 0; +} From 4b5c366bf40afd08d55732836a7afb7bef07ce11 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Tue, 28 May 2024 12:25:21 +0200 Subject: [PATCH 26/51] Remove cxxrtl from functional backend C++ testing, using yosys sim -sim-cmp instead --- tests/functional/single_bit/run-test.sh | 6 ++-- tests/functional/single_bit/vcd_harness.cc | 36 ++-------------------- 2 files changed, 5 insertions(+), 37 deletions(-) diff --git a/tests/functional/single_bit/run-test.sh b/tests/functional/single_bit/run-test.sh index 2eba8367483..d71a2c90fb8 100755 --- a/tests/functional/single_bit/run-test.sh +++ b/tests/functional/single_bit/run-test.sh @@ -14,14 +14,14 @@ run_test() { local base_name=$(basename "$verilog_file" .v) # Run yosys to process each Verilog file - if ${BASE_PATH}yosys -p "read_verilog $verilog_file; write_cxxrtl my_module_cxxrtl.cc; write_functional_cxx my_module_functional_cxx.cc"; then + if ${BASE_PATH}yosys -p "read_verilog $verilog_file; write_functional_cxx my_module_functional_cxx.cc"; then echo "Yosys processed $verilog_file successfully." # Compile the generated C++ files with vcd_harness.cpp - ${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cpp -I ${BASE_PATH}backends/functional/cxx_runtime/ -I ${BASE_PATH}backends/cxxrtl/runtime/ -o vcd_harness + ${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cc -I ${BASE_PATH}backends/functional/cxx_runtime/ -o vcd_harness # Generate VCD files with base_name - if ./vcd_harness ${base_name}_functional_cxx.vcd ${base_name}_cxxrtl.vcd; then + if ./vcd_harness ${base_name}_functional_cxx.vcd; then # Run yosys to process each Verilog file if ${BASE_PATH}yosys -p "read_verilog $verilog_file; sim -r ${base_name}_functional_cxx.vcd -scope my_module -timescale 1us -sim-cmp"; then diff --git a/tests/functional/single_bit/vcd_harness.cc b/tests/functional/single_bit/vcd_harness.cc index 7e474eea985..2086ef6fdcd 100644 --- a/tests/functional/single_bit/vcd_harness.cc +++ b/tests/functional/single_bit/vcd_harness.cc @@ -3,9 +3,6 @@ #include #include -#include - -#include "my_module_cxxrtl.cc" #include "my_module_functional_cxx.cc" struct DumpHeader { @@ -38,13 +35,12 @@ struct Dump { int main(int argc, char **argv) { - if (argc != 3) { - std::cerr << "Usage: " << argv[0] << " \n"; + if (argc != 2) { + std::cerr << "Usage: " << argv[0] << " \n"; return 1; } const std::string functional_vcd_filename = argv[1]; - const std::string cxxrtl_vcd_filename = argv[2]; constexpr int steps = 10; constexpr int number_timescale = 1; @@ -65,24 +61,6 @@ int main(int argc, char **argv) state.dump(d); } vcd_file << "$enddefinitions $end\n$dumpvars\n"; - - cxxrtl_design::p_my__module top; - - cxxrtl::debug_items all_debug_items; - cxxrtl::debug_scope debug_scope; - top.debug_info(&all_debug_items, nullptr, ""); - - cxxrtl::vcd_writer vcd; - vcd.timescale(number_timescale, units_timescale); - vcd.add_without_memories(all_debug_items); - - std::ofstream waves(cxxrtl_vcd_filename); - - top.p_a.set(false); - top.p_b.set(false); - top.step(); - - vcd.sample(0); vcd_file << "#0\n"; inputs.a = $const<1>(false); inputs.b = $const<1>(false); @@ -102,15 +80,6 @@ int main(int argc, char **argv) const bool a_value = dist(gen); const bool b_value = dist(gen); - // cxxrtl - top.p_a.set(a_value); - top.p_b.set(b_value); - top.step(); - vcd.sample(step + 1); - - waves << vcd.buffer; - vcd.buffer.clear(); - // Functional backend cxx vcd_file << "#" << (step + 1) << "\n"; inputs.a = $const<1>(a_value); @@ -128,7 +97,6 @@ int main(int argc, char **argv) } vcd_file.close(); - waves.close(); return 0; } From 89d9339907424805be1bf89f812741999b7789a3 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Tue, 28 May 2024 12:32:07 +0200 Subject: [PATCH 27/51] WIP --- tests/functional/multi_bit/run-test.sh | 75 +++++++++++-------- .../{vcd_harness.cpp => vcd_harness.cc} | 41 ++-------- 2 files changed, 48 insertions(+), 68 deletions(-) rename tests/functional/multi_bit/{vcd_harness.cpp => vcd_harness.cc} (72%) diff --git a/tests/functional/multi_bit/run-test.sh b/tests/functional/multi_bit/run-test.sh index 421630d5be5..d71a2c90fb8 100755 --- a/tests/functional/multi_bit/run-test.sh +++ b/tests/functional/multi_bit/run-test.sh @@ -1,38 +1,36 @@ #!/bin/bash -set -ex - -# Define the common variable for the relative path -BASE_PATH="../../../" - # Initialize an array to store the names of failing Verilog files and their failure types declare -A failing_files -# Loop through all Verilog files in the verilog directory -for verilog_file in verilog/*.v; do +# Function to run the test on a given Verilog file +run_test() { + # Define the common variable for the relative path + BASE_PATH="../../../" + + local verilog_file=$1 + # Extract the base name without extension - base_name=$(basename "$verilog_file" .v) + local base_name=$(basename "$verilog_file" .v) # Run yosys to process each Verilog file - if ${BASE_PATH}yosys -p "read_verilog $verilog_file; write_cxxrtl my_module_cxxrtl.cc; write_functional_cxx my_module_functional_cxx.cc"; then + if ${BASE_PATH}yosys -p "read_verilog $verilog_file; write_functional_cxx my_module_functional_cxx.cc"; then echo "Yosys processed $verilog_file successfully." # Compile the generated C++ files with vcd_harness.cpp - ${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cpp -I ${BASE_PATH}backends/functional/cxx_runtime/ -I ${BASE_PATH}backends/cxxrtl/runtime/ -o vcd_harness + ${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cc -I ${BASE_PATH}backends/functional/cxx_runtime/ -o vcd_harness # Generate VCD files with base_name - if ./vcd_harness ${base_name}_functional_cxx.vcd ${base_name}_cxxrtl.vcd ; then - # Run vcdiff and capture the output - output=$(vcdiff ${base_name}_functional_cxx.vcd ${base_name}_cxxrtl.vcd) - - # Check if there is any output - if [ -n "$output" ]; then - echo "Differences detected in $verilog_file:" - echo "$output" - failing_files["$verilog_file"]="Differences detected" - else - echo "No differences detected in $verilog_file." - fi + if ./vcd_harness ${base_name}_functional_cxx.vcd; then + + # Run yosys to process each Verilog file + if ${BASE_PATH}yosys -p "read_verilog $verilog_file; sim -r ${base_name}_functional_cxx.vcd -scope my_module -timescale 1us -sim-cmp"; then + echo "Yosys sim $verilog_file successfully." + else + echo "Yosys simulation of $verilog_file failed. There is a discrepancy with functional cxx" + failing_files["$verilog_file"]="Yosys sim failure" + fi + else echo "Failed to generate VCD files for $verilog_file." failing_files["$verilog_file"]="VCD generation failure" @@ -41,16 +39,29 @@ for verilog_file in verilog/*.v; do echo "Yosys failed to process $verilog_file." failing_files["$verilog_file"]="Yosys failure" fi -done +} -# Check if the array of failing files is empty -if [ ${#failing_files[@]} -eq 0 ]; then - echo "All files passed." - exit 0 -else - echo "The following files failed:" - for file in "${!failing_files[@]}"; do - echo "$file: ${failing_files[$file]}" +# Main function to run all tests +run_all_tests() { + # Loop through all Verilog files in the verilog directory + for verilog_file in verilog/*.v; do + run_test "$verilog_file" done - exit 1 + + # Check if the array of failing files is empty + if [ ${#failing_files[@]} -eq 0 ]; then + echo "All files passed." + return 0 + else + echo "The following files failed:" + for file in "${!failing_files[@]}"; do + echo "$file: ${failing_files[$file]}" + done + return 1 + fi +} + +# If the script is being sourced, do not execute the tests +if [[ "${BASH_SOURCE[0]}" == "${0}" ]]; then + run_all_tests fi diff --git a/tests/functional/multi_bit/vcd_harness.cpp b/tests/functional/multi_bit/vcd_harness.cc similarity index 72% rename from tests/functional/multi_bit/vcd_harness.cpp rename to tests/functional/multi_bit/vcd_harness.cc index bb8cca6fc8d..8c7e0ed4c96 100644 --- a/tests/functional/multi_bit/vcd_harness.cpp +++ b/tests/functional/multi_bit/vcd_harness.cc @@ -3,9 +3,6 @@ #include #include -#include - -#include "my_module_cxxrtl.cc" #include "my_module_functional_cxx.cc" struct DumpHeader { @@ -38,13 +35,12 @@ struct Dump { int main(int argc, char **argv) { - if (argc != 3) { - std::cerr << "Usage: " << argv[0] << " \n"; + if (argc != 2) { + std::cerr << "Usage: " << argv[0] << " \n"; return 1; } const std::string functional_vcd_filename = argv[1]; - const std::string cxxrtl_vcd_filename = argv[2]; constexpr int steps = 10; constexpr int number_timescale = 1; @@ -57,6 +53,7 @@ int main(int argc, char **argv) std::ofstream vcd_file(functional_vcd_filename); vcd_file << "$timescale " << number_timescale << " " << units_timescale << " $end\n"; + vcd_file << "$scope module my_module $end\n"; { DumpHeader d(vcd_file); inputs.dump(d); @@ -64,24 +61,6 @@ int main(int argc, char **argv) state.dump(d); } vcd_file << "$enddefinitions $end\n$dumpvars\n"; - - cxxrtl_design::p_my__module top; - - cxxrtl::debug_items all_debug_items; - cxxrtl::debug_scope debug_scope; - top.debug_info(&all_debug_items, nullptr, ""); - - cxxrtl::vcd_writer vcd; - vcd.timescale(number_timescale, units_timescale); - vcd.add_without_memories(all_debug_items); - - std::ofstream waves(cxxrtl_vcd_filename); - - top.p_a.set<8>(false); - top.p_b.set<8>(false); - top.step(); - - vcd.sample(0); vcd_file << "#0\n"; inputs.a = $const<8>(false); inputs.b = $const<8>(false); @@ -101,19 +80,10 @@ int main(int argc, char **argv) const bool a_value = dist(gen); const bool b_value = dist(gen); - // cxxrtl - top.p_a.set(a_value); - top.p_b.set(b_value); - top.step(); - vcd.sample(step + 1); - - waves << vcd.buffer; - vcd.buffer.clear(); - // Functional backend cxx vcd_file << "#" << (step + 1) << "\n"; - inputs.a = $const<8>(a_value); - inputs.b = $const<8>(b_value); + inputs.a = $const<1>(a_value); + inputs.b = $const<1>(b_value); my_module(inputs, outputs, state, next_state); { @@ -127,7 +97,6 @@ int main(int argc, char **argv) } vcd_file.close(); - waves.close(); return 0; } From ec6c48b75d3cf57234b6ac62cf93a5c4fbaa5e71 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Tue, 28 May 2024 12:42:59 +0200 Subject: [PATCH 28/51] Multi bit testing infrastructure works --- tests/functional/multi_bit/vcd_harness.cc | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/tests/functional/multi_bit/vcd_harness.cc b/tests/functional/multi_bit/vcd_harness.cc index 8c7e0ed4c96..901e8de1f78 100644 --- a/tests/functional/multi_bit/vcd_harness.cc +++ b/tests/functional/multi_bit/vcd_harness.cc @@ -2,6 +2,7 @@ #include #include #include +#include #include "my_module_functional_cxx.cc" @@ -74,16 +75,16 @@ int main(int argc, char **argv) std::random_device rd; std::mt19937 gen(rd()); - std::bernoulli_distribution dist(0.5); + std::uniform_int_distribution dist(0, 255); for (int step = 0; step < steps; ++step) { - const bool a_value = dist(gen); - const bool b_value = dist(gen); + const uint8_t a_value = dist(gen); + const uint8_t b_value = dist(gen); // Functional backend cxx vcd_file << "#" << (step + 1) << "\n"; - inputs.a = $const<1>(a_value); - inputs.b = $const<1>(b_value); + inputs.a = $const<8>(a_value); + inputs.b = $const<8>(b_value); my_module(inputs, outputs, state, next_state); { From f64c19bcd22eb7a3d9f4f76182a49b760afdb936 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Tue, 28 May 2024 12:54:46 +0200 Subject: [PATCH 29/51] Change permissions of verilog files --- tests/functional/single_bit/verilog/my_module_div.v | 0 tests/functional/single_bit/verilog/my_module_eqx.v | 0 tests/functional/single_bit/verilog/my_module_ge.v | 0 tests/functional/single_bit/verilog/my_module_gt.v | 0 tests/functional/single_bit/verilog/my_module_le.v | 0 tests/functional/single_bit/verilog/my_module_logic_and.v | 0 tests/functional/single_bit/verilog/my_module_logic_or.v | 0 tests/functional/single_bit/verilog/my_module_lt.v | 0 tests/functional/single_bit/verilog/my_module_mod.v | 0 tests/functional/single_bit/verilog/my_module_mul.v | 0 tests/functional/single_bit/verilog/my_module_ne.v | 0 tests/functional/single_bit/verilog/my_module_nex.v | 0 tests/functional/single_bit/verilog/my_module_or.v | 0 tests/functional/single_bit/verilog/my_module_pow.v | 0 tests/functional/single_bit/verilog/my_module_shl.v | 0 tests/functional/single_bit/verilog/my_module_shr.v | 0 tests/functional/single_bit/verilog/my_module_sshl.v | 0 tests/functional/single_bit/verilog/my_module_sshr.v | 0 tests/functional/single_bit/verilog/my_module_sub.v | 0 tests/functional/single_bit/verilog/my_module_xnor.v | 0 tests/functional/single_bit/verilog/my_module_xor.v | 0 21 files changed, 0 insertions(+), 0 deletions(-) mode change 100755 => 100644 tests/functional/single_bit/verilog/my_module_div.v mode change 100755 => 100644 tests/functional/single_bit/verilog/my_module_eqx.v mode change 100755 => 100644 tests/functional/single_bit/verilog/my_module_ge.v mode change 100755 => 100644 tests/functional/single_bit/verilog/my_module_gt.v mode change 100755 => 100644 tests/functional/single_bit/verilog/my_module_le.v mode change 100755 => 100644 tests/functional/single_bit/verilog/my_module_logic_and.v mode change 100755 => 100644 tests/functional/single_bit/verilog/my_module_logic_or.v mode change 100755 => 100644 tests/functional/single_bit/verilog/my_module_lt.v mode change 100755 => 100644 tests/functional/single_bit/verilog/my_module_mod.v mode change 100755 => 100644 tests/functional/single_bit/verilog/my_module_mul.v mode change 100755 => 100644 tests/functional/single_bit/verilog/my_module_ne.v mode change 100755 => 100644 tests/functional/single_bit/verilog/my_module_nex.v mode change 100755 => 100644 tests/functional/single_bit/verilog/my_module_or.v mode change 100755 => 100644 tests/functional/single_bit/verilog/my_module_pow.v mode change 100755 => 100644 tests/functional/single_bit/verilog/my_module_shl.v mode change 100755 => 100644 tests/functional/single_bit/verilog/my_module_shr.v mode change 100755 => 100644 tests/functional/single_bit/verilog/my_module_sshl.v mode change 100755 => 100644 tests/functional/single_bit/verilog/my_module_sshr.v mode change 100755 => 100644 tests/functional/single_bit/verilog/my_module_sub.v mode change 100755 => 100644 tests/functional/single_bit/verilog/my_module_xnor.v mode change 100755 => 100644 tests/functional/single_bit/verilog/my_module_xor.v diff --git a/tests/functional/single_bit/verilog/my_module_div.v b/tests/functional/single_bit/verilog/my_module_div.v old mode 100755 new mode 100644 diff --git a/tests/functional/single_bit/verilog/my_module_eqx.v b/tests/functional/single_bit/verilog/my_module_eqx.v old mode 100755 new mode 100644 diff --git a/tests/functional/single_bit/verilog/my_module_ge.v b/tests/functional/single_bit/verilog/my_module_ge.v old mode 100755 new mode 100644 diff --git a/tests/functional/single_bit/verilog/my_module_gt.v b/tests/functional/single_bit/verilog/my_module_gt.v old mode 100755 new mode 100644 diff --git a/tests/functional/single_bit/verilog/my_module_le.v b/tests/functional/single_bit/verilog/my_module_le.v old mode 100755 new mode 100644 diff --git a/tests/functional/single_bit/verilog/my_module_logic_and.v b/tests/functional/single_bit/verilog/my_module_logic_and.v old mode 100755 new mode 100644 diff --git a/tests/functional/single_bit/verilog/my_module_logic_or.v b/tests/functional/single_bit/verilog/my_module_logic_or.v old mode 100755 new mode 100644 diff --git a/tests/functional/single_bit/verilog/my_module_lt.v b/tests/functional/single_bit/verilog/my_module_lt.v old mode 100755 new mode 100644 diff --git a/tests/functional/single_bit/verilog/my_module_mod.v b/tests/functional/single_bit/verilog/my_module_mod.v old mode 100755 new mode 100644 diff --git a/tests/functional/single_bit/verilog/my_module_mul.v b/tests/functional/single_bit/verilog/my_module_mul.v old mode 100755 new mode 100644 diff --git a/tests/functional/single_bit/verilog/my_module_ne.v b/tests/functional/single_bit/verilog/my_module_ne.v old mode 100755 new mode 100644 diff --git a/tests/functional/single_bit/verilog/my_module_nex.v b/tests/functional/single_bit/verilog/my_module_nex.v old mode 100755 new mode 100644 diff --git a/tests/functional/single_bit/verilog/my_module_or.v b/tests/functional/single_bit/verilog/my_module_or.v old mode 100755 new mode 100644 diff --git a/tests/functional/single_bit/verilog/my_module_pow.v b/tests/functional/single_bit/verilog/my_module_pow.v old mode 100755 new mode 100644 diff --git a/tests/functional/single_bit/verilog/my_module_shl.v b/tests/functional/single_bit/verilog/my_module_shl.v old mode 100755 new mode 100644 diff --git a/tests/functional/single_bit/verilog/my_module_shr.v b/tests/functional/single_bit/verilog/my_module_shr.v old mode 100755 new mode 100644 diff --git a/tests/functional/single_bit/verilog/my_module_sshl.v b/tests/functional/single_bit/verilog/my_module_sshl.v old mode 100755 new mode 100644 diff --git a/tests/functional/single_bit/verilog/my_module_sshr.v b/tests/functional/single_bit/verilog/my_module_sshr.v old mode 100755 new mode 100644 diff --git a/tests/functional/single_bit/verilog/my_module_sub.v b/tests/functional/single_bit/verilog/my_module_sub.v old mode 100755 new mode 100644 diff --git a/tests/functional/single_bit/verilog/my_module_xnor.v b/tests/functional/single_bit/verilog/my_module_xnor.v old mode 100755 new mode 100644 diff --git a/tests/functional/single_bit/verilog/my_module_xor.v b/tests/functional/single_bit/verilog/my_module_xor.v old mode 100755 new mode 100644 From c0b8e6c90c287c6b22beb8ca9004411a43b8963a Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Tue, 28 May 2024 12:55:44 +0200 Subject: [PATCH 30/51] Rename verilog files for consistency --- tests/functional/single_bit/verilog/{add.v => my_module_add.v} | 0 tests/functional/single_bit/verilog/{and.v => my_module_and.v} | 0 2 files changed, 0 insertions(+), 0 deletions(-) rename tests/functional/single_bit/verilog/{add.v => my_module_add.v} (100%) rename tests/functional/single_bit/verilog/{and.v => my_module_and.v} (100%) diff --git a/tests/functional/single_bit/verilog/add.v b/tests/functional/single_bit/verilog/my_module_add.v similarity index 100% rename from tests/functional/single_bit/verilog/add.v rename to tests/functional/single_bit/verilog/my_module_add.v diff --git a/tests/functional/single_bit/verilog/and.v b/tests/functional/single_bit/verilog/my_module_and.v similarity index 100% rename from tests/functional/single_bit/verilog/and.v rename to tests/functional/single_bit/verilog/my_module_and.v From 37d7175252ac6f3e908fe7c45d51e24d49b3ce5b Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Tue, 28 May 2024 12:56:08 +0200 Subject: [PATCH 31/51] Rename verilog files for consistency --- tests/functional/multi_bit/verilog/{and.v => my_module_and.v} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename tests/functional/multi_bit/verilog/{and.v => my_module_and.v} (100%) diff --git a/tests/functional/multi_bit/verilog/and.v b/tests/functional/multi_bit/verilog/my_module_and.v similarity index 100% rename from tests/functional/multi_bit/verilog/and.v rename to tests/functional/multi_bit/verilog/my_module_and.v From 94171a46c66ee224dbc3f15d87305c280ff315c1 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Tue, 28 May 2024 13:22:32 +0200 Subject: [PATCH 32/51] Add some 8 bit tests for functional C++ backend --- tests/functional/multi_bit/verilog/my_module_add.v | 9 +++++++++ tests/functional/multi_bit/verilog/my_module_div.v | 9 +++++++++ tests/functional/multi_bit/verilog/my_module_logic_and.v | 9 +++++++++ tests/functional/multi_bit/verilog/my_module_logic_or.v | 9 +++++++++ tests/functional/multi_bit/verilog/my_module_mod.v | 9 +++++++++ tests/functional/multi_bit/verilog/my_module_mul.v | 9 +++++++++ tests/functional/multi_bit/verilog/my_module_or.v | 9 +++++++++ tests/functional/multi_bit/verilog/my_module_sub.v | 9 +++++++++ tests/functional/multi_bit/verilog/my_module_xor.v | 9 +++++++++ 9 files changed, 81 insertions(+) create mode 100644 tests/functional/multi_bit/verilog/my_module_add.v create mode 100644 tests/functional/multi_bit/verilog/my_module_div.v create mode 100644 tests/functional/multi_bit/verilog/my_module_logic_and.v create mode 100644 tests/functional/multi_bit/verilog/my_module_logic_or.v create mode 100644 tests/functional/multi_bit/verilog/my_module_mod.v create mode 100644 tests/functional/multi_bit/verilog/my_module_mul.v create mode 100644 tests/functional/multi_bit/verilog/my_module_or.v create mode 100644 tests/functional/multi_bit/verilog/my_module_sub.v create mode 100644 tests/functional/multi_bit/verilog/my_module_xor.v diff --git a/tests/functional/multi_bit/verilog/my_module_add.v b/tests/functional/multi_bit/verilog/my_module_add.v new file mode 100644 index 00000000000..b9c42165a16 --- /dev/null +++ b/tests/functional/multi_bit/verilog/my_module_add.v @@ -0,0 +1,9 @@ +module my_module( + input [7:0] a, + input [7:0] b, + output [7:0] y +); + // Perform operation + assign y = a + b; + +endmodule diff --git a/tests/functional/multi_bit/verilog/my_module_div.v b/tests/functional/multi_bit/verilog/my_module_div.v new file mode 100644 index 00000000000..9d36fd3d7c3 --- /dev/null +++ b/tests/functional/multi_bit/verilog/my_module_div.v @@ -0,0 +1,9 @@ +module my_module( + input [7:0] a, + input [7:0] b, + output [7:0] y +); + // Perform operation + assign y = a / b; + +endmodule diff --git a/tests/functional/multi_bit/verilog/my_module_logic_and.v b/tests/functional/multi_bit/verilog/my_module_logic_and.v new file mode 100644 index 00000000000..3c5245c9c15 --- /dev/null +++ b/tests/functional/multi_bit/verilog/my_module_logic_and.v @@ -0,0 +1,9 @@ +module my_module( + input [7:0] a, + input [7:0] b, + output [7:0] y +); + // Perform operation + assign y = a && b; + +endmodule diff --git a/tests/functional/multi_bit/verilog/my_module_logic_or.v b/tests/functional/multi_bit/verilog/my_module_logic_or.v new file mode 100644 index 00000000000..679babd9b2c --- /dev/null +++ b/tests/functional/multi_bit/verilog/my_module_logic_or.v @@ -0,0 +1,9 @@ +module my_module( + input [7:0] a, + input [7:0] b, + output [7:0] y +); + // Perform operation + assign y = a || b; + +endmodule diff --git a/tests/functional/multi_bit/verilog/my_module_mod.v b/tests/functional/multi_bit/verilog/my_module_mod.v new file mode 100644 index 00000000000..7a0b5705c6e --- /dev/null +++ b/tests/functional/multi_bit/verilog/my_module_mod.v @@ -0,0 +1,9 @@ +module my_module( + input [7:0] a, + input [7:0] b, + output [7:0] y +); + // Perform operation + assign y = a % b; + +endmodule diff --git a/tests/functional/multi_bit/verilog/my_module_mul.v b/tests/functional/multi_bit/verilog/my_module_mul.v new file mode 100644 index 00000000000..8244f4a8ec8 --- /dev/null +++ b/tests/functional/multi_bit/verilog/my_module_mul.v @@ -0,0 +1,9 @@ +module my_module( + input [7:0] a, + input [7:0] b, + output [7:0] y +); + // Perform operation + assign y = a * b; + +endmodule diff --git a/tests/functional/multi_bit/verilog/my_module_or.v b/tests/functional/multi_bit/verilog/my_module_or.v new file mode 100644 index 00000000000..f8b459af70b --- /dev/null +++ b/tests/functional/multi_bit/verilog/my_module_or.v @@ -0,0 +1,9 @@ +module my_module( + input [7:0] a, + input [7:0] b, + output [7:0] y +); + // Perform operation + assign y = a | b; + +endmodule diff --git a/tests/functional/multi_bit/verilog/my_module_sub.v b/tests/functional/multi_bit/verilog/my_module_sub.v new file mode 100644 index 00000000000..0c5b52073dd --- /dev/null +++ b/tests/functional/multi_bit/verilog/my_module_sub.v @@ -0,0 +1,9 @@ +module my_module( + input [7:0] a, + input [7:0] b, + output [7:0] y +); + // Perform operation + assign y = a - b; + +endmodule diff --git a/tests/functional/multi_bit/verilog/my_module_xor.v b/tests/functional/multi_bit/verilog/my_module_xor.v new file mode 100644 index 00000000000..4d7ab43890f --- /dev/null +++ b/tests/functional/multi_bit/verilog/my_module_xor.v @@ -0,0 +1,9 @@ +module my_module( + input [7:0] a, + input [7:0] b, + output [7:0] y +); + // Perform operation + assign y = a ^ b; + +endmodule From 1ce9a9795091db09b8358413f5b99445c2f154e3 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Tue, 28 May 2024 14:56:16 +0200 Subject: [PATCH 33/51] Initial, failing implementation of div and mod cells --- backends/functional/cxx.cc | 2 ++ backends/functional/cxx_runtime/sim.h | 30 +++++++++++++++++++++++++ backends/functional/smtlib.cc | 2 ++ kernel/graphtools.h | 12 ++++++++++ tests/functional/single_bit/run-test.sh | 3 ++- 5 files changed, 48 insertions(+), 1 deletion(-) diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index a4153035dad..f0ceb5d76d4 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -190,6 +190,8 @@ class CxxComputeGraphFactory { T logical_shift_right(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($shr), y_width, {{ID(WIDTH), y_width}}), 0, std::array{a, b}); } T arithmetic_shift_right(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($asr), y_width, {{ID(WIDTH), y_width}}), 0, std::array{a, b}); } T mul(T a, T b, int width) { return graph.add(CxxFunction(ID($mul), width), 0, std::array{a, b}); } + T mod(T a, T b, int width) { return graph.add(CxxFunction(ID($mod), width), 0, std::array{a, b}); } + T div(T a, T b, int width) { return graph.add(CxxFunction(ID($div), width), 0, std::array{a, b}); } T constant(RTLIL::Const value) { return graph.add(CxxFunction(ID($$const), value.size(), {{ID(value), value}}), 0); diff --git a/backends/functional/cxx_runtime/sim.h b/backends/functional/cxx_runtime/sim.h index 0cbbe9831a1..e6e1c2f953a 100644 --- a/backends/functional/cxx_runtime/sim.h +++ b/backends/functional/cxx_runtime/sim.h @@ -379,4 +379,34 @@ Signal $mul(Signal const& a, Signal const& b) return ret; } +template +Signal $div(Signal const& a, Signal const& b) +{ + Signal quotient = $const(0); + Signal remainder = a; + Signal divisor = b; + + for(int i = n - 1; i >= 0; i--) { + if(as_int(remainder) >= (as_int(divisor) << i)) { + remainder = $sub(remainder, $shl(divisor, $const(i))); + quotient[i] = true; + } + } + return quotient; +} + +template +Signal $mod(Signal const& a, Signal const& b) +{ + Signal remainder = a; + Signal divisor = b; + + for(int i = n - 1; i >= 0; i--) { + if(as_int(remainder) >= (as_int(divisor) << i)) { + remainder = $sub(remainder, $shl(divisor, $const(i))); + } + } + return remainder; +} + #endif diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index 2811d0bea7e..30883577215 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -368,6 +368,8 @@ class SmtlibComputeGraphFactory { T logical_shift_right(T a, T b, int y_width, int b_width) { return shift("bvlshl", a, b, y_width, b_width); } T arithmetic_shift_right(T a, T b, int y_width, int b_width) { return shift("bvashr", a, b, y_width, b_width, true); } T mul(T a, T b, int width) { return node(SExpr {"bvmul", Arg(1), Arg(2)}, width, {a, b}); } + T div(T a, T b, int width) { return node(SExpr {"bvudiv", Arg(1), Arg(2)}, width, {a, b}); } + T mod(T a, T b, int width) { return node(SExpr {"bvurem", Arg(1), Arg(2)}, width, {a, b}); } T constant(RTLIL::Const value) { return node(SExpr(value), value.size(), {}); } T input(IdString name, int width) { diff --git a/kernel/graphtools.h b/kernel/graphtools.h index 1c6b927739d..907a2b1cf4a 100644 --- a/kernel/graphtools.h +++ b/kernel/graphtools.h @@ -189,6 +189,18 @@ class CellSimplifier { T a = extend(inputs.at(ID(A)), a_width, width, is_signed); T b = extend(inputs.at(ID(B)), b_width, width, is_signed); return extend(factory.mul(a, b, width), width, y_width, is_signed); + }else if(cellType == ID($div)){ + bool is_signed = a_signed && b_signed; + int width = max(a_width, b_width); + T a = extend(inputs.at(ID(A)), a_width, width, is_signed); + T b = extend(inputs.at(ID(B)), b_width, width, is_signed); + return extend(factory.div(a, b, width), width, y_width, is_signed); + }else if(cellType == ID($mod)){ + bool is_signed = a_signed && b_signed; + int width = max(a_width, b_width); + T a = extend(inputs.at(ID(A)), a_width, width, is_signed); + T b = extend(inputs.at(ID(B)), b_width, width, is_signed); + return extend(factory.mod(a, b, width), width, y_width, is_signed); }else{ log_error("unhandled cell in CellSimplifier %s\n", cellType.c_str()); } diff --git a/tests/functional/single_bit/run-test.sh b/tests/functional/single_bit/run-test.sh index d71a2c90fb8..7fe74cc47d4 100755 --- a/tests/functional/single_bit/run-test.sh +++ b/tests/functional/single_bit/run-test.sh @@ -24,7 +24,8 @@ run_test() { if ./vcd_harness ${base_name}_functional_cxx.vcd; then # Run yosys to process each Verilog file - if ${BASE_PATH}yosys -p "read_verilog $verilog_file; sim -r ${base_name}_functional_cxx.vcd -scope my_module -timescale 1us -sim-cmp"; then + if ${BASE_PATH}yosys -p "read_verilog $verilog_file; sim -r ${base_name}_functional_cxx.vcd -scope my_module -vcd ${base_name}_yosys_sim.vcd -timescale 1us -sim-cmp"; then + # ${BASE_PATH}yosys -p "read_verilog $verilog_file; sim -vcd ${base_name}_yosys_sim.vcd -r ${base_name}_functional_cxx.vcd -scope my_module -timescale 1us" echo "Yosys sim $verilog_file successfully." else echo "Yosys simulation of $verilog_file failed. There is a discrepancy with functional cxx" From cdf4b1ffc91abd73b22ff539fcec786b8927ebca Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Tue, 28 May 2024 14:59:49 +0200 Subject: [PATCH 34/51] Added Functional backend C++ tests to make test --- Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Makefile b/Makefile index a4c8680b8c8..544f91128ff 100644 --- a/Makefile +++ b/Makefile @@ -849,6 +849,8 @@ endif +cd tests/xprop && bash run-test.sh $(SEEDOPT) +cd tests/fmt && bash run-test.sh +cd tests/cxxrtl && bash run-test.sh + +cd tests/functional/single_bit && bash run-test.sh + +cd tests/functional/multi_bit && bash run-test.sh @echo "" @echo " Passed \"make test\"." @echo "" From b8dc9c546434cd727c771e1f93be14e8909209a3 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Tue, 28 May 2024 19:36:03 +0200 Subject: [PATCH 35/51] Create vcd file from sim if -sim-cmp fails --- tests/functional/single_bit/run-test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/functional/single_bit/run-test.sh b/tests/functional/single_bit/run-test.sh index 7fe74cc47d4..685dc7a4691 100755 --- a/tests/functional/single_bit/run-test.sh +++ b/tests/functional/single_bit/run-test.sh @@ -25,9 +25,9 @@ run_test() { # Run yosys to process each Verilog file if ${BASE_PATH}yosys -p "read_verilog $verilog_file; sim -r ${base_name}_functional_cxx.vcd -scope my_module -vcd ${base_name}_yosys_sim.vcd -timescale 1us -sim-cmp"; then - # ${BASE_PATH}yosys -p "read_verilog $verilog_file; sim -vcd ${base_name}_yosys_sim.vcd -r ${base_name}_functional_cxx.vcd -scope my_module -timescale 1us" echo "Yosys sim $verilog_file successfully." else + ${BASE_PATH}yosys -p "read_verilog $verilog_file; sim -vcd ${base_name}_yosys_sim.vcd -r ${base_name}_functional_cxx.vcd -scope my_module -timescale 1us" echo "Yosys simulation of $verilog_file failed. There is a discrepancy with functional cxx" failing_files["$verilog_file"]="Yosys sim failure" fi From 54536afb158d661053e4b1845b0e978d6732d106 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Tue, 28 May 2024 23:15:03 +0200 Subject: [PATCH 36/51] Remove coverage --- dsn | 204 + flake.nix | 2 +- .../vcd_harness.info => sim.vcd | 0 test_and.v | 108 + tests/functional/coverage_report/amber.png | Bin 141 -> 0 bytes tests/functional/coverage_report/emerald.png | Bin 141 -> 0 bytes .../functional/and_cxxrtl.cc.func-sort-c.html | 100 - .../functional/and_cxxrtl.cc.func.html | 100 - .../functional/and_cxxrtl.cc.gcov.html | 161 - .../and_functional_cxx.cc.func-sort-c.html | 84 - .../and_functional_cxx.cc.func.html | 84 - .../and_functional_cxx.cc.gcov.html | 108 - .../functional/index-sort-f.html | 113 - .../functional/index-sort-l.html | 113 - .../coverage_report/functional/index.html | 113 - .../vcd_harness.cpp.func-sort-c.html | 84 - .../functional/vcd_harness.cpp.func.html | 84 - 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"/nix/store/7f3kcbzgv0m5nk1z24lg38127yg4r90k-iverilog-12.0/lib/ivl/vhdl_sys.vpi"; +:vpi_module "/nix/store/7f3kcbzgv0m5nk1z24lg38127yg4r90k-iverilog-12.0/lib/ivl/vhdl_textio.vpi"; +:vpi_module "/nix/store/7f3kcbzgv0m5nk1z24lg38127yg4r90k-iverilog-12.0/lib/ivl/v2005_math.vpi"; +:vpi_module "/nix/store/7f3kcbzgv0m5nk1z24lg38127yg4r90k-iverilog-12.0/lib/ivl/va_math.vpi"; +S_0x703640 .scope module, "testbench" "testbench" 2 4; + .timescale 0 0; +v0x74c7f0_0 .var/i "file", 31 0; +v0x74c8d0_0 .var "filename", 1023 0; +v0x74c9b0_0 .var/i "i", 31 0; +v0x74ca70_0 .var "sig_my_module_a", 0 0; +v0x74cb60_0 .var "sig_my_module_b", 0 0; +v0x74cc50_0 .net "sig_my_module_y", 0 0, L_0x74d160; 1 drivers +v0x74cd20_0 .var "xorshift128_t", 31 0; +v0x74cde0_0 .var "xorshift128_w", 31 0; +v0x74cec0_0 .var "xorshift128_x", 31 0; +v0x74cfa0_0 .var "xorshift128_y", 31 0; +v0x74d080_0 .var "xorshift128_z", 31 0; +S_0x6efef0 .scope task, "my_module_print_header" "my_module_print_header" 2 69, 2 69 0, S_0x703640; + .timescale 0 0; +TD_testbench.my_module_print_header ; + %vpi_call 2 71 "$fdisplay", v0x74c7f0_0, "#OUT#" {0 0 0}; + %vpi_call 2 72 "$fdisplay", v0x74c7f0_0, "#OUT# A sig_my_module_a" {0 0 0}; + %vpi_call 2 73 "$fdisplay", v0x74c7f0_0, "#OUT# B sig_my_module_b" {0 0 0}; + %vpi_call 2 74 "$fdisplay", v0x74c7f0_0, "#OUT# C sig_my_module_y" {0 0 0}; + %vpi_call 2 75 "$fdisplay", v0x74c7f0_0, "#OUT#" {0 0 0}; + %vpi_call 2 76 "$fdisplay", v0x74c7f0_0, "#OUT# AB # C" {0 0 0}; + %end; +S_0x701c90 .scope task, "my_module_print_status" "my_module_print_status" 2 63, 2 63 0, S_0x703640; + .timescale 0 0; +TD_testbench.my_module_print_status ; + %load/vec4 v0x74ca70_0; + %load/vec4 v0x74cb60_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x74cc50_0; + %vpi_call 2 65 "$fdisplay", v0x74c7f0_0, "#OUT# %b %b %b %t %d", S<1,vec4,u2>, 1'bx, S<0,vec4,u1>, $time, v0x74c9b0_0 {2 0 0}; + %end; +S_0x701e70 .scope task, "my_module_reset" "my_module_reset" 2 36, 2 36 0, S_0x703640; + .timescale 0 0; +TD_testbench.my_module_reset ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x74ca70_0, 2; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x74cb60_0, 4; + %delay 100, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x74ca70_0, 2; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x74cb60_0, 4; + %delay 100, 0; + %delay 0, 0; + %end; +S_0x733630 .scope task, "my_module_test" "my_module_test" 2 80, 2 80 0, S_0x703640; + .timescale 0 0; +TD_testbench.my_module_test ; + %vpi_call 2 82 "$fdisplay", v0x74c7f0_0, "#OUT#\012#OUT# ==== my_module ====" {0 0 0}; + %fork TD_testbench.my_module_reset, S_0x701e70; + %join; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x74c9b0_0, 0, 32; +T_3.0 ; + %load/vec4 v0x74c9b0_0; + %cmpi/s 1000, 0, 32; + %jmp/0xz T_3.1, 5; + %load/vec4 v0x74c9b0_0; + %pushi/vec4 20, 0, 32; + %mod/s; + %cmpi/e 0, 0, 32; + %jmp/0xz T_3.2, 4; + %fork TD_testbench.my_module_print_header, S_0x6efef0; + %join; +T_3.2 ; + %delay 100, 0; + %fork TD_testbench.my_module_update_data, S_0x71fde0; + %join; + %delay 100, 0; + %fork TD_testbench.my_module_update_clock, S_0x733810; + %join; + %delay 100, 0; + %fork TD_testbench.my_module_print_status, S_0x701c90; + %join; + %load/vec4 v0x74c9b0_0; + %addi 1, 0, 32; + %store/vec4 v0x74c9b0_0, 0, 32; + %jmp T_3.0; +T_3.1 ; + %end; +S_0x733810 .scope task, "my_module_update_clock" "my_module_update_clock" 2 58, 2 58 0, S_0x703640; + .timescale 0 0; +TD_testbench.my_module_update_clock ; + %end; +S_0x71fde0 .scope task, "my_module_update_data" "my_module_update_data" 2 48, 2 48 0, S_0x703640; + .timescale 0 0; +TD_testbench.my_module_update_data ; + %fork TD_testbench.xorshift128, S_0x74c610; + %join; + %load/vec4 v0x74cec0_0; + %load/vec4 v0x74cfa0_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x74d080_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x74cde0_0; + %concat/vec4; draw_concat_vec4 + %pad/u 1; + %assign/vec4 v0x74ca70_0, 2; + %fork TD_testbench.xorshift128, S_0x74c610; + %join; + %load/vec4 v0x74cec0_0; + %load/vec4 v0x74cfa0_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x74d080_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x74cde0_0; + %concat/vec4; draw_concat_vec4 + %pad/u 1; + %assign/vec4 v0x74cb60_0, 4; + %delay 100, 0; + %end; +S_0x71ffc0 .scope module, "uut_my_module" "my_module" 2 30, 3 1 0, S_0x703640; + .timescale 0 0; + .port_info 0 /INPUT 1 "a"; + .port_info 1 /INPUT 1 "b"; + .port_info 2 /OUTPUT 1 "y"; +L_0x74d160 .functor AND 1, v0x74ca70_0, v0x74cb60_0, C4<1>, C4<1>; +v0x7201f0_0 .net "a", 0 0, v0x74ca70_0; 1 drivers +v0x74c430_0 .net "b", 0 0, v0x74cb60_0; 1 drivers +v0x74c4f0_0 .net "y", 0 0, L_0x74d160; alias, 1 drivers +S_0x74c610 .scope task, "xorshift128" "xorshift128" 2 17, 2 17 0, S_0x703640; + .timescale 0 0; +TD_testbench.xorshift128 ; + %load/vec4 v0x74cec0_0; + %load/vec4 v0x74cec0_0; + %ix/load 4, 11, 0; + %flag_set/imm 4, 0; + %shiftl 4; + %xor; + %store/vec4 v0x74cd20_0, 0, 32; + %load/vec4 v0x74cfa0_0; + %store/vec4 v0x74cec0_0, 0, 32; + %load/vec4 v0x74d080_0; + %store/vec4 v0x74cfa0_0, 0, 32; + %load/vec4 v0x74cde0_0; + %store/vec4 v0x74d080_0, 0, 32; + %load/vec4 v0x74cde0_0; + %load/vec4 v0x74cde0_0; + %ix/load 4, 19, 0; + %flag_set/imm 4, 0; + %shiftr 4; + %xor; + %load/vec4 v0x74cd20_0; + %xor; + %load/vec4 v0x74cd20_0; + %ix/load 4, 8, 0; + %flag_set/imm 4, 0; + %shiftr 4; + %xor; + %store/vec4 v0x74cde0_0, 0, 32; + %end; + .scope S_0x703640; +T_7 ; + %pushi/vec4 123456789, 0, 32; + %store/vec4 v0x74cec0_0, 0, 32; + %pushi/vec4 362436069, 0, 32; + %store/vec4 v0x74cfa0_0, 0, 32; + %pushi/vec4 521288629, 0, 32; + %store/vec4 v0x74d080_0, 0, 32; + %pushi/vec4 1716911459, 0, 32; + %store/vec4 v0x74cde0_0, 0, 32; + %end; + .thread T_7; + .scope S_0x703640; +T_8 ; + %vpi_func 2 94 "$value$plusargs" 32, "VCD=%s", v0x74c8d0_0 {0 0 0}; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_8.0, 4; + %vpi_call 2 95 "$dumpfile", v0x74c8d0_0 {0 0 0}; + %vpi_call 2 96 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x703640 {0 0 0}; +T_8.0 ; + %vpi_func 2 98 "$value$plusargs" 32, "OUT=%s", v0x74c8d0_0 {0 0 0}; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_8.2, 4; + %vpi_func 2 99 "$fopen" 32, v0x74c8d0_0 {0 0 0}; + %store/vec4 v0x74c7f0_0, 0, 32; + %jmp T_8.3; +T_8.2 ; + %vpi_func 2 101 "$fopen" 32, "/dev/stdout" {0 0 0}; + %store/vec4 v0x74c7f0_0, 0, 32; +T_8.3 ; + %fork TD_testbench.my_module_test, S_0x733630; + %join; + %vpi_call 2 104 "$fclose", v0x74c7f0_0 {0 0 0}; + %vpi_call 2 105 "$finish" {0 0 0}; + %end; + .thread T_8; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "test_and.v"; + "tests/functional/single_bit/verilog/my_module_and.v"; diff --git a/flake.nix b/flake.nix index 6ed167dab80..90c646aa9a6 100644 --- a/flake.nix +++ b/flake.nix @@ -66,7 +66,7 @@ defaultPackage = yosys; packages.vcdiff = vcdiff; devShell = pkgs.mkShell { - buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git gtest abc-verifier gtkwave vcdiff lcov ]; + buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git gtest abc-verifier gtkwave vcdiff lcov racket verilog ]; }; } ); diff --git a/tests/functional/coverage_report/vcd_harness.info b/sim.vcd similarity index 100% rename from tests/functional/coverage_report/vcd_harness.info rename to sim.vcd diff --git a/test_and.v b/test_and.v new file mode 100644 index 00000000000..3799f2a16c2 --- /dev/null +++ b/test_and.v @@ -0,0 +1,108 @@ +`ifndef outfile + `define outfile "/dev/stdout" +`endif +module testbench; + +integer i; +integer file; + +reg [1023:0] filename; + +reg [31:0] xorshift128_x = 123456789; +reg [31:0] xorshift128_y = 362436069; +reg [31:0] xorshift128_z = 521288629; +reg [31:0] xorshift128_w = 1716918015; // <-- seed value +reg [31:0] xorshift128_t; + +task xorshift128; +begin + xorshift128_t = xorshift128_x ^ (xorshift128_x << 11); + xorshift128_x = xorshift128_y; + xorshift128_y = xorshift128_z; + xorshift128_z = xorshift128_w; + xorshift128_w = xorshift128_w ^ (xorshift128_w >> 19) ^ xorshift128_t ^ (xorshift128_t >> 8); +end +endtask + +wire [0:0] sig_my_module_y; +reg [0:0] sig_my_module_b; +reg [0:0] sig_my_module_a; +my_module uut_my_module( + .y(sig_my_module_y), + .b(sig_my_module_b), + .a(sig_my_module_a) +); + +task my_module_reset; +begin + sig_my_module_a <= #2 0; + sig_my_module_b <= #4 0; + #100; + sig_my_module_a <= #2 ~0; + sig_my_module_b <= #4 ~0; + #100; + #0; +end +endtask + +task my_module_update_data; +begin + xorshift128; + sig_my_module_a <= #2 { xorshift128_x, xorshift128_y, xorshift128_z, xorshift128_w }; + xorshift128; + sig_my_module_b <= #4 { xorshift128_x, xorshift128_y, xorshift128_z, xorshift128_w }; + #100; +end +endtask + +task my_module_update_clock; +begin +end +endtask + +task my_module_print_status; +begin + $fdisplay(file, "#OUT# %b %b %b %t %d", { sig_my_module_a, sig_my_module_b }, { 1'bx }, { sig_my_module_y }, $time, i); +end +endtask + +task my_module_print_header; +begin + $fdisplay(file, "#OUT#"); + $fdisplay(file, "#OUT# A sig_my_module_a"); + $fdisplay(file, "#OUT# B sig_my_module_b"); + $fdisplay(file, "#OUT# C sig_my_module_y"); + $fdisplay(file, "#OUT#"); + $fdisplay(file, {"#OUT# ", "A", "B", " ", "#", " ", "C"}); +end +endtask + +task my_module_test; +begin + $fdisplay(file, "#OUT#\n#OUT# ==== my_module ===="); + my_module_reset; + for (i=0; i<1000; i=i+1) begin + if (i % 20 == 0) my_module_print_header; + #100; my_module_update_data; + #100; my_module_update_clock; + #100; my_module_print_status; + end +end +endtask + +initial begin + if ($value$plusargs("VCD=%s", filename)) begin + $dumpfile(filename); + $dumpvars(0, testbench); + end + if ($value$plusargs("OUT=%s", filename)) begin + file = $fopen(filename); + end else begin + file = $fopen(`outfile); + end + my_module_test; + $fclose(file); + $finish; +end + +endmodule diff --git a/tests/functional/coverage_report/amber.png b/tests/functional/coverage_report/amber.png deleted file mode 100644 index 2cab170d8359081983a4e343848dfe06bc490f12..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 141 zcmeAS@N?(olHy`uVBq!ia0vp^j3CU&3?x-=hn)ga>?NMQuI!iC1^G2tW}LqE04T&+ z;1OBOz`!j8!i<;h*8KqrvZOouIx;Y9?C1WI$O`1M1^9%x{(levWG?NMQuI!iC1^Jb!lvI6;R0X`wF(yt=9xVZRt1vCRixIA4P dLn>}1Cji+@42)0J?}79&c)I$ztaD0e0sy@GAL0N2 diff --git a/tests/functional/coverage_report/functional/and_cxxrtl.cc.func-sort-c.html b/tests/functional/coverage_report/functional/and_cxxrtl.cc.func-sort-c.html deleted file mode 100644 index e8c04ffebc6..00000000000 --- a/tests/functional/coverage_report/functional/and_cxxrtl.cc.func-sort-c.html +++ /dev/null @@ -1,100 +0,0 @@ - - - - - - - LCOV - vcd_harness.info - functional/and_cxxrtl.cc - functions - - - - - - - - - - - - - - -
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Current view:top level - functional - and_cxxrtl.cc (source / functions)HitTotalCoverage
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_ZN13cxxrtl_design7p_Adder10debug_evalEv0
cxxrtl_design_create0
_ZN13cxxrtl_design7p_Adder10debug_infoEPN6cxxrtl11debug_itemsEPNS1_12debug_scopesENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEOSt3mapISB_NS1_8metadataESt4lessISB_ESaISt4pairIKSB_SD_EEE3
_ZN13cxxrtl_design7p_Adder5resetEv3
_ZN13cxxrtl_design7p_AdderC2Ev3
_ZN13cxxrtl_design7p_Adder4evalEPN6cxxrtl9performerE33
_ZN13cxxrtl_design7p_Adder6commitEv33
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_ZN13cxxrtl_design7p_Adder10debug_evalEv0
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_ZN13cxxrtl_design7p_Adder4evalEPN6cxxrtl9performerE33
_ZN13cxxrtl_design7p_Adder5resetEv3
_ZN13cxxrtl_design7p_Adder6commitEv33
_ZN13cxxrtl_design7p_AdderC2Ev3
cxxrtl_design_create0
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Current view:top level - functional - and_cxxrtl.cc (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:222975.9 %
Date:1980-01-01 00:00:00Functions:5771.4 %
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-       1             : #include <cxxrtl/cxxrtl.h>
-       2             : 
-       3             : #if defined(CXXRTL_INCLUDE_CAPI_IMPL) || \
-       4             :     defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)
-       5             : #include <cxxrtl/capi/cxxrtl_capi.cc>
-       6             : #endif
-       7             : 
-       8             : #if defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)
-       9             : #include <cxxrtl/capi/cxxrtl_capi_vcd.cc>
-      10             : #endif
-      11             : 
-      12             : using namespace cxxrtl_yosys;
-      13             : 
-      14             : namespace cxxrtl_design {
-      15             : 
-      16             : // \top: 1
-      17             : // \src: verilog/and.v:1.1-9.10
-      18           3 : struct p_Adder : public module {
-      19             :         // \src: verilog/and.v:4.14-4.17
-      20             :         /*output*/ value<1> p_sum;
-      21             :         // \src: verilog/and.v:3.14-3.15
-      22             :         /*input*/ value<1> p_b;
-      23             :         // \src: verilog/and.v:2.14-2.15
-      24             :         /*input*/ value<1> p_a;
-      25             :         p_Adder(interior) {}
-      26           3 :         p_Adder() {
-      27           3 :                 reset();
-      28           3 :         };
-      29             : 
-      30             :         void reset() override;
-      31             : 
-      32             :         bool eval(performer *performer = nullptr) override;
-      33             : 
-      34             :         template<class ObserverT>
-      35             :         bool commit(ObserverT &observer) {
-      36          33 :                 bool changed = false;
-      37             :                 return changed;
-      38             :         }
-      39             : 
-      40          33 :         bool commit() override {
-      41          33 :                 observer observer;
-      42          33 :                 return commit<>(observer);
-      43             :         }
-      44             : 
-      45             :         void debug_eval();
-      46             : 
-      47             :         void debug_info(debug_items *items, debug_scopes *scopes, std::string path, metadata_map &&cell_attrs = {}) override;
-      48             : }; // struct p_Adder
-      49             : 
-      50           3 : void p_Adder::reset() {
-      51           3 : }
-      52             : 
-      53          33 : bool p_Adder::eval(performer *performer) {
-      54          33 :         bool converged = true;
-      55             :         // \src: verilog/and.v:7.17-7.22
-      56             :         // cell $add$verilog/and.v:7$1
-      57          33 :         p_sum = add_uu<1>(p_a, p_b);
-      58          33 :         return converged;
-      59             : }
-      60             : 
-      61           0 : void p_Adder::debug_eval() {
-      62           0 : }
-      63             : 
-      64             : CXXRTL_EXTREMELY_COLD
-      65           3 : void p_Adder::debug_info(debug_items *items, debug_scopes *scopes, std::string path, metadata_map &&cell_attrs) {
-      66           3 :         assert(path.empty() || path[path.size() - 1] == ' ');
-      67           3 :         if (scopes) {
-      68           0 :                 scopes->add(path.empty() ? path : path.substr(0, path.size() - 1), "Adder", metadata_map({
-      69           0 :                         { "top", UINT64_C(1) },
-      70             :                         { "src", "verilog/and.v:1.1-9.10" },
-      71           0 :                 }), std::move(cell_attrs));
-      72             :         }
-      73           3 :         if (items) {
-      74           3 :                 items->add(path, "sum", "src\000sverilog/and.v:4.14-4.17\000", p_sum, 0, debug_item::OUTPUT|debug_item::DRIVEN_COMB);
-      75           3 :                 items->add(path, "b", "src\000sverilog/and.v:3.14-3.15\000", p_b, 0, debug_item::INPUT|debug_item::UNDRIVEN);
-      76           3 :                 items->add(path, "a", "src\000sverilog/and.v:2.14-2.15\000", p_a, 0, debug_item::INPUT|debug_item::UNDRIVEN);
-      77             :         }
-      78           3 : }
-      79             : 
-      80             : } // namespace cxxrtl_design
-      81             : 
-      82             : extern "C"
-      83           0 : cxxrtl_toplevel cxxrtl_design_create() {
-      84           0 :         return new _cxxrtl_toplevel { std::unique_ptr<cxxrtl_design::p_Adder>(new cxxrtl_design::p_Adder) };
-      85             : }
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_ZN12Adder_Inputs4dumpI10DumpHeaderEEvRT_3
_Z5AdderRK12Adder_InputsR13Adder_OutputsRK11Adder_StateRS4_30
_ZN12Adder_Inputs4dumpI4DumpEEvRT_33
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_ZN12Adder_Inputs4dumpI10DumpHeaderEEvRT_3
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-       1             : #include "sim.h"
-       2             : struct Adder_Inputs {
-       3             :         Signal<1> b;
-       4             :         Signal<1> a;
-       5             : 
-       6          36 :         template <typename T> void dump(T &out) {
-       7          36 :                 out("b", b);
-       8          36 :                 out("a", a);
-       9          36 :         }
-      10             : };
-      11             : 
-      12             : struct Adder_Outputs {
-      13             :         Signal<1> sum;
-      14             : 
-      15          36 :         template <typename T> void dump(T &out) {
-      16          36 :                 out("sum", sum);
-      17          36 :         }
-      18             : };
-      19             : 
-      20             : struct Adder_State {
-      21             : 
-      22             :         template <typename T> void dump(T &out) {
-      23             :         }
-      24             : };
-      25             : 
-      26          30 : void Adder(Adder_Inputs const &input, Adder_Outputs &output, Adder_State const &current_state, Adder_State &next_state)
-      27             : {
-      28          30 :         Signal<1> b = input.b;
-      29          30 :         Signal<1> a = input.a;
-      30          30 :         Signal<1> $add$verilog_and_v_7$1$_Y = $add(a, b); //
-      31          30 :         output.sum = $add$verilog_and_v_7$1$_Y;
-      32          30 : }
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Test:vcd_harness.infoLines:10511293.8 %
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Current view:top level - functional - vcd_harness.cpp (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:7070100.0 %
Date:1980-01-01 00:00:00Functions:33100.0 %
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main3
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Current view:top level - functional - vcd_harness.cpp (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:7070100.0 %
Date:1980-01-01 00:00:00Functions:33100.0 %
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main3
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Current view:top level - functional - vcd_harness.cpp (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:7070100.0 %
Date:1980-01-01 00:00:00Functions:33100.0 %
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          Line data    Source code
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-       1             : #include <cstdio>
-       2             : #include <iostream>
-       3             : #include <fstream>
-       4             : #include <random>
-       5             : 
-       6             : #include <cxxrtl/cxxrtl_vcd.h>
-       7             : 
-       8             : #include "and_cxxrtl.cc"
-       9             : #include "and_functional_cxx.cc"
-      10             : 
-      11             : struct DumpHeader {
-      12             :     std::ofstream &ofs;
-      13           3 :     DumpHeader(std::ofstream &ofs) : ofs(ofs) {}
-      14             :     template <size_t n>
-      15           9 :     void operator()(const char *name, Signal<n> value) {
-      16           9 :         ofs << "$var wire " << n << " " << name[0] << " " << name << " $end\n";
-      17           9 :     }
-      18             : };
-      19             : 
-      20             : struct Dump {
-      21             :     std::ofstream &ofs;
-      22          33 :     Dump(std::ofstream &ofs) : ofs(ofs) {}
-      23             :     template <size_t n>
-      24          99 :     void operator()(const char *name, Signal<n> value) {
-      25             :         // Bit
-      26             :         if (n == 1) {
-      27         156 :             ofs << (value[0] ? '1' : '0');
-      28          99 :             ofs << name[0] << "\n";
-      29             :             return;
-      30             :         }
-      31             :         // vector (multi-bit) signals
-      32             :         ofs << "b";
-      33             :         for (size_t i = n; i-- > 0;)
-      34             :             ofs << (value[i] ? '1' : '0');
-      35             :         ofs << " " << name[0] << "\n";
-      36             :     }
-      37             : };
-      38             : 
-      39           3 : int main(int argc, char **argv)
-      40             : {
-      41           3 :     constexpr int steps = 10;
-      42           3 :     constexpr int number_timescale = 1;
-      43           3 :     const std::string units_timescale = "us";
-      44           3 :     Adder_Inputs inputs;
-      45           3 :     Adder_Outputs outputs;
-      46           3 :     Adder_State state;
-      47           3 :     Adder_State next_state;
-      48             : 
-      49           3 :     std::ofstream vcd_file("functional_cxx.vcd");
-      50             : 
-      51           3 :     vcd_file << "$timescale " << number_timescale << " " << units_timescale << " $end\n"; //$scope module logic $end\n";
-      52           3 :     {
-      53           3 :         DumpHeader d(vcd_file);
-      54           3 :         inputs.dump(d);
-      55           3 :         outputs.dump(d);
-      56             :         // vcd_file << "$scope module state $end\n";
-      57           3 :         state.dump(d);
-      58             :     }
-      59           3 :     vcd_file << "$enddefinitions $end\n$dumpvars\n";
-      60             : 
-      61           3 :     cxxrtl_design::p_Adder top;
-      62             : 
-      63             :     // debug_items maps the hierarchical names of signals and memories in the design
-      64             :     // to a cxxrtl_object (a value, a wire, or a memory)
-      65           3 :     cxxrtl::debug_items all_debug_items;
-      66           3 :     cxxrtl::debug_scope debug_scope;
-      67             :     // Load the debug items of the top down the whole design hierarchy
-      68           6 :     top.debug_info(&all_debug_items, nullptr, "");
-      69             : 
-      70             :     // vcd_writer is the CXXRTL object that's responsible for creating a string with
-      71             :     // the VCD file contents.
-      72           3 :     cxxrtl::vcd_writer vcd;
-      73           3 :     vcd.timescale(number_timescale, units_timescale);
-      74             : 
-      75             :     // Here we tell the vcd writer to dump all the signals of the design, except for the
-      76             :     // memories, to the VCD file.
-      77             :     //
-      78             :     // It's not necessary to load all debug objects to the VCD. There is, for example,
-      79             :     // a  vcd.add(<debug items>, <filter>)) method which allows creating your custom filter to decide
-      80             :     // what to add and what not.
-      81           3 :     vcd.add_without_memories(all_debug_items);
-      82             : 
-      83           3 :     std::ofstream waves("cxxrtl.vcd");
-      84             : 
-      85           3 :     top.p_a.set<bool>(false);
-      86           3 :     top.p_b.set<bool>(false);
-      87           3 :     top.step();
-      88             : 
-      89             :     // We need to manually tell the VCD writer when to sample and write out the traced items.
-      90             :     // This is only a slight inconvenience and allows for complete flexibility.
-      91             :     // E.g. you could only start waveform tracing when an internal signal has reached some specific
-      92             :     // value etc.
-      93           3 :     vcd.sample(0);
-      94           3 :     vcd_file << "#0\n";
-      95           3 :     inputs.a = $const<1>(false);
-      96           3 :     inputs.b = $const<1>(false);
-      97           3 :     {
-      98           3 :         Dump d(vcd_file);
-      99           3 :         inputs.dump(d);
-     100           3 :         outputs.dump(d);
-     101           3 :         state.dump(d);
-     102             :     }
-     103             : 
-     104             :     // Initialize random number generator
-     105           3 :     std::random_device rd;
-     106           3 :     std::mt19937 gen(rd());
-     107           3 :     std::bernoulli_distribution dist(0.5); // 50% chance for true or false
-     108             :     
-     109          33 :     for (int step = 0; step < steps; ++step) {
-     110          30 :       const bool a_value = dist(gen);
-     111          30 :       const bool b_value = dist(gen);
-     112             : 
-     113             :         // cxxrtl
-     114          30 :         top.p_a.set<bool>(a_value);
-     115          30 :         top.p_b.set<bool>(b_value);
-     116          30 :         top.step();
-     117          30 :         vcd.sample(step + 1);
-     118             : 
-     119          30 :         waves << vcd.buffer;
-     120          30 :         vcd.buffer.clear();
-     121             : 
-     122             :         // Functional backend cxx
-     123          30 :         vcd_file << "#" << (step + 1) << "\n";
-     124          30 :         inputs.a = $const<1>(a_value);
-     125          30 :         inputs.b = $const<1>(b_value);
-     126          30 :         Adder(inputs, outputs, state, next_state);
-     127          30 :         {
-     128          30 :             Dump d(vcd_file);
-     129          30 :             inputs.dump(d);
-     130          30 :             outputs.dump(d);
-     131          30 :             state.dump(d);
-     132             :         }
-     133          30 :         state = next_state;
-     134             :     }
-     135             : 
-     136           3 :     vcd_file.close();
-     137           3 :     waves.close();
-     138             : 
-     139           3 :     return 0;
-     140           3 : }
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LCOV - code coverage report
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Current view:top level - home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl - cxxrtl.h (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:9011876.3 %
Date:1980-01-01 00:00:00Functions:7977.8 %
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Function Name Sort by function nameHit count Sort by hit count
_ZN6cxxrtl12debug_scopes3addERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEES8_OSt3mapIS6_NS_8metadataESt4lessIS6_ESaISt4pairIS7_SA_EEESH_0
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LCOV - code coverage report
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Current view:top level - home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl - cxxrtl.h (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:9011876.3 %
Date:1980-01-01 00:00:00Functions:7977.8 %
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Function Name Sort by function nameHit count Sort by hit count
_ZN6cxxrtl11debug_items3addERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEONS_10debug_itemEOSt3mapIS6_NS_8metadataESt4lessIS6_ESaISt4pairIS7_SC_EEE9
_ZN6cxxrtl11debug_items3addIJRNS_5valueILm1EEEijEEEvRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPKcSE_DpOT_9
_ZN6cxxrtl12debug_scopes3addERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEES8_OSt3mapIS6_NS_8metadataESt4lessIS6_ESaISt4pairIS7_SA_EEESH_0
_ZN6cxxrtl6module4stepEPNS_9performerE33
_ZN6cxxrtl8metadata11deserializeB5cxx11EPKc9
_ZN6cxxrtl8metadataC2ERKS0_18
_ZNK6cxxrtl5valueILm1EE3addERKS1_33
_ZNK6cxxrtl5valueILm1EE3aluILb0ELb0EEESt4pairIS1_bERKS1_33
_ZZN6cxxrtl8metadata11deserializeB5cxx11EPKcENKUlvE_clEv0
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Current view:top level - home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl - cxxrtl.h (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:9011876.3 %
Date:1980-01-01 00:00:00Functions:7977.8 %
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          Line data    Source code
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-       1             : /*
-       2             :  *  yosys -- Yosys Open SYnthesis Suite
-       3             :  *
-       4             :  *  Copyright (C) 2019-2020  whitequark <whitequark@whitequark.org>
-       5             :  *
-       6             :  *  Permission to use, copy, modify, and/or distribute this software for any
-       7             :  *  purpose with or without fee is hereby granted.
-       8             :  *
-       9             :  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-      10             :  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-      11             :  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-      12             :  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-      13             :  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-      14             :  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-      15             :  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-      16             :  *
-      17             :  */
-      18             : 
-      19             : // This file is included by the designs generated with `write_cxxrtl`. It is not used in Yosys itself.
-      20             : //
-      21             : // The CXXRTL support library implements compile time specialized arbitrary width arithmetics, as well as provides
-      22             : // composite lvalues made out of bit slices and concatenations of lvalues. This allows the `write_cxxrtl` pass
-      23             : // to perform a straightforward translation of RTLIL structures to readable C++, relying on the C++ compiler
-      24             : // to unwrap the abstraction and generate efficient code.
-      25             : 
-      26             : #ifndef CXXRTL_H
-      27             : #define CXXRTL_H
-      28             : 
-      29             : #include <cstddef>
-      30             : #include <cstdint>
-      31             : #include <cstring>
-      32             : #include <cassert>
-      33             : #include <limits>
-      34             : #include <type_traits>
-      35             : #include <tuple>
-      36             : #include <vector>
-      37             : #include <map>
-      38             : #include <algorithm>
-      39             : #include <memory>
-      40             : #include <functional>
-      41             : #include <sstream>
-      42             : #include <iostream>
-      43             : 
-      44             : // `cxxrtl::debug_item` has to inherit from `cxxrtl_object` to satisfy strict aliasing requirements.
-      45             : #include <cxxrtl/capi/cxxrtl_capi.h>
-      46             : 
-      47             : #ifndef __has_attribute
-      48             : #       define __has_attribute(x) 0
-      49             : #endif
-      50             : 
-      51             : // CXXRTL essentially uses the C++ compiler as a hygienic macro engine that feeds an instruction selector.
-      52             : // It generates a lot of specialized template functions with relatively large bodies that, when inlined
-      53             : // into the caller and (for those with loops) unrolled, often expose many new optimization opportunities.
-      54             : // Because of this, most of the CXXRTL runtime must be always inlined for best performance.
-      55             : #if __has_attribute(always_inline)
-      56             : #define CXXRTL_ALWAYS_INLINE inline __attribute__((__always_inline__))
-      57             : #else
-      58             : #define CXXRTL_ALWAYS_INLINE inline
-      59             : #endif
-      60             : // Conversely, some functions in the generated code are extremely large yet very cold, with both of these
-      61             : // properties being extreme enough to confuse C++ compilers into spending pathological amounts of time
-      62             : // on a futile (the code becomes worse) attempt to optimize the least important parts of code.
-      63             : #if __has_attribute(optnone)
-      64             : #define CXXRTL_EXTREMELY_COLD __attribute__((__optnone__))
-      65             : #elif __has_attribute(optimize)
-      66             : #define CXXRTL_EXTREMELY_COLD __attribute__((__optimize__(0)))
-      67             : #else
-      68             : #define CXXRTL_EXTREMELY_COLD
-      69             : #endif
-      70             : 
-      71             : // CXXRTL uses assert() to check for C++ contract violations (which may result in e.g. undefined behavior
-      72             : // of the simulation code itself), and CXXRTL_ASSERT to check for RTL contract violations (which may at
-      73             : // most result in undefined simulation results).
-      74             : //
-      75             : // Though by default, CXXRTL_ASSERT() expands to assert(), it may be overridden e.g. when integrating
-      76             : // the simulation into another process that should survive violating RTL contracts.
-      77             : #ifndef CXXRTL_ASSERT
-      78             : #ifndef CXXRTL_NDEBUG
-      79             : #define CXXRTL_ASSERT(x) assert(x)
-      80             : #else
-      81             : #define CXXRTL_ASSERT(x)
-      82             : #endif
-      83             : #endif
-      84             : 
-      85             : namespace cxxrtl {
-      86             : 
-      87             : // All arbitrary-width values in CXXRTL are backed by arrays of unsigned integers called chunks. The chunk size
-      88             : // is the same regardless of the value width to simplify manipulating values via FFI interfaces, e.g. driving
-      89             : // and introspecting the simulation in Python.
-      90             : //
-      91             : // It is practical to use chunk sizes between 32 bits and platform register size because when arithmetics on
-      92             : // narrower integer types is legalized by the C++ compiler, it inserts code to clear the high bits of the register.
-      93             : // However, (a) most of our operations do not change those bits in the first place because of invariants that are
-      94             : // invisible to the compiler, (b) we often operate on non-power-of-2 values and have to clear the high bits anyway.
-      95             : // Therefore, using relatively wide chunks and clearing the high bits explicitly and only when we know they may be
-      96             : // clobbered results in simpler generated code.
-      97             : typedef uint32_t chunk_t;
-      98             : typedef uint64_t wide_chunk_t;
-      99             : 
-     100             : template<typename T>
-     101             : struct chunk_traits {
-     102             :         static_assert(std::is_integral<T>::value && std::is_unsigned<T>::value,
-     103             :                       "chunk type must be an unsigned integral type");
-     104             :         using type = T;
-     105             :         static constexpr size_t bits = std::numeric_limits<T>::digits;
-     106             :         static constexpr T mask = std::numeric_limits<T>::max();
-     107             : };
-     108             : 
-     109             : template<class T>
-     110             : struct expr_base;
-     111             : 
-     112             : template<size_t Bits>
-     113             : struct value : public expr_base<value<Bits>> {
-     114             :         static constexpr size_t bits = Bits;
-     115             : 
-     116             :         using chunk = chunk_traits<chunk_t>;
-     117             :         static constexpr chunk::type msb_mask = (Bits % chunk::bits == 0) ? chunk::mask
-     118             :                 : chunk::mask >> (chunk::bits - (Bits % chunk::bits));
-     119             : 
-     120             :         static constexpr size_t chunks = (Bits + chunk::bits - 1) / chunk::bits;
-     121             :         chunk::type data[chunks] = {};
-     122             : 
-     123           3 :         value() = default;
-     124             :         template<typename... Init>
-     125             :         explicit constexpr value(Init ...init) : data{init...} {}
-     126             : 
-     127             :         value(const value<Bits> &) = default;
-     128             :         value<Bits> &operator=(const value<Bits> &) = default;
-     129             : 
-     130             :         value(value<Bits> &&) = default;
-     131             :         value<Bits> &operator=(value<Bits> &&) = default;
-     132             : 
-     133             :         // A (no-op) helper that forces the cast to value<>.
-     134             :         CXXRTL_ALWAYS_INLINE
-     135             :         const value<Bits> &val() const {
-     136             :                 return *this;
-     137             :         }
-     138             : 
-     139             :         std::string str() const {
-     140             :                 std::stringstream ss;
-     141             :                 ss << *this;
-     142             :                 return ss.str();
-     143             :         }
-     144             : 
-     145             :         // Conversion operations.
-     146             :         //
-     147             :         // These functions ensure that a conversion is never out of range, and should be always used, if at all
-     148             :         // possible, instead of direct manipulation of the `data` member. For very large types, .slice() and
-     149             :         // .concat() can be used to split them into more manageable parts.
-     150             :         template<class IntegerT, typename std::enable_if<!std::is_signed<IntegerT>::value, int>::type = 0>
-     151             :         CXXRTL_ALWAYS_INLINE
-     152             :         IntegerT get() const {
-     153             :                 static_assert(std::numeric_limits<IntegerT>::is_integer && !std::numeric_limits<IntegerT>::is_signed,
-     154             :                               "get<T>() requires T to be an unsigned integral type");
-     155             :                 static_assert(std::numeric_limits<IntegerT>::digits >= Bits,
-     156             :                               "get<T>() requires T to be at least as wide as the value is");
-     157             :                 IntegerT result = 0;
-     158             :                 for (size_t n = 0; n < chunks; n++)
-     159             :                         result |= IntegerT(data[n]) << (n * chunk::bits);
-     160             :                 return result;
-     161             :         }
-     162             : 
-     163             :         template<class IntegerT, typename std::enable_if<std::is_signed<IntegerT>::value, int>::type = 0>
-     164             :         CXXRTL_ALWAYS_INLINE
-     165             :         IntegerT get() const {
-     166             :                 auto unsigned_result = get<typename std::make_unsigned<IntegerT>::type>();
-     167             :                 IntegerT result;
-     168             :                 memcpy(&result, &unsigned_result, sizeof(IntegerT));
-     169             :                 return result;
-     170             :         }
-     171             : 
-     172             :         template<class IntegerT, typename std::enable_if<!std::is_signed<IntegerT>::value, int>::type = 0>
-     173             :         CXXRTL_ALWAYS_INLINE
-     174          30 :         void set(IntegerT value) {
-     175             :                 static_assert(std::numeric_limits<IntegerT>::is_integer && !std::numeric_limits<IntegerT>::is_signed,
-     176             :                               "set<T>() requires T to be an unsigned integral type");
-     177             :                 static_assert(std::numeric_limits<IntegerT>::digits >= Bits,
-     178             :                               "set<T>() requires the value to be at least as wide as T is");
-     179           6 :                 for (size_t n = 0; n < chunks; n++)
-     180          36 :                         data[n] = (value >> (n * chunk::bits)) & chunk::mask;
-     181             :         }
-     182             : 
-     183             :         template<class IntegerT, typename std::enable_if<std::is_signed<IntegerT>::value, int>::type = 0>
-     184             :         CXXRTL_ALWAYS_INLINE
-     185             :         void set(IntegerT value) {
-     186             :                 typename std::make_unsigned<IntegerT>::type unsigned_value;
-     187             :                 memcpy(&unsigned_value, &value, sizeof(IntegerT));
-     188             :                 set(unsigned_value);
-     189             :         }
-     190             : 
-     191             :         // Operations with compile-time parameters.
-     192             :         //
-     193             :         // These operations are used to implement slicing, concatenation, and blitting.
-     194             :         // The trunc, zext and sext operations add or remove most significant bits (i.e. on the left);
-     195             :         // the rtrunc and rzext operations add or remove least significant bits (i.e. on the right).
-     196             :         template<size_t NewBits>
-     197             :         CXXRTL_ALWAYS_INLINE
-     198             :         value<NewBits> trunc() const {
-     199             :                 static_assert(NewBits <= Bits, "trunc() may not increase width");
-     200             :                 value<NewBits> result;
-     201             :                 for (size_t n = 0; n < result.chunks; n++)
-     202             :                         result.data[n] = data[n];
-     203             :                 result.data[result.chunks - 1] &= result.msb_mask;
-     204             :                 return result;
-     205             :         }
-     206             : 
-     207             :         template<size_t NewBits>
-     208             :         CXXRTL_ALWAYS_INLINE
-     209          33 :         value<NewBits> zext() const {
-     210             :                 static_assert(NewBits >= Bits, "zext() may not decrease width");
-     211             :                 value<NewBits> result;
-     212          33 :                 for (size_t n = 0; n < chunks; n++)
-     213          33 :                         result.data[n] = data[n];
-     214             :                 return result;
-     215             :         }
-     216             : 
-     217             :         template<size_t NewBits>
-     218             :         CXXRTL_ALWAYS_INLINE
-     219             :         value<NewBits> sext() const {
-     220             :                 static_assert(NewBits >= Bits, "sext() may not decrease width");
-     221             :                 value<NewBits> result;
-     222             :                 for (size_t n = 0; n < chunks; n++)
-     223             :                         result.data[n] = data[n];
-     224             :                 if (is_neg()) {
-     225             :                         result.data[chunks - 1] |= ~msb_mask;
-     226             :                         for (size_t n = chunks; n < result.chunks; n++)
-     227             :                                 result.data[n] = chunk::mask;
-     228             :                         result.data[result.chunks - 1] &= result.msb_mask;
-     229             :                 }
-     230             :                 return result;
-     231             :         }
-     232             : 
-     233             :         template<size_t NewBits>
-     234             :         CXXRTL_ALWAYS_INLINE
-     235             :         value<NewBits> rtrunc() const {
-     236             :                 static_assert(NewBits <= Bits, "rtrunc() may not increase width");
-     237             :                 value<NewBits> result;
-     238             :                 constexpr size_t shift_chunks = (Bits - NewBits) / chunk::bits;
-     239             :                 constexpr size_t shift_bits   = (Bits - NewBits) % chunk::bits;
-     240             :                 chunk::type carry = 0;
-     241             :                 if (shift_chunks + result.chunks < chunks) {
-     242             :                         carry = (shift_bits == 0) ? 0
-     243             :                                 : data[shift_chunks + result.chunks] << (chunk::bits - shift_bits);
-     244             :                 }
-     245             :                 for (size_t n = result.chunks; n > 0; n--) {
-     246             :                         result.data[n - 1] = carry | (data[shift_chunks + n - 1] >> shift_bits);
-     247             :                         carry = (shift_bits == 0) ? 0
-     248             :                                 : data[shift_chunks + n - 1] << (chunk::bits - shift_bits);
-     249             :                 }
-     250             :                 return result;
-     251             :         }
-     252             : 
-     253             :         template<size_t NewBits>
-     254             :         CXXRTL_ALWAYS_INLINE
-     255             :         value<NewBits> rzext() const {
-     256             :                 static_assert(NewBits >= Bits, "rzext() may not decrease width");
-     257             :                 value<NewBits> result;
-     258             :                 constexpr size_t shift_chunks = (NewBits - Bits) / chunk::bits;
-     259             :                 constexpr size_t shift_bits   = (NewBits - Bits) % chunk::bits;
-     260             :                 chunk::type carry = 0;
-     261             :                 for (size_t n = 0; n < chunks; n++) {
-     262             :                         result.data[shift_chunks + n] = (data[n] << shift_bits) | carry;
-     263             :                         carry = (shift_bits == 0) ? 0
-     264             :                                 : data[n] >> (chunk::bits - shift_bits);
-     265             :                 }
-     266             :                 if (shift_chunks + chunks < result.chunks)
-     267             :                         result.data[shift_chunks + chunks] = carry;
-     268             :                 return result;
-     269             :         }
-     270             : 
-     271             :         // Bit blit operation, i.e. a partial read-modify-write.
-     272             :         template<size_t Stop, size_t Start>
-     273             :         CXXRTL_ALWAYS_INLINE
-     274             :         value<Bits> blit(const value<Stop - Start + 1> &source) const {
-     275             :                 static_assert(Stop >= Start, "blit() may not reverse bit order");
-     276             :                 constexpr chunk::type start_mask = ~(chunk::mask << (Start % chunk::bits));
-     277             :                 constexpr chunk::type stop_mask = (Stop % chunk::bits + 1 == chunk::bits) ? 0
-     278             :                         : (chunk::mask << (Stop % chunk::bits + 1));
-     279             :                 value<Bits> masked = *this;
-     280             :                 if (Start / chunk::bits == Stop / chunk::bits) {
-     281             :                         masked.data[Start / chunk::bits] &= stop_mask | start_mask;
-     282             :                 } else {
-     283             :                         masked.data[Start / chunk::bits] &= start_mask;
-     284             :                         for (size_t n = Start / chunk::bits + 1; n < Stop / chunk::bits; n++)
-     285             :                                 masked.data[n] = 0;
-     286             :                         masked.data[Stop / chunk::bits] &= stop_mask;
-     287             :                 }
-     288             :                 value<Bits> shifted = source
-     289             :                         .template rzext<Stop + 1>()
-     290             :                         .template zext<Bits>();
-     291             :                 return masked.bit_or(shifted);
-     292             :         }
-     293             : 
-     294             :         // Helpers for selecting extending or truncating operation depending on whether the result is wider or narrower
-     295             :         // than the operand. In C++17 these can be replaced with `if constexpr`.
-     296             :         template<size_t NewBits, typename = void>
-     297             :         struct zext_cast {
-     298             :                 CXXRTL_ALWAYS_INLINE
-     299          33 :                 value<NewBits> operator()(const value<Bits> &val) {
-     300          33 :                         return val.template zext<NewBits>();
-     301             :                 }
-     302             :         };
-     303             : 
-     304             :         template<size_t NewBits>
-     305             :         struct zext_cast<NewBits, typename std::enable_if<(NewBits < Bits)>::type> {
-     306             :                 CXXRTL_ALWAYS_INLINE
-     307             :                 value<NewBits> operator()(const value<Bits> &val) {
-     308             :                         return val.template trunc<NewBits>();
-     309             :                 }
-     310             :         };
-     311             : 
-     312             :         template<size_t NewBits, typename = void>
-     313             :         struct sext_cast {
-     314             :                 CXXRTL_ALWAYS_INLINE
-     315             :                 value<NewBits> operator()(const value<Bits> &val) {
-     316             :                         return val.template sext<NewBits>();
-     317             :                 }
-     318             :         };
-     319             : 
-     320             :         template<size_t NewBits>
-     321             :         struct sext_cast<NewBits, typename std::enable_if<(NewBits < Bits)>::type> {
-     322             :                 CXXRTL_ALWAYS_INLINE
-     323             :                 value<NewBits> operator()(const value<Bits> &val) {
-     324             :                         return val.template trunc<NewBits>();
-     325             :                 }
-     326             :         };
-     327             : 
-     328             :         template<size_t NewBits>
-     329             :         CXXRTL_ALWAYS_INLINE
-     330          33 :         value<NewBits> zcast() const {
-     331          33 :                 return zext_cast<NewBits>()(*this);
-     332             :         }
-     333             : 
-     334             :         template<size_t NewBits>
-     335             :         CXXRTL_ALWAYS_INLINE
-     336             :         value<NewBits> scast() const {
-     337             :                 return sext_cast<NewBits>()(*this);
-     338             :         }
-     339             : 
-     340             :         // Bit replication is far more efficient than the equivalent concatenation.
-     341             :         template<size_t Count>
-     342             :         CXXRTL_ALWAYS_INLINE
-     343             :         value<Bits * Count> repeat() const {
-     344             :                 static_assert(Bits == 1, "repeat() is implemented only for 1-bit values");
-     345             :                 return *this ? value<Bits * Count>().bit_not() : value<Bits * Count>();
-     346             :         }
-     347             : 
-     348             :         // Operations with run-time parameters (offsets, amounts, etc).
-     349             :         //
-     350             :         // These operations are used for computations.
-     351             :         bool bit(size_t offset) const {
-     352             :                 return data[offset / chunk::bits] & (1 << (offset % chunk::bits));
-     353             :         }
-     354             : 
-     355             :         void set_bit(size_t offset, bool value = true) {
-     356             :                 size_t offset_chunks = offset / chunk::bits;
-     357             :                 size_t offset_bits = offset % chunk::bits;
-     358             :                 data[offset_chunks] &= ~(1 << offset_bits);
-     359             :                 data[offset_chunks] |= value ? 1 << offset_bits : 0;
-     360             :         }
-     361             : 
-     362             :         explicit operator bool() const {
-     363             :                 return !is_zero();
-     364             :         }
-     365             : 
-     366             :         bool is_zero() const {
-     367             :                 for (size_t n = 0; n < chunks; n++)
-     368             :                         if (data[n] != 0)
-     369             :                                 return false;
-     370             :                 return true;
-     371             :         }
-     372             : 
-     373             :         bool is_neg() const {
-     374             :                 return data[chunks - 1] & (1 << ((Bits - 1) % chunk::bits));
-     375             :         }
-     376             : 
-     377             :         bool operator ==(const value<Bits> &other) const {
-     378             :                 for (size_t n = 0; n < chunks; n++)
-     379             :                         if (data[n] != other.data[n])
-     380             :                                 return false;
-     381             :                 return true;
-     382             :         }
-     383             : 
-     384             :         bool operator !=(const value<Bits> &other) const {
-     385             :                 return !(*this == other);
-     386             :         }
-     387             : 
-     388             :         value<Bits> bit_not() const {
-     389             :                 value<Bits> result;
-     390             :                 for (size_t n = 0; n < chunks; n++)
-     391             :                         result.data[n] = ~data[n];
-     392             :                 result.data[chunks - 1] &= msb_mask;
-     393             :                 return result;
-     394             :         }
-     395             : 
-     396             :         value<Bits> bit_and(const value<Bits> &other) const {
-     397             :                 value<Bits> result;
-     398             :                 for (size_t n = 0; n < chunks; n++)
-     399             :                         result.data[n] = data[n] & other.data[n];
-     400             :                 return result;
-     401             :         }
-     402             : 
-     403             :         value<Bits> bit_or(const value<Bits> &other) const {
-     404             :                 value<Bits> result;
-     405             :                 for (size_t n = 0; n < chunks; n++)
-     406             :                         result.data[n] = data[n] | other.data[n];
-     407             :                 return result;
-     408             :         }
-     409             : 
-     410             :         value<Bits> bit_xor(const value<Bits> &other) const {
-     411             :                 value<Bits> result;
-     412             :                 for (size_t n = 0; n < chunks; n++)
-     413             :                         result.data[n] = data[n] ^ other.data[n];
-     414             :                 return result;
-     415             :         }
-     416             : 
-     417             :         value<Bits> update(const value<Bits> &val, const value<Bits> &mask) const {
-     418             :                 return bit_and(mask.bit_not()).bit_or(val.bit_and(mask));
-     419             :         }
-     420             : 
-     421             :         template<size_t AmountBits>
-     422             :         value<Bits> shl(const value<AmountBits> &amount) const {
-     423             :                 // Ensure our early return is correct by prohibiting values larger than 4 Gbit.
-     424             :                 static_assert(Bits <= chunk::mask, "shl() of unreasonably large values is not supported");
-     425             :                 // Detect shifts definitely large than Bits early.
-     426             :                 for (size_t n = 1; n < amount.chunks; n++)
-     427             :                         if (amount.data[n] != 0)
-     428             :                                 return {};
-     429             :                 // Past this point we can use the least significant chunk as the shift size.
-     430             :                 size_t shift_chunks = amount.data[0] / chunk::bits;
-     431             :                 size_t shift_bits   = amount.data[0] % chunk::bits;
-     432             :                 if (shift_chunks >= chunks)
-     433             :                         return {};
-     434             :                 value<Bits> result;
-     435             :                 chunk::type carry = 0;
-     436             :                 for (size_t n = 0; n < chunks - shift_chunks; n++) {
-     437             :                         result.data[shift_chunks + n] = (data[n] << shift_bits) | carry;
-     438             :                         carry = (shift_bits == 0) ? 0
-     439             :                                 : data[n] >> (chunk::bits - shift_bits);
-     440             :                 }
-     441             :                 result.data[result.chunks - 1] &= result.msb_mask;
-     442             :                 return result;
-     443             :         }
-     444             : 
-     445             :         template<size_t AmountBits, bool Signed = false>
-     446             :         value<Bits> shr(const value<AmountBits> &amount) const {
-     447             :                 // Ensure our early return is correct by prohibiting values larger than 4 Gbit.
-     448             :                 static_assert(Bits <= chunk::mask, "shr() of unreasonably large values is not supported");
-     449             :                 // Detect shifts definitely large than Bits early.
-     450             :                 for (size_t n = 1; n < amount.chunks; n++)
-     451             :                         if (amount.data[n] != 0)
-     452             :                                 return (Signed && is_neg()) ? value<Bits>().bit_not() : value<Bits>();
-     453             :                 // Past this point we can use the least significant chunk as the shift size.
-     454             :                 size_t shift_chunks = amount.data[0] / chunk::bits;
-     455             :                 size_t shift_bits   = amount.data[0] % chunk::bits;
-     456             :                 if (shift_chunks >= chunks)
-     457             :                         return (Signed && is_neg()) ? value<Bits>().bit_not() : value<Bits>();
-     458             :                 value<Bits> result;
-     459             :                 chunk::type carry = 0;
-     460             :                 for (size_t n = 0; n < chunks - shift_chunks; n++) {
-     461             :                         result.data[chunks - shift_chunks - 1 - n] = carry | (data[chunks - 1 - n] >> shift_bits);
-     462             :                         carry = (shift_bits == 0) ? 0
-     463             :                                 : data[chunks - 1 - n] << (chunk::bits - shift_bits);
-     464             :                 }
-     465             :                 if (Signed && is_neg()) {
-     466             :                         size_t top_chunk_idx  = amount.data[0] > Bits ? 0 : (Bits - amount.data[0]) / chunk::bits;
-     467             :                         size_t top_chunk_bits = amount.data[0] > Bits ? 0 : (Bits - amount.data[0]) % chunk::bits;
-     468             :                         for (size_t n = top_chunk_idx + 1; n < chunks; n++)
-     469             :                                 result.data[n] = chunk::mask;
-     470             :                         if (amount.data[0] != 0)
-     471             :                                 result.data[top_chunk_idx] |= chunk::mask << top_chunk_bits;
-     472             :                         result.data[result.chunks - 1] &= result.msb_mask;
-     473             :                 }
-     474             :                 return result;
-     475             :         }
-     476             : 
-     477             :         template<size_t AmountBits>
-     478             :         value<Bits> sshr(const value<AmountBits> &amount) const {
-     479             :                 return shr<AmountBits, /*Signed=*/true>(amount);
-     480             :         }
-     481             : 
-     482             :         template<size_t ResultBits, size_t SelBits>
-     483             :         value<ResultBits> bmux(const value<SelBits> &sel) const {
-     484             :                 static_assert(ResultBits << SelBits == Bits, "invalid sizes used in bmux()");
-     485             :                 size_t amount = sel.data[0] * ResultBits;
-     486             :                 size_t shift_chunks = amount / chunk::bits;
-     487             :                 size_t shift_bits   = amount % chunk::bits;
-     488             :                 value<ResultBits> result;
-     489             :                 chunk::type carry = 0;
-     490             :                 if (ResultBits % chunk::bits + shift_bits > chunk::bits)
-     491             :                         carry = data[result.chunks + shift_chunks] << (chunk::bits - shift_bits);
-     492             :                 for (size_t n = 0; n < result.chunks; n++) {
-     493             :                         result.data[result.chunks - 1 - n] = carry | (data[result.chunks + shift_chunks - 1 - n] >> shift_bits);
-     494             :                         carry = (shift_bits == 0) ? 0
-     495             :                                 : data[result.chunks + shift_chunks - 1 - n] << (chunk::bits - shift_bits);
-     496             :                 }
-     497             :                 result.data[result.chunks - 1] &= result.msb_mask;
-     498             :                 return result;
-     499             :         }
-     500             : 
-     501             :         template<size_t ResultBits, size_t SelBits>
-     502             :         value<ResultBits> demux(const value<SelBits> &sel) const {
-     503             :                 static_assert(Bits << SelBits == ResultBits, "invalid sizes used in demux()");
-     504             :                 size_t amount = sel.data[0] * Bits;
-     505             :                 size_t shift_chunks = amount / chunk::bits;
-     506             :                 size_t shift_bits   = amount % chunk::bits;
-     507             :                 value<ResultBits> result;
-     508             :                 chunk::type carry = 0;
-     509             :                 for (size_t n = 0; n < chunks; n++) {
-     510             :                         result.data[shift_chunks + n] = (data[n] << shift_bits) | carry;
-     511             :                         carry = (shift_bits == 0) ? 0
-     512             :                                 : data[n] >> (chunk::bits - shift_bits);
-     513             :                 }
-     514             :                 if (Bits % chunk::bits + shift_bits > chunk::bits)
-     515             :                         result.data[shift_chunks + chunks] = carry;
-     516             :                 return result;
-     517             :         }
-     518             : 
-     519             :         size_t ctpop() const {
-     520             :                 size_t count = 0;
-     521             :                 for (size_t n = 0; n < chunks; n++) {
-     522             :                         // This loop implements the population count idiom as recognized by LLVM and GCC.
-     523             :                         for (chunk::type x = data[n]; x != 0; count++)
-     524             :                                 x = x & (x - 1);
-     525             :                 }
-     526             :                 return count;
-     527             :         }
-     528             : 
-     529             :         size_t ctlz() const {
-     530             :                 size_t count = 0;
-     531             :                 for (size_t n = 0; n < chunks; n++) {
-     532             :                         chunk::type x = data[chunks - 1 - n];
-     533             :                         // First add to `count` as if the chunk is zero
-     534             :                         constexpr size_t msb_chunk_bits = Bits % chunk::bits != 0 ? Bits % chunk::bits : chunk::bits;
-     535             :                         count += (n == 0 ? msb_chunk_bits : chunk::bits);
-     536             :                         // If the chunk isn't zero, correct the `count` value and return
-     537             :                         if (x != 0) {
-     538             :                                 for (; x != 0; count--)
-     539             :                                         x >>= 1;
-     540             :                                 break;
-     541             :                         }
-     542             :                 }
-     543             :                 return count;
-     544             :         }
-     545             : 
-     546             :         template<bool Invert, bool CarryIn>
-     547          33 :         std::pair<value<Bits>, bool /*CarryOut*/> alu(const value<Bits> &other) const {
-     548          33 :                 value<Bits> result;
-     549          33 :                 bool carry = CarryIn;
-     550          66 :                 for (size_t n = 0; n < result.chunks; n++) {
-     551          33 :                         result.data[n] = data[n] + (Invert ? ~other.data[n] : other.data[n]) + carry;
-     552             :                         if (result.chunks - 1 == n)
-     553          33 :                                 result.data[result.chunks - 1] &= result.msb_mask;
-     554          33 :                         carry = (result.data[n] <  data[n]) ||
-     555             :                                 (result.data[n] == data[n] && carry);
-     556             :                 }
-     557          33 :                 return {result, carry};
-     558             :         }
-     559             : 
-     560          33 :         value<Bits> add(const value<Bits> &other) const {
-     561          33 :                 return alu</*Invert=*/false, /*CarryIn=*/false>(other).first;
-     562             :         }
-     563             : 
-     564             :         value<Bits> sub(const value<Bits> &other) const {
-     565             :                 return alu</*Invert=*/true, /*CarryIn=*/true>(other).first;
-     566             :         }
-     567             : 
-     568             :         value<Bits> neg() const {
-     569             :                 return value<Bits>().sub(*this);
-     570             :         }
-     571             : 
-     572             :         bool ucmp(const value<Bits> &other) const {
-     573             :                 bool carry;
-     574             :                 std::tie(std::ignore, carry) = alu</*Invert=*/true, /*CarryIn=*/true>(other);
-     575             :                 return !carry; // a.ucmp(b) ≡ a u< b
-     576             :         }
-     577             : 
-     578             :         bool scmp(const value<Bits> &other) const {
-     579             :                 value<Bits> result;
-     580             :                 bool carry;
-     581             :                 std::tie(result, carry) = alu</*Invert=*/true, /*CarryIn=*/true>(other);
-     582             :                 bool overflow = (is_neg() == !other.is_neg()) && (is_neg() != result.is_neg());
-     583             :                 return result.is_neg() ^ overflow; // a.scmp(b) ≡ a s< b
-     584             :         }
-     585             : 
-     586             :         template<size_t ResultBits>
-     587             :         value<ResultBits> mul(const value<Bits> &other) const {
-     588             :                 value<ResultBits> result;
-     589             :                 wide_chunk_t wide_result[result.chunks + 1] = {};
-     590             :                 for (size_t n = 0; n < chunks; n++) {
-     591             :                         for (size_t m = 0; m < chunks && n + m < result.chunks; m++) {
-     592             :                                 wide_result[n + m] += wide_chunk_t(data[n]) * wide_chunk_t(other.data[m]);
-     593             :                                 wide_result[n + m + 1] += wide_result[n + m] >> chunk::bits;
-     594             :                                 wide_result[n + m] &= chunk::mask;
-     595             :                         }
-     596             :                 }
-     597             :                 for (size_t n = 0; n < result.chunks; n++) {
-     598             :                         result.data[n] = wide_result[n];
-     599             :                 }
-     600             :                 result.data[result.chunks - 1] &= result.msb_mask;
-     601             :                 return result;
-     602             :         }
-     603             : 
-     604             :         std::pair<value<Bits>, value<Bits>> udivmod(value<Bits> divisor) const {
-     605             :                 value<Bits> quotient;
-     606             :                 value<Bits> dividend = *this;
-     607             :                 if (dividend.ucmp(divisor))
-     608             :                         return {/*quotient=*/value<Bits>{0u}, /*remainder=*/dividend};
-     609             :                 int64_t divisor_shift = divisor.ctlz() - dividend.ctlz();
-     610             :                 assert(divisor_shift >= 0);
-     611             :                 divisor = divisor.shl(value<Bits>{(chunk::type) divisor_shift});
-     612             :                 for (size_t step = 0; step <= divisor_shift; step++) {
-     613             :                         quotient = quotient.shl(value<Bits>{1u});
-     614             :                         if (!dividend.ucmp(divisor)) {
-     615             :                                 dividend = dividend.sub(divisor);
-     616             :                                 quotient.set_bit(0, true);
-     617             :                         }
-     618             :                         divisor = divisor.shr(value<Bits>{1u});
-     619             :                 }
-     620             :                 return {quotient, /*remainder=*/dividend};
-     621             :         }
-     622             : 
-     623             :         std::pair<value<Bits>, value<Bits>> sdivmod(const value<Bits> &other) const {
-     624             :                 value<Bits + 1> quotient;
-     625             :                 value<Bits + 1> remainder;
-     626             :                 value<Bits + 1> dividend = sext<Bits + 1>();
-     627             :                 value<Bits + 1> divisor = other.template sext<Bits + 1>();
-     628             :                 if (is_neg()) dividend = dividend.neg();
-     629             :                 if (other.is_neg()) divisor = divisor.neg();
-     630             :                 std::tie(quotient, remainder) = dividend.udivmod(divisor);
-     631             :                 if (is_neg() != other.is_neg()) quotient = quotient.neg();
-     632             :                 if (is_neg()) remainder = remainder.neg();
-     633             :                 return {quotient.template trunc<Bits>(), remainder.template trunc<Bits>()};
-     634             :         }
-     635             : };
-     636             : 
-     637             : // Expression template for a slice, usable as lvalue or rvalue, and composable with other expression templates here.
-     638             : template<class T, size_t Stop, size_t Start>
-     639             : struct slice_expr : public expr_base<slice_expr<T, Stop, Start>> {
-     640             :         static_assert(Stop >= Start, "slice_expr() may not reverse bit order");
-     641             :         static_assert(Start < T::bits && Stop < T::bits, "slice_expr() must be within bounds");
-     642             :         static constexpr size_t bits = Stop - Start + 1;
-     643             : 
-     644             :         T &expr;
-     645             : 
-     646             :         slice_expr(T &expr) : expr(expr) {}
-     647             :         slice_expr(const slice_expr<T, Stop, Start> &) = delete;
-     648             : 
-     649             :         CXXRTL_ALWAYS_INLINE
-     650             :         operator value<bits>() const {
-     651             :                 return static_cast<const value<T::bits> &>(expr)
-     652             :                         .template rtrunc<T::bits - Start>()
-     653             :                         .template trunc<bits>();
-     654             :         }
-     655             : 
-     656             :         CXXRTL_ALWAYS_INLINE
-     657             :         slice_expr<T, Stop, Start> &operator=(const value<bits> &rhs) {
-     658             :                 // Generic partial assignment implemented using a read-modify-write operation on the sliced expression.
-     659             :                 expr = static_cast<const value<T::bits> &>(expr)
-     660             :                         .template blit<Stop, Start>(rhs);
-     661             :                 return *this;
-     662             :         }
-     663             : 
-     664             :         // A helper that forces the cast to value<>, which allows deduction to work.
-     665             :         CXXRTL_ALWAYS_INLINE
-     666             :         value<bits> val() const {
-     667             :                 return static_cast<const value<bits> &>(*this);
-     668             :         }
-     669             : };
-     670             : 
-     671             : // Expression template for a concatenation, usable as lvalue or rvalue, and composable with other expression templates here.
-     672             : template<class T, class U>
-     673             : struct concat_expr : public expr_base<concat_expr<T, U>> {
-     674             :         static constexpr size_t bits = T::bits + U::bits;
-     675             : 
-     676             :         T &ms_expr;
-     677             :         U &ls_expr;
-     678             : 
-     679             :         concat_expr(T &ms_expr, U &ls_expr) : ms_expr(ms_expr), ls_expr(ls_expr) {}
-     680             :         concat_expr(const concat_expr<T, U> &) = delete;
-     681             : 
-     682             :         CXXRTL_ALWAYS_INLINE
-     683             :         operator value<bits>() const {
-     684             :                 value<bits> ms_shifted = static_cast<const value<T::bits> &>(ms_expr)
-     685             :                         .template rzext<bits>();
-     686             :                 value<bits> ls_extended = static_cast<const value<U::bits> &>(ls_expr)
-     687             :                         .template zext<bits>();
-     688             :                 return ms_shifted.bit_or(ls_extended);
-     689             :         }
-     690             : 
-     691             :         CXXRTL_ALWAYS_INLINE
-     692             :         concat_expr<T, U> &operator=(const value<bits> &rhs) {
-     693             :                 ms_expr = rhs.template rtrunc<T::bits>();
-     694             :                 ls_expr = rhs.template trunc<U::bits>();
-     695             :                 return *this;
-     696             :         }
-     697             : 
-     698             :         // A helper that forces the cast to value<>, which allows deduction to work.
-     699             :         CXXRTL_ALWAYS_INLINE
-     700             :         value<bits> val() const {
-     701             :                 return static_cast<const value<bits> &>(*this);
-     702             :         }
-     703             : };
-     704             : 
-     705             : // Base class for expression templates, providing helper methods for operations that are valid on both rvalues and lvalues.
-     706             : //
-     707             : // Note that expression objects (slices and concatenations) constructed in this way should NEVER be captured because
-     708             : // they refer to temporaries that will, in general, only live until the end of the statement. For example, both of
-     709             : // these snippets perform use-after-free:
-     710             : //
-     711             : //    const auto &a = val.slice<7,0>().slice<1>();
-     712             : //    value<1> b = a;
-     713             : //
-     714             : //    auto &&c = val.slice<7,0>().slice<1>();
-     715             : //    c = value<1>{1u};
-     716             : //
-     717             : // An easy way to write code using slices and concatenations safely is to follow two simple rules:
-     718             : //   * Never explicitly name any type except `value<W>` or `const value<W> &`.
-     719             : //   * Never use a `const auto &` or `auto &&` in any such expression.
-     720             : // Then, any code that compiles will be well-defined.
-     721             : template<class T>
-     722             : struct expr_base {
-     723             :         template<size_t Stop, size_t Start = Stop>
-     724             :         CXXRTL_ALWAYS_INLINE
-     725             :         slice_expr<const T, Stop, Start> slice() const {
-     726             :                 return {*static_cast<const T *>(this)};
-     727             :         }
-     728             : 
-     729             :         template<size_t Stop, size_t Start = Stop>
-     730             :         CXXRTL_ALWAYS_INLINE
-     731             :         slice_expr<T, Stop, Start> slice() {
-     732             :                 return {*static_cast<T *>(this)};
-     733             :         }
-     734             : 
-     735             :         template<class U>
-     736             :         CXXRTL_ALWAYS_INLINE
-     737             :         concat_expr<const T, typename std::remove_reference<const U>::type> concat(const U &other) const {
-     738             :                 return {*static_cast<const T *>(this), other};
-     739             :         }
-     740             : 
-     741             :         template<class U>
-     742             :         CXXRTL_ALWAYS_INLINE
-     743             :         concat_expr<T, typename std::remove_reference<U>::type> concat(U &&other) {
-     744             :                 return {*static_cast<T *>(this), other};
-     745             :         }
-     746             : };
-     747             : 
-     748             : template<size_t Bits>
-     749             : std::ostream &operator<<(std::ostream &os, const value<Bits> &val) {
-     750             :         auto old_flags = os.flags(std::ios::right);
-     751             :         auto old_width = os.width(0);
-     752             :         auto old_fill  = os.fill('0');
-     753             :         os << val.bits << '\'' << std::hex;
-     754             :         for (size_t n = val.chunks - 1; n != (size_t)-1; n--) {
-     755             :                 if (n == val.chunks - 1 && Bits % value<Bits>::chunk::bits != 0)
-     756             :                         os.width((Bits % value<Bits>::chunk::bits + 3) / 4);
-     757             :                 else
-     758             :                         os.width((value<Bits>::chunk::bits + 3) / 4);
-     759             :                 os << val.data[n];
-     760             :         }
-     761             :         os.fill(old_fill);
-     762             :         os.width(old_width);
-     763             :         os.flags(old_flags);
-     764             :         return os;
-     765             : }
-     766             : 
-     767             : template<size_t Bits>
-     768             : struct wire {
-     769             :         static constexpr size_t bits = Bits;
-     770             : 
-     771             :         value<Bits> curr;
-     772             :         value<Bits> next;
-     773             : 
-     774             :         wire() = default;
-     775             :         explicit constexpr wire(const value<Bits> &init) : curr(init), next(init) {}
-     776             :         template<typename... Init>
-     777             :         explicit constexpr wire(Init ...init) : curr{init...}, next{init...} {}
-     778             : 
-     779             :         // Copying and copy-assigning values is natural. If, however, a value is replaced with a wire,
-     780             :         // e.g. because a module is built with a different optimization level, then existing code could
-     781             :         // unintentionally copy a wire instead, which would create a subtle but serious bug. To make sure
-     782             :         // this doesn't happen, prohibit copying and copy-assigning wires.
-     783             :         wire(const wire<Bits> &) = delete;
-     784             :         wire<Bits> &operator=(const wire<Bits> &) = delete;
-     785             : 
-     786             :         wire(wire<Bits> &&) = default;
-     787             :         wire<Bits> &operator=(wire<Bits> &&) = default;
-     788             : 
-     789             :         template<class IntegerT>
-     790             :         CXXRTL_ALWAYS_INLINE
-     791             :         IntegerT get() const {
-     792             :                 return curr.template get<IntegerT>();
-     793             :         }
-     794             : 
-     795             :         template<class IntegerT>
-     796             :         CXXRTL_ALWAYS_INLINE
-     797             :         void set(IntegerT other) {
-     798             :                 next.template set<IntegerT>(other);
-     799             :         }
-     800             : 
-     801             :         // This method intentionally takes a mandatory argument (to make it more difficult to misuse in
-     802             :         // black box implementations, leading to missed observer events). It is generic over its argument
-     803             :         // to allow the `on_update` method to be non-virtual.
-     804             :         template<class ObserverT>
-     805             :         bool commit(ObserverT &observer) {
-     806             :                 if (curr != next) {
-     807             :                         observer.on_update(curr.chunks, curr.data, next.data);
-     808             :                         curr = next;
-     809             :                         return true;
-     810             :                 }
-     811             :                 return false;
-     812             :         }
-     813             : };
-     814             : 
-     815             : template<size_t Bits>
-     816             : std::ostream &operator<<(std::ostream &os, const wire<Bits> &val) {
-     817             :         os << val.curr;
-     818             :         return os;
-     819             : }
-     820             : 
-     821             : template<size_t Width>
-     822             : struct memory {
-     823             :         const size_t depth;
-     824             :         std::unique_ptr<value<Width>[]> data;
-     825             : 
-     826             :         explicit memory(size_t depth) : depth(depth), data(new value<Width>[depth]) {}
-     827             : 
-     828             :         memory(const memory<Width> &) = delete;
-     829             :         memory<Width> &operator=(const memory<Width> &) = delete;
-     830             : 
-     831             :         memory(memory<Width> &&) = default;
-     832             :         memory<Width> &operator=(memory<Width> &&other) {
-     833             :                 assert(depth == other.depth);
-     834             :                 data = std::move(other.data);
-     835             :                 write_queue = std::move(other.write_queue);
-     836             :                 return *this;
-     837             :         }
-     838             : 
-     839             :         // An operator for direct memory reads. May be used at any time during the simulation.
-     840             :         const value<Width> &operator [](size_t index) const {
-     841             :                 assert(index < depth);
-     842             :                 return data[index];
-     843             :         }
-     844             : 
-     845             :         // An operator for direct memory writes. May only be used before the simulation is started. If used
-     846             :         // after the simulation is started, the design may malfunction.
-     847             :         value<Width> &operator [](size_t index) {
-     848             :                 assert(index < depth);
-     849             :                 return data[index];
-     850             :         }
-     851             : 
-     852             :         // A simple way to make a writable memory would be to use an array of wires instead of an array of values.
-     853             :         // However, there are two significant downsides to this approach: first, it has large overhead (2× space
-     854             :         // overhead, and O(depth) time overhead during commit); second, it does not simplify handling write port
-     855             :         // priorities. Although in principle write ports could be ordered or conditionally enabled in generated
-     856             :         // code based on their priorities and selected addresses, the feedback arc set problem is computationally
-     857             :         // expensive, and the heuristic based algorithms are not easily modified to guarantee (rather than prefer)
-     858             :         // a particular write port evaluation order.
-     859             :         //
-     860             :         // The approach used here instead is to queue writes into a buffer during the eval phase, then perform
-     861             :         // the writes during the commit phase in the priority order. This approach has low overhead, with both space
-     862             :         // and time proportional to the amount of write ports. Because virtually every memory in a practical design
-     863             :         // has at most two write ports, linear search is used on every write, being the fastest and simplest approach.
-     864             :         struct write {
-     865             :                 size_t index;
-     866             :                 value<Width> val;
-     867             :                 value<Width> mask;
-     868             :                 int priority;
-     869             :         };
-     870             :         std::vector<write> write_queue;
-     871             : 
-     872             :         void update(size_t index, const value<Width> &val, const value<Width> &mask, int priority = 0) {
-     873             :                 assert(index < depth);
-     874             :                 // Queue up the write while keeping the queue sorted by priority.
-     875             :                 write_queue.insert(
-     876             :                         std::upper_bound(write_queue.begin(), write_queue.end(), priority,
-     877             :                                 [](const int a, const write& b) { return a < b.priority; }),
-     878             :                         write { index, val, mask, priority });
-     879             :         }
-     880             : 
-     881             :         // See the note for `wire::commit()`.
-     882             :         template<class ObserverT>
-     883             :         bool commit(ObserverT &observer) {
-     884             :                 bool changed = false;
-     885             :                 for (const write &entry : write_queue) {
-     886             :                         value<Width> elem = data[entry.index];
-     887             :                         elem = elem.update(entry.val, entry.mask);
-     888             :                         if (data[entry.index] != elem) {
-     889             :                                 observer.on_update(value<Width>::chunks, data[0].data, elem.data, entry.index);
-     890             :                                 changed |= true;
-     891             :                         }
-     892             :                         data[entry.index] = elem;
-     893             :                 }
-     894             :                 write_queue.clear();
-     895             :                 return changed;
-     896             :         }
-     897             : };
-     898             : 
-     899          27 : struct metadata {
-     900             :         const enum {
-     901             :                 MISSING = 0,
-     902             :                 UINT    = 1,
-     903             :                 SINT    = 2,
-     904             :                 STRING  = 3,
-     905             :                 DOUBLE  = 4,
-     906             :         } value_type;
-     907             : 
-     908             :         // In debug mode, using the wrong .as_*() function will assert.
-     909             :         // In release mode, using the wrong .as_*() function will safely return a default value.
-     910             :         const uint64_t    uint_value = 0;
-     911             :         const int64_t     sint_value = 0;
-     912             :         const std::string string_value = "";
-     913             :         const double      double_value = 0.0;
-     914             : 
-     915             :         metadata() : value_type(MISSING) {}
-     916           0 :         metadata(uint64_t value) : value_type(UINT), uint_value(value) {}
-     917           0 :         metadata(int64_t value) : value_type(SINT), sint_value(value) {}
-     918           9 :         metadata(const std::string &value) : value_type(STRING), string_value(value) {}
-     919           0 :         metadata(const char *value) : value_type(STRING), string_value(value) {}
-     920           0 :         metadata(double value) : value_type(DOUBLE), double_value(value) {}
-     921             : 
-     922          18 :         metadata(const metadata &) = default;
-     923             :         metadata &operator=(const metadata &) = delete;
-     924             : 
-     925             :         uint64_t as_uint() const {
-     926             :                 assert(value_type == UINT);
-     927             :                 return uint_value;
-     928             :         }
-     929             : 
-     930             :         int64_t as_sint() const {
-     931             :                 assert(value_type == SINT);
-     932             :                 return sint_value;
-     933             :         }
-     934             : 
-     935             :         const std::string &as_string() const {
-     936             :                 assert(value_type == STRING);
-     937             :                 return string_value;
-     938             :         }
-     939             : 
-     940             :         double as_double() const {
-     941             :                 assert(value_type == DOUBLE);
-     942             :                 return double_value;
-     943             :         }
-     944             : 
-     945             :         // Internal CXXRTL use only.
-     946           9 :         static std::map<std::string, metadata> deserialize(const char *ptr) {
-     947           9 :                 std::map<std::string, metadata> result;
-     948           9 :                 std::string name;
-     949             :                 // Grammar:
-     950             :                 // string   ::= [^\0]+ \0
-     951             :                 // metadata ::= [uid] .{8} | s <string>
-     952             :                 // map      ::= ( <string> <metadata> )* \0
-     953          45 :                 for (;;) {
-     954          45 :                         if (*ptr) {
-     955          45 :                                 name += *ptr++;
-     956          18 :                         } else if (!name.empty()) {
-     957           9 :                                 ptr++;
-     958           9 :                                 auto get_u64 = [&]() {
-     959           0 :                                         uint64_t result = 0;
-     960           0 :                                         for (size_t count = 0; count < 8; count++)
-     961           0 :                                                 result = (result << 8) | *ptr++;
-     962           0 :                                         return result;
-     963           9 :                                 };
-     964           9 :                                 char type = *ptr++;
-     965           9 :                                 if (type == 'u') {
-     966           0 :                                         uint64_t value = get_u64();
-     967           0 :                                         result.emplace(name, value);
-     968           9 :                                 } else if (type == 'i') {
-     969           0 :                                         int64_t value = (int64_t)get_u64();
-     970           0 :                                         result.emplace(name, value);
-     971           9 :                                 } else if (type == 'd') {
-     972           0 :                                         double dvalue;
-     973           0 :                                         uint64_t uvalue = get_u64();
-     974           0 :                                         static_assert(sizeof(dvalue) == sizeof(uvalue), "double must be 64 bits in size");
-     975           0 :                                         memcpy(&dvalue, &uvalue, sizeof(dvalue));
-     976           0 :                                         result.emplace(name, dvalue);
-     977           9 :                                 } else if (type == 's') {
-     978           9 :                                         std::string value;
-     979           9 :                                         while (*ptr)
-     980         216 :                                                 value += *ptr++;
-     981           9 :                                         ptr++;
-     982           9 :                                         result.emplace(name, value);
-     983           9 :                                 } else {
-     984           0 :                                         assert(false && "Unknown type specifier");
-     985           9 :                                         return result;
-     986             :                                 }
-     987           9 :                                 name.clear();
-     988             :                         } else {
-     989           9 :                                 return result;
-     990             :                         }
-     991             :                 }
-     992           9 :         }
-     993             : };
-     994             : 
-     995             : typedef std::map<std::string, metadata> metadata_map;
-     996             : 
-     997             : struct performer;
-     998             : 
-     999             : // An object that allows formatting a string lazily.
-    1000             : struct lazy_fmt {
-    1001             :         virtual std::string operator() () const = 0;
-    1002             : };
-    1003             : 
-    1004             : // Flavor of a `$check` cell.
-    1005             : enum class flavor {
-    1006             :         // Corresponds to a `$assert` cell in other flows, and a Verilog `assert ()` statement.
-    1007             :         ASSERT,
-    1008             :         // Corresponds to a `$assume` cell in other flows, and a Verilog `assume ()` statement.
-    1009             :         ASSUME,
-    1010             :         // Corresponds to a `$live` cell in other flows, and a Verilog `assert (eventually)` statement.
-    1011             :         ASSERT_EVENTUALLY,
-    1012             :         // Corresponds to a `$fair` cell in other flows, and a Verilog `assume (eventually)` statement.
-    1013             :         ASSUME_EVENTUALLY,
-    1014             :         // Corresponds to a `$cover` cell in other flows, and a Verilog `cover ()` statement.
-    1015             :         COVER,
-    1016             : };
-    1017             : 
-    1018             : // An object that can be passed to a `eval()` method in order to act on side effects. The default behavior implemented
-    1019             : // below is the same as the behavior of `eval(nullptr)`, except that `-print-output` option of `write_cxxrtl` is not
-    1020             : // taken into account.
-    1021             : struct performer {
-    1022             :         // Called by generated formatting code to evaluate a Verilog `$time` expression.
-    1023             :         virtual int64_t vlog_time() const { return 0; }
-    1024             : 
-    1025             :         // Called by generated formatting code to evaluate a Verilog `$realtime` expression.
-    1026             :         virtual double vlog_realtime() const { return vlog_time(); }
-    1027             : 
-    1028             :         // Called when a `$print` cell is triggered.
-    1029             :         virtual void on_print(const lazy_fmt &formatter, const metadata_map &attributes) {
-    1030             :                 std::cout << formatter();
-    1031             :         }
-    1032             : 
-    1033             :         // Called when a `$check` cell is triggered.
-    1034             :         virtual void on_check(flavor type, bool condition, const lazy_fmt &formatter, const metadata_map &attributes) {
-    1035             :                 if (type == flavor::ASSERT || type == flavor::ASSUME) {
-    1036             :                         if (!condition)
-    1037             :                                 std::cerr << formatter();
-    1038             :                         CXXRTL_ASSERT(condition && "Check failed");
-    1039             :                 }
-    1040             :         }
-    1041             : };
-    1042             : 
-    1043             : // An object that can be passed to a `commit()` method in order to produce a replay log of every state change in
-    1044             : // the simulation. Unlike `performer`, `observer` does not use virtual calls as their overhead is unacceptable, and
-    1045             : // a comparatively heavyweight template-based solution is justified.
-    1046             : struct observer {
-    1047             :         // Called when the `commit()` method for a wire is about to update the `chunks` chunks at `base` with `chunks` chunks
-    1048             :         // at `value` that have a different bit pattern. It is guaranteed that `chunks` is equal to the wire chunk count and
-    1049             :         // `base` points to the first chunk.
-    1050             :         void on_update(size_t chunks, const chunk_t *base, const chunk_t *value) {}
-    1051             : 
-    1052             :         // Called when the `commit()` method for a memory is about to update the `chunks` chunks at `&base[chunks * index]`
-    1053             :         // with `chunks` chunks at `value` that have a different bit pattern. It is guaranteed that `chunks` is equal to
-    1054             :         // the memory element chunk count and `base` points to the first chunk of the first element of the memory.
-    1055             :         void on_update(size_t chunks, const chunk_t *base, const chunk_t *value, size_t index) {}
-    1056             : };
-    1057             : 
-    1058             : // Must be kept in sync with `struct FmtPart` in kernel/fmt.h!
-    1059             : // Default member initializers would make this a non-aggregate-type in C++11, so they are commented out.
-    1060             : struct fmt_part {
-    1061             :         enum {
-    1062             :                 LITERAL   = 0,
-    1063             :                 INTEGER   = 1,
-    1064             :                 STRING    = 2,
-    1065             :                 UNICHAR   = 3,
-    1066             :                 VLOG_TIME = 4,
-    1067             :         } type;
-    1068             : 
-    1069             :         // LITERAL type
-    1070             :         std::string str;
-    1071             : 
-    1072             :         // INTEGER/STRING/UNICHAR types
-    1073             :         // + value<Bits> val;
-    1074             : 
-    1075             :         // INTEGER/STRING/VLOG_TIME types
-    1076             :         enum {
-    1077             :                 RIGHT   = 0,
-    1078             :                 LEFT    = 1,
-    1079             :                 NUMERIC = 2,
-    1080             :         } justify; // = RIGHT;
-    1081             :         char padding; // = '\0';
-    1082             :         size_t width; // = 0;
-    1083             : 
-    1084             :         // INTEGER type
-    1085             :         unsigned base; // = 10;
-    1086             :         bool signed_; // = false;
-    1087             :         enum {
-    1088             :                 MINUS           = 0,
-    1089             :                 PLUS_MINUS      = 1,
-    1090             :                 SPACE_MINUS     = 2,
-    1091             :         } sign; // = MINUS;
-    1092             :         bool hex_upper; // = false;
-    1093             :         bool show_base; // = false;
-    1094             :         bool group; // = false;
-    1095             : 
-    1096             :         // VLOG_TIME type
-    1097             :         bool realtime; // = false;
-    1098             :         // + int64_t itime;
-    1099             :         // + double ftime;
-    1100             : 
-    1101             :         // Format the part as a string.
-    1102             :         //
-    1103             :         // The values of `vlog_time` and `vlog_realtime` are used for Verilog `$time` and `$realtime`, correspondingly.
-    1104             :         template<size_t Bits>
-    1105             :         std::string render(value<Bits> val, performer *performer = nullptr)
-    1106             :         {
-    1107             :                 // We might want to replace some of these bit() calls with direct
-    1108             :                 // chunk access if it turns out to be slow enough to matter.
-    1109             :                 std::string buf;
-    1110             :                 std::string prefix;
-    1111             :                 switch (type) {
-    1112             :                         case LITERAL:
-    1113             :                                 return str;
-    1114             : 
-    1115             :                         case STRING: {
-    1116             :                                 buf.reserve(Bits/8);
-    1117             :                                 for (int i = 0; i < Bits; i += 8) {
-    1118             :                                         char ch = 0;
-    1119             :                                         for (int j = 0; j < 8 && i + j < int(Bits); j++)
-    1120             :                                                 if (val.bit(i + j))
-    1121             :                                                         ch |= 1 << j;
-    1122             :                                         if (ch != 0)
-    1123             :                                                 buf.append({ch});
-    1124             :                                 }
-    1125             :                                 std::reverse(buf.begin(), buf.end());
-    1126             :                                 break;
-    1127             :                         }
-    1128             : 
-    1129             :                         case UNICHAR: {
-    1130             :                                 uint32_t codepoint = val.template get<uint32_t>();
-    1131             :                                 if (codepoint >= 0x10000)
-    1132             :                                         buf += (char)(0xf0 |  (codepoint >> 18));
-    1133             :                                 else if (codepoint >= 0x800)
-    1134             :                                         buf += (char)(0xe0 |  (codepoint >> 12));
-    1135             :                                 else if (codepoint >= 0x80)
-    1136             :                                         buf += (char)(0xc0 |  (codepoint >>  6));
-    1137             :                                 else
-    1138             :                                         buf += (char)codepoint;
-    1139             :                                 if (codepoint >= 0x10000)
-    1140             :                                         buf += (char)(0x80 | ((codepoint >> 12) & 0x3f));
-    1141             :                                 if (codepoint >= 0x800)
-    1142             :                                         buf += (char)(0x80 | ((codepoint >>  6) & 0x3f));
-    1143             :                                 if (codepoint >= 0x80)
-    1144             :                                         buf += (char)(0x80 | ((codepoint >>  0) & 0x3f));
-    1145             :                                 break;
-    1146             :                         }
-    1147             : 
-    1148             :                         case INTEGER: {
-    1149             :                                 bool negative = signed_ && val.is_neg();
-    1150             :                                 if (negative) {
-    1151             :                                         prefix = "-";
-    1152             :                                         val = val.neg();
-    1153             :                                 } else {
-    1154             :                                         switch (sign) {
-    1155             :                                                 case MINUS:       break;
-    1156             :                                                 case PLUS_MINUS:  prefix = "+"; break;
-    1157             :                                                 case SPACE_MINUS: prefix = " "; break;
-    1158             :                                         }
-    1159             :                                 }
-    1160             : 
-    1161             :                                 size_t val_width = Bits;
-    1162             :                                 if (base != 10) {
-    1163             :                                         val_width = 1;
-    1164             :                                         for (size_t index = 0; index < Bits; index++)
-    1165             :                                                 if (val.bit(index))
-    1166             :                                                         val_width = index + 1;
-    1167             :                                 }
-    1168             : 
-    1169             :                                 if (base == 2) {
-    1170             :                                         if (show_base)
-    1171             :                                                 prefix += "0b";
-    1172             :                                         for (size_t index = 0; index < val_width; index++) {
-    1173             :                                                 if (group && index > 0 && index % 4 == 0)
-    1174             :                                                         buf += '_';
-    1175             :                                                 buf += (val.bit(index) ? '1' : '0');
-    1176             :                                         }
-    1177             :                                 } else if (base == 8 || base == 16) {
-    1178             :                                         if (show_base)
-    1179             :                                                 prefix += (base == 16) ? (hex_upper ? "0X" : "0x") : "0o";
-    1180             :                                         size_t step = (base == 16) ? 4 : 3;
-    1181             :                                         for (size_t index = 0; index < val_width; index += step) {
-    1182             :                                                 if (group && index > 0 && index % (4 * step) == 0)
-    1183             :                                                         buf += '_';
-    1184             :                                                 uint8_t value = val.bit(index) | (val.bit(index + 1) << 1) | (val.bit(index + 2) << 2);
-    1185             :                                                 if (step == 4)
-    1186             :                                                         value |= val.bit(index + 3) << 3;
-    1187             :                                                 buf += (hex_upper ? "0123456789ABCDEF" : "0123456789abcdef")[value];
-    1188             :                                         }
-    1189             :                                 } else if (base == 10) {
-    1190             :                                         if (show_base)
-    1191             :                                                 prefix += "0d";
-    1192             :                                         if (val.is_zero())
-    1193             :                                                 buf += '0';
-    1194             :                                         value<(Bits > 4 ? Bits : 4)> xval = val.template zext<(Bits > 4 ? Bits : 4)>();
-    1195             :                                         size_t index = 0;
-    1196             :                                         while (!xval.is_zero()) {
-    1197             :                                                 if (group && index > 0 && index % 3 == 0)
-    1198             :                                                         buf += '_';
-    1199             :                                                 value<(Bits > 4 ? Bits : 4)> quotient, remainder;
-    1200             :                                                 if (Bits >= 4)
-    1201             :                                                         std::tie(quotient, remainder) = xval.udivmod(value<(Bits > 4 ? Bits : 4)>{10u});
-    1202             :                                                 else
-    1203             :                                                         std::tie(quotient, remainder) = std::make_pair(value<(Bits > 4 ? Bits : 4)>{0u}, xval);
-    1204             :                                                 buf += '0' + remainder.template trunc<4>().template get<uint8_t>();
-    1205             :                                                 xval = quotient;
-    1206             :                                                 index++;
-    1207             :                                         }
-    1208             :                                 } else assert(false && "Unsupported base for fmt_part");
-    1209             :                                 if (justify == NUMERIC && group && padding == '0') {
-    1210             :                                         int group_size = base == 10 ? 3 : 4;
-    1211             :                                         while (prefix.size() + buf.size() < width) {
-    1212             :                                                 if (buf.size() % (group_size + 1) == group_size)
-    1213             :                                                         buf += '_';
-    1214             :                                                 buf += '0';
-    1215             :                                         }
-    1216             :                                 }
-    1217             :                                 std::reverse(buf.begin(), buf.end());
-    1218             :                                 break;
-    1219             :                         }
-    1220             : 
-    1221             :                         case VLOG_TIME: {
-    1222             :                                 if (performer) {
-    1223             :                                         buf = realtime ? std::to_string(performer->vlog_realtime()) : std::to_string(performer->vlog_time());
-    1224             :                                 } else {
-    1225             :                                         buf = realtime ? std::to_string(0.0) : std::to_string(0);
-    1226             :                                 }
-    1227             :                                 break;
-    1228             :                         }
-    1229             :                 }
-    1230             : 
-    1231             :                 std::string str;
-    1232             :                 assert(width == 0 || padding != '\0');
-    1233             :                 if (prefix.size() + buf.size() < width) {
-    1234             :                         size_t pad_width = width - prefix.size() - buf.size();
-    1235             :                         switch (justify) {
-    1236             :                                 case LEFT:
-    1237             :                                         str += prefix;
-    1238             :                                         str += buf;
-    1239             :                                         str += std::string(pad_width, padding);
-    1240             :                                         break;
-    1241             :                                 case RIGHT:
-    1242             :                                         str += std::string(pad_width, padding);
-    1243             :                                         str += prefix;
-    1244             :                                         str += buf;
-    1245             :                                         break;
-    1246             :                                 case NUMERIC:
-    1247             :                                         str += prefix;
-    1248             :                                         str += std::string(pad_width, padding);
-    1249             :                                         str += buf;
-    1250             :                                         break;
-    1251             :                                 }
-    1252             :                 } else {
-    1253             :                         str += prefix;
-    1254             :                         str += buf;
-    1255             :                 }
-    1256             :                 return str;
-    1257             :         }
-    1258             : };
-    1259             : 
-    1260             : // Tag class to disambiguate values/wires and their aliases.
-    1261             : struct debug_alias {};
-    1262             : 
-    1263             : // Tag declaration to disambiguate values and debug outlines.
-    1264             : using debug_outline = ::_cxxrtl_outline;
-    1265             : 
-    1266             : // This structure is intended for consumption via foreign function interfaces, like Python's ctypes.
-    1267             : // Because of this it uses a C-style layout that is easy to parse rather than more idiomatic C++.
-    1268             : //
-    1269             : // To avoid violating strict aliasing rules, this structure has to be a subclass of the one used
-    1270             : // in the C API, or it would not be possible to cast between the pointers to these.
-    1271             : //
-    1272             : // The `attrs` member cannot be owned by this structure because a `cxxrtl_object` can be created
-    1273             : // from external C code.
-    1274             : struct debug_item : ::cxxrtl_object {
-    1275             :         // Object types.
-    1276             :         enum : uint32_t {
-    1277             :                 VALUE   = CXXRTL_VALUE,
-    1278             :                 WIRE    = CXXRTL_WIRE,
-    1279             :                 MEMORY  = CXXRTL_MEMORY,
-    1280             :                 ALIAS   = CXXRTL_ALIAS,
-    1281             :                 OUTLINE = CXXRTL_OUTLINE,
-    1282             :         };
-    1283             : 
-    1284             :         // Object flags.
-    1285             :         enum : uint32_t {
-    1286             :                 INPUT  = CXXRTL_INPUT,
-    1287             :                 OUTPUT = CXXRTL_OUTPUT,
-    1288             :                 INOUT  = CXXRTL_INOUT,
-    1289             :                 DRIVEN_SYNC = CXXRTL_DRIVEN_SYNC,
-    1290             :                 DRIVEN_COMB = CXXRTL_DRIVEN_COMB,
-    1291             :                 UNDRIVEN    = CXXRTL_UNDRIVEN,
-    1292             :         };
-    1293             : 
-    1294             :         debug_item(const ::cxxrtl_object &object) : cxxrtl_object(object) {}
-    1295             : 
-    1296             :         template<size_t Bits>
-    1297           9 :         debug_item(value<Bits> &item, size_t lsb_offset = 0, uint32_t flags_ = 0) {
-    1298             :                 static_assert(Bits == 0 || sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),
-    1299             :                               "value<Bits> is not compatible with C layout");
-    1300           9 :                 type    = VALUE;
-    1301           9 :                 flags   = flags_;
-    1302           9 :                 width   = Bits;
-    1303           9 :                 lsb_at  = lsb_offset;
-    1304           9 :                 depth   = 1;
-    1305           9 :                 zero_at = 0;
-    1306           9 :                 curr    = item.data;
-    1307           9 :                 next    = item.data;
-    1308           9 :                 outline = nullptr;
-    1309           9 :                 attrs   = nullptr;
-    1310             :         }
-    1311             : 
-    1312             :         template<size_t Bits>
-    1313             :         debug_item(const value<Bits> &item, size_t lsb_offset = 0) {
-    1314             :                 static_assert(Bits == 0 || sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),
-    1315             :                               "value<Bits> is not compatible with C layout");
-    1316             :                 type    = VALUE;
-    1317             :                 flags   = DRIVEN_COMB;
-    1318             :                 width   = Bits;
-    1319             :                 lsb_at  = lsb_offset;
-    1320             :                 depth   = 1;
-    1321             :                 zero_at = 0;
-    1322             :                 curr    = const_cast<chunk_t*>(item.data);
-    1323             :                 next    = nullptr;
-    1324             :                 outline = nullptr;
-    1325             :                 attrs   = nullptr;
-    1326             :         }
-    1327             : 
-    1328             :         template<size_t Bits>
-    1329             :         debug_item(wire<Bits> &item, size_t lsb_offset = 0, uint32_t flags_ = 0) {
-    1330             :                 static_assert(Bits == 0 ||
-    1331             :                               (sizeof(item.curr) == value<Bits>::chunks * sizeof(chunk_t) &&
-    1332             :                                sizeof(item.next) == value<Bits>::chunks * sizeof(chunk_t)),
-    1333             :                               "wire<Bits> is not compatible with C layout");
-    1334             :                 type    = WIRE;
-    1335             :                 flags   = flags_;
-    1336             :                 width   = Bits;
-    1337             :                 lsb_at  = lsb_offset;
-    1338             :                 depth   = 1;
-    1339             :                 zero_at = 0;
-    1340             :                 curr    = item.curr.data;
-    1341             :                 next    = item.next.data;
-    1342             :                 outline = nullptr;
-    1343             :                 attrs   = nullptr;
-    1344             :         }
-    1345             : 
-    1346             :         template<size_t Width>
-    1347             :         debug_item(memory<Width> &item, size_t zero_offset = 0) {
-    1348             :                 static_assert(Width == 0 || sizeof(item.data[0]) == value<Width>::chunks * sizeof(chunk_t),
-    1349             :                               "memory<Width> is not compatible with C layout");
-    1350             :                 type    = MEMORY;
-    1351             :                 flags   = 0;
-    1352             :                 width   = Width;
-    1353             :                 lsb_at  = 0;
-    1354             :                 depth   = item.depth;
-    1355             :                 zero_at = zero_offset;
-    1356             :                 curr    = item.data ? item.data[0].data : nullptr;
-    1357             :                 next    = nullptr;
-    1358             :                 outline = nullptr;
-    1359             :                 attrs   = nullptr;
-    1360             :         }
-    1361             : 
-    1362             :         template<size_t Bits>
-    1363             :         debug_item(debug_alias, const value<Bits> &item, size_t lsb_offset = 0) {
-    1364             :                 static_assert(Bits == 0 || sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),
-    1365             :                               "value<Bits> is not compatible with C layout");
-    1366             :                 type    = ALIAS;
-    1367             :                 flags   = DRIVEN_COMB;
-    1368             :                 width   = Bits;
-    1369             :                 lsb_at  = lsb_offset;
-    1370             :                 depth   = 1;
-    1371             :                 zero_at = 0;
-    1372             :                 curr    = const_cast<chunk_t*>(item.data);
-    1373             :                 next    = nullptr;
-    1374             :                 outline = nullptr;
-    1375             :                 attrs   = nullptr;
-    1376             :         }
-    1377             : 
-    1378             :         template<size_t Bits>
-    1379             :         debug_item(debug_alias, const wire<Bits> &item, size_t lsb_offset = 0) {
-    1380             :                 static_assert(Bits == 0 ||
-    1381             :                               (sizeof(item.curr) == value<Bits>::chunks * sizeof(chunk_t) &&
-    1382             :                                sizeof(item.next) == value<Bits>::chunks * sizeof(chunk_t)),
-    1383             :                               "wire<Bits> is not compatible with C layout");
-    1384             :                 type    = ALIAS;
-    1385             :                 flags   = DRIVEN_COMB;
-    1386             :                 width   = Bits;
-    1387             :                 lsb_at  = lsb_offset;
-    1388             :                 depth   = 1;
-    1389             :                 zero_at = 0;
-    1390             :                 curr    = const_cast<chunk_t*>(item.curr.data);
-    1391             :                 next    = nullptr;
-    1392             :                 outline = nullptr;
-    1393             :                 attrs   = nullptr;
-    1394             :         }
-    1395             : 
-    1396             :         template<size_t Bits>
-    1397             :         debug_item(debug_outline &group, const value<Bits> &item, size_t lsb_offset = 0) {
-    1398             :                 static_assert(Bits == 0 || sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),
-    1399             :                               "value<Bits> is not compatible with C layout");
-    1400             :                 type    = OUTLINE;
-    1401             :                 flags   = DRIVEN_COMB;
-    1402             :                 width   = Bits;
-    1403             :                 lsb_at  = lsb_offset;
-    1404             :                 depth   = 1;
-    1405             :                 zero_at = 0;
-    1406             :                 curr    = const_cast<chunk_t*>(item.data);
-    1407             :                 next    = nullptr;
-    1408             :                 outline = &group;
-    1409             :                 attrs   = nullptr;
-    1410             :         }
-    1411             : 
-    1412             :         template<size_t Bits, class IntegerT>
-    1413             :         IntegerT get() const {
-    1414             :                 assert(width == Bits && depth == 1);
-    1415             :                 value<Bits> item;
-    1416             :                 std::copy(curr, curr + value<Bits>::chunks, item.data);
-    1417             :                 return item.template get<IntegerT>();
-    1418             :         }
-    1419             : 
-    1420             :         template<size_t Bits, class IntegerT>
-    1421             :         void set(IntegerT other) const {
-    1422             :                 assert(width == Bits && depth == 1);
-    1423             :                 value<Bits> item;
-    1424             :                 item.template set<IntegerT>(other);
-    1425             :                 std::copy(item.data, item.data + value<Bits>::chunks, next);
-    1426             :         }
-    1427             : };
-    1428             : static_assert(std::is_standard_layout<debug_item>::value, "debug_item is not compatible with C layout");
-    1429             : 
-    1430             : } // namespace cxxrtl
-    1431             : 
-    1432           9 : typedef struct _cxxrtl_attr_set {
-    1433             :         cxxrtl::metadata_map map;
-    1434             : } *cxxrtl_attr_set;
-    1435             : 
-    1436             : namespace cxxrtl {
-    1437             : 
-    1438             : // Representation of an attribute set in the C++ interface.
-    1439             : using debug_attrs = ::_cxxrtl_attr_set;
-    1440             : 
-    1441           3 : struct debug_items {
-    1442             :         // Debug items may be composed of multiple parts, but the attributes are shared between all of them.
-    1443             :         // There are additional invariants, not all of which are not checked by this code:
-    1444             :         // - Memories and non-memories cannot be mixed together.
-    1445             :         // - Bit indices (considering `lsb_at` and `width`) must not overlap.
-    1446             :         // - Row indices (considering `depth` and `zero_at`) must be the same.
-    1447             :         // - The `INPUT` and `OUTPUT` flags must be the same for all parts.
-    1448             :         // Other than that, the parts can be quite different, e.g. it is OK to mix a value, a wire, an alias,
-    1449             :         // and an outline, in the debug information for a single name in four parts.
-    1450             :         std::map<std::string, std::vector<debug_item>> table;
-    1451             :         std::map<std::string, std::unique_ptr<debug_attrs>> attrs_table;
-    1452             : 
-    1453           9 :         void add(const std::string &path, debug_item &&item, metadata_map &&item_attrs = {}) {
-    1454           9 :                 assert((path.empty() || path[path.size() - 1] != ' ') && path.find("  ") == std::string::npos);
-    1455           9 :                 std::unique_ptr<debug_attrs> &attrs = attrs_table[path];
-    1456           9 :                 if (attrs.get() == nullptr)
-    1457           9 :                         attrs = std::unique_ptr<debug_attrs>(new debug_attrs);
-    1458          18 :                 for (auto attr : item_attrs)
-    1459          18 :                         attrs->map.insert(attr);
-    1460           9 :                 item.attrs = attrs.get();
-    1461           9 :                 std::vector<debug_item> &parts = table[path];
-    1462           9 :                 parts.emplace_back(item);
-    1463           9 :                 std::sort(parts.begin(), parts.end(),
-    1464           0 :                         [](const debug_item &a, const debug_item &b) {
-    1465           0 :                                 return a.lsb_at < b.lsb_at;
-    1466             :                         });
-    1467           9 :         }
-    1468             : 
-    1469             :         // This overload exists to reduce excessive stack slot allocation in `CXXRTL_EXTREMELY_COLD void debug_info()`.
-    1470             :         template<class... T>
-    1471           9 :         void add(const std::string &base_path, const char *path, const char *serialized_item_attrs, T&&... args) {
-    1472          18 :                 add(base_path + path, debug_item(std::forward<T>(args)...), metadata::deserialize(serialized_item_attrs));
-    1473           9 :         }
-    1474             : 
-    1475             :         size_t count(const std::string &path) const {
-    1476             :                 if (table.count(path) == 0)
-    1477             :                         return 0;
-    1478             :                 return table.at(path).size();
-    1479             :         }
-    1480             : 
-    1481             :         const std::vector<debug_item> &at(const std::string &path) const {
-    1482             :                 return table.at(path);
-    1483             :         }
-    1484             : 
-    1485             :         // Like `at()`, but operates only on single-part debug items.
-    1486             :         const debug_item &operator [](const std::string &path) const {
-    1487             :                 const std::vector<debug_item> &parts = table.at(path);
-    1488             :                 assert(parts.size() == 1);
-    1489             :                 return parts.at(0);
-    1490             :         }
-    1491             : 
-    1492             :         bool is_memory(const std::string &path) const {
-    1493             :                 return at(path).at(0).type == debug_item::MEMORY;
-    1494             :         }
-    1495             : 
-    1496             :         const metadata_map &attrs(const std::string &path) const {
-    1497             :                 return attrs_table.at(path)->map;
-    1498             :         }
-    1499             : };
-    1500             : 
-    1501             : // Only `module` scopes are defined. The type is implicit, since Yosys does not currently support
-    1502             : // any other scope types.
-    1503           3 : struct debug_scope {
-    1504             :         std::string module_name;
-    1505             :         std::unique_ptr<debug_attrs> module_attrs;
-    1506             :         std::unique_ptr<debug_attrs> cell_attrs;
-    1507             : };
-    1508             : 
-    1509             : struct debug_scopes {
-    1510             :         std::map<std::string, debug_scope> table;
-    1511             : 
-    1512           0 :         void add(const std::string &path, const std::string &module_name, metadata_map &&module_attrs, metadata_map &&cell_attrs) {
-    1513           0 :                 assert((path.empty() || path[path.size() - 1] != ' ') && path.find("  ") == std::string::npos);
-    1514           0 :                 assert(table.count(path) == 0);
-    1515           0 :                 debug_scope &scope = table[path];
-    1516           0 :                 scope.module_name = module_name;
-    1517           0 :                 scope.module_attrs = std::unique_ptr<debug_attrs>(new debug_attrs { module_attrs });
-    1518           0 :                 scope.cell_attrs = std::unique_ptr<debug_attrs>(new debug_attrs { cell_attrs });
-    1519           0 :         }
-    1520             : 
-    1521             :         // This overload exists to reduce excessive stack slot allocation in `CXXRTL_EXTREMELY_COLD void debug_info()`.
-    1522             :         void add(const std::string &base_path, const char *path, const char *module_name, const char *serialized_module_attrs, const char *serialized_cell_attrs) {
-    1523             :                 add(base_path + path, module_name, metadata::deserialize(serialized_module_attrs), metadata::deserialize(serialized_cell_attrs));
-    1524             :         }
-    1525             : 
-    1526             :         size_t contains(const std::string &path) const {
-    1527             :                 return table.count(path);
-    1528             :         }
-    1529             : 
-    1530             :         const debug_scope &operator [](const std::string &path) const {
-    1531             :                 return table.at(path);
-    1532             :         }
-    1533             : };
-    1534             : 
-    1535             : // Tag class to disambiguate the default constructor used by the toplevel module that calls `reset()`,
-    1536             : // and the constructor of interior modules that should not call it.
-    1537             : struct interior {};
-    1538             : 
-    1539             : // The core API of the `module` class consists of only four virtual methods: `reset()`, `eval()`,
-    1540             : // `commit`, and `debug_info()`. (The virtual destructor is made necessary by C++.) Every other method
-    1541             : // is a convenience method, and exists solely to simplify some common pattern for C++ API consumers.
-    1542             : // No behavior may be added to such convenience methods that other parts of CXXRTL can rely on, since
-    1543             : // there is no guarantee they will be called (and, for example, other CXXRTL libraries will often call
-    1544             : // the `eval()` and `commit()` directly instead, as well as being exposed in the C API).
-    1545             : struct module {
-    1546           3 :         module() {}
-    1547           3 :         virtual ~module() {}
-    1548             : 
-    1549             :         // Modules with black boxes cannot be copied. Although not all designs include black boxes,
-    1550             :         // delete the copy constructor and copy assignment operator to make sure that any downstream
-    1551             :         // code that manipulates modules doesn't accidentally depend on their availability.
-    1552             :         module(const module &) = delete;
-    1553             :         module &operator=(const module &) = delete;
-    1554             : 
-    1555             :         module(module &&) = default;
-    1556             :         module &operator=(module &&) = default;
-    1557             : 
-    1558             :         virtual void reset() = 0;
-    1559             : 
-    1560             :         // The `eval()` callback object, `performer`, is included in the virtual call signature since
-    1561             :         // the generated code has broadly identical performance properties.
-    1562             :         virtual bool eval(performer *performer = nullptr) = 0;
-    1563             : 
-    1564             :         // The `commit()` callback object, `observer`, is not included in the virtual call signature since
-    1565             :         // the generated code is severely pessimized by it. To observe commit events, the non-virtual
-    1566             :         // `commit(observer *)` overload must be called directly on a `module` subclass.
-    1567             :         virtual bool commit() = 0;
-    1568             : 
-    1569          33 :         size_t step(performer *performer = nullptr) {
-    1570          33 :                 size_t deltas = 0;
-    1571          33 :                 bool converged = false;
-    1572          33 :                 do {
-    1573          33 :                         converged = eval(performer);
-    1574          33 :                         deltas++;
-    1575          66 :                 } while (commit() && !converged);
-    1576          33 :                 return deltas;
-    1577             :         }
-    1578             : 
-    1579             :         virtual void debug_info(debug_items *items, debug_scopes *scopes, std::string path, metadata_map &&cell_attrs = {}) {
-    1580             :                 (void)items, (void)scopes, (void)path, (void)cell_attrs;
-    1581             :         }
-    1582             : 
-    1583             :         // Compatibility method.
-    1584             : #if __has_attribute(deprecated)
-    1585             :         __attribute__((deprecated("Use `debug_info(path, &items, /*scopes=*/nullptr);` instead. (`path` could be \"top \".)")))
-    1586             : #endif
-    1587             :         void debug_info(debug_items &items, std::string path) {
-    1588             :                 debug_info(&items, /*scopes=*/nullptr, path);
-    1589             :         }
-    1590             : };
-    1591             : 
-    1592             : } // namespace cxxrtl
-    1593             : 
-    1594             : // Internal structures used to communicate with the implementation of the C interface.
-    1595             : 
-    1596             : typedef struct _cxxrtl_toplevel {
-    1597             :         std::unique_ptr<cxxrtl::module> module;
-    1598             : } *cxxrtl_toplevel;
-    1599             : 
-    1600             : typedef struct _cxxrtl_outline {
-    1601             :         std::function<void()> eval;
-    1602             : } *cxxrtl_outline;
-    1603             : 
-    1604             : // Definitions of internal Yosys cells. Other than the functions in this namespace, CXXRTL is fully generic
-    1605             : // and indepenent of Yosys implementation details.
-    1606             : //
-    1607             : // The `write_cxxrtl` pass translates internal cells (cells with names that start with `$`) to calls of these
-    1608             : // functions. All of Yosys arithmetic and logical cells perform sign or zero extension on their operands,
-    1609             : // whereas basic operations on arbitrary width values require operands to be of the same width. These functions
-    1610             : // bridge the gap by performing the necessary casts. They are named similar to `cell_A[B]`, where A and B are `u`
-    1611             : // if the corresponding operand is unsigned, and `s` if it is signed.
-    1612             : namespace cxxrtl_yosys {
-    1613             : 
-    1614             : using namespace cxxrtl;
-    1615             : 
-    1616             : // std::max isn't constexpr until C++14 for no particular reason (it's an oversight), so we define our own.
-    1617             : template<class T>
-    1618             : CXXRTL_ALWAYS_INLINE
-    1619             : constexpr T max(const T &a, const T &b) {
-    1620             :         return a > b ? a : b;
-    1621             : }
-    1622             : 
-    1623             : // Logic operations
-    1624             : template<size_t BitsY, size_t BitsA>
-    1625             : CXXRTL_ALWAYS_INLINE
-    1626             : value<BitsY> logic_not(const value<BitsA> &a) {
-    1627             :         return value<BitsY> { a ? 0u : 1u };
-    1628             : }
-    1629             : 
-    1630             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1631             : CXXRTL_ALWAYS_INLINE
-    1632             : value<BitsY> logic_and(const value<BitsA> &a, const value<BitsB> &b) {
-    1633             :         return value<BitsY> { (bool(a) && bool(b)) ? 1u : 0u };
-    1634             : }
-    1635             : 
-    1636             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1637             : CXXRTL_ALWAYS_INLINE
-    1638             : value<BitsY> logic_or(const value<BitsA> &a, const value<BitsB> &b) {
-    1639             :         return value<BitsY> { (bool(a) || bool(b)) ? 1u : 0u };
-    1640             : }
-    1641             : 
-    1642             : // Reduction operations
-    1643             : template<size_t BitsY, size_t BitsA>
-    1644             : CXXRTL_ALWAYS_INLINE
-    1645             : value<BitsY> reduce_and(const value<BitsA> &a) {
-    1646             :         return value<BitsY> { a.bit_not().is_zero() ? 1u : 0u };
-    1647             : }
-    1648             : 
-    1649             : template<size_t BitsY, size_t BitsA>
-    1650             : CXXRTL_ALWAYS_INLINE
-    1651             : value<BitsY> reduce_or(const value<BitsA> &a) {
-    1652             :         return value<BitsY> { a ? 1u : 0u };
-    1653             : }
-    1654             : 
-    1655             : template<size_t BitsY, size_t BitsA>
-    1656             : CXXRTL_ALWAYS_INLINE
-    1657             : value<BitsY> reduce_xor(const value<BitsA> &a) {
-    1658             :         return value<BitsY> { (a.ctpop() % 2) ? 1u : 0u };
-    1659             : }
-    1660             : 
-    1661             : template<size_t BitsY, size_t BitsA>
-    1662             : CXXRTL_ALWAYS_INLINE
-    1663             : value<BitsY> reduce_xnor(const value<BitsA> &a) {
-    1664             :         return value<BitsY> { (a.ctpop() % 2) ? 0u : 1u };
-    1665             : }
-    1666             : 
-    1667             : template<size_t BitsY, size_t BitsA>
-    1668             : CXXRTL_ALWAYS_INLINE
-    1669             : value<BitsY> reduce_bool(const value<BitsA> &a) {
-    1670             :         return value<BitsY> { a ? 1u : 0u };
-    1671             : }
-    1672             : 
-    1673             : // Bitwise operations
-    1674             : template<size_t BitsY, size_t BitsA>
-    1675             : CXXRTL_ALWAYS_INLINE
-    1676             : value<BitsY> not_u(const value<BitsA> &a) {
-    1677             :         return a.template zcast<BitsY>().bit_not();
-    1678             : }
-    1679             : 
-    1680             : template<size_t BitsY, size_t BitsA>
-    1681             : CXXRTL_ALWAYS_INLINE
-    1682             : value<BitsY> not_s(const value<BitsA> &a) {
-    1683             :         return a.template scast<BitsY>().bit_not();
-    1684             : }
-    1685             : 
-    1686             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1687             : CXXRTL_ALWAYS_INLINE
-    1688             : value<BitsY> and_uu(const value<BitsA> &a, const value<BitsB> &b) {
-    1689             :         return a.template zcast<BitsY>().bit_and(b.template zcast<BitsY>());
-    1690             : }
-    1691             : 
-    1692             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1693             : CXXRTL_ALWAYS_INLINE
-    1694             : value<BitsY> and_ss(const value<BitsA> &a, const value<BitsB> &b) {
-    1695             :         return a.template scast<BitsY>().bit_and(b.template scast<BitsY>());
-    1696             : }
-    1697             : 
-    1698             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1699             : CXXRTL_ALWAYS_INLINE
-    1700             : value<BitsY> or_uu(const value<BitsA> &a, const value<BitsB> &b) {
-    1701             :         return a.template zcast<BitsY>().bit_or(b.template zcast<BitsY>());
-    1702             : }
-    1703             : 
-    1704             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1705             : CXXRTL_ALWAYS_INLINE
-    1706             : value<BitsY> or_ss(const value<BitsA> &a, const value<BitsB> &b) {
-    1707             :         return a.template scast<BitsY>().bit_or(b.template scast<BitsY>());
-    1708             : }
-    1709             : 
-    1710             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1711             : CXXRTL_ALWAYS_INLINE
-    1712             : value<BitsY> xor_uu(const value<BitsA> &a, const value<BitsB> &b) {
-    1713             :         return a.template zcast<BitsY>().bit_xor(b.template zcast<BitsY>());
-    1714             : }
-    1715             : 
-    1716             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1717             : CXXRTL_ALWAYS_INLINE
-    1718             : value<BitsY> xor_ss(const value<BitsA> &a, const value<BitsB> &b) {
-    1719             :         return a.template scast<BitsY>().bit_xor(b.template scast<BitsY>());
-    1720             : }
-    1721             : 
-    1722             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1723             : CXXRTL_ALWAYS_INLINE
-    1724             : value<BitsY> xnor_uu(const value<BitsA> &a, const value<BitsB> &b) {
-    1725             :         return a.template zcast<BitsY>().bit_xor(b.template zcast<BitsY>()).bit_not();
-    1726             : }
-    1727             : 
-    1728             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1729             : CXXRTL_ALWAYS_INLINE
-    1730             : value<BitsY> xnor_ss(const value<BitsA> &a, const value<BitsB> &b) {
-    1731             :         return a.template scast<BitsY>().bit_xor(b.template scast<BitsY>()).bit_not();
-    1732             : }
-    1733             : 
-    1734             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1735             : CXXRTL_ALWAYS_INLINE
-    1736             : value<BitsY> shl_uu(const value<BitsA> &a, const value<BitsB> &b) {
-    1737             :         return a.template zcast<BitsY>().shl(b);
-    1738             : }
-    1739             : 
-    1740             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1741             : CXXRTL_ALWAYS_INLINE
-    1742             : value<BitsY> shl_su(const value<BitsA> &a, const value<BitsB> &b) {
-    1743             :         return a.template scast<BitsY>().shl(b);
-    1744             : }
-    1745             : 
-    1746             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1747             : CXXRTL_ALWAYS_INLINE
-    1748             : value<BitsY> sshl_uu(const value<BitsA> &a, const value<BitsB> &b) {
-    1749             :         return a.template zcast<BitsY>().shl(b);
-    1750             : }
-    1751             : 
-    1752             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1753             : CXXRTL_ALWAYS_INLINE
-    1754             : value<BitsY> sshl_su(const value<BitsA> &a, const value<BitsB> &b) {
-    1755             :         return a.template scast<BitsY>().shl(b);
-    1756             : }
-    1757             : 
-    1758             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1759             : CXXRTL_ALWAYS_INLINE
-    1760             : value<BitsY> shr_uu(const value<BitsA> &a, const value<BitsB> &b) {
-    1761             :         return a.shr(b).template zcast<BitsY>();
-    1762             : }
-    1763             : 
-    1764             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1765             : CXXRTL_ALWAYS_INLINE
-    1766             : value<BitsY> shr_su(const value<BitsA> &a, const value<BitsB> &b) {
-    1767             :         return a.shr(b).template scast<BitsY>();
-    1768             : }
-    1769             : 
-    1770             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1771             : CXXRTL_ALWAYS_INLINE
-    1772             : value<BitsY> sshr_uu(const value<BitsA> &a, const value<BitsB> &b) {
-    1773             :         return a.shr(b).template zcast<BitsY>();
-    1774             : }
-    1775             : 
-    1776             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1777             : CXXRTL_ALWAYS_INLINE
-    1778             : value<BitsY> sshr_su(const value<BitsA> &a, const value<BitsB> &b) {
-    1779             :         return a.sshr(b).template scast<BitsY>();
-    1780             : }
-    1781             : 
-    1782             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1783             : CXXRTL_ALWAYS_INLINE
-    1784             : value<BitsY> shift_uu(const value<BitsA> &a, const value<BitsB> &b) {
-    1785             :         return shr_uu<BitsY>(a, b);
-    1786             : }
-    1787             : 
-    1788             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1789             : CXXRTL_ALWAYS_INLINE
-    1790             : value<BitsY> shift_su(const value<BitsA> &a, const value<BitsB> &b) {
-    1791             :         return shr_su<BitsY>(a, b);
-    1792             : }
-    1793             : 
-    1794             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1795             : CXXRTL_ALWAYS_INLINE
-    1796             : value<BitsY> shift_us(const value<BitsA> &a, const value<BitsB> &b) {
-    1797             :         return b.is_neg() ? shl_uu<BitsY>(a, b.template sext<BitsB + 1>().neg()) : shr_uu<BitsY>(a, b);
-    1798             : }
-    1799             : 
-    1800             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1801             : CXXRTL_ALWAYS_INLINE
-    1802             : value<BitsY> shift_ss(const value<BitsA> &a, const value<BitsB> &b) {
-    1803             :         return b.is_neg() ? shl_su<BitsY>(a, b.template sext<BitsB + 1>().neg()) : shr_su<BitsY>(a, b);
-    1804             : }
-    1805             : 
-    1806             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1807             : CXXRTL_ALWAYS_INLINE
-    1808             : value<BitsY> shiftx_uu(const value<BitsA> &a, const value<BitsB> &b) {
-    1809             :         return shift_uu<BitsY>(a, b);
-    1810             : }
-    1811             : 
-    1812             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1813             : CXXRTL_ALWAYS_INLINE
-    1814             : value<BitsY> shiftx_su(const value<BitsA> &a, const value<BitsB> &b) {
-    1815             :         return shift_su<BitsY>(a, b);
-    1816             : }
-    1817             : 
-    1818             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1819             : CXXRTL_ALWAYS_INLINE
-    1820             : value<BitsY> shiftx_us(const value<BitsA> &a, const value<BitsB> &b) {
-    1821             :         return shift_us<BitsY>(a, b);
-    1822             : }
-    1823             : 
-    1824             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1825             : CXXRTL_ALWAYS_INLINE
-    1826             : value<BitsY> shiftx_ss(const value<BitsA> &a, const value<BitsB> &b) {
-    1827             :         return shift_ss<BitsY>(a, b);
-    1828             : }
-    1829             : 
-    1830             : // Comparison operations
-    1831             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1832             : CXXRTL_ALWAYS_INLINE
-    1833             : value<BitsY> eq_uu(const value<BitsA> &a, const value<BitsB> &b) {
-    1834             :         constexpr size_t BitsExt = max(BitsA, BitsB);
-    1835             :         return value<BitsY>{ a.template zext<BitsExt>() == b.template zext<BitsExt>() ? 1u : 0u };
-    1836             : }
-    1837             : 
-    1838             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1839             : CXXRTL_ALWAYS_INLINE
-    1840             : value<BitsY> eq_ss(const value<BitsA> &a, const value<BitsB> &b) {
-    1841             :         constexpr size_t BitsExt = max(BitsA, BitsB);
-    1842             :         return value<BitsY>{ a.template sext<BitsExt>() == b.template sext<BitsExt>() ? 1u : 0u };
-    1843             : }
-    1844             : 
-    1845             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1846             : CXXRTL_ALWAYS_INLINE
-    1847             : value<BitsY> ne_uu(const value<BitsA> &a, const value<BitsB> &b) {
-    1848             :         constexpr size_t BitsExt = max(BitsA, BitsB);
-    1849             :         return value<BitsY>{ a.template zext<BitsExt>() != b.template zext<BitsExt>() ? 1u : 0u };
-    1850             : }
-    1851             : 
-    1852             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1853             : CXXRTL_ALWAYS_INLINE
-    1854             : value<BitsY> ne_ss(const value<BitsA> &a, const value<BitsB> &b) {
-    1855             :         constexpr size_t BitsExt = max(BitsA, BitsB);
-    1856             :         return value<BitsY>{ a.template sext<BitsExt>() != b.template sext<BitsExt>() ? 1u : 0u };
-    1857             : }
-    1858             : 
-    1859             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1860             : CXXRTL_ALWAYS_INLINE
-    1861             : value<BitsY> eqx_uu(const value<BitsA> &a, const value<BitsB> &b) {
-    1862             :         return eq_uu<BitsY>(a, b);
-    1863             : }
-    1864             : 
-    1865             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1866             : CXXRTL_ALWAYS_INLINE
-    1867             : value<BitsY> eqx_ss(const value<BitsA> &a, const value<BitsB> &b) {
-    1868             :         return eq_ss<BitsY>(a, b);
-    1869             : }
-    1870             : 
-    1871             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1872             : CXXRTL_ALWAYS_INLINE
-    1873             : value<BitsY> nex_uu(const value<BitsA> &a, const value<BitsB> &b) {
-    1874             :         return ne_uu<BitsY>(a, b);
-    1875             : }
-    1876             : 
-    1877             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1878             : CXXRTL_ALWAYS_INLINE
-    1879             : value<BitsY> nex_ss(const value<BitsA> &a, const value<BitsB> &b) {
-    1880             :         return ne_ss<BitsY>(a, b);
-    1881             : }
-    1882             : 
-    1883             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1884             : CXXRTL_ALWAYS_INLINE
-    1885             : value<BitsY> gt_uu(const value<BitsA> &a, const value<BitsB> &b) {
-    1886             :         constexpr size_t BitsExt = max(BitsA, BitsB);
-    1887             :         return value<BitsY> { b.template zext<BitsExt>().ucmp(a.template zext<BitsExt>()) ? 1u : 0u };
-    1888             : }
-    1889             : 
-    1890             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1891             : CXXRTL_ALWAYS_INLINE
-    1892             : value<BitsY> gt_ss(const value<BitsA> &a, const value<BitsB> &b) {
-    1893             :         constexpr size_t BitsExt = max(BitsA, BitsB);
-    1894             :         return value<BitsY> { b.template sext<BitsExt>().scmp(a.template sext<BitsExt>()) ? 1u : 0u };
-    1895             : }
-    1896             : 
-    1897             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1898             : CXXRTL_ALWAYS_INLINE
-    1899             : value<BitsY> ge_uu(const value<BitsA> &a, const value<BitsB> &b) {
-    1900             :         constexpr size_t BitsExt = max(BitsA, BitsB);
-    1901             :         return value<BitsY> { !a.template zext<BitsExt>().ucmp(b.template zext<BitsExt>()) ? 1u : 0u };
-    1902             : }
-    1903             : 
-    1904             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1905             : CXXRTL_ALWAYS_INLINE
-    1906             : value<BitsY> ge_ss(const value<BitsA> &a, const value<BitsB> &b) {
-    1907             :         constexpr size_t BitsExt = max(BitsA, BitsB);
-    1908             :         return value<BitsY> { !a.template sext<BitsExt>().scmp(b.template sext<BitsExt>()) ? 1u : 0u };
-    1909             : }
-    1910             : 
-    1911             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1912             : CXXRTL_ALWAYS_INLINE
-    1913             : value<BitsY> lt_uu(const value<BitsA> &a, const value<BitsB> &b) {
-    1914             :         constexpr size_t BitsExt = max(BitsA, BitsB);
-    1915             :         return value<BitsY> { a.template zext<BitsExt>().ucmp(b.template zext<BitsExt>()) ? 1u : 0u };
-    1916             : }
-    1917             : 
-    1918             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1919             : CXXRTL_ALWAYS_INLINE
-    1920             : value<BitsY> lt_ss(const value<BitsA> &a, const value<BitsB> &b) {
-    1921             :         constexpr size_t BitsExt = max(BitsA, BitsB);
-    1922             :         return value<BitsY> { a.template sext<BitsExt>().scmp(b.template sext<BitsExt>()) ? 1u : 0u };
-    1923             : }
-    1924             : 
-    1925             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1926             : CXXRTL_ALWAYS_INLINE
-    1927             : value<BitsY> le_uu(const value<BitsA> &a, const value<BitsB> &b) {
-    1928             :         constexpr size_t BitsExt = max(BitsA, BitsB);
-    1929             :         return value<BitsY> { !b.template zext<BitsExt>().ucmp(a.template zext<BitsExt>()) ? 1u : 0u };
-    1930             : }
-    1931             : 
-    1932             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1933             : CXXRTL_ALWAYS_INLINE
-    1934             : value<BitsY> le_ss(const value<BitsA> &a, const value<BitsB> &b) {
-    1935             :         constexpr size_t BitsExt = max(BitsA, BitsB);
-    1936             :         return value<BitsY> { !b.template sext<BitsExt>().scmp(a.template sext<BitsExt>()) ? 1u : 0u };
-    1937             : }
-    1938             : 
-    1939             : // Arithmetic operations
-    1940             : template<size_t BitsY, size_t BitsA>
-    1941             : CXXRTL_ALWAYS_INLINE
-    1942             : value<BitsY> pos_u(const value<BitsA> &a) {
-    1943             :         return a.template zcast<BitsY>();
-    1944             : }
-    1945             : 
-    1946             : template<size_t BitsY, size_t BitsA>
-    1947             : CXXRTL_ALWAYS_INLINE
-    1948             : value<BitsY> pos_s(const value<BitsA> &a) {
-    1949             :         return a.template scast<BitsY>();
-    1950             : }
-    1951             : 
-    1952             : template<size_t BitsY, size_t BitsA>
-    1953             : CXXRTL_ALWAYS_INLINE
-    1954             : value<BitsY> neg_u(const value<BitsA> &a) {
-    1955             :         return a.template zcast<BitsY>().neg();
-    1956             : }
-    1957             : 
-    1958             : template<size_t BitsY, size_t BitsA>
-    1959             : CXXRTL_ALWAYS_INLINE
-    1960             : value<BitsY> neg_s(const value<BitsA> &a) {
-    1961             :         return a.template scast<BitsY>().neg();
-    1962             : }
-    1963             : 
-    1964             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1965             : CXXRTL_ALWAYS_INLINE
-    1966          33 : value<BitsY> add_uu(const value<BitsA> &a, const value<BitsB> &b) {
-    1967          33 :         return a.template zcast<BitsY>().add(b.template zcast<BitsY>());
-    1968             : }
-    1969             : 
-    1970             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1971             : CXXRTL_ALWAYS_INLINE
-    1972             : value<BitsY> add_ss(const value<BitsA> &a, const value<BitsB> &b) {
-    1973             :         return a.template scast<BitsY>().add(b.template scast<BitsY>());
-    1974             : }
-    1975             : 
-    1976             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1977             : CXXRTL_ALWAYS_INLINE
-    1978             : value<BitsY> sub_uu(const value<BitsA> &a, const value<BitsB> &b) {
-    1979             :         return a.template zcast<BitsY>().sub(b.template zcast<BitsY>());
-    1980             : }
-    1981             : 
-    1982             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1983             : CXXRTL_ALWAYS_INLINE
-    1984             : value<BitsY> sub_ss(const value<BitsA> &a, const value<BitsB> &b) {
-    1985             :         return a.template scast<BitsY>().sub(b.template scast<BitsY>());
-    1986             : }
-    1987             : 
-    1988             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1989             : CXXRTL_ALWAYS_INLINE
-    1990             : value<BitsY> mul_uu(const value<BitsA> &a, const value<BitsB> &b) {
-    1991             :         constexpr size_t BitsM = BitsA >= BitsB ? BitsA : BitsB;
-    1992             :         return a.template zcast<BitsM>().template mul<BitsY>(b.template zcast<BitsM>());
-    1993             : }
-    1994             : 
-    1995             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    1996             : CXXRTL_ALWAYS_INLINE
-    1997             : value<BitsY> mul_ss(const value<BitsA> &a, const value<BitsB> &b) {
-    1998             :         return a.template scast<BitsY>().template mul<BitsY>(b.template scast<BitsY>());
-    1999             : }
-    2000             : 
-    2001             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    2002             : CXXRTL_ALWAYS_INLINE
-    2003             : std::pair<value<BitsY>, value<BitsY>> divmod_uu(const value<BitsA> &a, const value<BitsB> &b) {
-    2004             :         constexpr size_t Bits = max(BitsY, max(BitsA, BitsB));
-    2005             :         value<Bits> quotient;
-    2006             :         value<Bits> remainder;
-    2007             :         value<Bits> dividend = a.template zext<Bits>();
-    2008             :         value<Bits> divisor = b.template zext<Bits>();
-    2009             :         std::tie(quotient, remainder) = dividend.udivmod(divisor);
-    2010             :         return {quotient.template trunc<BitsY>(), remainder.template trunc<BitsY>()};
-    2011             : }
-    2012             : 
-    2013             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    2014             : CXXRTL_ALWAYS_INLINE
-    2015             : std::pair<value<BitsY>, value<BitsY>> divmod_ss(const value<BitsA> &a, const value<BitsB> &b) {
-    2016             :         constexpr size_t Bits = max(BitsY, max(BitsA, BitsB));
-    2017             :         value<Bits> quotient;
-    2018             :         value<Bits> remainder;
-    2019             :         value<Bits> dividend = a.template sext<Bits>();
-    2020             :         value<Bits> divisor = b.template sext<Bits>();
-    2021             :         std::tie(quotient, remainder) = dividend.sdivmod(divisor);
-    2022             :         return {quotient.template trunc<BitsY>(), remainder.template trunc<BitsY>()};
-    2023             : }
-    2024             : 
-    2025             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    2026             : CXXRTL_ALWAYS_INLINE
-    2027             : value<BitsY> div_uu(const value<BitsA> &a, const value<BitsB> &b) {
-    2028             :         return divmod_uu<BitsY>(a, b).first;
-    2029             : }
-    2030             : 
-    2031             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    2032             : CXXRTL_ALWAYS_INLINE
-    2033             : value<BitsY> div_ss(const value<BitsA> &a, const value<BitsB> &b) {
-    2034             :         return divmod_ss<BitsY>(a, b).first;
-    2035             : }
-    2036             : 
-    2037             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    2038             : CXXRTL_ALWAYS_INLINE
-    2039             : value<BitsY> mod_uu(const value<BitsA> &a, const value<BitsB> &b) {
-    2040             :         return divmod_uu<BitsY>(a, b).second;
-    2041             : }
-    2042             : 
-    2043             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    2044             : CXXRTL_ALWAYS_INLINE
-    2045             : value<BitsY> mod_ss(const value<BitsA> &a, const value<BitsB> &b) {
-    2046             :         return divmod_ss<BitsY>(a, b).second;
-    2047             : }
-    2048             : 
-    2049             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    2050             : CXXRTL_ALWAYS_INLINE
-    2051             : value<BitsY> modfloor_uu(const value<BitsA> &a, const value<BitsB> &b) {
-    2052             :         return divmod_uu<BitsY>(a, b).second;
-    2053             : }
-    2054             : 
-    2055             : // GHDL Modfloor operator. Returns r=a mod b, such that r has the same sign as b and
-    2056             : // a=b*N+r where N is some integer
-    2057             : // In practical terms, when a and b have different signs and the remainder returned by divmod_ss is not 0
-    2058             : // then return the remainder + b
-    2059             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    2060             : CXXRTL_ALWAYS_INLINE
-    2061             : value<BitsY> modfloor_ss(const value<BitsA> &a, const value<BitsB> &b) {
-    2062             :         value<BitsY> r;
-    2063             :         r = divmod_ss<BitsY>(a, b).second;
-    2064             :         if((b.is_neg() != a.is_neg()) && !r.is_zero())
-    2065             :                 return add_ss<BitsY>(b, r);
-    2066             :         return r;
-    2067             : }
-    2068             : 
-    2069             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    2070             : CXXRTL_ALWAYS_INLINE
-    2071             : value<BitsY> divfloor_uu(const value<BitsA> &a, const value<BitsB> &b) {
-    2072             :         return divmod_uu<BitsY>(a, b).first;
-    2073             : }
-    2074             : 
-    2075             : // Divfloor. Similar to above: returns q=a//b, where q has the sign of a*b and a=b*q+N.
-    2076             : // In other words, returns (truncating) a/b, except if a and b have different signs
-    2077             : // and there's non-zero remainder, subtract one more towards floor.
-    2078             : template<size_t BitsY, size_t BitsA, size_t BitsB>
-    2079             : CXXRTL_ALWAYS_INLINE
-    2080             : value<BitsY> divfloor_ss(const value<BitsA> &a, const value<BitsB> &b) {
-    2081             :         value<BitsY> q, r;
-    2082             :         std::tie(q, r) = divmod_ss<BitsY>(a, b);
-    2083             :         if ((b.is_neg() != a.is_neg()) && !r.is_zero())
-    2084             :                 return sub_uu<BitsY>(q, value<1> { 1u });
-    2085             :         return q;
-    2086             : 
-    2087             : }
-    2088             : 
-    2089             : // Memory helper
-    2090             : struct memory_index {
-    2091             :         bool valid;
-    2092             :         size_t index;
-    2093             : 
-    2094             :         template<size_t BitsAddr>
-    2095             :         memory_index(const value<BitsAddr> &addr, size_t offset, size_t depth) {
-    2096             :                 static_assert(value<BitsAddr>::chunks <= 1, "memory address is too wide");
-    2097             :                 size_t offset_index = addr.data[0];
-    2098             : 
-    2099             :                 valid = (offset_index >= offset && offset_index < offset + depth);
-    2100             :                 index = offset_index - offset;
-    2101             :         }
-    2102             : };
-    2103             : 
-    2104             : } // namespace cxxrtl_yosys
-    2105             : 
-    2106             : #endif
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Function Name Sort by function nameHit count Sort by hit count
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LCOV - code coverage report
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Current view:top level - home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl - cxxrtl_vcd.h (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:11216070.0 %
Date:1980-01-01 00:00:00Functions:151693.8 %
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Function Name Sort by function nameHit count Sort by hit count
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LCOV - code coverage report
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Current view:top level - home/roland/my_yosys/backends/cxxrtl/runtime/cxxrtl - cxxrtl_vcd.h (source / functions)HitTotalCoverage
Test:vcd_harness.infoLines:11216070.0 %
Date:1980-01-01 00:00:00Functions:151693.8 %
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          Line data    Source code
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-       1             : /*
-       2             :  *  yosys -- Yosys Open SYnthesis Suite
-       3             :  *
-       4             :  *  Copyright (C) 2020  whitequark <whitequark@whitequark.org>
-       5             :  *
-       6             :  *  Permission to use, copy, modify, and/or distribute this software for any
-       7             :  *  purpose with or without fee is hereby granted.
-       8             :  *
-       9             :  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-      10             :  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-      11             :  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-      12             :  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-      13             :  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-      14             :  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-      15             :  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-      16             :  *
-      17             :  */
-      18             : 
-      19             : #ifndef CXXRTL_VCD_H
-      20             : #define CXXRTL_VCD_H
-      21             : 
-      22             : #include <cxxrtl/cxxrtl.h>
-      23             : 
-      24             : namespace cxxrtl {
-      25             : 
-      26             : class vcd_writer {
-      27             :         struct variable {
-      28             :                 size_t ident;
-      29             :                 size_t width;
-      30             :                 chunk_t *curr;
-      31             :                 size_t cache_offset;
-      32             :                 debug_outline *outline;
-      33             :                 bool *outline_warm;
-      34             :         };
-      35             : 
-      36             :         std::vector<std::string> current_scope;
-      37             :         std::map<debug_outline*, bool> outlines;
-      38             :         std::vector<variable> variables;
-      39             :         std::vector<chunk_t> cache;
-      40             :         std::map<chunk_t*, size_t> aliases;
-      41             :         bool streaming = false;
-      42             : 
-      43           3 :         void emit_timescale(unsigned number, const std::string &unit) {
-      44           3 :                 assert(!streaming);
-      45           3 :                 assert(number == 1 || number == 10 || number == 100);
-      46           3 :                 assert(unit == "s" || unit == "ms" || unit == "us" ||
-      47             :                        unit == "ns" || unit == "ps" || unit == "fs");
-      48          12 :                 buffer += "$timescale " + std::to_string(number) + " " + unit + " $end\n";
-      49           3 :         }
-      50             : 
-      51          12 :         void emit_scope(const std::vector<std::string> &scope) {
-      52          12 :                 assert(!streaming);
-      53          12 :                 while (current_scope.size() > scope.size() ||
-      54          12 :                        (current_scope.size() > 0 &&
-      55           0 :                         current_scope[current_scope.size() - 1] != scope[current_scope.size() - 1])) {
-      56           0 :                         buffer += "$upscope $end\n";
-      57           0 :                         current_scope.pop_back();
-      58             :                 }
-      59          12 :                 while (current_scope.size() < scope.size()) {
-      60           0 :                         buffer += "$scope module " + scope[current_scope.size()] + " $end\n";
-      61           0 :                         current_scope.push_back(scope[current_scope.size()]);
-      62             :                 }
-      63          12 :         }
-      64             : 
-      65          60 :         void emit_ident(size_t ident) {
-      66          60 :                 do {
-      67          60 :                         buffer += '!' + ident % 94; // "base94"
-      68          60 :                         ident /= 94;
-      69          60 :                 } while (ident != 0);
-      70          60 :         }
-      71             : 
-      72           9 :         void emit_name(const std::string &name) {
-      73          24 :                 for (char c : name) {
-      74          15 :                         if (c == ':') {
-      75             :                                 // Due to a bug, GTKWave cannot parse a colon in the variable name, causing the VCD file
-      76             :                                 // to be unreadable. It cannot be escaped either, so replace it with the sideways colon.
-      77           0 :                                 buffer += "..";
-      78             :                         } else {
-      79          30 :                                 buffer += c;
-      80             :                         }
-      81             :                 }
-      82           9 :         }
-      83             : 
-      84           9 :         void emit_var(const variable &var, const std::string &type, const std::string &name,
-      85             :                       size_t lsb_at, bool multipart) {
-      86           9 :                 assert(!streaming);
-      87          36 :                 buffer += "$var " + type + " " + std::to_string(var.width) + " ";
-      88           9 :                 emit_ident(var.ident);
-      89           9 :                 buffer += " ";
-      90           9 :                 emit_name(name);
-      91           9 :                 if (multipart || name.back() == ']' || lsb_at != 0) {
-      92           0 :                         if (var.width == 1)
-      93           0 :                                 buffer += " [" + std::to_string(lsb_at) + "]";
-      94             :                         else
-      95           0 :                                 buffer += " [" + std::to_string(lsb_at + var.width - 1) + ":" + std::to_string(lsb_at) + "]";
-      96             :                 }
-      97           9 :                 buffer += " $end\n";
-      98           9 :         }
-      99             : 
-     100           3 :         void emit_enddefinitions() {
-     101           3 :                 assert(!streaming);
-     102           3 :                 buffer += "$enddefinitions $end\n";
-     103           3 :                 streaming = true;
-     104           3 :         }
-     105             : 
-     106          33 :         void emit_time(uint64_t timestamp) {
-     107          33 :                 assert(streaming);
-     108          99 :                 buffer += "#" + std::to_string(timestamp) + "\n";
-     109          33 :         }
-     110             : 
-     111          51 :         void emit_scalar(const variable &var) {
-     112          51 :                 assert(streaming);
-     113          51 :                 assert(var.width == 1);
-     114          78 :                 buffer += (*var.curr ? '1' : '0');
-     115          51 :                 emit_ident(var.ident);
-     116          51 :                 buffer += '\n';
-     117          51 :         }
-     118             : 
-     119           0 :         void emit_vector(const variable &var) {
-     120           0 :                 assert(streaming);
-     121           0 :                 buffer += 'b';
-     122           0 :                 for (size_t bit = var.width - 1; bit != (size_t)-1; bit--) {
-     123           0 :                         bool bit_curr = var.curr[bit / (8 * sizeof(chunk_t))] & (1 << (bit % (8 * sizeof(chunk_t))));
-     124           0 :                         buffer += (bit_curr ? '1' : '0');
-     125             :                 }
-     126           0 :                 buffer += ' ';
-     127           0 :                 emit_ident(var.ident);
-     128           0 :                 buffer += '\n';
-     129           0 :         }
-     130             : 
-     131          33 :         void reset_outlines() {
-     132          66 :                 for (auto &outline_it : outlines)
-     133          33 :                         outline_it.second = /*warm=*/(outline_it.first == nullptr);
-     134          33 :         }
-     135             : 
-     136           9 :         variable &register_variable(size_t width, chunk_t *curr, bool constant = false, debug_outline *outline = nullptr) {
-     137           9 :                 if (aliases.count(curr)) {
-     138           0 :                         return variables[aliases[curr]];
-     139             :                 } else {
-     140           9 :                         auto outline_it = outlines.emplace(outline, /*warm=*/(outline == nullptr)).first;
-     141           9 :                         const size_t chunks = (width + (sizeof(chunk_t) * 8 - 1)) / (sizeof(chunk_t) * 8);
-     142           9 :                         aliases[curr] = variables.size();
-     143           9 :                         if (constant) {
-     144           0 :                                 variables.emplace_back(variable { variables.size(), width, curr, (size_t)-1, outline_it->first, &outline_it->second });
-     145             :                         } else {
-     146           9 :                                 variables.emplace_back(variable { variables.size(), width, curr, cache.size(), outline_it->first, &outline_it->second });
-     147           9 :                                 cache.insert(cache.end(), &curr[0], &curr[chunks]);
-     148             :                         }
-     149           9 :                         return variables.back();
-     150             :                 }
-     151             :         }
-     152             : 
-     153          99 :         bool test_variable(const variable &var) {
-     154          99 :                 if (var.cache_offset == (size_t)-1)
-     155             :                         return false; // constant
-     156          99 :                 if (!*var.outline_warm) {
-     157           0 :                         var.outline->eval();
-     158           0 :                         *var.outline_warm = true;
-     159             :                 }
-     160          99 :                 const size_t chunks = (var.width + (sizeof(chunk_t) * 8 - 1)) / (sizeof(chunk_t) * 8);
-     161          99 :                 if (std::equal(&var.curr[0], &var.curr[chunks], &cache[var.cache_offset])) {
-     162             :                         return false;
-     163             :                 } else {
-     164          42 :                         std::copy(&var.curr[0], &var.curr[chunks], &cache[var.cache_offset]);
-     165          42 :                         return true;
-     166             :                 }
-     167             :         }
-     168             : 
-     169           9 :         static std::vector<std::string> split_hierarchy(const std::string &hier_name) {
-     170           9 :                 std::vector<std::string> hierarchy;
-     171           9 :                 size_t prev = 0;
-     172           9 :                 while (true) {
-     173           9 :                         size_t curr = hier_name.find_first_of(' ', prev);
-     174           9 :                         if (curr == std::string::npos) {
-     175          18 :                                 hierarchy.push_back(hier_name.substr(prev));
-     176           9 :                                 break;
-     177             :                         } else {
-     178           0 :                                 hierarchy.push_back(hier_name.substr(prev, curr - prev));
-     179           0 :                                 prev = curr + 1;
-     180             :                         }
-     181           0 :                 }
-     182           9 :                 return hierarchy;
-     183           0 :         }
-     184             : 
-     185             : public:
-     186             :         std::string buffer;
-     187             : 
-     188           3 :         void timescale(unsigned number, const std::string &unit) {
-     189           3 :                 emit_timescale(number, unit);
-     190           3 :         }
-     191             : 
-     192           9 :         void add(const std::string &hier_name, const debug_item &item, bool multipart = false) {
-     193           9 :                 std::vector<std::string> scope = split_hierarchy(hier_name);
-     194           9 :                 std::string name = scope.back();
-     195           9 :                 scope.pop_back();
-     196             : 
-     197           9 :                 emit_scope(scope);
-     198           9 :                 switch (item.type) {
-     199             :                         // Not the best naming but oh well...
-     200           9 :                         case debug_item::VALUE:
-     201          18 :                                 emit_var(register_variable(item.width, item.curr, /*constant=*/item.next == nullptr),
-     202           9 :                                          "wire", name, item.lsb_at, multipart);
-     203           9 :                                 break;
-     204           0 :                         case debug_item::WIRE:
-     205           0 :                                 emit_var(register_variable(item.width, item.curr),
-     206           0 :                                          "reg", name, item.lsb_at, multipart);
-     207           0 :                                 break;
-     208           0 :                         case debug_item::MEMORY: {
-     209           0 :                                 const size_t stride = (item.width + (sizeof(chunk_t) * 8 - 1)) / (sizeof(chunk_t) * 8);
-     210           0 :                                 for (size_t index = 0; index < item.depth; index++) {
-     211           0 :                                         chunk_t *nth_curr = &item.curr[stride * index];
-     212           0 :                                         std::string nth_name = name + '[' + std::to_string(index) + ']';
-     213           0 :                                         emit_var(register_variable(item.width, nth_curr),
-     214           0 :                                                  "reg", nth_name, item.lsb_at, multipart);
-     215           0 :                                 }
-     216             :                                 break;
-     217             :                         }
-     218           0 :                         case debug_item::ALIAS:
-     219             :                                 // Like VALUE, but, even though `item.next == nullptr` always holds, the underlying value
-     220             :                                 // can actually change, and must be tracked. In most cases the VCD identifier will be
-     221             :                                 // unified with the aliased reg, but we should handle the case where only the alias is
-     222             :                                 // added to the VCD writer, too.
-     223           0 :                                 emit_var(register_variable(item.width, item.curr),
-     224           0 :                                          "wire", name, item.lsb_at, multipart);
-     225           0 :                                 break;
-     226           0 :                         case debug_item::OUTLINE:
-     227           0 :                                 emit_var(register_variable(item.width, item.curr, /*constant=*/false, item.outline),
-     228           0 :                                          "wire", name, item.lsb_at, multipart);
-     229           0 :                                 break;
-     230             :                 }
-     231           9 :         }
-     232             : 
-     233             :         template<class Filter>
-     234           3 :         void add(const debug_items &items, const Filter &filter) {
-     235             :                 // `debug_items` is a map, so the items are already sorted in an order optimal for emitting
-     236             :                 // VCD scope sections.
-     237          12 :                 for (auto &it : items.table)
-     238          18 :                         for (auto &part : it.second)
-     239           9 :                                 if (filter(it.first, part))
-     240           9 :                                         add(it.first, part, it.second.size() > 1);
-     241           3 :         }
-     242             : 
-     243             :         void add(const debug_items &items) {
-     244             :                 this->add(items, [](const std::string &, const debug_item &) {
-     245             :                         return true;
-     246             :                 });
-     247             :         }
-     248             : 
-     249           3 :         void add_without_memories(const debug_items &items) {
-     250           3 :                 this->add(items, [](const std::string &, const debug_item &item) {
-     251           9 :                         return item.type != debug_item::MEMORY;
-     252             :                 });
-     253             :         }
-     254             : 
-     255          33 :         void sample(uint64_t timestamp) {
-     256          33 :                 bool first_sample = !streaming;
-     257          33 :                 if (first_sample) {
-     258           3 :                         emit_scope({});
-     259           3 :                         emit_enddefinitions();
-     260             :                 }
-     261          33 :                 reset_outlines();
-     262          33 :                 emit_time(timestamp);
-     263         132 :                 for (auto var : variables)
-     264          99 :                         if (test_variable(var) || first_sample) {
-     265          51 :                                 if (var.width == 1)
-     266          51 :                                         emit_scalar(var);
-     267             :                                 else
-     268           0 :                                         emit_vector(var);
-     269             :                         }
-     270          33 :         }
-     271             : };
-     272             : 
-     273             : }
-     274             : 
-     275             : #endif
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          Line data    Source code
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-       1             : /*
-       2             :  *  yosys -- Yosys Open SYnthesis Suite
-       3             :  *
-       4             :  *  Copyright (C) 2024  Emily Schmidt <emily@yosyshq.com>
-       5             :  *
-       6             :  *  Permission to use, copy, modify, and/or distribute this software for any
-       7             :  *  purpose with or without fee is hereby granted, provided that the above
-       8             :  *  copyright notice and this permission notice appear in all copies.
-       9             :  *
-      10             :  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-      11             :  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-      12             :  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-      13             :  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-      14             :  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-      15             :  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-      16             :  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-      17             :  *
-      18             :  */
-      19             : 
-      20             : #ifndef SIM_H
-      21             : #define SIM_H
-      22             : 
-      23             : #include <array>
-      24             : #include <cstdint>
-      25             : #include <cassert>
-      26             : 
-      27             : template<size_t n>
-      28             : using Signal = std::array<bool, n>;
-      29             : 
-      30             : template<size_t n, size_t m>
-      31             : Signal<n> slice(Signal<m> const& a, size_t offset)
-      32             : {
-      33             :     Signal<n> ret;
-      34             : 
-      35             :     std::copy(a.begin() + offset, a.begin() + offset + n, ret.begin());
-      36             :     return ret;
-      37             : }
-      38             : 
-      39             : template<size_t n>
-      40          30 : Signal<n> $const(uint32_t val)
-      41             : {
-      42             :     size_t i;
-      43             :     Signal<n> ret;
-      44             : 
-      45          30 :     for(i = 0; i < n; i++)
-      46             :         if(i < 32)
-      47          33 :             ret[i] = val & (1<<i);
-      48             :         else
-      49             :             ret[i] = false;
-      50             :     return ret;
-      51             : }
-      52             : 
-      53             : template<size_t n>
-      54             : Signal<n> $const(std::initializer_list<uint32_t> vals)
-      55             : {
-      56             :     size_t k, i;
-      57             :     Signal<n> ret;
-      58             : 
-      59             :     k = 0;
-      60             :     for (auto val : vals) {
-      61             :         for(i = 0; i < 32; i++)
-      62             :             if(i + k < n)
-      63             :                 ret[i + k] = val & (1<<i);
-      64             :         k += 32;
-      65             :     }
-      66             :     for(; k < n; k++)
-      67             :         ret[k] = false;
-      68             :     return ret;
-      69             : }
-      70             : 
-      71             : template<size_t n>
-      72             : bool as_bool(Signal<n> sig)
-      73             : {
-      74             :     for(int i = 0; i < n; i++)
-      75             :         if(sig[i])
-      76             :             return true;
-      77             :     return false;
-      78             : }
-      79             : 
-      80             : template<size_t n>
-      81             : uint32_t as_int(Signal<n> sig)
-      82             : {
-      83             :     uint32_t ret = 0;
-      84             :     for(int i = 0; i < n; i++)
-      85             :         if(sig[i] && i < 32)
-      86             :             ret |= 1<<i;
-      87             :     return ret;
-      88             : }
-      89             : 
-      90             : template<size_t n>
-      91             : Signal<n> $mux(Signal<n> const& a, Signal<n> const &b, Signal<1> const &s)
-      92             : {
-      93             :     return s[0] ? b : a;
-      94             : }
-      95             : 
-      96             : template<size_t n>
-      97             : Signal<n> $not(Signal<n> const& a)
-      98             : {
-      99             :     Signal<n> ret;
-     100             :     for(size_t i = 0; i < n; i++)
-     101             :         ret[i] = !a[i];
-     102             :     return ret;
-     103             : }
-     104             : 
-     105             : template<size_t n>
-     106             : Signal<n> $neg(Signal<n> const& a)
-     107             : {
-     108             :     Signal<n> ret;
-     109             :     bool carry = true;
-     110             :     for(size_t i = 0; i < n; i++) {
-     111             :         int r = !a[i] + carry;
-     112             :         ret[i] = (r & 1) != 0;
-     113             :         carry = (r >> 1) != 0;
-     114             :     }
-     115             :     return ret;
-     116             : }
-     117             : 
-     118             : template<size_t n>
-     119             : Signal<1> $reduce_or(Signal<n> const& a)
-     120             : {
-     121             :     return { as_bool(a) };
-     122             : }
-     123             : 
-     124             : template<size_t n>
-     125             : Signal<1> $reduce_and(Signal<n> const& a)
-     126             : {
-     127             :     for(size_t i = 0; i < n; i++)
-     128             :         if(!a[i])
-     129             :             return { false };
-     130             :     return { true };
-     131             : }
-     132             : 
-     133             : template<size_t n>
-     134             : Signal<1> $reduce_bool(Signal<n> const& a)
-     135             : {
-     136             :     return { as_bool(a) };
-     137             : }
-     138             : 
-     139             : template<size_t n>
-     140             : Signal<1> $logic_and(Signal<n> const& a, Signal<n> const& b)
-     141             : {
-     142             :     return { as_bool(a) && as_bool(b) };
-     143             : }
-     144             : 
-     145             : template<size_t n>
-     146             : Signal<1> $logic_or(Signal<n> const& a, Signal<n> const& b)
-     147             : {
-     148             :     return { as_bool(a) || as_bool(b) };
-     149             : }
-     150             : 
-     151             : template<size_t n>
-     152             : Signal<1> $logic_not(Signal<n> const& a)
-     153             : {
-     154             :     return { !as_bool(a) };
-     155             : }
-     156             : 
-     157             : template<size_t n>
-     158          30 : Signal<n> $add(Signal<n> const& a, Signal<n> const &b)
-     159             : {
-     160             :     Signal<n> ret;
-     161             :     size_t i;
-     162             :     int x = 0;
-     163          30 :     for(i = 0; i < n; i++){
-     164          30 :         x += (int)a[i] + (int)b[i];
-     165          30 :         ret[i] = x & 1;
-     166          30 :         x >>= 1;
-     167             :     }
-     168             :     return ret;
-     169             : }
-     170             : template<size_t n>
-     171             : Signal<n> $sub(Signal<n> const& a, Signal<n> const &b)
-     172             : {
-     173             :     Signal<n> ret;
-     174             :     int x = 1;
-     175             :     for(size_t i = 0; i < n; i++){
-     176             :         x += (int)a[i] + (int)!b[i];
-     177             :         ret[i] = x & 1;
-     178             :         x >>= 1;
-     179             :     }
-     180             :     return ret;
-     181             : }
-     182             : 
-     183             : template<size_t n>
-     184             : Signal<1> $uge(Signal<n> const& a, Signal<n> const &b)
-     185             : {
-     186             :     for(size_t i = n; i-- != 0; )
-     187             :         if(a[i] != b[i])
-     188             :             return { a[i] };
-     189             :     return { true };
-     190             : }
-     191             : 
-     192             : template<size_t n>
-     193             : Signal<1> $ugt(Signal<n> const& a, Signal<n> const &b)
-     194             : {
-     195             :     for(size_t i = n; i-- != 0; )
-     196             :         if(a[i] != b[i])
-     197             :             return { a[i] };
-     198             :     return { false };
-     199             : }
-     200             : 
-     201             : template<size_t n>
-     202             : Signal<1> $ge(Signal<n> const& a, Signal<n> const &b)
-     203             : {
-     204             :     if(a[n-1] != b[n-1])
-     205             :         return { b[n-1] };
-     206             :     return $uge(a, b);
-     207             : }
-     208             : 
-     209             : template<size_t n>
-     210             : Signal<1> $gt(Signal<n> const& a, Signal<n> const &b)
-     211             : {
-     212             :     if(a[n-1] != b[n-1])
-     213             :         return { b[n-1] };
-     214             :     return $ugt(a, b);
-     215             : }
-     216             : 
-     217             : template<size_t n> Signal<1> $ule(Signal<n> const& a, Signal<n> const &b) { return $uge(b, a); }
-     218             : template<size_t n> Signal<1> $ult(Signal<n> const& a, Signal<n> const &b) { return $ugt(b, a); }
-     219             : template<size_t n> Signal<1> $le(Signal<n> const& a, Signal<n> const &b) { return $ge(b, a); }
-     220             : template<size_t n> Signal<1> $lt(Signal<n> const& a, Signal<n> const &b) { return $gt(b, a); }
-     221             : 
-     222             : template<size_t n>
-     223             : Signal<n> $and(Signal<n> const& a, Signal<n> const &b)
-     224             : {
-     225             :     Signal<n> ret;
-     226             :     for(size_t i = 0; i < n; i++)
-     227             :         ret[i] = a[i] && b[i];
-     228             :     return ret;
-     229             : }
-     230             : 
-     231             : template<size_t n>
-     232             : Signal<n> $or(Signal<n> const& a, Signal<n> const &b)
-     233             : {
-     234             :     Signal<n> ret;
-     235             :     for(size_t i = 0; i < n; i++)
-     236             :         ret[i] = a[i] || b[i];
-     237             :     return ret;
-     238             : }
-     239             : 
-     240             : template<size_t n>
-     241             : Signal<n> $xor(Signal<n> const& a, Signal<n> const &b)
-     242             : {
-     243             :     Signal<n> ret;
-     244             :     for(size_t i = 0; i < n; i++)
-     245             :         ret[i] = a[i] != b[i];
-     246             :     return ret;
-     247             : }
-     248             : 
-     249             : template<size_t n, size_t na, size_t nb>
-     250             : Signal<n> $shl(Signal<na> const& a, Signal<nb> const &b)
-     251             : {
-     252             :     if(nb >= sizeof(int) * 8 - 1)
-     253             :         for(size_t i = sizeof(int) * 8 - 1; i < nb; i++)
-     254             :             assert(!b[i]);
-     255             :     size_t amount = as_int(b);
-     256             :     Signal<n> ret = $const<n>(0);
-     257             :     if(amount < n){
-     258             :         if(amount + na > n)
-     259             :             std::copy(a.begin(), a.begin() + (n - amount), ret.begin() + amount);
-     260             :         else
-     261             :             std::copy(a.begin(), a.end(), ret.begin() + amount);
-     262             :     }
-     263             :     return ret;
-     264             : }
-     265             : 
-     266             : template<size_t n, size_t nb>
-     267             : Signal<n> $shr(Signal<n> const& a, Signal<nb> const &b)
-     268             : {
-     269             :     if(nb >= sizeof(int) * 8 - 1)
-     270             :         for(size_t i = sizeof(int) * 8 - 1; i < nb; i++)
-     271             :             assert(!b[i]);
-     272             :     size_t amount = as_int(b);
-     273             :     Signal<n> ret;
-     274             :     for (size_t i = 0; i < n; i++) {
-     275             :         if(i + amount < n)
-     276             :             ret[i] = a[i + amount];
-     277             :         else
-     278             :             ret[i] = false;
-     279             :     }
-     280             :     return ret;
-     281             : }
-     282             : 
-     283             : template<size_t n, size_t nb>
-     284             : Signal<n> $asr(Signal<n> const& a, Signal<nb> const &b)
-     285             : {
-     286             :     if(nb >= sizeof(int) * 8 - 1)
-     287             :         for(size_t i = sizeof(int) * 8 - 1; i < nb; i++)
-     288             :             assert(!b[i]);
-     289             :     size_t amount = as_int(b);
-     290             :     Signal<n> ret;
-     291             :     for (size_t i = 0; i < n; i++) {
-     292             :         if(i + amount < n)
-     293             :             ret[i] = a[i + amount];
-     294             :         else
-     295             :             ret[i] = a[n - 1];
-     296             :     }
-     297             :     return ret;
-     298             : }
-     299             : 
-     300             : template<size_t n>
-     301             : Signal<1> $eq(Signal<n> const& a, Signal<n> const &b)
-     302             : {
-     303             :     for(size_t i = 0; i < n; i++)
-     304             :         if(a[i] != b[i])
-     305             :             return { false };
-     306             :     return { true };
-     307             : }
-     308             : 
-     309             : template<size_t n>
-     310             : Signal<1> $ne(Signal<n> const& a, Signal<n> const &b)
-     311             : {
-     312             :     for(size_t i = 0; i < n; i++)
-     313             :         if(a[i] != b[i])
-     314             :             return { true };
-     315             :     return { false };
-     316             : }
-     317             : 
-     318             : template<size_t n, size_t ns>
-     319             : Signal<n> $pmux(Signal<n> const& a, Signal<n*ns> const &b, Signal<ns> const &s)
-     320             : {
-     321             :     bool found;
-     322             :     Signal<n> ret;
-     323             : 
-     324             :     found = false;
-     325             :     ret = a;
-     326             :     for(size_t i = 0; i < ns; i++){
-     327             :         if(s[i]){
-     328             :             if(found)
-     329             :                 return $const<n>(0);
-     330             :             found = true;
-     331             :             ret = slice<n>(b, n * i);
-     332             :         }
-     333             :     }
-     334             :     return ret;
-     335             : }
-     336             : 
-     337             : template<size_t n, size_t m>
-     338             : Signal<n+m> concat(Signal<n> const& a, Signal<m> const& b)
-     339             : {
-     340             :     Signal<n + m> ret;
-     341             :     std::copy(a.begin(), a.end(), ret.begin());
-     342             :     std::copy(b.begin(), b.end(), ret.begin() + n);
-     343             :     return ret;
-     344             : }
-     345             : 
-     346             : template<size_t n, size_t m>
-     347             : Signal<n> $zero_extend(Signal<m> const& a)
-     348             : {
-     349             :     assert(n >= m);
-     350             :     Signal<n> ret;
-     351             :     std::copy(a.begin(), a.end(), ret.begin());
-     352             :     for(size_t i = m; i < n; i++)
-     353             :         ret[i] = false;
-     354             :     return ret;
-     355             : }
-     356             : 
-     357             : template<size_t n, size_t m>
-     358             : Signal<n> $sign_extend(Signal<m> const& a)
-     359             : {
-     360             :     assert(n >= m);
-     361             :     Signal<n> ret;
-     362             :     std::copy(a.begin(), a.end(), ret.begin());
-     363             :     for(size_t i = m; i < n; i++)
-     364             :         ret[i] = a[m-1];
-     365             :     return ret;
-     366             : }
-     367             : 
-     368             : #endif
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cxxrtl_design_create0
_ZN13cxxrtl_design7p_Adder10debug_infoEPN6cxxrtl11debug_itemsEPNS1_12debug_scopesENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEOSt3mapISB_NS1_8metadataESt4lessISB_ESaISt4pairIKSB_SD_EEE3
_ZN13cxxrtl_design7p_Adder5resetEv3
_ZN13cxxrtl_design7p_AdderC2Ev3
_ZN13cxxrtl_design7p_Adder4evalEPN6cxxrtl9performerE33
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_ZN13cxxrtl_design7p_Adder10debug_evalEv0
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_ZN13cxxrtl_design7p_Adder4evalEPN6cxxrtl9performerE33
_ZN13cxxrtl_design7p_Adder5resetEv3
_ZN13cxxrtl_design7p_Adder6commitEv33
_ZN13cxxrtl_design7p_AdderC2Ev3
cxxrtl_design_create0
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-       1             : #include <cxxrtl/cxxrtl.h>
-       2             : 
-       3             : #if defined(CXXRTL_INCLUDE_CAPI_IMPL) || \
-       4             :     defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)
-       5             : #include <cxxrtl/capi/cxxrtl_capi.cc>
-       6             : #endif
-       7             : 
-       8             : #if defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)
-       9             : #include <cxxrtl/capi/cxxrtl_capi_vcd.cc>
-      10             : #endif
-      11             : 
-      12             : using namespace cxxrtl_yosys;
-      13             : 
-      14             : namespace cxxrtl_design {
-      15             : 
-      16             : // \top: 1
-      17             : // \src: verilog/and.v:1.1-9.10
-      18           3 : struct p_Adder : public module {
-      19             :         // \src: verilog/and.v:4.14-4.17
-      20             :         /*output*/ value<1> p_sum;
-      21             :         // \src: verilog/and.v:3.14-3.15
-      22             :         /*input*/ value<1> p_b;
-      23             :         // \src: verilog/and.v:2.14-2.15
-      24             :         /*input*/ value<1> p_a;
-      25             :         p_Adder(interior) {}
-      26           3 :         p_Adder() {
-      27           3 :                 reset();
-      28           3 :         };
-      29             : 
-      30             :         void reset() override;
-      31             : 
-      32             :         bool eval(performer *performer = nullptr) override;
-      33             : 
-      34             :         template<class ObserverT>
-      35             :         bool commit(ObserverT &observer) {
-      36          33 :                 bool changed = false;
-      37             :                 return changed;
-      38             :         }
-      39             : 
-      40          33 :         bool commit() override {
-      41          33 :                 observer observer;
-      42          33 :                 return commit<>(observer);
-      43             :         }
-      44             : 
-      45             :         void debug_eval();
-      46             : 
-      47             :         void debug_info(debug_items *items, debug_scopes *scopes, std::string path, metadata_map &&cell_attrs = {}) override;
-      48             : }; // struct p_Adder
-      49             : 
-      50           3 : void p_Adder::reset() {
-      51           3 : }
-      52             : 
-      53          33 : bool p_Adder::eval(performer *performer) {
-      54          33 :         bool converged = true;
-      55             :         // \src: verilog/and.v:7.17-7.22
-      56             :         // cell $add$verilog/and.v:7$1
-      57          33 :         p_sum = add_uu<1>(p_a, p_b);
-      58          33 :         return converged;
-      59             : }
-      60             : 
-      61           0 : void p_Adder::debug_eval() {
-      62           0 : }
-      63             : 
-      64             : CXXRTL_EXTREMELY_COLD
-      65           3 : void p_Adder::debug_info(debug_items *items, debug_scopes *scopes, std::string path, metadata_map &&cell_attrs) {
-      66           3 :         assert(path.empty() || path[path.size() - 1] == ' ');
-      67           3 :         if (scopes) {
-      68           0 :                 scopes->add(path.empty() ? path : path.substr(0, path.size() - 1), "Adder", metadata_map({
-      69           0 :                         { "top", UINT64_C(1) },
-      70             :                         { "src", "verilog/and.v:1.1-9.10" },
-      71           0 :                 }), std::move(cell_attrs));
-      72             :         }
-      73           3 :         if (items) {
-      74           3 :                 items->add(path, "sum", "src\000sverilog/and.v:4.14-4.17\000", p_sum, 0, debug_item::OUTPUT|debug_item::DRIVEN_COMB);
-      75           3 :                 items->add(path, "b", "src\000sverilog/and.v:3.14-3.15\000", p_b, 0, debug_item::INPUT|debug_item::UNDRIVEN);
-      76           3 :                 items->add(path, "a", "src\000sverilog/and.v:2.14-2.15\000", p_a, 0, debug_item::INPUT|debug_item::UNDRIVEN);
-      77             :         }
-      78           3 : }
-      79             : 
-      80             : } // namespace cxxrtl_design
-      81             : 
-      82             : extern "C"
-      83           0 : cxxrtl_toplevel cxxrtl_design_create() {
-      84           0 :         return new _cxxrtl_toplevel { std::unique_ptr<cxxrtl_design::p_Adder>(new cxxrtl_design::p_Adder) };
-      85             : }
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_ZN12Adder_Inputs4dumpI10DumpHeaderEEvRT_3
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_ZN12Adder_Inputs4dumpI4DumpEEvRT_33
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-       1             : #include "sim.h"
-       2             : struct Adder_Inputs {
-       3             :         Signal<1> b;
-       4             :         Signal<1> a;
-       5             : 
-       6          36 :         template <typename T> void dump(T &out) {
-       7          36 :                 out("b", b);
-       8          36 :                 out("a", a);
-       9          36 :         }
-      10             : };
-      11             : 
-      12             : struct Adder_Outputs {
-      13             :         Signal<1> sum;
-      14             : 
-      15          36 :         template <typename T> void dump(T &out) {
-      16          36 :                 out("sum", sum);
-      17          36 :         }
-      18             : };
-      19             : 
-      20             : struct Adder_State {
-      21             : 
-      22             :         template <typename T> void dump(T &out) {
-      23             :         }
-      24             : };
-      25             : 
-      26          30 : void Adder(Adder_Inputs const &input, Adder_Outputs &output, Adder_State const &current_state, Adder_State &next_state)
-      27             : {
-      28          30 :         Signal<1> b = input.b;
-      29          30 :         Signal<1> a = input.a;
-      30          30 :         Signal<1> $add$verilog_and_v_7$1$_Y = $add(a, b); //
-      31          30 :         output.sum = $add$verilog_and_v_7$1$_Y;
-      32          30 : }
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Date:1980-01-01 00:00:00Functions:33100.0 %
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main3
_ZN10DumpHeaderclILm1EEEvPKcSt5arrayIbXT_EE9
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LCOV - code coverage report
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Current view:top level - home/roland/my_yosys/tests/functional - vcd_harness.cpp (source / functions)HitTotalCoverage
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_ZN10DumpHeaderclILm1EEEvPKcSt5arrayIbXT_EE9
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main3
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Current view:top level - home/roland/my_yosys/tests/functional - vcd_harness.cpp (source / functions)HitTotalCoverage
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-       1             : #include <cstdio>
-       2             : #include <iostream>
-       3             : #include <fstream>
-       4             : #include <random>
-       5             : 
-       6             : #include <cxxrtl/cxxrtl_vcd.h>
-       7             : 
-       8             : #include "and_cxxrtl.cc"
-       9             : #include "and_functional_cxx.cc"
-      10             : 
-      11             : struct DumpHeader {
-      12             :     std::ofstream &ofs;
-      13           3 :     DumpHeader(std::ofstream &ofs) : ofs(ofs) {}
-      14             :     template <size_t n>
-      15           9 :     void operator()(const char *name, Signal<n> value) {
-      16           9 :         ofs << "$var wire " << n << " " << name[0] << " " << name << " $end\n";
-      17           9 :     }
-      18             : };
-      19             : 
-      20             : struct Dump {
-      21             :     std::ofstream &ofs;
-      22          33 :     Dump(std::ofstream &ofs) : ofs(ofs) {}
-      23             :     template <size_t n>
-      24          99 :     void operator()(const char *name, Signal<n> value) {
-      25             :         // Bit
-      26             :         if (n == 1) {
-      27         156 :             ofs << (value[0] ? '1' : '0');
-      28          99 :             ofs << name[0] << "\n";
-      29             :             return;
-      30             :         }
-      31             :         // vector (multi-bit) signals
-      32             :         ofs << "b";
-      33             :         for (size_t i = n; i-- > 0;)
-      34             :             ofs << (value[i] ? '1' : '0');
-      35             :         ofs << " " << name[0] << "\n";
-      36             :     }
-      37             : };
-      38             : 
-      39           3 : int main(int argc, char **argv)
-      40             : {
-      41           3 :     constexpr int steps = 10;
-      42           3 :     constexpr int number_timescale = 1;
-      43           3 :     const std::string units_timescale = "us";
-      44           3 :     Adder_Inputs inputs;
-      45           3 :     Adder_Outputs outputs;
-      46           3 :     Adder_State state;
-      47           3 :     Adder_State next_state;
-      48             : 
-      49           3 :     std::ofstream vcd_file("functional_cxx.vcd");
-      50             : 
-      51           3 :     vcd_file << "$timescale " << number_timescale << " " << units_timescale << " $end\n"; //$scope module logic $end\n";
-      52           3 :     {
-      53           3 :         DumpHeader d(vcd_file);
-      54           3 :         inputs.dump(d);
-      55           3 :         outputs.dump(d);
-      56             :         // vcd_file << "$scope module state $end\n";
-      57           3 :         state.dump(d);
-      58             :     }
-      59           3 :     vcd_file << "$enddefinitions $end\n$dumpvars\n";
-      60             : 
-      61           3 :     cxxrtl_design::p_Adder top;
-      62             : 
-      63             :     // debug_items maps the hierarchical names of signals and memories in the design
-      64             :     // to a cxxrtl_object (a value, a wire, or a memory)
-      65           3 :     cxxrtl::debug_items all_debug_items;
-      66           3 :     cxxrtl::debug_scope debug_scope;
-      67             :     // Load the debug items of the top down the whole design hierarchy
-      68           6 :     top.debug_info(&all_debug_items, nullptr, "");
-      69             : 
-      70             :     // vcd_writer is the CXXRTL object that's responsible for creating a string with
-      71             :     // the VCD file contents.
-      72           3 :     cxxrtl::vcd_writer vcd;
-      73           3 :     vcd.timescale(number_timescale, units_timescale);
-      74             : 
-      75             :     // Here we tell the vcd writer to dump all the signals of the design, except for the
-      76             :     // memories, to the VCD file.
-      77             :     //
-      78             :     // It's not necessary to load all debug objects to the VCD. There is, for example,
-      79             :     // a  vcd.add(<debug items>, <filter>)) method which allows creating your custom filter to decide
-      80             :     // what to add and what not.
-      81           3 :     vcd.add_without_memories(all_debug_items);
-      82             : 
-      83           3 :     std::ofstream waves("cxxrtl.vcd");
-      84             : 
-      85           3 :     top.p_a.set<bool>(false);
-      86           3 :     top.p_b.set<bool>(false);
-      87           3 :     top.step();
-      88             : 
-      89             :     // We need to manually tell the VCD writer when to sample and write out the traced items.
-      90             :     // This is only a slight inconvenience and allows for complete flexibility.
-      91             :     // E.g. you could only start waveform tracing when an internal signal has reached some specific
-      92             :     // value etc.
-      93           3 :     vcd.sample(0);
-      94           3 :     vcd_file << "#0\n";
-      95           3 :     inputs.a = $const<1>(false);
-      96           3 :     inputs.b = $const<1>(false);
-      97           3 :     {
-      98           3 :         Dump d(vcd_file);
-      99           3 :         inputs.dump(d);
-     100           3 :         outputs.dump(d);
-     101           3 :         state.dump(d);
-     102             :     }
-     103             : 
-     104             :     // Initialize random number generator
-     105           3 :     std::random_device rd;
-     106           3 :     std::mt19937 gen(rd());
-     107           3 :     std::bernoulli_distribution dist(0.5); // 50% chance for true or false
-     108             :     
-     109          33 :     for (int step = 0; step < steps; ++step) {
-     110          30 :       const bool a_value = dist(gen);
-     111          30 :       const bool b_value = dist(gen);
-     112             : 
-     113             :         // cxxrtl
-     114          30 :         top.p_a.set<bool>(a_value);
-     115          30 :         top.p_b.set<bool>(b_value);
-     116          30 :         top.step();
-     117          30 :         vcd.sample(step + 1);
-     118             : 
-     119          30 :         waves << vcd.buffer;
-     120          30 :         vcd.buffer.clear();
-     121             : 
-     122             :         // Functional backend cxx
-     123          30 :         vcd_file << "#" << (step + 1) << "\n";
-     124          30 :         inputs.a = $const<1>(a_value);
-     125          30 :         inputs.b = $const<1>(b_value);
-     126          30 :         Adder(inputs, outputs, state, next_state);
-     127          30 :         {
-     128          30 :             Dump d(vcd_file);
-     129          30 :             inputs.dump(d);
-     130          30 :             outputs.dump(d);
-     131          30 :             state.dump(d);
-     132             :         }
-     133          30 :         state = next_state;
-     134             :     }
-     135             : 
-     136           3 :     vcd_file.close();
-     137           3 :     waves.close();
-     138             : 
-     139           3 :     return 0;
-     140           3 : }
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Test:vcd_harness.infoLines:10511293.8 %
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((($and$tests/functional/single_bit/verilog/my_module_and.v_7$1$_Y (bvand a b)))) + (pair + (my_module_outputs + $and$tests/functional/single_bit/verilog/my_module_and.v_7$1$_Y ; y + ) + (my_module_state + ) + ) + ))) +) diff --git a/tests/functional/smt/test_smt.rkt b/tests/functional/smt/test_smt.rkt new file mode 100644 index 00000000000..cb27d28bf40 --- /dev/null +++ b/tests/functional/smt/test_smt.rkt @@ -0,0 +1,22 @@ +#lang rosette/safe + +(require rosette/lib/smt) + +;; Define a function to load SMT-LIB from a file +(define (load-smt-file filepath) + (define smt-content (file->string filepath)) + (smt->rosette smt-content)) + +;; Path to your SMT-LIB file +(define smt-file-path "and.smt2") + +;; Load the SMT-LIB content +(define smt-formula (load-smt-file smt-file-path)) + +;; Example: Asserting a simple query +(define (test-smt-formula) + (define result (verify smt-formula)) + (printf "Result: ~a\n" result)) + +;; Run the test +(test-smt-formula) \ No newline at end of file diff --git a/vvp.vcd b/vvp.vcd new file mode 100644 index 00000000000..eb8b21e32e2 --- /dev/null +++ b/vvp.vcd @@ -0,0 +1,10489 @@ +$date + Tue May 28 17:57:15 2024 +$end +$version + Icarus Verilog +$end +$timescale + 1s +$end +$scope module testbench $end +$var wire 1 ! sig_my_module_y $end +$var reg 1024 " filename [1023:0] $end +$var reg 1 # sig_my_module_a $end +$var reg 1 $ sig_my_module_b $end +$var reg 32 % xorshift128_t [31:0] $end +$var reg 32 & xorshift128_w [31:0] $end +$var reg 32 ' xorshift128_x [31:0] $end +$var reg 32 ( xorshift128_y [31:0] $end +$var reg 32 ) xorshift128_z [31:0] $end +$var integer 32 * file [31:0] $end +$var integer 32 + i [31:0] $end +$scope module uut_my_module $end +$var wire 1 # a $end +$var wire 1 $ b $end +$var wire 1 ! y $end +$upscope $end +$scope task my_module_print_header $end +$upscope $end +$scope task my_module_print_status $end +$upscope $end +$scope task my_module_reset $end +$upscope $end +$scope task my_module_test $end +$upscope $end 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From 556c6f7457893cee2b2ac4b010cd47f0fa68e970 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Fri, 31 May 2024 10:43:33 +0200 Subject: [PATCH 37/51] sim-gold instead of sim-cmp for x values --- tests/functional/single_bit/run-test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/functional/single_bit/run-test.sh b/tests/functional/single_bit/run-test.sh index 685dc7a4691..5f08b82ac68 100755 --- a/tests/functional/single_bit/run-test.sh +++ b/tests/functional/single_bit/run-test.sh @@ -24,7 +24,7 @@ run_test() { if ./vcd_harness ${base_name}_functional_cxx.vcd; then # Run yosys to process each Verilog file - if ${BASE_PATH}yosys -p "read_verilog $verilog_file; sim -r ${base_name}_functional_cxx.vcd -scope my_module -vcd ${base_name}_yosys_sim.vcd -timescale 1us -sim-cmp"; then + if ${BASE_PATH}yosys -p "read_verilog $verilog_file; sim -r ${base_name}_functional_cxx.vcd -scope my_module -vcd ${base_name}_yosys_sim.vcd -timescale 1us -sim-gold"; then echo "Yosys sim $verilog_file successfully." else ${BASE_PATH}yosys -p "read_verilog $verilog_file; sim -vcd ${base_name}_yosys_sim.vcd -r ${base_name}_functional_cxx.vcd -scope my_module -timescale 1us" From 52cc2ae5cdacbe8f6c4eea7fd8e7a90d3df876dc Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Sat, 1 Jun 2024 17:41:05 +0200 Subject: [PATCH 38/51] Fix locale issue --- flake.nix | 1 + 1 file changed, 1 insertion(+) diff --git a/flake.nix b/flake.nix index 90c646aa9a6..ea55c012e5d 100644 --- a/flake.nix +++ b/flake.nix @@ -66,6 +66,7 @@ defaultPackage = yosys; packages.vcdiff = vcdiff; devShell = pkgs.mkShell { + LOCALE_ARCHIVE_2_27 = "${pkgs.glibcLocales}/lib/locale/locale-archive"; buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git gtest abc-verifier gtkwave vcdiff lcov racket verilog ]; }; } From 77f3534a7c9cc4756cc5e51384ed595874cff74f Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Tue, 4 Jun 2024 15:02:25 +0200 Subject: [PATCH 39/51] Simplify $mul CellSimplifier --- kernel/graphtools.h | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/kernel/graphtools.h b/kernel/graphtools.h index 907a2b1cf4a..47a7862d556 100644 --- a/kernel/graphtools.h +++ b/kernel/graphtools.h @@ -185,10 +185,9 @@ class CellSimplifier { return factory.slice(a, a_width, offset, y_width); }else if(cellType == ID($mul)){ bool is_signed = a_signed && b_signed; - int width = a_width + b_width; - T a = extend(inputs.at(ID(A)), a_width, width, is_signed); - T b = extend(inputs.at(ID(B)), b_width, width, is_signed); - return extend(factory.mul(a, b, width), width, y_width, is_signed); + T a = extend(inputs.at(ID(A)), a_width, y_width, is_signed); + T b = extend(inputs.at(ID(B)), b_width, y_width, is_signed); + return factory.mul(a, b, y_width); }else if(cellType == ID($div)){ bool is_signed = a_signed && b_signed; int width = max(a_width, b_width); From b126370663bfb4104c5c8d2dc1893a1b430482c9 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Tue, 4 Jun 2024 17:16:52 +0200 Subject: [PATCH 40/51] WIP --- a.cc | 32 ++ add.cc | 32 ++ add.smt | 0 add.smt2 | 22 + alternative_and.smt | 0 and.cc | 32 ++ and.smt | 23 + backends/functional/Makefile.inc | 4 +- backends/functional/alternative_cxx.cc | 265 +++++++++++ backends/functional/alternative_smtlib.cc | 517 ++++++++++++++++++++++ combined.smt2 | 43 ++ flake.nix | 2 +- functional_add.smt2 | 23 + kernel/alternative_functional.h | 369 +++++++++++++++ kernel/alternative_graphtools.h | 509 +++++++++++++++++++++ kernel/functional.h | 2 +- old_add.smt2 | 22 + tests/functional/smt/harness.smt2 | 48 ++ 18 files changed, 1942 insertions(+), 3 deletions(-) create mode 100644 a.cc create mode 100644 add.cc create mode 100644 add.smt create mode 100644 add.smt2 create mode 100644 alternative_and.smt create mode 100644 and.cc create mode 100644 and.smt create mode 100644 backends/functional/alternative_cxx.cc create mode 100644 backends/functional/alternative_smtlib.cc create mode 100644 combined.smt2 create mode 100644 functional_add.smt2 create mode 100644 kernel/alternative_functional.h create mode 100644 kernel/alternative_graphtools.h create mode 100644 old_add.smt2 create mode 100644 tests/functional/smt/harness.smt2 diff --git a/a.cc b/a.cc new file mode 100644 index 00000000000..77a449e7313 --- /dev/null +++ b/a.cc @@ -0,0 +1,32 @@ +#include "sim.h" +struct my_module_Inputs { + Signal<1> b; + Signal<1> a; + + template void dump(T &out) { + out("b", b); + out("a", a); + } +}; + +struct my_module_Outputs { + Signal<1> sum; + + template void dump(T &out) { + out("sum", sum); + } +}; + +struct my_module_State { + + template void dump(T &out) { + } +}; + +void my_module(my_module_Inputs const &input, my_module_Outputs &output, my_module_State const ¤t_state, my_module_State &next_state) +{ + Signal<1> b = input.b; + Signal<1> a = input.a; + Signal<1> $add$tests_functional_single_bit_verilog_my_module_add_v_7$1$_Y = $add(a, b); // + output.sum = $add$tests_functional_single_bit_verilog_my_module_add_v_7$1$_Y; +} diff --git a/add.cc b/add.cc new file mode 100644 index 00000000000..77a449e7313 --- /dev/null +++ b/add.cc @@ -0,0 +1,32 @@ +#include "sim.h" +struct my_module_Inputs { + Signal<1> b; + Signal<1> a; + + template void dump(T &out) { + out("b", b); + out("a", a); + } +}; + +struct my_module_Outputs { + Signal<1> sum; + + template void dump(T &out) { + out("sum", sum); + } +}; + +struct my_module_State { + + template void dump(T &out) { + } +}; + +void my_module(my_module_Inputs const &input, my_module_Outputs &output, my_module_State const ¤t_state, my_module_State &next_state) +{ + Signal<1> b = input.b; + Signal<1> a = input.a; + Signal<1> $add$tests_functional_single_bit_verilog_my_module_add_v_7$1$_Y = $add(a, b); // + output.sum = $add$tests_functional_single_bit_verilog_my_module_add_v_7$1$_Y; +} diff --git a/add.smt b/add.smt new file mode 100644 index 00000000000..e69de29bb2d diff --git a/add.smt2 b/add.smt2 new file mode 100644 index 00000000000..ed1f3319164 --- /dev/null +++ b/add.smt2 @@ -0,0 +1,22 @@ +; SMT-LIBv2 description generated by Yosys 0.41+101 (git sha1 52cc2ae5c, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) +; yosys-smt2-module my_module +(declare-sort |my_module_s| 0) +(declare-fun |my_module_is| (|my_module_s|) Bool) +(declare-fun |my_module#0| (|my_module_s|) (_ BitVec 1)) ; \a +(declare-fun |my_module#1| (|my_module_s|) (_ BitVec 1)) ; \b +(define-fun |my_module#2| ((state |my_module_s|)) (_ BitVec 1) (bvadd (|my_module#0| state) (|my_module#1| state))) ; $add$tests/functional/single_bit/verilog/my_module_add.v:7$1_Y +; yosys-smt2-output sum 1 +(define-fun |my_module_n sum| ((state |my_module_s|)) Bool (= ((_ extract 0 0) (|my_module#2| state)) #b1)) +; yosys-smt2-input b 1 +; yosys-smt2-witness {"offset": 0, "path": ["\\b"], "smtname": "b", "smtoffset": 0, "type": "input", "width": 1} +(define-fun |my_module_n b| ((state |my_module_s|)) Bool (= ((_ extract 0 0) (|my_module#1| state)) #b1)) +; yosys-smt2-input a 1 +; yosys-smt2-witness {"offset": 0, "path": ["\\a"], "smtname": "a", "smtoffset": 0, "type": "input", "width": 1} +(define-fun |my_module_n a| ((state |my_module_s|)) Bool (= ((_ extract 0 0) (|my_module#0| state)) #b1)) +(define-fun |my_module_a| ((state |my_module_s|)) Bool true) +(define-fun |my_module_u| ((state |my_module_s|)) Bool true) +(define-fun |my_module_i| ((state |my_module_s|)) Bool true) +(define-fun |my_module_h| ((state |my_module_s|)) Bool true) +(define-fun |my_module_t| ((state |my_module_s|) (next_state |my_module_s|)) Bool true) ; end of module my_module +; yosys-smt2-topmod my_module +; end of yosys output diff --git a/alternative_and.smt b/alternative_and.smt new file mode 100644 index 00000000000..e69de29bb2d diff --git a/and.cc b/and.cc new file mode 100644 index 00000000000..77a449e7313 --- /dev/null +++ b/and.cc @@ -0,0 +1,32 @@ +#include "sim.h" +struct my_module_Inputs { + Signal<1> b; + Signal<1> a; + + template void dump(T &out) { + out("b", b); + out("a", a); + } +}; + +struct my_module_Outputs { + Signal<1> sum; + + template void dump(T &out) { + out("sum", sum); + } +}; + +struct my_module_State { + + template void dump(T &out) { + } +}; + +void my_module(my_module_Inputs const &input, my_module_Outputs &output, my_module_State const ¤t_state, my_module_State &next_state) +{ + Signal<1> b = input.b; + Signal<1> a = input.a; + Signal<1> $add$tests_functional_single_bit_verilog_my_module_add_v_7$1$_Y = $add(a, b); // + output.sum = $add$tests_functional_single_bit_verilog_my_module_add_v_7$1$_Y; +} diff --git a/and.smt b/and.smt new file mode 100644 index 00000000000..18be0c8f9cd --- /dev/null +++ b/and.smt @@ -0,0 +1,23 @@ +(declare-datatype my_module_inputs ((my_module_inputs + (my_module_inputs_b (_ BitVec 1)) + (my_module_inputs_a (_ BitVec 1)) +))) +(declare-datatype my_module_outputs ((my_module_outputs + (my_module_outputs_sum (_ BitVec 1)) +))) +(declare-datatype my_module_state ((my_module_state +))) +(declare-datatypes ((Pair 2)) ((par (X Y) ((pair (first X) (second Y)))))) +(define-fun my_module_step ((inputs my_module_inputs) (current_state my_module_state)) (Pair my_module_outputs my_module_state) + (let (((b (my_module_inputs_b inputs)))) + (let (((a (my_module_inputs_a inputs)))) + (let ((($add$tests/functional/single_bit/verilog/my_module_add.v_7$1$_Y (bvadd a b)))) + (pair + (my_module_outputs + $add$tests/functional/single_bit/verilog/my_module_add.v_7$1$_Y ; sum + ) + (my_module_state + ) + ) + ))) +) diff --git a/backends/functional/Makefile.inc b/backends/functional/Makefile.inc index c712d2aefe5..675153c95b0 100644 --- a/backends/functional/Makefile.inc +++ b/backends/functional/Makefile.inc @@ -1,2 +1,4 @@ OBJS += backends/functional/cxx.o -OBJS += backends/functional/smtlib.o +# OBJS += backends/functional/smtlib.o +# OBJS += backends/functional/alternative_cxx.o +# OBJS += backends/functional/alternative_smtlib.o diff --git a/backends/functional/alternative_cxx.cc b/backends/functional/alternative_cxx.cc new file mode 100644 index 00000000000..5ba898d0cc8 --- /dev/null +++ b/backends/functional/alternative_cxx.cc @@ -0,0 +1,265 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2024 Emily Schmidt + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include +#include "kernel/yosys.h" +#include "kernel/drivertools.h" +#include "kernel/topo_scc.h" +#include "kernel/functional.h" +#include "kernel/alternative_graphtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +const char *reserved_keywords[] = { + "alignas","alignof","and","and_eq","asm","atomic_cancel","atomic_commit", + "atomic_noexcept","auto","bitand","bitor","bool","break","case", + "catch","char","char16_t","char32_t","char8_t","class","co_await", + "co_return","co_yield","compl","concept","const","const_cast","consteval", + "constexpr","constinit","continue","decltype","default","delete", + "do","double","dynamic_cast","else","enum","explicit","export", + "extern","false","float","for","friend","goto","if","inline", + "int","long","mutable","namespace","new","noexcept","not","not_eq", + "nullptr","operator","or","or_eq","private","protected","public", + "reflexpr","register","reinterpret_cast","requires","return","short", + "signed","sizeof","static","static_assert","static_cast","struct", + "switch","synchronized","template","this","thread_local","throw", + "true","try","typedef","typeid","typename","union","unsigned", + "using","virtual","void","volatile","wchar_t","while","xor","xor_eq", + nullptr +}; + +struct CxxScope { + pool used_names; + dict name_map; + + CxxScope() { + for(const char **p = reserved_keywords; *p != nullptr; p++) + reserve(*p); + } + void reserve(std::string name) { + used_names.insert(name); + } + std::string insert(IdString id) { + std::string str = RTLIL::unescape_id(id); + for(size_t i = 0; i < str.size(); i++) + if(strchr("!\"#%&'()*+,-./:;<=>?@[]\\^`{|}~ ", str[i])) + str[i] = '_'; + if(used_names.count(str) == 0){ + used_names.insert(str); + name_map.insert({id, str}); + return str; + } + for (int idx = 0 ; ; idx++){ + std::string suffixed = str + "_" + std::to_string(idx); + if (used_names.count(suffixed) == 0) { + used_names.insert(suffixed); + if(name_map.count(id) == 0) + name_map.insert({id, suffixed}); + return suffixed; + } + } + } + std::string operator[](IdString id) { + if(name_map.count(id) > 0) + return name_map[id]; + else + return insert(id); + } +}; + +struct CxxWriter { + std::ostream &f; + CxxWriter(std::ostream &out) : f(out) {} + void printf(const char *fmt, ...) + { + va_list va; + va_start(va, fmt); + f << vstringf(fmt, va); + va_end(va); + } +}; + +struct CxxStruct { + std::string name; + dict types; + CxxScope scope; + CxxStruct(std::string name) : name(name) { + scope.reserve("out"); + scope.reserve("dump"); + } + void insert(IdString name, std::string type) { + scope.insert(name); + types.insert({name, type}); + } + void print(CxxWriter &f) { + f.printf("struct %s {\n", name.c_str()); + for (auto p : types) { + f.printf("\t%s %s;\n", p.second.c_str(), scope[p.first].c_str()); + } + f.printf("\n\ttemplate void dump(T &out) {\n"); + for (auto p : types) { + f.printf("\t\tout(\"%s\", %s);\n", RTLIL::unescape_id(p.first).c_str(), scope[p.first].c_str()); + } + f.printf("\t}\n};\n\n"); + } + std::string operator[](IdString field) { + return scope[field]; + } +}; + +struct FunctionalCxxBackend : public Backend +{ + FunctionalCxxBackend() : Backend("functional_cxx", "convert design to C++ using the functional backend") {} + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + } + + void printCxx(std::ostream &stream, std::string, std::string const & name, CompleteComputeGraph &compute_graph) + { + dict inputs, state; + CxxWriter f(stream); + + // Dump the compute graph + for (int i = 0; i < compute_graph.size(); ++i) + { + auto ref = compute_graph[i]; + if(ref.function().name == ID($$input)) + inputs[ref.function().parameters.begin()->first] = ref.function().width; + if(ref.function().name == ID($$state)) + state[ref.function().parameters.begin()->first] = ref.function().width; + } + f.printf("#include \"sim.h\"\n"); + CxxStruct input_struct(name + "_Inputs"); + for (auto const &input : inputs) + input_struct.insert(input.first, "Signal<" + std::to_string(input.second) + ">"); + CxxStruct output_struct(name + "_Outputs"); + for (auto const &key : compute_graph.keys()) + if(state.count(key.first) == 0) + output_struct.insert(key.first, "Signal<" + std::to_string(compute_graph[key.second].function().width) + ">"); + CxxStruct state_struct(name + "_State"); + for (auto const &state_var : state) + state_struct.insert(state_var.first, "Signal<" + std::to_string(state_var.second) + ">"); + + idict node_names; + CxxScope locals; + + input_struct.print(f); + output_struct.print(f); + state_struct.print(f); + + f.printf("void %s(%s_Inputs const &input, %s_Outputs &output, %s_State const ¤t_state, %s_State &next_state)\n{\n", name.c_str(), name.c_str(), name.c_str(), name.c_str(), name.c_str()); + locals.reserve("input"); + locals.reserve("output"); + locals.reserve("current_state"); + locals.reserve("next_state"); + for (int i = 0; i < compute_graph.size(); ++i) + { + auto ref = compute_graph[i]; + int width = ref.function().width; + std::string name; + if(ref.has_sparse_attr()) + name = locals.insert(ref.sparse_attr()); + else + name = locals.insert("\\n" + std::to_string(i)); + node_names(name); + if(ref.function().name == ID($$input)) + f.printf("\tSignal<%d> %s = input.%s;\n", width, name.c_str(), input_struct[ref.function().parameters.begin()->first].c_str()); + else if(ref.function().name == ID($$state)) + f.printf("\tSignal<%d> %s = current_state.%s;\n", width, name.c_str(), state_struct[ref.function().parameters.begin()->first].c_str()); + else if(ref.function().name == ID($$buf)) + f.printf("\tSignal<%d> %s = %s;\n", width, name.c_str(), node_names[ref.arg(0).index()].c_str()); + else if(ref.function().name == ID($$cell_output)) + f.printf("\tSignal<%d> %s = %s.%s;\n", width, name.c_str(), node_names[ref.arg(0).index()].c_str(), RTLIL::unescape_id(ref.function().parameters.begin()->first).c_str()); + else if(ref.function().name == ID($$const)){ + auto c = ref.function().parameters.begin()->second; + if(c.size() <= 32){ + f.printf("\tSignal<%d> %s = $const<%d>(%#x);\n", width, name.c_str(), width, (uint32_t) c.as_int()); + }else{ + f.printf("\tSignal<%d> %s = $const<%d>({%#x", width, name.c_str(), width, (uint32_t) c.as_int()); + while(c.size() > 32){ + c = c.extract(32, c.size() - 32); + f.printf(", %#x", c.as_int()); + } + f.printf("});\n"); + } + }else if(ref.function().name == ID($$undriven)) + f.printf("\tSignal<%d> %s; //undriven\n", width, name.c_str()); + else if(ref.function().name == ID($$slice)) + f.printf("\tSignal<%d> %s = slice<%d>(%s, %d);\n", width, name.c_str(), width, node_names[ref.arg(0).index()].c_str(), ref.function().parameters.at(ID(offset)).as_int()); + else if(ref.function().name == ID($$concat)){ + f.printf("\tauto %s = concat(", name.c_str()); + for (int i = 0, end = ref.size(); i != end; ++i){ + if(i > 0) + f.printf(", "); + f.printf("%s", node_names[ref.arg(i).index()].c_str()); + } + f.printf(");\n"); + }else{ + f.printf("\t"); + if(ref.function().width > 0) + f.printf("Signal<%d>", ref.function().width); + else + f.printf("%s_Outputs", log_id(ref.function().name)); + f.printf(" %s = %s", name.c_str(), log_id(ref.function().name)); + if(ref.function().parameters.count(ID(WIDTH))){ + f.printf("<%d>", ref.function().parameters.at(ID(WIDTH)).as_int()); + } + f.printf("("); + for (int i = 0, end = ref.size(); i != end; ++i) + f.printf("%s%s", i>0?", ":"", node_names[ref.arg(i).index()].c_str()); + f.printf("); //"); + for (auto const ¶m : ref.function().parameters) + { + if (param.second.empty()) + f.printf("[%s]", log_id(param.first)); + else + f.printf("[%s=%s]", log_id(param.first), log_const(param.second)); + } + f.printf("\n"); + } + } + + for (auto const &key : compute_graph.keys()) + { + f.printf("\t%s.%s = %s;\n", state.count(key.first) > 0 ? "next_state" : "output", state_struct[key.first].c_str(), node_names[key.second].c_str()); + } + f.printf("}\n"); + } + + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing Functional C++ backend.\n"); + + size_t argidx = 1; + extra_args(f, filename, args, argidx, design); + + for (auto module : design->selected_modules()) { + log("Dumping module `%s'.\n", module->name.c_str()); + auto compute_graph = calculate_compute_graph(module); + printCxx(*f, filename, RTLIL::unescape_id(module->name), compute_graph); + } + } +} FunctionalCxxBackend; + +PRIVATE_NAMESPACE_END diff --git a/backends/functional/alternative_smtlib.cc b/backends/functional/alternative_smtlib.cc new file mode 100644 index 00000000000..88b3ed42d66 --- /dev/null +++ b/backends/functional/alternative_smtlib.cc @@ -0,0 +1,517 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2024 Emily Schmidt + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include "kernel/yosys.h" +#include "kernel/drivertools.h" +#include "kernel/topo_scc.h" +#include "kernel/functional.h" +#include "kernel/alternative_graphtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct SmtlibScope { + pool used_names; + dict name_map; + + SmtlibScope() { + /*for(const char **p = reserved_keywords; *p != nullptr; p++) + reserve(*p);*/ + } + void reserve(std::string name) { + used_names.insert(name); + } + std::string insert(IdString id) { + std::string str = RTLIL::unescape_id(id); + for(size_t i = 0; i < str.size(); i++) + if(!((unsigned char)str[i] < 0x80 && (isalnum(str[i]) || strchr("~!@$%^&*_-+=<>.?/", str[i])))) + str[i] = '_'; + if(used_names.count(str) == 0){ + used_names.insert(str); + name_map.insert({id, str}); + return str; + } + for (int idx = 0 ; ; idx++){ + std::string suffixed = str + "_" + std::to_string(idx); + if (used_names.count(suffixed) == 0) { + used_names.insert(suffixed); + if(name_map.count(id) == 0) + name_map.insert({id, suffixed}); + return suffixed; + } + } + } + std::string operator[](IdString id) { + if(name_map.count(id) > 0) + return name_map[id]; + else + return insert(id); + } +}; + +struct SmtlibWriter { + std::ostream &f; + SmtlibWriter(std::ostream &out) : f(out) {} + void printf(const char *fmt, ...) + { + va_list va; + va_start(va, fmt); + f << vstringf(fmt, va); + va_end(va); + } + template + SmtlibWriter & operator <<(T &&arg) { + f << std::forward(arg); + return *this; + } +}; + +struct Arg { + int n; + explicit Arg(int n_) : n(n_) {} + bool operator ==(Arg const &other) const { return n == other.n; } +}; + +class SExpr { + enum class Type { + None, + List, + Atom, + Arg, + }; + Type type = Type::None; + union { + std::string atom_; + vector list_; + Arg arg_; + }; + void set_none() { + switch(type) { + case Type::None: break; + case Type::Atom: atom_.~basic_string(); break; + case Type::List: list_.~vector(); break; + case Type::Arg: arg_.~Arg(); break; + } + type = Type::None; + } +public: + SExpr() {} + SExpr(const char *atom) : type(Type::Atom), atom_(atom) {} + SExpr(std::string atom) : type(Type::Atom), atom_(atom) {} + SExpr(int n) : type(Type::Atom), atom_(std::to_string(n)) {} + SExpr(RTLIL::Const const & n) : type(Type::Atom) { + new(&atom_) std::string("#b"); + atom_.reserve(n.size() + 2); + for (size_t i = n.size(); i > 0; i--) + if(n[i-1] == State::S1) + atom_ += "1"; + else + atom_ += "0"; + } + SExpr(vector &&list) : type(Type::List), list_(list) {} + SExpr(std::initializer_list list) : type(Type::List), list_(list) {} + SExpr(Arg arg) : type(Type::Arg), arg_(arg) {} + SExpr(SExpr const &other) { *this = other; } + SExpr(SExpr &&other) { *this = std::move(other); } + SExpr &operator =(SExpr const &other) { + set_none(); + switch(other.type) { + case Type::None: break; + case Type::Atom: new(&atom_) std::string(other.atom_); break; + case Type::List: new(&list_) vector(other.list_); break; + case Type::Arg: new(&arg_) Arg(other.arg_); break; + } + type = other.type; + return *this; + } + SExpr &operator =(SExpr &&other) { + set_none(); + switch(other.type) { + case Type::None: break; + case Type::Atom: new(&atom_) std::string(std::move(other.atom_)); break; + case Type::List: new(&list_) vector(std::move(other.list_)); break; + case Type::Arg: new(&arg_) Arg(std::move(other.arg_)); break; + } + type = other.type; + return *this; + } + ~SExpr() { set_none(); } + bool operator==(SExpr const &other) const { + if(type != other.type) return false; + switch(type) { + case Type::None: return true; + case Type::Atom: return atom_ == other.atom_; + case Type::List: return list_ == other.list_; + case Type::Arg: return arg_ == other.arg_; + } + } + bool is_none() const { return type == Type::None; } + bool is_atom() const { return type == Type::Atom; } + bool is_list() const { return type == Type::List; } + bool is_arg() const { return type == Type::Arg; } + std::string const &atom() const { log_assert(is_atom()); return atom_; } + std::vector const &list() const { log_assert(is_list()); return list_; } + Arg const &arg() const { log_assert(is_arg()); return arg_; } + unsigned int hash() const { + unsigned int inner; + switch(type) { + case Type::None: inner = 0; break; + case Type::Atom: inner = mkhash(atom_); break; + case Type::List: inner = mkhash(list_); break; + case Type::Arg: inner = arg_.n; break; + } + return mkhash((unsigned int) type, inner); + } + SExpr subst_args(std::vector const & args) const { + switch(type) { + case Type::None: + case Type::Atom: + return *this; + case Type::List: { + vector ret; + for(auto & a : list_) + ret.emplace_back(a.subst_args(args)); + return SExpr(std::move(ret)); + } + case Type::Arg: + if(arg_.n >= 1 && (size_t)arg_.n <= args.size()) + return args[arg_.n - 1]; + else + return *this; + } + } +}; + +std::ostream& operator << (std::ostream &os, SExpr const &s) { + if(s.is_atom()) + os << s.atom(); + else if(s.is_list()){ + os << "("; + bool first = true; + for(auto &el: s.list()) { + if(!first) os << " "; + else first = false; + os << el; + } + os << ")"; + }else if(s.is_arg()) + os << "#" << s.arg().n; + else if(s.is_none()) + os << ""; + else + os << "???"; + return os; +} + +struct SmtlibStruct { + SmtlibScope &scope; + std::string name; + idict members; + vector widths; + vector accessors; + SmtlibStruct(std::string name, SmtlibScope &scope) : scope(scope), name(name) { + } + std::string insert(IdString field, int width) { + if(members.at(field, -1) == -1){ + members(field); + scope.insert(field); + widths.push_back(width); + accessors.push_back(scope.insert(std::string("\\") + name + "_" + RTLIL::unescape_id(field))); + } + return scope[field]; + } + void print(SmtlibWriter &f) { + f.printf("(declare-datatype %s ((%s\n", name.c_str(), name.c_str()); + for (size_t i = 0; i < members.size(); i++) + f.printf(" (%s (_ BitVec %d))\n", accessors[i].c_str(), widths[i]); + f.printf(")))\n"); + } + void print_value(SmtlibWriter &f, dict values, int indentation) { + std::string spaces(indentation, ' '); + f << spaces << "(" << name << "\n"; + for (size_t i = 0; i < members.size(); i++) + f << spaces << " " << values[members[i]] << " ; " << RTLIL::unescape_id(members[i]) << "\n"; + f << spaces << ")\n"; + } + SExpr access(SExpr record, IdString member) { + int i = members.at(member); + return SExpr{accessors[i], record}; + } + std::string operator[](IdString field) { + return scope[field]; + } +}; + +struct Node { + SExpr expr; + int width; + + Node(SExpr &&expr, int width) : expr(std::move(expr)), width(width) {} + + bool operator==(Node const &other) const { + return expr == other.expr && width == other.width; + } + + unsigned int hash() const { + return mkhash(expr.hash(), width); + } +}; + +typedef ComputeGraph SmtlibComputeGraph; + +struct SmtlibModule { + std::string name; + SmtlibScope global_scope; + SmtlibStruct input_struct; + SmtlibStruct output_struct; + SmtlibStruct state_struct; + SmtlibComputeGraph compute_graph; + + SmtlibModule(std::string const &name) : + name(name), + input_struct(name + "_inputs", global_scope), + output_struct(name + "_outputs", global_scope), + state_struct(name + "_state", global_scope) + { } + void calculate_compute_graph(RTLIL::Module *module); + void write(std::ostream &stream); +}; + +class SmtlibComputeGraphFactory { + SmtlibModule &module; + SmtlibComputeGraph &graph; + using T = SmtlibComputeGraph::Ref; + static bool is_single_output(IdString type) + { + auto it = yosys_celltypes.cell_types.find(type); + return it != yosys_celltypes.cell_types.end() && it->second.outputs.size() <= 1; + } + T node(SExpr &&expr, int width, std::initializer_list args) { + return graph.add(Node(std::move(expr), width), 0, args); + } + T shift(const char *name, T a, T b, int y_width, int b_width, bool a_signed = false) { + int width = max(y_width, b_width); + T a_ = y_width < width ? extend(a, y_width, width, a_signed) : a; + T b_ = b_width < width ? extend(b, b_width, width, false) : b; + T y_ = node(SExpr {name, Arg(1), Arg(2)}, width, {a_, b_}); + if(y_width < width) + return slice(y_, width, 0, y_width); + else + return y_; + } + SExpr from_bool(SExpr &&arg) { + return SExpr{"ite", std::move(arg), RTLIL::Const(State::S1), RTLIL::Const(State::S0)}; + } + SExpr to_bool(SExpr &&arg) { + return SExpr{"=", std::move(arg), RTLIL::Const(State::S1)}; + } + SExpr extract(SExpr &&arg, int offset, int out_width) { + return SExpr {SExpr {"_", "extract", offset + out_width - 1, offset}, std::move(arg)}; + } +public: + SmtlibComputeGraphFactory(SmtlibModule &mod) : module(mod), graph(mod.compute_graph) {} + T slice(T a, int in_width, int offset, int out_width) { + assert(offset + out_width <= in_width); + return node(extract(Arg(1), offset, out_width), out_width, {a}); + } + T extend(T a, int in_width, int out_width, bool is_signed) { + assert(in_width < out_width); + if(is_signed) + return node(SExpr {SExpr {"_", "sign_extend", out_width - in_width}, Arg(1)}, out_width, {a}); + else + return node(SExpr {SExpr {"_", "zero_extend", out_width - in_width}, Arg(1)}, out_width, {a}); + } + T concat(T a, int a_width, T b, int b_width) { + return node(SExpr {"concat", Arg(1), Arg(2)}, a_width + b_width, {a, b}); + } + T add(T a, T b, int width) { return node(SExpr {"bvadd", Arg(1), Arg(2)}, width, {a, b}); } + + T constant(RTLIL::Const value) { return node(SExpr(value), value.size(), {}); } + T input(IdString name, int width) { + module.input_struct.insert(name, width); + return node(module.input_struct.access("inputs", name), width, {}); + } + T state(IdString name, int width) { + module.state_struct.insert(name, width); + return node(module.state_struct.access("current_state", name), width, {}); + } + T cell_output(T cell, IdString type, IdString name, int width) { + if (is_single_output(type)) + return cell; + else + return node(SExpr {"cell_output", Arg(1), RTLIL::unescape_id(name)}, width, {cell}); + } + T multiple(vector args, int width) { + vector expr; + expr.reserve(args.size() + 1); + expr.push_back("multiple"); + for(size_t i = 1; i <= args.size(); i++) + expr.push_back(Arg(i)); + return graph.add(Node(SExpr(std::move(expr)), width), 0, args); + } + T undriven(int width) { + return constant(RTLIL::Const(State::S0, width)); + //return node(SExpr {"undriven"}, width, {}); + } + T create_pending(int width) { + return node(SExpr(), width, {}); + } + void update_pending(T pending, T node) { + assert(pending.function().expr.is_none()); + pending.set_function(Node(Arg(1), pending.function().width)); + pending.append_arg(node); + } + void declare_output(T node, IdString name, int width) { + module.output_struct.insert(name, width); + node.assign_key(name); + } + void declare_state(T node, IdString name, int width) { + module.state_struct.insert(name, width); + node.assign_key(name); + } + void suggest_name(T node, IdString name) { + node.sparse_attr() = name; + } +}; + +void SmtlibModule::calculate_compute_graph(RTLIL::Module *module) +{ + SmtlibComputeGraphFactory factory(*this); + ComputeGraphConstruction construction(factory); + construction.add_module(module); + construction.process_queue(); + + // Perform topo sort and detect SCCs + SmtlibComputeGraph::SccAdaptor compute_graph_scc(compute_graph); + + bool scc = false; + std::vector perm; + topo_sorted_sccs(compute_graph_scc, [&](int *begin, int *end) { + perm.insert(perm.end(), begin, end); + if (end > begin + 1) + { + log_warning("SCC:"); + for (int *i = begin; i != end; ++i) + log(" %d", *i); + log("\n"); + scc = true; + } + }, /* sources_first */ true); + compute_graph.permute(perm); + if(scc) log_error("combinational loops, aborting\n"); + + // Forward $$buf + std::vector alias; + perm.clear(); + + for (int i = 0; i < compute_graph.size(); ++i) + { + auto node = compute_graph[i]; + if (node.function().expr == Arg(1) && node.arg(0).index() < i) + { + int target_index = alias[node.arg(0).index()]; + auto target_node = compute_graph[perm[target_index]]; + if(!target_node.has_sparse_attr() && node.has_sparse_attr()) + target_node.sparse_attr() = node.sparse_attr(); + alias.push_back(target_index); + } + else + { + alias.push_back(GetSize(perm)); + perm.push_back(i); + } + } + compute_graph.permute(perm, alias); +} + +void SmtlibModule::write(std::ostream &stream) +{ + SmtlibWriter f(stream); + + idict node_names; + SmtlibScope locals; + int paren_count = 0; + + input_struct.print(f); + output_struct.print(f); + state_struct.print(f); + + f << "(declare-datatypes ((Pair 2)) ((par (X Y) ((pair (first X) (second Y))))))\n"; + f.printf("(define-fun %s_step ((inputs %s_inputs) (current_state %s_state)) (Pair %s_outputs %s_state)\n", + name.c_str(), name.c_str(), name.c_str(), name.c_str(), name.c_str()); + + for (int i = 0; i < compute_graph.size(); ++i) + { + auto ref = compute_graph[i]; + std::string name; + if(ref.has_sparse_attr()) + name = locals.insert(ref.sparse_attr()); + else + name = locals.insert("\\n" + std::to_string(i)); + node_names(name); + vector args; + args.reserve(ref.size()); + for (int i = 0, end = ref.size(); i != end; ++i) + args.push_back(node_names[ref.arg(i).index()]); + f << " (let " << SExpr{{SExpr{name, ref.function().expr.subst_args(args)}}} << "\n"; + paren_count++; + } + dict outputs; + for(auto &a: compute_graph.keys()) + outputs.insert({a.first, node_names[a.second]}); + f.printf(" (pair \n"); + output_struct.print_value(f, outputs, 6); + state_struct.print_value(f, outputs, 6); + f.printf(" )\n"); + while(paren_count > 0){ + int n = min(paren_count, 80); + f << " " << std::string(n, ')') << "\n"; + paren_count -= n; + } + f.printf(")\n"); +} + +struct FunctionalSmtlibBackend : public Backend +{ + FunctionalSmtlibBackend() : Backend("alternative_functional_smtlib", "ALTERNATIVE!! convert design to SMTLIB using the functional backend") {} + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + } + + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing ALTERNATIVE!!! Functional SMTLIB backend.\n"); + + size_t argidx = 1; + extra_args(f, filename, args, argidx, design); + + for (auto module : design->selected_modules()) { + log("Dumping module `%s'.\n", module->name.c_str()); + SmtlibModule smt(RTLIL::unescape_id(module->name)); + smt.calculate_compute_graph(module); + smt.write(*f); + } + } +} FunctionalSmtlibBackend; + +PRIVATE_NAMESPACE_END diff --git a/combined.smt2 b/combined.smt2 new file mode 100644 index 00000000000..4ae8745bfee --- /dev/null +++ b/combined.smt2 @@ -0,0 +1,43 @@ +(set-logic QF_BV) + +; Declarations from functional_add.smt2 +(declare-datatype my_module_inputs ((my_module_inputs + (my_module_inputs_b (_ BitVec 1)) + (my_module_inputs_a (_ BitVec 1)) +))) +(declare-datatype my_module_outputs ((my_module_outputs + (my_module_outputs_sum (_ BitVec 1)) +))) +(declare-datatype my_module_state ((my_module_state))) +(declare-datatypes ((Pair 2)) ((par (X Y) ((pair (first X) (second Y)))))) + +; Declarations from old_add.smt2 +(declare-sort |my_module_s| 0) +(declare-fun |my_module#0| (|my_module_s|) (_ BitVec 1)) ; \a +(declare-fun |my_module#1| (|my_module_s|) (_ BitVec 1)) ; \b +(define-fun |my_module#2| ((state |my_module_s|)) (_ BitVec 1) (bvadd (|my_module#0| state) (|my_module#1| state))) ; $add$tests/functional/single_bit/verilog/my_module_add.v:7$1_Y + +; Input variables +(declare-const inputs my_module_inputs) + +; Instantiate functional_add +(define-fun functional_add ((inputs my_module_inputs)) (_ BitVec 1) + (let ((a (my_module_inputs_a inputs)) + (b (my_module_inputs_b inputs))) + (bvadd a b) + ) +) + +; Instantiate old_add +(define-fun old_add ((inputs my_module_inputs)) (_ BitVec 1) + (let ((a (my_module_inputs_a inputs)) + (b (my_module_inputs_b inputs))) + (bvadd a b) + ) +) + +; Assert equivalence +(assert (not (= (functional_add inputs) (old_add inputs)))) + +; Check satisfiability +(check-sat) \ No newline at end of file diff --git a/flake.nix b/flake.nix index ea55c012e5d..22d4cf9da97 100644 --- a/flake.nix +++ b/flake.nix @@ -67,7 +67,7 @@ packages.vcdiff = vcdiff; devShell = pkgs.mkShell { LOCALE_ARCHIVE_2_27 = "${pkgs.glibcLocales}/lib/locale/locale-archive"; - buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git gtest abc-verifier gtkwave vcdiff lcov racket verilog ]; + buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git gtest abc-verifier gtkwave vcdiff lcov racket verilog z3 ]; }; } ); diff --git a/functional_add.smt2 b/functional_add.smt2 new file mode 100644 index 00000000000..18be0c8f9cd --- /dev/null +++ b/functional_add.smt2 @@ -0,0 +1,23 @@ +(declare-datatype my_module_inputs ((my_module_inputs + (my_module_inputs_b (_ BitVec 1)) + (my_module_inputs_a (_ BitVec 1)) +))) +(declare-datatype my_module_outputs ((my_module_outputs + (my_module_outputs_sum (_ BitVec 1)) +))) +(declare-datatype my_module_state ((my_module_state +))) +(declare-datatypes ((Pair 2)) ((par (X Y) ((pair (first X) (second Y)))))) +(define-fun my_module_step ((inputs my_module_inputs) (current_state my_module_state)) (Pair my_module_outputs my_module_state) + (let (((b (my_module_inputs_b inputs)))) + (let (((a (my_module_inputs_a inputs)))) + (let ((($add$tests/functional/single_bit/verilog/my_module_add.v_7$1$_Y (bvadd a b)))) + (pair + (my_module_outputs + $add$tests/functional/single_bit/verilog/my_module_add.v_7$1$_Y ; sum + ) + (my_module_state + ) + ) + ))) +) diff --git a/kernel/alternative_functional.h b/kernel/alternative_functional.h new file mode 100644 index 00000000000..e5ee8824099 --- /dev/null +++ b/kernel/alternative_functional.h @@ -0,0 +1,369 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2024 Jannis Harder + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef FUNCTIONAL_H +#define FUNCTIONAL_H + +#include +#include "kernel/yosys.h" + +YOSYS_NAMESPACE_BEGIN + +template< + typename Fn, // Function type (deduplicated across whole graph) + typename Attr = std::tuple<>, // Call attributes (present in every node) + typename SparseAttr = std::tuple<>, // Sparse call attributes (optional per node) + typename Key = std::tuple<> // Stable keys to refer to nodes +> +struct ComputeGraph +{ + struct Ref; +private: + + // Functions are deduplicated by assigning unique ids + idict functions; + + struct Node { + int fn_index; + int arg_offset; + int arg_count; + Attr attr; + + Node(int fn_index, Attr &&attr, int arg_offset, int arg_count = 0) + : fn_index(fn_index), arg_offset(arg_offset), arg_count(arg_count), attr(std::move(attr)) {} + + Node(int fn_index, Attr const &attr, int arg_offset, int arg_count = 0) + : fn_index(fn_index), arg_offset(arg_offset), arg_count(arg_count), attr(attr) {} + }; + + + std::vector nodes; + std::vector args; + dict keys_; + dict sparse_attrs; + +public: + template + struct BaseRef + { + protected: + friend struct ComputeGraph; + Graph *graph_; + int index_; + BaseRef(Graph *graph, int index) : graph_(graph), index_(index) { + log_assert(index_ >= 0); + check(); + } + + void check() const { log_assert(index_ < graph_->size()); } + + Node const &deref() const { check(); return graph_->nodes[index_]; } + + public: + ComputeGraph const &graph() const { return graph_; } + int index() const { return index_; } + + int size() const { return deref().arg_count; } + + BaseRef arg(int n) const + { + Node const &node = deref(); + log_assert(n >= 0 && n < node.arg_count); + return BaseRef(graph_, graph_->args[node.arg_offset + n]); + } + + std::vector::const_iterator arg_indices_cbegin() const + { + Node const &node = deref(); + return graph_->args.cbegin() + node.arg_offset; + } + + std::vector::const_iterator arg_indices_cend() const + { + Node const &node = deref(); + return graph_->args.cbegin() + node.arg_offset + node.arg_count; + } + + Fn const &function() const { return graph_->functions[deref().fn_index]; } + Attr const &attr() const { return deref().attr; } + + bool has_sparse_attr() const { return graph_->sparse_attrs.count(index_); } + + SparseAttr const &sparse_attr() const + { + auto found = graph_->sparse_attrs.find(index_); + log_assert(found != graph_->sparse_attrs.end()); + return *found; + } + }; + + using ConstRef = BaseRef; + + struct Ref : public BaseRef + { + private: + friend struct ComputeGraph; + Ref(ComputeGraph *graph, int index) : BaseRef(graph, index) {} + Node &deref() const { this->check(); return this->graph_->nodes[this->index_]; } + + public: + void set_function(Fn const &function) const + { + deref().fn_index = this->graph_->functions(function); + } + + Attr &attr() const { return deref().attr; } + + void append_arg(ConstRef arg) const + { + log_assert(arg.graph_ == this->graph_); + append_arg(arg.index()); + } + + void append_arg(int arg) const + { + log_assert(arg >= 0 && arg < this->graph_->size()); + Node &node = deref(); + if (node.arg_offset + node.arg_count != GetSize(this->graph_->args)) + move_args(node); + this->graph_->args.push_back(arg); + node.arg_count++; + } + + operator ConstRef() const + { + return ConstRef(this->graph_, this->index_); + } + + SparseAttr &sparse_attr() const + { + return this->graph_->sparse_attrs[this->index_]; + } + + void clear_sparse_attr() const + { + this->graph_->sparse_attrs.erase(this->index_); + } + + void assign_key(Key const &key) const + { + this->graph_->keys_.emplace(key, this->index_); + } + + private: + void move_args(Node &node) const + { + auto &args = this->graph_->args; + int old_offset = node.arg_offset; + node.arg_offset = GetSize(args); + for (int i = 0; i != node.arg_count; ++i) + args.push_back(args[old_offset + i]); + } + + }; + + bool has_key(Key const &key) const + { + return keys_.count(key); + } + + dict const &keys() const + { + return keys_; + } + + ConstRef operator()(Key const &key) const + { + auto it = keys_.find(key); + log_assert(it != keys_.end()); + return (*this)[it->second]; + } + + Ref operator()(Key const &key) + { + auto it = keys_.find(key); + log_assert(it != keys_.end()); + return (*this)[it->second]; + } + + int size() const { return GetSize(nodes); } + + ConstRef operator[](int index) const { return ConstRef(this, index); } + Ref operator[](int index) { return Ref(this, index); } + + Ref add(Fn const &function, Attr &&attr) + { + int index = GetSize(nodes); + int fn_index = functions(function); + nodes.emplace_back(fn_index, std::move(attr), GetSize(args)); + return Ref(this, index); + } + + Ref add(Fn const &function, Attr const &attr) + { + int index = GetSize(nodes); + int fn_index = functions(function); + nodes.emplace_back(fn_index, attr, GetSize(args)); + return Ref(this, index); + } + + template + Ref add(Fn const &function, Attr const &attr, T const &args) + { + Ref added = add(function, attr); + for (auto arg : args) + added.append_arg(arg); + return added; + } + + template + Ref add(Fn const &function, Attr &&attr, T const &args) + { + Ref added = add(function, std::move(attr)); + for (auto arg : args) + added.append_arg(arg); + return added; + } + + template + Ref add(Fn const &function, Attr const &attr, T begin, T end) + { + Ref added = add(function, attr); + for (; begin != end; ++begin) + added.append_arg(*begin); + return added; + } + + void permute(std::vector const &perm) + { + log_assert(perm.size() <= nodes.size()); + std::vector inv_perm; + inv_perm.resize(nodes.size(), -1); + for (int i = 0; i < GetSize(perm); ++i) + { + int j = perm[i]; + log_assert(j >= 0 && j < GetSize(perm)); + log_assert(inv_perm[j] == -1); + inv_perm[j] = i; + } + permute(perm, inv_perm); + } + + void permute(std::vector const &perm, std::vector const &inv_perm) + { + log_assert(inv_perm.size() == nodes.size()); + std::vector new_nodes; + new_nodes.reserve(perm.size()); + dict new_sparse_attrs; + for (int i : perm) + { + int j = GetSize(new_nodes); + new_nodes.emplace_back(std::move(nodes[i])); + auto found = sparse_attrs.find(i); + if (found != sparse_attrs.end()) + new_sparse_attrs.emplace(j, std::move(found->second)); + } + + std::swap(nodes, new_nodes); + std::swap(sparse_attrs, new_sparse_attrs); + + for (int &arg : args) + { + log_assert(arg < GetSize(inv_perm)); + arg = inv_perm[arg]; + } + + for (auto &key : keys_) + { + log_assert(key.second < GetSize(inv_perm)); + key.second = inv_perm[key.second]; + } + } + + struct SccAdaptor + { + private: + ComputeGraph const &graph_; + std::vector indices_; + public: + SccAdaptor(ComputeGraph const &graph) : graph_(graph) + { + indices_.resize(graph.size(), -1); + } + + + typedef int node_type; + + struct node_enumerator { + private: + friend struct SccAdaptor; + int current, end; + node_enumerator(int current, int end) : current(current), end(end) {} + + public: + + bool finished() const { return current == end; } + node_type next() { + log_assert(!finished()); + node_type result = current; + ++current; + return result; + } + }; + + node_enumerator enumerate_nodes() { + return node_enumerator(0, GetSize(indices_)); + } + + + struct successor_enumerator { + private: + friend struct SccAdaptor; + std::vector::const_iterator current, end; + successor_enumerator(std::vector::const_iterator current, std::vector::const_iterator end) : + current(current), end(end) {} + + public: + bool finished() const { return current == end; } + node_type next() { + log_assert(!finished()); + node_type result = *current; + ++current; + return result; + } + }; + + successor_enumerator enumerate_successors(int index) const { + auto const &ref = graph_[index]; + return successor_enumerator(ref.arg_indices_cbegin(), ref.arg_indices_cend()); + } + + int &dfs_index(node_type const &node) { return indices_[node]; } + + std::vector const &dfs_indices() { return indices_; } + }; + +}; + + + +YOSYS_NAMESPACE_END + + +#endif diff --git a/kernel/alternative_graphtools.h b/kernel/alternative_graphtools.h new file mode 100644 index 00000000000..4abe6c5942b --- /dev/null +++ b/kernel/alternative_graphtools.h @@ -0,0 +1,509 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2024 Emily Schmidt + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef GRAPHTOOLS_H +#define GRAPHTOOLS_H + +#include "kernel/yosys.h" +#include "kernel/drivertools.h" +#include "kernel/functional.h" + +USING_YOSYS_NAMESPACE +YOSYS_NAMESPACE_BEGIN + +template +class CellSimplifier { + Factory &factory; + T reduce_shift_width(T b, int b_width, int y_width, int &reduced_b_width) { + log_assert(y_width > 0); + int new_width = ceil_log2(y_width + 1); + if (b_width <= new_width) { + reduced_b_width = b_width; + return b; + } else { + reduced_b_width = new_width; + T lower_b = factory.slice(b, b_width, 0, new_width); + T overflow = factory.gt(b, factory.constant(RTLIL::Const(y_width, b_width)), b_width); + return factory.mux(lower_b, factory.constant(RTLIL::Const(y_width, new_width)), overflow, new_width); + } + } +public: + T reduce_or(T a, int width) { + if (width == 1) + return a; + return factory.reduce_or(a, width); + } + T extend(T a, int in_width, int out_width, bool is_signed) { + if(in_width == out_width) + return a; + if(in_width > out_width) + return factory.slice(a, in_width, 0, out_width); + return factory.extend(a, in_width, out_width, is_signed); + } + T logical_shift_left(T a, T b, int y_width, int b_width) { + int reduced_b_width; + T reduced_b = reduce_shift_width(b, b_width, y_width, reduced_b_width); + return factory.logical_shift_left(a, reduced_b, y_width, reduced_b_width); + } + T logical_shift_right(T a, T b, int y_width, int b_width) { + int reduced_b_width; + T reduced_b = reduce_shift_width(b, b_width, y_width, reduced_b_width); + return factory.logical_shift_right(a, reduced_b, y_width, reduced_b_width); + } + T arithmetic_shift_right(T a, T b, int y_width, int b_width) { + int reduced_b_width; + T reduced_b = reduce_shift_width(b, b_width, y_width, reduced_b_width); + return factory.arithmetic_shift_right(a, reduced_b, y_width, reduced_b_width); + } + CellSimplifier(Factory &f) : factory(f) {} + T handle(IdString cellType, dict parameters, dict inputs) + { + int a_width = parameters.at(ID(A_WIDTH), Const(-1)).as_int(); + int b_width = parameters.at(ID(B_WIDTH), Const(-1)).as_int(); + int y_width = parameters.at(ID(Y_WIDTH), Const(-1)).as_int(); + bool a_signed = parameters.at(ID(A_SIGNED), Const(0)).as_bool(); + bool b_signed = parameters.at(ID(B_SIGNED), Const(0)).as_bool(); + if(cellType.in({ID($add), ID($sub), ID($and), ID($or), ID($xor), ID($xnor)})){ + bool is_signed = a_signed && b_signed; + T a = extend(inputs.at(ID(A)), a_width, y_width, is_signed); + T b = extend(inputs.at(ID(B)), b_width, y_width, is_signed); + if(cellType == ID($add)) + return factory.add(a, b, y_width); + else if(cellType == ID($sub)) + return factory.sub(a, b, y_width); + else if(cellType == ID($and)) + return factory.bitwise_and(a, b, y_width); + else if(cellType == ID($or)) + return factory.bitwise_or(a, b, y_width); + else if(cellType == ID($xor)) + return factory.bitwise_xor(a, b, y_width); + else if(cellType == ID($xnor)) + return factory.bitwise_not(factory.bitwise_xor(a, b, y_width), y_width); + else + log_abort(); + }else if(cellType.in({ID($eq), ID($ne), ID($eqx), ID($nex), ID($le), ID($lt), ID($ge), ID($gt)})){ + bool is_signed = a_signed && b_signed; + int width = max(a_width, b_width); + T a = extend(inputs.at(ID(A)), a_width, width, is_signed); + T b = extend(inputs.at(ID(B)), b_width, width, is_signed); + if(cellType.in({ID($eq), ID($eqx)})) + return extend(factory.eq(a, b, width), 1, y_width, false); + if(cellType.in({ID($ne), ID($nex)})) + return extend(factory.ne(a, b, width), 1, y_width, false); + else if(cellType == ID($lt)) + return extend(is_signed ? factory.gt(b, a, width) : factory.ugt(b, a, width), 1, y_width, false); + else if(cellType == ID($le)) + return extend(is_signed ? factory.ge(b, a, width) : factory.uge(b, a, width), 1, y_width, false); + else if(cellType == ID($gt)) + return extend(is_signed ? factory.gt(a, b, width) : factory.ugt(a, b, width), 1, y_width, false); + else if(cellType == ID($ge)) + return extend(is_signed ? factory.ge(a, b, width) : factory.uge(a, b, width), 1, y_width, false); + else + log_abort(); + }else if(cellType.in({ID($logic_or), ID($logic_and)})){ + T a = reduce_or(inputs.at(ID(A)), a_width); + T b = reduce_or(inputs.at(ID(B)), b_width); + T y = cellType == ID($logic_and) ? factory.bitwise_and(a, b, 1) : factory.bitwise_or(a, b, 1); + return extend(y, 1, y_width, false); + }else if(cellType == ID($not)){ + T a = extend(inputs.at(ID(A)), a_width, y_width, a_signed); + return factory.bitwise_not(a, y_width); + }else if(cellType == ID($pos)){ + return extend(inputs.at(ID(A)), a_width, y_width, a_signed); + }else if(cellType == ID($neg)){ + T a = extend(inputs.at(ID(A)), a_width, y_width, a_signed); + return factory.neg(a, y_width); + }else if(cellType == ID($logic_not)){ + T a = reduce_or(inputs.at(ID(A)), a_width); + T y = factory.bitwise_not(a, 1); + return extend(y, 1, y_width, false); + }else if(cellType.in({ID($reduce_or), ID($reduce_bool)})){ + T a = reduce_or(inputs.at(ID(A)), a_width); + return extend(a, 1, y_width, false); + }else if(cellType == ID($reduce_and)){ + T a = factory.reduce_and(inputs.at(ID(A)), a_width); + return extend(a, 1, y_width, false); + }else if(cellType.in({ID($reduce_xor), ID($reduce_xnor)})){ + T a = factory.reduce_xor(inputs.at(ID(A)), a_width); + T y = cellType == ID($reduce_xnor) ? factory.bitwise_not(a, 1) : a; + return extend(y, 1, y_width, false); + }else if(cellType == ID($shl) || cellType == ID($sshl)){ + T a = extend(inputs.at(ID(A)), a_width, y_width, a_signed); + T b = inputs.at(ID(B)); + return logical_shift_left(a, b, y_width, b_width); + }else if(cellType == ID($shr) || cellType == ID($sshr)){ + int width = max(a_width, y_width); + T a = extend(inputs.at(ID(A)), a_width, width, a_signed); + T b = inputs.at(ID(B)); + T y = a_signed && cellType == ID($sshr) ? + arithmetic_shift_right(a, b, width, b_width) : + logical_shift_right(a, b, width, b_width); + return extend(y, width, y_width, a_signed); + }else if(cellType == ID($shiftx) || cellType == ID($shift)){ + int width = max(a_width, y_width); + T a = extend(inputs.at(ID(A)), a_width, width, cellType == ID($shift) && a_signed); + T b = inputs.at(ID(B)); + T shr = logical_shift_right(a, b, width, b_width); + if(b_signed) { + T sign_b = factory.slice(b, b_width, b_width - 1, 1); + T shl = logical_shift_left(a, factory.neg(b, b_width), width, b_width); + T y = factory.mux(shr, shl, sign_b, width); + return extend(y, width, y_width, false); + } else { + return extend(shr, width, y_width, false); + } + }else if(cellType == ID($mux)){ + int width = parameters.at(ID(WIDTH)).as_int(); + return factory.mux(inputs.at(ID(A)), inputs.at(ID(B)), inputs.at(ID(S)), width); + }else if(cellType == ID($pmux)){ + int width = parameters.at(ID(WIDTH)).as_int(); + int s_width = parameters.at(ID(S_WIDTH)).as_int(); + return factory.pmux(inputs.at(ID(A)), inputs.at(ID(B)), inputs.at(ID(S)), width, s_width); + }else if(cellType == ID($concat)){ + T a = inputs.at(ID(A)); + T b = inputs.at(ID(B)); + return factory.concat(a, a_width, b, b_width); + }else if(cellType == ID($slice)){ + int offset = parameters.at(ID(OFFSET)).as_int(); + T a = inputs.at(ID(A)); + return factory.slice(a, a_width, offset, y_width); + }else if(cellType == ID($mul)){ + bool is_signed = a_signed && b_signed; + int width = a_width + b_width; + T a = extend(inputs.at(ID(A)), a_width, width, is_signed); + T b = extend(inputs.at(ID(B)), b_width, width, is_signed); + return extend(factory.mul(a, b, width), width, y_width, is_signed); + }else if(cellType == ID($div)){ + bool is_signed = a_signed && b_signed; + int width = max(a_width, b_width); + T a = extend(inputs.at(ID(A)), a_width, width, is_signed); + T b = extend(inputs.at(ID(B)), b_width, width, is_signed); + return extend(factory.div(a, b, width), width, y_width, is_signed); + }else if(cellType == ID($mod)){ + bool is_signed = a_signed && b_signed; + int width = max(a_width, b_width); + T a = extend(inputs.at(ID(A)), a_width, width, is_signed); + T b = extend(inputs.at(ID(B)), b_width, width, is_signed); + return extend(factory.mod(a, b, width), width, y_width, is_signed); + }else{ + log_error("unhandled cell in CellSimplifier %s\n", cellType.c_str()); + } + } +}; + + +struct Function { + IdString name; + int width; + dict parameters; + + Function(IdString name, int width) : name(name), width(width) {} + Function(IdString name, int width, dict parameters) : name(name), width(width), parameters(parameters) {} + + bool operator==(Function const &other) const { + return name == other.name && parameters == other.parameters && width == other.width; + } + + unsigned int hash() const { + return mkhash(name.hash(), parameters.hash()); + } +}; + +typedef ComputeGraph CompleteComputeGraph; + +class CompleteComputeGraphFactory { + CompleteComputeGraph &graph; + using T = CompleteComputeGraph::Ref; + static bool is_single_output(IdString type) + { + auto it = yosys_celltypes.cell_types.find(type); + return it != yosys_celltypes.cell_types.end() && it->second.outputs.size() <= 1; + } +public: + CompleteComputeGraphFactory(CompleteComputeGraph &g) : graph(g) {} + T slice(T a, int in_width, int offset, int out_width) { + assert(offset + out_width <= in_width); + return graph.add(Function(ID($$slice), out_width, {{ID(offset), offset}}), 0, std::array{a}); + } + T extend(T a, int in_width, int out_width, bool is_signed) { + assert(in_width < out_width); + if(is_signed) + return graph.add(Function(ID($sign_extend), out_width, {{ID(WIDTH), out_width}}), 0, std::array{a}); + else + return graph.add(Function(ID($zero_extend), out_width, {{ID(WIDTH), out_width}}), 0, std::array{a}); + } + T concat(T a, int a_width, T b, int b_width) { + return graph.add(Function(ID($$concat), a_width + b_width), 0, std::array{a, b}); + } + T add(T a, T b, int width) { return graph.add(Function(ID($add), width), 0, std::array{a, b}); } + T sub(T a, T b, int width) { return graph.add(Function(ID($sub), width), 0, std::array{a, b}); } + T bitwise_and(T a, T b, int width) { return graph.add(Function(ID($and), width), 0, std::array{a, b}); } + T bitwise_or(T a, T b, int width) { return graph.add(Function(ID($or), width), 0, std::array{a, b}); } + T bitwise_xor(T a, T b, int width) { return graph.add(Function(ID($xor), width), 0, std::array{a, b}); } + T bitwise_not(T a, int width) { return graph.add(Function(ID($not), width), 0, std::array{a}); } + T neg(T a, int width) { return graph.add(Function(ID($neg), width), 0, std::array{a}); } + T mux(T a, T b, T s, int width) { return graph.add(Function(ID($mux), width), 0, std::array{a, b, s}); } + T pmux(T a, T b, T s, int width, int) { return graph.add(Function(ID($pmux), width), 0, std::array{a, b, s}); } + T reduce_and(T a, int) { return graph.add(Function(ID($reduce_and), 1), 0, std::array{a}); } + T reduce_or(T a, int) { return graph.add(Function(ID($reduce_or), 1), 0, std::array{a}); } + T reduce_xor(T a, int) { return graph.add(Function(ID($reduce_xor), 1), 0, std::array{a}); } + T eq(T a, T b, int) { return graph.add(Function(ID($eq), 1), 0, std::array{a, b}); } + T ne(T a, T b, int) { return graph.add(Function(ID($ne), 1), 0, std::array{a, b}); } + T gt(T a, T b, int) { return graph.add(Function(ID($gt), 1), 0, std::array{a, b}); } + T ge(T a, T b, int) { return graph.add(Function(ID($ge), 1), 0, std::array{a, b}); } + T ugt(T a, T b, int) { return graph.add(Function(ID($ugt), 1), 0, std::array{a, b}); } + T uge(T a, T b, int) { return graph.add(Function(ID($uge), 1), 0, std::array{a, b}); } + T logical_shift_left(T a, T b, int y_width, int) { return graph.add(Function(ID($shl), y_width, {{ID(WIDTH), y_width}}), 0, std::array{a, b}); } + T logical_shift_right(T a, T b, int y_width, int) { return graph.add(Function(ID($shr), y_width, {{ID(WIDTH), y_width}}), 0, std::array{a, b}); } + T arithmetic_shift_right(T a, T b, int y_width, int) { return graph.add(Function(ID($asr), y_width, {{ID(WIDTH), y_width}}), 0, std::array{a, b}); } + T mul(T a, T b, int width) { return graph.add(Function(ID($mul), width), 0, std::array{a, b}); } + T mod(T a, T b, int width) { return graph.add(Function(ID($mod), width), 0, std::array{a, b}); } + T div(T a, T b, int width) { return graph.add(Function(ID($div), width), 0, std::array{a, b}); } + + T constant(RTLIL::Const value) { + return graph.add(Function(ID($$const), value.size(), {{ID(value), value}}), 0); + } + T input(IdString name, int width) { return graph.add(Function(ID($$input), width, {{name, {}}}), 0); } + T state(IdString name, int width) { return graph.add(Function(ID($$state), width, {{name, {}}}), 0); } + T cell_output(T cell, IdString type, IdString name, int width) { + if (is_single_output(type)) + return cell; + else + return graph.add(Function(ID($$cell_output), width, {{name, {}}}), 0, std::array{cell}); + } + T multiple(vector args, int width) { + return graph.add(Function(ID($$multiple), width), 0, args); + } + T undriven(int width) { + return graph.add(Function(ID($$undriven), width), 0); + } + + T create_pending(int width) { + return graph.add(Function(ID($$pending), width), 0); + } + void update_pending(T pending, T node) { + assert(pending.function().name == ID($$pending)); + pending.set_function(Function(ID($$buf), pending.function().width)); + pending.append_arg(node); + } + void declare_output(T node, IdString name, int) { + node.assign_key(name); + } + void declare_state(T node, IdString name, int) { + node.assign_key(name); + } + void suggest_name(T node, IdString name) { + node.sparse_attr() = name; + } +}; + +template +class ComputeGraphConstruction { + std::deque queue; + dict graph_nodes; + idict cells; + DriverMap driver_map; + Factory& factory; + CellSimplifier simplifier; + + T enqueue(DriveSpec const &spec) + { + auto it = graph_nodes.find(spec); + if(it == graph_nodes.end()){ + auto node = factory.create_pending(spec.size()); + graph_nodes.insert({spec, node}); + queue.emplace_back(spec); + return node; + }else + return it->second; + } +public: + ComputeGraphConstruction(Factory &f) : factory(f), simplifier(f) {} + void add_module(Module *module) + { + driver_map.add(module); + for (auto cell : module->cells()) { + if (cell->type.in(ID($assert), ID($assume), ID($cover), ID($check))) + enqueue(DriveBitMarker(cells(cell), 0)); + } + for (auto wire : module->wires()) { + if (wire->port_output) { + T node = enqueue(DriveChunk(DriveChunkWire(wire, 0, wire->width))); + factory.declare_output(node, wire->name, wire->width); + } + } + } + void process_queue() + { + for (; !queue.empty(); queue.pop_front()) { + DriveSpec spec = queue.front(); + T pending = graph_nodes.at(spec); + + if (spec.chunks().size() > 1) { + auto chunks = spec.chunks(); + T node = enqueue(chunks[0]); + int width = chunks[0].size(); + for(size_t i = 1; i < chunks.size(); i++) { + node = factory.concat(node, width, enqueue(chunks[i]), chunks[i].size()); + width += chunks[i].size(); + } + factory.update_pending(pending, node); + } else if (spec.chunks().size() == 1) { + DriveChunk chunk = spec.chunks()[0]; + if (chunk.is_wire()) { + DriveChunkWire wire_chunk = chunk.wire(); + if (wire_chunk.is_whole()) { + if (wire_chunk.wire->port_input) { + T node = factory.input(wire_chunk.wire->name, wire_chunk.width); + factory.suggest_name(node, wire_chunk.wire->name); + factory.update_pending(pending, node); + } else { + DriveSpec driver = driver_map(DriveSpec(wire_chunk)); + T node = enqueue(driver); + factory.suggest_name(node, wire_chunk.wire->name); + factory.update_pending(pending, node); + } + } else { + DriveChunkWire whole_wire(wire_chunk.wire, 0, wire_chunk.wire->width); + T node = factory.slice(enqueue(whole_wire), wire_chunk.wire->width, wire_chunk.offset, wire_chunk.width); + factory.update_pending(pending, node); + } + } else if (chunk.is_port()) { + DriveChunkPort port_chunk = chunk.port(); + if (port_chunk.is_whole()) { + if (driver_map.celltypes.cell_output(port_chunk.cell->type, port_chunk.port)) { + if (port_chunk.cell->type.in(ID($dff), ID($ff))) + { + Cell *cell = port_chunk.cell; + T node = factory.state(cell->name, port_chunk.width); + factory.suggest_name(node, port_chunk.cell->name); + factory.update_pending(pending, node); + for (auto const &conn : cell->connections()) { + if (driver_map.celltypes.cell_input(cell->type, conn.first)) { + T node = enqueue(DriveChunkPort(cell, conn)); + factory.declare_state(node, cell->name, port_chunk.width); + } + } + } + else + { + T cell = enqueue(DriveChunkMarker(cells(port_chunk.cell), 0, port_chunk.width)); + factory.suggest_name(cell, port_chunk.cell->name); + T node = factory.cell_output(cell, port_chunk.cell->type, port_chunk.port, port_chunk.width); + factory.suggest_name(node, port_chunk.cell->name.str() + "$" + port_chunk.port.str()); + factory.update_pending(pending, node); + } + } else { + DriveSpec driver = driver_map(DriveSpec(port_chunk)); + factory.update_pending(pending, enqueue(driver)); + } + } else { + DriveChunkPort whole_port(port_chunk.cell, port_chunk.port, 0, GetSize(port_chunk.cell->connections().at(port_chunk.port))); + T node = factory.slice(enqueue(whole_port), whole_port.width, port_chunk.offset, port_chunk.width); + factory.update_pending(pending, node); + } + } else if (chunk.is_constant()) { + T node = factory.constant(chunk.constant()); + factory.suggest_name(node, "$const" + std::to_string(chunk.size()) + "b" + chunk.constant().as_string()); + factory.update_pending(pending, node); + } else if (chunk.is_multiple()) { + vector args; + for (auto const &driver : chunk.multiple().multiple()) + args.push_back(enqueue(driver)); + T node = factory.multiple(args, chunk.size()); + factory.update_pending(pending, node); + } else if (chunk.is_marker()) { + Cell *cell = cells[chunk.marker().marker]; + dict connections; + for(auto const &conn : cell->connections()) { + if(driver_map.celltypes.cell_input(cell->type, conn.first)) + connections.insert({ conn.first, enqueue(DriveChunkPort(cell, conn)) }); + } + T node = simplifier.handle(cell->type, cell->parameters, connections); + factory.update_pending(pending, node); + } else if (chunk.is_none()) { + T node = factory.undriven(chunk.size()); + factory.update_pending(pending, node); + } else { + log_error("unhandled drivespec: %s\n", log_signal(chunk)); + log_abort(); + } + } else { + log_abort(); + } + } + } +}; + +CompleteComputeGraph calculate_compute_graph(RTLIL::Module *module) +{ + CompleteComputeGraph compute_graph; + CompleteComputeGraphFactory factory(compute_graph); + ComputeGraphConstruction construction(factory); + construction.add_module(module); + construction.process_queue(); + + // Perform topo sort and detect SCCs + CompleteComputeGraph::SccAdaptor compute_graph_scc(compute_graph); + + bool scc = false; + std::vector perm; + topo_sorted_sccs(compute_graph_scc, [&](int *begin, int *end) { + perm.insert(perm.end(), begin, end); + if (end > begin + 1) + { + log_warning("SCC:"); + for (int *i = begin; i != end; ++i) + log(" %d(%s)(%s)", *i, compute_graph[*i].function().name.c_str(), compute_graph[*i].has_sparse_attr() ? compute_graph[*i].sparse_attr().c_str() : ""); + log("\n"); + scc = true; + } + }, /* sources_first */ true); + compute_graph.permute(perm); + if(scc) log_error("combinational loops, aborting\n"); + + // Forward $$buf + std::vector alias; + perm.clear(); + + for (int i = 0; i < compute_graph.size(); ++i) + { + auto node = compute_graph[i]; + if (node.function().name == ID($$buf) && node.arg(0).index() < i) + { + int target_index = alias[node.arg(0).index()]; + auto target_node = compute_graph[perm[target_index]]; + if(!target_node.has_sparse_attr() && node.has_sparse_attr()) + target_node.sparse_attr() = node.sparse_attr(); + alias.push_back(target_index); + } + else + { + alias.push_back(GetSize(perm)); + perm.push_back(i); + } + } + compute_graph.permute(perm, alias); + return compute_graph; +}; + + +YOSYS_NAMESPACE_END + +#endif diff --git a/kernel/functional.h b/kernel/functional.h index e5ee8824099..90cf8a829ee 100644 --- a/kernel/functional.h +++ b/kernel/functional.h @@ -118,7 +118,7 @@ struct ComputeGraph struct Ref : public BaseRef { private: - friend struct ComputeGraph; + friend struct ComputeGraph; Ref(ComputeGraph *graph, int index) : BaseRef(graph, index) {} Node &deref() const { this->check(); return this->graph_->nodes[this->index_]; } diff --git a/old_add.smt2 b/old_add.smt2 new file mode 100644 index 00000000000..ed1f3319164 --- /dev/null +++ b/old_add.smt2 @@ -0,0 +1,22 @@ +; SMT-LIBv2 description generated by Yosys 0.41+101 (git sha1 52cc2ae5c, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) +; yosys-smt2-module my_module +(declare-sort |my_module_s| 0) +(declare-fun |my_module_is| (|my_module_s|) Bool) +(declare-fun |my_module#0| (|my_module_s|) (_ BitVec 1)) ; \a +(declare-fun |my_module#1| (|my_module_s|) (_ BitVec 1)) ; \b +(define-fun |my_module#2| ((state |my_module_s|)) (_ BitVec 1) (bvadd (|my_module#0| state) (|my_module#1| state))) ; $add$tests/functional/single_bit/verilog/my_module_add.v:7$1_Y +; yosys-smt2-output sum 1 +(define-fun |my_module_n sum| ((state |my_module_s|)) Bool (= ((_ extract 0 0) (|my_module#2| state)) #b1)) +; yosys-smt2-input b 1 +; yosys-smt2-witness {"offset": 0, "path": ["\\b"], "smtname": "b", "smtoffset": 0, "type": "input", "width": 1} +(define-fun |my_module_n b| ((state |my_module_s|)) Bool (= ((_ extract 0 0) (|my_module#1| state)) #b1)) +; yosys-smt2-input a 1 +; yosys-smt2-witness {"offset": 0, "path": ["\\a"], "smtname": "a", "smtoffset": 0, "type": "input", "width": 1} +(define-fun |my_module_n a| ((state |my_module_s|)) Bool (= ((_ extract 0 0) (|my_module#0| state)) #b1)) +(define-fun |my_module_a| ((state |my_module_s|)) Bool true) +(define-fun |my_module_u| ((state |my_module_s|)) Bool true) +(define-fun |my_module_i| ((state |my_module_s|)) Bool true) +(define-fun |my_module_h| ((state |my_module_s|)) Bool true) +(define-fun |my_module_t| ((state |my_module_s|) (next_state |my_module_s|)) Bool true) ; end of module my_module +; yosys-smt2-topmod my_module +; end of yosys output diff --git a/tests/functional/smt/harness.smt2 b/tests/functional/smt/harness.smt2 new file mode 100644 index 00000000000..0937791305e --- /dev/null +++ b/tests/functional/smt/harness.smt2 @@ -0,0 +1,48 @@ +; Load the datatypes and function definitions +(declare-datatype my_module_inputs ((my_module_inputs + (my_module_inputs_b (_ BitVec 1)) + (my_module_inputs_a (_ BitVec 1)) +))) +(declare-datatype my_module_outputs ((my_module_outputs + (my_module_outputs_sum (_ BitVec 1)) +))) +(declare-datatype my_module_state (())) + +(declare-datatypes ((Pair 2)) ((par (X Y) ((pair (first X) (second Y)))))) + +(define-fun my_module_step ((inputs my_module_inputs) (current_state my_module_state)) (Pair my_module_outputs my_module_state) + (let (((b (my_module_inputs_b inputs)))) + (let (((a (my_module_inputs_a inputs)))) + (let ((($add$tests/functional/single_bit/verilog/my_module_add.v_7$1$_Y (bvadd a b)))) + (pair + (my_module_outputs + $add$tests/functional/single_bit/verilog/my_module_add.v_7$1$_Y ; sum + ) + (my_module_state + ) + ) + ))) +) + +; Create input values +(declare-const input_a (_ BitVec 1)) +(declare-const input_b (_ BitVec 1)) +(declare-const initial_state my_module_state) + +; Define input values +(assert (= input_a #b1)) ; or #b0 for 0 +(assert (= input_b #b0)) ; or #b1 for 1 + +; Construct the input object +(define-const inputs my_module_inputs (my_module_inputs input_b input_a)) + +; Call the step function +(define-const result (my_module_step inputs initial_state)) + +; Extract the output +(define-const output (first result)) +(define-const output_sum (my_module_outputs_sum output)) + +; Check the output +(check-sat) +(get-value (output_sum)) \ No newline at end of file From da2b07616a79d4a55c05ea6af5b798659f0fcfdb Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Tue, 4 Jun 2024 17:30:12 +0200 Subject: [PATCH 41/51] WIP --- tests/functional/smt/harness.smt2 | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/tests/functional/smt/harness.smt2 b/tests/functional/smt/harness.smt2 index 0937791305e..51bcf18c486 100644 --- a/tests/functional/smt/harness.smt2 +++ b/tests/functional/smt/harness.smt2 @@ -6,28 +6,24 @@ (declare-datatype my_module_outputs ((my_module_outputs (my_module_outputs_sum (_ BitVec 1)) ))) -(declare-datatype my_module_state (())) +; (declare-datatype my_module_state (())) (declare-datatypes ((Pair 2)) ((par (X Y) ((pair (first X) (second Y)))))) -(define-fun my_module_step ((inputs my_module_inputs) (current_state my_module_state)) (Pair my_module_outputs my_module_state) +(define-fun my_module_step ((inputs my_module_inputs) ) (my_module_outputs) (let (((b (my_module_inputs_b inputs)))) (let (((a (my_module_inputs_a inputs)))) (let ((($add$tests/functional/single_bit/verilog/my_module_add.v_7$1$_Y (bvadd a b)))) - (pair (my_module_outputs $add$tests/functional/single_bit/verilog/my_module_add.v_7$1$_Y ; sum ) - (my_module_state - ) - ) ))) ) ; Create input values (declare-const input_a (_ BitVec 1)) (declare-const input_b (_ BitVec 1)) -(declare-const initial_state my_module_state) +; (declare-const initial_state my_module_state) ; Define input values (assert (= input_a #b1)) ; or #b0 for 0 @@ -37,7 +33,7 @@ (define-const inputs my_module_inputs (my_module_inputs input_b input_a)) ; Call the step function -(define-const result (my_module_step inputs initial_state)) +(define-const result (my_module_step inputs)) ; Extract the output (define-const output (first result)) From ea1edcb8a2394cab3a2ddacae04374ab4a61a364 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Tue, 4 Jun 2024 17:31:36 +0200 Subject: [PATCH 42/51] WIP --- tests/functional/smt/harness.smt2 | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/tests/functional/smt/harness.smt2 b/tests/functional/smt/harness.smt2 index 51bcf18c486..c5ec5f1e68e 100644 --- a/tests/functional/smt/harness.smt2 +++ b/tests/functional/smt/harness.smt2 @@ -10,14 +10,12 @@ (declare-datatypes ((Pair 2)) ((par (X Y) ((pair (first X) (second Y)))))) -(define-fun my_module_step ((inputs my_module_inputs) ) (my_module_outputs) - (let (((b (my_module_inputs_b inputs)))) - (let (((a (my_module_inputs_a inputs)))) - (let ((($add$tests/functional/single_bit/verilog/my_module_add.v_7$1$_Y (bvadd a b)))) - (my_module_outputs - $add$tests/functional/single_bit/verilog/my_module_add.v_7$1$_Y ; sum - ) - ))) +(define-fun my_module_step ((inputs my_module_inputs)) my_module_outputs + (let ((b (my_module_inputs_b inputs)) + (a (my_module_inputs_a inputs)) + (sum (bvadd a b))) + (my_module_outputs sum) + ) ) ; Create input values @@ -33,11 +31,10 @@ (define-const inputs my_module_inputs (my_module_inputs input_b input_a)) ; Call the step function -(define-const result (my_module_step inputs)) +(define-const result my_module_outputs (my_module_step inputs)) ; Extract the output -(define-const output (first result)) -(define-const output_sum (my_module_outputs_sum output)) +(define-const output_sum (_ BitVec 1) (my_module_outputs_sum result)) ; Check the output (check-sat) From 83a8e5de4f144c1ed41faed67f8abfd9932e6df5 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Wed, 5 Jun 2024 15:56:51 +0200 Subject: [PATCH 43/51] WIP --- backends/functional/Makefile.inc | 4 +- flake.nix | 1 + tests/functional/smt/harness.smt2 | 72 ++++++++++++++----------------- 3 files changed, 36 insertions(+), 41 deletions(-) diff --git a/backends/functional/Makefile.inc b/backends/functional/Makefile.inc index 675153c95b0..5776bf84ed9 100644 --- a/backends/functional/Makefile.inc +++ b/backends/functional/Makefile.inc @@ -1,4 +1,4 @@ -OBJS += backends/functional/cxx.o +# OBJS += backends/functional/cxx.o # OBJS += backends/functional/smtlib.o -# OBJS += backends/functional/alternative_cxx.o +OBJS += backends/functional/alternative_cxx.o # OBJS += backends/functional/alternative_smtlib.o diff --git a/flake.nix b/flake.nix index 22d4cf9da97..683ee78aafc 100644 --- a/flake.nix +++ b/flake.nix @@ -18,6 +18,7 @@ yosys = pkgs.clangStdenv.mkDerivation { name = "yosys"; src = ./. ; + dontStrip = true; buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git pkg-configUpstream ]; checkInputs = with pkgs; [ gtest ]; propagatedBuildInputs = [ abc-verifier ]; diff --git a/tests/functional/smt/harness.smt2 b/tests/functional/smt/harness.smt2 index c5ec5f1e68e..0bad92a44cf 100644 --- a/tests/functional/smt/harness.smt2 +++ b/tests/functional/smt/harness.smt2 @@ -1,41 +1,35 @@ -; Load the datatypes and function definitions -(declare-datatype my_module_inputs ((my_module_inputs - (my_module_inputs_b (_ BitVec 1)) - (my_module_inputs_a (_ BitVec 1)) -))) -(declare-datatype my_module_outputs ((my_module_outputs - (my_module_outputs_sum (_ BitVec 1)) -))) -; (declare-datatype my_module_state (())) - -(declare-datatypes ((Pair 2)) ((par (X Y) ((pair (first X) (second Y)))))) - -(define-fun my_module_step ((inputs my_module_inputs)) my_module_outputs - (let ((b (my_module_inputs_b inputs)) - (a (my_module_inputs_a inputs)) - (sum (bvadd a b))) - (my_module_outputs sum) - ) -) - -; Create input values -(declare-const input_a (_ BitVec 1)) -(declare-const input_b (_ BitVec 1)) -; (declare-const initial_state my_module_state) - -; Define input values -(assert (= input_a #b1)) ; or #b0 for 0 -(assert (= input_b #b0)) ; or #b1 for 1 - -; Construct the input object -(define-const inputs my_module_inputs (my_module_inputs input_b input_a)) - -; Call the step function -(define-const result my_module_outputs (my_module_step inputs)) - -; Extract the output -(define-const output_sum (_ BitVec 1) (my_module_outputs_sum result)) +(set-logic QF_UFBV) + +; Declare sorts and functions as defined in the original file +(declare-sort |my_module_s| 0) +(declare-fun |my_module_is| (|my_module_s|) Bool) +(declare-fun |my_module#0| (|my_module_s|) (_ BitVec 1)) ; \a +(declare-fun |my_module#1| (|my_module_s|) (_ BitVec 1)) ; \b +(define-fun |my_module#2| ((state |my_module_s|)) (_ BitVec 1) (bvadd (|my_module#0| state) (|my_module#1| state))) ; $add$tests/functional/single_bit/verilog/my_module_add.v:7$1_Y + +; Declare input witness functions +(define-fun |my_module_n a| ((state |my_module_s|)) Bool (= ((_ extract 0 0) (|my_module#0| state)) #b1)) +(define-fun |my_module_n b| ((state |my_module_s|)) Bool (= ((_ extract 0 0) (|my_module#1| state)) #b1)) + +; Declare output function +(define-fun |my_module_n sum| ((state |my_module_s|)) Bool (= ((_ extract 0 0) (|my_module#2| state)) #b1)) + +; Other functions as defined in the original file +(define-fun |my_module_a| ((state |my_module_s|)) Bool true) +(define-fun |my_module_u| ((state |my_module_s|)) Bool true) +(define-fun |my_module_i| ((state |my_module_s|)) Bool true) +(define-fun |my_module_h| ((state |my_module_s|)) Bool true) +(define-fun |my_module_t| ((state |my_module_s|) (next_state |my_module_s|)) Bool true) + +; Create a state variable +(declare-fun state0 () |my_module_s|) + +; Assign inputs +(assert (= (|my_module#0| state0) #b1)) ; a = 1 +(assert (= (|my_module#1| state0) #b0)) ; b = 0 ; Check the output -(check-sat) -(get-value (output_sum)) \ No newline at end of file +(assert (|my_module_n sum| state0)) ; sum should be 1 (0 + 1 = 1) + +; Check satisfiability +(check-sat) \ No newline at end of file From a543819476cec7d26c8c96ad8c35219f4779015e Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Thu, 6 Jun 2024 12:12:29 +0200 Subject: [PATCH 44/51] Testing against RTLIL --- tests/functional/single_cells/run-test.sh | 68 +++++++++++++++++++ .../single_cells/test_cell_add_00000.il | 17 +++++ .../single_cells/test_cell_alu_00000.il | 25 +++++++ .../single_cells/test_cell_and_00000.il | 17 +++++ .../single_cells/test_cell_bmux_00000.il | 14 ++++ .../single_cells/test_cell_demux_00000.il | 14 ++++ .../single_cells/test_cell_div_00000.il | 17 +++++ .../single_cells/test_cell_divfloor_00000.il | 17 +++++ .../single_cells/test_cell_eq_00000.il | 17 +++++ .../single_cells/test_cell_fa_00000.il | 17 +++++ .../single_cells/test_cell_ge_00000.il | 17 +++++ .../single_cells/test_cell_gt_00000.il | 17 +++++ .../single_cells/test_cell_lcu_00000.il | 15 ++++ .../single_cells/test_cell_le_00000.il | 17 +++++ .../single_cells/test_cell_logic_and_00000.il | 17 +++++ .../single_cells/test_cell_logic_not_00000.il | 13 ++++ .../single_cells/test_cell_logic_or_00000.il | 17 +++++ .../single_cells/test_cell_lt_00000.il | 17 +++++ .../single_cells/test_cell_lut_00000.il | 12 ++++ .../single_cells/test_cell_macc_00000.il | 17 +++++ .../single_cells/test_cell_mod_00000.il | 17 +++++ .../single_cells/test_cell_modfloor_00000.il | 17 +++++ .../single_cells/test_cell_mul_00000.il | 17 +++++ .../single_cells/test_cell_mux_00000.il | 15 ++++ .../single_cells/test_cell_ne_00000.il | 17 +++++ .../single_cells/test_cell_neg_00000.il | 13 ++++ .../single_cells/test_cell_not_00000.il | 13 ++++ .../single_cells/test_cell_or_00000.il | 17 +++++ .../single_cells/test_cell_pos_00000.il | 13 ++++ .../test_cell_reduce_and_00000.il | 13 ++++ .../test_cell_reduce_bool_00000.il | 13 ++++ .../single_cells/test_cell_reduce_or_00000.il | 13 ++++ .../test_cell_reduce_xnor_00000.il | 13 ++++ .../test_cell_reduce_xor_00000.il | 13 ++++ .../single_cells/test_cell_shift_00000.il | 17 +++++ .../single_cells/test_cell_shiftx_00000.il | 17 +++++ .../single_cells/test_cell_shl_00000.il | 17 +++++ .../single_cells/test_cell_shr_00000.il | 17 +++++ .../single_cells/test_cell_sop_00000.il | 13 ++++ .../single_cells/test_cell_sshl_00000.il | 17 +++++ .../single_cells/test_cell_sshr_00000.il | 17 +++++ .../single_cells/test_cell_sub_00000.il | 17 +++++ .../single_cells/test_cell_xnor_00000.il | 17 +++++ .../single_cells/test_cell_xor_00000.il | 17 +++++ 44 files changed, 752 insertions(+) create mode 100755 tests/functional/single_cells/run-test.sh create mode 100644 tests/functional/single_cells/test_cell_add_00000.il create mode 100644 tests/functional/single_cells/test_cell_alu_00000.il create mode 100644 tests/functional/single_cells/test_cell_and_00000.il create mode 100644 tests/functional/single_cells/test_cell_bmux_00000.il create mode 100644 tests/functional/single_cells/test_cell_demux_00000.il create mode 100644 tests/functional/single_cells/test_cell_div_00000.il create mode 100644 tests/functional/single_cells/test_cell_divfloor_00000.il create mode 100644 tests/functional/single_cells/test_cell_eq_00000.il create mode 100644 tests/functional/single_cells/test_cell_fa_00000.il create mode 100644 tests/functional/single_cells/test_cell_ge_00000.il create mode 100644 tests/functional/single_cells/test_cell_gt_00000.il create mode 100644 tests/functional/single_cells/test_cell_lcu_00000.il create mode 100644 tests/functional/single_cells/test_cell_le_00000.il create mode 100644 tests/functional/single_cells/test_cell_logic_and_00000.il create mode 100644 tests/functional/single_cells/test_cell_logic_not_00000.il create mode 100644 tests/functional/single_cells/test_cell_logic_or_00000.il create mode 100644 tests/functional/single_cells/test_cell_lt_00000.il create mode 100644 tests/functional/single_cells/test_cell_lut_00000.il create mode 100644 tests/functional/single_cells/test_cell_macc_00000.il create mode 100644 tests/functional/single_cells/test_cell_mod_00000.il create mode 100644 tests/functional/single_cells/test_cell_modfloor_00000.il create mode 100644 tests/functional/single_cells/test_cell_mul_00000.il create mode 100644 tests/functional/single_cells/test_cell_mux_00000.il create mode 100644 tests/functional/single_cells/test_cell_ne_00000.il create mode 100644 tests/functional/single_cells/test_cell_neg_00000.il create mode 100644 tests/functional/single_cells/test_cell_not_00000.il create mode 100644 tests/functional/single_cells/test_cell_or_00000.il create mode 100644 tests/functional/single_cells/test_cell_pos_00000.il create mode 100644 tests/functional/single_cells/test_cell_reduce_and_00000.il create mode 100644 tests/functional/single_cells/test_cell_reduce_bool_00000.il create mode 100644 tests/functional/single_cells/test_cell_reduce_or_00000.il create mode 100644 tests/functional/single_cells/test_cell_reduce_xnor_00000.il create mode 100644 tests/functional/single_cells/test_cell_reduce_xor_00000.il create mode 100644 tests/functional/single_cells/test_cell_shift_00000.il create mode 100644 tests/functional/single_cells/test_cell_shiftx_00000.il create mode 100644 tests/functional/single_cells/test_cell_shl_00000.il create mode 100644 tests/functional/single_cells/test_cell_shr_00000.il create mode 100644 tests/functional/single_cells/test_cell_sop_00000.il create mode 100644 tests/functional/single_cells/test_cell_sshl_00000.il create mode 100644 tests/functional/single_cells/test_cell_sshr_00000.il create mode 100644 tests/functional/single_cells/test_cell_sub_00000.il create mode 100644 tests/functional/single_cells/test_cell_xnor_00000.il create mode 100644 tests/functional/single_cells/test_cell_xor_00000.il diff --git a/tests/functional/single_cells/run-test.sh b/tests/functional/single_cells/run-test.sh new file mode 100755 index 00000000000..5f08b82ac68 --- /dev/null +++ b/tests/functional/single_cells/run-test.sh @@ -0,0 +1,68 @@ +#!/bin/bash + +# Initialize an array to store the names of failing Verilog files and their failure types +declare -A failing_files + +# Function to run the test on a given Verilog file +run_test() { + # Define the common variable for the relative path + BASE_PATH="../../../" + + local verilog_file=$1 + + # Extract the base name without extension + local base_name=$(basename "$verilog_file" .v) + + # Run yosys to process each Verilog file + if ${BASE_PATH}yosys -p "read_verilog $verilog_file; write_functional_cxx my_module_functional_cxx.cc"; then + echo "Yosys processed $verilog_file successfully." + + # Compile the generated C++ files with vcd_harness.cpp + ${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cc -I ${BASE_PATH}backends/functional/cxx_runtime/ -o vcd_harness + + # Generate VCD files with base_name + if ./vcd_harness ${base_name}_functional_cxx.vcd; then + + # Run yosys to process each Verilog file + if ${BASE_PATH}yosys -p "read_verilog $verilog_file; sim -r ${base_name}_functional_cxx.vcd -scope my_module -vcd ${base_name}_yosys_sim.vcd -timescale 1us -sim-gold"; then + echo "Yosys sim $verilog_file successfully." + else + ${BASE_PATH}yosys -p "read_verilog $verilog_file; sim -vcd ${base_name}_yosys_sim.vcd -r ${base_name}_functional_cxx.vcd -scope my_module -timescale 1us" + echo "Yosys simulation of $verilog_file failed. There is a discrepancy with functional cxx" + failing_files["$verilog_file"]="Yosys sim failure" + fi + + else + echo "Failed to generate VCD files for $verilog_file." + failing_files["$verilog_file"]="VCD generation failure" + fi + else + echo "Yosys failed to process $verilog_file." + failing_files["$verilog_file"]="Yosys failure" + fi +} + +# Main function to run all tests +run_all_tests() { + # Loop through all Verilog files in the verilog directory + for verilog_file in verilog/*.v; do + run_test "$verilog_file" + done + + # Check if the array of failing files is empty + if [ ${#failing_files[@]} -eq 0 ]; then + echo "All files passed." + return 0 + else + echo "The following files failed:" + for file in "${!failing_files[@]}"; do + echo "$file: ${failing_files[$file]}" + done + return 1 + fi +} + +# If the script is being sourced, do not execute the tests +if [[ "${BASH_SOURCE[0]}" == "${0}" ]]; then + run_all_tests +fi diff --git a/tests/functional/single_cells/test_cell_add_00000.il b/tests/functional/single_cells/test_cell_add_00000.il new file mode 100644 index 00000000000..531dabe41fa --- /dev/null +++ b/tests/functional/single_cells/test_cell_add_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 5 input 1 \A + wire width 4 input 2 \B + wire width 6 output 3 \Y + cell $add \UUT + parameter \A_SIGNED 1 + parameter \A_WIDTH 5 + parameter \B_SIGNED 1 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 6 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_alu_00000.il b/tests/functional/single_cells/test_cell_alu_00000.il new file mode 100644 index 00000000000..ebdd3b7343b --- /dev/null +++ b/tests/functional/single_cells/test_cell_alu_00000.il @@ -0,0 +1,25 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 8 input 1 \A + wire width 7 input 2 \B + wire input 3 \BI + wire input 4 \CI + wire width 6 output 5 \CO + wire width 6 output 6 \X + wire width 6 output 7 \Y + cell $alu \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 6 + connect \A \A + connect \B \B + connect \BI \BI + connect \CI \CI + connect \CO \CO + connect \X \X + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_and_00000.il b/tests/functional/single_cells/test_cell_and_00000.il new file mode 100644 index 00000000000..2578f60b774 --- /dev/null +++ b/tests/functional/single_cells/test_cell_and_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 2 input 1 \A + wire width 3 input 2 \B + wire width 2 output 3 \Y + cell $and \UUT + parameter \A_SIGNED 1 + parameter \A_WIDTH 2 + parameter \B_SIGNED 1 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 2 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_bmux_00000.il b/tests/functional/single_cells/test_cell_bmux_00000.il new file mode 100644 index 00000000000..1b613bd698c --- /dev/null +++ b/tests/functional/single_cells/test_cell_bmux_00000.il @@ -0,0 +1,14 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 8 input 1 \A + wire input 2 \S + wire width 4 output 3 \Y + cell $bmux \UUT + parameter \S_WIDTH 1 + parameter \WIDTH 4 + connect \A \A + connect \S \S + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_demux_00000.il b/tests/functional/single_cells/test_cell_demux_00000.il new file mode 100644 index 00000000000..dbe2dee62ac --- /dev/null +++ b/tests/functional/single_cells/test_cell_demux_00000.il @@ -0,0 +1,14 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 6 input 1 \A + wire width 5 input 2 \S + wire width 192 output 3 \Y + cell $demux \UUT + parameter \S_WIDTH 5 + parameter \WIDTH 6 + connect \A \A + connect \S \S + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_div_00000.il b/tests/functional/single_cells/test_cell_div_00000.il new file mode 100644 index 00000000000..6f278a7a079 --- /dev/null +++ b/tests/functional/single_cells/test_cell_div_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 4 input 1 \A + wire width 6 input 2 \B + wire output 3 \Y + cell $div \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_divfloor_00000.il b/tests/functional/single_cells/test_cell_divfloor_00000.il new file mode 100644 index 00000000000..67fce36b331 --- /dev/null +++ b/tests/functional/single_cells/test_cell_divfloor_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 4 input 1 \A + wire width 4 input 2 \B + wire width 6 output 3 \Y + cell $divfloor \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 6 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_eq_00000.il b/tests/functional/single_cells/test_cell_eq_00000.il new file mode 100644 index 00000000000..06fef02b5b2 --- /dev/null +++ b/tests/functional/single_cells/test_cell_eq_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 5 input 1 \A + wire input 2 \B + wire width 4 output 3 \Y + cell $eq \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_fa_00000.il b/tests/functional/single_cells/test_cell_fa_00000.il new file mode 100644 index 00000000000..97f0eb0297d --- /dev/null +++ b/tests/functional/single_cells/test_cell_fa_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire input 1 \A + wire input 2 \B + wire input 3 \C + wire output 4 \X + wire output 5 \Y + cell $fa \UUT + parameter \WIDTH 1 + connect \A \A + connect \B \B + connect \C \C + connect \X \X + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_ge_00000.il b/tests/functional/single_cells/test_cell_ge_00000.il new file mode 100644 index 00000000000..0ac72e9433d --- /dev/null +++ b/tests/functional/single_cells/test_cell_ge_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 3 input 1 \A + wire width 7 input 2 \B + wire width 6 output 3 \Y + cell $ge \UUT + parameter \A_SIGNED 1 + parameter \A_WIDTH 3 + parameter \B_SIGNED 1 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 6 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_gt_00000.il b/tests/functional/single_cells/test_cell_gt_00000.il new file mode 100644 index 00000000000..d4498d36f9e --- /dev/null +++ b/tests/functional/single_cells/test_cell_gt_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 7 input 1 \A + wire width 3 input 2 \B + wire width 4 output 3 \Y + cell $gt \UUT + parameter \A_SIGNED 1 + parameter \A_WIDTH 7 + parameter \B_SIGNED 1 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_lcu_00000.il b/tests/functional/single_cells/test_cell_lcu_00000.il new file mode 100644 index 00000000000..e1bda0b433c --- /dev/null +++ b/tests/functional/single_cells/test_cell_lcu_00000.il @@ -0,0 +1,15 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire input 1 \CI + wire width 2 output 2 \CO + wire width 2 input 3 \G + wire width 2 input 4 \P + cell $lcu \UUT + parameter \WIDTH 2 + connect \CI \CI + connect \CO \CO + connect \G \G + connect \P \P + end +end diff --git a/tests/functional/single_cells/test_cell_le_00000.il b/tests/functional/single_cells/test_cell_le_00000.il new file mode 100644 index 00000000000..609d99ce8a4 --- /dev/null +++ b/tests/functional/single_cells/test_cell_le_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 5 input 1 \A + wire width 4 input 2 \B + wire width 6 output 3 \Y + cell $le \UUT + parameter \A_SIGNED 1 + parameter \A_WIDTH 5 + parameter \B_SIGNED 1 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 6 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_logic_and_00000.il b/tests/functional/single_cells/test_cell_logic_and_00000.il new file mode 100644 index 00000000000..2eae6e3fcb1 --- /dev/null +++ b/tests/functional/single_cells/test_cell_logic_and_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 2 input 1 \A + wire width 7 input 2 \B + wire output 3 \Y + cell $logic_and \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_logic_not_00000.il b/tests/functional/single_cells/test_cell_logic_not_00000.il new file mode 100644 index 00000000000..c7898491ca5 --- /dev/null +++ b/tests/functional/single_cells/test_cell_logic_not_00000.il @@ -0,0 +1,13 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 3 input 1 \A + wire width 8 output 2 \Y + cell $logic_not \UUT + parameter \A_SIGNED 1 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 8 + connect \A \A + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_logic_or_00000.il b/tests/functional/single_cells/test_cell_logic_or_00000.il new file mode 100644 index 00000000000..7a1ef6cbda0 --- /dev/null +++ b/tests/functional/single_cells/test_cell_logic_or_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 8 input 1 \A + wire width 7 input 2 \B + wire width 2 output 3 \Y + cell $logic_or \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 2 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_lt_00000.il b/tests/functional/single_cells/test_cell_lt_00000.il new file mode 100644 index 00000000000..fd3ee1f8bad --- /dev/null +++ b/tests/functional/single_cells/test_cell_lt_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 8 input 1 \A + wire width 5 input 2 \B + wire width 6 output 3 \Y + cell $lt \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 6 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_lut_00000.il b/tests/functional/single_cells/test_cell_lut_00000.il new file mode 100644 index 00000000000..7c4882bb61a --- /dev/null +++ b/tests/functional/single_cells/test_cell_lut_00000.il @@ -0,0 +1,12 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 2 input 1 \A + wire output 2 \Y + cell $lut \UUT + parameter \LUT 4'1111 + parameter \WIDTH 2 + connect \A \A + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_macc_00000.il b/tests/functional/single_cells/test_cell_macc_00000.il new file mode 100644 index 00000000000..66b51634e97 --- /dev/null +++ b/tests/functional/single_cells/test_cell_macc_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 3 input 1 \A + wire width 0 input 2 \B + wire width 2 output 3 \Y + cell $macc \UUT + parameter \A_WIDTH 3 + parameter \B_WIDTH 0 + parameter \CONFIG 10'0110000010 + parameter \CONFIG_WIDTH 10 + parameter \Y_WIDTH 2 + connect \A \A + connect \B { } + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_mod_00000.il b/tests/functional/single_cells/test_cell_mod_00000.il new file mode 100644 index 00000000000..a484918f05c --- /dev/null +++ b/tests/functional/single_cells/test_cell_mod_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 6 input 1 \A + wire width 8 input 2 \B + wire width 2 output 3 \Y + cell $mod \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 2 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_modfloor_00000.il b/tests/functional/single_cells/test_cell_modfloor_00000.il new file mode 100644 index 00000000000..6cd00aeea5d --- /dev/null +++ b/tests/functional/single_cells/test_cell_modfloor_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 5 input 1 \A + wire width 7 input 2 \B + wire width 4 output 3 \Y + cell $modfloor \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 4 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_mul_00000.il b/tests/functional/single_cells/test_cell_mul_00000.il new file mode 100644 index 00000000000..c77aaffb87e --- /dev/null +++ b/tests/functional/single_cells/test_cell_mul_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 6 input 1 \A + wire width 2 input 2 \B + wire width 5 output 3 \Y + cell $mul \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 5 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_mux_00000.il b/tests/functional/single_cells/test_cell_mux_00000.il new file mode 100644 index 00000000000..3fc52ac7716 --- /dev/null +++ b/tests/functional/single_cells/test_cell_mux_00000.il @@ -0,0 +1,15 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 4 input 1 \A + wire width 4 input 2 \B + wire input 3 \S + wire width 4 output 4 \Y + cell $mux \UUT + parameter \WIDTH 4 + connect \A \A + connect \B \B + connect \S \S + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_ne_00000.il b/tests/functional/single_cells/test_cell_ne_00000.il new file mode 100644 index 00000000000..47ba31397ed --- /dev/null +++ b/tests/functional/single_cells/test_cell_ne_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 7 input 1 \A + wire width 5 input 2 \B + wire width 4 output 3 \Y + cell $ne \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 4 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_neg_00000.il b/tests/functional/single_cells/test_cell_neg_00000.il new file mode 100644 index 00000000000..ee4273508d1 --- /dev/null +++ b/tests/functional/single_cells/test_cell_neg_00000.il @@ -0,0 +1,13 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 2 input 1 \A + wire width 5 output 2 \Y + cell $neg \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 5 + connect \A \A + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_not_00000.il b/tests/functional/single_cells/test_cell_not_00000.il new file mode 100644 index 00000000000..9281ded0dfa --- /dev/null +++ b/tests/functional/single_cells/test_cell_not_00000.il @@ -0,0 +1,13 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 7 input 1 \A + wire width 7 output 2 \Y + cell $not \UUT + parameter \A_SIGNED 1 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A \A + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_or_00000.il b/tests/functional/single_cells/test_cell_or_00000.il new file mode 100644 index 00000000000..100ea42cd38 --- /dev/null +++ b/tests/functional/single_cells/test_cell_or_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 7 input 1 \A + wire input 2 \B + wire width 2 output 3 \Y + cell $or \UUT + parameter \A_SIGNED 1 + parameter \A_WIDTH 7 + parameter \B_SIGNED 1 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_pos_00000.il b/tests/functional/single_cells/test_cell_pos_00000.il new file mode 100644 index 00000000000..182f0acd38f --- /dev/null +++ b/tests/functional/single_cells/test_cell_pos_00000.il @@ -0,0 +1,13 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire input 1 \A + wire width 3 output 2 \Y + cell $pos \UUT + parameter \A_SIGNED 1 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \A + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_reduce_and_00000.il b/tests/functional/single_cells/test_cell_reduce_and_00000.il new file mode 100644 index 00000000000..079ed33ade5 --- /dev/null +++ b/tests/functional/single_cells/test_cell_reduce_and_00000.il @@ -0,0 +1,13 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 4 input 1 \A + wire width 5 output 2 \Y + cell $reduce_and \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 5 + connect \A \A + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_reduce_bool_00000.il b/tests/functional/single_cells/test_cell_reduce_bool_00000.il new file mode 100644 index 00000000000..a417179c818 --- /dev/null +++ b/tests/functional/single_cells/test_cell_reduce_bool_00000.il @@ -0,0 +1,13 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire input 1 \A + wire width 2 output 2 \Y + cell $reduce_bool \UUT + parameter \A_SIGNED 1 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \A + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_reduce_or_00000.il b/tests/functional/single_cells/test_cell_reduce_or_00000.il new file mode 100644 index 00000000000..881c6dfe3a1 --- /dev/null +++ b/tests/functional/single_cells/test_cell_reduce_or_00000.il @@ -0,0 +1,13 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 2 input 1 \A + wire width 7 output 2 \Y + cell $reduce_or \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 7 + connect \A \A + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_reduce_xnor_00000.il b/tests/functional/single_cells/test_cell_reduce_xnor_00000.il new file mode 100644 index 00000000000..c06562729ea --- /dev/null +++ b/tests/functional/single_cells/test_cell_reduce_xnor_00000.il @@ -0,0 +1,13 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 4 input 1 \A + wire width 4 output 2 \Y + cell $reduce_xnor \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \A + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_reduce_xor_00000.il b/tests/functional/single_cells/test_cell_reduce_xor_00000.il new file mode 100644 index 00000000000..428d2ea87a2 --- /dev/null +++ b/tests/functional/single_cells/test_cell_reduce_xor_00000.il @@ -0,0 +1,13 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 4 input 1 \A + wire output 2 \Y + cell $reduce_xor \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \A + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_shift_00000.il b/tests/functional/single_cells/test_cell_shift_00000.il new file mode 100644 index 00000000000..f82a2a79df7 --- /dev/null +++ b/tests/functional/single_cells/test_cell_shift_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire input 1 \A + wire width 6 input 2 \B + wire width 4 output 3 \Y + cell $shift \UUT + parameter \A_SIGNED 1 + parameter \A_WIDTH 1 + parameter \B_SIGNED 1 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 4 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_shiftx_00000.il b/tests/functional/single_cells/test_cell_shiftx_00000.il new file mode 100644 index 00000000000..b89ac5bef91 --- /dev/null +++ b/tests/functional/single_cells/test_cell_shiftx_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire input 1 \A + wire width 5 input 2 \B + wire width 3 output 3 \Y + cell $shiftx \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 3 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_shl_00000.il b/tests/functional/single_cells/test_cell_shl_00000.il new file mode 100644 index 00000000000..1cfee2a52b5 --- /dev/null +++ b/tests/functional/single_cells/test_cell_shl_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 8 input 1 \A + wire width 2 input 2 \B + wire width 3 output 3 \Y + cell $shl \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_shr_00000.il b/tests/functional/single_cells/test_cell_shr_00000.il new file mode 100644 index 00000000000..35dd379099c --- /dev/null +++ b/tests/functional/single_cells/test_cell_shr_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 7 input 1 \A + wire width 6 input 2 \B + wire width 4 output 3 \Y + cell $shr \UUT + parameter \A_SIGNED 1 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 4 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_sop_00000.il b/tests/functional/single_cells/test_cell_sop_00000.il new file mode 100644 index 00000000000..df0f8f20abe --- /dev/null +++ b/tests/functional/single_cells/test_cell_sop_00000.il @@ -0,0 +1,13 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 8 input 1 \A + wire output 2 \Y + cell $sop \UUT + parameter \DEPTH 8 + parameter \TABLE 128'10010000100100000101101010001001101000101010010100010000010100000101010100000001001010010110101010101010101000100100011001000110 + parameter \WIDTH 8 + connect \A \A + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_sshl_00000.il b/tests/functional/single_cells/test_cell_sshl_00000.il new file mode 100644 index 00000000000..798288754ce --- /dev/null +++ b/tests/functional/single_cells/test_cell_sshl_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 5 input 1 \A + wire width 3 input 2 \B + wire width 6 output 3 \Y + cell $sshl \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 6 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_sshr_00000.il b/tests/functional/single_cells/test_cell_sshr_00000.il new file mode 100644 index 00000000000..3f59a693f24 --- /dev/null +++ b/tests/functional/single_cells/test_cell_sshr_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 3 input 1 \A + wire width 2 input 2 \B + wire width 2 output 3 \Y + cell $sshr \UUT + parameter \A_SIGNED 1 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_sub_00000.il b/tests/functional/single_cells/test_cell_sub_00000.il new file mode 100644 index 00000000000..cb9ec2f7904 --- /dev/null +++ b/tests/functional/single_cells/test_cell_sub_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 6 input 1 \A + wire width 6 input 2 \B + wire width 6 output 3 \Y + cell $sub \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_xnor_00000.il b/tests/functional/single_cells/test_cell_xnor_00000.il new file mode 100644 index 00000000000..85bd7d239df --- /dev/null +++ b/tests/functional/single_cells/test_cell_xnor_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 7 input 1 \A + wire width 8 input 2 \B + wire width 7 output 3 \Y + cell $xnor \UUT + parameter \A_SIGNED 1 + parameter \A_WIDTH 7 + parameter \B_SIGNED 1 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 7 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/test_cell_xor_00000.il b/tests/functional/single_cells/test_cell_xor_00000.il new file mode 100644 index 00000000000..2359698b55b --- /dev/null +++ b/tests/functional/single_cells/test_cell_xor_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 6 input 1 \A + wire width 2 input 2 \B + wire width 8 output 3 \Y + cell $xor \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 8 + connect \A \A + connect \B \B + connect \Y \Y + end +end From 8cadb047bb07dcf0a285e1db0c81b3086bc0900d Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Thu, 6 Jun 2024 12:14:35 +0200 Subject: [PATCH 45/51] Move files --- .../single_cells/{ => rtlil}/test_cell_add_00000.il | 0 .../single_cells/{ => rtlil}/test_cell_alu_00000.il | 0 .../single_cells/{ => rtlil}/test_cell_and_00000.il | 0 .../single_cells/{ => rtlil}/test_cell_bmux_00000.il | 0 .../single_cells/{ => rtlil}/test_cell_demux_00000.il | 0 .../single_cells/{ => rtlil}/test_cell_div_00000.il | 0 .../{ => rtlil}/test_cell_divfloor_00000.il | 0 .../single_cells/{ => rtlil}/test_cell_eq_00000.il | 0 .../single_cells/{ => rtlil}/test_cell_fa_00000.il | 0 .../single_cells/{ => rtlil}/test_cell_ge_00000.il | 0 .../single_cells/{ => rtlil}/test_cell_gt_00000.il | 0 .../single_cells/{ => rtlil}/test_cell_lcu_00000.il | 0 .../single_cells/{ => rtlil}/test_cell_le_00000.il | 0 .../{ => rtlil}/test_cell_logic_and_00000.il | 0 .../{ => rtlil}/test_cell_logic_not_00000.il | 0 .../{ => rtlil}/test_cell_logic_or_00000.il | 0 .../single_cells/{ => rtlil}/test_cell_lt_00000.il | 0 .../single_cells/{ => rtlil}/test_cell_lut_00000.il | 0 .../single_cells/{ => rtlil}/test_cell_macc_00000.il | 0 .../single_cells/{ => rtlil}/test_cell_mod_00000.il | 0 .../{ => rtlil}/test_cell_modfloor_00000.il | 0 .../single_cells/{ => rtlil}/test_cell_mul_00000.il | 0 .../single_cells/{ => rtlil}/test_cell_mux_00000.il | 0 .../single_cells/{ => rtlil}/test_cell_ne_00000.il | 0 .../single_cells/{ => rtlil}/test_cell_neg_00000.il | 0 .../single_cells/{ => rtlil}/test_cell_not_00000.il | 0 .../single_cells/{ => rtlil}/test_cell_or_00000.il | 0 .../single_cells/{ => rtlil}/test_cell_pos_00000.il | 0 .../{ => rtlil}/test_cell_reduce_and_00000.il | 0 .../{ => rtlil}/test_cell_reduce_bool_00000.il | 0 .../{ => rtlil}/test_cell_reduce_or_00000.il | 0 .../{ => rtlil}/test_cell_reduce_xnor_00000.il | 0 .../{ => rtlil}/test_cell_reduce_xor_00000.il | 0 .../single_cells/{ => rtlil}/test_cell_shift_00000.il | 0 .../single_cells/{ => rtlil}/test_cell_shiftx_00000.il | 0 .../single_cells/{ => rtlil}/test_cell_shl_00000.il | 0 .../single_cells/{ => rtlil}/test_cell_shr_00000.il | 0 .../single_cells/{ => rtlil}/test_cell_sop_00000.il | 0 .../single_cells/{ => rtlil}/test_cell_sshl_00000.il | 0 .../single_cells/{ => rtlil}/test_cell_sshr_00000.il | 0 .../single_cells/{ => rtlil}/test_cell_sub_00000.il | 0 .../single_cells/{ => rtlil}/test_cell_xnor_00000.il | 0 .../single_cells/{ => rtlil}/test_cell_xor_00000.il | 0 tests/functional/single_cells/run-test.sh | 10 +++++----- 44 files changed, 5 insertions(+), 5 deletions(-) rename tests/functional/single_cells/{ => rtlil}/test_cell_add_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_alu_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_and_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_bmux_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_demux_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_div_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_divfloor_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_eq_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_fa_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_ge_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_gt_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_lcu_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_le_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_logic_and_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_logic_not_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_logic_or_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_lt_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_lut_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_macc_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_mod_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_modfloor_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_mul_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_mux_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_ne_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_neg_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_not_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_or_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_pos_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_reduce_and_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_reduce_bool_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_reduce_or_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_reduce_xnor_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_reduce_xor_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_shift_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_shiftx_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_shl_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_shr_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_sop_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_sshl_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_sshr_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_sub_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_xnor_00000.il (100%) rename tests/functional/single_cells/{ => rtlil}/test_cell_xor_00000.il (100%) diff --git a/tests/functional/single_cells/test_cell_add_00000.il b/tests/functional/single_cells/rtlil/test_cell_add_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_add_00000.il rename to tests/functional/single_cells/rtlil/test_cell_add_00000.il diff --git a/tests/functional/single_cells/test_cell_alu_00000.il b/tests/functional/single_cells/rtlil/test_cell_alu_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_alu_00000.il rename to tests/functional/single_cells/rtlil/test_cell_alu_00000.il diff --git a/tests/functional/single_cells/test_cell_and_00000.il b/tests/functional/single_cells/rtlil/test_cell_and_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_and_00000.il rename to tests/functional/single_cells/rtlil/test_cell_and_00000.il diff --git a/tests/functional/single_cells/test_cell_bmux_00000.il b/tests/functional/single_cells/rtlil/test_cell_bmux_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_bmux_00000.il rename to tests/functional/single_cells/rtlil/test_cell_bmux_00000.il diff --git a/tests/functional/single_cells/test_cell_demux_00000.il b/tests/functional/single_cells/rtlil/test_cell_demux_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_demux_00000.il rename to tests/functional/single_cells/rtlil/test_cell_demux_00000.il diff --git a/tests/functional/single_cells/test_cell_div_00000.il b/tests/functional/single_cells/rtlil/test_cell_div_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_div_00000.il rename to tests/functional/single_cells/rtlil/test_cell_div_00000.il diff --git a/tests/functional/single_cells/test_cell_divfloor_00000.il b/tests/functional/single_cells/rtlil/test_cell_divfloor_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_divfloor_00000.il rename to tests/functional/single_cells/rtlil/test_cell_divfloor_00000.il diff --git a/tests/functional/single_cells/test_cell_eq_00000.il b/tests/functional/single_cells/rtlil/test_cell_eq_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_eq_00000.il rename to tests/functional/single_cells/rtlil/test_cell_eq_00000.il diff --git a/tests/functional/single_cells/test_cell_fa_00000.il b/tests/functional/single_cells/rtlil/test_cell_fa_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_fa_00000.il rename to tests/functional/single_cells/rtlil/test_cell_fa_00000.il diff --git a/tests/functional/single_cells/test_cell_ge_00000.il b/tests/functional/single_cells/rtlil/test_cell_ge_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_ge_00000.il rename to tests/functional/single_cells/rtlil/test_cell_ge_00000.il diff --git a/tests/functional/single_cells/test_cell_gt_00000.il b/tests/functional/single_cells/rtlil/test_cell_gt_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_gt_00000.il rename to tests/functional/single_cells/rtlil/test_cell_gt_00000.il diff --git a/tests/functional/single_cells/test_cell_lcu_00000.il b/tests/functional/single_cells/rtlil/test_cell_lcu_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_lcu_00000.il rename to tests/functional/single_cells/rtlil/test_cell_lcu_00000.il diff --git a/tests/functional/single_cells/test_cell_le_00000.il b/tests/functional/single_cells/rtlil/test_cell_le_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_le_00000.il rename to tests/functional/single_cells/rtlil/test_cell_le_00000.il diff --git a/tests/functional/single_cells/test_cell_logic_and_00000.il b/tests/functional/single_cells/rtlil/test_cell_logic_and_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_logic_and_00000.il rename to tests/functional/single_cells/rtlil/test_cell_logic_and_00000.il diff --git a/tests/functional/single_cells/test_cell_logic_not_00000.il b/tests/functional/single_cells/rtlil/test_cell_logic_not_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_logic_not_00000.il rename to tests/functional/single_cells/rtlil/test_cell_logic_not_00000.il diff --git a/tests/functional/single_cells/test_cell_logic_or_00000.il b/tests/functional/single_cells/rtlil/test_cell_logic_or_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_logic_or_00000.il rename to tests/functional/single_cells/rtlil/test_cell_logic_or_00000.il diff --git a/tests/functional/single_cells/test_cell_lt_00000.il b/tests/functional/single_cells/rtlil/test_cell_lt_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_lt_00000.il rename to tests/functional/single_cells/rtlil/test_cell_lt_00000.il diff --git a/tests/functional/single_cells/test_cell_lut_00000.il b/tests/functional/single_cells/rtlil/test_cell_lut_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_lut_00000.il rename to tests/functional/single_cells/rtlil/test_cell_lut_00000.il diff --git a/tests/functional/single_cells/test_cell_macc_00000.il b/tests/functional/single_cells/rtlil/test_cell_macc_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_macc_00000.il rename to tests/functional/single_cells/rtlil/test_cell_macc_00000.il diff --git a/tests/functional/single_cells/test_cell_mod_00000.il b/tests/functional/single_cells/rtlil/test_cell_mod_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_mod_00000.il rename to tests/functional/single_cells/rtlil/test_cell_mod_00000.il diff --git a/tests/functional/single_cells/test_cell_modfloor_00000.il b/tests/functional/single_cells/rtlil/test_cell_modfloor_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_modfloor_00000.il rename to tests/functional/single_cells/rtlil/test_cell_modfloor_00000.il diff --git a/tests/functional/single_cells/test_cell_mul_00000.il b/tests/functional/single_cells/rtlil/test_cell_mul_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_mul_00000.il rename to tests/functional/single_cells/rtlil/test_cell_mul_00000.il diff --git a/tests/functional/single_cells/test_cell_mux_00000.il b/tests/functional/single_cells/rtlil/test_cell_mux_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_mux_00000.il rename to tests/functional/single_cells/rtlil/test_cell_mux_00000.il diff --git a/tests/functional/single_cells/test_cell_ne_00000.il b/tests/functional/single_cells/rtlil/test_cell_ne_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_ne_00000.il rename to tests/functional/single_cells/rtlil/test_cell_ne_00000.il diff --git a/tests/functional/single_cells/test_cell_neg_00000.il b/tests/functional/single_cells/rtlil/test_cell_neg_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_neg_00000.il rename to tests/functional/single_cells/rtlil/test_cell_neg_00000.il diff --git a/tests/functional/single_cells/test_cell_not_00000.il b/tests/functional/single_cells/rtlil/test_cell_not_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_not_00000.il rename to tests/functional/single_cells/rtlil/test_cell_not_00000.il diff --git a/tests/functional/single_cells/test_cell_or_00000.il b/tests/functional/single_cells/rtlil/test_cell_or_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_or_00000.il rename to tests/functional/single_cells/rtlil/test_cell_or_00000.il diff --git a/tests/functional/single_cells/test_cell_pos_00000.il b/tests/functional/single_cells/rtlil/test_cell_pos_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_pos_00000.il rename to tests/functional/single_cells/rtlil/test_cell_pos_00000.il diff --git a/tests/functional/single_cells/test_cell_reduce_and_00000.il b/tests/functional/single_cells/rtlil/test_cell_reduce_and_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_reduce_and_00000.il rename to tests/functional/single_cells/rtlil/test_cell_reduce_and_00000.il diff --git a/tests/functional/single_cells/test_cell_reduce_bool_00000.il b/tests/functional/single_cells/rtlil/test_cell_reduce_bool_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_reduce_bool_00000.il rename to tests/functional/single_cells/rtlil/test_cell_reduce_bool_00000.il diff --git a/tests/functional/single_cells/test_cell_reduce_or_00000.il b/tests/functional/single_cells/rtlil/test_cell_reduce_or_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_reduce_or_00000.il rename to tests/functional/single_cells/rtlil/test_cell_reduce_or_00000.il diff --git a/tests/functional/single_cells/test_cell_reduce_xnor_00000.il b/tests/functional/single_cells/rtlil/test_cell_reduce_xnor_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_reduce_xnor_00000.il rename to tests/functional/single_cells/rtlil/test_cell_reduce_xnor_00000.il diff --git a/tests/functional/single_cells/test_cell_reduce_xor_00000.il b/tests/functional/single_cells/rtlil/test_cell_reduce_xor_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_reduce_xor_00000.il rename to tests/functional/single_cells/rtlil/test_cell_reduce_xor_00000.il diff --git a/tests/functional/single_cells/test_cell_shift_00000.il b/tests/functional/single_cells/rtlil/test_cell_shift_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_shift_00000.il rename to tests/functional/single_cells/rtlil/test_cell_shift_00000.il diff --git a/tests/functional/single_cells/test_cell_shiftx_00000.il b/tests/functional/single_cells/rtlil/test_cell_shiftx_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_shiftx_00000.il rename to tests/functional/single_cells/rtlil/test_cell_shiftx_00000.il diff --git a/tests/functional/single_cells/test_cell_shl_00000.il b/tests/functional/single_cells/rtlil/test_cell_shl_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_shl_00000.il rename to tests/functional/single_cells/rtlil/test_cell_shl_00000.il diff --git a/tests/functional/single_cells/test_cell_shr_00000.il b/tests/functional/single_cells/rtlil/test_cell_shr_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_shr_00000.il rename to tests/functional/single_cells/rtlil/test_cell_shr_00000.il diff --git a/tests/functional/single_cells/test_cell_sop_00000.il b/tests/functional/single_cells/rtlil/test_cell_sop_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_sop_00000.il rename to tests/functional/single_cells/rtlil/test_cell_sop_00000.il diff --git a/tests/functional/single_cells/test_cell_sshl_00000.il b/tests/functional/single_cells/rtlil/test_cell_sshl_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_sshl_00000.il rename to tests/functional/single_cells/rtlil/test_cell_sshl_00000.il diff --git a/tests/functional/single_cells/test_cell_sshr_00000.il b/tests/functional/single_cells/rtlil/test_cell_sshr_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_sshr_00000.il rename to tests/functional/single_cells/rtlil/test_cell_sshr_00000.il diff --git a/tests/functional/single_cells/test_cell_sub_00000.il b/tests/functional/single_cells/rtlil/test_cell_sub_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_sub_00000.il rename to tests/functional/single_cells/rtlil/test_cell_sub_00000.il diff --git a/tests/functional/single_cells/test_cell_xnor_00000.il b/tests/functional/single_cells/rtlil/test_cell_xnor_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_xnor_00000.il rename to tests/functional/single_cells/rtlil/test_cell_xnor_00000.il diff --git a/tests/functional/single_cells/test_cell_xor_00000.il b/tests/functional/single_cells/rtlil/test_cell_xor_00000.il similarity index 100% rename from tests/functional/single_cells/test_cell_xor_00000.il rename to tests/functional/single_cells/rtlil/test_cell_xor_00000.il diff --git a/tests/functional/single_cells/run-test.sh b/tests/functional/single_cells/run-test.sh index 5f08b82ac68..b9828ff84ad 100755 --- a/tests/functional/single_cells/run-test.sh +++ b/tests/functional/single_cells/run-test.sh @@ -1,9 +1,9 @@ #!/bin/bash -# Initialize an array to store the names of failing Verilog files and their failure types +# Initialize an array to store the names of failing RTLIL files and their failure types declare -A failing_files -# Function to run the test on a given Verilog file +# Function to run the test on a given RTLIL file run_test() { # Define the common variable for the relative path BASE_PATH="../../../" @@ -13,7 +13,7 @@ run_test() { # Extract the base name without extension local base_name=$(basename "$verilog_file" .v) - # Run yosys to process each Verilog file + # Run yosys to process each RTLIL file if ${BASE_PATH}yosys -p "read_verilog $verilog_file; write_functional_cxx my_module_functional_cxx.cc"; then echo "Yosys processed $verilog_file successfully." @@ -23,7 +23,7 @@ run_test() { # Generate VCD files with base_name if ./vcd_harness ${base_name}_functional_cxx.vcd; then - # Run yosys to process each Verilog file + # Run yosys to process each RTLIL file if ${BASE_PATH}yosys -p "read_verilog $verilog_file; sim -r ${base_name}_functional_cxx.vcd -scope my_module -vcd ${base_name}_yosys_sim.vcd -timescale 1us -sim-gold"; then echo "Yosys sim $verilog_file successfully." else @@ -44,7 +44,7 @@ run_test() { # Main function to run all tests run_all_tests() { - # Loop through all Verilog files in the verilog directory + # Loop through all RTLIL files in the verilog directory for verilog_file in verilog/*.v; do run_test "$verilog_file" done From 5929df23af947550e64d1d08b03bcec323231317 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Thu, 6 Jun 2024 15:55:16 +0200 Subject: [PATCH 46/51] WIP --- tests/functional/single_cells/add_rtlil.cc | 79 ++++++++++++ tests/functional/single_cells/run-test.sh | 62 ++++----- tests/functional/single_cells/vcd_harness.cc | 127 +++++++++++++++++++ 3 files changed, 239 insertions(+), 29 deletions(-) create mode 100644 tests/functional/single_cells/add_rtlil.cc create mode 100644 tests/functional/single_cells/vcd_harness.cc diff --git a/tests/functional/single_cells/add_rtlil.cc b/tests/functional/single_cells/add_rtlil.cc new file mode 100644 index 00000000000..22795b351a6 --- /dev/null +++ b/tests/functional/single_cells/add_rtlil.cc @@ -0,0 +1,79 @@ +#include + +#if defined(CXXRTL_INCLUDE_CAPI_IMPL) || \ + defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL) +#include +#endif + +#if defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL) +#include +#endif + +using namespace cxxrtl_yosys; + +namespace cxxrtl_design { + +// \top: 1 +struct p_gold : public module { + /*output*/ value<6> p_Y; + /*input*/ value<4> p_B; + /*input*/ value<5> p_A; + p_gold(interior) {} + p_gold() { + reset(); + }; + + void reset() override; + + bool eval(performer *performer = nullptr) override; + + template + bool commit(ObserverT &observer) { + bool changed = false; + return changed; + } + + bool commit() override { + observer observer; + return commit<>(observer); + } + + void debug_eval(); + + void debug_info(debug_items *items, debug_scopes *scopes, std::string path, metadata_map &&cell_attrs = {}) override; +}; // struct p_gold + +void p_gold::reset() { +} + +bool p_gold::eval(performer *performer) { + bool converged = true; + // cell \UUT + p_Y = add_ss<6>(p_A, p_B); + return converged; +} + +void p_gold::debug_eval() { +} + +CXXRTL_EXTREMELY_COLD +void p_gold::debug_info(debug_items *items, debug_scopes *scopes, std::string path, metadata_map &&cell_attrs) { + assert(path.empty() || path[path.size() - 1] == ' '); + if (scopes) { + scopes->add(path.empty() ? path : path.substr(0, path.size() - 1), "gold", metadata_map({ + { "top", UINT64_C(1) }, + }), std::move(cell_attrs)); + } + if (items) { + items->add(path, "Y", "", p_Y, 0, debug_item::OUTPUT|debug_item::DRIVEN_COMB); + items->add(path, "B", "", p_B, 0, debug_item::INPUT|debug_item::UNDRIVEN); + items->add(path, "A", "", p_A, 0, debug_item::INPUT|debug_item::UNDRIVEN); + } +} + +} // namespace cxxrtl_design + +extern "C" +cxxrtl_toplevel cxxrtl_design_create() { + return new _cxxrtl_toplevel { std::unique_ptr(new cxxrtl_design::p_gold) }; +} diff --git a/tests/functional/single_cells/run-test.sh b/tests/functional/single_cells/run-test.sh index b9828ff84ad..017b3349d61 100755 --- a/tests/functional/single_cells/run-test.sh +++ b/tests/functional/single_cells/run-test.sh @@ -8,45 +8,49 @@ run_test() { # Define the common variable for the relative path BASE_PATH="../../../" - local verilog_file=$1 + local rtlil_file=$1 # Extract the base name without extension - local base_name=$(basename "$verilog_file" .v) + local base_name=$(basename "$rtlil_file" .v) # Run yosys to process each RTLIL file - if ${BASE_PATH}yosys -p "read_verilog $verilog_file; write_functional_cxx my_module_functional_cxx.cc"; then - echo "Yosys processed $verilog_file successfully." + if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; write_functional_cxx my_module_functional_cxx.cc"; then + echo "Yosys processed $rtlil_file successfully." # Compile the generated C++ files with vcd_harness.cpp - ${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cc -I ${BASE_PATH}backends/functional/cxx_runtime/ -o vcd_harness - - # Generate VCD files with base_name - if ./vcd_harness ${base_name}_functional_cxx.vcd; then - - # Run yosys to process each RTLIL file - if ${BASE_PATH}yosys -p "read_verilog $verilog_file; sim -r ${base_name}_functional_cxx.vcd -scope my_module -vcd ${base_name}_yosys_sim.vcd -timescale 1us -sim-gold"; then - echo "Yosys sim $verilog_file successfully." - else - ${BASE_PATH}yosys -p "read_verilog $verilog_file; sim -vcd ${base_name}_yosys_sim.vcd -r ${base_name}_functional_cxx.vcd -scope my_module -timescale 1us" - echo "Yosys simulation of $verilog_file failed. There is a discrepancy with functional cxx" - failing_files["$verilog_file"]="Yosys sim failure" - fi - - else - echo "Failed to generate VCD files for $verilog_file." - failing_files["$verilog_file"]="VCD generation failure" - fi - else - echo "Yosys failed to process $verilog_file." - failing_files["$verilog_file"]="Yosys failure" - fi + if ${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cc -I ${BASE_PATH}backends/functional/cxx_runtime/ -o vcd_harness; then + echo "Compilation successful." + # Generate VCD files with base_name + if ./vcd_harness ${base_name}_functional_cxx.vcd; then + + # Run yosys to process each RTLIL file + if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -r ${base_name}_functional_cxx.vcd -scope gold -vcd ${base_name}_yosys_sim.vcd -timescale 1us -sim-gold"; then + echo "Yosys sim $rtlil_file successfully." + else + ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -vcd ${base_name}_yosys_sim.vcd -r ${base_name}_functional_cxx.vcd -scope my_module -timescale 1us" + echo "Yosys simulation of $rtlil_file failed. There is a discrepancy with functional cxx" + failing_files["$rtlil_file"]="Yosys sim failure" + fi + + else + echo "Failed to generate VCD files for $rtlil_file." + failing_files["$rtlil_file"]="VCD generation failure" + fi + else + echo "Failed to compile harness for $rtlil_file." + failing_files["$rtlil_file"]="Compilation failure" + fi + else + echo "Yosys failed to process $rtlil_file." + failing_files["$rtlil_file"]="Yosys failure" + fi } # Main function to run all tests run_all_tests() { - # Loop through all RTLIL files in the verilog directory - for verilog_file in verilog/*.v; do - run_test "$verilog_file" + # Loop through all RTLIL files in the rtlil directory + for rtlil_file in rtlil/*.il; do + run_test "$rtlil_file" done # Check if the array of failing files is empty diff --git a/tests/functional/single_cells/vcd_harness.cc b/tests/functional/single_cells/vcd_harness.cc new file mode 100644 index 00000000000..6051306c8d6 --- /dev/null +++ b/tests/functional/single_cells/vcd_harness.cc @@ -0,0 +1,127 @@ +#include +#include +#include +#include + +#include "my_module_functional_cxx.cc" + +struct DumpHeader { + std::ofstream &ofs; + DumpHeader(std::ofstream &ofs) : ofs(ofs) {} + template + void operator()(const char *name, Signal value) { + ofs << "$var wire " << n << " " << name[0] << " " << name << " $end\n"; + } +}; + +struct Dump { + std::ofstream &ofs; + Dump(std::ofstream &ofs) : ofs(ofs) {} + template + void operator()(const char *name, Signal value) { + // Bit + if (n == 1) { + ofs << (value[0] ? '1' : '0'); + ofs << name[0] << "\n"; + return; + } + // vector (multi-bit) signals + ofs << "b"; + for (size_t i = n; i-- > 0;) + ofs << (value[i] ? '1' : '0'); + ofs << " " << name[0] << "\n"; + } +}; + +// Function to set all values in a signal to false +template +void set_all_false(Signal& signal) { + std::fill(signal.begin(), signal.end(), false); +} + +template +void set_all_random(Signal& signal) { + std::random_device rd; // Random device for seeding + std::mt19937 gen(rd()); // Mersenne Twister engine + std::bernoulli_distribution dist(0.5); // 50-50 distribution + + for (auto& value : signal) { + value = dist(gen); // Set each value to a random boolean + } +} + +int main(int argc, char **argv) +{ + if (argc != 2) { + std::cerr << "Usage: " << argv[0] << " \n"; + return 1; + } + + const std::string functional_vcd_filename = argv[1]; + + constexpr int steps = 10; + constexpr int number_timescale = 1; + const std::string units_timescale = "us"; + gold_Inputs inputs; + gold_Outputs outputs; + gold_State state; + gold_State next_state; + + std::ofstream vcd_file(functional_vcd_filename); + + vcd_file << "$timescale " << number_timescale << " " << units_timescale << " $end\n"; + vcd_file << "$scope module gold $end\n"; + { + DumpHeader d(vcd_file); + inputs.dump(d); + outputs.dump(d); + state.dump(d); + } + vcd_file << "$enddefinitions $end\n$dumpvars\n"; + vcd_file << "#0\n"; + // Set all signals to false + for (int i = 0; i < inputs.size(); ++i) { + auto input_variant = inputs.get_input(i); + std::visit([](auto& signal_ref) { + set_all_false(signal_ref.get()); + }, input_variant); + } + + gold(inputs, outputs, state, next_state); + { + Dump d(vcd_file); + inputs.dump(d); + outputs.dump(d); + state.dump(d); + } + + std::random_device rd; + std::mt19937 gen(rd()); + std::bernoulli_distribution dist(0.5); + + for (int step = 0; step < steps; ++step) { + // Functional backend cxx + vcd_file << "#" << (step + 1) << "\n"; + // Set all signals to random + for (int i = 0; i < inputs.size(); ++i) { + auto input_variant = inputs.get_input(i); + std::visit([](auto& signal_ref) { + set_all_random(signal_ref.get()); + }, input_variant); + } + + gold(inputs, outputs, state, next_state); + { + Dump d(vcd_file); + inputs.dump(d); + outputs.dump(d); + state.dump(d); + } + + state = next_state; + } + + vcd_file.close(); + + return 0; +} From 6f38d5f1e4cbef4f80c81e05d540f680c5628ab1 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Thu, 6 Jun 2024 16:20:03 +0200 Subject: [PATCH 47/51] WIP --- backends/functional/Makefile.inc | 4 +-- backends/functional/cxx.cc | 46 ++++++++++++++++++++++++++---- my_module_functional_cxx.cc | 48 ++++++++++++++++++++++++++++++++ 3 files changed, 91 insertions(+), 7 deletions(-) create mode 100644 my_module_functional_cxx.cc diff --git a/backends/functional/Makefile.inc b/backends/functional/Makefile.inc index 5776bf84ed9..675153c95b0 100644 --- a/backends/functional/Makefile.inc +++ b/backends/functional/Makefile.inc @@ -1,4 +1,4 @@ -# OBJS += backends/functional/cxx.o +OBJS += backends/functional/cxx.o # OBJS += backends/functional/smtlib.o -OBJS += backends/functional/alternative_cxx.o +# OBJS += backends/functional/alternative_cxx.o # OBJS += backends/functional/alternative_smtlib.o diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index f0ceb5d76d4..8aaed5482fe 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -101,7 +101,10 @@ struct CxxStruct { std::string name; dict types; CxxScope scope; - CxxStruct(std::string name) : name(name) { + bool generate_methods; + int count; + CxxStruct(std::string name, bool generate_methods = false, int count = 0) + : name(name), generate_methods(generate_methods), count(count) { scope.reserve("out"); scope.reserve("dump"); } @@ -114,15 +117,47 @@ struct CxxStruct { for (auto p : types) { f.printf("\t%s %s;\n", p.second.c_str(), scope[p.first].c_str()); } - f.printf("\n\ttemplate void dump(T &out) {\n"); + f.printf("\n\ttemplate void dump(T &out) const {\n"); for (auto p : types) { f.printf("\t\tout(\"%s\", %s);\n", RTLIL::unescape_id(p.first).c_str(), scope[p.first].c_str()); } - f.printf("\t}\n};\n\n"); - } + f.printf("\t}\n\n"); + + if (generate_methods) { + // Add size method + f.printf("\tint size() const {\n"); + f.printf("\t\treturn %d;\n", count); + f.printf("\t}\n\n"); + + // Add get_input method + f.printf("\tstd::variant<%s> get_input(const int index) {\n", generate_variant_types().c_str()); + f.printf("\t\tswitch (index) {\n"); + int idx = 0; + for (auto p : types) { + f.printf("\t\t\tcase %d: return std::ref(%s);\n", idx, scope[p.first].c_str()); + idx++; + } + f.printf("\t\t\tdefault: throw std::out_of_range(\"Invalid input index\");\n"); + f.printf("\t\t}\n"); + f.printf("\t}\n"); + } + + f.printf("};\n\n"); + }; std::string operator[](IdString field) { return scope[field]; } + private: + std::string generate_variant_types() const { + std::string variant_types; + for (const auto& p : types) { + if (!variant_types.empty()) { + variant_types += ", "; + } + variant_types += "std::reference_wrapper<" + p.second + ">"; + } + return variant_types; + } }; struct CxxFunction { @@ -307,7 +342,8 @@ struct FunctionalCxxBackend : public Backend state[ref.function().parameters.begin()->first] = ref.function().width; } f.printf("#include \"sim.h\"\n"); - CxxStruct input_struct(name + "_Inputs"); + f.printf("#include \n"); + CxxStruct input_struct(name + "_Inputs", true, inputs.size()); for (auto const &input : inputs) input_struct.insert(input.first, "Signal<" + std::to_string(input.second) + ">"); CxxStruct output_struct(name + "_Outputs"); diff --git a/my_module_functional_cxx.cc b/my_module_functional_cxx.cc new file mode 100644 index 00000000000..495813c0dec --- /dev/null +++ b/my_module_functional_cxx.cc @@ -0,0 +1,48 @@ +#include "sim.h" +struct gold_Inputs { + Signal<4> B; + Signal<5> A; + + template void dump(T &out) const { + out("B", B); + out("A", A); + } + + int size() const { + return 2; + } + + std::variant>, std::reference_wrapper>> get_input(const int index) const { + switch (index) { + case 0: return std::ref(B); + case 1: return std::ref(A); + default: throw std::out_of_range("Invalid input index"); + } + } +}; + +struct gold_Outputs { + Signal<6> Y; + + template void dump(T &out) const { + out("Y", Y); + } + +}; + +struct gold_State { + + template void dump(T &out) const { + } + +}; + +void gold(gold_Inputs const &input, gold_Outputs &output, gold_State const ¤t_state, gold_State &next_state) +{ + Signal<4> B = input.B; + Signal<5> A = input.A; + Signal<6> n2 = $sign_extend<6>(A); //[WIDTH=6] + Signal<6> n3 = $sign_extend<6>(B); //[WIDTH=6] + Signal<6> UUT$_Y = $add(n2, n3); // + output.Y = UUT$_Y; +} From 89f124eb287b937d78f5099d4af5e444f035ec5f Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Thu, 6 Jun 2024 16:38:14 +0200 Subject: [PATCH 48/51] Compile with C++17 --- tests/functional/single_cells/run-test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/functional/single_cells/run-test.sh b/tests/functional/single_cells/run-test.sh index 017b3349d61..f87be8ebaf5 100755 --- a/tests/functional/single_cells/run-test.sh +++ b/tests/functional/single_cells/run-test.sh @@ -18,7 +18,7 @@ run_test() { echo "Yosys processed $rtlil_file successfully." # Compile the generated C++ files with vcd_harness.cpp - if ${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cc -I ${BASE_PATH}backends/functional/cxx_runtime/ -o vcd_harness; then + if ${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cc -I ${BASE_PATH}backends/functional/cxx_runtime/ -std=c++17 -o vcd_harness; then echo "Compilation successful." # Generate VCD files with base_name if ./vcd_harness ${base_name}_functional_cxx.vcd; then From 3a9a55e05140dd50304a54052b8963ae81842f66 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Thu, 6 Jun 2024 16:46:59 +0200 Subject: [PATCH 49/51] Set on unique types for variant --- backends/functional/cxx.cc | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index 8aaed5482fe..169df74621f 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -148,16 +148,20 @@ struct CxxStruct { return scope[field]; } private: - std::string generate_variant_types() const { - std::string variant_types; + std::string generate_variant_types() const { + std::set unique_types; for (const auto& p : types) { - if (!variant_types.empty()) { - variant_types += ", "; + unique_types.insert("std::reference_wrapper<" + p.second + ">"); + } + std::ostringstream oss; + for (auto it = unique_types.begin(); it != unique_types.end(); ++it) { + if (it != unique_types.begin()) { + oss << ", "; } - variant_types += "std::reference_wrapper<" + p.second + ">"; + oss << *it; } - return variant_types; - } + return oss.str(); + } }; struct CxxFunction { From a4d5d9a6f0bd990df8e4d65525c566ef61523075 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Thu, 6 Jun 2024 16:50:41 +0200 Subject: [PATCH 50/51] scope is gold, not my_module --- tests/functional/single_cells/run-test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/functional/single_cells/run-test.sh b/tests/functional/single_cells/run-test.sh index f87be8ebaf5..a2741060734 100755 --- a/tests/functional/single_cells/run-test.sh +++ b/tests/functional/single_cells/run-test.sh @@ -27,7 +27,7 @@ run_test() { if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -r ${base_name}_functional_cxx.vcd -scope gold -vcd ${base_name}_yosys_sim.vcd -timescale 1us -sim-gold"; then echo "Yosys sim $rtlil_file successfully." else - ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -vcd ${base_name}_yosys_sim.vcd -r ${base_name}_functional_cxx.vcd -scope my_module -timescale 1us" + ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -vcd ${base_name}_yosys_sim.vcd -r ${base_name}_functional_cxx.vcd -scope gold -timescale 1us" echo "Yosys simulation of $rtlil_file failed. There is a discrepancy with functional cxx" failing_files["$rtlil_file"]="Yosys sim failure" fi From fb6511b6e8808ad42b850e67ba65d0446bb8c44c Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Thu, 6 Jun 2024 17:13:24 +0200 Subject: [PATCH 51/51] =?UTF-8?q?=C2=B4Print=20also=20successful=20files?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tests/functional/single_cells/run-test.sh | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/tests/functional/single_cells/run-test.sh b/tests/functional/single_cells/run-test.sh index a2741060734..67cdf4a11c4 100755 --- a/tests/functional/single_cells/run-test.sh +++ b/tests/functional/single_cells/run-test.sh @@ -2,6 +2,8 @@ # Initialize an array to store the names of failing RTLIL files and their failure types declare -A failing_files +# Initialize an array to store the names of successful RTLIL files +declare -A successful_files # Function to run the test on a given RTLIL file run_test() { @@ -26,6 +28,7 @@ run_test() { # Run yosys to process each RTLIL file if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -r ${base_name}_functional_cxx.vcd -scope gold -vcd ${base_name}_yosys_sim.vcd -timescale 1us -sim-gold"; then echo "Yosys sim $rtlil_file successfully." + successful_files["$rtlil_file"]="Success" else ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -vcd ${base_name}_yosys_sim.vcd -r ${base_name}_functional_cxx.vcd -scope gold -timescale 1us" echo "Yosys simulation of $rtlil_file failed. There is a discrepancy with functional cxx" @@ -56,12 +59,20 @@ run_all_tests() { # Check if the array of failing files is empty if [ ${#failing_files[@]} -eq 0 ]; then echo "All files passed." + echo "The following files passed:" + for file in "${!successful_files[@]}"; do + echo "$file" + done return 0 else echo "The following files failed:" for file in "${!failing_files[@]}"; do echo "$file: ${failing_files[$file]}" done + echo "The following files passed:" + for file in "${!successful_files[@]}"; do + echo "$file" + done return 1 fi }