From 5d61ec5aa087b6e3918c67f6fcabdc20fa26f0bc Mon Sep 17 00:00:00 2001
From: Amiot Noe <noe.amiot@lip6.fr>
Date: Tue, 21 May 2024 21:47:00 +0200
Subject: [PATCH] cxxrtl: Prevent wires with input or output ports from being
 aliased

---
 backends/cxxrtl/cxxrtl_backend.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc
index 703494682a8..9ddbd33b0a3 100644
--- a/backends/cxxrtl/cxxrtl_backend.cc
+++ b/backends/cxxrtl/cxxrtl_backend.cc
@@ -3263,6 +3263,7 @@ struct CxxrtlWorker {
 						debug_wire_type = wire_type; // wire is a member
 
 					if (!debug_alias) continue;
+					if (wire->port_input || wire->port_output) continue; // preserve input/output metadata in flags
 					const RTLIL::Wire *it = wire;
 					while (flow.is_inlinable(it)) {
 						log_assert(flow.wire_comb_defs[it].size() == 1);