From dc693652583e83db82cc95c407e4778e640473d7 Mon Sep 17 00:00:00 2001
From: Asherah Connor <ashe@kivikakk.ee>
Date: Sun, 26 May 2024 18:21:45 +0300
Subject: [PATCH 1/2] cxxrtl: failing test: unconnected blackbox outputs don't
 compile.

---
 tests/cxxrtl/run-test.sh               |  4 ++++
 tests/cxxrtl/test_unconnected_output.v | 24 ++++++++++++++++++++++++
 2 files changed, 28 insertions(+)
 create mode 100644 tests/cxxrtl/test_unconnected_output.v

diff --git a/tests/cxxrtl/run-test.sh b/tests/cxxrtl/run-test.sh
index 89de71c6b26..fd11a378379 100755
--- a/tests/cxxrtl/run-test.sh
+++ b/tests/cxxrtl/run-test.sh
@@ -11,3 +11,7 @@ run_subtest () {
 
 run_subtest value
 run_subtest value_fuzz
+
+# Compile-only test.
+../../yosys -p "read_verilog test_unconnected_output.v; proc; clean; write_cxxrtl cxxrtl-test-unconnected_output.cc"
+${CC:-gcc} -std=c++11 -c -o cxxrtl-test-unconnected_output -I../../backends/cxxrtl/runtime cxxrtl-test-unconnected_output.cc
diff --git a/tests/cxxrtl/test_unconnected_output.v b/tests/cxxrtl/test_unconnected_output.v
new file mode 100644
index 00000000000..84d172bdbbf
--- /dev/null
+++ b/tests/cxxrtl/test_unconnected_output.v
@@ -0,0 +1,24 @@
+(* cxxrtl_blackbox *)
+module blackbox(...);
+    (* cxxrtl_edge = "p" *)
+    input clk;
+
+    (* cxxrtl_sync *)
+    output [7:0] out1;
+
+    (* cxxrtl_sync *)
+    output [7:0] out2;
+endmodule
+
+module unconnected_output(
+    input  clk,
+           in,
+    output out
+);
+    blackbox bb (
+        .clock (clock),
+        .in    (in),
+        .out1  (out),
+        .out2  (/* unconnected */),
+    );
+endmodule

From e97c36d4c4189d57eb84e8d6f57de85dfdd551f8 Mon Sep 17 00:00:00 2001
From: Asherah Connor <ashe@kivikakk.ee>
Date: Sun, 26 May 2024 18:31:32 +0300
Subject: [PATCH 2/2] cxxrtl: don't emit syncs for empty lhs.

---
 backends/cxxrtl/cxxrtl_backend.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc
index 9ddbd33b0a3..8dc14863d60 100644
--- a/backends/cxxrtl/cxxrtl_backend.cc
+++ b/backends/cxxrtl/cxxrtl_backend.cc
@@ -1138,7 +1138,7 @@ struct CxxrtlWorker {
 		f << indent << "// cell " << cell->name.str() << " syncs\n";
 		for (auto conn : cell->connections())
 			if (cell->output(conn.first))
-				if (is_cxxrtl_sync_port(cell, conn.first)) {
+				if (is_cxxrtl_sync_port(cell, conn.first) && !conn.second.empty()) {
 					f << indent;
 					dump_sigspec_lhs(conn.second, for_debug);
 					f << " = " << mangle(cell) << access << mangle_wire_name(conn.first) << ".curr;\n";