diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index c36a38daef7..d27878fa78f 100644
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -89,6 +89,9 @@ struct OptReduceWorker
 		RTLIL::SigSpec new_sig_a(new_sig_a_bits);
 		new_sig_a.sort_and_unify();
 
+		if (GetSize(new_sig_a) == 0)
+			new_sig_a = (cell->type == ID($reduce_or)) ? State::S0 : State::S1;
+
 		if (new_sig_a != sig_a || sig_a.size() != cell->getPort(ID::A).size()) {
 			log("    New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
 			did_something = true;
diff --git a/tests/opt/opt_reduce_andor.ys b/tests/opt/opt_reduce_andor.ys
new file mode 100644
index 00000000000..b570365288b
--- /dev/null
+++ b/tests/opt/opt_reduce_andor.ys
@@ -0,0 +1,14 @@
+# Check that opt_reduce doesn't produce zero width $reduce_or/$reduce_and,
+
+read_verilog <<EOT
+module reduce_const(output wire o, output wire a);
+    wire [3:0] zero = 4'b0000;
+    wire [3:0] ones = 4'b1111;
+    assign o = |zero;
+    assign a = &ones;
+endmodule
+EOT
+
+equiv_opt -assert opt_reduce
+design -load postopt
+select -assert-none r:A_WIDTH=0