From 023f029dcfa488410e1261c200f07f6af46b8a48 Mon Sep 17 00:00:00 2001 From: George Rennie Date: Wed, 25 Sep 2024 16:20:29 +0100 Subject: [PATCH 1/2] opt_reduce: keep at least one input to $reduce_or/and cells --- passes/opt/opt_reduce.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index c36a38daef7..d27878fa78f 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -89,6 +89,9 @@ struct OptReduceWorker RTLIL::SigSpec new_sig_a(new_sig_a_bits); new_sig_a.sort_and_unify(); + if (GetSize(new_sig_a) == 0) + new_sig_a = (cell->type == ID($reduce_or)) ? State::S0 : State::S1; + if (new_sig_a != sig_a || sig_a.size() != cell->getPort(ID::A).size()) { log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a)); did_something = true; From 0572f8806f25dcf543215a47d08bb0f57a74ba7e Mon Sep 17 00:00:00 2001 From: George Rennie Date: Wed, 25 Sep 2024 16:28:41 +0100 Subject: [PATCH 2/2] opt_reduce: add test for constant $reduce_and/or not being zero width --- tests/opt/opt_reduce_andor.ys | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 tests/opt/opt_reduce_andor.ys diff --git a/tests/opt/opt_reduce_andor.ys b/tests/opt/opt_reduce_andor.ys new file mode 100644 index 00000000000..b570365288b --- /dev/null +++ b/tests/opt/opt_reduce_andor.ys @@ -0,0 +1,14 @@ +# Check that opt_reduce doesn't produce zero width $reduce_or/$reduce_and, + +read_verilog <