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Pull requests: YosysHQ/yosys

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Pull requests list

wreduce: Optimize signedness when possible
#4819 opened Dec 16, 2024 by povik Loading…
Add $macc_v2
#4818 opened Dec 13, 2024 by povik Draft
3 of 14 tasks
macc: Stop using the B port
#4817 opened Dec 13, 2024 by povik Loading…
Add -blackbox option to setundef pass
#4812 opened Dec 10, 2024 by KrystalDelusion Loading…
2 of 3 tasks
qlf_k6n10f: leave unused clocks disconnected
#4796 opened Dec 3, 2024 by Ravenslofty Loading…
Refactor full_selection
#4768 opened Nov 25, 2024 by KrystalDelusion Loading…
2 of 4 tasks
Add Optimization Barriers
#4763 opened Nov 20, 2024 by georgerennie Loading…
write_verilog: Lower $bwmux in expr mode
#4752 opened Nov 15, 2024 by povik Loading…
cxxrtl: strip $paramod from module name in scope info
#4745 opened Nov 14, 2024 by whitequark Loading…
Add splitfanout pass
#4741 opened Nov 14, 2024 by akashlevy Loading…
9 of 10 tasks
Add muldiv_c and muxadd peepopts
#4740 opened Nov 13, 2024 by akashlevy Loading…
23 of 24 tasks
synth_quicklogic: add -noflatten option
#4735 opened Nov 13, 2024 by nakengelhardt Loading…
Fix setting bits of parameters in setundef pass
#4733 opened Nov 12, 2024 by kamilrakoczy Loading…
write_btor: support $buf
#4711 opened Nov 6, 2024 by georgerennie Loading…
extract_fa: Fix xor3/xnor3 inversion bug
#4691 opened Oct 30, 2024 by hovind Loading…
Prepend Verilog globals to module AST
#4656 opened Oct 11, 2024 by jmi2k Loading…
Allow whitespace in tee command paths
#4619 opened Sep 29, 2024 by malmeloo Loading…
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