From 1d0ec55c870f7bee655669b400381fbce1e17ec5 Mon Sep 17 00:00:00 2001 From: Ziang Date: Wed, 11 Dec 2019 22:21:38 -0500 Subject: [PATCH] Corrected wrong validation of spectre attack Project accomplished --- FU.cpp | 19 +- ROB.cpp | 2 +- branch.cpp | 4 +- branch.h | 2 +- clock.cpp | 2 +- FU.h => headers/FU.h | 0 ROB.h => headers/ROB.h | 0 headers/branch.h | 48 + clock.h => headers/clock.h | 0 import.h => headers/import.h | 0 instruction.h => headers/instruction.h | 0 issue.h => headers/issue.h | 0 memory.h => headers/memory.h | 0 mips.h => headers/mips.h | 0 output.h => headers/output.h | 0 registor.h => headers/registor.h | 0 reserv_station.h => headers/reserv_station.h | 0 import.cpp | 2 +- instruction.cpp | 2 +- issue.cpp | 4 +- memory.cpp | 2 +- mips.cpp | 2 +- output.cpp | 2 +- registor.cpp | 2 +- reserv_station.cpp | 4 +- .../attacked_code.txt | 0 .../example_Case1.txt => test_case/case1.txt | 0 test_case/case10.txt | 17 + .../case11.txt | 0 .../example_Case2.txt => test_case/case2.txt | 0 .../example_Case3.txt => test_case/case3.txt | 0 .../example_Case4.txt => test_case/case4.txt | 0 .../example_Case5.txt => test_case/case5.txt | 0 .../example_Case6.txt => test_case/case6.txt | 0 .../example_Case7.txt => test_case/case7.txt | 0 .../example_Case8.txt => test_case/case8.txt | 0 .../example_Case9.txt => test_case/case9.txt | 0 test_case/the_test_case.txt | 20 + test_case/victim_code.txt | 23 + tumasulu/.gitignore | 40 - tumasulu/ExeTable.h | 16 - tumasulu/Import.cpp | 254 -- tumasulu/Import.h | 46 - tumasulu/InputTest.txt | 25 - tumasulu/InstBuffer.h | 15 - tumasulu/LdSdQueue.h | 19 - tumasulu/Memory.h | 17 - tumasulu/Output.h | 124 - tumasulu/RAT.h | 13 - tumasulu/ROB.h | 18 - tumasulu/RegFiles.h | 11 - tumasulu/RsFU.h | 22 - tumasulu/RsIU.h | 22 - tumasulu/extable.csv | 12 - tumasulu/extable.txt | 13 - tumasulu/queue.h | 33 - tumasulu/test.txt | 19 - tumasulu/test_cases/Output File1.csv | 32 - tumasulu/test_cases/Output File12.csv | 120 - tumasulu/test_cases/Output File2.csv | 32 - tumasulu/test_cases/Output File3.csv | 32 - tumasulu/test_cases/Output File4.csv | 32 - tumasulu/test_cases/Output File5.csv | 32 - tumasulu/test_cases/Output File7.csv | 32 - tumasulu/test_cases/Output File8.csv | 120 - tumasulu/tumasulu.cpp | 2256 ----------------- 66 files changed, 138 insertions(+), 3426 deletions(-) rename FU.h => headers/FU.h (100%) rename ROB.h => headers/ROB.h (100%) create mode 100644 headers/branch.h rename clock.h => headers/clock.h (100%) rename import.h => headers/import.h (100%) rename instruction.h => headers/instruction.h (100%) rename issue.h => headers/issue.h (100%) rename memory.h => headers/memory.h (100%) rename mips.h => headers/mips.h (100%) rename output.h => headers/output.h (100%) rename registor.h => headers/registor.h (100%) rename reserv_station.h => headers/reserv_station.h (100%) rename victim_code.txt => test_case/attacked_code.txt (100%) rename tumasulu/test_cases/example_Case1.txt => test_case/case1.txt (100%) create mode 100644 test_case/case10.txt rename tumasulu/test_cases/example_Case12.txt => test_case/case11.txt (100%) rename tumasulu/test_cases/example_Case2.txt => test_case/case2.txt (100%) rename tumasulu/test_cases/example_Case3.txt => test_case/case3.txt (100%) rename tumasulu/test_cases/example_Case4.txt => test_case/case4.txt (100%) rename tumasulu/test_cases/example_Case5.txt => test_case/case5.txt (100%) rename tumasulu/test_cases/example_Case6.txt => test_case/case6.txt (100%) rename tumasulu/test_cases/example_Case7.txt => test_case/case7.txt (100%) rename tumasulu/test_cases/example_Case8.txt => test_case/case8.txt (100%) rename tumasulu/test_cases/example_Case9.txt => test_case/case9.txt (100%) create mode 100644 test_case/the_test_case.txt create mode 100644 test_case/victim_code.txt delete mode 100644 tumasulu/.gitignore delete mode 100644 tumasulu/ExeTable.h delete mode 100644 tumasulu/Import.cpp delete mode 100644 tumasulu/Import.h delete mode 100644 tumasulu/InputTest.txt delete mode 100644 tumasulu/InstBuffer.h delete mode 100644 tumasulu/LdSdQueue.h delete mode 100644 tumasulu/Memory.h delete mode 100644 tumasulu/Output.h delete mode 100644 tumasulu/RAT.h delete mode 100644 tumasulu/ROB.h delete mode 100644 tumasulu/RegFiles.h delete mode 100644 tumasulu/RsFU.h delete mode 100644 tumasulu/RsIU.h delete mode 100644 tumasulu/extable.csv delete mode 100644 tumasulu/extable.txt delete mode 100644 tumasulu/queue.h delete mode 100644 tumasulu/test.txt delete mode 100644 tumasulu/test_cases/Output File1.csv delete mode 100644 tumasulu/test_cases/Output File12.csv delete mode 100644 tumasulu/test_cases/Output File2.csv delete mode 100644 tumasulu/test_cases/Output File3.csv delete mode 100644 tumasulu/test_cases/Output File4.csv delete mode 100644 tumasulu/test_cases/Output File5.csv delete mode 100644 tumasulu/test_cases/Output File7.csv delete mode 100644 tumasulu/test_cases/Output File8.csv delete mode 100644 tumasulu/tumasulu.cpp diff --git a/FU.cpp b/FU.cpp index 0844f13..a810d6c 100644 --- a/FU.cpp +++ b/FU.cpp @@ -1,4 +1,4 @@ -#include "FU.h" +#include ".\headers\FU.h" extern config *CPU_cfg; extern instr_queue *instr_Q; @@ -239,8 +239,19 @@ A: at_rising_edge(next_vdd); { if (branch == tmp->taken) { - at_falling_edge(next_vdd); - R->finished = true; + if (tmp->taken && tmp->target != R->instr_i + 1 + task.offset) + { + tmp->target = R->instr_i + 1 +task.offset; + brcUnit.to_target(R->instr_i + 1 + task.offset); + msg_log("Begin Squash", 3); + brcUnit.to_squash(task.dest); + at_falling_edge(next_vdd); + } + else + { + at_falling_edge(next_vdd); + R->finished = true; + } } else { @@ -258,7 +269,7 @@ A: at_rising_edge(next_vdd); { if (branch) { - CPU_BTB.addEntry(R->instr_i, (R->instr_i + 1 + task.offset)%8); + CPU_BTB.addEntry(R->instr_i, R->instr_i + 1 + task.offset); brcUnit.to_target(R->instr_i + 1 + task.offset); msg_log("Begin Squash", 3); brcUnit.to_squash(task.dest); diff --git a/ROB.cpp b/ROB.cpp index f67a57b..2d323b3 100644 --- a/ROB.cpp +++ b/ROB.cpp @@ -1,4 +1,4 @@ -#include "ROB.h" +#include ".\headers\ROB.h" extern config *CPU_cfg; extern instr_queue *instr_Q; diff --git a/branch.cpp b/branch.cpp index 43493e1..2f4921d 100644 --- a/branch.cpp +++ b/branch.cpp @@ -1,5 +1,5 @@ -#include "branch.h" -#include "clock.h" +#include ".\headers\branch.h" +#include ".\headers\clock.h" extern unordered_map RAT; extern vector clk_wait_list; diff --git a/branch.h b/branch.h index 617b4a6..eb09db5 100644 --- a/branch.h +++ b/branch.h @@ -16,7 +16,7 @@ typedef struct squash_param bool flag = false; //Whether the squash has begun }squash_param; -#include "mips.h" +#include ".\headers\mips.h" class BTB { diff --git a/clock.cpp b/clock.cpp index 18e4b7d..1937047 100644 --- a/clock.cpp +++ b/clock.cpp @@ -1,4 +1,4 @@ -#include "clock.h" +#include ".\headers\clock.h" extern vector clk_wait_list; extern int debug_level; diff --git a/FU.h b/headers/FU.h similarity index 100% rename from FU.h rename to headers/FU.h diff --git a/ROB.h b/headers/ROB.h similarity index 100% rename from ROB.h rename to headers/ROB.h diff --git a/headers/branch.h b/headers/branch.h new file mode 100644 index 0000000..617b4a6 --- /dev/null +++ b/headers/branch.h @@ -0,0 +1,48 @@ +#ifndef BRANCH_H +#define BRANCH_H + +typedef struct BTBEntry +{ + int target; + bool predicted; + bool taken; +}BTBEntry; + +typedef struct squash_param +{ + int R_f; //The front pointer of ROB + int R_r; //The rear pointer of ROB + int ROB_i; //The affected ROB index + bool flag = false; //Whether the squash has begun +}squash_param; + +#include "mips.h" + +class BTB +{ + private: + BTBEntry buf[BTB_LEN]; + public: + BTB(); + void addEntry(int _instr_i, int _target); + BTBEntry *getEntry(int instr_i); +}; + +class branchCtrl +{ + private: + int ROB_i; + int target; + public: + pthread_t handle; + int next_vdd; + branchCtrl(); + void to_squash(int _ROB_i); + void to_target(int _target); + int squash_ROB_i(); + void branch_automat(); +}; + +void init_brcUnit(); + +#endif \ No newline at end of file diff --git a/clock.h b/headers/clock.h similarity index 100% rename from clock.h rename to headers/clock.h diff --git a/import.h b/headers/import.h similarity index 100% rename from import.h rename to headers/import.h diff --git a/instruction.h b/headers/instruction.h similarity index 100% rename from instruction.h rename to headers/instruction.h diff --git a/issue.h b/headers/issue.h similarity index 100% rename from issue.h rename to headers/issue.h diff --git a/memory.h b/headers/memory.h similarity index 100% rename from memory.h rename to headers/memory.h diff --git a/mips.h b/headers/mips.h similarity index 100% rename from mips.h rename to headers/mips.h diff --git a/output.h b/headers/output.h similarity index 100% rename from output.h rename to headers/output.h diff --git a/registor.h b/headers/registor.h similarity index 100% rename from registor.h rename to headers/registor.h diff --git a/reserv_station.h b/headers/reserv_station.h similarity index 100% rename from reserv_station.h rename to headers/reserv_station.h diff --git a/import.cpp b/import.cpp index 0463de8..f6ab045 100644 --- a/import.cpp +++ b/import.cpp @@ -1,4 +1,4 @@ -#include "import.h" +#include ".\headers\import.h" extern config *CPU_cfg; extern clk_tick sys_clk; diff --git a/instruction.cpp b/instruction.cpp index c136dc9..c0220d8 100644 --- a/instruction.cpp +++ b/instruction.cpp @@ -1,4 +1,4 @@ -#include "instruction.h" +#include ".\headers\instruction.h" instr_queue::instr_queue(vector a): Q(a),size(a.size()) diff --git a/issue.cpp b/issue.cpp index 10faa1a..2d3d41d 100644 --- a/issue.cpp +++ b/issue.cpp @@ -1,4 +1,4 @@ -#include "issue.h" +#include ".\headers\issue.h" extern pthread_t iss_unit; extern clk_tick sys_clk; @@ -264,7 +264,7 @@ void *issue_automat(void *arg) if (BTBEntry* predctr = CPU_BTB.getEntry(R->instr_i)) { if (predctr->taken) - instr_Q->move_ptr(((R->instr_i)/8)*8 + predctr->target); + instr_Q->move_ptr(((R->instr_i)/8)*8 + (predctr->target)%8); else instr_Q->ptr_advance(); } diff --git a/memory.cpp b/memory.cpp index 74e30f6..21746f1 100644 --- a/memory.cpp +++ b/memory.cpp @@ -1,4 +1,4 @@ -#include "memory.h" +#include ".\headers\memory.h" extern clk_tick sys_clk; extern memory main_mem; diff --git a/mips.cpp b/mips.cpp index 8cd0925..58f0fb2 100644 --- a/mips.cpp +++ b/mips.cpp @@ -1,4 +1,4 @@ -#include "mips.h" +#include ".\headers\mips.h" config *CPU_cfg = nullptr; instr_queue *instr_Q = nullptr; diff --git a/output.cpp b/output.cpp index 8b83260..752c504 100644 --- a/output.cpp +++ b/output.cpp @@ -1,4 +1,4 @@ -#include "output.h" +#include ".\headers\output.h" using namespace std; diff --git a/registor.cpp b/registor.cpp index fc7963f..ec561f4 100644 --- a/registor.cpp +++ b/registor.cpp @@ -1,4 +1,4 @@ -#include "registor.h" +#include ".\headers\registor.h" extern clk_tick sys_clk; diff --git a/reserv_station.cpp b/reserv_station.cpp index 21dad92..cbc2a8f 100644 --- a/reserv_station.cpp +++ b/reserv_station.cpp @@ -1,5 +1,5 @@ -#include "reserv_station.h" -#include "mips.h" +#include ".\headers\reserv_station.h" +#include ".\headers\mips.h" extern config *CPU_cfg; extern clk_tick sys_clk; diff --git a/victim_code.txt b/test_case/attacked_code.txt similarity index 100% rename from victim_code.txt rename to test_case/attacked_code.txt diff --git a/tumasulu/test_cases/example_Case1.txt b/test_case/case1.txt similarity index 100% rename from tumasulu/test_cases/example_Case1.txt rename to test_case/case1.txt diff --git a/test_case/case10.txt b/test_case/case10.txt new file mode 100644 index 0000000..89b1aa3 --- /dev/null +++ b/test_case/case10.txt @@ -0,0 +1,17 @@ + # of rs Cycles in EX Cycles in Mem # of FUs +Integer adder 2 1 1 +FP adder 3 3 1 +FP multiplier 2 20 1 +Load/store unit 3 1 4 1 +ROB entries = 128 +CDB buffer entries = 1 +R1=10,R2=16,R3=30,F1=111.111,F2=222.222 +Mem[4]=1,Mem[8]=2,Mem[12]=3.4 + +ADD R1,R0,R0 +SD F1, 0(R1) +ADDI R1,R1,4 +BNE R1,R2,-3 +SD F2, 0(R1) +LD F3, 0(R1) +LD F4, -8(R1) diff --git a/tumasulu/test_cases/example_Case12.txt b/test_case/case11.txt similarity index 100% rename from tumasulu/test_cases/example_Case12.txt rename to test_case/case11.txt diff --git a/tumasulu/test_cases/example_Case2.txt b/test_case/case2.txt similarity index 100% rename from tumasulu/test_cases/example_Case2.txt rename to test_case/case2.txt diff --git a/tumasulu/test_cases/example_Case3.txt b/test_case/case3.txt similarity index 100% rename from tumasulu/test_cases/example_Case3.txt rename to test_case/case3.txt diff --git a/tumasulu/test_cases/example_Case4.txt b/test_case/case4.txt similarity index 100% rename from tumasulu/test_cases/example_Case4.txt rename to test_case/case4.txt diff --git a/tumasulu/test_cases/example_Case5.txt b/test_case/case5.txt similarity index 100% rename from tumasulu/test_cases/example_Case5.txt rename to test_case/case5.txt diff --git a/tumasulu/test_cases/example_Case6.txt b/test_case/case6.txt similarity index 100% rename from tumasulu/test_cases/example_Case6.txt rename to test_case/case6.txt diff --git a/tumasulu/test_cases/example_Case7.txt b/test_case/case7.txt similarity index 100% rename from tumasulu/test_cases/example_Case7.txt rename to test_case/case7.txt diff --git a/tumasulu/test_cases/example_Case8.txt b/test_case/case8.txt similarity index 100% rename from tumasulu/test_cases/example_Case8.txt rename to test_case/case8.txt diff --git a/tumasulu/test_cases/example_Case9.txt b/test_case/case9.txt similarity index 100% rename from tumasulu/test_cases/example_Case9.txt rename to test_case/case9.txt diff --git a/test_case/the_test_case.txt b/test_case/the_test_case.txt new file mode 100644 index 0000000..35ec594 --- /dev/null +++ b/test_case/the_test_case.txt @@ -0,0 +1,20 @@ + # of rs Cycles in EX Cycles in Mem # of FUs +Integer adder 4 1 1 +FP adder 3 4 1 +FP multiplier 2 15 1 +Load/store unit 10 1 5 1 +ROB entries = 64 +CDB buffer entries = 1 + +R1=12, R2=32, F20=3.0 +Mem[4]=3.0, Mem[8]=2.0, Mem[12]=1.0, Mem[24]=6.0, Mem[28]=5.0, Mem[32]=4.0 + +ld F2, 0(R1) +mult.d F4, F2, F20 +ld F6, 0(R2) +add.d F6, F4, F6 +sd F6, 0(R2) +addi R1, R1, -4 +addi R2, R2, -4 +bne R1, R0, -8 +NOP \ No newline at end of file diff --git a/test_case/victim_code.txt b/test_case/victim_code.txt new file mode 100644 index 0000000..3c7b953 --- /dev/null +++ b/test_case/victim_code.txt @@ -0,0 +1,23 @@ + # of rs Cycles in EX Cycles in Mem # of FUs +Integer adder 4 1 1 +FP adder 3 4 1 +FP multiplier 2 15 1 +Load/store unit 3 1 5 1 +ROB entries = 64 +CDB buffer entries = 1 + +R0=0 +Mem[4]=3.0 + +Addi R2, R0, -2 +Addi R3, R0, 4 +Addi R2, R2, 2 +Ld F1, 0(R1) +Beq R2, R0, 5 +Addi R3, R3, 4 +Addi R2, R2, 8 +Mult.d F3, F2, F1 +Add R2, R2, R2 +Add R1, R1, R1 +Add R1, R1, R1 +Add R1, R1, R1 \ No newline at end of file diff --git a/tumasulu/.gitignore b/tumasulu/.gitignore deleted file mode 100644 index ef20741..0000000 --- a/tumasulu/.gitignore +++ /dev/null @@ -1,40 +0,0 @@ -# Prerequisites -*.d - -# Compiled Object files -*.slo -*.lo -*.o -*.obj - -# Precompiled Headers -*.gch -*.pch - -# Compiled Dynamic libraries -*.so -*.dylib -*.dll - -# Fortran module files -*.mod -*.smod - -# Compiled Static libraries -*.lai -*.la -*.a -*.lib - -# Executables -*.exe -*.out -*.app - -.vscode/ -.vs/ -Debug/ -*.sln -*.vcxproj.filters -*.vcxproj.user -*.vcxproj \ No newline at end of file diff --git a/tumasulu/ExeTable.h b/tumasulu/ExeTable.h deleted file mode 100644 index 33ff0b3..0000000 --- a/tumasulu/ExeTable.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef EXETABLE_H -#define EXETABLE_H -#include -#include -using namespace std; -class ExeTable // Structure definition for the execution table. -{ -public: - string Instruction; // holds instruction string - int Issue; - int Exec; - int Mem; - int WB; - int Commit; -}; -#endif \ No newline at end of file diff --git a/tumasulu/Import.cpp b/tumasulu/Import.cpp deleted file mode 100644 index dd7a23a..0000000 --- a/tumasulu/Import.cpp +++ /dev/null @@ -1,254 +0,0 @@ -#include "Import.h" -#include -#include -#include -#include -#include -#include -using namespace std; - -void Import::ReadInput() -{ - // readind input text file - string s; - ifstream infile; - infile.open("InputTest.txt"); - //ofstream outfile; - ofstream outfile("test.txt"); - if (outfile.fail()) - { - cout << "Output file could not be opened.\n"; - exit(1); - } - - if (!infile) - { - cerr << "Unable to open file datafile.txt"; - exit(1); // call system to stop - } - - L1:while (getline(infile, s)) { - if (!s.empty()) { - stringstream line(s); - while (line >> s) { - outfile << s; - if (s != "," ) { - input.push_back(s); - outfile << ' '; - } - } - } - else { - goto L1; - } - outfile << endl; // put input in a new file after removing all extra spaces - //------------------------------------------------------------------------------------ - number_of_lines++; - //cout << s << '\n' << endl; - } - /*for (int i = 0; i < input.size(); i++) - cout << input[i] << "\n"; */ - infile.close(); - outfile.close(); -} -//---------------------------------------------------------------------------- -int Import::convertStringToInt(string& input) -{ - // Convert string to int - - stringstream ss(input); - int retval; - ss >> retval; - return retval; -} -//-------------------------------------------------------------------------------- -double Import::convertStringToFloat(string& input) -{ - //convert string to float - - stringstream ss(input); - double retval; - ss >> retval; - return retval; -} -//--------------------------------------------------------------------------------- -vector Import::ReadInstruction(string str) -{ - //geting opccode, dest, src1, src2 - // Used to split string around spaces. - istringstream ss(str); - Inst_content.clear(); - // Traverse through all words - do { - // Read a word - string word; - ss >> word; - - // push to vector the read word - Inst_content.push_back(word); - // While there is more to read - } while (ss); - return Inst_content; -} - -void Import::SetVariables() { - ifstream infile; - string s; - vector line1; - int no_lines = 0; - infile.open("test.txt"); - if (!infile) - { - cerr << "Unable to open file datafile.txt"; - exit(1); // call system to stop - } - - while (getline(infile, s)) { - //read data line by line and get unique info from each line. input format is constant just reg value and memory will increase - if (no_lines == 1) { - stringstream line(s); - while (line >> s) { - line1.push_back(s); - } - Int_adder_rs = convertStringToInt(line1[2]); - Int_adder_ex = convertStringToInt(line1[3]); - Int_adder_fu = convertStringToInt(line1[4]); - line1.clear(); - } - - if (no_lines == 2) { - stringstream line(s); - while (line >> s) { - line1.push_back(s); - } - FP_adder_rs = convertStringToInt(line1[2]); - FP_adder_ex = convertStringToInt(line1[3]); - FP_adder_fu = convertStringToInt(line1[4]); - line1.clear(); - } - - if (no_lines == 3) { - stringstream line(s); - while (line >> s) { - line1.push_back(s); - } - FP_Mul_rs = convertStringToInt(line1[2]); - FP_Mul_ex = convertStringToInt(line1[3]); - FP_Mul_fu = convertStringToInt(line1[4]); - line1.clear(); - } - - if (no_lines == 4) { - stringstream line(s); - while (line >> s) { - line1.push_back(s); - } - LdSd_rs = convertStringToInt(line1[2]); - LdSd_ex = convertStringToInt(line1[3]); - LdSd_mem = convertStringToInt(line1[4]); - LdSd_fu = convertStringToInt(line1[5]); - - line1.clear(); - } - - if (no_lines == 5) { - stringstream line(s); - while (line >> s) { - line1.push_back(s); - } - ROB_entries = convertStringToInt(line1[3]); - - line1.clear(); - } - - if (no_lines == 7) { - stringstream line(s); - while (line >> s) { - line1.push_back(s); - } - for (int i = 0; i < line1.size(); i++) { //line1 nw contains all reg name and value with delimter ',' I am removing it to make the string - //only conatins variable name before '=' and variable value after equal. - //string delimiter = "="; - //string token= line1[i].substr(0, line1[i].find(delimiter)); //token1 is R1, R2 ,F2 ,.. etc - //line1[i].erase(remove(line1[i].begin(), line1[i].end(), '='), line1[i].end()); - line1[i].erase(remove(line1[i].begin(), line1[i].end(), ','), line1[i].end()); - register_var.push_back(line1[i]); - } - - //if want to find first reg value can get it like this but for now I think it's better to leave the string as R1=10 until later on - // just test to make sure I can get the value correct. if float use function convertStringtofloat and vise versa. - /*int length = register_var[3].length(); - size_t pos = register_var[3].find('='); - cout << pos << endl; - string token = register_var[3].substr(pos+1, length); - cout << token << endl; - double Reg1value = convertStringToFloat(token); - cout << " first register value is " << Reg1value << endl; - for (int i = 0; i < register_var.size(); i++) // just to check what is in reg_var now - cout << register_var[i] << "\n";*/ - - line1.clear(); - } - - // for now format Mem[4]=10 - if (no_lines == 8) { - stringstream line(s); - while (line >> s) { - line1.push_back(s); - } - for (int i = 0; i < line1.size(); i++) { - line1[i].erase(remove(line1[i].begin(), line1[i].end(), ','), line1[i].end()); - memory_var.push_back(line1[i]); - } - line1.clear(); - } - - // starting from line 9 it will be instructions untill number_of_lines - // removing {, ( ) } so now every line of inst is sperated be a space delimter - // format: Opcode DestReg src1 src2 if we found it's better to change it later we will. - if (no_lines >= 9) { - s.erase(remove(s.begin(), s.end(), ','), s.end()); - replace(s.begin(), s.end(), '(', ' '); - replace(s.begin(), s.end(), ')', ' '); - instructions.push_back(s); - - } - - no_lines++; - } - //output to check compare with .txt - //------------------------------------------------------------------------------------------------------ - /* - cout << "Number of lines in text file: " << number_of_lines << endl; - cout << "IRs is " << Int_adder_rs << " exi " << Int_adder_ex << " fui " << Int_adder_fu << endl; - cout << "rs f " << FP_adder_rs << " ex f " << FP_adder_ex << " fu f " << FP_adder_fu << endl; - cout << "rs fm " << FP_Mul_rs << " ex fm " << FP_Mul_ex << " fu fm " << FP_Mul_fu << endl; - cout << "rs LD " << LdSd_rs << " ex ld " << LdSd_ex << " Ld mem " << LdSd_mem << " fu ld " << LdSd_fu << endl; - cout << " Rob entries " << ROB_entries << endl; - for (int i = 0; i < register_var.size(); i++) // just to check what is in reg_var now - cout << register_var[i] << "\n"; - for (int i = 0; i < memory_var.size(); i++) // just to check what is in mem_var now - cout << memory_var[i] << "\n"; - for (int i = 0; i < instructions.size(); i++) - cout << instructions[i] << "\n"; */ - - //-------------------------------------------------------------------------------------------------- - //test to check function is working properly - /*Inst_content=ReadInstruction(instructions[1]); - cout << "opcode " << Inst_content[0] << endl; - cout << "dest " << Inst_content[1] << endl; - cout << "src1 " << Inst_content[2] << endl; - cout << "src2 " << Inst_content[3] << endl; */ - - - /*for (int i = 0; i < instructions.size(); i++) - cout << instructions[i] << "\n"; - for (int i = 0; i < memory_var.size(); i++) // just to check what is in mem_var now - cout << memory_var[i] << "\n"; */ - /*for (int i = 0; i < line1.size(); i++) - cout << line1[i] << "\n"; */ - - - - infile.close(); -} \ No newline at end of file diff --git a/tumasulu/Import.h b/tumasulu/Import.h deleted file mode 100644 index 94645f2..0000000 --- a/tumasulu/Import.h +++ /dev/null @@ -1,46 +0,0 @@ -#ifndef IMPORT_H -#define IMPORT_H - -#include -#include -#include -#include -#include -#include - -using namespace std; - -class Import -{ - // this class is used to read input.txt and give back all the info needed to start. -private: - vector Inst_content; - int number_of_lines = 0; - vector input; - -public: - int Int_adder_rs; - int Int_adder_ex; - int Int_adder_fu; - int FP_adder_rs; - int FP_adder_ex; - int FP_adder_fu; - int FP_Mul_rs; - int FP_Mul_ex; - int FP_Mul_fu; - int LdSd_rs; - int LdSd_ex; - int LdSd_mem; - int LdSd_fu; - int ROB_entries; - vector instructions; - vector memory_var; - vector register_var; - void ReadInput();// read input file and remove extra spaces and commas - int convertStringToInt(string& input); // Convert string to int - double convertStringToFloat(string& input); //convert string to float - vector ReadInstruction(string str); //geting opccode, dest, src1, src2 - void SetVariables();//read data line by line and get unique info from each line. input format is constant just reg value and memory will increase - -}; -#endif \ No newline at end of file diff --git a/tumasulu/InputTest.txt b/tumasulu/InputTest.txt deleted file mode 100644 index 87689c6..0000000 --- a/tumasulu/InputTest.txt +++ /dev/null @@ -1,25 +0,0 @@ -# of rs Cycles in EX Cycles in Mem # of FUs -Integer adder 4 1 1 -FP adder 3 4 1 -FP multiplier 2 15 1 -Load/store unit 5 1 5 1 -ROB entries = 128 - -R1=12, R2=32, R3=10, R4=5 , R6=8 ,R7=9 , R9=4 , R10=2 , R11=2 , R12=5 , R13=6 , F0=6.1 ,F2=2.5 , F4=4 , F5=5 , F6=3 ,F7=8 , F8=12 ,F9=15 , F10=18 ,F15=5.3, F20=2.0 -Mem[4]=3.0, Mem[8]=2.0, Mem[12]=1.0, Mem[24]=6.0, Mem[28]=5.0, Mem[32]=4.0 -ld F6, 4(R2) -ld F2, 8(R3) -mult.d F0, F2, F4 -sub.d F8, F6, F2 -add.d F10, F1, F6 -add.d F5, F7, F9 -addi R6, R7, 7 -nop -mult.d F8, F15, F5 -add R1, R9, R10 -add R11, R12, R13 - - - - - diff --git a/tumasulu/InstBuffer.h b/tumasulu/InstBuffer.h deleted file mode 100644 index d9f32c6..0000000 --- a/tumasulu/InstBuffer.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef InstBuffer_h -#define InstBuffer_h -#include -#include -using namespace std; -class InstBuffer -{ -public: - InstBuffer(){} - string Opcode; - string Dest; - string Src1; - string Src2; -}; -#endif \ No newline at end of file diff --git a/tumasulu/LdSdQueue.h b/tumasulu/LdSdQueue.h deleted file mode 100644 index 48abbfd..0000000 --- a/tumasulu/LdSdQueue.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef LdSdQueue_h -#define LdSdQueue_h -#include -#include -using namespace std; -class LdSdQueue -{ public: - string Dest; // Destination of the load operation. - int Offset; // offset of memory address for Ld/St. - string Reg; // Register of memory address for Ld/St. - string Inst; // Instruction field. - string Opcode; // Operand field. - string State; // State of the instruction (Ready, Execute). - int Addr; // Address after calculation in Execution stage. - int Cycle; // Cycle started execution. - int ETable_Entry; // ETable entry for that instruction. - int ROB_entry; // entry of ROB for SD. -}; -#endif \ No newline at end of file diff --git a/tumasulu/Memory.h b/tumasulu/Memory.h deleted file mode 100644 index 80292cc..0000000 --- a/tumasulu/Memory.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef MEMORY_H -#define MEMORY_H - - - -#include -#include -using namespace std; - -class Memory -{ -public: - // Global definition of Memory (256B, 64W x 64B). - double Value; - bool ischanged; -}; -#endif \ No newline at end of file diff --git a/tumasulu/Output.h b/tumasulu/Output.h deleted file mode 100644 index cde3c19..0000000 --- a/tumasulu/Output.h +++ /dev/null @@ -1,124 +0,0 @@ -#ifndef OUTPUT_H -#define OUTPUT_H -#include -#include -#include -#include -#include -#include -#include -#include -#include "RegFiles.h" -#include "InstBuffer.h" -#include "RAT.h" -#include "RsIU.h" -#include "RsFU.h" -#include "Memory.h" -#include "ROB.h" -#include "ExeTable.h" -#include "LdSdQueue.h" -#include "Import.h" -#include "queue.h" - -using namespace std; -class Output { - -public: - void OutputFcn(ExeTable *Extable, RegFiles *RFiles, Memory *Mem , Import input) - { - //Import input; - // This function print the Output file after the code execution. - // it should be called from the main program, after the code execution, to make the output file. - try - { - ofstream outfile("extable.csv"); - // Output file where the data would Execution table, register files and memory would be written. - //FileWriter writer = new FileWriter("Output File.csv"); - - - // First we print the header of the execution table. - outfile<<"Execution Table" ; - outfile << endl; - outfile<<"Instructions,ISSUE,EXEC,MEM,WB,COMMIT \n"; - - // then we print the execution table itself. - for (int i = 0; i -#include -using namespace std; -class RAT -{ - // Global definition of RAT for integer and floating Register Files -public: - string R; //should be ROBx or Rx for integer. - string F; //should be ROBx or Fx for float. -}; -#endif \ No newline at end of file diff --git a/tumasulu/ROB.h b/tumasulu/ROB.h deleted file mode 100644 index 6bf6249..0000000 --- a/tumasulu/ROB.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef ROB_H -#define ROB_H -#include -#include -using namespace std; -class ROB -{ -public: - bool Busy; // Ready to commit or not. - string Dest; // Destination of the instruction (R1, R2, F1, F2) - double Value; // Result of the instruction, entry of ROB waiting to finish, address for Ld/St. - string Opcode; // Opcode of the operation. - string Inst; // Instruction field. - string State; // State of the instruction (Execute, Write_Result, Commit). - int Addr; // Adress for load and store. - int ETable_Entry; // ETable entry for that instruction. -}; -#endif \ No newline at end of file diff --git a/tumasulu/RegFiles.h b/tumasulu/RegFiles.h deleted file mode 100644 index 1a502da..0000000 --- a/tumasulu/RegFiles.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef REGFILES_H -#define REGFILES_H -#include -using namespace std; -class RegFiles -{ -public: - int intRegFile; - double floatRegFile; -}; -#endif \ No newline at end of file diff --git a/tumasulu/RsFU.h b/tumasulu/RsFU.h deleted file mode 100644 index 5d7272f..0000000 --- a/tumasulu/RsFU.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef RSFU_H -#define RSFU_H -#include -#include -using namespace std; -class RsFU -{ -public: - string Inst; // Instruction field. - bool Busy; // free or not. - string Opcode; // Operand field . - string State; // State of the instruction (Ready, Execute). - int Cycle; // Cycle started execution. - double Vj; // value of the first operand. - double Vk; // value of the second operand. - string Qj; // name from RAt table for the first operand. - string Qk; // name from RAt table for the second operand. - int Addr; // offset of branch instructions. - string Dest; // ROB entry that will store the operand. - int ETable_Entry; // ETable entry for that instruction. -}; -#endif \ No newline at end of file diff --git a/tumasulu/RsIU.h b/tumasulu/RsIU.h deleted file mode 100644 index f5bc996..0000000 --- a/tumasulu/RsIU.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef RSIU_H -#define RSIU_H -#include -#include -using namespace std; -class RsIU -{ -public: - string Inst; // Instruction field. - bool Busy; // free or not. - string Opcode; // Operand field . - string State; // State of the instruction (Ready, Execute). - int Cycle; // Cycle started execution. - int Vj; // value of the first operand. - int Vk; // value of the second operand. - string Qj; // name from RAt table for the first operand. - string Qk; // name from RAt table for the second operand. - int Addr; // offset of branch instructions. - string Dest; // ROB entry that will store the operand. - int ETable_Entry; // ETable entry for that instruction. -}; -#endif \ No newline at end of file diff --git a/tumasulu/extable.csv b/tumasulu/extable.csv deleted file mode 100644 index b18e74f..0000000 --- a/tumasulu/extable.csv +++ /dev/null @@ -1,12 +0,0 @@ -Execution Table -Instructions,ISSUE,EXEC,MEM,WB,COMMIT -addi R1 R2 6, 1,2, ,3,4 -addi R4 R2 8, 2,3, ,4,5 -mult.d F6 F5 F8, 3,4, ,19,20 -add R7 R10 R5, 4,5, ,6,21 -add R12 R13 R14, 5,6, ,7,22 -ld F2 15(R3), 6,7,8,13,23 -add R14 R15 R16, 7,8, ,9,24 -add R17 R15 R13, 8,9, ,10,25 -mult.d F5 F4 F3, 9,10, ,25,26 -add.d F6 F7 F9F9, 10,11, ,15,27 diff --git a/tumasulu/extable.txt b/tumasulu/extable.txt deleted file mode 100644 index 944b931..0000000 --- a/tumasulu/extable.txt +++ /dev/null @@ -1,13 +0,0 @@ -Execution Table -Instructions,ISSUE,EXEC,MEM,WB,COMMIT -addi R1 R2 6, 1,2, ,3,4 -addi R4 R2 8, 2,3, ,4,5 -mult.d F6 F5 F8, 3,4, ,19,20 -add R7 R10 R5, 4,5, ,6,21 -add R12 R13 R14, 5,6, ,7,22 -add R14 R15 R16, 6,7, ,8,23 -add R17 R15 R13, 7,8, ,9,24 -mult.d F5 F4 F3, 8,9, ,24,25 -add.d F6 F7 F9, 9,10, ,14,26 - - diff --git a/tumasulu/queue.h b/tumasulu/queue.h deleted file mode 100644 index c177071..0000000 --- a/tumasulu/queue.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef queue_h -#define queue_h -#include -#include -#include - -template -class queue -{ -private: - std::mutex d_mutex; - std::condition_variable d_condition; - //std::deque d_queue; -public: - //std::mutex d_mutex; - //std::condition_variable d_condition; - std::deque d_queue; - void push(T const& value) { - { - std::unique_lock lock(this->d_mutex); - d_queue.push_front(value); - } - this->d_condition.notify_one(); - } - T pop() { - std::unique_lock lock(this->d_mutex); - this->d_condition.wait(lock, [=] { return !this->d_queue.empty(); }); - T rc(std::move(this->d_queue.back())); - this->d_queue.pop_back(); - return rc; - } -}; -#endif \ No newline at end of file diff --git a/tumasulu/test.txt b/tumasulu/test.txt deleted file mode 100644 index 6938463..0000000 --- a/tumasulu/test.txt +++ /dev/null @@ -1,19 +0,0 @@ -# of rs Cycles in EX Cycles in Mem # of FUs -Integer adder 4 1 1 -FP adder 3 4 1 -FP multiplier 2 15 1 -Load/store unit 5 1 5 1 -ROB entries = 128 -CDB buffer entries = 1 -R1=12, R2=32, R3=8, R4=8, R7=8, R10=8, R12=8, R13=9, R14=7, R16=9, R17=7, F2=7, F3=7, F4=7, F5=7, F6=7, F7=8, F8=9, F9=7, F20=2.0 -Mem[4]=3.0, Mem[8]=2.0, Mem[12]=1.0, Mem[24]=6.0, Mem[28]=5.0, Mem[32]=4.0 -addi R1, R2, 6 -addi R4, R2, 8 -mult.d F6, F5, F8 -add R7, R10, R5 -add R12, R13, R14 -ld F2, 15(R3) -add R14, R15, R16 -add R17, R15, R13 -mult.d F5, F4, F3 -add.d F6, F7, F9F9 diff --git a/tumasulu/test_cases/Output File1.csv b/tumasulu/test_cases/Output File1.csv deleted file mode 100644 index 5892bbb..0000000 --- a/tumasulu/test_cases/Output File1.csv +++ /dev/null @@ -1,32 +0,0 @@ -Execution Table ,,,,,,,,Non-Zero Memory Values , -Instructions,ISSUE,EXEC,MEM,WB,COMMIT ,,,ADDRESS,VALUE -ADDI R1 R2 6,1,2, ,3,4,,,4,3 -ADDI R4 R2 8,2,3, ,4,5,,,8,2 -MULT.D F6 F5 F8,3,4, ,19,20,,,12,1 -ADD R7 R10 R5,4,5, ,6,21,,,24,6 -ADD R12 R13 R14,5,6, ,7,22,,,28,5 -LD F2 15(R3),6,7,8,13,23,,,32,4 -ADD R14 R15 R16,7,8, ,9,24,,,33,0 -ADD R17 R15 R13,8,9, ,10,25,,,, -MULT.D F5 F4 F3,9,10, ,25,26,,,, -ADD.D F6 F7 F9,10,11, ,15,27,,,, -,,,,,,,,, -,,,,,,,,, -Integer Register File ,,,,,,Floating point Register File ,,, -REGs,VALUE,REGs,VALUE ,,,REGs,VALUE,REGs,VALUE -R0,0,R1,38,,,F0,0,F1,0 -R2,32,R3,8,,,F2,0,F3,7 -R4,40,R5,0,,,F4,7,F5,49 -R6,0,R7,8,,,F6,15,F7,8 -R8,0,R9,0,,,F8,9,F9,7 -R10,8,R11,0,,,F10,0,F11,0 -R12,16,R13,9,,,F12,0,F13,0 -R14,9,R15,0,,,F14,0,F15,0 -R16,9,R17,9,,,F16,0,F17,0 -R18,0,R19,0,,,F18,0,F19,0 -R20,0,R21,0,,,F20,2,F21,0 -R22,0,R23,0,,,F22,0,F23,0 -R24,0,R25,0,,,F24,0,F25,0 -R26,0,R27,0,,,F26,0,F27,0 -R28,0,R29,0,,,F28,0,F29,0 -R30,0,R31,0,,,F30,0,F31,0 diff --git a/tumasulu/test_cases/Output File12.csv b/tumasulu/test_cases/Output File12.csv deleted file mode 100644 index 3ae0f01..0000000 --- a/tumasulu/test_cases/Output File12.csv +++ /dev/null @@ -1,120 +0,0 @@ -Execution Table -Instructions,ISSUE,EXEC,MEM,WB,COMMIT -MULT.D F1 F2 F3,1,2, ,17,18 -MULT.D F4 F1 F2,2,19, ,34,35 -MULT.D F14 F4 F6,18,36, ,51,52 -ADD.D F4 F7 F9,19,20, ,24,53 -LD F4 12(R7),20,21,22,27,54 -LD F7 20(R17),21,22,27,32,55 -MULT.D F7 F8 F10,35,37, ,52,56 -LD F7 20(R17),36,37,38,43,57 -LD F13 20(R16),37,38,43,48,58 -LD F13 14(R7),38,39,48,53,59 - - -Integer Register File -REGs,VALUE,REGs,VALUE -R0,0,R1,0 -R2,0,R3,0 -R4,0,R5,0 -R6,0,R7,9 -R8,0,R9,0 -R10,0,R11,0 -R12,0,R13,0 -R14,0,R15,0 -R16,8,R17,9 -R18,0,R19,0 -R20,0,R21,0 -R22,0,R23,0 -R24,0,R25,0 -R26,0,R27,0 -R28,0,R29,0 -R30,0,R31,0 - - -Floating point Register File -REGs,VALUE,REGs,VALUE -F0,0.0,F1,18.0 -F2,9.0,F3,2.0 -F4,0.0,F5,0.0 -F6,7.0,F7,0.0 -F8,6.0,F9,6.0 -F10,8.0,F11,0.0 -F12,0.0,F13,0.0 -F14,1134.0,F15,0.0 -F16,0.0,F17,0.0 -F18,0.0,F19,0.0 -F20,0.0,F21,0.0 -F22,0.0,F23,0.0 -F24,0.0,F25,0.0 -F26,0.0,F27,0.0 -F28,0.0,F29,0.0 -F30,0.0,F31,0.0 - - -Non-Zero Memory Values -ADDRESS,VALUE -0,0.0 -1,0.0 -2,0.0 -3,0.0 -4,3.0 -5,0.0 -6,0.0 -7,0.0 -8,2.0 -9,0.0 -10,0.0 -11,0.0 -12,1.0 -13,0.0 -14,0.0 -15,0.0 -16,0.0 -17,0.0 -18,0.0 -19,0.0 -20,0.0 -21,0.0 -22,0.0 -23,0.0 -24,6.0 -25,0.0 -26,0.0 -27,0.0 -28,5.0 -29,0.0 -30,0.0 -31,0.0 -32,4.0 -33,0.0 -34,0.0 -35,0.0 -36,0.0 -37,0.0 -38,0.0 -39,0.0 -40,0.0 -41,0.0 -42,0.0 -43,0.0 -44,0.0 -45,0.0 -46,0.0 -47,0.0 -48,0.0 -49,0.0 -50,0.0 -51,0.0 -52,0.0 -53,0.0 -54,0.0 -55,0.0 -56,0.0 -57,0.0 -58,0.0 -59,0.0 -60,0.0 -61,0.0 -62,0.0 -63,0.0 diff --git a/tumasulu/test_cases/Output File2.csv b/tumasulu/test_cases/Output File2.csv deleted file mode 100644 index 30d7d85..0000000 --- a/tumasulu/test_cases/Output File2.csv +++ /dev/null @@ -1,32 +0,0 @@ -Execution Table ,,,,,,,,Non-Zero Memory Values , -Instructions,ISSUE,EXEC,MEM,WB,COMMIT ,,,ADDRESS,VALUE -LD F6 4(R2),1,2,3,8,9,,,4,3 -LD F2 8(R3),2,3,8,15,16,,,8,2 -MULT.D F0 F2 F4,3,16, ,31,32,,,12,1 -SUB.D F8 F6 F2,4,16, ,20,33,,,24,6 -ADD.D F10 F1 F6,5,9, ,13,34,,,28,5 -ADD.D F5 F7 F9,6,7, ,14,35,,,32,4 -ADDI R6 R7 7,7,8, ,9,36,,,, -MULT.D F8 F15 F5,8,15, ,30,37,,,, -ADD R1 R9 R10,9,10, ,11,38,,,, -ADD R11 R12 R13,10,11, ,12,39,,,, -,,,,,,,,, -,,,,,,,,, -Integer Register File ,,,,,,Floating point Register File ,,, -REGs,VALUE,REGs,VALUE ,,,REGs,VALUE,REGs,VALUE -R0,0,R1,6,,,F0,0,F1,0 -R2,32,R3,10,,,F2,0,F3,0 -R4,5,R5,0,,,F4,4,F5,23 -R6,16,R7,9,,,F6,0,F7,8 -R8,0,R9,4,,,F8,121.9000044,F9,15 -R10,2,R11,11,,,F10,0,F11,0 -R12,5,R13,6,,,F12,0,F13,0 -R14,0,R15,0,,,F14,0,F15,5.300000191 -R16,0,R17,0,,,F16,0,F17,0 -R18,0,R19,0,,,F18,0,F19,0 -R20,0,R21,0,,,F20,2,F21,0 -R22,0,R23,0,,,F22,0,F23,0 -R24,0,R25,0,,,F24,0,F25,0 -R26,0,R27,0,,,F26,0,F27,0 -R28,0,R29,0,,,F28,0,F29,0 -R30,0,R31,0,,,F30,0,F31,0 diff --git a/tumasulu/test_cases/Output File3.csv b/tumasulu/test_cases/Output File3.csv deleted file mode 100644 index e7504bf..0000000 --- a/tumasulu/test_cases/Output File3.csv +++ /dev/null @@ -1,32 +0,0 @@ -Execution Table ,,,,,,,,Non-Zero Memory Values , -Instructions,ISSUE,EXEC,MEM,WB,COMMIT ,,,ADDRESS,VALUE -ADD R1 R2 R3,1,2, ,3,4,,,4,3 -MULT.D F1 F2 F3,2,3, ,18,19,,,8,2 -ADD.D F6 F5 F8,3,4, ,8,20,,,12,1 -LD F9 12(R7),4,5,6,11,21,,,24,6 -ADD R12 R13 R14,5,6, ,7,22,,,28,5 -LD F10 15(R8),6,7,11,17,23,,,32,4 -MULT.D F14 F15 F16,7,8, ,23,24,,,, -ADDI R17 R15 9,8,9, ,10,25,,,, -LD F13 20(R17),9,11,17,22,26,,,, -ADD.D F6 F7 F9,10,12, ,16,27,,,, -,,,,,,,,, -,,,,,,,,, -Integer Register File ,,,,,,Floating point Register File ,,, -REGs,VALUE,REGs,VALUE ,,,REGs,VALUE,REGs,VALUE -R0,0,R1,38,,,F0,0,F1,42 -R2,32,R3,6,,,F2,6,F3,7 -R4,7,R5,0,,,F4,4,F5,7 -R6,8,R7,9,,,F6,7,F7,7 -R8,8,R9,9,,,F8,7,F9,0 -R10,10,R11,5,,,F10,0,F11,0 -R12,12,R13,8,,,F12,0,F13,0 -R14,4,R15,5,,,F14,3388,F15,44 -R16,0,R17,14,,,F16,77,F17,0 -R18,0,R19,0,,,F18,0,F19,0 -R20,0,R21,0,,,F20,2,F21,0 -R22,0,R23,0,,,F22,0,F23,0 -R24,0,R25,0,,,F24,0,F25,0 -R26,0,R27,0,,,F26,0,F27,0 -R28,0,R29,0,,,F28,0,F29,0 -R30,0,R31,0,,,F30,0,F31,0 diff --git a/tumasulu/test_cases/Output File4.csv b/tumasulu/test_cases/Output File4.csv deleted file mode 100644 index f265e3f..0000000 --- a/tumasulu/test_cases/Output File4.csv +++ /dev/null @@ -1,32 +0,0 @@ -Execution Table ,,,,,,,,Non-Zero Memory Values , -Instructions,ISSUE,EXEC,MEM,WB,COMMIT ,,,ADDRESS,VALUE -ADD.D F3 F5 F7,1,2, ,7,8,,,4,3 -LD F5 17(R6),2,3,4,10,11,,,8,2 -LD F3 48(R3),3,4,10,15,16,,,12,1 -ADD R2 R4 R6,4,5, ,6,17,,,24,6 -MULT.D F4 F7 F2,5,6, ,21,22,,,28,5 -ADD R4 R4 R5,6,7, ,8,23,,,32,4 -ADD R8 R4 R5,7,8, ,9,24,,,, -MULT.D F7 F4 F2,8,9, ,24,25,,,, -ADD.D F4 F2 F7,9,25, ,29,30,,,, -ADD.D F2 F4 F8,10,30, ,34,35,,,, -,,,,,,,,, -,,,,,,,,, -Integer Register File ,,,,,,Floating point Register File ,,, -REGs,VALUE,REGs,VALUE ,,,REGs,VALUE,REGs,VALUE -R0,0,R1,0,,,F0,0,F1,0 -R2,16,R3,7,,,F2,3029.300185,F3,0 -R4,14,R5,7,,,F4,2940.300185,F5,0 -R6,9,R7,7,,,F6,30,F7,2928.200185 -R8,21,R9,0,,,F8,89,F9,0 -R10,0,R11,0,,,F10,0,F11,0 -R12,0,R13,0,,,F12,0,F13,0 -R14,0,R15,0,,,F14,0,F15,0 -R16,0,R17,0,,,F16,0,F17,0 -R18,0,R19,0,,,F18,0,F19,0 -R20,0,R21,0,,,F20,0,F21,0 -R22,0,R23,0,,,F22,0,F23,0 -R24,0,R25,0,,,F24,0,F25,0 -R26,0,R27,0,,,F26,0,F27,0 -R28,0,R29,0,,,F28,0,F29,0 -R30,0,R31,0,,,F30,0,F31,0 diff --git a/tumasulu/test_cases/Output File5.csv b/tumasulu/test_cases/Output File5.csv deleted file mode 100644 index 606eb1c..0000000 --- a/tumasulu/test_cases/Output File5.csv +++ /dev/null @@ -1,32 +0,0 @@ -Execution Table ,,,,,,,,Non-Zero Memory Values , -Instructions,ISSUE,EXEC,MEM,WB,COMMIT ,,,ADDRESS,VALUE -MULT.D F0 F2 F4,1,2, ,17,18,,,4,3 -SUB.D F2 F0 F5,2,18, ,22,23,,,8,2 -ADD.D F0 F2 F3,3,23, ,27,28,,,12,1 -LD F6 54(R2),4,5,6,13,29,,,24,6 -ADD.D F3 F15 F5,5,6, ,10,30,,,28,5 -MULT.D F0 F3 F6,6,14, ,29,31,,,32,4 -ADDI R1 R9 9,7,8, ,9,32,,,, -LD F2 17(R2),8,9,13,18,33,,,, -ADDI R1 R5 5,9,10, ,11,34,,,, -ADDI R7 R1 8,10,11, ,12,35,,,, -,,,,,,,,, -,,,,,,,,, -Integer Register File ,,,,,,Floating point Register File ,,, -REGs,VALUE,REGs,VALUE ,,,REGs,VALUE,REGs,VALUE -R0,0,R1,12,,,F0,0,F1,0 -R2,3,R3,0,,,F2,0,F3,55 -R4,0,R5,7,,,F4,9,F5,10 -R6,5,R7,20,,,F6,0,F7,0 -R8,6,R9,8,,,F8,0,F9,0 -R10,6,R11,0,,,F10,0,F11,0 -R12,0,R13,0,,,F12,0,F13,0 -R14,0,R15,0,,,F14,0,F15,45 -R16,0,R17,0,,,F16,0,F17,0 -R18,0,R19,0,,,F18,0,F19,0 -R20,0,R21,0,,,F20,0,F21,0 -R22,0,R23,0,,,F22,0,F23,0 -R24,0,R25,0,,,F24,0,F25,0 -R26,0,R27,0,,,F26,0,F27,0 -R28,0,R29,0,,,F28,0,F29,0 -R30,0,R31,0,,,F30,0,F31,0 diff --git a/tumasulu/test_cases/Output File7.csv b/tumasulu/test_cases/Output File7.csv deleted file mode 100644 index bcfbf86..0000000 --- a/tumasulu/test_cases/Output File7.csv +++ /dev/null @@ -1,32 +0,0 @@ -Execution Table ,,,,,,,,Non-Zero Memory Values , -Instructions,ISSUE,EXEC,MEM,WB,COMMIT ,,,ADDRESS,VALUE -LD F1 10(R2),1,2,3,8,9,,,4,3 -LD F2 20(R3),2,3,8,13,14,,,8,2 -LD F3 20(R4),3,4,13,19,20,,,12,1 -ADD.D F4 F3 F2,4,20, ,24,25,,,14,-5 -SUB.D F5 F2 F1,5,14, ,18,26,,,21,5 -ADD.D F2 F3 F2,6,21, ,26,27,,,24,6 -SUB.D F6 F5 F4,19,25, ,29,30,,,28,5 -SD F6 10(R2),20,21, , ,31,,,32,4 -ADD R1 R2 R3,21,22, ,23,32,,,, -SD F2 11(R1),22,24, , ,36,,,, -,,,,,,,,, -,,,,,,,,, -Integer Register File ,,,,,,Floating point Register File ,,, -REGs,VALUE,REGs,VALUE ,,,REGs,VALUE,REGs,VALUE -R0,0,R1,10,,,F0,0,F1,0 -R2,4,R3,6,,,F2,5,F3,5 -R4,8,R5,0,,,F4,5,F5,0 -R6,0,R7,0,,,F6,-5,F7,0 -R8,0,R9,0,,,F8,0,F9,0 -R10,0,R11,0,,,F10,0,F11,0 -R12,0,R13,0,,,F12,0,F13,0 -R14,0,R15,0,,,F14,0,F15,0 -R16,0,R17,0,,,F16,0,F17,0 -R18,0,R19,0,,,F18,0,F19,0 -R20,0,R21,0,,,F20,0,F21,0 -R22,0,R23,0,,,F22,0,F23,0 -R24,0,R25,0,,,F24,0,F25,0 -R26,0,R27,0,,,F26,0,F27,0 -R28,0,R29,0,,,F28,0,F29,0 -R30,0,R31,0,,,F30,0,F31,0 diff --git a/tumasulu/test_cases/Output File8.csv b/tumasulu/test_cases/Output File8.csv deleted file mode 100644 index 046d661..0000000 --- a/tumasulu/test_cases/Output File8.csv +++ /dev/null @@ -1,120 +0,0 @@ -Execution Table -Instructions,ISSUE,EXEC,MEM,WB,COMMIT -MULT.D F4 F7 F2,1,2, ,17,18 -MULT.D F8 F4 F1,2,20, ,35,36 -MULT.D F8 F2 F3,18,19, ,34,37 -ADD.D F9 F10 F11,19,20, ,24,38 -LD F5 17(R6),20,21,22,28,39 -LD F3 48(R3),21,22,28,33,40 -ADD.D F7 F4 F2,22,23, ,27,41 -ADD.D F10 F7 F2,23,28, ,32,42 -LD F11 17(R6),24,25,33,38,43 -MULT.D F6 F3 F1,35,36, ,51,52 - - -Integer Register File -REGs,VALUE,REGs,VALUE -R0,0,R1,0 -R2,0,R3,7 -R4,0,R5,0 -R6,8,R7,0 -R8,0,R9,0 -R10,0,R11,0 -R12,0,R13,0 -R14,0,R15,0 -R16,0,R17,0 -R18,0,R19,0 -R20,0,R21,0 -R22,0,R23,0 -R24,0,R25,0 -R26,0,R27,0 -R28,0,R29,0 -R30,0,R31,0 - - -Floating point Register File -REGs,VALUE,REGs,VALUE -F0,0.0,F1,1.0 -F2,6.0,F3,0.0 -F4,42.0,F5,0.0 -F6,0.0,F7,48.0 -F8,36.0,F9,12.0 -F10,54.0,F11,0.0 -F12,0.0,F13,0.0 -F14,0.0,F15,0.0 -F16,0.0,F17,0.0 -F18,0.0,F19,0.0 -F20,0.0,F21,0.0 -F22,0.0,F23,0.0 -F24,0.0,F25,0.0 -F26,0.0,F27,0.0 -F28,0.0,F29,0.0 -F30,0.0,F31,0.0 - - -Non-Zero Memory Values -ADDRESS,VALUE -0,0.0 -1,0.0 -2,0.0 -3,0.0 -4,3.0 -5,0.0 -6,0.0 -7,0.0 -8,2.0 -9,0.0 -10,0.0 -11,0.0 -12,1.0 -13,0.0 -14,0.0 -15,0.0 -16,0.0 -17,0.0 -18,0.0 -19,0.0 -20,0.0 -21,0.0 -22,0.0 -23,0.0 -24,6.0 -25,0.0 -26,0.0 -27,0.0 -28,5.0 -29,0.0 -30,0.0 -31,0.0 -32,4.0 -33,0.0 -34,0.0 -35,0.0 -36,0.0 -37,0.0 -38,0.0 -39,0.0 -40,0.0 -41,0.0 -42,0.0 -43,0.0 -44,0.0 -45,0.0 -46,0.0 -47,0.0 -48,0.0 -49,0.0 -50,0.0 -51,0.0 -52,0.0 -53,0.0 -54,0.0 -55,0.0 -56,0.0 -57,0.0 -58,0.0 -59,0.0 -60,0.0 -61,0.0 -62,0.0 -63,0.0 diff --git a/tumasulu/tumasulu.cpp b/tumasulu/tumasulu.cpp deleted file mode 100644 index 822dc36..0000000 --- a/tumasulu/tumasulu.cpp +++ /dev/null @@ -1,2256 +0,0 @@ -// tumasulu.cpp : This file contains the 'main' function. Program execution begins and ends there. -// Decleration of libraries and classes. -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "RegFiles.h" -#include "InstBuffer.h" -#include "RAT.h" -#include "RsIU.h" -#include "RsFU.h" -#include "Memory.h" -#include "ROB.h" -#include "ExeTable.h" -#include "LdSdQueue.h" -#include "Import.h" -#include "queue.h" -#include "Output.h" - -using namespace std; - -//---------------------------------------------------------------------------------------------------------// -//---------------------------------******Global variables*******-------------------------------------------- -//---------------------------------------------------------------------------------------------------------// -int cycles; // cycles count (starting from 1). -int pc; // program counter (used as a pointer for the instruction buffer). -int ETable_pc; // Execution Table pointer (used as a pointer for the instruction buffer). -int ETable_entries; // No. of Execution table entries (I guess it would be better if implemented ad linked list because you don't know how many entries will be). -int RegFiles_entries = 32; // No. of Register files entries (it is stated that they are fixed). -int IQ_entries; // No. of Instruction Buffer entries (should be calculated from the input parser). -int Mem_entries = 64; // No. of Memory entries (it is stated that they are fixed). -int ROB_entries; // No. of Reorder buffer entries. -int LSQ_entries; // No. of Load Store Queue Rs entries. -int RSFA_entries; // No. of Floating point Adders Reservation Stations entries. -int RSFM_entries; // No. of Floating point Multiplier Reservation Stations entries. -int RSI_entries; // No. of Integer Reservation Stations entries. -int FA_cycles; -int FM_cycles; -int I_cycles; -int LS_cycles_ex; -int LS_cycles_mem; -int FA_funcUnits; -int FM_funcUnits; -int I_funcUnits; -int LS_funcUnits; -bool IU_busy; // if IU is busy -bool Mem_busy; // if Mem is busy -bool Mem_busy_sd; // if Mem is busy due to store -int Cycle_Mem_busy; // the cycle the meory was busy in. -bool CDB_busy; // if Mem is busy -bool Stall; // whether to stall or not. -int inst_count; // no of the instruction for commiting purposes. -int inst_commit; // the instruction that should commit. -int LSQ_count; // LSQ count. -bool dont_fetch; // the instruction that should commit. - -//------------------------------------------------------------------------------------------------------------------ -//-------- Project Arch--------------------------------------------------------------------------------------------- - -Import input; // object of out input file -RegFiles* RF = new RegFiles[RegFiles_entries]; // pointer to 32 register files -ExeTable* Extable; // pointer to extable -InstBuffer* IQ; // pointer to inst buffer -ROB* Rob; // pointer to ROB -RAT* Rat; // pointer to RAT -Memory* Mem = new Memory[Mem_entries]; // pointer to memory -queue LSQ; // Global definition of LSQ. -RsFU* RSFA; // Global definition of RSFA. -RsFU* RSFM; // Global definition of RSFM. -RsIU* RSI; // Global definition of RSI. - - -//------------------------------------------------------------------------------------------------------------------ -//------------------------------------------------------------------------------------------------------------------ - -/////////////////////////////////////////////////////////// -//////////////// Functions Implementations //////////////// -////////////////////////////////////////////////////////// - -void Arch_unit() { - cycles = 1; // start from cycle 1. - pc = 0; // first instruction. - ETable_pc = 0; // ExecTable pointer. - Mem_busy = false; - Mem_busy_sd = false; - IU_busy = false; - CDB_busy = false; - Stall = false; - inst_count = 0; - inst_commit = 0; - dont_fetch = false; - LSQ_count = 0; - //------------------------------------------------------------------- - // creating Exetable and puting instructions in it - Extable = new ExeTable[ETable_entries]; - for (int i = 0; i < ETable_entries; i++) { - // initialize each entry in the Execution Table. - Extable[i].Mem = 0; - } - //Extable = new ExeTable[IQ_entries]; - for (int i = 0; i < IQ_entries; i++) { - Extable[i].Instruction = input.instructions[i]; - //cout << Extable[i].Instruction << endl; - - } - - - //------------------------------------------------------------------ - /// creating intial RAT which will have R1, R2,.. etc as intial value. - Rat = new RAT[RegFiles_entries]; - - for (int i = 0; i < RegFiles_entries; i++) - { - Rat[i].R = "R" + to_string(i); - Rat[i].F = "F" + to_string(i); - //cout << Rat[i].R << endl; - //cout << Rat[i].F << endl; - } - //----------------------------------------------------------------------- - //intializing memory - - for (int i = 0; i < Mem_entries; i++) { - Mem[i].Value = 0.0; - } - - for (int i = 0; i < input.memory_var.size(); i++) - { - // my format is Mem[4]=1 , Mem[12]=3.4 ... etc - string delimiter = "]"; - string token = input.memory_var[i].substr(4, input.memory_var[i].find(delimiter) - 4); //token1 is 1, 2,......,etc - string value = input.memory_var[i].substr(input.memory_var[i].find(delimiter) + 2, input.memory_var[i].length()); - int Mem_entry = input.convertStringToInt(token); - Mem[Mem_entry].Value = input.convertStringToFloat(value); - - } - - for (int i = 0; i < Mem_entries; i++) - { - - if (Mem[i].Value == NULL) // because some will initialized in the input parser - { - Mem[i].Value = 0.0; - Mem[i].ischanged = false; - } - } - - //-------------------------------------------------------------------------------------------------------- - RSFM = new RsFU[RSFM_entries]; // initialize each entry in the RSFM. - for (int i = 0; i < RSFM_entries; i++) - { - RSFM[i].Busy = false; - RSFM[i].Qj = "NULL"; - RSFM[i].Qk = "NULL"; - - } - - RSFA = new RsFU[RSFA_entries]; // initialize each entry in the RSFA. - - for (int i = 0; i < RSFA_entries; i++) - { - RSFA[i].Busy = false; - RSFA[i].Qj = "NULL"; - RSFA[i].Qk = "NULL"; - } - RSI = new RsIU[RSI_entries]; // initialize each entry in the RSI. - - for (int i = 0; i < RSI_entries; i++) - { - RSI[i].Busy = false; - RSI[i].Qj = "NULL"; - RSI[i].Qk = "NULL"; - } - - - -} -//------------------------------------------------------------------------------------------------------------------------ - -void Fetch() -{ - string temp; - int index; - LdSdQueue* LSQ_temp = new LdSdQueue(); - bool f; - - -L1: if (pc >= IQ_entries) -{ - dont_fetch = true; - Stall = true; - return; -} -string Opcode = IQ[pc].Opcode; -for_each(Opcode.begin(), Opcode.end(), [](char& c) { - c = ::toupper(c); - }); -//cout << Opcode << endl; -if (Opcode == "LD") { - if (LSQ_count < LSQ_entries) { - // we have a space in Load store Queue (you can check from any field). - for (int j = 0; j < ROB_entries; j++) { - if (!Rob[j].Busy) { - //find a free ROB entry - LSQ_temp->Inst = IQ[pc].Opcode + " " + IQ[pc].Dest + " " + IQ[pc].Src1 + "(" + IQ[pc].Src2 + ")"; // store whole instruction for debugging purposes. - LSQ_temp->Opcode = IQ[pc].Opcode; // may be removed later if of no use. - LSQ_temp->ETable_Entry = ETable_pc; - LSQ_temp->ROB_entry = j; - LSQ_temp->State = "NULL"; - Rob[j].Busy = true; - Rob[j].Inst = IQ[pc].Opcode + " " + IQ[pc].Dest + " " + IQ[pc].Src1 + "(" + IQ[pc].Src2 + ")"; // store whole instruction for debugging purposes. - Rob[j].Dest = IQ[pc].Dest; // store the destination in ROB entry. - Rob[j].Opcode = IQ[pc].Opcode; - Rob[j].ETable_Entry = ETable_pc; - Rob[j].State = "NULL"; - //cout << LSQ_temp->Inst << endl; - //cout << Rob[j].Inst << endl; - // resolving Src1 - //cout << IQ[pc].Src2 << endl; - if (IQ[pc].Src2.find("R") != string::npos) { - temp = IQ[pc].Src2.substr(1, IQ[pc].Src2.find('R') - 1); // remove R to convert it to integer. - index = input.convertStringToInt(temp); - //cout << index << endl; - if (index < RegFiles_entries) { - //correct input range. - //Rat[1].R = "ROB3"; - //Rob[3].Value = 100.6; - //Rob[3].State = "Write_Back"; - if (Rat[index].R.find("ROB") != string::npos) // Src2 is in ROB - { - temp = Rat[index].R.substr(3, Rat[index].R.find("ROB") - 1); // remove ROB to convert it to integer. - index = input.convertStringToInt(temp); - //cout << index << endl; - // check if this entry is in the write back or commit stage. - if ((Rob[index].State == "Write_Back") || (Rob[index].State == "Commit")) - { - int conv = (int)Rob[index].Value; - LSQ_temp->Reg = to_string(conv); // copy from ROB to LSQ - //cout << LSQ_temp->Reg << endl; - try - { - input.convertStringToInt(LSQ_temp->Reg); - LSQ_temp->State = "Ready"; - } - catch (exception e) // invalid format - { - - } - //cout <<"LD1"<< LSQ_temp->State << endl; - - } - else - { // instruction is not finished yet, store ROB entry in LSQ.Reg. - LSQ_temp->Reg = "ROB" + to_string(index); - //cout << LSQ_temp->Reg <<"Rob plus index"<< endl; - - } - } - else if (Rat[index].R.find("R") != string::npos) // Src2 is in ARF - { - temp = Rat[index].R.substr(1, Rat[index].R.find('R') - 1); // remove R to convert it to integer. - index = input.convertStringToInt(temp); - int conv = RF[index].intRegFile; - LSQ_temp->Reg = to_string(conv); // copy from ARF to LSQ - //cout << LSQ_temp->Reg << "Found in arf" << endl; - try - { - input.convertStringToInt(LSQ_temp->Reg); - LSQ_temp->State = "Ready"; - } - catch (exception e) // invalid format - { - } - //cout <<"LD2"<< LSQ_temp->State << endl; - - } - - } - else // Src1 input range is exceeded. - { - cout << "Src1 exceeded range of register files." << endl; - exit(1); // exit code. - } - } - else // wrong Src2 format - { - cout << "Src1 field is wrong, should be in the format of 'Rx'" << endl; - exit(1); // exit code. - } - // resolving Src2, immediate value, just copy to LSQ.Offset. - - try - { - LSQ_temp->Offset = input.convertStringToInt(IQ[pc].Src1); - } - catch (exception e) // invalid format - { - cout << "Src2 field for Ld/St operations should be integer" << endl; - exit(1); // exit code. - } - //cout << LSQ_temp->Offset << endl; - // store destination in LSQ.Dest if it is a load - - if (IQ[pc].Dest.find("F") != string::npos) - { - temp = IQ[pc].Dest.substr(1, IQ[pc].Dest.find('F') - 1);// remove F to convert it to integer. - index = input.convertStringToInt(temp); - Rat[index].F = "ROB" + to_string(j); // store the ROB destination. - LSQ_temp->Dest = "ROB" + to_string(j); // store the ROB destination. - } - else // wrong Dest format - { - cout << "Dest field is wrong, should be in the format of 'Rx'" << endl; - exit(1); // exit code. - } - - // this point means instruction was correctly fetched an decode, increment pc then, update ExecTable. - pc++; - Extable[ETable_pc].Instruction = LSQ_temp->Inst; - Extable[ETable_pc].Issue = cycles; - ETable_pc++; - LSQ.push(*LSQ_temp); // add the entry to the lSQ. - LSQ_count++; - break; // break the loop found an empty ROB - } - //break; - } - - } - - //goto L1; -} -else if (Opcode == "SD") { - if (LSQ_count < LSQ_entries) // we have a space in Load store Queue (you can check from any field). - { - for (int j = 0; j < ROB_entries; j++) //searching for an empty ROB space - { - if (!Rob[j].Busy) { - - //find a free ROB entry - LSQ_temp->Inst = IQ[pc].Opcode + " " + IQ[pc].Dest + " " + IQ[pc].Src1 + "(" + IQ[pc].Src2 + ")"; // store whole instruction for debugging purposes. - LSQ_temp->Opcode = IQ[pc].Opcode; // may be removed later if of no use. - LSQ_temp->ETable_Entry = ETable_pc; - LSQ_temp->ROB_entry = j; - LSQ_temp->State = "NULL"; - Rob[j].Busy = true; - Rob[j].Inst = IQ[pc].Opcode + " " + IQ[pc].Dest + " " + IQ[pc].Src1 + "(" + IQ[pc].Src2 + ")"; // store whole instruction for debugging purposes. - Rob[j].Dest = IQ[pc].Dest; // store the destination in ROB entry. - Rob[j].Opcode = IQ[pc].Opcode; - Rob[j].ETable_Entry = ETable_pc; - Rob[j].State = "NULL"; - //cout << LSQ_temp->Inst << endl; - //cout << Rob[j].Inst << endl; - // resolving Src1 - - //cout << IQ[pc].Src2 << endl; - if (IQ[pc].Src2.find("R") != string::npos) { - temp = IQ[pc].Src2.substr(1, IQ[pc].Src2.find('R') - 1); // remove R to convert it to integer. - index = input.convertStringToInt(temp); - //cout << index << endl; - if (index < RegFiles_entries) { - //correct input range. - //Rat[2].R = "ROB4"; - //Rob[4].Value = 101.9; - //Rob[4].State = "Write_Back"; - if (Rat[index].R.find("ROB") != string::npos) // Src2 is in ROB - { - temp = Rat[index].R.substr(3, Rat[index].R.find("ROB") - 1); // remove ROB to convert it to integer. - index = input.convertStringToInt(temp); - //cout << index << endl; - // check if this entry is in the write back or commit stage. - if ((Rob[index].State == "Write_Back") || (Rob[index].State == "Commit")) - { - int conv = (int)Rob[index].Value; - LSQ_temp->Reg = to_string(conv); // copy from ROB to LSQ - //cout << LSQ_temp->Reg << endl; - try - { - input.convertStringToInt(LSQ_temp->Reg); - LSQ_temp->State = "Ready"; - } - catch (exception e) // invalid format - { - } - //cout << "SD1"<State << endl; - } - else - { // instruction is not finished yet, store ROB entry in LSQ.Reg. - LSQ_temp->Reg = "ROB" + to_string(index); - //cout << LSQ_temp->Reg << endl; - } - } - else if (Rat[index].R.find("R") != string::npos) // Src2 is in ARF - { - temp = Rat[index].R.substr(1, Rat[index].R.find('R') - 1); // remove R to convert it to integer. - index = input.convertStringToInt(temp); - int conv = RF[index].intRegFile; - LSQ_temp->Reg = to_string(conv); // copy from ARF to LSQ - try - { - input.convertStringToInt(LSQ_temp->Reg); - LSQ_temp->State = "Ready"; - } - catch (exception e) // invalid format - { - } - //cout << "SD2" << LSQ_temp->State << endl; - - } - - } - else // Src1 input range is exceeded. - { - cout << "Src1 exceeded range of register files." << endl; - exit(1); // exit code. - } - } - else // wrong Src2 format - { - cout << "Src1 field is wrong, should be in the format of 'Rx'" << endl; - exit(1); // exit code. - } - // resolving Src2, immediate value, just copy to LSQ.Offset. - - try - { - LSQ_temp->Offset = input.convertStringToInt(IQ[pc].Src1); - } - catch (exception e) // invalid format - { - cout << "Src2 field for Ld/St operations should be integer" << endl; - exit(1); // exit code. - } - //cout << LSQ_temp->Offset << endl; - // store destination in LSQ.Dest if it is a load - - if (IQ[pc].Dest.find("F") != string::npos) - { - temp = IQ[pc].Dest.substr(1, IQ[pc].Dest.find('F') - 1);// remove F to convert it to integer. - index = input.convertStringToInt(temp); - Rat[index].F = "ROB" + to_string(j); // store the ROB destination. - LSQ_temp->Dest = "ROB" + to_string(j); // store the ROB destination. - } - else // wrong Dest format - { - cout << "Dest field is wrong, should be in the format of 'Rx'" << endl; - exit(1); // exit code. - } - - // this point means instruction was correctly fetched an decode, increment pc then, update ExecTable. - pc++; - Extable[ETable_pc].Instruction = LSQ_temp->Inst; - Extable[ETable_pc].Issue = cycles; - ETable_pc++; - LSQ.push(*LSQ_temp); // add the entry to the lSQ. - LSQ_count++; - break; // break the loop found an empty ROB - - } - // break; - } - - } - //goto L1; -} - - -else if (Opcode == "BEQ" || Opcode == "BNE") { - // offset is Dest field, Rs and Rt is Src1 and Src2. - // 3 is dest is Src2 , R2 is src1 is Dest , R3 is Scr2 is Src1 - for (int i = 0; i < RSI_entries; i++) { - if (!RSI[i].Busy) - { //find an empty reservation station - Stall = true; // stop fetching till you figure out the destination address. - RSI[i].Busy = true; - RSI[i].Inst = IQ[pc].Opcode + " " + IQ[pc].Dest + " " + IQ[pc].Src1 + " " + IQ[pc].Src2; // store whole instruction for debugging purposes. - RSI[i].Opcode = IQ[pc].Opcode; // may be removed later if of no use. - RSI[i].ETable_Entry = ETable_pc; - //cout << RSI[i].Inst << endl; - // resolving dest - - if (IQ[pc].Dest.find("R") != string::npos) - { - temp = IQ[pc].Dest.substr(1, IQ[pc].Dest.find('R') - 1); // remove R to convert it to integer. - index = input.convertStringToInt(temp); - //cout << "dest index "<Inst << endl; - for (int i = 0; i < LSQ.d_queue.size(); i++) { - //*LSQ_temp = LSQ.pop(); - //cout << LSQ_temp->Inst << endl; - *LSQ_temp=LSQ.d_queue[i]; - LSQ.d_queue[i].Inst = "gj"; - //cout << LSQ_temp->Inst << endl; - } - *LSQ_temp = LSQ.pop(); - cout << LSQ_temp->Inst << endl; - *LSQ_temp = LSQ.pop(); - cout << LSQ_temp->Inst << endl; */ - - if (cycles > 1) // No instruction could start execution before cycle 2. - { - // Go for the Integer Functional Unit first - - L2: if (IU_busy) // if we have an instruction which is executing - { - for (int i = 0; i < RSI_entries; i++) - { - if (RSI[i].Busy && (RSI[i].State == "Execute") && !brk) // if we have an instruction and is executed then move to the next FU, because IU is not pipelined - { - temp = RSI[i].Cycle + I_cycles; // is it time to write back or not. - if (temp <= cycles) // if it is time - { - string Opcode = RSI[i].Opcode; - for_each(Opcode.begin(), Opcode.end(), [](char& c) { - c = ::toupper(c); - }); - //cout << Opcode << endl; - if (Opcode == "BEQ") - { - result_bool = (RSI[i].Vj == RSI[i].Vk); // get the result. - - if (result_bool) - { - pc = pc + RSI[i].Addr; - } - Stall = false; // don't stall any more. - Fetch(); - // empty the ES entry and update the ExecTable. - RSI[i].Busy = false; - RSI[i].State = "NULL"; - //ETable[RSI[i].ETable_Entry].WB = cycles; - IU_busy = false; - for (int k = 0; k < RSI_entries; k++) - { - if (RSI[k].Busy && (RSI[k].State == "Ready") && (Extable[RSI[k].ETable_Entry].Issue < cycles)) // if it is ready and issued prior - { - RSI[k].State = "Execute"; - RSI[k].Cycle = cycles; - Extable[RSI[k].ETable_Entry].Exec = cycles; - IU_busy = true; - break; - } - } - // we updated all the things here then break; - //break; - } - else if (Opcode == "BNE") { - result_bool = (RSI[i].Vj != RSI[i].Vk); // get the result. - if (result_bool) { - pc = pc + RSI[i].Addr; - } - - Stall = false; // don't stall any more. - Fetch(); - // empty the ES entry and update the ExecTable. - RSI[i].Busy = false; - RSI[i].State = "NULL"; - //Extable[RSI[i].ETable_Entry].WB = cycles; - IU_busy = false; - for (int k = 0; k < RSI_entries; k++) - { - if (RSI[k].Busy && (RSI[k].State == "Ready") && (Extable[RSI[k].ETable_Entry].Issue < cycles)) // if it is ready and issued prior - { - RSI[k].State = "Execute"; - RSI[k].Cycle = cycles; - Extable[RSI[k].ETable_Entry].Exec = cycles; - IU_busy = true; - break; - } - //break; - } - // we updated all the things here then break; - //break; - //break; - } - else if (Opcode == "ADD" || Opcode == "ADDI") - { - if (!CDB_busy) - { - CDB_busy = true; // make the CDB busy - result = RSI[i].Vj + RSI[i].Vk; // get the result. - // get the ROB entry that needs update - string temp = RSI[i].Dest.substr(3, RSI[i].Dest.find("ROB") - 1); - ROB_index = input.convertStringToInt(temp); - Rob[ROB_index].Value = (float)result; - Rob[ROB_index].State = "Commit"; - - // find entries that need to be updated in the same RSI - for (int j = 0; j < RSI_entries; j++) - { - if (RSI[j].Busy) - { - if (RSI[j].Qj.compare(RSI[i].Dest) == 0) // if any of the Q field match the Dest - { - RSI[j].Qj = "NULL"; - RSI[j].Vj = (int)result; - } - - if (RSI[j].Qk.compare(RSI[i].Dest) == 0) // if any of the Q field match the Dest - { - RSI[j].Qk = "NULL"; - RSI[j].Vk = (int)result; - } - - // if all the operand are ready and the inst is not executing already - if (!((RSI[j].State == "Execute") || (RSI[j].State == "Ready"))) - if ((RSI[j].Qj == "NULL") && (RSI[j].Qk == "NULL")) - RSI[j].State = "Ready"; - } - } - // find entries that need to be updated in LSQ - - for (int j = 0; j < LSQ_count; j++) - { - //*LSQ_temp = LSQ.pop(); // pull entry - if (LSQ.d_queue[j].Reg.compare(RSI[i].Dest) == 0) - { - LSQ.d_queue[j].Reg = to_string(result); - LSQ.d_queue[j].State = "ReadyA"; - } - //LSQ.push(*LSQ_temp); // push back again, do this for all entries. - } - // empty the ES entry and update the ExecTable. - RSI[i].Busy = false; - RSI[i].State = "NULL"; - Extable[RSI[i].ETable_Entry].WB = cycles; - IU_busy = false; - // no since an instruction is done, we may start execution of another - - for (int k = 0; k < RSI_entries; k++) - { - if (RSI[k].Busy && (RSI[k].State == "Ready") && (Extable[RSI[k].ETable_Entry].Issue < cycles)) // if it is ready and issued prior - { - RSI[k].State = "Execute"; - RSI[k].Cycle = cycles; - Extable[RSI[k].ETable_Entry].Exec = cycles; - IU_busy = true; - break; - } - //break; - } - // we updated all the things here then break; - break; - } - // break; - } - else if (Opcode == "SUB") - { - if (!CDB_busy) - { - CDB_busy = true; // make the CDB busy - result = RSI[i].Vj - RSI[i].Vk; // get the result. - // get the ROB entry that needs update - string temp = RSI[i].Dest.substr(3, RSI[i].Dest.find("ROB") - 1); - ROB_index = input.convertStringToInt(temp); - Rob[ROB_index].Value = (float)result; - Rob[ROB_index].State = "Commit"; - - // find entries that need to be updated in the same RSI - - for (int j = 0; j < RSI_entries; j++) - { - if (RSI[j].Busy) - { - if (RSI[j].Qj.compare(RSI[i].Dest)==0) // if any of the Q field match the Dest - { - RSI[j].Qj = "NULL"; - RSI[j].Vj = (int)result; - } - - if (RSI[j].Qk.compare(RSI[i].Dest)==0) // if any of the Q field match the Dest - { - RSI[j].Qk = "NULL"; - RSI[j].Vk = (int)result; - } - - // if all the operand are ready and the inst is not executing already - if (!((RSI[j].State == "Execute") || (RSI[j].State == "Ready"))) - if ((RSI[j].Qj == "NULL") && (RSI[j].Qk == "NULL")) - RSI[j].State = "Ready"; - } - } - - - // find entries that need to be updated in LSQ - - for (int j = 0; j < LSQ_count; j++) - { - //*LSQ_temp = LSQ.pop(); // pull entry - if (LSQ.d_queue[j].Reg.compare(RSI[i].Dest)==0) - { - LSQ.d_queue[j].Reg = to_string(result); - LSQ.d_queue[j].State = "ReadyA"; - } - //LSQ.push(*LSQ_temp); // push back again, do this for all entries. - } - // empty the ES entry and update the ExecTable. - RSI[i].Busy = false; - RSI[i].State = "NULL"; - Extable[RSI[i].ETable_Entry].WB = cycles; - IU_busy = false; - // no since an instruction is done, we may start execution of another - - for (int k = 0; k < RSI_entries; k++) - { - if (RSI[k].Busy && (RSI[k].State == "Ready") && (Extable[RSI[k].ETable_Entry].Issue < cycles)) // if it is ready and issued prior - { - RSI[k].State = "Execute"; - RSI[k].Cycle = cycles; - Extable[RSI[k].ETable_Entry].Exec = cycles; - IU_busy = true; - break; - } - } - // we updated all the things here then break; - break; - } - //break; - } - - brk = true; - } - else // then we are not done yet - break; - } - - } - - } - // if IU is not busy, search for a ready instruction to execute. - else - { - for (int i = 0; i < RSI_entries; i++) - { - if (RSI[i].Busy && (RSI[i].State == "Ready") && (Extable[RSI[i].ETable_Entry].Issue < cycles)) // if it is ready and issued prior - { - RSI[i].State = "Execute"; - RSI[i].Cycle = cycles; - Extable[RSI[i].ETable_Entry].Exec = cycles; - IU_busy = true; - break; - //goto L2; - } - } - } - // Go for the FP adder Unit - - for (int i = 0; i < RSFA_entries; i++) - { - if (RSFA[i].Busy && (RSFA[i].State == "Execute")) // if we have an instruction and is executed then move to the next FU, because IU is not pipelined - { - temp = RSFA[i].Cycle + FA_cycles; // is it time to write back or not. - if (temp <= cycles) // if it is time - { - if (!CDB_busy) // and CDB is free - { - CDB_busy = true; // make the CDB busy - string Opcode = RSFA[i].Opcode; - for_each(Opcode.begin(), Opcode.end(), [](char& c) { - c = ::toupper(c); - }); - //cout << Opcode << endl; - - if (Opcode == "ADD.D") - { - result = RSFA[i].Vj + RSFA[i].Vk; // get the result. - // get the ROB entry that needs update - string temp = RSFA[i].Dest.substr(3, RSFA[i].Dest.find("ROB") - 1); - ROB_index = input.convertStringToInt(temp); - Rob[ROB_index].Value = result; - Rob[ROB_index].State = "Commit"; - - // find entries that need to be updated in the same RSFA - - for (int j = 0; j < RSFA_entries; j++) - { - if (RSFA[j].Busy) - { - if (RSFA[j].Qj.compare(RSFA[i].Dest) == 0) // if any of the Q field match the Dest - { - RSFA[j].Qj = "NULL"; - RSFA[j].Vj = result; - } - - if (RSFA[j].Qk.compare(RSFA[i].Dest) == 0) // if any of the Q field match the Dest - { - RSFA[j].Qk = "NULL"; - RSFA[j].Vk = result; - } - - // if all the operand are ready and the inst is not executing already - if (!((RSFA[j].State == "Execute") || (RSFA[j].State == "Ready"))) - if ((RSFA[j].Qj == "NULL") && (RSFA[j].Qk == "NULL")) - RSFA[j].State = "Ready"; - } - } - // find entries that need to be updated in LSQ - for (int j = 0; j < LSQ_count; j++) - { - //*LSQ_temp = LSQ.pop(); // pull entry - if (LSQ.d_queue[j].Dest.compare(RSFA[i].Dest) == 0) { - LSQ.d_queue[j].Dest = to_string(result); - } - //LSQ.push(*LSQ_temp); // push back again, do this for all entries. - } - // find entries that need to be updated in the RSFM - - for (int j = 0; j < RSFM_entries; j++) - { - if (RSFM[j].Busy) - { - if (RSFM[j].Qj.compare(RSFA[i].Dest) == 0) // if any of the Q field match the Dest - { - RSFM[j].Qj = "NULL"; - RSFM[j].Vj = result; - } - - if (RSFM[j].Qk.compare(RSFA[i].Dest) == 0) // if any of the Q field match the Dest - { - RSFM[j].Qk = "NULL"; - RSFM[j].Vk = result; - } - - // if all the operand are ready and the inst is not executing already - if (!((RSFM[j].State == "Execute") || (RSFM[j].State == "Ready"))) - if ((RSFM[j].Qj == "NULL") && (RSFM[j].Qk == "NULL")) - RSFM[j].State = "ReadyA"; - } - } - // empty the ES entry and update the ExecTable. - RSFA[i].Busy = false; - RSFA[i].State = "NULL"; - Extable[RSFA[i].ETable_Entry].WB = cycles; - - // we updated all the things here then break; - break; - } - else if (Opcode == "SUB.D") - { - result = RSFA[i].Vj - RSFA[i].Vk; // get the result. - - // get the ROB entry that needs update - string temp = RSFA[i].Dest.substr(3, RSFA[i].Dest.find("ROB") - 1); - ROB_index = input.convertStringToInt(temp); - Rob[ROB_index].Value = result; - Rob[ROB_index].State = "Commit"; - // find entries that need to be updated in the same RSFA - - for (int j = 0; j < RSFA_entries; j++) - { - if (RSFA[j].Busy) - { - if (RSFA[j].Qj.compare(RSFA[i].Dest) == 0) // if any of the Q field match the Dest - { - RSFA[j].Qj = "NULL"; - RSFA[j].Vj = result; - } - - if (RSFA[j].Qk.compare(RSFA[i].Dest) == 0) // if any of the Q field match the Dest - { - RSFA[j].Qk = "NULL"; - RSFA[j].Vk = result; - } - - // if all the operand are ready and the inst is not executing already - if (!((RSFA[j].State == "Execute") || (RSFA[j].State == "Ready"))) - if ((RSFA[j].Qj == "NULL") && (RSFA[j].Qk == "NULL")) - RSFA[j].State = "Ready"; - } - } - // find entries that need to be updated in LSQ - for (int j = 0; j < LSQ_count; j++) - { - //*LSQ_temp = LSQ.pop(); // pull entry - if (LSQ.d_queue[j].Dest.compare(RSFA[i].Dest) == 0) - LSQ.d_queue[j].Dest = to_string(result); - //LSQ.push(*LSQ_temp); // push back again, do this for all entries. - } - // find entries that need to be updated in the RSFM - - for (int j = 0; j < RSFM_entries; j++) - { - if (RSFM[j].Busy) - { - if (RSFM[j].Qj.compare(RSFA[i].Dest) == 0) // if any of the Q field match the Dest - { - RSFM[j].Qj = "NULL"; - RSFM[j].Vj = result; - } - - if (RSFM[j].Qk.compare(RSFA[i].Dest) == 0) // if any of the Q field match the Dest - { - RSFM[j].Qk = "NULL"; - RSFM[j].Vk = result; - } - - // if all the operand are ready and the inst is not executing already - if (!((RSFM[j].State == "Execute") || (RSFM[j].State == "Ready"))) - if ((RSFM[j].Qj == "NULL") && (RSFM[j].Qk == "NULL")) - RSFM[j].State = "ReadyA"; - } - } - // empty the ES entry and update the ExecTable. - RSFA[i].Busy = false; - RSFA[i].State = "NULL"; - Extable[RSFA[i].ETable_Entry].WB = cycles; - - // we updated all the things here then break; - break; - } - // one instruction has write back so break, no need to loop. - break; - } - else // CDB is not free - { - break; - } - } - } - else // if instruction is ready make it execute because it is piplined - { - if (RSFA[i].Busy && (RSFA[i].State == "Ready") && (Extable[RSFA[i].ETable_Entry].Issue < cycles)) // if it is ready and issued prior) // if it is ready - { - RSFA[i].State = "Execute"; - RSFA[i].Cycle = cycles; - Extable[RSFA[i].ETable_Entry].Exec = cycles; - break; - } - } - } - // Go for the FP Multiplier Unit - for (int i = 0; i < RSFM_entries; i++) - { - if (RSFM[i].Busy && (RSFM[i].State == "Execute")) // if we have an instruction and is executed then move to the next FU, because IU is not pipelined - { - temp = RSFM[i].Cycle + FM_cycles; // is it time to write back or not. - if (temp <= cycles) // if it is time - { - if (!CDB_busy) // and CDB is free - { - CDB_busy = true; // make the CDB busy - string Opcode = RSFM[i].Opcode; - for_each(Opcode.begin(), Opcode.end(), [](char& c) { - c = ::toupper(c); - }); - //cout << Opcode << endl; - if (Opcode == "MULT.D") - { - result = RSFM[i].Vj * RSFM[i].Vk; // get the result. - - // get the ROB entry that needs update - string temp = RSFM[i].Dest.substr(3, RSFM[i].Dest.find("ROB") - 1); - ROB_index = input.convertStringToInt(temp); - Rob[ROB_index].Value = result; - Rob[ROB_index].State = "Commit"; - // find entries that need to be updated in the same RSFM - - for (int j = 0; j < RSFM_entries; j++) - { - if (RSFM[j].Busy) - { - if (RSFM[j].Qj.compare(RSFM[i].Dest)==0) // if any of the Q field match the Dest - { - RSFM[j].Qj = "NULL"; - RSFM[j].Vj = result; - } - - if (RSFM[j].Qk.compare(RSFM[i].Dest)==0) // if any of the Q field match the Dest - { - RSFM[j].Qk = "NULL"; - RSFM[j].Vk = result; - } - - // if all the operand are ready and the inst is not executing already - if (!((RSFM[j].State == "Execute") || (RSFM[j].State == "Ready"))) - if ((RSFM[j].Qj == "NULL") && (RSFM[j].Qk == "NULL")) - RSFM[j].State = "ReadyA"; - } - } - // find entries that need to be updated in LSQ - for (int j = 0; j < LSQ_count; j++) - { - //*LSQ_temp = LSQ.pop(); // pull entry - if (LSQ.d_queue[j].Dest.compare(RSFM[i].Dest)==0) - LSQ.d_queue[j].Dest = to_string(result); - //LSQ.push(*LSQ_temp); // push back again, do this for all entries. - } - // find entries that need to be updated in the RSFA - - for (int j = 0; j < RSFA_entries; j++) - { - if (RSFA[j].Busy) - { - if (RSFA[j].Qj.compare(RSFM[i].Dest)==0) // if any of the Q field match the Dest - { - RSFA[j].Qj = "NULL"; - RSFA[j].Vj = result; - } - - if (RSFA[j].Qk.compare(RSFM[i].Dest)==0) // if any of the Q field match the Dest - { - RSFA[j].Qk = "NULL"; - RSFA[j].Vk = result; - } - - // if all the operand are ready and the inst is not executing already - if (!((RSFA[j].State == "Execute") || (RSFA[j].State == "Ready"))) - if ((RSFA[j].Qj == "NULL") && (RSFA[j].Qk == "NULL")) - RSFA[j].State = "Ready"; - } - } - // empty the ES entry and update the ExecTable. - RSFM[i].Busy = false; - RSFM[i].State = "NULL"; - Extable[RSFM[i].ETable_Entry].WB = cycles; - - // we updated all the things here then break; - break; - - } - // one instruction has write back so break, no need to loop. - break; - } - else // CDB is not free - { - break; - } - } - } - else // if instruction is ready make it execute, because it is piplined - { - if (RSFM[i].Busy && (RSFM[i].State == "Ready") && (Extable[RSFM[i].ETable_Entry].Issue < cycles)) // if it is ready and issued prior - { - RSFM[i].State = "Execute"; - RSFM[i].Cycle = cycles; - Extable[RSFM[i].ETable_Entry].Exec = cycles; - - for (int j = i + 1; j < RSFM_entries; j++) - if (RSFM[i].Busy && (RSFM[i].State == "ReadyA")) // just make it ready for the next cycle. - RSFM[i].State = "Ready"; - - break; - } - else if (RSFM[i].Busy && (RSFM[i].State == "ReadyA")) // just make it ready for the next cycle. - RSFM[i].State = "Ready"; - } - } - // Go for the Load Store Functional unit - - for (int j = 0; j < LSQ_count; j++) // look for any instruction that is executing. - { - //*LSQ_temp = LSQ.pop(); // pull entry - - if ((LSQ.d_queue[j].State == "Execute")) - { - temp = LSQ.d_queue[j].Cycle + 1; // is execution finished or not. - if (temp == cycles) - { - result = (float)LSQ.d_queue[j].Offset + (int)input.convertStringToFloat(LSQ.d_queue[j].Reg); - LSQ.d_queue[j].Addr = (int)result; - // store also in the ROB.dest - for (int l = 0; l < ROB_entries; l++) - { - if (Rob[l].Busy && (Rob[l].ETable_Entry == LSQ.d_queue[j].ETable_Entry)) - { - Rob[l].Addr = (int)result; - break; - } - } - LSQ.d_queue[j].State = "Memory"; - //LSQ.push(*LSQ_temp); - break; - } - } - // LSQ.push(*LSQ_temp); - } - for (int j = 0; j < LSQ_count; j++) // look for any instruction that is ready. - { - //*LSQ_temp = LSQ.pop(); // pull entry - - if ((LSQ.d_queue[j].State == "Ready") && (Extable[LSQ.d_queue[j].ETable_Entry].Issue < cycles)) - { - LSQ.d_queue[j].State = "Execute"; - LSQ.d_queue[j].Cycle = cycles; - Extable[LSQ.d_queue[j].ETable_Entry].Exec = cycles; - //LSQ.push(*LSQ_temp); - break; - } - //LSQ.push(*LSQ_temp); - - } - - for (int j = 0; j < LSQ_count; j++) // look for any instruction that is ready. - { - //*LSQ_temp = LSQ.pop(); // pull entry - if (LSQ.d_queue[j].State == "ReadyA") { - LSQ.d_queue[j].State = "Ready"; - } - //LSQ.push(*LSQ_temp); - } - - } -} -void memory() -{ - string temp; - int index; - double val; - bool match_found = false; - bool fill_up = false; - LdSdQueue* LSQ_temp = new LdSdQueue(); - LdSdQueue* LSQ_temp1 = new LdSdQueue(); - int count = LSQ_count; - - - - if (Mem_busy && Mem_busy_sd) { - if ((Cycle_Mem_busy + LS_cycles_mem) == cycles) - { - Mem_busy = false; - Mem_busy_sd = false; - } - } - if (count == 0) - return; - if (LSQ_count == 0) - return ; - queue *LSQ_local = new queue[LSQ_count]; - //ArrayBlockingQueue LSQ_local = new ArrayBlockingQueue(LSQ_count); - if (Mem_busy) // if memory is busy - { - if ((Cycle_Mem_busy + LS_cycles_mem) <= cycles) // memory is done - { - int LSQ_size = LSQ_count; - for (int i = 0; i < LSQ_size; i++) - { - *LSQ_temp = LSQ.pop(); - if (!fill_up) - { - if ((LSQ_temp->State.compare("InMemory")==0) && !CDB_busy) // if Instruction already in memory and CDB is free - { - CDB_busy = true; - Mem_busy = false; - - val = (float)Mem[LSQ_temp->Addr].Value; - // get the ROB entry that needs update - Rob[LSQ_temp->ROB_entry].Value = val; - Rob[LSQ_temp->ROB_entry].State = "Commit"; - - // find entries that need to be updated in the same RSFA - - for (int j = 0; j < RSFA_entries; j++) - { - if (RSFA[j].Busy) - { - if (RSFA[j].Qj.compare(LSQ_temp->Dest)==0) // if any of the Q field match the Dest - { - RSFA[j].Qj = "NULL"; - RSFA[j].Vj = val; - } - - if (RSFA[j].Qk.compare(LSQ_temp->Dest)==0) // if any of the Q field match the Dest - { - RSFA[j].Qk = "NULL"; - RSFA[j].Vk = val; - } - - // if all the operand are ready and the inst is not executing already - if (!((RSFA[j].State == "Execute") || (RSFA[j].State == "Ready"))) - if ((RSFA[j].Qj == "NULL") && (RSFA[j].Qk == "NULL")) - RSFA[j].State = "Ready"; - } - } - // find entries that need to be updated in the RSFM - - for (int j = 0; j < RSFM_entries; j++) - { - if (RSFM[j].Busy) - { - if (RSFM[j].Qj.compare(LSQ_temp->Dest)==0) // if any of the Q field match the Dest - { - RSFM[j].Qj = "NULL"; - RSFM[j].Vj = val; - } - - if (RSFM[j].Qk.compare(LSQ_temp->Dest)==0) // if any of the Q field match the Dest - { - RSFM[j].Qk = "NULL"; - RSFM[j].Vk = val; - } - - // if all the operand are ready and the inst is not executing already - if (!((RSFM[j].State == "Execute") || (RSFM[j].State == "Ready"))) - if ((RSFM[j].Qj == "NULL") && (RSFM[j].Qk == "NULL")) - RSFM[j].State = "Ready"; - } - } - - // empty the ES entry and update the ExecTable. - Extable[LSQ_temp->ETable_Entry].WB = cycles; - - // check if any other instruction - - fill_up = true; - - LSQ_count--; - } - else - LSQ.push(*LSQ_temp); - } - else - LSQ.push(*LSQ_temp); - } - // check if CDB is free do its code - if (!Mem_busy) - { - fill_up = false; - for (int i = 0; i < LSQ_count; i++) - { - *LSQ_temp = LSQ.pop(); - LSQ_local[i].push(*LSQ_temp); // copy each entry to another queue to check for dependencies - if( (LSQ_temp->State.compare("Memory")==0) && !fill_up) // if Instruction in memory stage and not fill up - { - string Opcode = LSQ_temp->Opcode; - for_each(Opcode.begin(), Opcode.end(), [](char& c) { - c = ::toupper(c); - }); - //cout << Opcode << endl; - if (Opcode == "LD") - { - if (!match_found) // if I didn't find a match or no instructions are ready, then go to memory - { - Mem_busy = true; - Cycle_Mem_busy = cycles; - LSQ_temp->State = "InMemory"; - LSQ.push(*LSQ_temp); - Extable[LSQ_temp->ETable_Entry].Mem = cycles; - fill_up = true; - } - break; - } - else if (Opcode == "SD") - { - try - { - // if value is ready then yous hsould be able to commit - val = input.convertStringToFloat(LSQ_temp->Dest); - - Rob[LSQ_temp->ROB_entry].Value = val; - Rob[LSQ_temp->ROB_entry].Addr = LSQ_temp->Addr; - LSQ_temp->State = "Commit"; - Rob[LSQ_temp->ROB_entry].State = "Commit"; - fill_up = true; - LSQ_count--; - } - catch (exception e) // then value is not ready yet - { - LSQ.push(*LSQ_temp); - } - - break; - } - - } - else // if not in memory stage, put it back to the queue - LSQ.push(*LSQ_temp); - } - } - - } - } - else // if memory is free - { - for (int i = 0; i < LSQ_count; i++) - { - *LSQ_temp = LSQ.pop(); - LSQ_local->push(*LSQ_temp); // copy each entry to another queue to check for dependencies - if ((LSQ_temp->State.compare("Memory")==0) && !fill_up) // if Instruction in memory stage and not fill up - { - string Opcode = LSQ_temp->Opcode; - for_each(Opcode.begin(), Opcode.end(), [](char& c) { - c = ::toupper(c); - }); - //cout << Opcode << endl; - if (Opcode == "LD") { - if (!match_found) // if I didn't find a match or no instructions are ready, then go to memory - { - Mem_busy = true; - Cycle_Mem_busy = cycles; - LSQ_temp->State = "InMemory"; - LSQ.push(*LSQ_temp); - Extable[LSQ_temp->ETable_Entry].Mem = cycles; - fill_up = true; - } - break; - - } - else if (Opcode == "SD") { - try - { - // if value is ready then yous hsould be able to commit - val = input.convertStringToFloat(LSQ_temp->Dest); - - Rob[LSQ_temp->ROB_entry].Value = val; - Rob[LSQ_temp->ROB_entry].Addr = LSQ_temp->Addr; - LSQ_temp->State = "Commit"; - Rob[LSQ_temp->ROB_entry].State = "Commit"; - LSQ_count--; - fill_up = true; - } - catch (exception e) // then value is not ready yet - { - LSQ.push(*LSQ_temp); - } - break; - } - } - else // if not in memory stage, put it back to the queue - LSQ.push(*LSQ_temp); - } - } -} -void commit() -{ - bool temp; - int index; - string test; - test = Extable[inst_commit].Instruction; - if ((test.find("BNE")!= string::npos) || (test.find("BEQ")!= string::npos) )// if next instruction is Branch then increment inst_commit - inst_commit++; //instruction that should commit - - for (int i = 0; i < ROB_entries; i++) - { - - // if entry is busy and instruction is ready to commit and in order - temp = Rob[i].Busy && (Rob[i].State.compare("Commit")==0) && (Rob[i].ETable_Entry == inst_commit); - temp = temp && (Extable[Rob[i].ETable_Entry].WB < cycles); - if (temp) - { - string Opcode = Rob[i].Opcode; - for_each(Opcode.begin(), Opcode.end(), [](char& c) { - c = ::toupper(c); - }); - //cout << Opcode << endl; - if (Opcode == "ADD" || Opcode == "SUB" || Opcode == "ADDI") - { - string x = Rob[i].Dest.substr(1, Rob[i].Dest.find('R') - 1); // remove R to convert it to integer. - index = input.convertStringToInt(x); - RF[index].intRegFile = (int)Rob[i].Value; // update register file. - // check whether to update the RAT or not. - if (Rat[index].R.compare("ROB" + to_string(i))==0) - Rat[index].R = "R" + to_string(index); - } - else if (Opcode == "ADD.D" || Opcode == "SUB.D" || Opcode == "MULT.D" || Opcode == "LD") - { - string x = Rob[i].Dest.substr(1, Rob[i].Dest.find('F') - 1); // remove F to convert it to integer. - index = input.convertStringToInt(x); - RF[index].floatRegFile = Rob[i].Value; // update register file. - } - else if (Opcode == "SD") - { - if (Mem_busy) - return; - - index = Rob[i].Addr; // get index of register file - Mem[index].Value = Rob[i].Value; // update register file. - - Mem_busy = true; - Cycle_Mem_busy = cycles; - Mem_busy_sd = true; - } - Rob[i].Busy = false; - Rob[i].State = "NULL"; - Extable[Rob[i].ETable_Entry].Commit = cycles; - inst_commit++; - break; - } - //break; - } -} - - -//---------------------------------------------------------------------------------------------------------------------- -void intialize() { - //creat inst. buffer, Register file, ROB and intialize parameters needed - //Import input; - input.ReadInput(); //read iput txt file and generating a new txt file with no extra spaces or commas - input.SetVariables(); //getting needed info from txt file - ROB_entries = input.ROB_entries; - RSFM_entries = input.FP_Mul_rs; - LSQ_entries = input.LdSd_rs; - RSFA_entries = input.FP_adder_rs; - RSI_entries = input.Int_adder_rs; - FA_cycles = input.FP_adder_ex; - FM_cycles = input.FP_Mul_ex; - I_cycles = input.Int_adder_ex; - LS_cycles_ex = input.LdSd_ex; - LS_cycles_mem = input.LdSd_mem; - FA_funcUnits = input.FP_adder_fu; - FM_funcUnits = input.FP_Mul_fu; - I_funcUnits = input.Int_adder_fu; - LS_funcUnits = input.LdSd_fu; - IQ_entries = (input.instructions.size()); //no of inst we have - //cout << "no of inst " << IQ_entries << endl; - - //creating ROB that has 128 entry(stated)--------------------------------------------------------------- - Rob = new ROB[ROB_entries]; - for (int i = 0; i < ROB_entries; i++) - { - //Rob = new ROB[i]; // initialize each entry in the ROB. - Rob[i].Busy = false; - } - //----------------------------------------------------------------------------------------------------- - // creating our instruction buffer - - IQ = new InstBuffer[IQ_entries]; // pointer to instruction buffer - - for (int i = 0; i < IQ_entries; i++) { - vector temp = input.ReadInstruction(input.instructions[i]); //we know that temp size is always 4 - (*(IQ + i)).Opcode = temp[0]; - (*(IQ + i)).Dest = temp[1]; - //(*(Rob + i)).Dest = temp[1]; - (*(IQ + i)).Src1 = temp[2]; - (*(IQ + i)).Src2 = temp[3]; - //output test-------------------------------------------------------------------------------- - /* - cout << "opcode " << i << (*(IQ + i)).Opcode << endl; - cout << "Dest " << i << (*(IQ + i)).Dest << endl; - cout<< "dest rob "<< i << (*(Rob +i)).Dest <Inst << endl; // just a test for queue class - *Lsq = LSQ.pop(); - cout << Lsq->Inst << endl; // just a test for queue class */ - //commit(); - //cout << IQ[0].Dest << endl; - //cout << "R0 "<