Adding proper support for RISC-V

[tact1m4n3]

Just some thoughts to improve the riscv support in microzig. 😀 Maybe we could discuss this further in this issue.

Problems:

1. Currently, it seems that for each riscv chip we are creating a new cpu implementation from scratch.
   • Quite inefficient.
   • Implementations are not required to follow a template.
   • This is somehow understandable because some cpus implement custom extensions.
2. regz does not properly support a riscv vector table.
   • Because of the nature of the riscv vector table I don't think regz is able to create it.
3. start.zig places the vector table no matter what at the start of the flash. Maybe this export should be moved to each cpu implementation that requires it since on riscv the entrypoint might be at the beginning of the flash.

Ideas:

1. Unifying all riscv cpus in a single implementation. Due to microzig's modular design, it would be easy to make the implementation load some configuration. (we could make a chip definition also take in a cpu configuration that is a zig file maybe? or just use the existing hal, board, app to do the configuration). Some stuff that should be configurable:
   • entry point
   • logic for selecting the right handler to call for an external interrupt (on the pico this depends on a custom extension implemented for the hazard3)
   • defining what goes in VectorTableOptions which is currently defined in start.zig based on chip.VectorTable
2. Maybe regz should just give a list of all interrupts for the chip and each cpu should do the generation of the VectorTable.