diff --git a/.gitignore b/.gitignore index 5c171958..ab500c64 100644 --- a/.gitignore +++ b/.gitignore @@ -9,3 +9,5 @@ boxzer-out microzig-deploy/ zig-cache/ zig-out/ + +*.regz diff --git a/port/stmicro/stm32/src/chips/all.zig b/port/stmicro/stm32/src/chips/all.zig index 5858aca2..4d958d58 100644 --- a/port/stmicro/stm32/src/chips/all.zig +++ b/port/stmicro/stm32/src/chips/all.zig @@ -305338,15 +305338,47 @@ pub const types = struct { }), /// sample time register 1 SMPR1: mmio.Mmio(packed struct(u32) { - /// Channel x sample time selection - SMP: SAMPLE_TIME, - padding: u29, + /// (1/8 of SMP) Channel x sample time selection + @"SMP[0]": SAMPLE_TIME, + /// (2/8 of SMP) Channel x sample time selection + @"SMP[1]": SAMPLE_TIME, + /// (3/8 of SMP) Channel x sample time selection + @"SMP[2]": SAMPLE_TIME, + /// (4/8 of SMP) Channel x sample time selection + @"SMP[3]": SAMPLE_TIME, + /// (5/8 of SMP) Channel x sample time selection + @"SMP[4]": SAMPLE_TIME, + /// (6/8 of SMP) Channel x sample time selection + @"SMP[5]": SAMPLE_TIME, + /// (7/8 of SMP) Channel x sample time selection + @"SMP[6]": SAMPLE_TIME, + /// (8/8 of SMP) Channel x sample time selection + @"SMP[7]": SAMPLE_TIME, + padding: u8, }), /// sample time register 2 SMPR2: mmio.Mmio(packed struct(u32) { - /// Channel 0 sampling time selection - SMP: SAMPLE_TIME, - padding: u29, + /// (1/10 of SMP) Channel 0 sampling time selection + @"SMP[0]": SAMPLE_TIME, + /// (2/10 of SMP) Channel 0 sampling time selection + @"SMP[1]": SAMPLE_TIME, + /// (3/10 of SMP) Channel 0 sampling time selection + @"SMP[2]": SAMPLE_TIME, + /// (4/10 of SMP) Channel 0 sampling time selection + @"SMP[3]": SAMPLE_TIME, + /// (5/10 of SMP) Channel 0 sampling time selection + @"SMP[4]": SAMPLE_TIME, + /// (6/10 of SMP) Channel 0 sampling time selection + @"SMP[5]": SAMPLE_TIME, + /// (7/10 of SMP) Channel 0 sampling time selection + @"SMP[6]": SAMPLE_TIME, + /// (8/10 of SMP) Channel 0 sampling time selection + @"SMP[7]": SAMPLE_TIME, + /// (9/10 of SMP) Channel 0 sampling time selection + @"SMP[8]": SAMPLE_TIME, + /// (10/10 of SMP) Channel 0 sampling time selection + @"SMP[9]": SAMPLE_TIME, + padding: u2, }), /// injected channel data offset register x JOFR: [4]mmio.Mmio(packed struct(u32) { @@ -305368,30 +305400,60 @@ pub const types = struct { }), /// regular sequence register 1 SQR1: mmio.Mmio(packed struct(u32) { - /// 13th to 16th conversion in regular sequence - SQ: u5, - reserved20: u15, + /// (1/4 of SQ) 13th to 16th conversion in regular sequence + @"SQ[0]": u5, + /// (2/4 of SQ) 13th to 16th conversion in regular sequence + @"SQ[1]": u5, + /// (3/4 of SQ) 13th to 16th conversion in regular sequence + @"SQ[2]": u5, + /// (4/4 of SQ) 13th to 16th conversion in regular sequence + @"SQ[3]": u5, /// Regular channel sequence length L: u4, padding: u8, }), /// regular sequence register 2 SQR2: mmio.Mmio(packed struct(u32) { - /// 7th to 12th conversion in regular sequence - SQ: u5, - padding: u27, + /// (1/6 of SQ) 7th to 12th conversion in regular sequence + @"SQ[0]": u5, + /// (2/6 of SQ) 7th to 12th conversion in regular sequence + @"SQ[1]": u5, + /// (3/6 of SQ) 7th to 12th conversion in regular sequence + @"SQ[2]": u5, + /// (4/6 of SQ) 7th to 12th conversion in regular sequence + @"SQ[3]": u5, + /// (5/6 of SQ) 7th to 12th conversion in regular sequence + @"SQ[4]": u5, + /// (6/6 of SQ) 7th to 12th conversion in regular sequence + @"SQ[5]": u5, + padding: u2, }), /// regular sequence register 3 SQR3: mmio.Mmio(packed struct(u32) { - /// 1st to 6th conversion in regular sequence - SQ: u5, - padding: u27, + /// (1/6 of SQ) 1st to 6th conversion in regular sequence + @"SQ[0]": u5, + /// (2/6 of SQ) 1st to 6th conversion in regular sequence + @"SQ[1]": u5, + /// (3/6 of SQ) 1st to 6th conversion in regular sequence + @"SQ[2]": u5, + /// (4/6 of SQ) 1st to 6th conversion in regular sequence + @"SQ[3]": u5, + /// (5/6 of SQ) 1st to 6th conversion in regular sequence + @"SQ[4]": u5, + /// (6/6 of SQ) 1st to 6th conversion in regular sequence + @"SQ[5]": u5, + padding: u2, }), /// injected sequence register JSQR: mmio.Mmio(packed struct(u32) { - /// 1st conversion in injected sequence - JSQ: u5, - reserved20: u15, + /// (1/4 of JSQ) 1st conversion in injected sequence + @"JSQ[0]": u5, + /// (2/4 of JSQ) 1st conversion in injected sequence + @"JSQ[1]": u5, + /// (3/4 of JSQ) 1st conversion in injected sequence + @"JSQ[2]": u5, + /// (4/4 of JSQ) 1st conversion in injected sequence + @"JSQ[3]": u5, /// Injected sequence length JL: u2, padding: u10, @@ -305528,9 +305590,12 @@ pub const types = struct { JEOC: u1, /// Injected channel end of sequence flag JEOS: u1, - /// Analog watchdog flag - AWD: u1, - reserved10: u2, + /// (1/3 of AWD) Analog watchdog flag + @"AWD[0]": u1, + /// (2/3 of AWD) Analog watchdog flag + @"AWD[1]": u1, + /// (3/3 of AWD) Analog watchdog flag + @"AWD[2]": u1, /// Injected context queue overflow JQOVF: u1, padding: u21, @@ -305551,9 +305616,12 @@ pub const types = struct { JEOCIE: u1, /// End of injected sequence of conversions interrupt enable JEOSIE: u1, - /// Analog watchdog X interrupt enable - AWDIE: u1, - reserved10: u2, + /// (1/3 of AWDIE) Analog watchdog X interrupt enable + @"AWDIE[0]": u1, + /// (2/3 of AWDIE) Analog watchdog X interrupt enable + @"AWDIE[1]": u1, + /// (3/3 of AWDIE) Analog watchdog X interrupt enable + @"AWDIE[2]": u1, /// Injected context queue overflow interrupt enable JQOVFIE: u1, padding: u21, @@ -305626,15 +305694,47 @@ pub const types = struct { /// sample time register 1 SMPR1: mmio.Mmio(packed struct(u32) { reserved3: u3, - /// Channel x sampling time selection - SMP: SAMPLE_TIME, - padding: u26, + /// (1/9 of SMP) Channel x sampling time selection + @"SMP[0]": SAMPLE_TIME, + /// (2/9 of SMP) Channel x sampling time selection + @"SMP[1]": SAMPLE_TIME, + /// (3/9 of SMP) Channel x sampling time selection + @"SMP[2]": SAMPLE_TIME, + /// (4/9 of SMP) Channel x sampling time selection + @"SMP[3]": SAMPLE_TIME, + /// (5/9 of SMP) Channel x sampling time selection + @"SMP[4]": SAMPLE_TIME, + /// (6/9 of SMP) Channel x sampling time selection + @"SMP[5]": SAMPLE_TIME, + /// (7/9 of SMP) Channel x sampling time selection + @"SMP[6]": SAMPLE_TIME, + /// (8/9 of SMP) Channel x sampling time selection + @"SMP[7]": SAMPLE_TIME, + /// (9/9 of SMP) Channel x sampling time selection + @"SMP[8]": SAMPLE_TIME, + padding: u2, }), /// sample time register 2 SMPR2: mmio.Mmio(packed struct(u32) { - /// Channel x sampling time selection - SMP: SAMPLE_TIME, - padding: u29, + /// (1/9 of SMP) Channel x sampling time selection + @"SMP[0]": SAMPLE_TIME, + /// (2/9 of SMP) Channel x sampling time selection + @"SMP[1]": SAMPLE_TIME, + /// (3/9 of SMP) Channel x sampling time selection + @"SMP[2]": SAMPLE_TIME, + /// (4/9 of SMP) Channel x sampling time selection + @"SMP[3]": SAMPLE_TIME, + /// (5/9 of SMP) Channel x sampling time selection + @"SMP[4]": SAMPLE_TIME, + /// (6/9 of SMP) Channel x sampling time selection + @"SMP[5]": SAMPLE_TIME, + /// (7/9 of SMP) Channel x sampling time selection + @"SMP[6]": SAMPLE_TIME, + /// (8/9 of SMP) Channel x sampling time selection + @"SMP[7]": SAMPLE_TIME, + /// (9/9 of SMP) Channel x sampling time selection + @"SMP[8]": SAMPLE_TIME, + padding: u5, }), reserved32: [4]u8, /// watchdog threshold register 1 @@ -305670,27 +305770,63 @@ pub const types = struct { /// Regular channel sequence length L: u4, reserved6: u2, - /// X conversion in regular sequence - SQ: u5, - padding: u21, + /// (1/4 of SQ) X conversion in regular sequence + @"SQ[0]": u5, + reserved12: u1, + /// (2/4 of SQ) X conversion in regular sequence + @"SQ[1]": u5, + reserved18: u1, + /// (3/4 of SQ) X conversion in regular sequence + @"SQ[2]": u5, + reserved24: u1, + /// (4/4 of SQ) X conversion in regular sequence + @"SQ[3]": u5, + padding: u3, }), /// regular sequence register 2 SQR2: mmio.Mmio(packed struct(u32) { - /// X conversion in regular sequence - SQ: u5, - padding: u27, + /// (1/5 of SQ) X conversion in regular sequence + @"SQ[0]": u5, + reserved6: u1, + /// (2/5 of SQ) X conversion in regular sequence + @"SQ[1]": u5, + reserved12: u1, + /// (3/5 of SQ) X conversion in regular sequence + @"SQ[2]": u5, + reserved18: u1, + /// (4/5 of SQ) X conversion in regular sequence + @"SQ[3]": u5, + reserved24: u1, + /// (5/5 of SQ) X conversion in regular sequence + @"SQ[4]": u5, + padding: u3, }), /// regular sequence register 3 SQR3: mmio.Mmio(packed struct(u32) { - /// X conversion in regular sequence - SQ: u5, - padding: u27, + /// (1/5 of SQ) X conversion in regular sequence + @"SQ[0]": u5, + reserved6: u1, + /// (2/5 of SQ) X conversion in regular sequence + @"SQ[1]": u5, + reserved12: u1, + /// (3/5 of SQ) X conversion in regular sequence + @"SQ[2]": u5, + reserved18: u1, + /// (4/5 of SQ) X conversion in regular sequence + @"SQ[3]": u5, + reserved24: u1, + /// (5/5 of SQ) X conversion in regular sequence + @"SQ[4]": u5, + padding: u3, }), /// regular sequence register 4 SQR4: mmio.Mmio(packed struct(u32) { - /// X conversion in regular sequence - SQ: u5, - padding: u27, + /// (1/2 of SQ) X conversion in regular sequence + @"SQ[0]": u5, + reserved6: u1, + /// (2/2 of SQ) X conversion in regular sequence + @"SQ[1]": u5, + padding: u21, }), /// regular Data Register DR: mmio.Mmio(packed struct(u32) { @@ -305707,9 +305843,18 @@ pub const types = struct { JEXTSEL: u4, /// External Trigger Enable and Polarity Selection for injected channels JEXTEN: JEXTEN, - /// X conversion in the injected sequence - JSQ: u5, - padding: u19, + /// (1/4 of JSQ) X conversion in the injected sequence + @"JSQ[0]": u5, + reserved14: u1, + /// (2/4 of JSQ) X conversion in the injected sequence + @"JSQ[1]": u5, + reserved20: u1, + /// (3/4 of JSQ) X conversion in the injected sequence + @"JSQ[2]": u5, + reserved26: u1, + /// (4/4 of JSQ) X conversion in the injected sequence + @"JSQ[3]": u5, + padding: u1, }), reserved96: [16]u8, /// offset register X @@ -305733,9 +305878,41 @@ pub const types = struct { /// Analog Watchdog X Configuration Register AWDCR: [2]mmio.Mmio(packed struct(u32) { reserved1: u1, - /// AWD2CH - AWD2CH0: u1, - padding: u30, + /// (1/17 of AWD2CH0) AWD2CH + @"AWD2CH0[0]": u1, + /// (2/17 of AWD2CH0) AWD2CH + @"AWD2CH0[1]": u1, + /// (3/17 of AWD2CH0) AWD2CH + @"AWD2CH0[2]": u1, + /// (4/17 of AWD2CH0) AWD2CH + @"AWD2CH0[3]": u1, + /// (5/17 of AWD2CH0) AWD2CH + @"AWD2CH0[4]": u1, + /// (6/17 of AWD2CH0) AWD2CH + @"AWD2CH0[5]": u1, + /// (7/17 of AWD2CH0) AWD2CH + @"AWD2CH0[6]": u1, + /// (8/17 of AWD2CH0) AWD2CH + @"AWD2CH0[7]": u1, + /// (9/17 of AWD2CH0) AWD2CH + @"AWD2CH0[8]": u1, + /// (10/17 of AWD2CH0) AWD2CH + @"AWD2CH0[9]": u1, + /// (11/17 of AWD2CH0) AWD2CH + @"AWD2CH0[10]": u1, + /// (12/17 of AWD2CH0) AWD2CH + @"AWD2CH0[11]": u1, + /// (13/17 of AWD2CH0) AWD2CH + @"AWD2CH0[12]": u1, + /// (14/17 of AWD2CH0) AWD2CH + @"AWD2CH0[13]": u1, + /// (15/17 of AWD2CH0) AWD2CH + @"AWD2CH0[14]": u1, + /// (16/17 of AWD2CH0) AWD2CH + @"AWD2CH0[15]": u1, + /// (17/17 of AWD2CH0) AWD2CH + @"AWD2CH0[16]": u1, + padding: u14, }), reserved176: [8]u8, /// Differential Mode Selection Register 2 @@ -306034,21 +306211,75 @@ pub const types = struct { }), /// sample time register 1 SMPR1: mmio.Mmio(packed struct(u32) { - /// channel 20-29 sampling time selection - SMP: SAMPLE_TIME, - padding: u29, + /// (1/10 of SMP) channel 20-29 sampling time selection + @"SMP[0]": SAMPLE_TIME, + /// (2/10 of SMP) channel 20-29 sampling time selection + @"SMP[1]": SAMPLE_TIME, + /// (3/10 of SMP) channel 20-29 sampling time selection + @"SMP[2]": SAMPLE_TIME, + /// (4/10 of SMP) channel 20-29 sampling time selection + @"SMP[3]": SAMPLE_TIME, + /// (5/10 of SMP) channel 20-29 sampling time selection + @"SMP[4]": SAMPLE_TIME, + /// (6/10 of SMP) channel 20-29 sampling time selection + @"SMP[5]": SAMPLE_TIME, + /// (7/10 of SMP) channel 20-29 sampling time selection + @"SMP[6]": SAMPLE_TIME, + /// (8/10 of SMP) channel 20-29 sampling time selection + @"SMP[7]": SAMPLE_TIME, + /// (9/10 of SMP) channel 20-29 sampling time selection + @"SMP[8]": SAMPLE_TIME, + /// (10/10 of SMP) channel 20-29 sampling time selection + @"SMP[9]": SAMPLE_TIME, + padding: u2, }), /// sample time register 2 SMPR2: mmio.Mmio(packed struct(u32) { - /// channel 10-19 sampling time selection - SMP: SAMPLE_TIME, - padding: u29, + /// (1/10 of SMP) channel 10-19 sampling time selection + @"SMP[0]": SAMPLE_TIME, + /// (2/10 of SMP) channel 10-19 sampling time selection + @"SMP[1]": SAMPLE_TIME, + /// (3/10 of SMP) channel 10-19 sampling time selection + @"SMP[2]": SAMPLE_TIME, + /// (4/10 of SMP) channel 10-19 sampling time selection + @"SMP[3]": SAMPLE_TIME, + /// (5/10 of SMP) channel 10-19 sampling time selection + @"SMP[4]": SAMPLE_TIME, + /// (6/10 of SMP) channel 10-19 sampling time selection + @"SMP[5]": SAMPLE_TIME, + /// (7/10 of SMP) channel 10-19 sampling time selection + @"SMP[6]": SAMPLE_TIME, + /// (8/10 of SMP) channel 10-19 sampling time selection + @"SMP[7]": SAMPLE_TIME, + /// (9/10 of SMP) channel 10-19 sampling time selection + @"SMP[8]": SAMPLE_TIME, + /// (10/10 of SMP) channel 10-19 sampling time selection + @"SMP[9]": SAMPLE_TIME, + padding: u2, }), /// sample time register 3 SMPR3: mmio.Mmio(packed struct(u32) { - /// channel 0-9 sampling time selection - SMP: SAMPLE_TIME, - padding: u29, + /// (1/10 of SMP) channel 0-9 sampling time selection + @"SMP[0]": SAMPLE_TIME, + /// (2/10 of SMP) channel 0-9 sampling time selection + @"SMP[1]": SAMPLE_TIME, + /// (3/10 of SMP) channel 0-9 sampling time selection + @"SMP[2]": SAMPLE_TIME, + /// (4/10 of SMP) channel 0-9 sampling time selection + @"SMP[3]": SAMPLE_TIME, + /// (5/10 of SMP) channel 0-9 sampling time selection + @"SMP[4]": SAMPLE_TIME, + /// (6/10 of SMP) channel 0-9 sampling time selection + @"SMP[5]": SAMPLE_TIME, + /// (7/10 of SMP) channel 0-9 sampling time selection + @"SMP[6]": SAMPLE_TIME, + /// (8/10 of SMP) channel 0-9 sampling time selection + @"SMP[7]": SAMPLE_TIME, + /// (9/10 of SMP) channel 0-9 sampling time selection + @"SMP[8]": SAMPLE_TIME, + /// (10/10 of SMP) channel 0-9 sampling time selection + @"SMP[9]": SAMPLE_TIME, + padding: u2, }), /// injected channel data offset register 1 JOFR1: mmio.Mmio(packed struct(u32) { @@ -306088,36 +306319,81 @@ pub const types = struct { }), /// regular sequence register 1 SQR1: mmio.Mmio(packed struct(u32) { - /// 25th-29th conversion in regular sequence - SQ: u5, - reserved20: u15, + /// (1/4 of SQ) 25th-29th conversion in regular sequence + @"SQ[0]": u5, + /// (2/4 of SQ) 25th-29th conversion in regular sequence + @"SQ[1]": u5, + /// (3/4 of SQ) 25th-29th conversion in regular sequence + @"SQ[2]": u5, + /// (4/4 of SQ) 25th-29th conversion in regular sequence + @"SQ[3]": u5, /// Regular channel sequence length L: u4, padding: u8, }), /// regular sequence register 2 SQR2: mmio.Mmio(packed struct(u32) { - /// 19th-24th conversion in regular sequence - SQ: u5, - padding: u27, + /// (1/6 of SQ) 19th-24th conversion in regular sequence + @"SQ[0]": u5, + /// (2/6 of SQ) 19th-24th conversion in regular sequence + @"SQ[1]": u5, + /// (3/6 of SQ) 19th-24th conversion in regular sequence + @"SQ[2]": u5, + /// (4/6 of SQ) 19th-24th conversion in regular sequence + @"SQ[3]": u5, + /// (5/6 of SQ) 19th-24th conversion in regular sequence + @"SQ[4]": u5, + /// (6/6 of SQ) 19th-24th conversion in regular sequence + @"SQ[5]": u5, + padding: u2, }), /// regular sequence register 3 SQR3: mmio.Mmio(packed struct(u32) { - /// 13th-18th conversion in regular sequence - SQ: u5, - padding: u27, + /// (1/6 of SQ) 13th-18th conversion in regular sequence + @"SQ[0]": u5, + /// (2/6 of SQ) 13th-18th conversion in regular sequence + @"SQ[1]": u5, + /// (3/6 of SQ) 13th-18th conversion in regular sequence + @"SQ[2]": u5, + /// (4/6 of SQ) 13th-18th conversion in regular sequence + @"SQ[3]": u5, + /// (5/6 of SQ) 13th-18th conversion in regular sequence + @"SQ[4]": u5, + /// (6/6 of SQ) 13th-18th conversion in regular sequence + @"SQ[5]": u5, + padding: u2, }), /// regular sequence register 4 SQR4: mmio.Mmio(packed struct(u32) { - /// 7th-12th conversion in regular sequence - SQ: u5, - padding: u27, + /// (1/6 of SQ) 7th-12th conversion in regular sequence + @"SQ[0]": u5, + /// (2/6 of SQ) 7th-12th conversion in regular sequence + @"SQ[1]": u5, + /// (3/6 of SQ) 7th-12th conversion in regular sequence + @"SQ[2]": u5, + /// (4/6 of SQ) 7th-12th conversion in regular sequence + @"SQ[3]": u5, + /// (5/6 of SQ) 7th-12th conversion in regular sequence + @"SQ[4]": u5, + /// (6/6 of SQ) 7th-12th conversion in regular sequence + @"SQ[5]": u5, + padding: u2, }), /// regular sequence register 5 SQR5: mmio.Mmio(packed struct(u32) { - /// 1st-6th conversion in regular sequence - SQ: u5, - padding: u27, + /// (1/6 of SQ) 1st-6th conversion in regular sequence + @"SQ[0]": u5, + /// (2/6 of SQ) 1st-6th conversion in regular sequence + @"SQ[1]": u5, + /// (3/6 of SQ) 1st-6th conversion in regular sequence + @"SQ[2]": u5, + /// (4/6 of SQ) 1st-6th conversion in regular sequence + @"SQ[3]": u5, + /// (5/6 of SQ) 1st-6th conversion in regular sequence + @"SQ[4]": u5, + /// (6/6 of SQ) 1st-6th conversion in regular sequence + @"SQ[5]": u5, + padding: u2, }), /// injected sequence register JSQR: mmio.Mmio(packed struct(u32) { @@ -306165,9 +306441,11 @@ pub const types = struct { }), /// sample time register 0 SMPR0: mmio.Mmio(packed struct(u32) { - /// channel 30-31 sampling time selection - SMP: SAMPLE_TIME, - padding: u29, + /// (1/2 of SMP) channel 30-31 sampling time selection + @"SMP[0]": SAMPLE_TIME, + /// (2/2 of SMP) channel 30-31 sampling time selection + @"SMP[1]": SAMPLE_TIME, + padding: u26, }), reserved768: [672]u8, /// ADC common status register @@ -306671,9 +306949,45 @@ pub const types = struct { /// Sampling time selection SMP2: SAMPLE_TIME, reserved8: u1, - /// Channel sampling time selection - SMPSEL: u1, - padding: u23, + /// (1/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[0]": u1, + /// (2/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[1]": u1, + /// (3/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[2]": u1, + /// (4/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[3]": u1, + /// (5/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[4]": u1, + /// (6/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[5]": u1, + /// (7/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[6]": u1, + /// (8/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[7]": u1, + /// (9/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[8]": u1, + /// (10/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[9]": u1, + /// (11/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[10]": u1, + /// (12/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[11]": u1, + /// (13/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[12]": u1, + /// (14/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[13]": u1, + /// (15/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[14]": u1, + /// (16/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[15]": u1, + /// (17/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[16]": u1, + /// (18/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[17]": u1, + /// (19/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[18]": u1, + padding: u5, }), reserved32: [8]u8, /// watchdog threshold register @@ -307140,17 +307454,51 @@ pub const types = struct { }), /// sampling time register 1 SMPR: mmio.Mmio(packed struct(u32) { - /// channel n * 10 + x sampling time - SMP: SAMPLE_TIME, - reserved31: u28, + /// (1/10 of SMP) channel n * 10 + x sampling time + @"SMP[0]": SAMPLE_TIME, + /// (2/10 of SMP) channel n * 10 + x sampling time + @"SMP[1]": SAMPLE_TIME, + /// (3/10 of SMP) channel n * 10 + x sampling time + @"SMP[2]": SAMPLE_TIME, + /// (4/10 of SMP) channel n * 10 + x sampling time + @"SMP[3]": SAMPLE_TIME, + /// (5/10 of SMP) channel n * 10 + x sampling time + @"SMP[4]": SAMPLE_TIME, + /// (6/10 of SMP) channel n * 10 + x sampling time + @"SMP[5]": SAMPLE_TIME, + /// (7/10 of SMP) channel n * 10 + x sampling time + @"SMP[6]": SAMPLE_TIME, + /// (8/10 of SMP) channel n * 10 + x sampling time + @"SMP[7]": SAMPLE_TIME, + /// (9/10 of SMP) channel n * 10 + x sampling time + @"SMP[8]": SAMPLE_TIME, + /// (10/10 of SMP) channel n * 10 + x sampling time + @"SMP[9]": SAMPLE_TIME, + reserved31: u1, /// Addition of one clock cycle to the sampling time SMPPLUS: u1, }), /// sampling time register 2 SMPR2: mmio.Mmio(packed struct(u32) { - /// channel n * 10 + x sampling time - SMP: SAMPLE_TIME, - padding: u29, + /// (1/9 of SMP) channel n * 10 + x sampling time + @"SMP[0]": SAMPLE_TIME, + /// (2/9 of SMP) channel n * 10 + x sampling time + @"SMP[1]": SAMPLE_TIME, + /// (3/9 of SMP) channel n * 10 + x sampling time + @"SMP[2]": SAMPLE_TIME, + /// (4/9 of SMP) channel n * 10 + x sampling time + @"SMP[3]": SAMPLE_TIME, + /// (5/9 of SMP) channel n * 10 + x sampling time + @"SMP[4]": SAMPLE_TIME, + /// (6/9 of SMP) channel n * 10 + x sampling time + @"SMP[5]": SAMPLE_TIME, + /// (7/9 of SMP) channel n * 10 + x sampling time + @"SMP[6]": SAMPLE_TIME, + /// (8/9 of SMP) channel n * 10 + x sampling time + @"SMP[7]": SAMPLE_TIME, + /// (9/9 of SMP) channel n * 10 + x sampling time + @"SMP[8]": SAMPLE_TIME, + padding: u5, }), reserved32: [4]u8, /// analog watchdog threshold register 1 @@ -307188,27 +307536,63 @@ pub const types = struct { /// L L: u4, reserved6: u2, - /// group regular sequencer rank 1-4 - SQ: u5, - padding: u21, + /// (1/4 of SQ) group regular sequencer rank 1-4 + @"SQ[0]": u5, + reserved12: u1, + /// (2/4 of SQ) group regular sequencer rank 1-4 + @"SQ[1]": u5, + reserved18: u1, + /// (3/4 of SQ) group regular sequencer rank 1-4 + @"SQ[2]": u5, + reserved24: u1, + /// (4/4 of SQ) group regular sequencer rank 1-4 + @"SQ[3]": u5, + padding: u3, }), /// group regular sequencer ranks register 2 SQR2: mmio.Mmio(packed struct(u32) { - /// group regular sequencer rank 5-9 - SQ: u5, - padding: u27, + /// (1/5 of SQ) group regular sequencer rank 5-9 + @"SQ[0]": u5, + reserved6: u1, + /// (2/5 of SQ) group regular sequencer rank 5-9 + @"SQ[1]": u5, + reserved12: u1, + /// (3/5 of SQ) group regular sequencer rank 5-9 + @"SQ[2]": u5, + reserved18: u1, + /// (4/5 of SQ) group regular sequencer rank 5-9 + @"SQ[3]": u5, + reserved24: u1, + /// (5/5 of SQ) group regular sequencer rank 5-9 + @"SQ[4]": u5, + padding: u3, }), /// group regular sequencer ranks register 3 SQR3: mmio.Mmio(packed struct(u32) { - /// group regular sequencer rank 10-14 - SQ: u5, - padding: u27, + /// (1/5 of SQ) group regular sequencer rank 10-14 + @"SQ[0]": u5, + reserved6: u1, + /// (2/5 of SQ) group regular sequencer rank 10-14 + @"SQ[1]": u5, + reserved12: u1, + /// (3/5 of SQ) group regular sequencer rank 10-14 + @"SQ[2]": u5, + reserved18: u1, + /// (4/5 of SQ) group regular sequencer rank 10-14 + @"SQ[3]": u5, + reserved24: u1, + /// (5/5 of SQ) group regular sequencer rank 10-14 + @"SQ[4]": u5, + padding: u3, }), /// group regular sequencer ranks register 4 SQR4: mmio.Mmio(packed struct(u32) { - /// group regular sequencer rank 15-16 - SQ: u5, - padding: u27, + /// (1/2 of SQ) group regular sequencer rank 15-16 + @"SQ[0]": u5, + reserved6: u1, + /// (2/2 of SQ) group regular sequencer rank 15-16 + @"SQ[1]": u5, + padding: u21, }), /// group regular conversion data register DR: mmio.Mmio(packed struct(u32) { @@ -307225,9 +307609,17 @@ pub const types = struct { JEXTSEL: u5, /// group injected external trigger polarity JEXTEN: JEXTEN, - /// group injected sequencer rank 1-4 - JSQ: u5, - padding: u18, + /// (1/4 of JSQ) group injected sequencer rank 1-4 + @"JSQ[0]": u5, + reserved15: u1, + /// (2/4 of JSQ) group injected sequencer rank 1-4 + @"JSQ[1]": u5, + reserved21: u1, + /// (3/4 of JSQ) group injected sequencer rank 1-4 + @"JSQ[2]": u5, + reserved27: u1, + /// (4/4 of JSQ) group injected sequencer rank 1-4 + @"JSQ[3]": u5, }), reserved96: [16]u8, /// offset number 1-4 register @@ -307267,9 +307659,43 @@ pub const types = struct { reserved176: [8]u8, /// channel differential or single-ended mode selection register DIFSEL: mmio.Mmio(packed struct(u32) { - /// channel differential or single-ended mode for channel - DIFSEL: DIFSEL, - padding: u31, + /// (1/18 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[0]": DIFSEL, + /// (2/18 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[1]": DIFSEL, + /// (3/18 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[2]": DIFSEL, + /// (4/18 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[3]": DIFSEL, + /// (5/18 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[4]": DIFSEL, + /// (6/18 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[5]": DIFSEL, + /// (7/18 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[6]": DIFSEL, + /// (8/18 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[7]": DIFSEL, + /// (9/18 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[8]": DIFSEL, + /// (10/18 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[9]": DIFSEL, + /// (11/18 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[10]": DIFSEL, + /// (12/18 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[11]": DIFSEL, + /// (13/18 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[12]": DIFSEL, + /// (14/18 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[13]": DIFSEL, + /// (15/18 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[14]": DIFSEL, + /// (16/18 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[15]": DIFSEL, + /// (17/18 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[16]": DIFSEL, + /// (18/18 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[17]": DIFSEL, + padding: u14, }), /// calibration factors register CALFACT: mmio.Mmio(packed struct(u32) { @@ -307438,9 +307864,12 @@ pub const types = struct { JEOC: u1, /// Injected channel end of sequence flag This bit is set by hardware at the end of the conversions of all injected channels in the group. It is cleared by software writing 1 to it JEOS: u1, - /// Analog watchdog 1-3 flags. Set by hardware when the converted voltage crosses the values programmed in the corresponding fields LT and HT fields of the relevant TR register. It is cleared by software. - AWD: u1, - reserved10: u2, + /// (1/3 of AWD) Analog watchdog 1-3 flags. Set by hardware when the converted voltage crosses the values programmed in the corresponding fields LT and HT fields of the relevant TR register. It is cleared by software. + @"AWD[0]": u1, + /// (2/3 of AWD) Analog watchdog 1-3 flags. Set by hardware when the converted voltage crosses the values programmed in the corresponding fields LT and HT fields of the relevant TR register. It is cleared by software. + @"AWD[1]": u1, + /// (3/3 of AWD) Analog watchdog 1-3 flags. Set by hardware when the converted voltage crosses the values programmed in the corresponding fields LT and HT fields of the relevant TR register. It is cleared by software. + @"AWD[2]": u1, /// Injected context queue overflow This bit is set by hardware when an Overflow of the Injected Queue of Context occurs. It is cleared by software writing 1 to it. Refer to for more information JQOVF: u1, padding: u21, @@ -307461,9 +307890,12 @@ pub const types = struct { JEOCIE: u1, /// End of injected sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of injected sequence of conversions interrupt. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). JEOSIE: u1, - /// Analog watchdog 1-3 interrupt enable. This bit is set and cleared by software to enable/disable the analog watchdog 1-3 interrupts. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). - AWDIE: u1, - reserved10: u2, + /// (1/3 of AWDIE) Analog watchdog 1-3 interrupt enable. This bit is set and cleared by software to enable/disable the analog watchdog 1-3 interrupts. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + @"AWDIE[0]": u1, + /// (2/3 of AWDIE) Analog watchdog 1-3 interrupt enable. This bit is set and cleared by software to enable/disable the analog watchdog 1-3 interrupts. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + @"AWDIE[1]": u1, + /// (3/3 of AWDIE) Analog watchdog 1-3 interrupt enable. This bit is set and cleared by software to enable/disable the analog watchdog 1-3 interrupts. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + @"AWDIE[2]": u1, /// Injected context queue overflow interrupt enable This bit is set and cleared by software to enable/disable the Injected Context Queue Overflow interrupt. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). JQOVFIE: u1, padding: u21, @@ -307501,9 +307933,16 @@ pub const types = struct { reserved3: u1, /// Data resolution These bits are written by software to select the resolution of the conversion. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). RES: RES, - /// External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - EXTSEL: u1, - reserved10: u4, + /// (1/5 of EXTSEL) External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + @"EXTSEL[0]": u1, + /// (2/5 of EXTSEL) External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + @"EXTSEL[1]": u1, + /// (3/5 of EXTSEL) External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + @"EXTSEL[2]": u1, + /// (4/5 of EXTSEL) External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + @"EXTSEL[3]": u1, + /// (5/5 of EXTSEL) External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + @"EXTSEL[4]": u1, /// External trigger enable and polarity selection for regular channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of a regular group. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). EXTEN: EXTEN, /// Overrun mode This bit is set and cleared by software and configure the way data overrun is managed. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). @@ -307560,17 +307999,53 @@ pub const types = struct { }), /// sample time register 1 SMPR1: mmio.Mmio(packed struct(u32) { - /// Channel 0-9 sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. - SMP: SAMPLE_TIME, - reserved31: u28, + /// (1/10 of SMP) Channel 0-9 sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + @"SMP[0]": SAMPLE_TIME, + /// (2/10 of SMP) Channel 0-9 sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + @"SMP[1]": SAMPLE_TIME, + /// (3/10 of SMP) Channel 0-9 sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + @"SMP[2]": SAMPLE_TIME, + /// (4/10 of SMP) Channel 0-9 sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + @"SMP[3]": SAMPLE_TIME, + /// (5/10 of SMP) Channel 0-9 sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + @"SMP[4]": SAMPLE_TIME, + /// (6/10 of SMP) Channel 0-9 sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + @"SMP[5]": SAMPLE_TIME, + /// (7/10 of SMP) Channel 0-9 sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + @"SMP[6]": SAMPLE_TIME, + /// (8/10 of SMP) Channel 0-9 sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + @"SMP[7]": SAMPLE_TIME, + /// (9/10 of SMP) Channel 0-9 sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + @"SMP[8]": SAMPLE_TIME, + /// (10/10 of SMP) Channel 0-9 sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + @"SMP[9]": SAMPLE_TIME, + reserved31: u1, /// Addition of one clock cycle to the sampling time. To make sure no conversion is ongoing, the software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 SMPPLUS: SMPPLUS, }), /// sample time register 2 SMPR2: mmio.Mmio(packed struct(u32) { - /// Channel 10-19 sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. - SMP: SAMPLE_TIME, - padding: u29, + /// (1/10 of SMP) Channel 10-19 sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + @"SMP[0]": SAMPLE_TIME, + /// (2/10 of SMP) Channel 10-19 sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + @"SMP[1]": SAMPLE_TIME, + /// (3/10 of SMP) Channel 10-19 sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + @"SMP[2]": SAMPLE_TIME, + /// (4/10 of SMP) Channel 10-19 sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + @"SMP[3]": SAMPLE_TIME, + /// (5/10 of SMP) Channel 10-19 sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + @"SMP[4]": SAMPLE_TIME, + /// (6/10 of SMP) Channel 10-19 sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + @"SMP[5]": SAMPLE_TIME, + /// (7/10 of SMP) Channel 10-19 sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + @"SMP[6]": SAMPLE_TIME, + /// (8/10 of SMP) Channel 10-19 sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + @"SMP[7]": SAMPLE_TIME, + /// (9/10 of SMP) Channel 10-19 sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + @"SMP[8]": SAMPLE_TIME, + /// (10/10 of SMP) Channel 10-19 sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + @"SMP[9]": SAMPLE_TIME, + padding: u2, }), reserved32: [4]u8, /// watchdog threshold register 1 @@ -307608,27 +308083,63 @@ pub const types = struct { /// Regular channel sequence length These bits are written by software to define the total number of conversions in the regular channel conversion sequence. ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). L: u4, reserved6: u2, - /// 1st-4th conversions in regular sequence These bits are written by software with the channel number (0 to 19) assigned as the 1st-4th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - SQ: u5, - padding: u21, + /// (1/4 of SQ) 1st-4th conversions in regular sequence These bits are written by software with the channel number (0 to 19) assigned as the 1st-4th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + @"SQ[0]": u5, + reserved12: u1, + /// (2/4 of SQ) 1st-4th conversions in regular sequence These bits are written by software with the channel number (0 to 19) assigned as the 1st-4th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + @"SQ[1]": u5, + reserved18: u1, + /// (3/4 of SQ) 1st-4th conversions in regular sequence These bits are written by software with the channel number (0 to 19) assigned as the 1st-4th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + @"SQ[2]": u5, + reserved24: u1, + /// (4/4 of SQ) 1st-4th conversions in regular sequence These bits are written by software with the channel number (0 to 19) assigned as the 1st-4th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + @"SQ[3]": u5, + padding: u3, }), /// regular sequence register 2 SQR2: mmio.Mmio(packed struct(u32) { - /// 5th-9th conversions in regular sequence These bits are written by software with the channel number (0 to 19) assigned as the 5th-9th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - SQ: u5, - padding: u27, + /// (1/5 of SQ) 5th-9th conversions in regular sequence These bits are written by software with the channel number (0 to 19) assigned as the 5th-9th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + @"SQ[0]": u5, + reserved6: u1, + /// (2/5 of SQ) 5th-9th conversions in regular sequence These bits are written by software with the channel number (0 to 19) assigned as the 5th-9th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + @"SQ[1]": u5, + reserved12: u1, + /// (3/5 of SQ) 5th-9th conversions in regular sequence These bits are written by software with the channel number (0 to 19) assigned as the 5th-9th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + @"SQ[2]": u5, + reserved18: u1, + /// (4/5 of SQ) 5th-9th conversions in regular sequence These bits are written by software with the channel number (0 to 19) assigned as the 5th-9th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + @"SQ[3]": u5, + reserved24: u1, + /// (5/5 of SQ) 5th-9th conversions in regular sequence These bits are written by software with the channel number (0 to 19) assigned as the 5th-9th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + @"SQ[4]": u5, + padding: u3, }), /// regular sequence register 3 SQR3: mmio.Mmio(packed struct(u32) { - /// 10th-14th conversions in regular sequence These bits are written by software with the channel number (0 to 19) assigned as the 10th-14th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - SQ: u5, - padding: u27, + /// (1/5 of SQ) 10th-14th conversions in regular sequence These bits are written by software with the channel number (0 to 19) assigned as the 10th-14th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + @"SQ[0]": u5, + reserved6: u1, + /// (2/5 of SQ) 10th-14th conversions in regular sequence These bits are written by software with the channel number (0 to 19) assigned as the 10th-14th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + @"SQ[1]": u5, + reserved12: u1, + /// (3/5 of SQ) 10th-14th conversions in regular sequence These bits are written by software with the channel number (0 to 19) assigned as the 10th-14th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + @"SQ[2]": u5, + reserved18: u1, + /// (4/5 of SQ) 10th-14th conversions in regular sequence These bits are written by software with the channel number (0 to 19) assigned as the 10th-14th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + @"SQ[3]": u5, + reserved24: u1, + /// (5/5 of SQ) 10th-14th conversions in regular sequence These bits are written by software with the channel number (0 to 19) assigned as the 10th-14th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + @"SQ[4]": u5, + padding: u3, }), /// regular sequence register 4 SQR4: mmio.Mmio(packed struct(u32) { - /// 15th-16th conversions in regular sequence These bits are written by software with the channel number (0 to 19) assigned as the 15th-16th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - SQ: u5, - padding: u27, + /// (1/2 of SQ) 15th-16th conversions in regular sequence These bits are written by software with the channel number (0 to 19) assigned as the 15th-16th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + @"SQ[0]": u5, + reserved6: u1, + /// (2/2 of SQ) 15th-16th conversions in regular sequence These bits are written by software with the channel number (0 to 19) assigned as the 15th-16th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + @"SQ[1]": u5, + padding: u21, }), /// regular data register DR: mmio.Mmio(packed struct(u32) { @@ -307645,9 +308156,17 @@ pub const types = struct { JEXTSEL: u5, /// External trigger enable and polarity selection for injected channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). If JQM = 1 and if the Queue of Context becomes empty, the software and hardware triggers of the injected sequence are both internally disabled (refer to Queue of context for injected conversions). JEXTEN: EXTEN, - /// 1st-4th conversions in the injected sequence These bits are written by software with the channel number (0 to 19) assigned as the 1st-4th in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). - JSQ: u5, - padding: u18, + /// (1/4 of JSQ) 1st-4th conversions in the injected sequence These bits are written by software with the channel number (0 to 19) assigned as the 1st-4th in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). + @"JSQ[0]": u5, + reserved15: u1, + /// (2/4 of JSQ) 1st-4th conversions in the injected sequence These bits are written by software with the channel number (0 to 19) assigned as the 1st-4th in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). + @"JSQ[1]": u5, + reserved21: u1, + /// (3/4 of JSQ) 1st-4th conversions in the injected sequence These bits are written by software with the channel number (0 to 19) assigned as the 1st-4th in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). + @"JSQ[2]": u5, + reserved27: u1, + /// (4/4 of JSQ) 1st-4th conversions in the injected sequence These bits are written by software with the channel number (0 to 19) assigned as the 1st-4th in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). + @"JSQ[3]": u5, }), reserved96: [16]u8, /// offset 1-4 register @@ -307959,9 +308478,45 @@ pub const types = struct { reserved40: [4]u8, /// channel selection register CHSELR: mmio.Mmio(packed struct(u32) { - /// Channel-x selection - @"CHSEL x": u1, - padding: u31, + /// (1/19 of CHSEL x) Channel-x selection + @"CHSEL x[0]": u1, + /// (2/19 of CHSEL x) Channel-x selection + @"CHSEL x[1]": u1, + /// (3/19 of CHSEL x) Channel-x selection + @"CHSEL x[2]": u1, + /// (4/19 of CHSEL x) Channel-x selection + @"CHSEL x[3]": u1, + /// (5/19 of CHSEL x) Channel-x selection + @"CHSEL x[4]": u1, + /// (6/19 of CHSEL x) Channel-x selection + @"CHSEL x[5]": u1, + /// (7/19 of CHSEL x) Channel-x selection + @"CHSEL x[6]": u1, + /// (8/19 of CHSEL x) Channel-x selection + @"CHSEL x[7]": u1, + /// (9/19 of CHSEL x) Channel-x selection + @"CHSEL x[8]": u1, + /// (10/19 of CHSEL x) Channel-x selection + @"CHSEL x[9]": u1, + /// (11/19 of CHSEL x) Channel-x selection + @"CHSEL x[10]": u1, + /// (12/19 of CHSEL x) Channel-x selection + @"CHSEL x[11]": u1, + /// (13/19 of CHSEL x) Channel-x selection + @"CHSEL x[12]": u1, + /// (14/19 of CHSEL x) Channel-x selection + @"CHSEL x[13]": u1, + /// (15/19 of CHSEL x) Channel-x selection + @"CHSEL x[14]": u1, + /// (16/19 of CHSEL x) Channel-x selection + @"CHSEL x[15]": u1, + /// (17/19 of CHSEL x) Channel-x selection + @"CHSEL x[16]": u1, + /// (18/19 of CHSEL x) Channel-x selection + @"CHSEL x[17]": u1, + /// (19/19 of CHSEL x) Channel-x selection + @"CHSEL x[18]": u1, + padding: u13, }), reserved64: [20]u8, /// data register @@ -308171,9 +308726,45 @@ pub const types = struct { /// Sampling time selection SMP2: SAMPLE_TIME, reserved8: u1, - /// Channel sampling time selection - SMPSEL: u1, - padding: u23, + /// (1/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[0]": u1, + /// (2/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[1]": u1, + /// (3/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[2]": u1, + /// (4/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[3]": u1, + /// (5/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[4]": u1, + /// (6/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[5]": u1, + /// (7/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[6]": u1, + /// (8/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[7]": u1, + /// (9/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[8]": u1, + /// (10/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[9]": u1, + /// (11/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[10]": u1, + /// (12/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[11]": u1, + /// (13/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[12]": u1, + /// (14/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[13]": u1, + /// (15/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[14]": u1, + /// (16/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[15]": u1, + /// (17/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[16]": u1, + /// (18/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[17]": u1, + /// (19/19 of SMPSEL) Channel sampling time selection + @"SMPSEL[18]": u1, + padding: u5, }), reserved32: [8]u8, /// watchdog threshold register @@ -308826,9 +309417,45 @@ pub const types = struct { reserved40: [4]u8, /// channel selection register CHSELR: mmio.Mmio(packed struct(u32) { - /// Channel-x selection - @"CHSEL x": u1, - padding: u31, + /// (1/19 of CHSEL x) Channel-x selection + @"CHSEL x[0]": u1, + /// (2/19 of CHSEL x) Channel-x selection + @"CHSEL x[1]": u1, + /// (3/19 of CHSEL x) Channel-x selection + @"CHSEL x[2]": u1, + /// (4/19 of CHSEL x) Channel-x selection + @"CHSEL x[3]": u1, + /// (5/19 of CHSEL x) Channel-x selection + @"CHSEL x[4]": u1, + /// (6/19 of CHSEL x) Channel-x selection + @"CHSEL x[5]": u1, + /// (7/19 of CHSEL x) Channel-x selection + @"CHSEL x[6]": u1, + /// (8/19 of CHSEL x) Channel-x selection + @"CHSEL x[7]": u1, + /// (9/19 of CHSEL x) Channel-x selection + @"CHSEL x[8]": u1, + /// (10/19 of CHSEL x) Channel-x selection + @"CHSEL x[9]": u1, + /// (11/19 of CHSEL x) Channel-x selection + @"CHSEL x[10]": u1, + /// (12/19 of CHSEL x) Channel-x selection + @"CHSEL x[11]": u1, + /// (13/19 of CHSEL x) Channel-x selection + @"CHSEL x[12]": u1, + /// (14/19 of CHSEL x) Channel-x selection + @"CHSEL x[13]": u1, + /// (15/19 of CHSEL x) Channel-x selection + @"CHSEL x[14]": u1, + /// (16/19 of CHSEL x) Channel-x selection + @"CHSEL x[15]": u1, + /// (17/19 of CHSEL x) Channel-x selection + @"CHSEL x[16]": u1, + /// (18/19 of CHSEL x) Channel-x selection + @"CHSEL x[17]": u1, + /// (19/19 of CHSEL x) Channel-x selection + @"CHSEL x[18]": u1, + padding: u13, }), reserved64: [20]u8, /// data register @@ -309037,15 +309664,49 @@ pub const types = struct { }), /// sample time register 1 SMPR1: mmio.Mmio(packed struct(u32) { - /// Channel 10 sampling time selection - SMP: SAMPLE_TIME, - padding: u29, + /// (1/9 of SMP) Channel 10 sampling time selection + @"SMP[0]": SAMPLE_TIME, + /// (2/9 of SMP) Channel 10 sampling time selection + @"SMP[1]": SAMPLE_TIME, + /// (3/9 of SMP) Channel 10 sampling time selection + @"SMP[2]": SAMPLE_TIME, + /// (4/9 of SMP) Channel 10 sampling time selection + @"SMP[3]": SAMPLE_TIME, + /// (5/9 of SMP) Channel 10 sampling time selection + @"SMP[4]": SAMPLE_TIME, + /// (6/9 of SMP) Channel 10 sampling time selection + @"SMP[5]": SAMPLE_TIME, + /// (7/9 of SMP) Channel 10 sampling time selection + @"SMP[6]": SAMPLE_TIME, + /// (8/9 of SMP) Channel 10 sampling time selection + @"SMP[7]": SAMPLE_TIME, + /// (9/9 of SMP) Channel 10 sampling time selection + @"SMP[8]": SAMPLE_TIME, + padding: u5, }), /// sample time register 2 SMPR2: mmio.Mmio(packed struct(u32) { - /// Channel 0 sampling time selection - SMP: SAMPLE_TIME, - padding: u29, + /// (1/10 of SMP) Channel 0 sampling time selection + @"SMP[0]": SAMPLE_TIME, + /// (2/10 of SMP) Channel 0 sampling time selection + @"SMP[1]": SAMPLE_TIME, + /// (3/10 of SMP) Channel 0 sampling time selection + @"SMP[2]": SAMPLE_TIME, + /// (4/10 of SMP) Channel 0 sampling time selection + @"SMP[3]": SAMPLE_TIME, + /// (5/10 of SMP) Channel 0 sampling time selection + @"SMP[4]": SAMPLE_TIME, + /// (6/10 of SMP) Channel 0 sampling time selection + @"SMP[5]": SAMPLE_TIME, + /// (7/10 of SMP) Channel 0 sampling time selection + @"SMP[6]": SAMPLE_TIME, + /// (8/10 of SMP) Channel 0 sampling time selection + @"SMP[7]": SAMPLE_TIME, + /// (9/10 of SMP) Channel 0 sampling time selection + @"SMP[8]": SAMPLE_TIME, + /// (10/10 of SMP) Channel 0 sampling time selection + @"SMP[9]": SAMPLE_TIME, + padding: u2, }), /// injected channel data offset register x JOFR: [4]mmio.Mmio(packed struct(u32) { @@ -309067,30 +309728,60 @@ pub const types = struct { }), /// regular sequence register 1 SQR1: mmio.Mmio(packed struct(u32) { - /// 13th conversion in regular sequence - SQ: u5, - reserved20: u15, + /// (1/4 of SQ) 13th conversion in regular sequence + @"SQ[0]": u5, + /// (2/4 of SQ) 13th conversion in regular sequence + @"SQ[1]": u5, + /// (3/4 of SQ) 13th conversion in regular sequence + @"SQ[2]": u5, + /// (4/4 of SQ) 13th conversion in regular sequence + @"SQ[3]": u5, /// Regular channel sequence length L: u4, padding: u8, }), /// regular sequence register 2 SQR2: mmio.Mmio(packed struct(u32) { - /// 7th conversion in regular sequence - SQ: u5, - padding: u27, + /// (1/6 of SQ) 7th conversion in regular sequence + @"SQ[0]": u5, + /// (2/6 of SQ) 7th conversion in regular sequence + @"SQ[1]": u5, + /// (3/6 of SQ) 7th conversion in regular sequence + @"SQ[2]": u5, + /// (4/6 of SQ) 7th conversion in regular sequence + @"SQ[3]": u5, + /// (5/6 of SQ) 7th conversion in regular sequence + @"SQ[4]": u5, + /// (6/6 of SQ) 7th conversion in regular sequence + @"SQ[5]": u5, + padding: u2, }), /// regular sequence register 3 SQR3: mmio.Mmio(packed struct(u32) { - /// 1st conversion in regular sequence - SQ: u5, - padding: u27, + /// (1/6 of SQ) 1st conversion in regular sequence + @"SQ[0]": u5, + /// (2/6 of SQ) 1st conversion in regular sequence + @"SQ[1]": u5, + /// (3/6 of SQ) 1st conversion in regular sequence + @"SQ[2]": u5, + /// (4/6 of SQ) 1st conversion in regular sequence + @"SQ[3]": u5, + /// (5/6 of SQ) 1st conversion in regular sequence + @"SQ[4]": u5, + /// (6/6 of SQ) 1st conversion in regular sequence + @"SQ[5]": u5, + padding: u2, }), /// injected sequence register JSQR: mmio.Mmio(packed struct(u32) { - /// 1st conversion in injected sequence - JSQ: u5, - reserved20: u15, + /// (1/4 of JSQ) 1st conversion in injected sequence + @"JSQ[0]": u5, + /// (2/4 of JSQ) 1st conversion in injected sequence + @"JSQ[1]": u5, + /// (3/4 of JSQ) 1st conversion in injected sequence + @"JSQ[2]": u5, + /// (4/4 of JSQ) 1st conversion in injected sequence + @"JSQ[3]": u5, /// Injected sequence length JL: u2, padding: u10, @@ -309166,9 +309857,12 @@ pub const types = struct { JEOC: u1, /// JEOS JEOS: u1, - /// AWD1 - AWD: u1, - reserved10: u2, + /// (1/3 of AWD) AWD1 + @"AWD[0]": u1, + /// (2/3 of AWD) AWD1 + @"AWD[1]": u1, + /// (3/3 of AWD) AWD1 + @"AWD[2]": u1, /// JQOVF JQOVF: u1, padding: u21, @@ -309284,9 +309978,27 @@ pub const types = struct { }), /// sample time register 1 SMPR: [2]mmio.Mmio(packed struct(u32) { - /// Channel 0 sampling time selection - SMP: SAMPLE_TIME, - padding: u29, + /// (1/10 of SMP) Channel 0 sampling time selection + @"SMP[0]": SAMPLE_TIME, + /// (2/10 of SMP) Channel 0 sampling time selection + @"SMP[1]": SAMPLE_TIME, + /// (3/10 of SMP) Channel 0 sampling time selection + @"SMP[2]": SAMPLE_TIME, + /// (4/10 of SMP) Channel 0 sampling time selection + @"SMP[3]": SAMPLE_TIME, + /// (5/10 of SMP) Channel 0 sampling time selection + @"SMP[4]": SAMPLE_TIME, + /// (6/10 of SMP) Channel 0 sampling time selection + @"SMP[5]": SAMPLE_TIME, + /// (7/10 of SMP) Channel 0 sampling time selection + @"SMP[6]": SAMPLE_TIME, + /// (8/10 of SMP) Channel 0 sampling time selection + @"SMP[7]": SAMPLE_TIME, + /// (9/10 of SMP) Channel 0 sampling time selection + @"SMP[8]": SAMPLE_TIME, + /// (10/10 of SMP) Channel 0 sampling time selection + @"SMP[9]": SAMPLE_TIME, + padding: u2, }), reserved32: [4]u8, /// watchdog threshold register 1 @@ -309304,27 +310016,63 @@ pub const types = struct { /// Regular channel sequence length L: u4, reserved6: u2, - /// SQ1 - SQ: u5, - padding: u21, + /// (1/4 of SQ) SQ1 + @"SQ[0]": u5, + reserved12: u1, + /// (2/4 of SQ) SQ1 + @"SQ[1]": u5, + reserved18: u1, + /// (3/4 of SQ) SQ1 + @"SQ[2]": u5, + reserved24: u1, + /// (4/4 of SQ) SQ1 + @"SQ[3]": u5, + padding: u3, }), /// regular sequence register 2 SQR2: mmio.Mmio(packed struct(u32) { - /// SQ5 - SQ: u5, - padding: u27, + /// (1/5 of SQ) SQ5 + @"SQ[0]": u5, + reserved6: u1, + /// (2/5 of SQ) SQ5 + @"SQ[1]": u5, + reserved12: u1, + /// (3/5 of SQ) SQ5 + @"SQ[2]": u5, + reserved18: u1, + /// (4/5 of SQ) SQ5 + @"SQ[3]": u5, + reserved24: u1, + /// (5/5 of SQ) SQ5 + @"SQ[4]": u5, + padding: u3, }), /// regular sequence register 3 SQR3: mmio.Mmio(packed struct(u32) { - /// SQ10 - SQ: u5, - padding: u27, + /// (1/5 of SQ) SQ10 + @"SQ[0]": u5, + reserved6: u1, + /// (2/5 of SQ) SQ10 + @"SQ[1]": u5, + reserved12: u1, + /// (3/5 of SQ) SQ10 + @"SQ[2]": u5, + reserved18: u1, + /// (4/5 of SQ) SQ10 + @"SQ[3]": u5, + reserved24: u1, + /// (5/5 of SQ) SQ10 + @"SQ[4]": u5, + padding: u3, }), /// regular sequence register 4 SQR4: mmio.Mmio(packed struct(u32) { - /// SQ15 - SQ: u5, - padding: u27, + /// (1/2 of SQ) SQ15 + @"SQ[0]": u5, + reserved6: u1, + /// (2/2 of SQ) SQ15 + @"SQ[1]": u5, + padding: u21, }), /// regular Data Register DR: mmio.Mmio(packed struct(u32) { @@ -309341,9 +310089,18 @@ pub const types = struct { JEXTSEL: u4, /// JEXTEN JEXTEN: u2, - /// JSQ1 - JSQ: u5, - padding: u19, + /// (1/4 of JSQ) JSQ1 + @"JSQ[0]": u5, + reserved14: u1, + /// (2/4 of JSQ) JSQ1 + @"JSQ[1]": u5, + reserved20: u1, + /// (3/4 of JSQ) JSQ1 + @"JSQ[2]": u5, + reserved26: u1, + /// (4/4 of JSQ) JSQ1 + @"JSQ[3]": u5, + padding: u1, }), reserved96: [16]u8, /// offset register 1 @@ -309708,15 +310465,71 @@ pub const types = struct { }), /// sampling time register 1-2 SMPR: [2]mmio.Mmio(packed struct(u32) { - /// channel n * 10 + x sampling time - SMP: SAMPLE_TIME, - padding: u29, + /// (1/10 of SMP) channel n * 10 + x sampling time + @"SMP[0]": SAMPLE_TIME, + /// (2/10 of SMP) channel n * 10 + x sampling time + @"SMP[1]": SAMPLE_TIME, + /// (3/10 of SMP) channel n * 10 + x sampling time + @"SMP[2]": SAMPLE_TIME, + /// (4/10 of SMP) channel n * 10 + x sampling time + @"SMP[3]": SAMPLE_TIME, + /// (5/10 of SMP) channel n * 10 + x sampling time + @"SMP[4]": SAMPLE_TIME, + /// (6/10 of SMP) channel n * 10 + x sampling time + @"SMP[5]": SAMPLE_TIME, + /// (7/10 of SMP) channel n * 10 + x sampling time + @"SMP[6]": SAMPLE_TIME, + /// (8/10 of SMP) channel n * 10 + x sampling time + @"SMP[7]": SAMPLE_TIME, + /// (9/10 of SMP) channel n * 10 + x sampling time + @"SMP[8]": SAMPLE_TIME, + /// (10/10 of SMP) channel n * 10 + x sampling time + @"SMP[9]": SAMPLE_TIME, + padding: u2, }), /// pre channel selection register PCSEL: mmio.Mmio(packed struct(u32) { - /// Channel x (VINP[i]) pre selection - PCSEL: PCSEL, - padding: u31, + /// (1/20 of PCSEL) Channel x (VINP[i]) pre selection + @"PCSEL[0]": PCSEL, + /// (2/20 of PCSEL) Channel x (VINP[i]) pre selection + @"PCSEL[1]": PCSEL, + /// (3/20 of PCSEL) Channel x (VINP[i]) pre selection + @"PCSEL[2]": PCSEL, + /// (4/20 of PCSEL) Channel x (VINP[i]) pre selection + @"PCSEL[3]": PCSEL, + /// (5/20 of PCSEL) Channel x (VINP[i]) pre selection + @"PCSEL[4]": PCSEL, + /// (6/20 of PCSEL) Channel x (VINP[i]) pre selection + @"PCSEL[5]": PCSEL, + /// (7/20 of PCSEL) Channel x (VINP[i]) pre selection + @"PCSEL[6]": PCSEL, + /// (8/20 of PCSEL) Channel x (VINP[i]) pre selection + @"PCSEL[7]": PCSEL, + /// (9/20 of PCSEL) Channel x (VINP[i]) pre selection + @"PCSEL[8]": PCSEL, + /// (10/20 of PCSEL) Channel x (VINP[i]) pre selection + @"PCSEL[9]": PCSEL, + /// (11/20 of PCSEL) Channel x (VINP[i]) pre selection + @"PCSEL[10]": PCSEL, + /// (12/20 of PCSEL) Channel x (VINP[i]) pre selection + @"PCSEL[11]": PCSEL, + /// (13/20 of PCSEL) Channel x (VINP[i]) pre selection + @"PCSEL[12]": PCSEL, + /// (14/20 of PCSEL) Channel x (VINP[i]) pre selection + @"PCSEL[13]": PCSEL, + /// (15/20 of PCSEL) Channel x (VINP[i]) pre selection + @"PCSEL[14]": PCSEL, + /// (16/20 of PCSEL) Channel x (VINP[i]) pre selection + @"PCSEL[15]": PCSEL, + /// (17/20 of PCSEL) Channel x (VINP[i]) pre selection + @"PCSEL[16]": PCSEL, + /// (18/20 of PCSEL) Channel x (VINP[i]) pre selection + @"PCSEL[17]": PCSEL, + /// (19/20 of PCSEL) Channel x (VINP[i]) pre selection + @"PCSEL[18]": PCSEL, + /// (20/20 of PCSEL) Channel x (VINP[i]) pre selection + @"PCSEL[19]": PCSEL, + padding: u12, }), /// analog watchdog 1 threshold register LTR1: mmio.Mmio(packed struct(u32) { @@ -309736,27 +310549,63 @@ pub const types = struct { /// L3 L: u4, reserved6: u2, - /// group regular sequencer rank 1-4 - SQ: u5, - padding: u21, + /// (1/4 of SQ) group regular sequencer rank 1-4 + @"SQ[0]": u5, + reserved12: u1, + /// (2/4 of SQ) group regular sequencer rank 1-4 + @"SQ[1]": u5, + reserved18: u1, + /// (3/4 of SQ) group regular sequencer rank 1-4 + @"SQ[2]": u5, + reserved24: u1, + /// (4/4 of SQ) group regular sequencer rank 1-4 + @"SQ[3]": u5, + padding: u3, }), /// group regular sequencer ranks register 2 SQR2: mmio.Mmio(packed struct(u32) { - /// group regular sequencer rank 5-9 - SQ: u5, - padding: u27, + /// (1/5 of SQ) group regular sequencer rank 5-9 + @"SQ[0]": u5, + reserved6: u1, + /// (2/5 of SQ) group regular sequencer rank 5-9 + @"SQ[1]": u5, + reserved12: u1, + /// (3/5 of SQ) group regular sequencer rank 5-9 + @"SQ[2]": u5, + reserved18: u1, + /// (4/5 of SQ) group regular sequencer rank 5-9 + @"SQ[3]": u5, + reserved24: u1, + /// (5/5 of SQ) group regular sequencer rank 5-9 + @"SQ[4]": u5, + padding: u3, }), /// group regular sequencer ranks register 3 SQR3: mmio.Mmio(packed struct(u32) { - /// group regular sequencer rank 10-14 - SQ: u5, - padding: u27, + /// (1/5 of SQ) group regular sequencer rank 10-14 + @"SQ[0]": u5, + reserved6: u1, + /// (2/5 of SQ) group regular sequencer rank 10-14 + @"SQ[1]": u5, + reserved12: u1, + /// (3/5 of SQ) group regular sequencer rank 10-14 + @"SQ[2]": u5, + reserved18: u1, + /// (4/5 of SQ) group regular sequencer rank 10-14 + @"SQ[3]": u5, + reserved24: u1, + /// (5/5 of SQ) group regular sequencer rank 10-14 + @"SQ[4]": u5, + padding: u3, }), /// group regular sequencer ranks register 4 SQR4: mmio.Mmio(packed struct(u32) { - /// group regular sequencer rank 15-16 - SQ: u5, - padding: u27, + /// (1/2 of SQ) group regular sequencer rank 15-16 + @"SQ[0]": u5, + reserved6: u1, + /// (2/2 of SQ) group regular sequencer rank 15-16 + @"SQ[1]": u5, + padding: u21, }), /// group regular conversion data register DR: mmio.Mmio(packed struct(u32) { @@ -309773,9 +310622,17 @@ pub const types = struct { JEXTSEL: u5, /// group injected external trigger polarity JEXTEN: JEXTEN, - /// group injected sequencer rank 1-4 - JSQ1: u5, - padding: u18, + /// (1/4 of JSQ1) group injected sequencer rank 1-4 + @"JSQ1[0]": u5, + reserved15: u1, + /// (2/4 of JSQ1) group injected sequencer rank 1-4 + @"JSQ1[1]": u5, + reserved21: u1, + /// (3/4 of JSQ1) group injected sequencer rank 1-4 + @"JSQ1[2]": u5, + reserved27: u1, + /// (4/4 of JSQ1) group injected sequencer rank 1-4 + @"JSQ1[3]": u5, }), reserved96: [16]u8, /// offset number 1-4 register @@ -309796,16 +310653,92 @@ pub const types = struct { reserved160: [16]u8, /// analog watchdog 2 configuration register AWD2CR: mmio.Mmio(packed struct(u32) { - /// analog watchdog 2 monitored channel selection - AWD2CH: u1, - padding: u31, + /// (1/20 of AWD2CH) analog watchdog 2 monitored channel selection + @"AWD2CH[0]": u1, + /// (2/20 of AWD2CH) analog watchdog 2 monitored channel selection + @"AWD2CH[1]": u1, + /// (3/20 of AWD2CH) analog watchdog 2 monitored channel selection + @"AWD2CH[2]": u1, + /// (4/20 of AWD2CH) analog watchdog 2 monitored channel selection + @"AWD2CH[3]": u1, + /// (5/20 of AWD2CH) analog watchdog 2 monitored channel selection + @"AWD2CH[4]": u1, + /// (6/20 of AWD2CH) analog watchdog 2 monitored channel selection + @"AWD2CH[5]": u1, + /// (7/20 of AWD2CH) analog watchdog 2 monitored channel selection + @"AWD2CH[6]": u1, + /// (8/20 of AWD2CH) analog watchdog 2 monitored channel selection + @"AWD2CH[7]": u1, + /// (9/20 of AWD2CH) analog watchdog 2 monitored channel selection + @"AWD2CH[8]": u1, + /// (10/20 of AWD2CH) analog watchdog 2 monitored channel selection + @"AWD2CH[9]": u1, + /// (11/20 of AWD2CH) analog watchdog 2 monitored channel selection + @"AWD2CH[10]": u1, + /// (12/20 of AWD2CH) analog watchdog 2 monitored channel selection + @"AWD2CH[11]": u1, + /// (13/20 of AWD2CH) analog watchdog 2 monitored channel selection + @"AWD2CH[12]": u1, + /// (14/20 of AWD2CH) analog watchdog 2 monitored channel selection + @"AWD2CH[13]": u1, + /// (15/20 of AWD2CH) analog watchdog 2 monitored channel selection + @"AWD2CH[14]": u1, + /// (16/20 of AWD2CH) analog watchdog 2 monitored channel selection + @"AWD2CH[15]": u1, + /// (17/20 of AWD2CH) analog watchdog 2 monitored channel selection + @"AWD2CH[16]": u1, + /// (18/20 of AWD2CH) analog watchdog 2 monitored channel selection + @"AWD2CH[17]": u1, + /// (19/20 of AWD2CH) analog watchdog 2 monitored channel selection + @"AWD2CH[18]": u1, + /// (20/20 of AWD2CH) analog watchdog 2 monitored channel selection + @"AWD2CH[19]": u1, + padding: u12, }), /// analog watchdog 3 configuration register AWD3CR: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// analog watchdog 3 monitored channel selection - AWD3CH: u1, - padding: u30, + /// (1/20 of AWD3CH) analog watchdog 3 monitored channel selection + @"AWD3CH[0]": u1, + /// (2/20 of AWD3CH) analog watchdog 3 monitored channel selection + @"AWD3CH[1]": u1, + /// (3/20 of AWD3CH) analog watchdog 3 monitored channel selection + @"AWD3CH[2]": u1, + /// (4/20 of AWD3CH) analog watchdog 3 monitored channel selection + @"AWD3CH[3]": u1, + /// (5/20 of AWD3CH) analog watchdog 3 monitored channel selection + @"AWD3CH[4]": u1, + /// (6/20 of AWD3CH) analog watchdog 3 monitored channel selection + @"AWD3CH[5]": u1, + /// (7/20 of AWD3CH) analog watchdog 3 monitored channel selection + @"AWD3CH[6]": u1, + /// (8/20 of AWD3CH) analog watchdog 3 monitored channel selection + @"AWD3CH[7]": u1, + /// (9/20 of AWD3CH) analog watchdog 3 monitored channel selection + @"AWD3CH[8]": u1, + /// (10/20 of AWD3CH) analog watchdog 3 monitored channel selection + @"AWD3CH[9]": u1, + /// (11/20 of AWD3CH) analog watchdog 3 monitored channel selection + @"AWD3CH[10]": u1, + /// (12/20 of AWD3CH) analog watchdog 3 monitored channel selection + @"AWD3CH[11]": u1, + /// (13/20 of AWD3CH) analog watchdog 3 monitored channel selection + @"AWD3CH[12]": u1, + /// (14/20 of AWD3CH) analog watchdog 3 monitored channel selection + @"AWD3CH[13]": u1, + /// (15/20 of AWD3CH) analog watchdog 3 monitored channel selection + @"AWD3CH[14]": u1, + /// (16/20 of AWD3CH) analog watchdog 3 monitored channel selection + @"AWD3CH[15]": u1, + /// (17/20 of AWD3CH) analog watchdog 3 monitored channel selection + @"AWD3CH[16]": u1, + /// (18/20 of AWD3CH) analog watchdog 3 monitored channel selection + @"AWD3CH[17]": u1, + /// (19/20 of AWD3CH) analog watchdog 3 monitored channel selection + @"AWD3CH[18]": u1, + /// (20/20 of AWD3CH) analog watchdog 3 monitored channel selection + @"AWD3CH[19]": u1, + padding: u11, }), reserved176: [8]u8, /// watchdog lower threshold register 2 @@ -309834,9 +310767,47 @@ pub const types = struct { }), /// channel differential or single-ended mode selection register DIFSEL: mmio.Mmio(packed struct(u32) { - /// channel differential or single-ended mode for channel - DIFSEL: DIFSEL, - padding: u31, + /// (1/20 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[0]": DIFSEL, + /// (2/20 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[1]": DIFSEL, + /// (3/20 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[2]": DIFSEL, + /// (4/20 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[3]": DIFSEL, + /// (5/20 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[4]": DIFSEL, + /// (6/20 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[5]": DIFSEL, + /// (7/20 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[6]": DIFSEL, + /// (8/20 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[7]": DIFSEL, + /// (9/20 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[8]": DIFSEL, + /// (10/20 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[9]": DIFSEL, + /// (11/20 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[10]": DIFSEL, + /// (12/20 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[11]": DIFSEL, + /// (13/20 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[12]": DIFSEL, + /// (14/20 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[13]": DIFSEL, + /// (15/20 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[14]": DIFSEL, + /// (16/20 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[15]": DIFSEL, + /// (17/20 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[16]": DIFSEL, + /// (18/20 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[17]": DIFSEL, + /// (19/20 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[18]": DIFSEL, + /// (20/20 of DIFSEL) channel differential or single-ended mode for channel + @"DIFSEL[19]": DIFSEL, + padding: u12, }), /// calibration factors register CALFACT: mmio.Mmio(packed struct(u32) { @@ -309926,9 +310897,12 @@ pub const types = struct { JEOC_MST: u1, /// End of injected sequence flag of the master ADC JEOS: u1, - /// Analog watchdog flag of the master ADC - AWD_MST: u1, - reserved10: u2, + /// (1/3 of AWD_MST) Analog watchdog flag of the master ADC + @"AWD_MST[0]": u1, + /// (2/3 of AWD_MST) Analog watchdog flag of the master ADC + @"AWD_MST[1]": u1, + /// (3/3 of AWD_MST) Analog watchdog flag of the master ADC + @"AWD_MST[2]": u1, /// Injected context queue overflow flag of the master ADC JQOVF_MST: u1, reserved16: u5, @@ -309946,9 +310920,12 @@ pub const types = struct { JEOC_SLV: u1, /// End of injected sequence flag of the slave ADC JEOS_SLV: u1, - /// Analog watchdog flag of the slave ADC - AWD_SLV: u1, - reserved26: u2, + /// (1/3 of AWD_SLV) Analog watchdog flag of the slave ADC + @"AWD_SLV[0]": u1, + /// (2/3 of AWD_SLV) Analog watchdog flag of the slave ADC + @"AWD_SLV[1]": u1, + /// (3/3 of AWD_SLV) Analog watchdog flag of the slave ADC + @"AWD_SLV[2]": u1, /// Injected context queue overflow flag of the slave ADC JQOVF_SLV: u1, padding: u5, @@ -310090,9 +311067,12 @@ pub const types = struct { JEOC_MST: u1, /// End of injected sequence flag of the master ADC This bit is a copy of the JEOS bit in the corresponding ADC_ISR register. JEOS_MST: u1, - /// Analog watchdog 1 flag of the master ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register. - AWD_MST: u1, - reserved10: u2, + /// (1/3 of AWD_MST) Analog watchdog 1 flag of the master ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register. + @"AWD_MST[0]": u1, + /// (2/3 of AWD_MST) Analog watchdog 1 flag of the master ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register. + @"AWD_MST[1]": u1, + /// (3/3 of AWD_MST) Analog watchdog 1 flag of the master ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register. + @"AWD_MST[2]": u1, /// Injected Context Queue Overflow flag of the master ADC This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register. JQOVF_MST: u1, reserved16: u5, @@ -310110,9 +311090,12 @@ pub const types = struct { JEOC_SLV: u1, /// End of injected sequence flag of the slave ADC This bit is a copy of the JEOS bit in the corresponding ADC_ISR register. JEOS_SLV: u1, - /// Analog watchdog 1 flag of the slave ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register. - AWD_SLV: u1, - reserved26: u2, + /// (1/3 of AWD_SLV) Analog watchdog 1 flag of the slave ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register. + @"AWD_SLV[0]": u1, + /// (2/3 of AWD_SLV) Analog watchdog 1 flag of the slave ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register. + @"AWD_SLV[1]": u1, + /// (3/3 of AWD_SLV) Analog watchdog 1 flag of the slave ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register. + @"AWD_SLV[2]": u1, /// Injected Context Queue Overflow flag of the slave ADC This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register. JQOVF_SLV: u1, padding: u5, @@ -310335,19 +311318,45 @@ pub const types = struct { pub const ADC_COMMON = extern struct { /// ADC Common status register CSR: mmio.Mmio(packed struct(u32) { - /// Analog watchdog event occurred - AWD: u1, - /// End of conversion of ADC - EOC: u1, - /// Injected channel end of conversion of ADC - JEOC: u1, - /// Injected channel conversion started - JSTRT: u1, - /// regular channel conversion started - STRT: u1, - /// Overrun occurred - OVR: u1, - padding: u26, + /// (1/3 of AWD) Analog watchdog event occurred + @"AWD[0]": u1, + /// (1/3 of EOC) End of conversion of ADC + @"EOC[0]": u1, + /// (1/3 of JEOC) Injected channel end of conversion of ADC + @"JEOC[0]": u1, + /// (1/3 of JSTRT) Injected channel conversion started + @"JSTRT[0]": u1, + /// (1/3 of STRT) regular channel conversion started + @"STRT[0]": u1, + /// (1/3 of OVR) Overrun occurred + @"OVR[0]": u1, + reserved8: u2, + /// (2/3 of AWD) Analog watchdog event occurred + @"AWD[1]": u1, + /// (2/3 of EOC) End of conversion of ADC + @"EOC[1]": u1, + /// (2/3 of JEOC) Injected channel end of conversion of ADC + @"JEOC[1]": u1, + /// (2/3 of JSTRT) Injected channel conversion started + @"JSTRT[1]": u1, + /// (2/3 of STRT) regular channel conversion started + @"STRT[1]": u1, + /// (2/3 of OVR) Overrun occurred + @"OVR[1]": u1, + reserved16: u2, + /// (3/3 of AWD) Analog watchdog event occurred + @"AWD[2]": u1, + /// (3/3 of EOC) End of conversion of ADC + @"EOC[2]": u1, + /// (3/3 of JEOC) Injected channel end of conversion of ADC + @"JEOC[2]": u1, + /// (3/3 of JSTRT) Injected channel conversion started + @"JSTRT[2]": u1, + /// (3/3 of STRT) regular channel conversion started + @"STRT[2]": u1, + /// (3/3 of OVR) Overrun occurred + @"OVR[2]": u1, + padding: u10, }), /// ADC common control register CCR: mmio.Mmio(packed struct(u32) { @@ -310372,9 +311381,10 @@ pub const types = struct { }), /// ADC common regular data register for dual and triple modes CDR: mmio.Mmio(packed struct(u32) { - /// 1st data item of a pair of regular conversions - DATA: u16, - padding: u16, + /// (1/2 of DATA) 1st data item of a pair of regular conversions + @"DATA[0]": u16, + /// (2/2 of DATA) 1st data item of a pair of regular conversions + @"DATA[1]": u16, }), }; }; @@ -310405,9 +311415,12 @@ pub const types = struct { JEOC_MST: u1, /// JEOS_MST JEOS_MST: u1, - /// Analog watchdog flag of the master ADC - AWD_MST: u1, - reserved10: u2, + /// (1/3 of AWD_MST) Analog watchdog flag of the master ADC + @"AWD_MST[0]": u1, + /// (2/3 of AWD_MST) Analog watchdog flag of the master ADC + @"AWD_MST[1]": u1, + /// (3/3 of AWD_MST) Analog watchdog flag of the master ADC + @"AWD_MST[2]": u1, /// JQOVF_MST JQOVF_MST: u1, reserved16: u5, @@ -310425,9 +311438,12 @@ pub const types = struct { JEOC_SLV: u1, /// End of injected sequence flag of the slave ADC JEOS_SLV: u1, - /// Analog watchdog 1 flag of the slave ADC - AWD_SLV: u1, - reserved26: u2, + /// (1/3 of AWD_SLV) Analog watchdog 1 flag of the slave ADC + @"AWD_SLV[0]": u1, + /// (2/3 of AWD_SLV) Analog watchdog 1 flag of the slave ADC + @"AWD_SLV[1]": u1, + /// (3/3 of AWD_SLV) Analog watchdog 1 flag of the slave ADC + @"AWD_SLV[2]": u1, /// Injected Context Queue Overflow flag of the slave ADC JQOVF_SLV: u1, padding: u5, @@ -310554,9 +311570,12 @@ pub const types = struct { JEOC_MST: u1, /// End of injected sequence flag of the master ADC JEOS_MST: u1, - /// Analog watchdog flag of the master ADC - AWD_MST: u1, - reserved10: u2, + /// (1/3 of AWD_MST) Analog watchdog flag of the master ADC + @"AWD_MST[0]": u1, + /// (2/3 of AWD_MST) Analog watchdog flag of the master ADC + @"AWD_MST[1]": u1, + /// (3/3 of AWD_MST) Analog watchdog flag of the master ADC + @"AWD_MST[2]": u1, /// Injected Context Queue Overflow flag of the master ADC JQOVF_MST: u1, reserved16: u5, @@ -310574,9 +311593,12 @@ pub const types = struct { JEOC_SLV: u1, /// End of injected sequence flag of the slave ADC JEOS_SLV: u1, - /// Analog watchdog flag of the slave ADC - AWD_SLV: u1, - reserved26: u2, + /// (1/3 of AWD_SLV) Analog watchdog flag of the slave ADC + @"AWD_SLV[0]": u1, + /// (2/3 of AWD_SLV) Analog watchdog flag of the slave ADC + @"AWD_SLV[1]": u1, + /// (3/3 of AWD_SLV) Analog watchdog flag of the slave ADC + @"AWD_SLV[2]": u1, /// Injected Context Queue Overflow flag of the slave ADC JQOVF_SLV: u1, padding: u5, @@ -311806,9 +312828,15 @@ pub const types = struct { }), /// External interrupt configuration register 1 (AFIO_EXTICR1) EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI12 configuration - EXTI: u4, - padding: u28, + /// (1/4 of EXTI) EXTI12 configuration + @"EXTI[0]": u4, + /// (2/4 of EXTI) EXTI12 configuration + @"EXTI[1]": u4, + /// (3/4 of EXTI) EXTI12 configuration + @"EXTI[2]": u4, + /// (4/4 of EXTI) EXTI12 configuration + @"EXTI[3]": u4, + padding: u16, }), reserved28: [4]u8, /// AF remap and debug I/O configuration register @@ -311921,27 +312949,137 @@ pub const types = struct { pub const DMA = extern struct { /// DMA interrupt status register (DMA_ISR) ISR: mmio.Mmio(packed struct(u32) { - /// Channel 1 Global interrupt flag - GIF: u1, - /// Channel 1 Transfer Complete flag - TCIF: u1, - /// Channel 1 Half Transfer Complete flag - HTIF: u1, - /// Channel 1 Transfer Error flag - TEIF: u1, - padding: u28, + /// (1/8 of GIF) Channel 1 Global interrupt flag + @"GIF[0]": u1, + /// (1/8 of TCIF) Channel 1 Transfer Complete flag + @"TCIF[0]": u1, + /// (1/8 of HTIF) Channel 1 Half Transfer Complete flag + @"HTIF[0]": u1, + /// (1/8 of TEIF) Channel 1 Transfer Error flag + @"TEIF[0]": u1, + /// (2/8 of GIF) Channel 1 Global interrupt flag + @"GIF[1]": u1, + /// (2/8 of TCIF) Channel 1 Transfer Complete flag + @"TCIF[1]": u1, + /// (2/8 of HTIF) Channel 1 Half Transfer Complete flag + @"HTIF[1]": u1, + /// (2/8 of TEIF) Channel 1 Transfer Error flag + @"TEIF[1]": u1, + /// (3/8 of GIF) Channel 1 Global interrupt flag + @"GIF[2]": u1, + /// (3/8 of TCIF) Channel 1 Transfer Complete flag + @"TCIF[2]": u1, + /// (3/8 of HTIF) Channel 1 Half Transfer Complete flag + @"HTIF[2]": u1, + /// (3/8 of TEIF) Channel 1 Transfer Error flag + @"TEIF[2]": u1, + /// (4/8 of GIF) Channel 1 Global interrupt flag + @"GIF[3]": u1, + /// (4/8 of TCIF) Channel 1 Transfer Complete flag + @"TCIF[3]": u1, + /// (4/8 of HTIF) Channel 1 Half Transfer Complete flag + @"HTIF[3]": u1, + /// (4/8 of TEIF) Channel 1 Transfer Error flag + @"TEIF[3]": u1, + /// (5/8 of GIF) Channel 1 Global interrupt flag + @"GIF[4]": u1, + /// (5/8 of TCIF) Channel 1 Transfer Complete flag + @"TCIF[4]": u1, + /// (5/8 of HTIF) Channel 1 Half Transfer Complete flag + @"HTIF[4]": u1, + /// (5/8 of TEIF) Channel 1 Transfer Error flag + @"TEIF[4]": u1, + /// (6/8 of GIF) Channel 1 Global interrupt flag + @"GIF[5]": u1, + /// (6/8 of TCIF) Channel 1 Transfer Complete flag + @"TCIF[5]": u1, + /// (6/8 of HTIF) Channel 1 Half Transfer Complete flag + @"HTIF[5]": u1, + /// (6/8 of TEIF) Channel 1 Transfer Error flag + @"TEIF[5]": u1, + /// (7/8 of GIF) Channel 1 Global interrupt flag + @"GIF[6]": u1, + /// (7/8 of TCIF) Channel 1 Transfer Complete flag + @"TCIF[6]": u1, + /// (7/8 of HTIF) Channel 1 Half Transfer Complete flag + @"HTIF[6]": u1, + /// (7/8 of TEIF) Channel 1 Transfer Error flag + @"TEIF[6]": u1, + /// (8/8 of GIF) Channel 1 Global interrupt flag + @"GIF[7]": u1, + /// (8/8 of TCIF) Channel 1 Transfer Complete flag + @"TCIF[7]": u1, + /// (8/8 of HTIF) Channel 1 Half Transfer Complete flag + @"HTIF[7]": u1, + /// (8/8 of TEIF) Channel 1 Transfer Error flag + @"TEIF[7]": u1, }), /// DMA interrupt flag clear register (DMA_IFCR) IFCR: mmio.Mmio(packed struct(u32) { - /// Channel 1 Global interrupt flag - GIF: u1, - /// Channel 1 Transfer Complete flag - TCIF: u1, - /// Channel 1 Half Transfer Complete flag - HTIF: u1, - /// Channel 1 Transfer Error flag - TEIF: u1, - padding: u28, + /// (1/8 of GIF) Channel 1 Global interrupt flag + @"GIF[0]": u1, + /// (1/8 of TCIF) Channel 1 Transfer Complete flag + @"TCIF[0]": u1, + /// (1/8 of HTIF) Channel 1 Half Transfer Complete flag + @"HTIF[0]": u1, + /// (1/8 of TEIF) Channel 1 Transfer Error flag + @"TEIF[0]": u1, + /// (2/8 of GIF) Channel 1 Global interrupt flag + @"GIF[1]": u1, + /// (2/8 of TCIF) Channel 1 Transfer Complete flag + @"TCIF[1]": u1, + /// (2/8 of HTIF) Channel 1 Half Transfer Complete flag + @"HTIF[1]": u1, + /// (2/8 of TEIF) Channel 1 Transfer Error flag + @"TEIF[1]": u1, + /// (3/8 of GIF) Channel 1 Global interrupt flag + @"GIF[2]": u1, + /// (3/8 of TCIF) Channel 1 Transfer Complete flag + @"TCIF[2]": u1, + /// (3/8 of HTIF) Channel 1 Half Transfer Complete flag + @"HTIF[2]": u1, + /// (3/8 of TEIF) Channel 1 Transfer Error flag + @"TEIF[2]": u1, + /// (4/8 of GIF) Channel 1 Global interrupt flag + @"GIF[3]": u1, + /// (4/8 of TCIF) Channel 1 Transfer Complete flag + @"TCIF[3]": u1, + /// (4/8 of HTIF) Channel 1 Half Transfer Complete flag + @"HTIF[3]": u1, + /// (4/8 of TEIF) Channel 1 Transfer Error flag + @"TEIF[3]": u1, + /// (5/8 of GIF) Channel 1 Global interrupt flag + @"GIF[4]": u1, + /// (5/8 of TCIF) Channel 1 Transfer Complete flag + @"TCIF[4]": u1, + /// (5/8 of HTIF) Channel 1 Half Transfer Complete flag + @"HTIF[4]": u1, + /// (5/8 of TEIF) Channel 1 Transfer Error flag + @"TEIF[4]": u1, + /// (6/8 of GIF) Channel 1 Global interrupt flag + @"GIF[5]": u1, + /// (6/8 of TCIF) Channel 1 Transfer Complete flag + @"TCIF[5]": u1, + /// (6/8 of HTIF) Channel 1 Half Transfer Complete flag + @"HTIF[5]": u1, + /// (6/8 of TEIF) Channel 1 Transfer Error flag + @"TEIF[5]": u1, + /// (7/8 of GIF) Channel 1 Global interrupt flag + @"GIF[6]": u1, + /// (7/8 of TCIF) Channel 1 Transfer Complete flag + @"TCIF[6]": u1, + /// (7/8 of HTIF) Channel 1 Half Transfer Complete flag + @"HTIF[6]": u1, + /// (7/8 of TEIF) Channel 1 Transfer Error flag + @"TEIF[6]": u1, + /// (8/8 of GIF) Channel 1 Global interrupt flag + @"GIF[7]": u1, + /// (8/8 of TCIF) Channel 1 Transfer Complete flag + @"TCIF[7]": u1, + /// (8/8 of HTIF) Channel 1 Half Transfer Complete flag + @"HTIF[7]": u1, + /// (8/8 of TEIF) Channel 1 Transfer Error flag + @"TEIF[7]": u1, }), /// Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers CH: u32, @@ -312023,36 +313161,159 @@ pub const types = struct { pub const DMA = extern struct { /// DMA interrupt status register (DMA_ISR) ISR: mmio.Mmio(packed struct(u32) { - /// Channel 1 Global interrupt flag - GIF: u1, - /// Channel 1 Transfer Complete flag - TCIF: u1, - /// Channel 1 Half Transfer Complete flag - HTIF: u1, - /// Channel 1 Transfer Error flag - TEIF: u1, - padding: u28, + /// (1/8 of GIF) Channel 1 Global interrupt flag + @"GIF[0]": u1, + /// (1/8 of TCIF) Channel 1 Transfer Complete flag + @"TCIF[0]": u1, + /// (1/8 of HTIF) Channel 1 Half Transfer Complete flag + @"HTIF[0]": u1, + /// (1/8 of TEIF) Channel 1 Transfer Error flag + @"TEIF[0]": u1, + /// (2/8 of GIF) Channel 1 Global interrupt flag + @"GIF[1]": u1, + /// (2/8 of TCIF) Channel 1 Transfer Complete flag + @"TCIF[1]": u1, + /// (2/8 of HTIF) Channel 1 Half Transfer Complete flag + @"HTIF[1]": u1, + /// (2/8 of TEIF) Channel 1 Transfer Error flag + @"TEIF[1]": u1, + /// (3/8 of GIF) Channel 1 Global interrupt flag + @"GIF[2]": u1, + /// (3/8 of TCIF) Channel 1 Transfer Complete flag + @"TCIF[2]": u1, + /// (3/8 of HTIF) Channel 1 Half Transfer Complete flag + @"HTIF[2]": u1, + /// (3/8 of TEIF) Channel 1 Transfer Error flag + @"TEIF[2]": u1, + /// (4/8 of GIF) Channel 1 Global interrupt flag + @"GIF[3]": u1, + /// (4/8 of TCIF) Channel 1 Transfer Complete flag + @"TCIF[3]": u1, + /// (4/8 of HTIF) Channel 1 Half Transfer Complete flag + @"HTIF[3]": u1, + /// (4/8 of TEIF) Channel 1 Transfer Error flag + @"TEIF[3]": u1, + /// (5/8 of GIF) Channel 1 Global interrupt flag + @"GIF[4]": u1, + /// (5/8 of TCIF) Channel 1 Transfer Complete flag + @"TCIF[4]": u1, + /// (5/8 of HTIF) Channel 1 Half Transfer Complete flag + @"HTIF[4]": u1, + /// (5/8 of TEIF) Channel 1 Transfer Error flag + @"TEIF[4]": u1, + /// (6/8 of GIF) Channel 1 Global interrupt flag + @"GIF[5]": u1, + /// (6/8 of TCIF) Channel 1 Transfer Complete flag + @"TCIF[5]": u1, + /// (6/8 of HTIF) Channel 1 Half Transfer Complete flag + @"HTIF[5]": u1, + /// (6/8 of TEIF) Channel 1 Transfer Error flag + @"TEIF[5]": u1, + /// (7/8 of GIF) Channel 1 Global interrupt flag + @"GIF[6]": u1, + /// (7/8 of TCIF) Channel 1 Transfer Complete flag + @"TCIF[6]": u1, + /// (7/8 of HTIF) Channel 1 Half Transfer Complete flag + @"HTIF[6]": u1, + /// (7/8 of TEIF) Channel 1 Transfer Error flag + @"TEIF[6]": u1, + /// (8/8 of GIF) Channel 1 Global interrupt flag + @"GIF[7]": u1, + /// (8/8 of TCIF) Channel 1 Transfer Complete flag + @"TCIF[7]": u1, + /// (8/8 of HTIF) Channel 1 Half Transfer Complete flag + @"HTIF[7]": u1, + /// (8/8 of TEIF) Channel 1 Transfer Error flag + @"TEIF[7]": u1, }), /// DMA interrupt flag clear register (DMA_IFCR) IFCR: mmio.Mmio(packed struct(u32) { - /// Channel 1 Global interrupt flag - GIF: u1, - /// Channel 1 Transfer Complete flag - TCIF: u1, - /// Channel 1 Half Transfer Complete flag - HTIF: u1, - /// Channel 1 Transfer Error flag - TEIF: u1, - padding: u28, + /// (1/8 of GIF) Channel 1 Global interrupt flag + @"GIF[0]": u1, + /// (1/8 of TCIF) Channel 1 Transfer Complete flag + @"TCIF[0]": u1, + /// (1/8 of HTIF) Channel 1 Half Transfer Complete flag + @"HTIF[0]": u1, + /// (1/8 of TEIF) Channel 1 Transfer Error flag + @"TEIF[0]": u1, + /// (2/8 of GIF) Channel 1 Global interrupt flag + @"GIF[1]": u1, + /// (2/8 of TCIF) Channel 1 Transfer Complete flag + @"TCIF[1]": u1, + /// (2/8 of HTIF) Channel 1 Half Transfer Complete flag + @"HTIF[1]": u1, + /// (2/8 of TEIF) Channel 1 Transfer Error flag + @"TEIF[1]": u1, + /// (3/8 of GIF) Channel 1 Global interrupt flag + @"GIF[2]": u1, + /// (3/8 of TCIF) Channel 1 Transfer Complete flag + @"TCIF[2]": u1, + /// (3/8 of HTIF) Channel 1 Half Transfer Complete flag + @"HTIF[2]": u1, + /// (3/8 of TEIF) Channel 1 Transfer Error flag + @"TEIF[2]": u1, + /// (4/8 of GIF) Channel 1 Global interrupt flag + @"GIF[3]": u1, + /// (4/8 of TCIF) Channel 1 Transfer Complete flag + @"TCIF[3]": u1, + /// (4/8 of HTIF) Channel 1 Half Transfer Complete flag + @"HTIF[3]": u1, + /// (4/8 of TEIF) Channel 1 Transfer Error flag + @"TEIF[3]": u1, + /// (5/8 of GIF) Channel 1 Global interrupt flag + @"GIF[4]": u1, + /// (5/8 of TCIF) Channel 1 Transfer Complete flag + @"TCIF[4]": u1, + /// (5/8 of HTIF) Channel 1 Half Transfer Complete flag + @"HTIF[4]": u1, + /// (5/8 of TEIF) Channel 1 Transfer Error flag + @"TEIF[4]": u1, + /// (6/8 of GIF) Channel 1 Global interrupt flag + @"GIF[5]": u1, + /// (6/8 of TCIF) Channel 1 Transfer Complete flag + @"TCIF[5]": u1, + /// (6/8 of HTIF) Channel 1 Half Transfer Complete flag + @"HTIF[5]": u1, + /// (6/8 of TEIF) Channel 1 Transfer Error flag + @"TEIF[5]": u1, + /// (7/8 of GIF) Channel 1 Global interrupt flag + @"GIF[6]": u1, + /// (7/8 of TCIF) Channel 1 Transfer Complete flag + @"TCIF[6]": u1, + /// (7/8 of HTIF) Channel 1 Half Transfer Complete flag + @"HTIF[6]": u1, + /// (7/8 of TEIF) Channel 1 Transfer Error flag + @"TEIF[6]": u1, + /// (8/8 of GIF) Channel 1 Global interrupt flag + @"GIF[7]": u1, + /// (8/8 of TCIF) Channel 1 Transfer Complete flag + @"TCIF[7]": u1, + /// (8/8 of HTIF) Channel 1 Half Transfer Complete flag + @"HTIF[7]": u1, + /// (8/8 of TEIF) Channel 1 Transfer Error flag + @"TEIF[7]": u1, }), /// Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers CH: u32, reserved168: [156]u8, /// channel selection register CSELR: mmio.Mmio(packed struct(u32) { - /// DMA channel selection - CS: u4, - padding: u28, + /// (1/8 of CS) DMA channel selection + @"CS[0]": u4, + /// (2/8 of CS) DMA channel selection + @"CS[1]": u4, + /// (3/8 of CS) DMA channel selection + @"CS[2]": u4, + /// (4/8 of CS) DMA channel selection + @"CS[3]": u4, + /// (5/8 of CS) DMA channel selection + @"CS[4]": u4, + /// (6/8 of CS) DMA channel selection + @"CS[5]": u4, + /// (7/8 of CS) DMA channel selection + @"CS[6]": u4, + /// (8/8 of CS) DMA channel selection + @"CS[7]": u4, }), }; }; @@ -312212,26 +313473,53 @@ pub const types = struct { }), /// transmit status register TSR: mmio.Mmio(packed struct(u32) { - /// RQCP0 - RQCP: u1, - /// TXOK0 - TXOK: u1, - /// ALST0 - ALST: u1, - /// TERR0 - TERR: u1, + /// (1/3 of RQCP) RQCP0 + @"RQCP[0]": u1, + /// (1/3 of TXOK) TXOK0 + @"TXOK[0]": u1, + /// (1/3 of ALST) ALST0 + @"ALST[0]": u1, + /// (1/3 of TERR) TERR0 + @"TERR[0]": u1, reserved7: u3, - /// ABRQ0 - ABRQ: u1, - reserved24: u16, + /// (1/3 of ABRQ) ABRQ0 + @"ABRQ[0]": u1, + /// (2/3 of RQCP) RQCP0 + @"RQCP[1]": u1, + /// (2/3 of TXOK) TXOK0 + @"TXOK[1]": u1, + /// (2/3 of ALST) ALST0 + @"ALST[1]": u1, + /// (2/3 of TERR) TERR0 + @"TERR[1]": u1, + reserved15: u3, + /// (2/3 of ABRQ) ABRQ0 + @"ABRQ[1]": u1, + /// (3/3 of RQCP) RQCP0 + @"RQCP[2]": u1, + /// (3/3 of TXOK) TXOK0 + @"TXOK[2]": u1, + /// (3/3 of ALST) ALST0 + @"ALST[2]": u1, + /// (3/3 of TERR) TERR0 + @"TERR[2]": u1, + reserved23: u3, + /// (3/3 of ABRQ) ABRQ0 + @"ABRQ[2]": u1, /// CODE CODE: u2, - /// Lowest priority flag for mailbox 0 - TME: u1, - reserved29: u2, - /// Lowest priority flag for mailbox 0 - LOW: u1, - padding: u2, + /// (1/3 of TME) Lowest priority flag for mailbox 0 + @"TME[0]": u1, + /// (2/3 of TME) Lowest priority flag for mailbox 0 + @"TME[1]": u1, + /// (3/3 of TME) Lowest priority flag for mailbox 0 + @"TME[2]": u1, + /// (1/3 of LOW) Lowest priority flag for mailbox 0 + @"LOW[0]": u1, + /// (2/3 of LOW) Lowest priority flag for mailbox 0 + @"LOW[1]": u1, + /// (3/3 of LOW) Lowest priority flag for mailbox 0 + @"LOW[2]": u1, }), /// receive FIFO 0 register RFR: [2]mmio.Mmio(packed struct(u32) { @@ -312250,13 +313538,19 @@ pub const types = struct { IER: mmio.Mmio(packed struct(u32) { /// TMEIE TMEIE: u1, - /// FMPIE0 - FMPIE: u1, - /// FFIE0 - FFIE: u1, - /// FOVIE0 - FOVIE: u1, - reserved8: u4, + /// (1/2 of FMPIE) FMPIE0 + @"FMPIE[0]": u1, + /// (1/2 of FFIE) FFIE0 + @"FFIE[0]": u1, + /// (1/2 of FOVIE) FOVIE0 + @"FOVIE[0]": u1, + /// (2/2 of FMPIE) FMPIE0 + @"FMPIE[1]": u1, + /// (2/2 of FFIE) FFIE0 + @"FFIE[1]": u1, + /// (2/2 of FOVIE) FOVIE0 + @"FOVIE[1]": u1, + reserved8: u1, /// EWGIE EWGIE: u1, /// EPVIE @@ -312296,9 +313590,10 @@ pub const types = struct { /// BRP BRP: u10, reserved16: u6, - /// TS1 - TS: u4, - reserved24: u4, + /// (1/2 of TS) TS1 + @"TS[0]": u4, + /// (2/2 of TS) TS1 + @"TS[1]": u4, /// SJW SJW: u2, reserved30: u4, @@ -312325,30 +313620,246 @@ pub const types = struct { }), /// filter mode register FM1R: mmio.Mmio(packed struct(u32) { - /// Filter mode - FBM: u1, - padding: u31, + /// (1/28 of FBM) Filter mode + @"FBM[0]": u1, + /// (2/28 of FBM) Filter mode + @"FBM[1]": u1, + /// (3/28 of FBM) Filter mode + @"FBM[2]": u1, + /// (4/28 of FBM) Filter mode + @"FBM[3]": u1, + /// (5/28 of FBM) Filter mode + @"FBM[4]": u1, + /// (6/28 of FBM) Filter mode + @"FBM[5]": u1, + /// (7/28 of FBM) Filter mode + @"FBM[6]": u1, + /// (8/28 of FBM) Filter mode + @"FBM[7]": u1, + /// (9/28 of FBM) Filter mode + @"FBM[8]": u1, + /// (10/28 of FBM) Filter mode + @"FBM[9]": u1, + /// (11/28 of FBM) Filter mode + @"FBM[10]": u1, + /// (12/28 of FBM) Filter mode + @"FBM[11]": u1, + /// (13/28 of FBM) Filter mode + @"FBM[12]": u1, + /// (14/28 of FBM) Filter mode + @"FBM[13]": u1, + /// (15/28 of FBM) Filter mode + @"FBM[14]": u1, + /// (16/28 of FBM) Filter mode + @"FBM[15]": u1, + /// (17/28 of FBM) Filter mode + @"FBM[16]": u1, + /// (18/28 of FBM) Filter mode + @"FBM[17]": u1, + /// (19/28 of FBM) Filter mode + @"FBM[18]": u1, + /// (20/28 of FBM) Filter mode + @"FBM[19]": u1, + /// (21/28 of FBM) Filter mode + @"FBM[20]": u1, + /// (22/28 of FBM) Filter mode + @"FBM[21]": u1, + /// (23/28 of FBM) Filter mode + @"FBM[22]": u1, + /// (24/28 of FBM) Filter mode + @"FBM[23]": u1, + /// (25/28 of FBM) Filter mode + @"FBM[24]": u1, + /// (26/28 of FBM) Filter mode + @"FBM[25]": u1, + /// (27/28 of FBM) Filter mode + @"FBM[26]": u1, + /// (28/28 of FBM) Filter mode + @"FBM[27]": u1, + padding: u4, }), reserved524: [4]u8, /// filter scale register FS1R: mmio.Mmio(packed struct(u32) { - /// Filter scale configuration - FSC: u1, - padding: u31, + /// (1/28 of FSC) Filter scale configuration + @"FSC[0]": u1, + /// (2/28 of FSC) Filter scale configuration + @"FSC[1]": u1, + /// (3/28 of FSC) Filter scale configuration + @"FSC[2]": u1, + /// (4/28 of FSC) Filter scale configuration + @"FSC[3]": u1, + /// (5/28 of FSC) Filter scale configuration + @"FSC[4]": u1, + /// (6/28 of FSC) Filter scale configuration + @"FSC[5]": u1, + /// (7/28 of FSC) Filter scale configuration + @"FSC[6]": u1, + /// (8/28 of FSC) Filter scale configuration + @"FSC[7]": u1, + /// (9/28 of FSC) Filter scale configuration + @"FSC[8]": u1, + /// (10/28 of FSC) Filter scale configuration + @"FSC[9]": u1, + /// (11/28 of FSC) Filter scale configuration + @"FSC[10]": u1, + /// (12/28 of FSC) Filter scale configuration + @"FSC[11]": u1, + /// (13/28 of FSC) Filter scale configuration + @"FSC[12]": u1, + /// (14/28 of FSC) Filter scale configuration + @"FSC[13]": u1, + /// (15/28 of FSC) Filter scale configuration + @"FSC[14]": u1, + /// (16/28 of FSC) Filter scale configuration + @"FSC[15]": u1, + /// (17/28 of FSC) Filter scale configuration + @"FSC[16]": u1, + /// (18/28 of FSC) Filter scale configuration + @"FSC[17]": u1, + /// (19/28 of FSC) Filter scale configuration + @"FSC[18]": u1, + /// (20/28 of FSC) Filter scale configuration + @"FSC[19]": u1, + /// (21/28 of FSC) Filter scale configuration + @"FSC[20]": u1, + /// (22/28 of FSC) Filter scale configuration + @"FSC[21]": u1, + /// (23/28 of FSC) Filter scale configuration + @"FSC[22]": u1, + /// (24/28 of FSC) Filter scale configuration + @"FSC[23]": u1, + /// (25/28 of FSC) Filter scale configuration + @"FSC[24]": u1, + /// (26/28 of FSC) Filter scale configuration + @"FSC[25]": u1, + /// (27/28 of FSC) Filter scale configuration + @"FSC[26]": u1, + /// (28/28 of FSC) Filter scale configuration + @"FSC[27]": u1, + padding: u4, }), reserved532: [4]u8, /// filter FIFO assignment register FFA1R: mmio.Mmio(packed struct(u32) { - /// Filter FIFO assignment for filter 0 - FFA: u1, - padding: u31, + /// (1/28 of FFA) Filter FIFO assignment for filter 0 + @"FFA[0]": u1, + /// (2/28 of FFA) Filter FIFO assignment for filter 0 + @"FFA[1]": u1, + /// (3/28 of FFA) Filter FIFO assignment for filter 0 + @"FFA[2]": u1, + /// (4/28 of FFA) Filter FIFO assignment for filter 0 + @"FFA[3]": u1, + /// (5/28 of FFA) Filter FIFO assignment for filter 0 + @"FFA[4]": u1, + /// (6/28 of FFA) Filter FIFO assignment for filter 0 + @"FFA[5]": u1, + /// (7/28 of FFA) Filter FIFO assignment for filter 0 + @"FFA[6]": u1, + /// (8/28 of FFA) Filter FIFO assignment for filter 0 + @"FFA[7]": u1, + /// (9/28 of FFA) Filter FIFO assignment for filter 0 + @"FFA[8]": u1, + /// (10/28 of FFA) Filter FIFO assignment for filter 0 + @"FFA[9]": u1, + /// (11/28 of FFA) Filter FIFO assignment for filter 0 + @"FFA[10]": u1, + /// (12/28 of FFA) Filter FIFO assignment for filter 0 + @"FFA[11]": u1, + /// (13/28 of FFA) Filter FIFO assignment for filter 0 + @"FFA[12]": u1, + /// (14/28 of FFA) Filter FIFO assignment for filter 0 + @"FFA[13]": u1, + /// (15/28 of FFA) Filter FIFO assignment for filter 0 + @"FFA[14]": u1, + /// (16/28 of FFA) Filter FIFO assignment for filter 0 + @"FFA[15]": u1, + /// (17/28 of FFA) Filter FIFO assignment for filter 0 + @"FFA[16]": u1, + /// (18/28 of FFA) Filter FIFO assignment for filter 0 + @"FFA[17]": u1, + /// (19/28 of FFA) Filter FIFO assignment for filter 0 + @"FFA[18]": u1, + /// (20/28 of FFA) Filter FIFO assignment for filter 0 + @"FFA[19]": u1, + /// (21/28 of FFA) Filter FIFO assignment for filter 0 + @"FFA[20]": u1, + /// (22/28 of FFA) Filter FIFO assignment for filter 0 + @"FFA[21]": u1, + /// (23/28 of FFA) Filter FIFO assignment for filter 0 + @"FFA[22]": u1, + /// (24/28 of FFA) Filter FIFO assignment for filter 0 + @"FFA[23]": u1, + /// (25/28 of FFA) Filter FIFO assignment for filter 0 + @"FFA[24]": u1, + /// (26/28 of FFA) Filter FIFO assignment for filter 0 + @"FFA[25]": u1, + /// (27/28 of FFA) Filter FIFO assignment for filter 0 + @"FFA[26]": u1, + /// (28/28 of FFA) Filter FIFO assignment for filter 0 + @"FFA[27]": u1, + padding: u4, }), reserved540: [4]u8, /// filter activation register FA1R: mmio.Mmio(packed struct(u32) { - /// Filter active - FACT: u1, - padding: u31, + /// (1/28 of FACT) Filter active + @"FACT[0]": u1, + /// (2/28 of FACT) Filter active + @"FACT[1]": u1, + /// (3/28 of FACT) Filter active + @"FACT[2]": u1, + /// (4/28 of FACT) Filter active + @"FACT[3]": u1, + /// (5/28 of FACT) Filter active + @"FACT[4]": u1, + /// (6/28 of FACT) Filter active + @"FACT[5]": u1, + /// (7/28 of FACT) Filter active + @"FACT[6]": u1, + /// (8/28 of FACT) Filter active + @"FACT[7]": u1, + /// (9/28 of FACT) Filter active + @"FACT[8]": u1, + /// (10/28 of FACT) Filter active + @"FACT[9]": u1, + /// (11/28 of FACT) Filter active + @"FACT[10]": u1, + /// (12/28 of FACT) Filter active + @"FACT[11]": u1, + /// (13/28 of FACT) Filter active + @"FACT[12]": u1, + /// (14/28 of FACT) Filter active + @"FACT[13]": u1, + /// (15/28 of FACT) Filter active + @"FACT[14]": u1, + /// (16/28 of FACT) Filter active + @"FACT[15]": u1, + /// (17/28 of FACT) Filter active + @"FACT[16]": u1, + /// (18/28 of FACT) Filter active + @"FACT[17]": u1, + /// (19/28 of FACT) Filter active + @"FACT[18]": u1, + /// (20/28 of FACT) Filter active + @"FACT[19]": u1, + /// (21/28 of FACT) Filter active + @"FACT[20]": u1, + /// (22/28 of FACT) Filter active + @"FACT[21]": u1, + /// (23/28 of FACT) Filter active + @"FACT[22]": u1, + /// (24/28 of FACT) Filter active + @"FACT[23]": u1, + /// (25/28 of FACT) Filter active + @"FACT[24]": u1, + /// (26/28 of FACT) Filter active + @"FACT[25]": u1, + /// (27/28 of FACT) Filter active + @"FACT[26]": u1, + /// (28/28 of FACT) Filter active + @"FACT[27]": u1, + padding: u4, }), reserved576: [32]u8, /// CAN Filter Bank cluster @@ -312359,15 +313870,137 @@ pub const types = struct { pub const FB = extern struct { /// Filter bank 0 register 1 FR1: mmio.Mmio(packed struct(u32) { - /// Filter bits - FB: u1, - padding: u31, + /// (1/32 of FB) Filter bits + @"FB[0]": u1, + /// (2/32 of FB) Filter bits + @"FB[1]": u1, + /// (3/32 of FB) Filter bits + @"FB[2]": u1, + /// (4/32 of FB) Filter bits + @"FB[3]": u1, + /// (5/32 of FB) Filter bits + @"FB[4]": u1, + /// (6/32 of FB) Filter bits + @"FB[5]": u1, + /// (7/32 of FB) Filter bits + @"FB[6]": u1, + /// (8/32 of FB) Filter bits + @"FB[7]": u1, + /// (9/32 of FB) Filter bits + @"FB[8]": u1, + /// (10/32 of FB) Filter bits + @"FB[9]": u1, + /// (11/32 of FB) Filter bits + @"FB[10]": u1, + /// (12/32 of FB) Filter bits + @"FB[11]": u1, + /// (13/32 of FB) Filter bits + @"FB[12]": u1, + /// (14/32 of FB) Filter bits + @"FB[13]": u1, + /// (15/32 of FB) Filter bits + @"FB[14]": u1, + /// (16/32 of FB) Filter bits + @"FB[15]": u1, + /// (17/32 of FB) Filter bits + @"FB[16]": u1, + /// (18/32 of FB) Filter bits + @"FB[17]": u1, + /// (19/32 of FB) Filter bits + @"FB[18]": u1, + /// (20/32 of FB) Filter bits + @"FB[19]": u1, + /// (21/32 of FB) Filter bits + @"FB[20]": u1, + /// (22/32 of FB) Filter bits + @"FB[21]": u1, + /// (23/32 of FB) Filter bits + @"FB[22]": u1, + /// (24/32 of FB) Filter bits + @"FB[23]": u1, + /// (25/32 of FB) Filter bits + @"FB[24]": u1, + /// (26/32 of FB) Filter bits + @"FB[25]": u1, + /// (27/32 of FB) Filter bits + @"FB[26]": u1, + /// (28/32 of FB) Filter bits + @"FB[27]": u1, + /// (29/32 of FB) Filter bits + @"FB[28]": u1, + /// (30/32 of FB) Filter bits + @"FB[29]": u1, + /// (31/32 of FB) Filter bits + @"FB[30]": u1, + /// (32/32 of FB) Filter bits + @"FB[31]": u1, }), /// Filter bank 0 register 2 FR2: mmio.Mmio(packed struct(u32) { - /// Filter bits - FB: u1, - padding: u31, + /// (1/32 of FB) Filter bits + @"FB[0]": u1, + /// (2/32 of FB) Filter bits + @"FB[1]": u1, + /// (3/32 of FB) Filter bits + @"FB[2]": u1, + /// (4/32 of FB) Filter bits + @"FB[3]": u1, + /// (5/32 of FB) Filter bits + @"FB[4]": u1, + /// (6/32 of FB) Filter bits + @"FB[5]": u1, + /// (7/32 of FB) Filter bits + @"FB[6]": u1, + /// (8/32 of FB) Filter bits + @"FB[7]": u1, + /// (9/32 of FB) Filter bits + @"FB[8]": u1, + /// (10/32 of FB) Filter bits + @"FB[9]": u1, + /// (11/32 of FB) Filter bits + @"FB[10]": u1, + /// (12/32 of FB) Filter bits + @"FB[11]": u1, + /// (13/32 of FB) Filter bits + @"FB[12]": u1, + /// (14/32 of FB) Filter bits + @"FB[13]": u1, + /// (15/32 of FB) Filter bits + @"FB[14]": u1, + /// (16/32 of FB) Filter bits + @"FB[15]": u1, + /// (17/32 of FB) Filter bits + @"FB[16]": u1, + /// (18/32 of FB) Filter bits + @"FB[17]": u1, + /// (19/32 of FB) Filter bits + @"FB[18]": u1, + /// (20/32 of FB) Filter bits + @"FB[19]": u1, + /// (21/32 of FB) Filter bits + @"FB[20]": u1, + /// (22/32 of FB) Filter bits + @"FB[21]": u1, + /// (23/32 of FB) Filter bits + @"FB[22]": u1, + /// (24/32 of FB) Filter bits + @"FB[23]": u1, + /// (25/32 of FB) Filter bits + @"FB[24]": u1, + /// (26/32 of FB) Filter bits + @"FB[25]": u1, + /// (27/32 of FB) Filter bits + @"FB[26]": u1, + /// (28/32 of FB) Filter bits + @"FB[27]": u1, + /// (29/32 of FB) Filter bits + @"FB[28]": u1, + /// (30/32 of FB) Filter bits + @"FB[29]": u1, + /// (31/32 of FB) Filter bits + @"FB[30]": u1, + /// (32/32 of FB) Filter bits + @"FB[31]": u1, }), }; @@ -312397,15 +314030,25 @@ pub const types = struct { }), /// mailbox data high register RDLR: mmio.Mmio(packed struct(u32) { - /// DATA0 - DATA: u8, - padding: u24, + /// (1/4 of DATA) DATA0 + @"DATA[0]": u8, + /// (2/4 of DATA) DATA0 + @"DATA[1]": u8, + /// (3/4 of DATA) DATA0 + @"DATA[2]": u8, + /// (4/4 of DATA) DATA0 + @"DATA[3]": u8, }), /// receive FIFO mailbox data high register RDHR: mmio.Mmio(packed struct(u32) { - /// DATA4 - DATA: u8, - padding: u24, + /// (1/4 of DATA) DATA4 + @"DATA[0]": u8, + /// (2/4 of DATA) DATA4 + @"DATA[1]": u8, + /// (3/4 of DATA) DATA4 + @"DATA[2]": u8, + /// (4/4 of DATA) DATA4 + @"DATA[3]": u8, }), }; @@ -312437,15 +314080,25 @@ pub const types = struct { }), /// mailbox data low register TDLR: mmio.Mmio(packed struct(u32) { - /// DATA0 - DATA: u8, - padding: u24, + /// (1/4 of DATA) DATA0 + @"DATA[0]": u8, + /// (2/4 of DATA) DATA0 + @"DATA[1]": u8, + /// (3/4 of DATA) DATA0 + @"DATA[2]": u8, + /// (4/4 of DATA) DATA0 + @"DATA[3]": u8, }), /// mailbox data high register TDHR: mmio.Mmio(packed struct(u32) { - /// DATA4 - DATA: u8, - padding: u24, + /// (1/4 of DATA) DATA4 + @"DATA[0]": u8, + /// (2/4 of DATA) DATA4 + @"DATA[1]": u8, + /// (3/4 of DATA) DATA4 + @"DATA[2]": u8, + /// (4/4 of DATA) DATA4 + @"DATA[3]": u8, }), }; }; @@ -312967,45 +314620,472 @@ pub const types = struct { }), /// FDCAN Tx Buffer Request Pending Register TXBRP: mmio.Mmio(packed struct(u32) { - /// Transmission Request Pending - TRP: u1, - padding: u31, + /// (1/32 of TRP) Transmission Request Pending + @"TRP[0]": u1, + /// (2/32 of TRP) Transmission Request Pending + @"TRP[1]": u1, + /// (3/32 of TRP) Transmission Request Pending + @"TRP[2]": u1, + /// (4/32 of TRP) Transmission Request Pending + @"TRP[3]": u1, + /// (5/32 of TRP) Transmission Request Pending + @"TRP[4]": u1, + /// (6/32 of TRP) Transmission Request Pending + @"TRP[5]": u1, + /// (7/32 of TRP) Transmission Request Pending + @"TRP[6]": u1, + /// (8/32 of TRP) Transmission Request Pending + @"TRP[7]": u1, + /// (9/32 of TRP) Transmission Request Pending + @"TRP[8]": u1, + /// (10/32 of TRP) Transmission Request Pending + @"TRP[9]": u1, + /// (11/32 of TRP) Transmission Request Pending + @"TRP[10]": u1, + /// (12/32 of TRP) Transmission Request Pending + @"TRP[11]": u1, + /// (13/32 of TRP) Transmission Request Pending + @"TRP[12]": u1, + /// (14/32 of TRP) Transmission Request Pending + @"TRP[13]": u1, + /// (15/32 of TRP) Transmission Request Pending + @"TRP[14]": u1, + /// (16/32 of TRP) Transmission Request Pending + @"TRP[15]": u1, + /// (17/32 of TRP) Transmission Request Pending + @"TRP[16]": u1, + /// (18/32 of TRP) Transmission Request Pending + @"TRP[17]": u1, + /// (19/32 of TRP) Transmission Request Pending + @"TRP[18]": u1, + /// (20/32 of TRP) Transmission Request Pending + @"TRP[19]": u1, + /// (21/32 of TRP) Transmission Request Pending + @"TRP[20]": u1, + /// (22/32 of TRP) Transmission Request Pending + @"TRP[21]": u1, + /// (23/32 of TRP) Transmission Request Pending + @"TRP[22]": u1, + /// (24/32 of TRP) Transmission Request Pending + @"TRP[23]": u1, + /// (25/32 of TRP) Transmission Request Pending + @"TRP[24]": u1, + /// (26/32 of TRP) Transmission Request Pending + @"TRP[25]": u1, + /// (27/32 of TRP) Transmission Request Pending + @"TRP[26]": u1, + /// (28/32 of TRP) Transmission Request Pending + @"TRP[27]": u1, + /// (29/32 of TRP) Transmission Request Pending + @"TRP[28]": u1, + /// (30/32 of TRP) Transmission Request Pending + @"TRP[29]": u1, + /// (31/32 of TRP) Transmission Request Pending + @"TRP[30]": u1, + /// (32/32 of TRP) Transmission Request Pending + @"TRP[31]": u1, }), /// FDCAN Tx Buffer Add Request Register TXBAR: mmio.Mmio(packed struct(u32) { - /// Add Request - AR: u1, - padding: u31, + /// (1/32 of AR) Add Request + @"AR[0]": u1, + /// (2/32 of AR) Add Request + @"AR[1]": u1, + /// (3/32 of AR) Add Request + @"AR[2]": u1, + /// (4/32 of AR) Add Request + @"AR[3]": u1, + /// (5/32 of AR) Add Request + @"AR[4]": u1, + /// (6/32 of AR) Add Request + @"AR[5]": u1, + /// (7/32 of AR) Add Request + @"AR[6]": u1, + /// (8/32 of AR) Add Request + @"AR[7]": u1, + /// (9/32 of AR) Add Request + @"AR[8]": u1, + /// (10/32 of AR) Add Request + @"AR[9]": u1, + /// (11/32 of AR) Add Request + @"AR[10]": u1, + /// (12/32 of AR) Add Request + @"AR[11]": u1, + /// (13/32 of AR) Add Request + @"AR[12]": u1, + /// (14/32 of AR) Add Request + @"AR[13]": u1, + /// (15/32 of AR) Add Request + @"AR[14]": u1, + /// (16/32 of AR) Add Request + @"AR[15]": u1, + /// (17/32 of AR) Add Request + @"AR[16]": u1, + /// (18/32 of AR) Add Request + @"AR[17]": u1, + /// (19/32 of AR) Add Request + @"AR[18]": u1, + /// (20/32 of AR) Add Request + @"AR[19]": u1, + /// (21/32 of AR) Add Request + @"AR[20]": u1, + /// (22/32 of AR) Add Request + @"AR[21]": u1, + /// (23/32 of AR) Add Request + @"AR[22]": u1, + /// (24/32 of AR) Add Request + @"AR[23]": u1, + /// (25/32 of AR) Add Request + @"AR[24]": u1, + /// (26/32 of AR) Add Request + @"AR[25]": u1, + /// (27/32 of AR) Add Request + @"AR[26]": u1, + /// (28/32 of AR) Add Request + @"AR[27]": u1, + /// (29/32 of AR) Add Request + @"AR[28]": u1, + /// (30/32 of AR) Add Request + @"AR[29]": u1, + /// (31/32 of AR) Add Request + @"AR[30]": u1, + /// (32/32 of AR) Add Request + @"AR[31]": u1, }), /// FDCAN Tx Buffer Cancellation Request Register TXBCR: mmio.Mmio(packed struct(u32) { - /// Cancellation Request - CR: u1, - padding: u31, + /// (1/32 of CR) Cancellation Request + @"CR[0]": u1, + /// (2/32 of CR) Cancellation Request + @"CR[1]": u1, + /// (3/32 of CR) Cancellation Request + @"CR[2]": u1, + /// (4/32 of CR) Cancellation Request + @"CR[3]": u1, + /// (5/32 of CR) Cancellation Request + @"CR[4]": u1, + /// (6/32 of CR) Cancellation Request + @"CR[5]": u1, + /// (7/32 of CR) Cancellation Request + @"CR[6]": u1, + /// (8/32 of CR) Cancellation Request + @"CR[7]": u1, + /// (9/32 of CR) Cancellation Request + @"CR[8]": u1, + /// (10/32 of CR) Cancellation Request + @"CR[9]": u1, + /// (11/32 of CR) Cancellation Request + @"CR[10]": u1, + /// (12/32 of CR) Cancellation Request + @"CR[11]": u1, + /// (13/32 of CR) Cancellation Request + @"CR[12]": u1, + /// (14/32 of CR) Cancellation Request + @"CR[13]": u1, + /// (15/32 of CR) Cancellation Request + @"CR[14]": u1, + /// (16/32 of CR) Cancellation Request + @"CR[15]": u1, + /// (17/32 of CR) Cancellation Request + @"CR[16]": u1, + /// (18/32 of CR) Cancellation Request + @"CR[17]": u1, + /// (19/32 of CR) Cancellation Request + @"CR[18]": u1, + /// (20/32 of CR) Cancellation Request + @"CR[19]": u1, + /// (21/32 of CR) Cancellation Request + @"CR[20]": u1, + /// (22/32 of CR) Cancellation Request + @"CR[21]": u1, + /// (23/32 of CR) Cancellation Request + @"CR[22]": u1, + /// (24/32 of CR) Cancellation Request + @"CR[23]": u1, + /// (25/32 of CR) Cancellation Request + @"CR[24]": u1, + /// (26/32 of CR) Cancellation Request + @"CR[25]": u1, + /// (27/32 of CR) Cancellation Request + @"CR[26]": u1, + /// (28/32 of CR) Cancellation Request + @"CR[27]": u1, + /// (29/32 of CR) Cancellation Request + @"CR[28]": u1, + /// (30/32 of CR) Cancellation Request + @"CR[29]": u1, + /// (31/32 of CR) Cancellation Request + @"CR[30]": u1, + /// (32/32 of CR) Cancellation Request + @"CR[31]": u1, }), /// FDCAN Tx Buffer Transmission Occurred Register TXBTO: mmio.Mmio(packed struct(u32) { - /// Transmission Occurred - TO: u1, - padding: u31, + /// (1/32 of TO) Transmission Occurred + @"TO[0]": u1, + /// (2/32 of TO) Transmission Occurred + @"TO[1]": u1, + /// (3/32 of TO) Transmission Occurred + @"TO[2]": u1, + /// (4/32 of TO) Transmission Occurred + @"TO[3]": u1, + /// (5/32 of TO) Transmission Occurred + @"TO[4]": u1, + /// (6/32 of TO) Transmission Occurred + @"TO[5]": u1, + /// (7/32 of TO) Transmission Occurred + @"TO[6]": u1, + /// (8/32 of TO) Transmission Occurred + @"TO[7]": u1, + /// (9/32 of TO) Transmission Occurred + @"TO[8]": u1, + /// (10/32 of TO) Transmission Occurred + @"TO[9]": u1, + /// (11/32 of TO) Transmission Occurred + @"TO[10]": u1, + /// (12/32 of TO) Transmission Occurred + @"TO[11]": u1, + /// (13/32 of TO) Transmission Occurred + @"TO[12]": u1, + /// (14/32 of TO) Transmission Occurred + @"TO[13]": u1, + /// (15/32 of TO) Transmission Occurred + @"TO[14]": u1, + /// (16/32 of TO) Transmission Occurred + @"TO[15]": u1, + /// (17/32 of TO) Transmission Occurred + @"TO[16]": u1, + /// (18/32 of TO) Transmission Occurred + @"TO[17]": u1, + /// (19/32 of TO) Transmission Occurred + @"TO[18]": u1, + /// (20/32 of TO) Transmission Occurred + @"TO[19]": u1, + /// (21/32 of TO) Transmission Occurred + @"TO[20]": u1, + /// (22/32 of TO) Transmission Occurred + @"TO[21]": u1, + /// (23/32 of TO) Transmission Occurred + @"TO[22]": u1, + /// (24/32 of TO) Transmission Occurred + @"TO[23]": u1, + /// (25/32 of TO) Transmission Occurred + @"TO[24]": u1, + /// (26/32 of TO) Transmission Occurred + @"TO[25]": u1, + /// (27/32 of TO) Transmission Occurred + @"TO[26]": u1, + /// (28/32 of TO) Transmission Occurred + @"TO[27]": u1, + /// (29/32 of TO) Transmission Occurred + @"TO[28]": u1, + /// (30/32 of TO) Transmission Occurred + @"TO[29]": u1, + /// (31/32 of TO) Transmission Occurred + @"TO[30]": u1, + /// (32/32 of TO) Transmission Occurred + @"TO[31]": u1, }), /// FDCAN Tx Buffer Cancellation Finished Register TXBCF: mmio.Mmio(packed struct(u32) { - /// Cancellation Finished - CF: u1, - padding: u31, + /// (1/32 of CF) Cancellation Finished + @"CF[0]": u1, + /// (2/32 of CF) Cancellation Finished + @"CF[1]": u1, + /// (3/32 of CF) Cancellation Finished + @"CF[2]": u1, + /// (4/32 of CF) Cancellation Finished + @"CF[3]": u1, + /// (5/32 of CF) Cancellation Finished + @"CF[4]": u1, + /// (6/32 of CF) Cancellation Finished + @"CF[5]": u1, + /// (7/32 of CF) Cancellation Finished + @"CF[6]": u1, + /// (8/32 of CF) Cancellation Finished + @"CF[7]": u1, + /// (9/32 of CF) Cancellation Finished + @"CF[8]": u1, + /// (10/32 of CF) Cancellation Finished + @"CF[9]": u1, + /// (11/32 of CF) Cancellation Finished + @"CF[10]": u1, + /// (12/32 of CF) Cancellation Finished + @"CF[11]": u1, + /// (13/32 of CF) Cancellation Finished + @"CF[12]": u1, + /// (14/32 of CF) Cancellation Finished + @"CF[13]": u1, + /// (15/32 of CF) Cancellation Finished + @"CF[14]": u1, + /// (16/32 of CF) Cancellation Finished + @"CF[15]": u1, + /// (17/32 of CF) Cancellation Finished + @"CF[16]": u1, + /// (18/32 of CF) Cancellation Finished + @"CF[17]": u1, + /// (19/32 of CF) Cancellation Finished + @"CF[18]": u1, + /// (20/32 of CF) Cancellation Finished + @"CF[19]": u1, + /// (21/32 of CF) Cancellation Finished + @"CF[20]": u1, + /// (22/32 of CF) Cancellation Finished + @"CF[21]": u1, + /// (23/32 of CF) Cancellation Finished + @"CF[22]": u1, + /// (24/32 of CF) Cancellation Finished + @"CF[23]": u1, + /// (25/32 of CF) Cancellation Finished + @"CF[24]": u1, + /// (26/32 of CF) Cancellation Finished + @"CF[25]": u1, + /// (27/32 of CF) Cancellation Finished + @"CF[26]": u1, + /// (28/32 of CF) Cancellation Finished + @"CF[27]": u1, + /// (29/32 of CF) Cancellation Finished + @"CF[28]": u1, + /// (30/32 of CF) Cancellation Finished + @"CF[29]": u1, + /// (31/32 of CF) Cancellation Finished + @"CF[30]": u1, + /// (32/32 of CF) Cancellation Finished + @"CF[31]": u1, }), /// FDCAN Tx Buffer Transmission Interrupt Enable Register TXBTIE: mmio.Mmio(packed struct(u32) { - /// Transmission Interrupt Enable - TIE: u1, - padding: u31, + /// (1/32 of TIE) Transmission Interrupt Enable + @"TIE[0]": u1, + /// (2/32 of TIE) Transmission Interrupt Enable + @"TIE[1]": u1, + /// (3/32 of TIE) Transmission Interrupt Enable + @"TIE[2]": u1, + /// (4/32 of TIE) Transmission Interrupt Enable + @"TIE[3]": u1, + /// (5/32 of TIE) Transmission Interrupt Enable + @"TIE[4]": u1, + /// (6/32 of TIE) Transmission Interrupt Enable + @"TIE[5]": u1, + /// (7/32 of TIE) Transmission Interrupt Enable + @"TIE[6]": u1, + /// (8/32 of TIE) Transmission Interrupt Enable + @"TIE[7]": u1, + /// (9/32 of TIE) Transmission Interrupt Enable + @"TIE[8]": u1, + /// (10/32 of TIE) Transmission Interrupt Enable + @"TIE[9]": u1, + /// (11/32 of TIE) Transmission Interrupt Enable + @"TIE[10]": u1, + /// (12/32 of TIE) Transmission Interrupt Enable + @"TIE[11]": u1, + /// (13/32 of TIE) Transmission Interrupt Enable + @"TIE[12]": u1, + /// (14/32 of TIE) Transmission Interrupt Enable + @"TIE[13]": u1, + /// (15/32 of TIE) Transmission Interrupt Enable + @"TIE[14]": u1, + /// (16/32 of TIE) Transmission Interrupt Enable + @"TIE[15]": u1, + /// (17/32 of TIE) Transmission Interrupt Enable + @"TIE[16]": u1, + /// (18/32 of TIE) Transmission Interrupt Enable + @"TIE[17]": u1, + /// (19/32 of TIE) Transmission Interrupt Enable + @"TIE[18]": u1, + /// (20/32 of TIE) Transmission Interrupt Enable + @"TIE[19]": u1, + /// (21/32 of TIE) Transmission Interrupt Enable + @"TIE[20]": u1, + /// (22/32 of TIE) Transmission Interrupt Enable + @"TIE[21]": u1, + /// (23/32 of TIE) Transmission Interrupt Enable + @"TIE[22]": u1, + /// (24/32 of TIE) Transmission Interrupt Enable + @"TIE[23]": u1, + /// (25/32 of TIE) Transmission Interrupt Enable + @"TIE[24]": u1, + /// (26/32 of TIE) Transmission Interrupt Enable + @"TIE[25]": u1, + /// (27/32 of TIE) Transmission Interrupt Enable + @"TIE[26]": u1, + /// (28/32 of TIE) Transmission Interrupt Enable + @"TIE[27]": u1, + /// (29/32 of TIE) Transmission Interrupt Enable + @"TIE[28]": u1, + /// (30/32 of TIE) Transmission Interrupt Enable + @"TIE[29]": u1, + /// (31/32 of TIE) Transmission Interrupt Enable + @"TIE[30]": u1, + /// (32/32 of TIE) Transmission Interrupt Enable + @"TIE[31]": u1, }), /// FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register TXBCIE: mmio.Mmio(packed struct(u32) { - /// Cancellation Finished Interrupt Enable - CF: u1, - padding: u31, + /// (1/32 of CF) Cancellation Finished Interrupt Enable + @"CF[0]": u1, + /// (2/32 of CF) Cancellation Finished Interrupt Enable + @"CF[1]": u1, + /// (3/32 of CF) Cancellation Finished Interrupt Enable + @"CF[2]": u1, + /// (4/32 of CF) Cancellation Finished Interrupt Enable + @"CF[3]": u1, + /// (5/32 of CF) Cancellation Finished Interrupt Enable + @"CF[4]": u1, + /// (6/32 of CF) Cancellation Finished Interrupt Enable + @"CF[5]": u1, + /// (7/32 of CF) Cancellation Finished Interrupt Enable + @"CF[6]": u1, + /// (8/32 of CF) Cancellation Finished Interrupt Enable + @"CF[7]": u1, + /// (9/32 of CF) Cancellation Finished Interrupt Enable + @"CF[8]": u1, + /// (10/32 of CF) Cancellation Finished Interrupt Enable + @"CF[9]": u1, + /// (11/32 of CF) Cancellation Finished Interrupt Enable + @"CF[10]": u1, + /// (12/32 of CF) Cancellation Finished Interrupt Enable + @"CF[11]": u1, + /// (13/32 of CF) Cancellation Finished Interrupt Enable + @"CF[12]": u1, + /// (14/32 of CF) Cancellation Finished Interrupt Enable + @"CF[13]": u1, + /// (15/32 of CF) Cancellation Finished Interrupt Enable + @"CF[14]": u1, + /// (16/32 of CF) Cancellation Finished Interrupt Enable + @"CF[15]": u1, + /// (17/32 of CF) Cancellation Finished Interrupt Enable + @"CF[16]": u1, + /// (18/32 of CF) Cancellation Finished Interrupt Enable + @"CF[17]": u1, + /// (19/32 of CF) Cancellation Finished Interrupt Enable + @"CF[18]": u1, + /// (20/32 of CF) Cancellation Finished Interrupt Enable + @"CF[19]": u1, + /// (21/32 of CF) Cancellation Finished Interrupt Enable + @"CF[20]": u1, + /// (22/32 of CF) Cancellation Finished Interrupt Enable + @"CF[21]": u1, + /// (23/32 of CF) Cancellation Finished Interrupt Enable + @"CF[22]": u1, + /// (24/32 of CF) Cancellation Finished Interrupt Enable + @"CF[23]": u1, + /// (25/32 of CF) Cancellation Finished Interrupt Enable + @"CF[24]": u1, + /// (26/32 of CF) Cancellation Finished Interrupt Enable + @"CF[25]": u1, + /// (27/32 of CF) Cancellation Finished Interrupt Enable + @"CF[26]": u1, + /// (28/32 of CF) Cancellation Finished Interrupt Enable + @"CF[27]": u1, + /// (29/32 of CF) Cancellation Finished Interrupt Enable + @"CF[28]": u1, + /// (30/32 of CF) Cancellation Finished Interrupt Enable + @"CF[29]": u1, + /// (31/32 of CF) Cancellation Finished Interrupt Enable + @"CF[30]": u1, + /// (32/32 of CF) Cancellation Finished Interrupt Enable + @"CF[31]": u1, }), reserved240: [8]u8, /// FDCAN Tx Event FIFO Configuration Register @@ -313781,9 +315861,10 @@ pub const types = struct { }), /// FDCAN interrupt line select register ILS: mmio.Mmio(packed struct(u32) { - /// RX FIFO bit grouping the following interruption. RFLL: Rx FIFO X message lost interrupt line RFFL: Rx FIFO X full interrupt line RFNL: Rx FIFO X new message interrupt line. - RXFIFO: u1, - reserved2: u1, + /// (1/2 of RXFIFO) RX FIFO bit grouping the following interruption. RFLL: Rx FIFO X message lost interrupt line RFFL: Rx FIFO X full interrupt line RFNL: Rx FIFO X new message interrupt line. + @"RXFIFO[0]": u1, + /// (2/2 of RXFIFO) RX FIFO bit grouping the following interruption. RFLL: Rx FIFO X message lost interrupt line RFFL: Rx FIFO X full interrupt line RFNL: Rx FIFO X new message interrupt line. + @"RXFIFO[1]": u1, /// Status message bit grouping the following interruption. TCFL: Transmission cancellation finished interrupt line TCL: Transmission completed interrupt line HPML: High-priority message interrupt line. SMSG: u1, /// Tx FIFO ERROR grouping the following interruption. TEFLL: Tx event FIFO element lost interrupt line TEFFL: Tx event FIFO full interrupt line TEFNL: Tx event FIFO new entry interrupt line TFEL: Tx FIFO empty interrupt line. @@ -313897,45 +315978,73 @@ pub const types = struct { }), /// FDCAN Tx buffer request pending register TXBRP: mmio.Mmio(packed struct(u32) { - /// Transmission request pending. Each Tx buffer has its own transmission request pending bit. The bits are set via register TXBAR. The bits are reset after a requested transmission has completed or has been canceled via register TXBCR. After a TXBRP bit has been set, a Tx scan is started to check for the pending Tx request with the highest priority (Tx buffer with lowest Message ID). A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. After a cancellation has been requested, a finished cancellation is signaled via TXBCF after successful transmission together with the corresponding TXBTO bit when the transmission has not yet been started at the point of cancellation when the transmission has been aborted due to lost arbitration when an error occurred during frame transmission In DAR mode all transmissions are automatically canceled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions - TRP: u1, - padding: u31, + /// (1/3 of TRP) Transmission request pending. Each Tx buffer has its own transmission request pending bit. The bits are set via register TXBAR. The bits are reset after a requested transmission has completed or has been canceled via register TXBCR. After a TXBRP bit has been set, a Tx scan is started to check for the pending Tx request with the highest priority (Tx buffer with lowest Message ID). A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. After a cancellation has been requested, a finished cancellation is signaled via TXBCF after successful transmission together with the corresponding TXBTO bit when the transmission has not yet been started at the point of cancellation when the transmission has been aborted due to lost arbitration when an error occurred during frame transmission In DAR mode all transmissions are automatically canceled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions + @"TRP[0]": u1, + /// (2/3 of TRP) Transmission request pending. Each Tx buffer has its own transmission request pending bit. The bits are set via register TXBAR. The bits are reset after a requested transmission has completed or has been canceled via register TXBCR. After a TXBRP bit has been set, a Tx scan is started to check for the pending Tx request with the highest priority (Tx buffer with lowest Message ID). A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. After a cancellation has been requested, a finished cancellation is signaled via TXBCF after successful transmission together with the corresponding TXBTO bit when the transmission has not yet been started at the point of cancellation when the transmission has been aborted due to lost arbitration when an error occurred during frame transmission In DAR mode all transmissions are automatically canceled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions + @"TRP[1]": u1, + /// (3/3 of TRP) Transmission request pending. Each Tx buffer has its own transmission request pending bit. The bits are set via register TXBAR. The bits are reset after a requested transmission has completed or has been canceled via register TXBCR. After a TXBRP bit has been set, a Tx scan is started to check for the pending Tx request with the highest priority (Tx buffer with lowest Message ID). A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. After a cancellation has been requested, a finished cancellation is signaled via TXBCF after successful transmission together with the corresponding TXBTO bit when the transmission has not yet been started at the point of cancellation when the transmission has been aborted due to lost arbitration when an error occurred during frame transmission In DAR mode all transmissions are automatically canceled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions + @"TRP[2]": u1, + padding: u29, }), /// FDCAN Tx buffer add request register TXBAR: mmio.Mmio(packed struct(u32) { - /// Add request. Each Tx buffer has its own add request bit. Writing a 1 sets the corresponding add request bit; writing a 0 has no impact. This enables the Host to set transmission requests for multiple Tx buffers with one write to TXBAR. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed - AR: u1, - padding: u31, + /// (1/3 of AR) Add request. Each Tx buffer has its own add request bit. Writing a 1 sets the corresponding add request bit; writing a 0 has no impact. This enables the Host to set transmission requests for multiple Tx buffers with one write to TXBAR. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed + @"AR[0]": u1, + /// (2/3 of AR) Add request. Each Tx buffer has its own add request bit. Writing a 1 sets the corresponding add request bit; writing a 0 has no impact. This enables the Host to set transmission requests for multiple Tx buffers with one write to TXBAR. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed + @"AR[1]": u1, + /// (3/3 of AR) Add request. Each Tx buffer has its own add request bit. Writing a 1 sets the corresponding add request bit; writing a 0 has no impact. This enables the Host to set transmission requests for multiple Tx buffers with one write to TXBAR. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed + @"AR[2]": u1, + padding: u29, }), /// FDCAN Tx buffer cancellation request register TXBCR: mmio.Mmio(packed struct(u32) { - /// Cancellation request. Each Tx buffer has its own cancellation request bit. Writing a 1 sets the corresponding CR bit; writing a 0 has no impact. This enables the Host to set cancellation requests for multiple Tx buffers with one write to TXBCR. The bits remain set until the corresponding TXBRP bit is reset - CR: u1, - padding: u31, + /// (1/3 of CR) Cancellation request. Each Tx buffer has its own cancellation request bit. Writing a 1 sets the corresponding CR bit; writing a 0 has no impact. This enables the Host to set cancellation requests for multiple Tx buffers with one write to TXBCR. The bits remain set until the corresponding TXBRP bit is reset + @"CR[0]": u1, + /// (2/3 of CR) Cancellation request. Each Tx buffer has its own cancellation request bit. Writing a 1 sets the corresponding CR bit; writing a 0 has no impact. This enables the Host to set cancellation requests for multiple Tx buffers with one write to TXBCR. The bits remain set until the corresponding TXBRP bit is reset + @"CR[1]": u1, + /// (3/3 of CR) Cancellation request. Each Tx buffer has its own cancellation request bit. Writing a 1 sets the corresponding CR bit; writing a 0 has no impact. This enables the Host to set cancellation requests for multiple Tx buffers with one write to TXBCR. The bits remain set until the corresponding TXBRP bit is reset + @"CR[2]": u1, + padding: u29, }), /// FDCAN Tx buffer transmission occurred register TXBTO: mmio.Mmio(packed struct(u32) { - /// Transmission occurred.. Each Tx buffer has its own TO bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register TXBAR - TO: u1, - padding: u31, + /// (1/3 of TO) Transmission occurred.. Each Tx buffer has its own TO bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register TXBAR + @"TO[0]": u1, + /// (2/3 of TO) Transmission occurred.. Each Tx buffer has its own TO bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register TXBAR + @"TO[1]": u1, + /// (3/3 of TO) Transmission occurred.. Each Tx buffer has its own TO bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register TXBAR + @"TO[2]": u1, + padding: u29, }), /// FDCAN Tx buffer cancellation finished register TXBCF: mmio.Mmio(packed struct(u32) { - /// Cancellation finished. Each Tx buffer has its own CF bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register TXBAR - CF: u1, - padding: u31, + /// (1/3 of CF) Cancellation finished. Each Tx buffer has its own CF bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register TXBAR + @"CF[0]": u1, + /// (2/3 of CF) Cancellation finished. Each Tx buffer has its own CF bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register TXBAR + @"CF[1]": u1, + /// (3/3 of CF) Cancellation finished. Each Tx buffer has its own CF bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register TXBAR + @"CF[2]": u1, + padding: u29, }), /// FDCAN Tx buffer transmission interrupt enable register TXBTIE: mmio.Mmio(packed struct(u32) { - /// Transmission interrupt enable. Each Tx buffer has its own TIE bit - TIE: u1, - padding: u31, + /// (1/3 of TIE) Transmission interrupt enable. Each Tx buffer has its own TIE bit + @"TIE[0]": u1, + /// (2/3 of TIE) Transmission interrupt enable. Each Tx buffer has its own TIE bit + @"TIE[1]": u1, + /// (3/3 of TIE) Transmission interrupt enable. Each Tx buffer has its own TIE bit + @"TIE[2]": u1, + padding: u29, }), /// FDCAN Tx buffer cancellation finished interrupt enable register TXBCIE: mmio.Mmio(packed struct(u32) { - /// Cancellation finished interrupt enable.. Each Tx buffer has its own CFIE bit - CFIE: u1, - padding: u31, + /// (1/3 of CFIE) Cancellation finished interrupt enable.. Each Tx buffer has its own CFIE bit + @"CFIE[0]": u1, + /// (2/3 of CFIE) Cancellation finished interrupt enable.. Each Tx buffer has its own CFIE bit + @"CFIE[1]": u1, + /// (3/3 of CFIE) Cancellation finished interrupt enable.. Each Tx buffer has its own CFIE bit + @"CFIE[2]": u1, + padding: u29, }), /// FDCAN Tx event FIFO status register TXEFS: mmio.Mmio(packed struct(u32) { @@ -314259,18 +316368,18 @@ pub const types = struct { pub const COMP = extern struct { /// Comparator status register. SR: mmio.Mmio(packed struct(u32) { - /// COMP Channel1 output status bit This bit is read-only. It reflects the current COMP Channel1 output taking into account POLARITY and BLANKING bits effect. - CVAL: u1, + /// (1/1 of CVAL) COMP Channel1 output status bit This bit is read-only. It reflects the current COMP Channel1 output taking into account POLARITY and BLANKING bits effect. + @"CVAL[0]": u1, reserved16: u15, - /// COMP Channel1 interrupt flag This bit is set by hardware when the COMP Channel1 output is set This bit is cleared by software writing 1 the CC1IF bit in the COMP_ICFR register. - CIF: u1, + /// (1/1 of CIF) COMP Channel1 interrupt flag This bit is set by hardware when the COMP Channel1 output is set This bit is cleared by software writing 1 the CC1IF bit in the COMP_ICFR register. + @"CIF[0]": u1, padding: u15, }), /// Comparator interrupt clear flag register. ICFR: mmio.Mmio(packed struct(u32) { reserved16: u16, - /// Clear COMP Channel1 interrupt flag Writing 1 clears the C1IF flag in the COMP_SR register. - CCIF: u1, + /// (1/1 of CCIF) Clear COMP Channel1 interrupt flag Writing 1 clears the C1IF flag in the COMP_SR register. + @"CCIF[0]": u1, padding: u15, }), reserved12: [4]u8, @@ -314373,19 +316482,25 @@ pub const types = struct { pub const COMP = extern struct { /// Comparator status register. SR: mmio.Mmio(packed struct(u32) { - /// COMP channel 1 output status bit. - CVAL: u1, - reserved16: u15, - /// COMP channel 1 Interrupt Flag. - CIF: u1, - padding: u15, + /// (1/2 of CVAL) COMP channel 1 output status bit. + @"CVAL[0]": u1, + /// (2/2 of CVAL) COMP channel 1 output status bit. + @"CVAL[1]": u1, + reserved16: u14, + /// (1/2 of CIF) COMP channel 1 Interrupt Flag. + @"CIF[0]": u1, + /// (2/2 of CIF) COMP channel 1 Interrupt Flag. + @"CIF[1]": u1, + padding: u14, }), /// Comparator interrupt clear flag register. ICFR: mmio.Mmio(packed struct(u32) { reserved16: u16, - /// Clear COMP channel 1 Interrupt Flag. - CCIF: u1, - padding: u15, + /// (1/2 of CCIF) Clear COMP channel 1 Interrupt Flag. + @"CCIF[0]": u1, + /// (2/2 of CCIF) Clear COMP channel 1 Interrupt Flag. + @"CCIF[1]": u1, + padding: u14, }), /// Comparator option register. OR: mmio.Mmio(packed struct(u32) { @@ -314484,19 +316599,25 @@ pub const types = struct { pub const COMP = extern struct { /// Comparator status register. SR: mmio.Mmio(packed struct(u32) { - /// COMP channel 1 output status bit. - CVAL: u1, - reserved16: u15, - /// COMP channel 1 Interrupt Flag. - CIF: u1, - padding: u15, + /// (1/2 of CVAL) COMP channel 1 output status bit. + @"CVAL[0]": u1, + /// (2/2 of CVAL) COMP channel 1 output status bit. + @"CVAL[1]": u1, + reserved16: u14, + /// (1/2 of CIF) COMP channel 1 Interrupt Flag. + @"CIF[0]": u1, + /// (2/2 of CIF) COMP channel 1 Interrupt Flag. + @"CIF[1]": u1, + padding: u14, }), /// Comparator interrupt clear flag register. ICFR: mmio.Mmio(packed struct(u32) { reserved16: u16, - /// Clear COMP channel 1 Interrupt Flag. - CCIF: u1, - padding: u15, + /// (1/2 of CCIF) Clear COMP channel 1 Interrupt Flag. + @"CCIF[0]": u1, + /// (2/2 of CCIF) Clear COMP channel 1 Interrupt Flag. + @"CCIF[1]": u1, + padding: u14, }), /// Comparator option register. OR: mmio.Mmio(packed struct(u32) { @@ -315726,27 +317847,44 @@ pub const types = struct { pub const DAC = extern struct { /// control register CR: mmio.Mmio(packed struct(u32) { - /// channel enable - EN: u1, - /// channel output buffer disable - BOFF: u1, - /// channel trigger enable - TEN: u1, - /// channel trigger selection - TSEL: u3, - /// channel noise/triangle wave generation enable - WAVE: WAVE, - /// channel mask/amplitude selector - MAMP: u4, - /// channel DMA enable - DMAEN: u1, - padding: u19, + /// (1/2 of EN) channel enable + @"EN[0]": u1, + /// (1/2 of BOFF) channel output buffer disable + @"BOFF[0]": u1, + /// (1/2 of TEN) channel trigger enable + @"TEN[0]": u1, + /// (1/2 of TSEL) channel trigger selection + @"TSEL[0]": u3, + /// (1/2 of WAVE) channel noise/triangle wave generation enable + @"WAVE[0]": WAVE, + /// (1/2 of MAMP) channel mask/amplitude selector + @"MAMP[0]": u4, + /// (1/2 of DMAEN) channel DMA enable + @"DMAEN[0]": u1, + reserved16: u3, + /// (2/2 of EN) channel enable + @"EN[1]": u1, + /// (2/2 of BOFF) channel output buffer disable + @"BOFF[1]": u1, + /// (2/2 of TEN) channel trigger enable + @"TEN[1]": u1, + /// (2/2 of TSEL) channel trigger selection + @"TSEL[1]": u3, + /// (2/2 of WAVE) channel noise/triangle wave generation enable + @"WAVE[1]": WAVE, + /// (2/2 of MAMP) channel mask/amplitude selector + @"MAMP[1]": u4, + /// (2/2 of DMAEN) channel DMA enable + @"DMAEN[1]": u1, + padding: u3, }), /// software trigger register SWTRIGR: mmio.Mmio(packed struct(u32) { - /// channel software trigger - SWTRIG: u1, - padding: u31, + /// (1/2 of SWTRIG) channel software trigger + @"SWTRIG[0]": u1, + /// (2/2 of SWTRIG) channel software trigger + @"SWTRIG[1]": u1, + padding: u30, }), /// channel 12-bit right-aligned data holding register DHR12R: mmio.Mmio(packed struct(u32) { @@ -315770,22 +317908,29 @@ pub const types = struct { reserved32: [12]u8, /// dual 12-bit right-aligned data holding register DHR12RD: mmio.Mmio(packed struct(u32) { - /// channel 12-bit right-aligned data - DHR: u12, - padding: u20, + /// (1/2 of DHR) channel 12-bit right-aligned data + @"DHR[0]": u12, + reserved16: u4, + /// (2/2 of DHR) channel 12-bit right-aligned data + @"DHR[1]": u12, + padding: u4, }), /// dual 12-bit left aligned data holding register DHR12LD: mmio.Mmio(packed struct(u32) { reserved4: u4, - /// channel 12-bit left-aligned data - DHR: u12, - padding: u16, + /// (1/2 of DHR) channel 12-bit left-aligned data + @"DHR[0]": u12, + reserved20: u4, + /// (2/2 of DHR) channel 12-bit left-aligned data + @"DHR[1]": u12, }), /// dual 8-bit right aligned data holding register DHR8RD: mmio.Mmio(packed struct(u32) { - /// channel 8-bit right-aligned data - DHR: u8, - padding: u24, + /// (1/2 of DHR) channel 8-bit right-aligned data + @"DHR[0]": u8, + /// (2/2 of DHR) channel 8-bit right-aligned data + @"DHR[1]": u8, + padding: u16, }), /// channel data output register DOR: [2]mmio.Mmio(packed struct(u32) { @@ -315811,29 +317956,48 @@ pub const types = struct { pub const DAC = extern struct { /// control register CR: mmio.Mmio(packed struct(u32) { - /// channel enable - EN: u1, - /// channel output buffer disable - BOFF: u1, - /// channel trigger enable - TEN: u1, - /// channel trigger selection - TSEL: u3, - /// channel noise/triangle wave generation enable - WAVE: WAVE, - /// channel mask/amplitude selector - MAMP: u4, - /// channel DMA enable - DMAEN: u1, - /// channel DMA Underrun Interrupt enable - DMAUDRIE: u1, - padding: u18, + /// (1/2 of EN) channel enable + @"EN[0]": u1, + /// (1/2 of BOFF) channel output buffer disable + @"BOFF[0]": u1, + /// (1/2 of TEN) channel trigger enable + @"TEN[0]": u1, + /// (1/2 of TSEL) channel trigger selection + @"TSEL[0]": u3, + /// (1/2 of WAVE) channel noise/triangle wave generation enable + @"WAVE[0]": WAVE, + /// (1/2 of MAMP) channel mask/amplitude selector + @"MAMP[0]": u4, + /// (1/2 of DMAEN) channel DMA enable + @"DMAEN[0]": u1, + /// (1/2 of DMAUDRIE) channel DMA Underrun Interrupt enable + @"DMAUDRIE[0]": u1, + reserved16: u2, + /// (2/2 of EN) channel enable + @"EN[1]": u1, + /// (2/2 of BOFF) channel output buffer disable + @"BOFF[1]": u1, + /// (2/2 of TEN) channel trigger enable + @"TEN[1]": u1, + /// (2/2 of TSEL) channel trigger selection + @"TSEL[1]": u3, + /// (2/2 of WAVE) channel noise/triangle wave generation enable + @"WAVE[1]": WAVE, + /// (2/2 of MAMP) channel mask/amplitude selector + @"MAMP[1]": u4, + /// (2/2 of DMAEN) channel DMA enable + @"DMAEN[1]": u1, + /// (2/2 of DMAUDRIE) channel DMA Underrun Interrupt enable + @"DMAUDRIE[1]": u1, + padding: u2, }), /// software trigger register SWTRIGR: mmio.Mmio(packed struct(u32) { - /// channel software trigger - SWTRIG: u1, - padding: u31, + /// (1/2 of SWTRIG) channel software trigger + @"SWTRIG[0]": u1, + /// (2/2 of SWTRIG) channel software trigger + @"SWTRIG[1]": u1, + padding: u30, }), /// channel 12-bit right-aligned data holding register DHR12R: mmio.Mmio(packed struct(u32) { @@ -315857,22 +318021,29 @@ pub const types = struct { reserved32: [12]u8, /// dual 12-bit right-aligned data holding register DHR12RD: mmio.Mmio(packed struct(u32) { - /// channel 12-bit right-aligned data - DHR: u12, - padding: u20, + /// (1/2 of DHR) channel 12-bit right-aligned data + @"DHR[0]": u12, + reserved16: u4, + /// (2/2 of DHR) channel 12-bit right-aligned data + @"DHR[1]": u12, + padding: u4, }), /// dual 12-bit left aligned data holding register DHR12LD: mmio.Mmio(packed struct(u32) { reserved4: u4, - /// channel 12-bit left-aligned data - DHR: u12, - padding: u16, + /// (1/2 of DHR) channel 12-bit left-aligned data + @"DHR[0]": u12, + reserved20: u4, + /// (2/2 of DHR) channel 12-bit left-aligned data + @"DHR[1]": u12, }), /// dual 8-bit right aligned data holding register DHR8RD: mmio.Mmio(packed struct(u32) { - /// channel 8-bit right-aligned data - DHR: u8, - padding: u24, + /// (1/2 of DHR) channel 8-bit right-aligned data + @"DHR[0]": u8, + /// (2/2 of DHR) channel 8-bit right-aligned data + @"DHR[1]": u8, + padding: u16, }), /// channel data output register DOR: [2]mmio.Mmio(packed struct(u32) { @@ -315883,9 +318054,12 @@ pub const types = struct { /// status register SR: mmio.Mmio(packed struct(u32) { reserved13: u13, - /// channel DMA underrun flag - DMAUDR: u1, - padding: u18, + /// (1/2 of DMAUDR) channel DMA underrun flag + @"DMAUDR[0]": u1, + reserved29: u15, + /// (2/2 of DMAUDR) channel DMA underrun flag + @"DMAUDR[1]": u1, + padding: u2, }), }; }; @@ -315924,30 +318098,50 @@ pub const types = struct { pub const DAC = extern struct { /// control register CR: mmio.Mmio(packed struct(u32) { - /// channel enable - EN: u1, + /// (1/2 of EN) channel enable + @"EN[0]": u1, reserved2: u1, - /// channel trigger enable - TEN: u1, - /// channel trigger selection - TSEL: u3, - /// channel noise/triangle wave generation enable - WAVE: WAVE, - /// channel mask/amplitude selector - MAMP: u4, - /// channel DMA enable - DMAEN: u1, - /// channel DMA Underrun Interrupt enable - DMAUDRIE: u1, - /// DAC channel calibration enable - CEN: u1, - padding: u17, + /// (1/2 of TEN) channel trigger enable + @"TEN[0]": u1, + /// (1/2 of TSEL) channel trigger selection + @"TSEL[0]": u3, + /// (1/2 of WAVE) channel noise/triangle wave generation enable + @"WAVE[0]": WAVE, + /// (1/2 of MAMP) channel mask/amplitude selector + @"MAMP[0]": u4, + /// (1/2 of DMAEN) channel DMA enable + @"DMAEN[0]": u1, + /// (1/2 of DMAUDRIE) channel DMA Underrun Interrupt enable + @"DMAUDRIE[0]": u1, + /// (1/2 of CEN) DAC channel calibration enable + @"CEN[0]": u1, + reserved16: u1, + /// (2/2 of EN) channel enable + @"EN[1]": u1, + reserved18: u1, + /// (2/2 of TEN) channel trigger enable + @"TEN[1]": u1, + /// (2/2 of TSEL) channel trigger selection + @"TSEL[1]": u3, + /// (2/2 of WAVE) channel noise/triangle wave generation enable + @"WAVE[1]": WAVE, + /// (2/2 of MAMP) channel mask/amplitude selector + @"MAMP[1]": u4, + /// (2/2 of DMAEN) channel DMA enable + @"DMAEN[1]": u1, + /// (2/2 of DMAUDRIE) channel DMA Underrun Interrupt enable + @"DMAUDRIE[1]": u1, + /// (2/2 of CEN) DAC channel calibration enable + @"CEN[1]": u1, + padding: u1, }), /// software trigger register SWTRIGR: mmio.Mmio(packed struct(u32) { - /// channel software trigger - SWTRIG: u1, - padding: u31, + /// (1/2 of SWTRIG) channel software trigger + @"SWTRIG[0]": u1, + /// (2/2 of SWTRIG) channel software trigger + @"SWTRIG[1]": u1, + padding: u30, }), /// channel 12-bit right-aligned data holding register DHR12R: mmio.Mmio(packed struct(u32) { @@ -315971,23 +318165,221 @@ pub const types = struct { reserved32: [12]u8, /// dual 12-bit right-aligned data holding register DHR12RD: mmio.Mmio(packed struct(u32) { + /// (1/2 of DHR) channel 12-bit right-aligned data + @"DHR[0]": u12, + reserved16: u4, + /// (2/2 of DHR) channel 12-bit right-aligned data + @"DHR[1]": u12, + padding: u4, + }), + /// dual 12-bit left aligned data holding register + DHR12LD: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// (1/2 of DHR) channel 12-bit left-aligned data + @"DHR[0]": u12, + reserved20: u4, + /// (2/2 of DHR) channel 12-bit left-aligned data + @"DHR[1]": u12, + }), + /// dual 8-bit right aligned data holding register + DHR8RD: mmio.Mmio(packed struct(u32) { + /// (1/2 of DHR) channel 8-bit right-aligned data + @"DHR[0]": u8, + /// (2/2 of DHR) channel 8-bit right-aligned data + @"DHR[1]": u8, + padding: u16, + }), + /// channel data output register + DOR: [2]mmio.Mmio(packed struct(u32) { + /// channel data output + DOR: u12, + padding: u20, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + reserved13: u13, + /// (1/2 of DMAUDR) channel DMA underrun flag + @"DMAUDR[0]": u1, + /// (1/2 of CAL_FLAG) channel calibration offset status + @"CAL_FLAG[0]": u1, + /// (1/2 of BWST) channel busy writing sample time flag + @"BWST[0]": u1, + reserved29: u13, + /// (2/2 of DMAUDR) channel DMA underrun flag + @"DMAUDR[1]": u1, + /// (2/2 of CAL_FLAG) channel calibration offset status + @"CAL_FLAG[1]": u1, + /// (2/2 of BWST) channel busy writing sample time flag + @"BWST[1]": u1, + }), + /// calibration control register + CCR: mmio.Mmio(packed struct(u32) { + /// (1/2 of OTRIM) channel offset trimming value + @"OTRIM[0]": u5, + reserved16: u11, + /// (2/2 of OTRIM) channel offset trimming value + @"OTRIM[1]": u5, + padding: u11, + }), + /// mode control register + MCR: mmio.Mmio(packed struct(u32) { + /// (1/2 of MODE) DAC channel mode + @"MODE[0]": MODE, + reserved16: u13, + /// (2/2 of MODE) DAC channel mode + @"MODE[1]": MODE, + padding: u13, + }), + /// sample and hold sample time register + SHSR: [2]mmio.Mmio(packed struct(u32) { + /// channel sample time + TSAMPLE: u10, + padding: u22, + }), + /// sample and hold hold time register + SHHR: mmio.Mmio(packed struct(u32) { + /// (1/2 of THOLD) channel hold time + @"THOLD[0]": u10, + reserved16: u6, + /// (2/2 of THOLD) channel hold time + @"THOLD[1]": u10, + padding: u6, + }), + /// sample and hold refresh time register + SHRR: mmio.Mmio(packed struct(u32) { + /// (1/2 of TREFRESH) channel refresh time + @"TREFRESH[0]": u8, + reserved16: u8, + /// (2/2 of TREFRESH) channel refresh time + @"TREFRESH[1]": u8, + padding: u8, + }), + }; + }; + + pub const dac_v4 = struct { + pub const MODE = enum(u3) { + /// Normal mode, external pin only, buffer enabled + NORMAL_EXT_BUFEN = 0x0, + /// Normal mode, external pin and internal peripherals, buffer enabled + NORMAL_EXT_INT_BUFEN = 0x1, + /// Normal mode, external pin only, buffer disabled + NORMAL_EXT_BUFDIS = 0x2, + /// Normal mode, internal peripherals only, buffer disabled + NORMAL_INT_BUFDIS = 0x3, + /// Sample and hold mode, external pin only, buffer enabled + SAMPHOLD_EXT_BUFEN = 0x4, + /// Sample and hold mode, external pin and internal peripherals, buffer enabled + SAMPHOLD_EXT_INT_BUFEN = 0x5, + /// Sample and hold mode, external pin and internal peripherals, buffer disabled + SAMPHOLD_EXT_INT_BUFDIS = 0x6, + /// Sample and hold mode, internal peripherals only, buffer disabled + SAMPHOLD_INT_BUFDIS = 0x7, + }; + + pub const WAVE = enum(u2) { + /// Wave generation disabled + Disabled = 0x0, + /// Noise wave generation enabled + Noise = 0x1, + /// Triangle wave generation enabled + Triangle = 0x2, + _, + }; + + /// Digital-to-analog converter + pub const DAC = extern struct { + /// control register + CR: mmio.Mmio(packed struct(u32) { + /// (1/2 of EN) channel enable + @"EN[0]": u1, + /// (1/2 of TEN) channel trigger enable + @"TEN[0]": u1, + /// (1/2 of TSEL) channel trigger selection + @"TSEL[0]": u4, + /// (1/2 of WAVE) channel noise/triangle wave generation enable + @"WAVE[0]": WAVE, + /// (1/2 of MAMP) channel mask/amplitude selector + @"MAMP[0]": u4, + /// (1/2 of DMAEN) channel DMA enable + @"DMAEN[0]": u1, + /// (1/2 of DMAUDRIE) channel DMA Underrun Interrupt enable + @"DMAUDRIE[0]": u1, + /// (1/2 of CEN) DAC channel calibration enable + @"CEN[0]": u1, + reserved16: u1, + /// (2/2 of EN) channel enable + @"EN[1]": u1, + /// (2/2 of TEN) channel trigger enable + @"TEN[1]": u1, + /// (2/2 of TSEL) channel trigger selection + @"TSEL[1]": u4, + /// (2/2 of WAVE) channel noise/triangle wave generation enable + @"WAVE[1]": WAVE, + /// (2/2 of MAMP) channel mask/amplitude selector + @"MAMP[1]": u4, + /// (2/2 of DMAEN) channel DMA enable + @"DMAEN[1]": u1, + /// (2/2 of DMAUDRIE) channel DMA Underrun Interrupt enable + @"DMAUDRIE[1]": u1, + /// (2/2 of CEN) DAC channel calibration enable + @"CEN[1]": u1, + padding: u1, + }), + /// software trigger register + SWTRIGR: mmio.Mmio(packed struct(u32) { + /// (1/2 of SWTRIG) channel software trigger + @"SWTRIG[0]": u1, + /// (2/2 of SWTRIG) channel software trigger + @"SWTRIG[1]": u1, + padding: u30, + }), + /// channel 12-bit right-aligned data holding register + DHR12R: mmio.Mmio(packed struct(u32) { /// channel 12-bit right-aligned data DHR: u12, padding: u20, }), - /// dual 12-bit left aligned data holding register - DHR12LD: mmio.Mmio(packed struct(u32) { + /// channel 12-bit left-aligned data holding register + DHR12L: mmio.Mmio(packed struct(u32) { reserved4: u4, /// channel 12-bit left-aligned data DHR: u12, padding: u16, }), - /// dual 8-bit right aligned data holding register - DHR8RD: mmio.Mmio(packed struct(u32) { + /// channel 8-bit right-aligned data holding register + DHR8R: mmio.Mmio(packed struct(u32) { /// channel 8-bit right-aligned data DHR: u8, padding: u24, }), + reserved32: [12]u8, + /// dual 12-bit right-aligned data holding register + DHR12RD: mmio.Mmio(packed struct(u32) { + /// (1/2 of DHR) channel 12-bit right-aligned data + @"DHR[0]": u12, + reserved16: u4, + /// (2/2 of DHR) channel 12-bit right-aligned data + @"DHR[1]": u12, + padding: u4, + }), + /// dual 12-bit left aligned data holding register + DHR12LD: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// (1/2 of DHR) channel 12-bit left-aligned data + @"DHR[0]": u12, + reserved20: u4, + /// (2/2 of DHR) channel 12-bit left-aligned data + @"DHR[1]": u12, + }), + /// dual 8-bit right aligned data holding register + DHR8RD: mmio.Mmio(packed struct(u32) { + /// (1/2 of DHR) channel 8-bit right-aligned data + @"DHR[0]": u8, + /// (2/2 of DHR) channel 8-bit right-aligned data + @"DHR[1]": u8, + padding: u16, + }), /// channel data output register DOR: [2]mmio.Mmio(packed struct(u32) { /// channel data output @@ -315997,25 +318389,37 @@ pub const types = struct { /// status register SR: mmio.Mmio(packed struct(u32) { reserved13: u13, - /// channel DMA underrun flag - DMAUDR: u1, - /// channel calibration offset status - CAL_FLAG: u1, - /// channel busy writing sample time flag - BWST: u1, - padding: u16, + /// (1/2 of DMAUDR) channel DMA underrun flag + @"DMAUDR[0]": u1, + /// (1/2 of CAL_FLAG) channel calibration offset status + @"CAL_FLAG[0]": u1, + /// (1/2 of BWST) channel busy writing sample time flag + @"BWST[0]": u1, + reserved29: u13, + /// (2/2 of DMAUDR) channel DMA underrun flag + @"DMAUDR[1]": u1, + /// (2/2 of CAL_FLAG) channel calibration offset status + @"CAL_FLAG[1]": u1, + /// (2/2 of BWST) channel busy writing sample time flag + @"BWST[1]": u1, }), /// calibration control register CCR: mmio.Mmio(packed struct(u32) { - /// channel offset trimming value - OTRIM: u5, - padding: u27, + /// (1/2 of OTRIM) channel offset trimming value + @"OTRIM[0]": u5, + reserved16: u11, + /// (2/2 of OTRIM) channel offset trimming value + @"OTRIM[1]": u5, + padding: u11, }), /// mode control register MCR: mmio.Mmio(packed struct(u32) { - /// DAC channel mode - MODE: MODE, - padding: u29, + /// (1/2 of MODE) DAC channel mode + @"MODE[0]": MODE, + reserved16: u13, + /// (2/2 of MODE) DAC channel mode + @"MODE[1]": MODE, + padding: u13, }), /// sample and hold sample time register SHSR: [2]mmio.Mmio(packed struct(u32) { @@ -316025,20 +318429,26 @@ pub const types = struct { }), /// sample and hold hold time register SHHR: mmio.Mmio(packed struct(u32) { - /// channel hold time - THOLD: u10, - padding: u22, + /// (1/2 of THOLD) channel hold time + @"THOLD[0]": u10, + reserved16: u6, + /// (2/2 of THOLD) channel hold time + @"THOLD[1]": u10, + padding: u6, }), /// sample and hold refresh time register SHRR: mmio.Mmio(packed struct(u32) { - /// channel refresh time - TREFRESH: u8, - padding: u24, + /// (1/2 of TREFRESH) channel refresh time + @"TREFRESH[0]": u8, + reserved16: u8, + /// (2/2 of TREFRESH) channel refresh time + @"TREFRESH[1]": u8, + padding: u8, }), }; }; - pub const dac_v4 = struct { + pub const dac_v5 = struct { pub const MODE = enum(u3) { /// Normal mode, external pin only, buffer enabled NORMAL_EXT_BUFEN = 0x0, @@ -316072,178 +318482,49 @@ pub const types = struct { pub const DAC = extern struct { /// control register CR: mmio.Mmio(packed struct(u32) { - /// channel enable - EN: u1, - /// channel trigger enable - TEN: u1, - /// channel trigger selection - TSEL: u4, - /// channel noise/triangle wave generation enable - WAVE: WAVE, - /// channel mask/amplitude selector - MAMP: u4, - /// channel DMA enable - DMAEN: u1, - /// channel DMA Underrun Interrupt enable - DMAUDRIE: u1, - /// DAC channel calibration enable - CEN: u1, - padding: u17, - }), - /// software trigger register - SWTRIGR: mmio.Mmio(packed struct(u32) { - /// channel software trigger - SWTRIG: u1, - padding: u31, - }), - /// channel 12-bit right-aligned data holding register - DHR12R: mmio.Mmio(packed struct(u32) { - /// channel 12-bit right-aligned data - DHR: u12, - padding: u20, - }), - /// channel 12-bit left-aligned data holding register - DHR12L: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// channel 12-bit left-aligned data - DHR: u12, - padding: u16, - }), - /// channel 8-bit right-aligned data holding register - DHR8R: mmio.Mmio(packed struct(u32) { - /// channel 8-bit right-aligned data - DHR: u8, - padding: u24, - }), - reserved32: [12]u8, - /// dual 12-bit right-aligned data holding register - DHR12RD: mmio.Mmio(packed struct(u32) { - /// channel 12-bit right-aligned data - DHR: u12, - padding: u20, - }), - /// dual 12-bit left aligned data holding register - DHR12LD: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// channel 12-bit left-aligned data - DHR: u12, - padding: u16, - }), - /// dual 8-bit right aligned data holding register - DHR8RD: mmio.Mmio(packed struct(u32) { - /// channel 8-bit right-aligned data - DHR: u8, - padding: u24, - }), - /// channel data output register - DOR: [2]mmio.Mmio(packed struct(u32) { - /// channel data output - DOR: u12, - padding: u20, - }), - /// status register - SR: mmio.Mmio(packed struct(u32) { - reserved13: u13, - /// channel DMA underrun flag - DMAUDR: u1, - /// channel calibration offset status - CAL_FLAG: u1, - /// channel busy writing sample time flag - BWST: u1, - padding: u16, - }), - /// calibration control register - CCR: mmio.Mmio(packed struct(u32) { - /// channel offset trimming value - OTRIM: u5, - padding: u27, - }), - /// mode control register - MCR: mmio.Mmio(packed struct(u32) { - /// DAC channel mode - MODE: MODE, - padding: u29, - }), - /// sample and hold sample time register - SHSR: [2]mmio.Mmio(packed struct(u32) { - /// channel sample time - TSAMPLE: u10, - padding: u22, - }), - /// sample and hold hold time register - SHHR: mmio.Mmio(packed struct(u32) { - /// channel hold time - THOLD: u10, - padding: u22, - }), - /// sample and hold refresh time register - SHRR: mmio.Mmio(packed struct(u32) { - /// channel refresh time - TREFRESH: u8, - padding: u24, - }), - }; - }; - - pub const dac_v5 = struct { - pub const MODE = enum(u3) { - /// Normal mode, external pin only, buffer enabled - NORMAL_EXT_BUFEN = 0x0, - /// Normal mode, external pin and internal peripherals, buffer enabled - NORMAL_EXT_INT_BUFEN = 0x1, - /// Normal mode, external pin only, buffer disabled - NORMAL_EXT_BUFDIS = 0x2, - /// Normal mode, internal peripherals only, buffer disabled - NORMAL_INT_BUFDIS = 0x3, - /// Sample and hold mode, external pin only, buffer enabled - SAMPHOLD_EXT_BUFEN = 0x4, - /// Sample and hold mode, external pin and internal peripherals, buffer enabled - SAMPHOLD_EXT_INT_BUFEN = 0x5, - /// Sample and hold mode, external pin and internal peripherals, buffer disabled - SAMPHOLD_EXT_INT_BUFDIS = 0x6, - /// Sample and hold mode, internal peripherals only, buffer disabled - SAMPHOLD_INT_BUFDIS = 0x7, - }; - - pub const WAVE = enum(u2) { - /// Wave generation disabled - Disabled = 0x0, - /// Noise wave generation enabled - Noise = 0x1, - /// Triangle wave generation enabled - Triangle = 0x2, - _, - }; - - /// Digital-to-analog converter - pub const DAC = extern struct { - /// control register - CR: mmio.Mmio(packed struct(u32) { - /// channel enable - EN: u1, - /// channel trigger enable - TEN: u1, - /// channel trigger selection - TSEL: u4, - /// channel noise/triangle wave generation enable - WAVE: WAVE, - /// channel mask/amplitude selector - MAMP: u4, - /// channel DMA enable - DMAEN: u1, - /// channel DMA Underrun Interrupt enable - DMAUDRIE: u1, - /// DAC channel calibration enable - CEN: u1, + /// (1/2 of EN) channel enable + @"EN[0]": u1, + /// (1/2 of TEN) channel trigger enable + @"TEN[0]": u1, + /// (1/2 of TSEL) channel trigger selection + @"TSEL[0]": u4, + /// (1/2 of WAVE) channel noise/triangle wave generation enable + @"WAVE[0]": WAVE, + /// (1/2 of MAMP) channel mask/amplitude selector + @"MAMP[0]": u4, + /// (1/2 of DMAEN) channel DMA enable + @"DMAEN[0]": u1, + /// (1/2 of DMAUDRIE) channel DMA Underrun Interrupt enable + @"DMAUDRIE[0]": u1, + /// (1/2 of CEN) DAC channel calibration enable + @"CEN[0]": u1, /// high frequency interface mode enable HFSEL: u1, - padding: u16, + /// (2/2 of EN) channel enable + @"EN[1]": u1, + /// (2/2 of TEN) channel trigger enable + @"TEN[1]": u1, + /// (2/2 of TSEL) channel trigger selection + @"TSEL[1]": u4, + /// (2/2 of WAVE) channel noise/triangle wave generation enable + @"WAVE[1]": WAVE, + /// (2/2 of MAMP) channel mask/amplitude selector + @"MAMP[1]": u4, + /// (2/2 of DMAEN) channel DMA enable + @"DMAEN[1]": u1, + /// (2/2 of DMAUDRIE) channel DMA Underrun Interrupt enable + @"DMAUDRIE[1]": u1, + /// (2/2 of CEN) DAC channel calibration enable + @"CEN[1]": u1, + padding: u1, }), /// software trigger register SWTRIGR: mmio.Mmio(packed struct(u32) { - /// channel software trigger - SWTRIG: u1, - padding: u31, + /// (1/2 of SWTRIG) channel software trigger + @"SWTRIG[0]": u1, + /// (2/2 of SWTRIG) channel software trigger + @"SWTRIG[1]": u1, + padding: u30, }), /// channel 12-bit right-aligned data holding register DHR12R: mmio.Mmio(packed struct(u32) { @@ -316267,22 +318548,29 @@ pub const types = struct { reserved32: [12]u8, /// dual 12-bit right-aligned data holding register DHR12RD: mmio.Mmio(packed struct(u32) { - /// channel 12-bit right-aligned data - DHR: u12, - padding: u20, + /// (1/2 of DHR) channel 12-bit right-aligned data + @"DHR[0]": u12, + reserved16: u4, + /// (2/2 of DHR) channel 12-bit right-aligned data + @"DHR[1]": u12, + padding: u4, }), /// dual 12-bit left aligned data holding register DHR12LD: mmio.Mmio(packed struct(u32) { reserved4: u4, - /// channel 12-bit left-aligned data - DHR: u12, - padding: u16, + /// (1/2 of DHR) channel 12-bit left-aligned data + @"DHR[0]": u12, + reserved20: u4, + /// (2/2 of DHR) channel 12-bit left-aligned data + @"DHR[1]": u12, }), /// dual 8-bit right aligned data holding register DHR8RD: mmio.Mmio(packed struct(u32) { - /// channel 8-bit right-aligned data - DHR: u8, - padding: u24, + /// (1/2 of DHR) channel 8-bit right-aligned data + @"DHR[0]": u8, + /// (2/2 of DHR) channel 8-bit right-aligned data + @"DHR[1]": u8, + padding: u16, }), /// channel data output register DOR: [2]mmio.Mmio(packed struct(u32) { @@ -316293,25 +318581,37 @@ pub const types = struct { /// status register SR: mmio.Mmio(packed struct(u32) { reserved13: u13, - /// channel DMA underrun flag - DMAUDR: u1, - /// channel calibration offset status - CAL_FLAG: u1, - /// channel busy writing sample time flag - BWST: u1, - padding: u16, + /// (1/2 of DMAUDR) channel DMA underrun flag + @"DMAUDR[0]": u1, + /// (1/2 of CAL_FLAG) channel calibration offset status + @"CAL_FLAG[0]": u1, + /// (1/2 of BWST) channel busy writing sample time flag + @"BWST[0]": u1, + reserved29: u13, + /// (2/2 of DMAUDR) channel DMA underrun flag + @"DMAUDR[1]": u1, + /// (2/2 of CAL_FLAG) channel calibration offset status + @"CAL_FLAG[1]": u1, + /// (2/2 of BWST) channel busy writing sample time flag + @"BWST[1]": u1, }), /// calibration control register CCR: mmio.Mmio(packed struct(u32) { - /// channel offset trimming value - OTRIM: u5, - padding: u27, + /// (1/2 of OTRIM) channel offset trimming value + @"OTRIM[0]": u5, + reserved16: u11, + /// (2/2 of OTRIM) channel offset trimming value + @"OTRIM[1]": u5, + padding: u11, }), /// mode control register MCR: mmio.Mmio(packed struct(u32) { - /// DAC channel mode - MODE: MODE, - padding: u29, + /// (1/2 of MODE) DAC channel mode + @"MODE[0]": MODE, + reserved16: u13, + /// (2/2 of MODE) DAC channel mode + @"MODE[1]": MODE, + padding: u13, }), /// sample and hold sample time register SHSR: [2]mmio.Mmio(packed struct(u32) { @@ -316321,15 +318621,21 @@ pub const types = struct { }), /// sample and hold hold time register SHHR: mmio.Mmio(packed struct(u32) { - /// channel hold time - THOLD: u10, - padding: u22, + /// (1/2 of THOLD) channel hold time + @"THOLD[0]": u10, + reserved16: u6, + /// (2/2 of THOLD) channel hold time + @"THOLD[1]": u10, + padding: u6, }), /// sample and hold refresh time register SHRR: mmio.Mmio(packed struct(u32) { - /// channel refresh time - TREFRESH: u8, - padding: u24, + /// (1/2 of TREFRESH) channel refresh time + @"TREFRESH[0]": u8, + reserved16: u8, + /// (2/2 of TREFRESH) channel refresh time + @"TREFRESH[1]": u8, + padding: u8, }), }; }; @@ -316368,32 +318674,53 @@ pub const types = struct { pub const DAC = extern struct { /// control register CR: mmio.Mmio(packed struct(u32) { - /// channel enable - EN: u1, - /// channel trigger enable - TEN: u1, - /// channel trigger selection - TSEL: u4, - /// channel noise/triangle wave generation enable - WAVE: WAVE, - /// channel mask/amplitude selector - MAMP: u4, - /// channel DMA enable - DMAEN: u1, - /// channel DMA Underrun Interrupt enable - DMAUDRIE: u1, - /// DAC channel calibration enable - CEN: u1, - padding: u17, + /// (1/2 of EN) channel enable + @"EN[0]": u1, + /// (1/2 of TEN) channel trigger enable + @"TEN[0]": u1, + /// (1/2 of TSEL) channel trigger selection + @"TSEL[0]": u4, + /// (1/2 of WAVE) channel noise/triangle wave generation enable + @"WAVE[0]": WAVE, + /// (1/2 of MAMP) channel mask/amplitude selector + @"MAMP[0]": u4, + /// (1/2 of DMAEN) channel DMA enable + @"DMAEN[0]": u1, + /// (1/2 of DMAUDRIE) channel DMA Underrun Interrupt enable + @"DMAUDRIE[0]": u1, + /// (1/2 of CEN) DAC channel calibration enable + @"CEN[0]": u1, + reserved16: u1, + /// (2/2 of EN) channel enable + @"EN[1]": u1, + /// (2/2 of TEN) channel trigger enable + @"TEN[1]": u1, + /// (2/2 of TSEL) channel trigger selection + @"TSEL[1]": u4, + /// (2/2 of WAVE) channel noise/triangle wave generation enable + @"WAVE[1]": WAVE, + /// (2/2 of MAMP) channel mask/amplitude selector + @"MAMP[1]": u4, + /// (2/2 of DMAEN) channel DMA enable + @"DMAEN[1]": u1, + /// (2/2 of DMAUDRIE) channel DMA Underrun Interrupt enable + @"DMAUDRIE[1]": u1, + /// (2/2 of CEN) DAC channel calibration enable + @"CEN[1]": u1, + padding: u1, }), /// software trigger register SWTRIGR: mmio.Mmio(packed struct(u32) { - /// channel software trigger - SWTRIG: u1, - reserved16: u15, - /// channel software trigger B - SWTRIGB: u1, - padding: u15, + /// (1/2 of SWTRIG) channel software trigger + @"SWTRIG[0]": u1, + /// (2/2 of SWTRIG) channel software trigger + @"SWTRIG[1]": u1, + reserved16: u14, + /// (1/2 of SWTRIGB) channel software trigger B + @"SWTRIGB[0]": u1, + /// (2/2 of SWTRIGB) channel software trigger B + @"SWTRIGB[1]": u1, + padding: u14, }), /// channel 12-bit right-aligned data holding register DHR12R: mmio.Mmio(packed struct(u32) { @@ -316424,22 +318751,29 @@ pub const types = struct { reserved32: [12]u8, /// dual 12-bit right-aligned data holding register DHR12RD: mmio.Mmio(packed struct(u32) { - /// channel 12-bit right-aligned data - DHR: u12, - padding: u20, + /// (1/2 of DHR) channel 12-bit right-aligned data + @"DHR[0]": u12, + reserved16: u4, + /// (2/2 of DHR) channel 12-bit right-aligned data + @"DHR[1]": u12, + padding: u4, }), /// dual 12-bit left aligned data holding register DHR12LD: mmio.Mmio(packed struct(u32) { reserved4: u4, - /// channel 12-bit left-aligned data - DHR: u12, - padding: u16, + /// (1/2 of DHR) channel 12-bit left-aligned data + @"DHR[0]": u12, + reserved20: u4, + /// (2/2 of DHR) channel 12-bit left-aligned data + @"DHR[1]": u12, }), /// dual 8-bit right aligned data holding register DHR8RD: mmio.Mmio(packed struct(u32) { - /// channel 8-bit right-aligned data - DHR: u8, - padding: u24, + /// (1/2 of DHR) channel 8-bit right-aligned data + @"DHR[0]": u8, + /// (2/2 of DHR) channel 8-bit right-aligned data + @"DHR[1]": u8, + padding: u16, }), /// channel data output register DOR: [2]mmio.Mmio(packed struct(u32) { @@ -316453,37 +318787,57 @@ pub const types = struct { /// status register SR: mmio.Mmio(packed struct(u32) { reserved11: u11, - /// channel ready status bit - DACRDY: u1, - /// channel output register status bit - DORSTAT: u1, - /// channel DMA underrun flag - DMAUDR: u1, - /// channel calibration offset status - CAL_FLAG: u1, - /// channel busy writing sample time flag - BWST: u1, - padding: u16, + /// (1/2 of DACRDY) channel ready status bit + @"DACRDY[0]": u1, + /// (1/2 of DORSTAT) channel output register status bit + @"DORSTAT[0]": u1, + /// (1/2 of DMAUDR) channel DMA underrun flag + @"DMAUDR[0]": u1, + /// (1/2 of CAL_FLAG) channel calibration offset status + @"CAL_FLAG[0]": u1, + /// (1/2 of BWST) channel busy writing sample time flag + @"BWST[0]": u1, + reserved27: u11, + /// (2/2 of DACRDY) channel ready status bit + @"DACRDY[1]": u1, + /// (2/2 of DORSTAT) channel output register status bit + @"DORSTAT[1]": u1, + /// (2/2 of DMAUDR) channel DMA underrun flag + @"DMAUDR[1]": u1, + /// (2/2 of CAL_FLAG) channel calibration offset status + @"CAL_FLAG[1]": u1, + /// (2/2 of BWST) channel busy writing sample time flag + @"BWST[1]": u1, }), /// calibration control register CCR: mmio.Mmio(packed struct(u32) { - /// channel offset trimming value - OTRIM: u5, - padding: u27, + /// (1/2 of OTRIM) channel offset trimming value + @"OTRIM[0]": u5, + reserved16: u11, + /// (2/2 of OTRIM) channel offset trimming value + @"OTRIM[1]": u5, + padding: u11, }), /// mode control register MCR: mmio.Mmio(packed struct(u32) { - /// DAC channel mode - MODE: MODE, + /// (1/2 of MODE) DAC channel mode + @"MODE[0]": MODE, reserved8: u5, - /// channel DMA double data mode. - DMADOUBLE: u1, - /// enable signed format for DAC channel - SINFORMAT: u1, + /// (1/2 of DMADOUBLE) channel DMA double data mode. + @"DMADOUBLE[0]": u1, + /// (1/2 of SINFORMAT) enable signed format for DAC channel + @"SINFORMAT[0]": u1, reserved14: u4, /// high frequency interface mode selection HFSEL: u2, - padding: u16, + /// (2/2 of MODE) DAC channel mode + @"MODE[1]": MODE, + reserved24: u5, + /// (2/2 of DMADOUBLE) channel DMA double data mode. + @"DMADOUBLE[1]": u1, + /// (2/2 of SINFORMAT) enable signed format for DAC channel + @"SINFORMAT[1]": u1, + padding: u6, }), /// sample and hold sample time register SHSR: [2]mmio.Mmio(packed struct(u32) { @@ -316493,15 +318847,21 @@ pub const types = struct { }), /// sample and hold hold time register SHHR: mmio.Mmio(packed struct(u32) { - /// channel hold time - THOLD: u10, - padding: u22, + /// (1/2 of THOLD) channel hold time + @"THOLD[0]": u10, + reserved16: u6, + /// (2/2 of THOLD) channel hold time + @"THOLD[1]": u10, + padding: u6, }), /// sample and hold refresh time register SHRR: mmio.Mmio(packed struct(u32) { - /// channel refresh time - TREFRESH: u8, - padding: u24, + /// (1/2 of TREFRESH) channel refresh time + @"TREFRESH[0]": u8, + reserved16: u8, + /// (2/2 of TREFRESH) channel refresh time + @"TREFRESH[1]": u8, + padding: u8, }), }; }; @@ -316541,32 +318901,53 @@ pub const types = struct { pub const DAC = extern struct { /// control register CR: mmio.Mmio(packed struct(u32) { - /// channel enable - EN: u1, - /// channel trigger enable - TEN: u1, - /// channel trigger selection - TSEL: u4, - /// channel noise/triangle wave generation enable - WAVE: WAVE, - /// channel mask/amplitude selector - MAMP: u4, - /// channel DMA enable - DMAEN: u1, - /// channel DMA Underrun Interrupt enable - DMAUDRIE: u1, - /// DAC channel calibration enable - CEN: u1, - padding: u17, + /// (1/2 of EN) channel enable + @"EN[0]": u1, + /// (1/2 of TEN) channel trigger enable + @"TEN[0]": u1, + /// (1/2 of TSEL) channel trigger selection + @"TSEL[0]": u4, + /// (1/2 of WAVE) channel noise/triangle wave generation enable + @"WAVE[0]": WAVE, + /// (1/2 of MAMP) channel mask/amplitude selector + @"MAMP[0]": u4, + /// (1/2 of DMAEN) channel DMA enable + @"DMAEN[0]": u1, + /// (1/2 of DMAUDRIE) channel DMA Underrun Interrupt enable + @"DMAUDRIE[0]": u1, + /// (1/2 of CEN) DAC channel calibration enable + @"CEN[0]": u1, + reserved16: u1, + /// (2/2 of EN) channel enable + @"EN[1]": u1, + /// (2/2 of TEN) channel trigger enable + @"TEN[1]": u1, + /// (2/2 of TSEL) channel trigger selection + @"TSEL[1]": u4, + /// (2/2 of WAVE) channel noise/triangle wave generation enable + @"WAVE[1]": WAVE, + /// (2/2 of MAMP) channel mask/amplitude selector + @"MAMP[1]": u4, + /// (2/2 of DMAEN) channel DMA enable + @"DMAEN[1]": u1, + /// (2/2 of DMAUDRIE) channel DMA Underrun Interrupt enable + @"DMAUDRIE[1]": u1, + /// (2/2 of CEN) DAC channel calibration enable + @"CEN[1]": u1, + padding: u1, }), /// software trigger register SWTRIGR: mmio.Mmio(packed struct(u32) { - /// channel software trigger - SWTRIG: u1, - reserved16: u15, - /// channel software trigger B - SWTRIGB: u1, - padding: u15, + /// (1/2 of SWTRIG) channel software trigger + @"SWTRIG[0]": u1, + /// (2/2 of SWTRIG) channel software trigger + @"SWTRIG[1]": u1, + reserved16: u14, + /// (1/2 of SWTRIGB) channel software trigger B + @"SWTRIGB[0]": u1, + /// (2/2 of SWTRIGB) channel software trigger B + @"SWTRIGB[1]": u1, + padding: u14, }), /// channel 12-bit right-aligned data holding register DHR12R: mmio.Mmio(packed struct(u32) { @@ -316597,22 +318978,29 @@ pub const types = struct { reserved32: [12]u8, /// dual 12-bit right-aligned data holding register DHR12RD: mmio.Mmio(packed struct(u32) { - /// channel 12-bit right-aligned data - DHR: u12, - padding: u20, + /// (1/2 of DHR) channel 12-bit right-aligned data + @"DHR[0]": u12, + reserved16: u4, + /// (2/2 of DHR) channel 12-bit right-aligned data + @"DHR[1]": u12, + padding: u4, }), /// dual 12-bit left aligned data holding register DHR12LD: mmio.Mmio(packed struct(u32) { reserved4: u4, - /// channel 12-bit left-aligned data - DHR: u12, - padding: u16, + /// (1/2 of DHR) channel 12-bit left-aligned data + @"DHR[0]": u12, + reserved20: u4, + /// (2/2 of DHR) channel 12-bit left-aligned data + @"DHR[1]": u12, }), /// dual 8-bit right aligned data holding register DHR8RD: mmio.Mmio(packed struct(u32) { - /// channel 8-bit right-aligned data - DHR: u8, - padding: u24, + /// (1/2 of DHR) channel 8-bit right-aligned data + @"DHR[0]": u8, + /// (2/2 of DHR) channel 8-bit right-aligned data + @"DHR[1]": u8, + padding: u16, }), /// channel data output register DOR: [2]mmio.Mmio(packed struct(u32) { @@ -316626,37 +319014,57 @@ pub const types = struct { /// status register SR: mmio.Mmio(packed struct(u32) { reserved11: u11, - /// channel ready status bit - DACRDY: u1, - /// channel output register status bit - DORSTAT: u1, - /// channel DMA underrun flag - DMAUDR: u1, - /// channel calibration offset status - CAL_FLAG: u1, - /// channel busy writing sample time flag - BWST: u1, - padding: u16, + /// (1/2 of DACRDY) channel ready status bit + @"DACRDY[0]": u1, + /// (1/2 of DORSTAT) channel output register status bit + @"DORSTAT[0]": u1, + /// (1/2 of DMAUDR) channel DMA underrun flag + @"DMAUDR[0]": u1, + /// (1/2 of CAL_FLAG) channel calibration offset status + @"CAL_FLAG[0]": u1, + /// (1/2 of BWST) channel busy writing sample time flag + @"BWST[0]": u1, + reserved27: u11, + /// (2/2 of DACRDY) channel ready status bit + @"DACRDY[1]": u1, + /// (2/2 of DORSTAT) channel output register status bit + @"DORSTAT[1]": u1, + /// (2/2 of DMAUDR) channel DMA underrun flag + @"DMAUDR[1]": u1, + /// (2/2 of CAL_FLAG) channel calibration offset status + @"CAL_FLAG[1]": u1, + /// (2/2 of BWST) channel busy writing sample time flag + @"BWST[1]": u1, }), /// calibration control register CCR: mmio.Mmio(packed struct(u32) { - /// channel offset trimming value - OTRIM: u5, - padding: u27, + /// (1/2 of OTRIM) channel offset trimming value + @"OTRIM[0]": u5, + reserved16: u11, + /// (2/2 of OTRIM) channel offset trimming value + @"OTRIM[1]": u5, + padding: u11, }), /// mode control register MCR: mmio.Mmio(packed struct(u32) { - /// DAC channel mode - MODE: MODE, + /// (1/2 of MODE) DAC channel mode + @"MODE[0]": MODE, reserved8: u5, - /// channel DMA double data mode. - DMADOUBLE: u1, - /// enable signed format for DAC channel - SINFORMAT: u1, + /// (1/2 of DMADOUBLE) channel DMA double data mode. + @"DMADOUBLE[0]": u1, + /// (1/2 of SINFORMAT) enable signed format for DAC channel + @"SINFORMAT[0]": u1, reserved14: u4, /// high frequency interface mode selection HFSEL: u2, - padding: u16, + /// (2/2 of MODE) DAC channel mode + @"MODE[1]": MODE, + reserved24: u5, + /// (2/2 of DMADOUBLE) channel DMA double data mode. + @"DMADOUBLE[1]": u1, + /// (2/2 of SINFORMAT) enable signed format for DAC channel + @"SINFORMAT[1]": u1, + padding: u6, }), /// sample and hold sample time register SHSR: [2]mmio.Mmio(packed struct(u32) { @@ -316666,15 +319074,21 @@ pub const types = struct { }), /// sample and hold hold time register SHHR: mmio.Mmio(packed struct(u32) { - /// channel hold time - THOLD: u10, - padding: u22, + /// (1/2 of THOLD) channel hold time + @"THOLD[0]": u10, + reserved16: u6, + /// (2/2 of THOLD) channel hold time + @"THOLD[1]": u10, + padding: u6, }), /// sample and hold refresh time register SHRR: mmio.Mmio(packed struct(u32) { - /// channel refresh time - TREFRESH: u8, - padding: u24, + /// (1/2 of TREFRESH) channel refresh time + @"TREFRESH[0]": u8, + reserved16: u8, + /// (2/2 of TREFRESH) channel refresh time + @"TREFRESH[1]": u8, + padding: u8, }), reserved88: [8]u8, /// Sawtooth register @@ -316689,12 +319103,18 @@ pub const types = struct { }), /// Sawtooth Mode register STMODR: mmio.Mmio(packed struct(u32) { - /// channel sawtooth reset trigger selection - STRSTTRIGSEL: u4, + /// (1/2 of STRSTTRIGSEL) channel sawtooth reset trigger selection + @"STRSTTRIGSEL[0]": u4, reserved8: u4, - /// channel sawtooth increment trigger selection - STINCTRIGSEL: u4, - padding: u20, + /// (1/2 of STINCTRIGSEL) channel sawtooth increment trigger selection + @"STINCTRIGSEL[0]": u4, + reserved16: u4, + /// (2/2 of STRSTTRIGSEL) channel sawtooth reset trigger selection + @"STRSTTRIGSEL[1]": u4, + reserved24: u4, + /// (2/2 of STINCTRIGSEL) channel sawtooth increment trigger selection + @"STINCTRIGSEL[1]": u4, + padding: u4, }), }; }; @@ -317504,12 +319924,70 @@ pub const types = struct { reserved32: [8]u8, /// DBGMCU AHB1 peripheral freeze register. AHB1FZR: mmio.Mmio(packed struct(u32) { - /// GPDMA1 channel 0 stop in debug. - GPDMA1_STOP: u1, - reserved16: u15, - /// GPDMA2 channel 0 stop in debug. - GPDMA2_STOP: u1, - padding: u15, + /// (1/16 of GPDMA1_STOP) GPDMA1 channel 0 stop in debug. + @"GPDMA1_STOP[0]": u1, + /// (2/16 of GPDMA1_STOP) GPDMA1 channel 0 stop in debug. + @"GPDMA1_STOP[1]": u1, + /// (3/16 of GPDMA1_STOP) GPDMA1 channel 0 stop in debug. + @"GPDMA1_STOP[2]": u1, + /// (4/16 of GPDMA1_STOP) GPDMA1 channel 0 stop in debug. + @"GPDMA1_STOP[3]": u1, + /// (5/16 of GPDMA1_STOP) GPDMA1 channel 0 stop in debug. + @"GPDMA1_STOP[4]": u1, + /// (6/16 of GPDMA1_STOP) GPDMA1 channel 0 stop in debug. + @"GPDMA1_STOP[5]": u1, + /// (7/16 of GPDMA1_STOP) GPDMA1 channel 0 stop in debug. + @"GPDMA1_STOP[6]": u1, + /// (8/16 of GPDMA1_STOP) GPDMA1 channel 0 stop in debug. + @"GPDMA1_STOP[7]": u1, + /// (9/16 of GPDMA1_STOP) GPDMA1 channel 0 stop in debug. + @"GPDMA1_STOP[8]": u1, + /// (10/16 of GPDMA1_STOP) GPDMA1 channel 0 stop in debug. + @"GPDMA1_STOP[9]": u1, + /// (11/16 of GPDMA1_STOP) GPDMA1 channel 0 stop in debug. + @"GPDMA1_STOP[10]": u1, + /// (12/16 of GPDMA1_STOP) GPDMA1 channel 0 stop in debug. + @"GPDMA1_STOP[11]": u1, + /// (13/16 of GPDMA1_STOP) GPDMA1 channel 0 stop in debug. + @"GPDMA1_STOP[12]": u1, + /// (14/16 of GPDMA1_STOP) GPDMA1 channel 0 stop in debug. + @"GPDMA1_STOP[13]": u1, + /// (15/16 of GPDMA1_STOP) GPDMA1 channel 0 stop in debug. + @"GPDMA1_STOP[14]": u1, + /// (16/16 of GPDMA1_STOP) GPDMA1 channel 0 stop in debug. + @"GPDMA1_STOP[15]": u1, + /// (1/16 of GPDMA2_STOP) GPDMA2 channel 0 stop in debug. + @"GPDMA2_STOP[0]": u1, + /// (2/16 of GPDMA2_STOP) GPDMA2 channel 0 stop in debug. + @"GPDMA2_STOP[1]": u1, + /// (3/16 of GPDMA2_STOP) GPDMA2 channel 0 stop in debug. + @"GPDMA2_STOP[2]": u1, + /// (4/16 of GPDMA2_STOP) GPDMA2 channel 0 stop in debug. + @"GPDMA2_STOP[3]": u1, + /// (5/16 of GPDMA2_STOP) GPDMA2 channel 0 stop in debug. + @"GPDMA2_STOP[4]": u1, + /// (6/16 of GPDMA2_STOP) GPDMA2 channel 0 stop in debug. + @"GPDMA2_STOP[5]": u1, + /// (7/16 of GPDMA2_STOP) GPDMA2 channel 0 stop in debug. + @"GPDMA2_STOP[6]": u1, + /// (8/16 of GPDMA2_STOP) GPDMA2 channel 0 stop in debug. + @"GPDMA2_STOP[7]": u1, + /// (9/16 of GPDMA2_STOP) GPDMA2 channel 0 stop in debug. + @"GPDMA2_STOP[8]": u1, + /// (10/16 of GPDMA2_STOP) GPDMA2 channel 0 stop in debug. + @"GPDMA2_STOP[9]": u1, + /// (11/16 of GPDMA2_STOP) GPDMA2 channel 0 stop in debug. + @"GPDMA2_STOP[10]": u1, + /// (12/16 of GPDMA2_STOP) GPDMA2 channel 0 stop in debug. + @"GPDMA2_STOP[11]": u1, + /// (13/16 of GPDMA2_STOP) GPDMA2 channel 0 stop in debug. + @"GPDMA2_STOP[12]": u1, + /// (14/16 of GPDMA2_STOP) GPDMA2 channel 0 stop in debug. + @"GPDMA2_STOP[13]": u1, + /// (15/16 of GPDMA2_STOP) GPDMA2 channel 0 stop in debug. + @"GPDMA2_STOP[14]": u1, + /// (16/16 of GPDMA2_STOP) GPDMA2 channel 0 stop in debug. + @"GPDMA2_STOP[15]": u1, }), reserved252: [216]u8, /// DBGMCU status register. @@ -320204,15 +322682,75 @@ pub const types = struct { reserved128: [64]u8, /// DMAMUX request line multiplexer interrupt channel status register CSR: mmio.Mmio(packed struct(u32) { - /// Synchronization overrun event flag - SOF: u1, - padding: u31, + /// (1/16 of SOF) Synchronization overrun event flag + @"SOF[0]": u1, + /// (2/16 of SOF) Synchronization overrun event flag + @"SOF[1]": u1, + /// (3/16 of SOF) Synchronization overrun event flag + @"SOF[2]": u1, + /// (4/16 of SOF) Synchronization overrun event flag + @"SOF[3]": u1, + /// (5/16 of SOF) Synchronization overrun event flag + @"SOF[4]": u1, + /// (6/16 of SOF) Synchronization overrun event flag + @"SOF[5]": u1, + /// (7/16 of SOF) Synchronization overrun event flag + @"SOF[6]": u1, + /// (8/16 of SOF) Synchronization overrun event flag + @"SOF[7]": u1, + /// (9/16 of SOF) Synchronization overrun event flag + @"SOF[8]": u1, + /// (10/16 of SOF) Synchronization overrun event flag + @"SOF[9]": u1, + /// (11/16 of SOF) Synchronization overrun event flag + @"SOF[10]": u1, + /// (12/16 of SOF) Synchronization overrun event flag + @"SOF[11]": u1, + /// (13/16 of SOF) Synchronization overrun event flag + @"SOF[12]": u1, + /// (14/16 of SOF) Synchronization overrun event flag + @"SOF[13]": u1, + /// (15/16 of SOF) Synchronization overrun event flag + @"SOF[14]": u1, + /// (16/16 of SOF) Synchronization overrun event flag + @"SOF[15]": u1, + padding: u16, }), /// DMAMUX request line multiplexer interrupt clear flag register CFR: mmio.Mmio(packed struct(u32) { - /// Synchronization overrun event flag - SOF: u1, - padding: u31, + /// (1/16 of SOF) Synchronization overrun event flag + @"SOF[0]": u1, + /// (2/16 of SOF) Synchronization overrun event flag + @"SOF[1]": u1, + /// (3/16 of SOF) Synchronization overrun event flag + @"SOF[2]": u1, + /// (4/16 of SOF) Synchronization overrun event flag + @"SOF[3]": u1, + /// (5/16 of SOF) Synchronization overrun event flag + @"SOF[4]": u1, + /// (6/16 of SOF) Synchronization overrun event flag + @"SOF[5]": u1, + /// (7/16 of SOF) Synchronization overrun event flag + @"SOF[6]": u1, + /// (8/16 of SOF) Synchronization overrun event flag + @"SOF[7]": u1, + /// (9/16 of SOF) Synchronization overrun event flag + @"SOF[8]": u1, + /// (10/16 of SOF) Synchronization overrun event flag + @"SOF[9]": u1, + /// (11/16 of SOF) Synchronization overrun event flag + @"SOF[10]": u1, + /// (12/16 of SOF) Synchronization overrun event flag + @"SOF[11]": u1, + /// (13/16 of SOF) Synchronization overrun event flag + @"SOF[12]": u1, + /// (14/16 of SOF) Synchronization overrun event flag + @"SOF[13]": u1, + /// (15/16 of SOF) Synchronization overrun event flag + @"SOF[14]": u1, + /// (16/16 of SOF) Synchronization overrun event flag + @"SOF[15]": u1, + padding: u16, }), reserved256: [120]u8, /// DMAMux - DMA request generator channel x control register @@ -320234,15 +322772,43 @@ pub const types = struct { reserved320: [32]u8, /// DMAMux - DMA request generator status register RGSR: mmio.Mmio(packed struct(u32) { - /// Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register. - OF: u1, - padding: u31, + /// (1/8 of OF) Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register. + @"OF[0]": u1, + /// (2/8 of OF) Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register. + @"OF[1]": u1, + /// (3/8 of OF) Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register. + @"OF[2]": u1, + /// (4/8 of OF) Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register. + @"OF[3]": u1, + /// (5/8 of OF) Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register. + @"OF[4]": u1, + /// (6/8 of OF) Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register. + @"OF[5]": u1, + /// (7/8 of OF) Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register. + @"OF[6]": u1, + /// (8/8 of OF) Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register. + @"OF[7]": u1, + padding: u24, }), /// DMAMux - DMA request generator clear flag register RGCFR: mmio.Mmio(packed struct(u32) { - /// Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register. - OF: u1, - padding: u31, + /// (1/8 of OF) Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register. + @"OF[0]": u1, + /// (2/8 of OF) Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register. + @"OF[1]": u1, + /// (3/8 of OF) Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register. + @"OF[2]": u1, + /// (4/8 of OF) Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register. + @"OF[3]": u1, + /// (5/8 of OF) Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register. + @"OF[4]": u1, + /// (6/8 of OF) Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register. + @"OF[5]": u1, + /// (7/8 of OF) Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register. + @"OF[6]": u1, + /// (8/8 of OF) Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register. + @"OF[7]": u1, + padding: u24, }), }; }; @@ -323174,9 +325740,70 @@ pub const types = struct { }), /// Temperature sensor option register. OR: mmio.Mmio(packed struct(u32) { - /// general purpose option bits. - OP: u1, - padding: u31, + /// (1/32 of OP) general purpose option bits. + @"OP[0]": u1, + /// (2/32 of OP) general purpose option bits. + @"OP[1]": u1, + /// (3/32 of OP) general purpose option bits. + @"OP[2]": u1, + /// (4/32 of OP) general purpose option bits. + @"OP[3]": u1, + /// (5/32 of OP) general purpose option bits. + @"OP[4]": u1, + /// (6/32 of OP) general purpose option bits. + @"OP[5]": u1, + /// (7/32 of OP) general purpose option bits. + @"OP[6]": u1, + /// (8/32 of OP) general purpose option bits. + @"OP[7]": u1, + /// (9/32 of OP) general purpose option bits. + @"OP[8]": u1, + /// (10/32 of OP) general purpose option bits. + @"OP[9]": u1, + /// (11/32 of OP) general purpose option bits. + @"OP[10]": u1, + /// (12/32 of OP) general purpose option bits. + @"OP[11]": u1, + /// (13/32 of OP) general purpose option bits. + @"OP[12]": u1, + /// (14/32 of OP) general purpose option bits. + @"OP[13]": u1, + /// (15/32 of OP) general purpose option bits. + @"OP[14]": u1, + /// (16/32 of OP) general purpose option bits. + @"OP[15]": u1, + /// (17/32 of OP) general purpose option bits. + @"OP[16]": u1, + /// (18/32 of OP) general purpose option bits. + @"OP[17]": u1, + /// (19/32 of OP) general purpose option bits. + @"OP[18]": u1, + /// (20/32 of OP) general purpose option bits. + @"OP[19]": u1, + /// (21/32 of OP) general purpose option bits. + @"OP[20]": u1, + /// (22/32 of OP) general purpose option bits. + @"OP[21]": u1, + /// (23/32 of OP) general purpose option bits. + @"OP[22]": u1, + /// (24/32 of OP) general purpose option bits. + @"OP[23]": u1, + /// (25/32 of OP) general purpose option bits. + @"OP[24]": u1, + /// (26/32 of OP) general purpose option bits. + @"OP[25]": u1, + /// (27/32 of OP) general purpose option bits. + @"OP[26]": u1, + /// (28/32 of OP) general purpose option bits. + @"OP[27]": u1, + /// (29/32 of OP) general purpose option bits. + @"OP[28]": u1, + /// (30/32 of OP) general purpose option bits. + @"OP[29]": u1, + /// (31/32 of OP) general purpose option bits. + @"OP[30]": u1, + /// (32/32 of OP) general purpose option bits. + @"OP[31]": u1, }), }; }; @@ -323946,6 +326573,7 @@ pub const types = struct { BFD: BFD, /// Pass control frames PCF: PCF, + // skipped overlapping field SAIF at offset 7 bits /// Source address filter SAF: u1, /// Hash or perfect filter @@ -325121,6 +327749,7 @@ pub const types = struct { BFD: BFD, /// Pass control frames PCF: PCF, + // skipped overlapping field SAIF at offset 7 bits /// Source address filter SAF: u1, /// Hash or perfect filter @@ -326300,6 +328929,7 @@ pub const types = struct { BFD: BFD, /// Pass control frames PCF: PCF, + // skipped overlapping field SAIF at offset 7 bits /// Source address filter SAF: u1, /// Hash or perfect filter @@ -327820,9 +330450,15 @@ pub const types = struct { /// Auxiliary Snapshot FIFO Clear ATSFC: u1, reserved4: u3, - /// Auxiliary Snapshot 0-3 Enable - ATSEN: u1, - padding: u27, + /// (1/4 of ATSEN) Auxiliary Snapshot 0-3 Enable + @"ATSEN[0]": u1, + /// (2/4 of ATSEN) Auxiliary Snapshot 0-3 Enable + @"ATSEN[1]": u1, + /// (3/4 of ATSEN) Auxiliary Snapshot 0-3 Enable + @"ATSEN[2]": u1, + /// (4/4 of ATSEN) Auxiliary Snapshot 0-3 Enable + @"ATSEN[3]": u1, + padding: u24, }), reserved2888: [4]u8, /// Auxiliary timestamp nanoseconds register @@ -328081,53 +330717,485 @@ pub const types = struct { pub const EXTI = extern struct { /// Rising Trigger selection register RTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Falling Trigger selection register FTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Software interrupt event register SWIER: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Rising pending register RPR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Falling pending register FPR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), reserved96: [76]u8, /// Configuration register EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI configuration bits - EXTI: u8, - padding: u24, + /// (1/4 of EXTI) EXTI configuration bits + @"EXTI[0]": u8, + /// (2/4 of EXTI) EXTI configuration bits + @"EXTI[1]": u8, + /// (3/4 of EXTI) EXTI configuration bits + @"EXTI[2]": u8, + /// (4/4 of EXTI) EXTI configuration bits + @"EXTI[3]": u8, }), reserved128: [16]u8, /// Interrupt mask register IMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Event mask register EMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), }; }; @@ -328137,53 +331205,485 @@ pub const types = struct { pub const EXTI = extern struct { /// Rising Trigger selection register RTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Falling Trigger selection register FTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Software interrupt event register SWIER: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Rising pending register RPR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Falling pending register FPR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), reserved96: [76]u8, /// Configuration register EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI configuration bits - EXTI: u8, - padding: u24, + /// (1/4 of EXTI) EXTI configuration bits + @"EXTI[0]": u8, + /// (2/4 of EXTI) EXTI configuration bits + @"EXTI[1]": u8, + /// (3/4 of EXTI) EXTI configuration bits + @"EXTI[2]": u8, + /// (4/4 of EXTI) EXTI configuration bits + @"EXTI[3]": u8, }), reserved128: [16]u8, /// Interrupt mask register IMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Event mask register EMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), }; }; @@ -328193,52 +331693,484 @@ pub const types = struct { pub const EXTI = extern struct { /// rising trigger selection register RTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// falling trigger selection register FTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// software interrupt event register SWIER: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// rising edge pending register RPR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// falling edge pending register FPR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// security configuration register SECCFGR: mmio.Mmio(packed struct(u32) { - /// Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. - SEC: u1, - padding: u31, + /// (1/32 of SEC) Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + @"SEC[0]": u1, + /// (2/32 of SEC) Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + @"SEC[1]": u1, + /// (3/32 of SEC) Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + @"SEC[2]": u1, + /// (4/32 of SEC) Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + @"SEC[3]": u1, + /// (5/32 of SEC) Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + @"SEC[4]": u1, + /// (6/32 of SEC) Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + @"SEC[5]": u1, + /// (7/32 of SEC) Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + @"SEC[6]": u1, + /// (8/32 of SEC) Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + @"SEC[7]": u1, + /// (9/32 of SEC) Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + @"SEC[8]": u1, + /// (10/32 of SEC) Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + @"SEC[9]": u1, + /// (11/32 of SEC) Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + @"SEC[10]": u1, + /// (12/32 of SEC) Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + @"SEC[11]": u1, + /// (13/32 of SEC) Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + @"SEC[12]": u1, + /// (14/32 of SEC) Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + @"SEC[13]": u1, + /// (15/32 of SEC) Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + @"SEC[14]": u1, + /// (16/32 of SEC) Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + @"SEC[15]": u1, + /// (17/32 of SEC) Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + @"SEC[16]": u1, + /// (18/32 of SEC) Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + @"SEC[17]": u1, + /// (19/32 of SEC) Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + @"SEC[18]": u1, + /// (20/32 of SEC) Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + @"SEC[19]": u1, + /// (21/32 of SEC) Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + @"SEC[20]": u1, + /// (22/32 of SEC) Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + @"SEC[21]": u1, + /// (23/32 of SEC) Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + @"SEC[22]": u1, + /// (24/32 of SEC) Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + @"SEC[23]": u1, + /// (25/32 of SEC) Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + @"SEC[24]": u1, + /// (26/32 of SEC) Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + @"SEC[25]": u1, + /// (27/32 of SEC) Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + @"SEC[26]": u1, + /// (28/32 of SEC) Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + @"SEC[27]": u1, + /// (29/32 of SEC) Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + @"SEC[28]": u1, + /// (30/32 of SEC) Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + @"SEC[29]": u1, + /// (31/32 of SEC) Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + @"SEC[30]": u1, + /// (32/32 of SEC) Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. + @"SEC[31]": u1, }), /// privilege configuration register PRIVCFGR: mmio.Mmio(packed struct(u32) { - /// Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. - PRIV: u1, - padding: u31, + /// (1/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[0]": u1, + /// (2/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[1]": u1, + /// (3/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[2]": u1, + /// (4/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[3]": u1, + /// (5/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[4]": u1, + /// (6/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[5]": u1, + /// (7/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[6]": u1, + /// (8/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[7]": u1, + /// (9/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[8]": u1, + /// (10/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[9]": u1, + /// (11/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[10]": u1, + /// (12/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[11]": u1, + /// (13/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[12]": u1, + /// (14/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[13]": u1, + /// (15/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[14]": u1, + /// (16/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[15]": u1, + /// (17/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[16]": u1, + /// (18/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[17]": u1, + /// (19/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[18]": u1, + /// (20/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[19]": u1, + /// (21/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[20]": u1, + /// (22/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[21]": u1, + /// (23/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[22]": u1, + /// (24/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[23]": u1, + /// (25/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[24]": u1, + /// (26/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[25]": u1, + /// (27/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[26]": u1, + /// (28/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[27]": u1, + /// (29/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[28]": u1, + /// (30/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[29]": u1, + /// (31/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[30]": u1, + /// (32/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[31]": u1, }), reserved96: [68]u8, /// external interrupt selection register EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI12 GPIO port selection These bits are written by software to select the source input for EXTI12 external interrupt. When EXTI_PRIVCFGR.PRIV12 is disabled, EXTI12 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV12 is enabled, EXTI12 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved - EXTI: u8, - padding: u24, + /// (1/4 of EXTI) EXTI12 GPIO port selection These bits are written by software to select the source input for EXTI12 external interrupt. When EXTI_PRIVCFGR.PRIV12 is disabled, EXTI12 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV12 is enabled, EXTI12 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved + @"EXTI[0]": u8, + /// (2/4 of EXTI) EXTI12 GPIO port selection These bits are written by software to select the source input for EXTI12 external interrupt. When EXTI_PRIVCFGR.PRIV12 is disabled, EXTI12 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV12 is enabled, EXTI12 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved + @"EXTI[1]": u8, + /// (3/4 of EXTI) EXTI12 GPIO port selection These bits are written by software to select the source input for EXTI12 external interrupt. When EXTI_PRIVCFGR.PRIV12 is disabled, EXTI12 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV12 is enabled, EXTI12 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved + @"EXTI[2]": u8, + /// (4/4 of EXTI) EXTI12 GPIO port selection These bits are written by software to select the source input for EXTI12 external interrupt. When EXTI_PRIVCFGR.PRIV12 is disabled, EXTI12 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV12 is enabled, EXTI12 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved + @"EXTI[3]": u8, }), /// lock register LOCKR: mmio.Mmio(packed struct(u32) { @@ -328249,15 +332181,137 @@ pub const types = struct { reserved128: [12]u8, /// CPU wakeup with interrupt mask register IMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// CPU wakeup with event mask register EMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), }; }; @@ -328267,60 +332321,553 @@ pub const types = struct { pub const EXTI = extern struct { /// rising trigger selection register RTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// falling trigger selection register FTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// software interrupt event register SWIER: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// rising edge pending register RPR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// falling edge pending register FPR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), reserved24: [4]u8, /// privilege configuration register PRIVCFGR: mmio.Mmio(packed struct(u32) { - /// Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. - PRIV: u1, - padding: u31, + /// (1/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[0]": u1, + /// (2/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[1]": u1, + /// (3/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[2]": u1, + /// (4/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[3]": u1, + /// (5/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[4]": u1, + /// (6/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[5]": u1, + /// (7/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[6]": u1, + /// (8/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[7]": u1, + /// (9/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[8]": u1, + /// (10/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[9]": u1, + /// (11/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[10]": u1, + /// (12/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[11]": u1, + /// (13/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[12]": u1, + /// (14/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[13]": u1, + /// (15/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[14]": u1, + /// (16/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[15]": u1, + /// (17/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[16]": u1, + /// (18/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[17]": u1, + /// (19/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[18]": u1, + /// (20/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[19]": u1, + /// (21/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[20]": u1, + /// (22/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[21]": u1, + /// (23/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[22]": u1, + /// (24/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[23]": u1, + /// (25/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[24]": u1, + /// (26/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[25]": u1, + /// (27/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[26]": u1, + /// (28/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[27]": u1, + /// (29/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[28]": u1, + /// (30/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[29]": u1, + /// (31/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[30]": u1, + /// (32/32 of PRIV) Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. + @"PRIV[31]": u1, }), reserved96: [68]u8, /// external interrupt selection register EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI12 GPIO port selection These bits are written by software to select the source input for EXTI12 external interrupt. When EXTI_PRIVCFGR.PRIV12 is disabled, EXTI12 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV12 is enabled, EXTI12 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved - EXTI: u8, - padding: u24, + /// (1/4 of EXTI) EXTI12 GPIO port selection These bits are written by software to select the source input for EXTI12 external interrupt. When EXTI_PRIVCFGR.PRIV12 is disabled, EXTI12 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV12 is enabled, EXTI12 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved + @"EXTI[0]": u8, + /// (2/4 of EXTI) EXTI12 GPIO port selection These bits are written by software to select the source input for EXTI12 external interrupt. When EXTI_PRIVCFGR.PRIV12 is disabled, EXTI12 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV12 is enabled, EXTI12 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved + @"EXTI[1]": u8, + /// (3/4 of EXTI) EXTI12 GPIO port selection These bits are written by software to select the source input for EXTI12 external interrupt. When EXTI_PRIVCFGR.PRIV12 is disabled, EXTI12 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV12 is enabled, EXTI12 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved + @"EXTI[2]": u8, + /// (4/4 of EXTI) EXTI12 GPIO port selection These bits are written by software to select the source input for EXTI12 external interrupt. When EXTI_PRIVCFGR.PRIV12 is disabled, EXTI12 can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIV12 is enabled, EXTI12 can only be accessed with privileged access. Unprivileged write to this bit is discarded. Others: reserved + @"EXTI[3]": u8, }), reserved128: [16]u8, /// CPU wakeup with interrupt mask register IMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// CPU wakeup with event mask register EMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), }; }; @@ -328330,40 +332877,406 @@ pub const types = struct { pub const EXTI = extern struct { /// Rising Trigger selection register RTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Falling Trigger selection register FTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Software interrupt event register SWIER: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), reserved128: [116]u8, /// Interrupt mask register IMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Event mask register EMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Pending register PR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), }; }; @@ -328373,52 +333286,484 @@ pub const types = struct { pub const EXTI = extern struct { /// Rising Trigger selection register RTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Falling Trigger selection register FTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Software interrupt event register SWIER: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Rising pending register RPR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Falling pending register FPR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Security configuration register SECCFGR: mmio.Mmio(packed struct(u32) { - /// Security enable on event input x - SEC: u1, - padding: u31, + /// (1/32 of SEC) Security enable on event input x + @"SEC[0]": u1, + /// (2/32 of SEC) Security enable on event input x + @"SEC[1]": u1, + /// (3/32 of SEC) Security enable on event input x + @"SEC[2]": u1, + /// (4/32 of SEC) Security enable on event input x + @"SEC[3]": u1, + /// (5/32 of SEC) Security enable on event input x + @"SEC[4]": u1, + /// (6/32 of SEC) Security enable on event input x + @"SEC[5]": u1, + /// (7/32 of SEC) Security enable on event input x + @"SEC[6]": u1, + /// (8/32 of SEC) Security enable on event input x + @"SEC[7]": u1, + /// (9/32 of SEC) Security enable on event input x + @"SEC[8]": u1, + /// (10/32 of SEC) Security enable on event input x + @"SEC[9]": u1, + /// (11/32 of SEC) Security enable on event input x + @"SEC[10]": u1, + /// (12/32 of SEC) Security enable on event input x + @"SEC[11]": u1, + /// (13/32 of SEC) Security enable on event input x + @"SEC[12]": u1, + /// (14/32 of SEC) Security enable on event input x + @"SEC[13]": u1, + /// (15/32 of SEC) Security enable on event input x + @"SEC[14]": u1, + /// (16/32 of SEC) Security enable on event input x + @"SEC[15]": u1, + /// (17/32 of SEC) Security enable on event input x + @"SEC[16]": u1, + /// (18/32 of SEC) Security enable on event input x + @"SEC[17]": u1, + /// (19/32 of SEC) Security enable on event input x + @"SEC[18]": u1, + /// (20/32 of SEC) Security enable on event input x + @"SEC[19]": u1, + /// (21/32 of SEC) Security enable on event input x + @"SEC[20]": u1, + /// (22/32 of SEC) Security enable on event input x + @"SEC[21]": u1, + /// (23/32 of SEC) Security enable on event input x + @"SEC[22]": u1, + /// (24/32 of SEC) Security enable on event input x + @"SEC[23]": u1, + /// (25/32 of SEC) Security enable on event input x + @"SEC[24]": u1, + /// (26/32 of SEC) Security enable on event input x + @"SEC[25]": u1, + /// (27/32 of SEC) Security enable on event input x + @"SEC[26]": u1, + /// (28/32 of SEC) Security enable on event input x + @"SEC[27]": u1, + /// (29/32 of SEC) Security enable on event input x + @"SEC[28]": u1, + /// (30/32 of SEC) Security enable on event input x + @"SEC[29]": u1, + /// (31/32 of SEC) Security enable on event input x + @"SEC[30]": u1, + /// (32/32 of SEC) Security enable on event input x + @"SEC[31]": u1, }), /// Privilege configuration register PRIVCFGR: mmio.Mmio(packed struct(u32) { - /// Security enable on event input x - PRIV: u1, - padding: u31, + /// (1/32 of PRIV) Security enable on event input x + @"PRIV[0]": u1, + /// (2/32 of PRIV) Security enable on event input x + @"PRIV[1]": u1, + /// (3/32 of PRIV) Security enable on event input x + @"PRIV[2]": u1, + /// (4/32 of PRIV) Security enable on event input x + @"PRIV[3]": u1, + /// (5/32 of PRIV) Security enable on event input x + @"PRIV[4]": u1, + /// (6/32 of PRIV) Security enable on event input x + @"PRIV[5]": u1, + /// (7/32 of PRIV) Security enable on event input x + @"PRIV[6]": u1, + /// (8/32 of PRIV) Security enable on event input x + @"PRIV[7]": u1, + /// (9/32 of PRIV) Security enable on event input x + @"PRIV[8]": u1, + /// (10/32 of PRIV) Security enable on event input x + @"PRIV[9]": u1, + /// (11/32 of PRIV) Security enable on event input x + @"PRIV[10]": u1, + /// (12/32 of PRIV) Security enable on event input x + @"PRIV[11]": u1, + /// (13/32 of PRIV) Security enable on event input x + @"PRIV[12]": u1, + /// (14/32 of PRIV) Security enable on event input x + @"PRIV[13]": u1, + /// (15/32 of PRIV) Security enable on event input x + @"PRIV[14]": u1, + /// (16/32 of PRIV) Security enable on event input x + @"PRIV[15]": u1, + /// (17/32 of PRIV) Security enable on event input x + @"PRIV[16]": u1, + /// (18/32 of PRIV) Security enable on event input x + @"PRIV[17]": u1, + /// (19/32 of PRIV) Security enable on event input x + @"PRIV[18]": u1, + /// (20/32 of PRIV) Security enable on event input x + @"PRIV[19]": u1, + /// (21/32 of PRIV) Security enable on event input x + @"PRIV[20]": u1, + /// (22/32 of PRIV) Security enable on event input x + @"PRIV[21]": u1, + /// (23/32 of PRIV) Security enable on event input x + @"PRIV[22]": u1, + /// (24/32 of PRIV) Security enable on event input x + @"PRIV[23]": u1, + /// (25/32 of PRIV) Security enable on event input x + @"PRIV[24]": u1, + /// (26/32 of PRIV) Security enable on event input x + @"PRIV[25]": u1, + /// (27/32 of PRIV) Security enable on event input x + @"PRIV[26]": u1, + /// (28/32 of PRIV) Security enable on event input x + @"PRIV[27]": u1, + /// (29/32 of PRIV) Security enable on event input x + @"PRIV[28]": u1, + /// (30/32 of PRIV) Security enable on event input x + @"PRIV[29]": u1, + /// (31/32 of PRIV) Security enable on event input x + @"PRIV[30]": u1, + /// (32/32 of PRIV) Security enable on event input x + @"PRIV[31]": u1, }), reserved96: [68]u8, /// Configuration register EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI configuration bits - EXTI: u8, - padding: u24, + /// (1/4 of EXTI) EXTI configuration bits + @"EXTI[0]": u8, + /// (2/4 of EXTI) EXTI configuration bits + @"EXTI[1]": u8, + /// (3/4 of EXTI) EXTI configuration bits + @"EXTI[2]": u8, + /// (4/4 of EXTI) EXTI configuration bits + @"EXTI[3]": u8, }), /// EXTI lock register LOCKRG: mmio.Mmio(packed struct(u32) { @@ -328429,15 +333774,137 @@ pub const types = struct { reserved128: [12]u8, /// Interrupt mask register IMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Event mask register EMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), }; }; @@ -328447,53 +333914,485 @@ pub const types = struct { pub const EXTI = extern struct { /// Rising Trigger selection register RTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Falling Trigger selection register FTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Software interrupt event register SWIER: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Rising pending register RPR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Falling pending register FPR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), reserved96: [76]u8, /// Configuration register EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI configuration bits - EXTI: u8, - padding: u24, + /// (1/4 of EXTI) EXTI configuration bits + @"EXTI[0]": u8, + /// (2/4 of EXTI) EXTI configuration bits + @"EXTI[1]": u8, + /// (3/4 of EXTI) EXTI configuration bits + @"EXTI[2]": u8, + /// (4/4 of EXTI) EXTI configuration bits + @"EXTI[3]": u8, }), reserved128: [16]u8, /// Interrupt mask register IMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Event mask register EMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), }; }; @@ -328503,52 +334402,484 @@ pub const types = struct { pub const EXTI = extern struct { /// Rising Trigger selection register RTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Falling Trigger selection register FTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Software interrupt event register SWIER: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Rising pending register RPR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Falling pending register FPR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Security configuration register SECCFGR: mmio.Mmio(packed struct(u32) { - /// Security enable on event input x - SEC: u1, - padding: u31, + /// (1/32 of SEC) Security enable on event input x + @"SEC[0]": u1, + /// (2/32 of SEC) Security enable on event input x + @"SEC[1]": u1, + /// (3/32 of SEC) Security enable on event input x + @"SEC[2]": u1, + /// (4/32 of SEC) Security enable on event input x + @"SEC[3]": u1, + /// (5/32 of SEC) Security enable on event input x + @"SEC[4]": u1, + /// (6/32 of SEC) Security enable on event input x + @"SEC[5]": u1, + /// (7/32 of SEC) Security enable on event input x + @"SEC[6]": u1, + /// (8/32 of SEC) Security enable on event input x + @"SEC[7]": u1, + /// (9/32 of SEC) Security enable on event input x + @"SEC[8]": u1, + /// (10/32 of SEC) Security enable on event input x + @"SEC[9]": u1, + /// (11/32 of SEC) Security enable on event input x + @"SEC[10]": u1, + /// (12/32 of SEC) Security enable on event input x + @"SEC[11]": u1, + /// (13/32 of SEC) Security enable on event input x + @"SEC[12]": u1, + /// (14/32 of SEC) Security enable on event input x + @"SEC[13]": u1, + /// (15/32 of SEC) Security enable on event input x + @"SEC[14]": u1, + /// (16/32 of SEC) Security enable on event input x + @"SEC[15]": u1, + /// (17/32 of SEC) Security enable on event input x + @"SEC[16]": u1, + /// (18/32 of SEC) Security enable on event input x + @"SEC[17]": u1, + /// (19/32 of SEC) Security enable on event input x + @"SEC[18]": u1, + /// (20/32 of SEC) Security enable on event input x + @"SEC[19]": u1, + /// (21/32 of SEC) Security enable on event input x + @"SEC[20]": u1, + /// (22/32 of SEC) Security enable on event input x + @"SEC[21]": u1, + /// (23/32 of SEC) Security enable on event input x + @"SEC[22]": u1, + /// (24/32 of SEC) Security enable on event input x + @"SEC[23]": u1, + /// (25/32 of SEC) Security enable on event input x + @"SEC[24]": u1, + /// (26/32 of SEC) Security enable on event input x + @"SEC[25]": u1, + /// (27/32 of SEC) Security enable on event input x + @"SEC[26]": u1, + /// (28/32 of SEC) Security enable on event input x + @"SEC[27]": u1, + /// (29/32 of SEC) Security enable on event input x + @"SEC[28]": u1, + /// (30/32 of SEC) Security enable on event input x + @"SEC[29]": u1, + /// (31/32 of SEC) Security enable on event input x + @"SEC[30]": u1, + /// (32/32 of SEC) Security enable on event input x + @"SEC[31]": u1, }), /// Privilege configuration register PRIVCFGR: mmio.Mmio(packed struct(u32) { - /// Security enable on event input x - PRIV: u1, - padding: u31, + /// (1/32 of PRIV) Security enable on event input x + @"PRIV[0]": u1, + /// (2/32 of PRIV) Security enable on event input x + @"PRIV[1]": u1, + /// (3/32 of PRIV) Security enable on event input x + @"PRIV[2]": u1, + /// (4/32 of PRIV) Security enable on event input x + @"PRIV[3]": u1, + /// (5/32 of PRIV) Security enable on event input x + @"PRIV[4]": u1, + /// (6/32 of PRIV) Security enable on event input x + @"PRIV[5]": u1, + /// (7/32 of PRIV) Security enable on event input x + @"PRIV[6]": u1, + /// (8/32 of PRIV) Security enable on event input x + @"PRIV[7]": u1, + /// (9/32 of PRIV) Security enable on event input x + @"PRIV[8]": u1, + /// (10/32 of PRIV) Security enable on event input x + @"PRIV[9]": u1, + /// (11/32 of PRIV) Security enable on event input x + @"PRIV[10]": u1, + /// (12/32 of PRIV) Security enable on event input x + @"PRIV[11]": u1, + /// (13/32 of PRIV) Security enable on event input x + @"PRIV[12]": u1, + /// (14/32 of PRIV) Security enable on event input x + @"PRIV[13]": u1, + /// (15/32 of PRIV) Security enable on event input x + @"PRIV[14]": u1, + /// (16/32 of PRIV) Security enable on event input x + @"PRIV[15]": u1, + /// (17/32 of PRIV) Security enable on event input x + @"PRIV[16]": u1, + /// (18/32 of PRIV) Security enable on event input x + @"PRIV[17]": u1, + /// (19/32 of PRIV) Security enable on event input x + @"PRIV[18]": u1, + /// (20/32 of PRIV) Security enable on event input x + @"PRIV[19]": u1, + /// (21/32 of PRIV) Security enable on event input x + @"PRIV[20]": u1, + /// (22/32 of PRIV) Security enable on event input x + @"PRIV[21]": u1, + /// (23/32 of PRIV) Security enable on event input x + @"PRIV[22]": u1, + /// (24/32 of PRIV) Security enable on event input x + @"PRIV[23]": u1, + /// (25/32 of PRIV) Security enable on event input x + @"PRIV[24]": u1, + /// (26/32 of PRIV) Security enable on event input x + @"PRIV[25]": u1, + /// (27/32 of PRIV) Security enable on event input x + @"PRIV[26]": u1, + /// (28/32 of PRIV) Security enable on event input x + @"PRIV[27]": u1, + /// (29/32 of PRIV) Security enable on event input x + @"PRIV[28]": u1, + /// (30/32 of PRIV) Security enable on event input x + @"PRIV[29]": u1, + /// (31/32 of PRIV) Security enable on event input x + @"PRIV[30]": u1, + /// (32/32 of PRIV) Security enable on event input x + @"PRIV[31]": u1, }), reserved96: [68]u8, /// Configuration register EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI configuration bits - EXTI: u8, - padding: u24, + /// (1/4 of EXTI) EXTI configuration bits + @"EXTI[0]": u8, + /// (2/4 of EXTI) EXTI configuration bits + @"EXTI[1]": u8, + /// (3/4 of EXTI) EXTI configuration bits + @"EXTI[2]": u8, + /// (4/4 of EXTI) EXTI configuration bits + @"EXTI[3]": u8, }), /// EXTI lock register LOCKRG: mmio.Mmio(packed struct(u32) { @@ -328559,15 +334890,137 @@ pub const types = struct { reserved128: [12]u8, /// Interrupt mask register IMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Event mask register EMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), }; }; @@ -328577,39 +335030,405 @@ pub const types = struct { pub const EXTI = extern struct { /// Interrupt mask register IMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Interrupt mask register EMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Rising Trigger selection register RTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Falling Trigger selection register FTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Software interrupt event register SWIER: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Pending register PR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), }; }; @@ -328619,15 +335438,137 @@ pub const types = struct { pub const CPU = extern struct { /// CPU x interrupt mask register IMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// CPU x event mask register EMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), }; @@ -328635,27 +335576,271 @@ pub const types = struct { pub const EXTI = extern struct { /// rising trigger selection register RTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// falling trigger selection register FTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// software interrupt event register SWIER: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// EXTI pending register PR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), reserved128: [112]u8, /// CPU specific registers @@ -328668,40 +335853,406 @@ pub const types = struct { pub const EXTI = extern struct { /// Rising Trigger selection register RTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Falling Trigger selection register FTSR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Software interrupt event register SWIER: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Pending register PR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), reserved128: [112]u8, /// Interrupt mask register IMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), /// Event mask register EMR: mmio.Mmio(packed struct(u32) { - /// EXTI line - LINE: u1, - padding: u31, + /// (1/32 of LINE) EXTI line + @"LINE[0]": u1, + /// (2/32 of LINE) EXTI line + @"LINE[1]": u1, + /// (3/32 of LINE) EXTI line + @"LINE[2]": u1, + /// (4/32 of LINE) EXTI line + @"LINE[3]": u1, + /// (5/32 of LINE) EXTI line + @"LINE[4]": u1, + /// (6/32 of LINE) EXTI line + @"LINE[5]": u1, + /// (7/32 of LINE) EXTI line + @"LINE[6]": u1, + /// (8/32 of LINE) EXTI line + @"LINE[7]": u1, + /// (9/32 of LINE) EXTI line + @"LINE[8]": u1, + /// (10/32 of LINE) EXTI line + @"LINE[9]": u1, + /// (11/32 of LINE) EXTI line + @"LINE[10]": u1, + /// (12/32 of LINE) EXTI line + @"LINE[11]": u1, + /// (13/32 of LINE) EXTI line + @"LINE[12]": u1, + /// (14/32 of LINE) EXTI line + @"LINE[13]": u1, + /// (15/32 of LINE) EXTI line + @"LINE[14]": u1, + /// (16/32 of LINE) EXTI line + @"LINE[15]": u1, + /// (17/32 of LINE) EXTI line + @"LINE[16]": u1, + /// (18/32 of LINE) EXTI line + @"LINE[17]": u1, + /// (19/32 of LINE) EXTI line + @"LINE[18]": u1, + /// (20/32 of LINE) EXTI line + @"LINE[19]": u1, + /// (21/32 of LINE) EXTI line + @"LINE[20]": u1, + /// (22/32 of LINE) EXTI line + @"LINE[21]": u1, + /// (23/32 of LINE) EXTI line + @"LINE[22]": u1, + /// (24/32 of LINE) EXTI line + @"LINE[23]": u1, + /// (25/32 of LINE) EXTI line + @"LINE[24]": u1, + /// (26/32 of LINE) EXTI line + @"LINE[25]": u1, + /// (27/32 of LINE) EXTI line + @"LINE[26]": u1, + /// (28/32 of LINE) EXTI line + @"LINE[27]": u1, + /// (29/32 of LINE) EXTI line + @"LINE[28]": u1, + /// (30/32 of LINE) EXTI line + @"LINE[29]": u1, + /// (31/32 of LINE) EXTI line + @"LINE[30]": u1, + /// (32/32 of LINE) EXTI line + @"LINE[31]": u1, }), }; }; @@ -333579,16 +341130,138 @@ pub const types = struct { }), /// Write Protection Register 1 WRPROT: mmio.Mmio(packed struct(u32) { - /// Write Protection - WRPROT: u1, - padding: u31, + /// (1/32 of WRPROT) Write Protection + @"WRPROT[0]": u1, + /// (2/32 of WRPROT) Write Protection + @"WRPROT[1]": u1, + /// (3/32 of WRPROT) Write Protection + @"WRPROT[2]": u1, + /// (4/32 of WRPROT) Write Protection + @"WRPROT[3]": u1, + /// (5/32 of WRPROT) Write Protection + @"WRPROT[4]": u1, + /// (6/32 of WRPROT) Write Protection + @"WRPROT[5]": u1, + /// (7/32 of WRPROT) Write Protection + @"WRPROT[6]": u1, + /// (8/32 of WRPROT) Write Protection + @"WRPROT[7]": u1, + /// (9/32 of WRPROT) Write Protection + @"WRPROT[8]": u1, + /// (10/32 of WRPROT) Write Protection + @"WRPROT[9]": u1, + /// (11/32 of WRPROT) Write Protection + @"WRPROT[10]": u1, + /// (12/32 of WRPROT) Write Protection + @"WRPROT[11]": u1, + /// (13/32 of WRPROT) Write Protection + @"WRPROT[12]": u1, + /// (14/32 of WRPROT) Write Protection + @"WRPROT[13]": u1, + /// (15/32 of WRPROT) Write Protection + @"WRPROT[14]": u1, + /// (16/32 of WRPROT) Write Protection + @"WRPROT[15]": u1, + /// (17/32 of WRPROT) Write Protection + @"WRPROT[16]": u1, + /// (18/32 of WRPROT) Write Protection + @"WRPROT[17]": u1, + /// (19/32 of WRPROT) Write Protection + @"WRPROT[18]": u1, + /// (20/32 of WRPROT) Write Protection + @"WRPROT[19]": u1, + /// (21/32 of WRPROT) Write Protection + @"WRPROT[20]": u1, + /// (22/32 of WRPROT) Write Protection + @"WRPROT[21]": u1, + /// (23/32 of WRPROT) Write Protection + @"WRPROT[22]": u1, + /// (24/32 of WRPROT) Write Protection + @"WRPROT[23]": u1, + /// (25/32 of WRPROT) Write Protection + @"WRPROT[24]": u1, + /// (26/32 of WRPROT) Write Protection + @"WRPROT[25]": u1, + /// (27/32 of WRPROT) Write Protection + @"WRPROT[26]": u1, + /// (28/32 of WRPROT) Write Protection + @"WRPROT[27]": u1, + /// (29/32 of WRPROT) Write Protection + @"WRPROT[28]": u1, + /// (30/32 of WRPROT) Write Protection + @"WRPROT[29]": u1, + /// (31/32 of WRPROT) Write Protection + @"WRPROT[30]": u1, + /// (32/32 of WRPROT) Write Protection + @"WRPROT[31]": u1, }), reserved128: [92]u8, /// Write Protection Register 2 WRPROT2: mmio.Mmio(packed struct(u32) { - /// Write Protection - WRPROT: u1, - padding: u31, + /// (1/32 of WRPROT) Write Protection + @"WRPROT[0]": u1, + /// (2/32 of WRPROT) Write Protection + @"WRPROT[1]": u1, + /// (3/32 of WRPROT) Write Protection + @"WRPROT[2]": u1, + /// (4/32 of WRPROT) Write Protection + @"WRPROT[3]": u1, + /// (5/32 of WRPROT) Write Protection + @"WRPROT[4]": u1, + /// (6/32 of WRPROT) Write Protection + @"WRPROT[5]": u1, + /// (7/32 of WRPROT) Write Protection + @"WRPROT[6]": u1, + /// (8/32 of WRPROT) Write Protection + @"WRPROT[7]": u1, + /// (9/32 of WRPROT) Write Protection + @"WRPROT[8]": u1, + /// (10/32 of WRPROT) Write Protection + @"WRPROT[9]": u1, + /// (11/32 of WRPROT) Write Protection + @"WRPROT[10]": u1, + /// (12/32 of WRPROT) Write Protection + @"WRPROT[11]": u1, + /// (13/32 of WRPROT) Write Protection + @"WRPROT[12]": u1, + /// (14/32 of WRPROT) Write Protection + @"WRPROT[13]": u1, + /// (15/32 of WRPROT) Write Protection + @"WRPROT[14]": u1, + /// (16/32 of WRPROT) Write Protection + @"WRPROT[15]": u1, + /// (17/32 of WRPROT) Write Protection + @"WRPROT[16]": u1, + /// (18/32 of WRPROT) Write Protection + @"WRPROT[17]": u1, + /// (19/32 of WRPROT) Write Protection + @"WRPROT[18]": u1, + /// (20/32 of WRPROT) Write Protection + @"WRPROT[19]": u1, + /// (21/32 of WRPROT) Write Protection + @"WRPROT[20]": u1, + /// (22/32 of WRPROT) Write Protection + @"WRPROT[21]": u1, + /// (23/32 of WRPROT) Write Protection + @"WRPROT[22]": u1, + /// (24/32 of WRPROT) Write Protection + @"WRPROT[23]": u1, + /// (25/32 of WRPROT) Write Protection + @"WRPROT[24]": u1, + /// (26/32 of WRPROT) Write Protection + @"WRPROT[25]": u1, + /// (27/32 of WRPROT) Write Protection + @"WRPROT[26]": u1, + /// (28/32 of WRPROT) Write Protection + @"WRPROT[27]": u1, + /// (29/32 of WRPROT) Write Protection + @"WRPROT[28]": u1, + /// (30/32 of WRPROT) Write Protection + @"WRPROT[29]": u1, + /// (31/32 of WRPROT) Write Protection + @"WRPROT[30]": u1, + /// (32/32 of WRPROT) Write Protection + @"WRPROT[31]": u1, }), }; }; @@ -333773,13 +341446,15 @@ pub const types = struct { PG: u1, /// Page erase PER: u1, - /// Bank 1 Mass erase - MER: u1, + /// (1/2 of MER) Bank 1 Mass erase + @"MER[0]": u1, /// Page number PNB: u8, /// Bank erase BKER: u1, - reserved16: u4, + reserved15: u3, + /// (2/2 of MER) Bank 1 Mass erase + @"MER[1]": u1, /// Start START: u1, /// Options modification start @@ -336932,8 +344607,70 @@ pub const types = struct { OEM2KEYR2: u32, /// secure block based register 1 SECBBR: [4]mmio.Mmio(packed struct(u32) { - BLOCK: u1, - padding: u31, + /// (1/32 of BLOCK) + @"BLOCK[0]": u1, + /// (2/32 of BLOCK) + @"BLOCK[1]": u1, + /// (3/32 of BLOCK) + @"BLOCK[2]": u1, + /// (4/32 of BLOCK) + @"BLOCK[3]": u1, + /// (5/32 of BLOCK) + @"BLOCK[4]": u1, + /// (6/32 of BLOCK) + @"BLOCK[5]": u1, + /// (7/32 of BLOCK) + @"BLOCK[6]": u1, + /// (8/32 of BLOCK) + @"BLOCK[7]": u1, + /// (9/32 of BLOCK) + @"BLOCK[8]": u1, + /// (10/32 of BLOCK) + @"BLOCK[9]": u1, + /// (11/32 of BLOCK) + @"BLOCK[10]": u1, + /// (12/32 of BLOCK) + @"BLOCK[11]": u1, + /// (13/32 of BLOCK) + @"BLOCK[12]": u1, + /// (14/32 of BLOCK) + @"BLOCK[13]": u1, + /// (15/32 of BLOCK) + @"BLOCK[14]": u1, + /// (16/32 of BLOCK) + @"BLOCK[15]": u1, + /// (17/32 of BLOCK) + @"BLOCK[16]": u1, + /// (18/32 of BLOCK) + @"BLOCK[17]": u1, + /// (19/32 of BLOCK) + @"BLOCK[18]": u1, + /// (20/32 of BLOCK) + @"BLOCK[19]": u1, + /// (21/32 of BLOCK) + @"BLOCK[20]": u1, + /// (22/32 of BLOCK) + @"BLOCK[21]": u1, + /// (23/32 of BLOCK) + @"BLOCK[22]": u1, + /// (24/32 of BLOCK) + @"BLOCK[23]": u1, + /// (25/32 of BLOCK) + @"BLOCK[24]": u1, + /// (26/32 of BLOCK) + @"BLOCK[25]": u1, + /// (27/32 of BLOCK) + @"BLOCK[26]": u1, + /// (28/32 of BLOCK) + @"BLOCK[27]": u1, + /// (29/32 of BLOCK) + @"BLOCK[28]": u1, + /// (30/32 of BLOCK) + @"BLOCK[29]": u1, + /// (31/32 of BLOCK) + @"BLOCK[30]": u1, + /// (32/32 of BLOCK) + @"BLOCK[31]": u1, }), reserved192: [48]u8, /// secure HDP control register @@ -336953,8 +344690,70 @@ pub const types = struct { reserved208: [8]u8, /// privilege block based register 1 PRIVBBR: [4]mmio.Mmio(packed struct(u32) { - BLOCK: u1, - padding: u31, + /// (1/32 of BLOCK) + @"BLOCK[0]": u1, + /// (2/32 of BLOCK) + @"BLOCK[1]": u1, + /// (3/32 of BLOCK) + @"BLOCK[2]": u1, + /// (4/32 of BLOCK) + @"BLOCK[3]": u1, + /// (5/32 of BLOCK) + @"BLOCK[4]": u1, + /// (6/32 of BLOCK) + @"BLOCK[5]": u1, + /// (7/32 of BLOCK) + @"BLOCK[6]": u1, + /// (8/32 of BLOCK) + @"BLOCK[7]": u1, + /// (9/32 of BLOCK) + @"BLOCK[8]": u1, + /// (10/32 of BLOCK) + @"BLOCK[9]": u1, + /// (11/32 of BLOCK) + @"BLOCK[10]": u1, + /// (12/32 of BLOCK) + @"BLOCK[11]": u1, + /// (13/32 of BLOCK) + @"BLOCK[12]": u1, + /// (14/32 of BLOCK) + @"BLOCK[13]": u1, + /// (15/32 of BLOCK) + @"BLOCK[14]": u1, + /// (16/32 of BLOCK) + @"BLOCK[15]": u1, + /// (17/32 of BLOCK) + @"BLOCK[16]": u1, + /// (18/32 of BLOCK) + @"BLOCK[17]": u1, + /// (19/32 of BLOCK) + @"BLOCK[18]": u1, + /// (20/32 of BLOCK) + @"BLOCK[19]": u1, + /// (21/32 of BLOCK) + @"BLOCK[20]": u1, + /// (22/32 of BLOCK) + @"BLOCK[21]": u1, + /// (23/32 of BLOCK) + @"BLOCK[22]": u1, + /// (24/32 of BLOCK) + @"BLOCK[23]": u1, + /// (25/32 of BLOCK) + @"BLOCK[24]": u1, + /// (26/32 of BLOCK) + @"BLOCK[25]": u1, + /// (27/32 of BLOCK) + @"BLOCK[26]": u1, + /// (28/32 of BLOCK) + @"BLOCK[27]": u1, + /// (29/32 of BLOCK) + @"BLOCK[28]": u1, + /// (30/32 of BLOCK) + @"BLOCK[29]": u1, + /// (31/32 of BLOCK) + @"BLOCK[30]": u1, + /// (32/32 of BLOCK) + @"BLOCK[31]": u1, }), }; }; @@ -339005,9 +346804,15 @@ pub const types = struct { PCSCNTR: mmio.Mmio(packed struct(u32) { /// Chip select counter. These bits are written by software to define the maximum chip select low pulse duration. It is expressed in FMC_CLK cycles for synchronous accesses and in HCLK cycles for asynchronous accesses. The counter is disabled if the programmed value is 0. CSCOUNT: u16, - /// Counter Bank 1 enable This bit enables the chip select counter for PSRAM/NOR Bank 1. - CNTBEN: u1, - padding: u15, + /// (1/4 of CNTBEN) Counter Bank 1 enable This bit enables the chip select counter for PSRAM/NOR Bank 1. + @"CNTBEN[0]": u1, + /// (2/4 of CNTBEN) Counter Bank 1 enable This bit enables the chip select counter for PSRAM/NOR Bank 1. + @"CNTBEN[1]": u1, + /// (3/4 of CNTBEN) Counter Bank 1 enable This bit enables the chip select counter for PSRAM/NOR Bank 1. + @"CNTBEN[2]": u1, + /// (4/4 of CNTBEN) Counter Bank 1 enable This bit enables the chip select counter for PSRAM/NOR Bank 1. + @"CNTBEN[3]": u1, + padding: u12, }), reserved260: [224]u8, /// SRAM/NOR-Flash write timing registers 1. @@ -339073,9 +346878,10 @@ pub const types = struct { SDCMR: mmio.Mmio(packed struct(u32) { /// Command mode These bits define the command issued to the SDRAM device. Note: When a command is issued, at least one Command Target Bank bit ( CTB1 or CTB2) must be set otherwise the command will be ignored. Note: If two SDRAM banks are used, the Auto-refresh and PALL command must be issued simultaneously to the two devices with CTB1 and CTB2 bits set otherwise the command will be ignored. Note: If only one SDRAM bank is used and a command is issued with it’s associated CTB bit set, the other CTB bit of the the unused bank must be kept to 0. MODE: MODE, - /// Command Target Bank 2 This bit indicates whether the command will be issued to SDRAM Bank 2 or not. - CTB: u1, - reserved5: u1, + /// (1/2 of CTB) Command Target Bank 2 This bit indicates whether the command will be issued to SDRAM Bank 2 or not. + @"CTB[0]": u1, + /// (2/2 of CTB) Command Target Bank 2 This bit indicates whether the command will be issued to SDRAM Bank 2 or not. + @"CTB[1]": u1, /// Number of Auto-refresh These bits define the number of consecutive Auto-refresh commands issued when MODE = ‘011’. .... NRFS: u4, /// Mode Register definition This 13-bit field defines the SDRAM Mode Register content. The Mode Register is programmed using the Load Mode Register command. @@ -339096,9 +346902,10 @@ pub const types = struct { SDSR: mmio.Mmio(packed struct(u32) { /// Refresh error flag An interrupt is generated if REIE = 1 and RE = 1. RE: u1, - /// Status Mode for Bank 1 This bit defines the Status Mode of SDRAM Bank 1. - MODES: MODES, - reserved5: u2, + /// (1/2 of MODES) Status Mode for Bank 1 This bit defines the Status Mode of SDRAM Bank 1. + @"MODES[0]": MODES, + /// (2/2 of MODES) Status Mode for Bank 1 This bit defines the Status Mode of SDRAM Bank 1. + @"MODES[1]": MODES, /// Busy status This bit defines the status of the SDRAM controller after a Command Mode request 1; SDRAM Controller is not ready to accept a new request. BUSY: u1, padding: u26, @@ -340619,30 +348426,45 @@ pub const types = struct { pub const GFXMMU = extern struct { /// GFXMMU configuration register. CR: mmio.Mmio(packed struct(u32) { - /// Buffer overflow interrupt enable. This bit enables the buffer 0 overflow interrupt. - BOIE: u1, - reserved4: u3, + /// (1/4 of BOIE) Buffer overflow interrupt enable. This bit enables the buffer 0 overflow interrupt. + @"BOIE[0]": u1, + /// (2/4 of BOIE) Buffer overflow interrupt enable. This bit enables the buffer 0 overflow interrupt. + @"BOIE[1]": u1, + /// (3/4 of BOIE) Buffer overflow interrupt enable. This bit enables the buffer 0 overflow interrupt. + @"BOIE[2]": u1, + /// (4/4 of BOIE) Buffer overflow interrupt enable. This bit enables the buffer 0 overflow interrupt. + @"BOIE[3]": u1, /// AHB master error interrupt enable. This bit enables the AHB master error interrupt. AMEIE: u1, reserved6: u1, - /// 192 Block mode. This bit defines the number of blocks per line. - BM: BM192, + /// (1/1 of BM) 192 Block mode. This bit defines the number of blocks per line. + @"BM[0]": BM192, padding: u25, }), /// GFXMMU status register. SR: mmio.Mmio(packed struct(u32) { - /// Buffer overflow flag. This bit is set when an overflow occurs during the offset calculation of the buffer 0. It is cleared by writing 1 to CB0OF. - BOF: u1, - reserved4: u3, + /// (1/4 of BOF) Buffer overflow flag. This bit is set when an overflow occurs during the offset calculation of the buffer 0. It is cleared by writing 1 to CB0OF. + @"BOF[0]": u1, + /// (2/4 of BOF) Buffer overflow flag. This bit is set when an overflow occurs during the offset calculation of the buffer 0. It is cleared by writing 1 to CB0OF. + @"BOF[1]": u1, + /// (3/4 of BOF) Buffer overflow flag. This bit is set when an overflow occurs during the offset calculation of the buffer 0. It is cleared by writing 1 to CB0OF. + @"BOF[2]": u1, + /// (4/4 of BOF) Buffer overflow flag. This bit is set when an overflow occurs during the offset calculation of the buffer 0. It is cleared by writing 1 to CB0OF. + @"BOF[3]": u1, /// AHB master error flag. This bit is set when an AHB error happens during a transaction. It is cleared by writing 1 to CAMEF. AMEF: u1, padding: u27, }), /// GFXMMU flag clear register. FCR: mmio.Mmio(packed struct(u32) { - /// Clear buffer overflow flag. Writing 1 clears the buffer 0 overflow flag in the GFXMMU_SR register. - CBOF: u1, - reserved4: u3, + /// (1/4 of CBOF) Clear buffer overflow flag. Writing 1 clears the buffer 0 overflow flag in the GFXMMU_SR register. + @"CBOF[0]": u1, + /// (2/4 of CBOF) Clear buffer overflow flag. Writing 1 clears the buffer 0 overflow flag in the GFXMMU_SR register. + @"CBOF[1]": u1, + /// (3/4 of CBOF) Clear buffer overflow flag. Writing 1 clears the buffer 0 overflow flag in the GFXMMU_SR register. + @"CBOF[2]": u1, + /// (4/4 of CBOF) Clear buffer overflow flag. Writing 1 clears the buffer 0 overflow flag in the GFXMMU_SR register. + @"CBOF[3]": u1, /// Clear AHB master error flag. Writing 1 clears the AHB master error flag in the GFXMMU_SR register. CAMEF: u1, padding: u27, @@ -340707,14 +348529,19 @@ pub const types = struct { pub const GFXMMU = extern struct { /// GFXMMU configuration register. CR: mmio.Mmio(packed struct(u32) { - /// Buffer overflow interrupt enable. This bit enables the buffer 0 overflow interrupt. - BOIE: u1, - reserved4: u3, + /// (1/4 of BOIE) Buffer overflow interrupt enable. This bit enables the buffer 0 overflow interrupt. + @"BOIE[0]": u1, + /// (2/4 of BOIE) Buffer overflow interrupt enable. This bit enables the buffer 0 overflow interrupt. + @"BOIE[1]": u1, + /// (3/4 of BOIE) Buffer overflow interrupt enable. This bit enables the buffer 0 overflow interrupt. + @"BOIE[2]": u1, + /// (4/4 of BOIE) Buffer overflow interrupt enable. This bit enables the buffer 0 overflow interrupt. + @"BOIE[3]": u1, /// AHB master error interrupt enable. This bit enables the AHB master error interrupt. AMEIE: u1, reserved6: u1, - /// 192 Block mode. This bit defines the number of blocks per line. - BM: BM192, + /// (1/1 of BM) 192 Block mode. This bit defines the number of blocks per line. + @"BM[0]": BM192, /// Cache enable. This bit enables the cache unit. CE: u1, /// Cache lock. This bit lock the cache onto the buffer defined in the CLB field. @@ -340734,18 +348561,28 @@ pub const types = struct { }), /// GFXMMU status register. SR: mmio.Mmio(packed struct(u32) { - /// Buffer overflow flag. This bit is set when an overflow occurs during the offset calculation of the buffer 0. It is cleared by writing 1 to CB0OF. - BOF: u1, - reserved4: u3, + /// (1/4 of BOF) Buffer overflow flag. This bit is set when an overflow occurs during the offset calculation of the buffer 0. It is cleared by writing 1 to CB0OF. + @"BOF[0]": u1, + /// (2/4 of BOF) Buffer overflow flag. This bit is set when an overflow occurs during the offset calculation of the buffer 0. It is cleared by writing 1 to CB0OF. + @"BOF[1]": u1, + /// (3/4 of BOF) Buffer overflow flag. This bit is set when an overflow occurs during the offset calculation of the buffer 0. It is cleared by writing 1 to CB0OF. + @"BOF[2]": u1, + /// (4/4 of BOF) Buffer overflow flag. This bit is set when an overflow occurs during the offset calculation of the buffer 0. It is cleared by writing 1 to CB0OF. + @"BOF[3]": u1, /// AHB master error flag. This bit is set when an AHB error happens during a transaction. It is cleared by writing 1 to CAMEF. AMEF: u1, padding: u27, }), /// GFXMMU flag clear register. FCR: mmio.Mmio(packed struct(u32) { - /// Clear buffer overflow flag. Writing 1 clears the buffer 0 overflow flag in the GFXMMU_SR register. - CBOF: u1, - reserved4: u3, + /// (1/4 of CBOF) Clear buffer overflow flag. Writing 1 clears the buffer 0 overflow flag in the GFXMMU_SR register. + @"CBOF[0]": u1, + /// (2/4 of CBOF) Clear buffer overflow flag. Writing 1 clears the buffer 0 overflow flag in the GFXMMU_SR register. + @"CBOF[1]": u1, + /// (3/4 of CBOF) Clear buffer overflow flag. Writing 1 clears the buffer 0 overflow flag in the GFXMMU_SR register. + @"CBOF[2]": u1, + /// (4/4 of CBOF) Clear buffer overflow flag. Writing 1 clears the buffer 0 overflow flag in the GFXMMU_SR register. + @"CBOF[3]": u1, /// Clear AHB master error flag. Writing 1 clears the AHB master error flag in the GFXMMU_SR register. CAMEF: u1, padding: u27, @@ -341110,33 +348947,183 @@ pub const types = struct { pub const GPDMA = extern struct { /// GPDMA secure configuration register SECCFGR: mmio.Mmio(packed struct(u32) { - /// SEC0 - SEC: u1, - padding: u31, + /// (1/16 of SEC) SEC0 + @"SEC[0]": u1, + /// (2/16 of SEC) SEC0 + @"SEC[1]": u1, + /// (3/16 of SEC) SEC0 + @"SEC[2]": u1, + /// (4/16 of SEC) SEC0 + @"SEC[3]": u1, + /// (5/16 of SEC) SEC0 + @"SEC[4]": u1, + /// (6/16 of SEC) SEC0 + @"SEC[5]": u1, + /// (7/16 of SEC) SEC0 + @"SEC[6]": u1, + /// (8/16 of SEC) SEC0 + @"SEC[7]": u1, + /// (9/16 of SEC) SEC0 + @"SEC[8]": u1, + /// (10/16 of SEC) SEC0 + @"SEC[9]": u1, + /// (11/16 of SEC) SEC0 + @"SEC[10]": u1, + /// (12/16 of SEC) SEC0 + @"SEC[11]": u1, + /// (13/16 of SEC) SEC0 + @"SEC[12]": u1, + /// (14/16 of SEC) SEC0 + @"SEC[13]": u1, + /// (15/16 of SEC) SEC0 + @"SEC[14]": u1, + /// (16/16 of SEC) SEC0 + @"SEC[15]": u1, + padding: u16, }), /// GPDMA privileged configuration register PRIVCFGR: mmio.Mmio(packed struct(u32) { - /// PRIV0 - PRIV: u1, - padding: u31, + /// (1/16 of PRIV) PRIV0 + @"PRIV[0]": u1, + /// (2/16 of PRIV) PRIV0 + @"PRIV[1]": u1, + /// (3/16 of PRIV) PRIV0 + @"PRIV[2]": u1, + /// (4/16 of PRIV) PRIV0 + @"PRIV[3]": u1, + /// (5/16 of PRIV) PRIV0 + @"PRIV[4]": u1, + /// (6/16 of PRIV) PRIV0 + @"PRIV[5]": u1, + /// (7/16 of PRIV) PRIV0 + @"PRIV[6]": u1, + /// (8/16 of PRIV) PRIV0 + @"PRIV[7]": u1, + /// (9/16 of PRIV) PRIV0 + @"PRIV[8]": u1, + /// (10/16 of PRIV) PRIV0 + @"PRIV[9]": u1, + /// (11/16 of PRIV) PRIV0 + @"PRIV[10]": u1, + /// (12/16 of PRIV) PRIV0 + @"PRIV[11]": u1, + /// (13/16 of PRIV) PRIV0 + @"PRIV[12]": u1, + /// (14/16 of PRIV) PRIV0 + @"PRIV[13]": u1, + /// (15/16 of PRIV) PRIV0 + @"PRIV[14]": u1, + /// (16/16 of PRIV) PRIV0 + @"PRIV[15]": u1, + padding: u16, }), /// GPDMA configuration lock register RCFGLOCKR: mmio.Mmio(packed struct(u32) { - /// LOCK0 - LOCK: u1, - padding: u31, + /// (1/16 of LOCK) LOCK0 + @"LOCK[0]": u1, + /// (2/16 of LOCK) LOCK0 + @"LOCK[1]": u1, + /// (3/16 of LOCK) LOCK0 + @"LOCK[2]": u1, + /// (4/16 of LOCK) LOCK0 + @"LOCK[3]": u1, + /// (5/16 of LOCK) LOCK0 + @"LOCK[4]": u1, + /// (6/16 of LOCK) LOCK0 + @"LOCK[5]": u1, + /// (7/16 of LOCK) LOCK0 + @"LOCK[6]": u1, + /// (8/16 of LOCK) LOCK0 + @"LOCK[7]": u1, + /// (9/16 of LOCK) LOCK0 + @"LOCK[8]": u1, + /// (10/16 of LOCK) LOCK0 + @"LOCK[9]": u1, + /// (11/16 of LOCK) LOCK0 + @"LOCK[10]": u1, + /// (12/16 of LOCK) LOCK0 + @"LOCK[11]": u1, + /// (13/16 of LOCK) LOCK0 + @"LOCK[12]": u1, + /// (14/16 of LOCK) LOCK0 + @"LOCK[13]": u1, + /// (15/16 of LOCK) LOCK0 + @"LOCK[14]": u1, + /// (16/16 of LOCK) LOCK0 + @"LOCK[15]": u1, + padding: u16, }), /// GPDMA non-secure masked interrupt status register MISR: mmio.Mmio(packed struct(u32) { - /// MIS0 - MIS: u1, - padding: u31, + /// (1/16 of MIS) MIS0 + @"MIS[0]": u1, + /// (2/16 of MIS) MIS0 + @"MIS[1]": u1, + /// (3/16 of MIS) MIS0 + @"MIS[2]": u1, + /// (4/16 of MIS) MIS0 + @"MIS[3]": u1, + /// (5/16 of MIS) MIS0 + @"MIS[4]": u1, + /// (6/16 of MIS) MIS0 + @"MIS[5]": u1, + /// (7/16 of MIS) MIS0 + @"MIS[6]": u1, + /// (8/16 of MIS) MIS0 + @"MIS[7]": u1, + /// (9/16 of MIS) MIS0 + @"MIS[8]": u1, + /// (10/16 of MIS) MIS0 + @"MIS[9]": u1, + /// (11/16 of MIS) MIS0 + @"MIS[10]": u1, + /// (12/16 of MIS) MIS0 + @"MIS[11]": u1, + /// (13/16 of MIS) MIS0 + @"MIS[12]": u1, + /// (14/16 of MIS) MIS0 + @"MIS[13]": u1, + /// (15/16 of MIS) MIS0 + @"MIS[14]": u1, + /// (16/16 of MIS) MIS0 + @"MIS[15]": u1, + padding: u16, }), /// GPDMA secure masked interrupt status register SMISR: mmio.Mmio(packed struct(u32) { - /// MIS0 - MIS: u1, - padding: u31, + /// (1/16 of MIS) MIS0 + @"MIS[0]": u1, + /// (2/16 of MIS) MIS0 + @"MIS[1]": u1, + /// (3/16 of MIS) MIS0 + @"MIS[2]": u1, + /// (4/16 of MIS) MIS0 + @"MIS[3]": u1, + /// (5/16 of MIS) MIS0 + @"MIS[4]": u1, + /// (6/16 of MIS) MIS0 + @"MIS[5]": u1, + /// (7/16 of MIS) MIS0 + @"MIS[6]": u1, + /// (8/16 of MIS) MIS0 + @"MIS[7]": u1, + /// (9/16 of MIS) MIS0 + @"MIS[8]": u1, + /// (10/16 of MIS) MIS0 + @"MIS[9]": u1, + /// (11/16 of MIS) MIS0 + @"MIS[10]": u1, + /// (12/16 of MIS) MIS0 + @"MIS[11]": u1, + /// (13/16 of MIS) MIS0 + @"MIS[12]": u1, + /// (14/16 of MIS) MIS0 + @"MIS[13]": u1, + /// (15/16 of MIS) MIS0 + @"MIS[14]": u1, + /// (16/16 of MIS) MIS0 + @"MIS[15]": u1, + padding: u16, }), reserved80: [60]u8, CH: u32, @@ -341194,44 +349181,248 @@ pub const types = struct { pub const GPIO = extern struct { /// Port configuration register low (GPIOn_CRL) CR: [2]mmio.Mmio(packed struct(u32) { - /// Port n mode bits - MODE: MODE, - /// Port n configuration bits, for input mode - CNF_IN: CNF_IN, - padding: u28, + /// (1/8 of MODE) Port n mode bits + @"MODE[0]": MODE, + /// (1/8 of CNF_IN) Port n configuration bits, for input mode + @"CNF_IN[0]": CNF_IN, + /// (2/8 of MODE) Port n mode bits + @"MODE[1]": MODE, + /// (2/8 of CNF_IN) Port n configuration bits, for input mode + @"CNF_IN[1]": CNF_IN, + /// (3/8 of MODE) Port n mode bits + @"MODE[2]": MODE, + /// (3/8 of CNF_IN) Port n configuration bits, for input mode + @"CNF_IN[2]": CNF_IN, + /// (4/8 of MODE) Port n mode bits + @"MODE[3]": MODE, + /// (4/8 of CNF_IN) Port n configuration bits, for input mode + @"CNF_IN[3]": CNF_IN, + /// (5/8 of MODE) Port n mode bits + @"MODE[4]": MODE, + /// (5/8 of CNF_IN) Port n configuration bits, for input mode + @"CNF_IN[4]": CNF_IN, + /// (6/8 of MODE) Port n mode bits + @"MODE[5]": MODE, + /// (6/8 of CNF_IN) Port n configuration bits, for input mode + @"CNF_IN[5]": CNF_IN, + /// (7/8 of MODE) Port n mode bits + @"MODE[6]": MODE, + /// (7/8 of CNF_IN) Port n configuration bits, for input mode + @"CNF_IN[6]": CNF_IN, + /// (8/8 of MODE) Port n mode bits + @"MODE[7]": MODE, + /// (8/8 of CNF_IN) Port n configuration bits, for input mode + @"CNF_IN[7]": CNF_IN, }), /// Port input data register (GPIOn_IDR) IDR: mmio.Mmio(packed struct(u32) { - /// Port input data - IDR: IDR, - padding: u31, + /// (1/16 of IDR) Port input data + @"IDR[0]": IDR, + /// (2/16 of IDR) Port input data + @"IDR[1]": IDR, + /// (3/16 of IDR) Port input data + @"IDR[2]": IDR, + /// (4/16 of IDR) Port input data + @"IDR[3]": IDR, + /// (5/16 of IDR) Port input data + @"IDR[4]": IDR, + /// (6/16 of IDR) Port input data + @"IDR[5]": IDR, + /// (7/16 of IDR) Port input data + @"IDR[6]": IDR, + /// (8/16 of IDR) Port input data + @"IDR[7]": IDR, + /// (9/16 of IDR) Port input data + @"IDR[8]": IDR, + /// (10/16 of IDR) Port input data + @"IDR[9]": IDR, + /// (11/16 of IDR) Port input data + @"IDR[10]": IDR, + /// (12/16 of IDR) Port input data + @"IDR[11]": IDR, + /// (13/16 of IDR) Port input data + @"IDR[12]": IDR, + /// (14/16 of IDR) Port input data + @"IDR[13]": IDR, + /// (15/16 of IDR) Port input data + @"IDR[14]": IDR, + /// (16/16 of IDR) Port input data + @"IDR[15]": IDR, + padding: u16, }), /// Port output data register (GPIOn_ODR) ODR: mmio.Mmio(packed struct(u32) { - /// Port output data - ODR: ODR, - padding: u31, + /// (1/16 of ODR) Port output data + @"ODR[0]": ODR, + /// (2/16 of ODR) Port output data + @"ODR[1]": ODR, + /// (3/16 of ODR) Port output data + @"ODR[2]": ODR, + /// (4/16 of ODR) Port output data + @"ODR[3]": ODR, + /// (5/16 of ODR) Port output data + @"ODR[4]": ODR, + /// (6/16 of ODR) Port output data + @"ODR[5]": ODR, + /// (7/16 of ODR) Port output data + @"ODR[6]": ODR, + /// (8/16 of ODR) Port output data + @"ODR[7]": ODR, + /// (9/16 of ODR) Port output data + @"ODR[8]": ODR, + /// (10/16 of ODR) Port output data + @"ODR[9]": ODR, + /// (11/16 of ODR) Port output data + @"ODR[10]": ODR, + /// (12/16 of ODR) Port output data + @"ODR[11]": ODR, + /// (13/16 of ODR) Port output data + @"ODR[12]": ODR, + /// (14/16 of ODR) Port output data + @"ODR[13]": ODR, + /// (15/16 of ODR) Port output data + @"ODR[14]": ODR, + /// (16/16 of ODR) Port output data + @"ODR[15]": ODR, + padding: u16, }), /// Port bit set/reset register (GPIOn_BSRR) BSRR: mmio.Mmio(packed struct(u32) { - /// Set bit - BS: u1, - reserved16: u15, - /// Reset bit - BR: u1, - padding: u15, + /// (1/16 of BS) Set bit + @"BS[0]": u1, + /// (2/16 of BS) Set bit + @"BS[1]": u1, + /// (3/16 of BS) Set bit + @"BS[2]": u1, + /// (4/16 of BS) Set bit + @"BS[3]": u1, + /// (5/16 of BS) Set bit + @"BS[4]": u1, + /// (6/16 of BS) Set bit + @"BS[5]": u1, + /// (7/16 of BS) Set bit + @"BS[6]": u1, + /// (8/16 of BS) Set bit + @"BS[7]": u1, + /// (9/16 of BS) Set bit + @"BS[8]": u1, + /// (10/16 of BS) Set bit + @"BS[9]": u1, + /// (11/16 of BS) Set bit + @"BS[10]": u1, + /// (12/16 of BS) Set bit + @"BS[11]": u1, + /// (13/16 of BS) Set bit + @"BS[12]": u1, + /// (14/16 of BS) Set bit + @"BS[13]": u1, + /// (15/16 of BS) Set bit + @"BS[14]": u1, + /// (16/16 of BS) Set bit + @"BS[15]": u1, + /// (1/16 of BR) Reset bit + @"BR[0]": u1, + /// (2/16 of BR) Reset bit + @"BR[1]": u1, + /// (3/16 of BR) Reset bit + @"BR[2]": u1, + /// (4/16 of BR) Reset bit + @"BR[3]": u1, + /// (5/16 of BR) Reset bit + @"BR[4]": u1, + /// (6/16 of BR) Reset bit + @"BR[5]": u1, + /// (7/16 of BR) Reset bit + @"BR[6]": u1, + /// (8/16 of BR) Reset bit + @"BR[7]": u1, + /// (9/16 of BR) Reset bit + @"BR[8]": u1, + /// (10/16 of BR) Reset bit + @"BR[9]": u1, + /// (11/16 of BR) Reset bit + @"BR[10]": u1, + /// (12/16 of BR) Reset bit + @"BR[11]": u1, + /// (13/16 of BR) Reset bit + @"BR[12]": u1, + /// (14/16 of BR) Reset bit + @"BR[13]": u1, + /// (15/16 of BR) Reset bit + @"BR[14]": u1, + /// (16/16 of BR) Reset bit + @"BR[15]": u1, }), /// Port bit reset register (GPIOn_BRR) BRR: mmio.Mmio(packed struct(u32) { - /// Reset bit - BR: u1, - padding: u31, + /// (1/16 of BR) Reset bit + @"BR[0]": u1, + /// (2/16 of BR) Reset bit + @"BR[1]": u1, + /// (3/16 of BR) Reset bit + @"BR[2]": u1, + /// (4/16 of BR) Reset bit + @"BR[3]": u1, + /// (5/16 of BR) Reset bit + @"BR[4]": u1, + /// (6/16 of BR) Reset bit + @"BR[5]": u1, + /// (7/16 of BR) Reset bit + @"BR[6]": u1, + /// (8/16 of BR) Reset bit + @"BR[7]": u1, + /// (9/16 of BR) Reset bit + @"BR[8]": u1, + /// (10/16 of BR) Reset bit + @"BR[9]": u1, + /// (11/16 of BR) Reset bit + @"BR[10]": u1, + /// (12/16 of BR) Reset bit + @"BR[11]": u1, + /// (13/16 of BR) Reset bit + @"BR[12]": u1, + /// (14/16 of BR) Reset bit + @"BR[13]": u1, + /// (15/16 of BR) Reset bit + @"BR[14]": u1, + /// (16/16 of BR) Reset bit + @"BR[15]": u1, + padding: u16, }), /// Port configuration lock register LCKR: mmio.Mmio(packed struct(u32) { - /// Port configuration locked - LCK: u1, - reserved16: u15, + /// (1/16 of LCK) Port configuration locked + @"LCK[0]": u1, + /// (2/16 of LCK) Port configuration locked + @"LCK[1]": u1, + /// (3/16 of LCK) Port configuration locked + @"LCK[2]": u1, + /// (4/16 of LCK) Port configuration locked + @"LCK[3]": u1, + /// (5/16 of LCK) Port configuration locked + @"LCK[4]": u1, + /// (6/16 of LCK) Port configuration locked + @"LCK[5]": u1, + /// (7/16 of LCK) Port configuration locked + @"LCK[6]": u1, + /// (8/16 of LCK) Port configuration locked + @"LCK[7]": u1, + /// (9/16 of LCK) Port configuration locked + @"LCK[8]": u1, + /// (10/16 of LCK) Port configuration locked + @"LCK[9]": u1, + /// (11/16 of LCK) Port configuration locked + @"LCK[10]": u1, + /// (12/16 of LCK) Port configuration locked + @"LCK[11]": u1, + /// (13/16 of LCK) Port configuration locked + @"LCK[12]": u1, + /// (14/16 of LCK) Port configuration locked + @"LCK[13]": u1, + /// (15/16 of LCK) Port configuration locked + @"LCK[14]": u1, + /// (16/16 of LCK) Port configuration locked + @"LCK[15]": u1, /// Port configuration lock key active LCKK: u1, padding: u15, @@ -341297,63 +349488,340 @@ pub const types = struct { pub const GPIO = extern struct { /// GPIO port mode register MODER: mmio.Mmio(packed struct(u32) { - /// Port x configuration bits (y = 0..15) - MODER: MODER, - padding: u30, + /// (1/16 of MODER) Port x configuration bits (y = 0..15) + @"MODER[0]": MODER, + /// (2/16 of MODER) Port x configuration bits (y = 0..15) + @"MODER[1]": MODER, + /// (3/16 of MODER) Port x configuration bits (y = 0..15) + @"MODER[2]": MODER, + /// (4/16 of MODER) Port x configuration bits (y = 0..15) + @"MODER[3]": MODER, + /// (5/16 of MODER) Port x configuration bits (y = 0..15) + @"MODER[4]": MODER, + /// (6/16 of MODER) Port x configuration bits (y = 0..15) + @"MODER[5]": MODER, + /// (7/16 of MODER) Port x configuration bits (y = 0..15) + @"MODER[6]": MODER, + /// (8/16 of MODER) Port x configuration bits (y = 0..15) + @"MODER[7]": MODER, + /// (9/16 of MODER) Port x configuration bits (y = 0..15) + @"MODER[8]": MODER, + /// (10/16 of MODER) Port x configuration bits (y = 0..15) + @"MODER[9]": MODER, + /// (11/16 of MODER) Port x configuration bits (y = 0..15) + @"MODER[10]": MODER, + /// (12/16 of MODER) Port x configuration bits (y = 0..15) + @"MODER[11]": MODER, + /// (13/16 of MODER) Port x configuration bits (y = 0..15) + @"MODER[12]": MODER, + /// (14/16 of MODER) Port x configuration bits (y = 0..15) + @"MODER[13]": MODER, + /// (15/16 of MODER) Port x configuration bits (y = 0..15) + @"MODER[14]": MODER, + /// (16/16 of MODER) Port x configuration bits (y = 0..15) + @"MODER[15]": MODER, }), /// GPIO port output type register OTYPER: mmio.Mmio(packed struct(u32) { - /// Port x configuration bits (y = 0..15) - OT: OT, - padding: u31, + /// (1/16 of OT) Port x configuration bits (y = 0..15) + @"OT[0]": OT, + /// (2/16 of OT) Port x configuration bits (y = 0..15) + @"OT[1]": OT, + /// (3/16 of OT) Port x configuration bits (y = 0..15) + @"OT[2]": OT, + /// (4/16 of OT) Port x configuration bits (y = 0..15) + @"OT[3]": OT, + /// (5/16 of OT) Port x configuration bits (y = 0..15) + @"OT[4]": OT, + /// (6/16 of OT) Port x configuration bits (y = 0..15) + @"OT[5]": OT, + /// (7/16 of OT) Port x configuration bits (y = 0..15) + @"OT[6]": OT, + /// (8/16 of OT) Port x configuration bits (y = 0..15) + @"OT[7]": OT, + /// (9/16 of OT) Port x configuration bits (y = 0..15) + @"OT[8]": OT, + /// (10/16 of OT) Port x configuration bits (y = 0..15) + @"OT[9]": OT, + /// (11/16 of OT) Port x configuration bits (y = 0..15) + @"OT[10]": OT, + /// (12/16 of OT) Port x configuration bits (y = 0..15) + @"OT[11]": OT, + /// (13/16 of OT) Port x configuration bits (y = 0..15) + @"OT[12]": OT, + /// (14/16 of OT) Port x configuration bits (y = 0..15) + @"OT[13]": OT, + /// (15/16 of OT) Port x configuration bits (y = 0..15) + @"OT[14]": OT, + /// (16/16 of OT) Port x configuration bits (y = 0..15) + @"OT[15]": OT, + padding: u16, }), /// GPIO port output speed register OSPEEDR: mmio.Mmio(packed struct(u32) { - /// Port x configuration bits (y = 0..15) - OSPEEDR: OSPEEDR, - padding: u30, + /// (1/16 of OSPEEDR) Port x configuration bits (y = 0..15) + @"OSPEEDR[0]": OSPEEDR, + /// (2/16 of OSPEEDR) Port x configuration bits (y = 0..15) + @"OSPEEDR[1]": OSPEEDR, + /// (3/16 of OSPEEDR) Port x configuration bits (y = 0..15) + @"OSPEEDR[2]": OSPEEDR, + /// (4/16 of OSPEEDR) Port x configuration bits (y = 0..15) + @"OSPEEDR[3]": OSPEEDR, + /// (5/16 of OSPEEDR) Port x configuration bits (y = 0..15) + @"OSPEEDR[4]": OSPEEDR, + /// (6/16 of OSPEEDR) Port x configuration bits (y = 0..15) + @"OSPEEDR[5]": OSPEEDR, + /// (7/16 of OSPEEDR) Port x configuration bits (y = 0..15) + @"OSPEEDR[6]": OSPEEDR, + /// (8/16 of OSPEEDR) Port x configuration bits (y = 0..15) + @"OSPEEDR[7]": OSPEEDR, + /// (9/16 of OSPEEDR) Port x configuration bits (y = 0..15) + @"OSPEEDR[8]": OSPEEDR, + /// (10/16 of OSPEEDR) Port x configuration bits (y = 0..15) + @"OSPEEDR[9]": OSPEEDR, + /// (11/16 of OSPEEDR) Port x configuration bits (y = 0..15) + @"OSPEEDR[10]": OSPEEDR, + /// (12/16 of OSPEEDR) Port x configuration bits (y = 0..15) + @"OSPEEDR[11]": OSPEEDR, + /// (13/16 of OSPEEDR) Port x configuration bits (y = 0..15) + @"OSPEEDR[12]": OSPEEDR, + /// (14/16 of OSPEEDR) Port x configuration bits (y = 0..15) + @"OSPEEDR[13]": OSPEEDR, + /// (15/16 of OSPEEDR) Port x configuration bits (y = 0..15) + @"OSPEEDR[14]": OSPEEDR, + /// (16/16 of OSPEEDR) Port x configuration bits (y = 0..15) + @"OSPEEDR[15]": OSPEEDR, }), /// GPIO port pull-up/pull-down register PUPDR: mmio.Mmio(packed struct(u32) { - /// Port x configuration bits (y = 0..15) - PUPDR: PUPDR, - padding: u30, + /// (1/16 of PUPDR) Port x configuration bits (y = 0..15) + @"PUPDR[0]": PUPDR, + /// (2/16 of PUPDR) Port x configuration bits (y = 0..15) + @"PUPDR[1]": PUPDR, + /// (3/16 of PUPDR) Port x configuration bits (y = 0..15) + @"PUPDR[2]": PUPDR, + /// (4/16 of PUPDR) Port x configuration bits (y = 0..15) + @"PUPDR[3]": PUPDR, + /// (5/16 of PUPDR) Port x configuration bits (y = 0..15) + @"PUPDR[4]": PUPDR, + /// (6/16 of PUPDR) Port x configuration bits (y = 0..15) + @"PUPDR[5]": PUPDR, + /// (7/16 of PUPDR) Port x configuration bits (y = 0..15) + @"PUPDR[6]": PUPDR, + /// (8/16 of PUPDR) Port x configuration bits (y = 0..15) + @"PUPDR[7]": PUPDR, + /// (9/16 of PUPDR) Port x configuration bits (y = 0..15) + @"PUPDR[8]": PUPDR, + /// (10/16 of PUPDR) Port x configuration bits (y = 0..15) + @"PUPDR[9]": PUPDR, + /// (11/16 of PUPDR) Port x configuration bits (y = 0..15) + @"PUPDR[10]": PUPDR, + /// (12/16 of PUPDR) Port x configuration bits (y = 0..15) + @"PUPDR[11]": PUPDR, + /// (13/16 of PUPDR) Port x configuration bits (y = 0..15) + @"PUPDR[12]": PUPDR, + /// (14/16 of PUPDR) Port x configuration bits (y = 0..15) + @"PUPDR[13]": PUPDR, + /// (15/16 of PUPDR) Port x configuration bits (y = 0..15) + @"PUPDR[14]": PUPDR, + /// (16/16 of PUPDR) Port x configuration bits (y = 0..15) + @"PUPDR[15]": PUPDR, }), /// GPIO port input data register IDR: mmio.Mmio(packed struct(u32) { - /// Port input data (y = 0..15) - IDR: IDR, - padding: u31, + /// (1/16 of IDR) Port input data (y = 0..15) + @"IDR[0]": IDR, + /// (2/16 of IDR) Port input data (y = 0..15) + @"IDR[1]": IDR, + /// (3/16 of IDR) Port input data (y = 0..15) + @"IDR[2]": IDR, + /// (4/16 of IDR) Port input data (y = 0..15) + @"IDR[3]": IDR, + /// (5/16 of IDR) Port input data (y = 0..15) + @"IDR[4]": IDR, + /// (6/16 of IDR) Port input data (y = 0..15) + @"IDR[5]": IDR, + /// (7/16 of IDR) Port input data (y = 0..15) + @"IDR[6]": IDR, + /// (8/16 of IDR) Port input data (y = 0..15) + @"IDR[7]": IDR, + /// (9/16 of IDR) Port input data (y = 0..15) + @"IDR[8]": IDR, + /// (10/16 of IDR) Port input data (y = 0..15) + @"IDR[9]": IDR, + /// (11/16 of IDR) Port input data (y = 0..15) + @"IDR[10]": IDR, + /// (12/16 of IDR) Port input data (y = 0..15) + @"IDR[11]": IDR, + /// (13/16 of IDR) Port input data (y = 0..15) + @"IDR[12]": IDR, + /// (14/16 of IDR) Port input data (y = 0..15) + @"IDR[13]": IDR, + /// (15/16 of IDR) Port input data (y = 0..15) + @"IDR[14]": IDR, + /// (16/16 of IDR) Port input data (y = 0..15) + @"IDR[15]": IDR, + padding: u16, }), /// GPIO port output data register ODR: mmio.Mmio(packed struct(u32) { - /// Port output data (y = 0..15) - ODR: ODR, - padding: u31, + /// (1/16 of ODR) Port output data (y = 0..15) + @"ODR[0]": ODR, + /// (2/16 of ODR) Port output data (y = 0..15) + @"ODR[1]": ODR, + /// (3/16 of ODR) Port output data (y = 0..15) + @"ODR[2]": ODR, + /// (4/16 of ODR) Port output data (y = 0..15) + @"ODR[3]": ODR, + /// (5/16 of ODR) Port output data (y = 0..15) + @"ODR[4]": ODR, + /// (6/16 of ODR) Port output data (y = 0..15) + @"ODR[5]": ODR, + /// (7/16 of ODR) Port output data (y = 0..15) + @"ODR[6]": ODR, + /// (8/16 of ODR) Port output data (y = 0..15) + @"ODR[7]": ODR, + /// (9/16 of ODR) Port output data (y = 0..15) + @"ODR[8]": ODR, + /// (10/16 of ODR) Port output data (y = 0..15) + @"ODR[9]": ODR, + /// (11/16 of ODR) Port output data (y = 0..15) + @"ODR[10]": ODR, + /// (12/16 of ODR) Port output data (y = 0..15) + @"ODR[11]": ODR, + /// (13/16 of ODR) Port output data (y = 0..15) + @"ODR[12]": ODR, + /// (14/16 of ODR) Port output data (y = 0..15) + @"ODR[13]": ODR, + /// (15/16 of ODR) Port output data (y = 0..15) + @"ODR[14]": ODR, + /// (16/16 of ODR) Port output data (y = 0..15) + @"ODR[15]": ODR, + padding: u16, }), /// GPIO port bit set/reset register BSRR: mmio.Mmio(packed struct(u32) { - /// Port x set bit y (y= 0..15) - BS: u1, - reserved16: u15, - /// Port x set bit y (y= 0..15) - BR: u1, - padding: u15, + /// (1/16 of BS) Port x set bit y (y= 0..15) + @"BS[0]": u1, + /// (2/16 of BS) Port x set bit y (y= 0..15) + @"BS[1]": u1, + /// (3/16 of BS) Port x set bit y (y= 0..15) + @"BS[2]": u1, + /// (4/16 of BS) Port x set bit y (y= 0..15) + @"BS[3]": u1, + /// (5/16 of BS) Port x set bit y (y= 0..15) + @"BS[4]": u1, + /// (6/16 of BS) Port x set bit y (y= 0..15) + @"BS[5]": u1, + /// (7/16 of BS) Port x set bit y (y= 0..15) + @"BS[6]": u1, + /// (8/16 of BS) Port x set bit y (y= 0..15) + @"BS[7]": u1, + /// (9/16 of BS) Port x set bit y (y= 0..15) + @"BS[8]": u1, + /// (10/16 of BS) Port x set bit y (y= 0..15) + @"BS[9]": u1, + /// (11/16 of BS) Port x set bit y (y= 0..15) + @"BS[10]": u1, + /// (12/16 of BS) Port x set bit y (y= 0..15) + @"BS[11]": u1, + /// (13/16 of BS) Port x set bit y (y= 0..15) + @"BS[12]": u1, + /// (14/16 of BS) Port x set bit y (y= 0..15) + @"BS[13]": u1, + /// (15/16 of BS) Port x set bit y (y= 0..15) + @"BS[14]": u1, + /// (16/16 of BS) Port x set bit y (y= 0..15) + @"BS[15]": u1, + /// (1/16 of BR) Port x set bit y (y= 0..15) + @"BR[0]": u1, + /// (2/16 of BR) Port x set bit y (y= 0..15) + @"BR[1]": u1, + /// (3/16 of BR) Port x set bit y (y= 0..15) + @"BR[2]": u1, + /// (4/16 of BR) Port x set bit y (y= 0..15) + @"BR[3]": u1, + /// (5/16 of BR) Port x set bit y (y= 0..15) + @"BR[4]": u1, + /// (6/16 of BR) Port x set bit y (y= 0..15) + @"BR[5]": u1, + /// (7/16 of BR) Port x set bit y (y= 0..15) + @"BR[6]": u1, + /// (8/16 of BR) Port x set bit y (y= 0..15) + @"BR[7]": u1, + /// (9/16 of BR) Port x set bit y (y= 0..15) + @"BR[8]": u1, + /// (10/16 of BR) Port x set bit y (y= 0..15) + @"BR[9]": u1, + /// (11/16 of BR) Port x set bit y (y= 0..15) + @"BR[10]": u1, + /// (12/16 of BR) Port x set bit y (y= 0..15) + @"BR[11]": u1, + /// (13/16 of BR) Port x set bit y (y= 0..15) + @"BR[12]": u1, + /// (14/16 of BR) Port x set bit y (y= 0..15) + @"BR[13]": u1, + /// (15/16 of BR) Port x set bit y (y= 0..15) + @"BR[14]": u1, + /// (16/16 of BR) Port x set bit y (y= 0..15) + @"BR[15]": u1, }), /// GPIO port configuration lock register LCKR: mmio.Mmio(packed struct(u32) { - /// Port configuration locked - LCK: u1, - reserved16: u15, + /// (1/16 of LCK) Port configuration locked + @"LCK[0]": u1, + /// (2/16 of LCK) Port configuration locked + @"LCK[1]": u1, + /// (3/16 of LCK) Port configuration locked + @"LCK[2]": u1, + /// (4/16 of LCK) Port configuration locked + @"LCK[3]": u1, + /// (5/16 of LCK) Port configuration locked + @"LCK[4]": u1, + /// (6/16 of LCK) Port configuration locked + @"LCK[5]": u1, + /// (7/16 of LCK) Port configuration locked + @"LCK[6]": u1, + /// (8/16 of LCK) Port configuration locked + @"LCK[7]": u1, + /// (9/16 of LCK) Port configuration locked + @"LCK[8]": u1, + /// (10/16 of LCK) Port configuration locked + @"LCK[9]": u1, + /// (11/16 of LCK) Port configuration locked + @"LCK[10]": u1, + /// (12/16 of LCK) Port configuration locked + @"LCK[11]": u1, + /// (13/16 of LCK) Port configuration locked + @"LCK[12]": u1, + /// (14/16 of LCK) Port configuration locked + @"LCK[13]": u1, + /// (15/16 of LCK) Port configuration locked + @"LCK[14]": u1, + /// (16/16 of LCK) Port configuration locked + @"LCK[15]": u1, /// Port configuration lock key active LCKK: u1, padding: u15, }), /// GPIO alternate function registers. The register described in the datasheet as AFRL is index 0 in this array, and AFRH is index 1. Note that when operating on AFRH, you need to subtract 8 from any operations on the field array it contains -- the alternate function for pin 9 is at index 1, for instance. AFR: [2]mmio.Mmio(packed struct(u32) { - /// Alternate function selection for one of the pins controlled by this register (0-7). - AFR: u4, - padding: u28, + /// (1/8 of AFR) Alternate function selection for one of the pins controlled by this register (0-7). + @"AFR[0]": u4, + /// (2/8 of AFR) Alternate function selection for one of the pins controlled by this register (0-7). + @"AFR[1]": u4, + /// (3/8 of AFR) Alternate function selection for one of the pins controlled by this register (0-7). + @"AFR[2]": u4, + /// (4/8 of AFR) Alternate function selection for one of the pins controlled by this register (0-7). + @"AFR[3]": u4, + /// (5/8 of AFR) Alternate function selection for one of the pins controlled by this register (0-7). + @"AFR[4]": u4, + /// (6/8 of AFR) Alternate function selection for one of the pins controlled by this register (0-7). + @"AFR[5]": u4, + /// (7/8 of AFR) Alternate function selection for one of the pins controlled by this register (0-7). + @"AFR[6]": u4, + /// (8/8 of AFR) Alternate function selection for one of the pins controlled by this register (0-7). + @"AFR[7]": u4, }), }; }; @@ -341924,9 +350392,17 @@ pub const types = struct { SYNCSRC: SYNCSRC, /// Master Counter enable MCEN: u1, - /// Timer X counter enable - TCEN: u1, - reserved25: u7, + /// (1/5 of TCEN) Timer X counter enable + @"TCEN[0]": u1, + /// (2/5 of TCEN) Timer X counter enable + @"TCEN[1]": u1, + /// (3/5 of TCEN) Timer X counter enable + @"TCEN[2]": u1, + /// (4/5 of TCEN) Timer X counter enable + @"TCEN[3]": u1, + /// (5/5 of TCEN) Timer X counter enable + @"TCEN[4]": u1, + reserved25: u3, /// AC Synchronization DACSYNC: DACSYNC, /// Preload enable @@ -341939,9 +350415,14 @@ pub const types = struct { }), /// Master Timer Interrupt Status Register MISR: mmio.Mmio(packed struct(u32) { - /// Master Compare X Interrupt Flag - MCMP: u1, - reserved4: u3, + /// (1/4 of MCMP) Master Compare X Interrupt Flag + @"MCMP[0]": u1, + /// (2/4 of MCMP) Master Compare X Interrupt Flag + @"MCMP[1]": u1, + /// (3/4 of MCMP) Master Compare X Interrupt Flag + @"MCMP[2]": u1, + /// (4/4 of MCMP) Master Compare X Interrupt Flag + @"MCMP[3]": u1, /// Master Repetition Interrupt Flag MREP: u1, /// Sync Input Interrupt Flag @@ -341952,9 +350433,14 @@ pub const types = struct { }), /// Master Timer Interrupt Clear Register MICR: mmio.Mmio(packed struct(u32) { - /// Master Compare X Interrupt flag clear - MCMPC: u1, - reserved4: u3, + /// (1/4 of MCMPC) Master Compare X Interrupt flag clear + @"MCMPC[0]": u1, + /// (2/4 of MCMPC) Master Compare X Interrupt flag clear + @"MCMPC[1]": u1, + /// (3/4 of MCMPC) Master Compare X Interrupt flag clear + @"MCMPC[2]": u1, + /// (4/4 of MCMPC) Master Compare X Interrupt flag clear + @"MCMPC[3]": u1, /// Repetition Interrupt flag clear MREPC: u1, /// Sync Input Interrupt flag clear @@ -341965,9 +350451,14 @@ pub const types = struct { }), /// Master Timer DMA / Interrupt Enable Register MDIER: mmio.Mmio(packed struct(u32) { - /// Master Compare X Interrupt Enable - MCMPIE: u1, - reserved4: u3, + /// (1/4 of MCMPIE) Master Compare X Interrupt Enable + @"MCMPIE[0]": u1, + /// (2/4 of MCMPIE) Master Compare X Interrupt Enable + @"MCMPIE[1]": u1, + /// (3/4 of MCMPIE) Master Compare X Interrupt Enable + @"MCMPIE[2]": u1, + /// (4/4 of MCMPIE) Master Compare X Interrupt Enable + @"MCMPIE[3]": u1, /// Master Repetition Interrupt Enable MREPIE: u1, /// Sync Input Interrupt Enable @@ -341975,9 +350466,14 @@ pub const types = struct { /// Master Update Interrupt Enable MUPDIE: u1, reserved16: u9, - /// Master Compare X DMA request Enable - MCMPDE: u1, - reserved20: u3, + /// (1/4 of MCMPDE) Master Compare X DMA request Enable + @"MCMPDE[0]": u1, + /// (2/4 of MCMPDE) Master Compare X DMA request Enable + @"MCMPDE[1]": u1, + /// (3/4 of MCMPDE) Master Compare X DMA request Enable + @"MCMPDE[2]": u1, + /// (4/4 of MCMPDE) Master Compare X DMA request Enable + @"MCMPDE[3]": u1, /// Master Repetition DMA request Enable MREPDE: u1, /// Sync Input DMA request Enable @@ -342018,31 +350514,68 @@ pub const types = struct { CR1: mmio.Mmio(packed struct(u32) { /// Master Update Disable MUDIS: u1, - /// Timer X Update Disable - TUDIS: u1, - reserved16: u14, - /// ADC Trigger X Update Source - ADUSRC: u3, - padding: u13, + /// (1/5 of TUDIS) Timer X Update Disable + @"TUDIS[0]": u1, + /// (2/5 of TUDIS) Timer X Update Disable + @"TUDIS[1]": u1, + /// (3/5 of TUDIS) Timer X Update Disable + @"TUDIS[2]": u1, + /// (4/5 of TUDIS) Timer X Update Disable + @"TUDIS[3]": u1, + /// (5/5 of TUDIS) Timer X Update Disable + @"TUDIS[4]": u1, + reserved16: u10, + /// (1/4 of ADUSRC) ADC Trigger X Update Source + @"ADUSRC[0]": u3, + /// (2/4 of ADUSRC) ADC Trigger X Update Source + @"ADUSRC[1]": u3, + /// (3/4 of ADUSRC) ADC Trigger X Update Source + @"ADUSRC[2]": u3, + /// (4/4 of ADUSRC) ADC Trigger X Update Source + @"ADUSRC[3]": u3, + padding: u4, }), /// High Resolution Timer: Control Register 2 CR2: mmio.Mmio(packed struct(u32) { /// Master Timer Software Update MSWU: u1, - /// Timer X Software Update - TSWU: u1, - reserved8: u6, + /// (1/5 of TSWU) Timer X Software Update + @"TSWU[0]": u1, + /// (2/5 of TSWU) Timer X Software Update + @"TSWU[1]": u1, + /// (3/5 of TSWU) Timer X Software Update + @"TSWU[2]": u1, + /// (4/5 of TSWU) Timer X Software Update + @"TSWU[3]": u1, + /// (5/5 of TSWU) Timer X Software Update + @"TSWU[4]": u1, + reserved8: u2, /// Master Counter Software Reset MRST: u1, - /// Timer X Counter Software Reset - TRST: u1, - padding: u22, + /// (1/5 of TRST) Timer X Counter Software Reset + @"TRST[0]": u1, + /// (2/5 of TRST) Timer X Counter Software Reset + @"TRST[1]": u1, + /// (3/5 of TRST) Timer X Counter Software Reset + @"TRST[2]": u1, + /// (4/5 of TRST) Timer X Counter Software Reset + @"TRST[3]": u1, + /// (5/5 of TRST) Timer X Counter Software Reset + @"TRST[4]": u1, + padding: u18, }), /// High Resolution Timer: Interrupt Status Register ISR: mmio.Mmio(packed struct(u32) { - /// Fault X Interrupt Flag - FLT: u1, - reserved5: u4, + /// (1/5 of FLT) Fault X Interrupt Flag + @"FLT[0]": u1, + /// (2/5 of FLT) Fault X Interrupt Flag + @"FLT[1]": u1, + /// (3/5 of FLT) Fault X Interrupt Flag + @"FLT[2]": u1, + /// (4/5 of FLT) Fault X Interrupt Flag + @"FLT[3]": u1, + /// (5/5 of FLT) Fault X Interrupt Flag + @"FLT[4]": u1, /// System Fault Interrupt Flag SYSFLT: u1, reserved16: u10, @@ -342054,9 +350587,16 @@ pub const types = struct { }), /// High Resolution Timer: Interrupt Clear Register ICR: mmio.Mmio(packed struct(u32) { - /// Fault X Interrupt Flag Clear - FLT: u1, - reserved5: u4, + /// (1/5 of FLT) Fault X Interrupt Flag Clear + @"FLT[0]": u1, + /// (2/5 of FLT) Fault X Interrupt Flag Clear + @"FLT[1]": u1, + /// (3/5 of FLT) Fault X Interrupt Flag Clear + @"FLT[2]": u1, + /// (4/5 of FLT) Fault X Interrupt Flag Clear + @"FLT[3]": u1, + /// (5/5 of FLT) Fault X Interrupt Flag Clear + @"FLT[4]": u1, /// System Fault Interrupt Flag Clear SYSFLT: u1, reserved16: u10, @@ -342068,9 +350608,16 @@ pub const types = struct { }), /// High Resolution Timer: Interrupt Enable Register IER: mmio.Mmio(packed struct(u32) { - /// Fault X Interrupt Flag Enable - FLT: u1, - reserved5: u4, + /// (1/5 of FLT) Fault X Interrupt Flag Enable + @"FLT[0]": u1, + /// (2/5 of FLT) Fault X Interrupt Flag Enable + @"FLT[1]": u1, + /// (3/5 of FLT) Fault X Interrupt Flag Enable + @"FLT[2]": u1, + /// (4/5 of FLT) Fault X Interrupt Flag Enable + @"FLT[3]": u1, + /// (5/5 of FLT) Fault X Interrupt Flag Enable + @"FLT[4]": u1, /// System Fault Interrupt Flag Enable SYSFLT: u1, reserved16: u10, @@ -342121,9 +350668,17 @@ pub const types = struct { reserved16: u5, /// Master Timer Burst Mode MTBM: u1, - /// Timer X Burst Mode - TBM: u1, - reserved31: u13, + /// (1/5 of TBM) Timer X Burst Mode + @"TBM[0]": u1, + /// (2/5 of TBM) Timer X Burst Mode + @"TBM[1]": u1, + /// (3/5 of TBM) Timer X Burst Mode + @"TBM[2]": u1, + /// (4/5 of TBM) Timer X Burst Mode + @"TBM[3]": u1, + /// (5/5 of TBM) Timer X Burst Mode + @"TBM[4]": u1, + reserved31: u9, BMSTAT: u1, }), /// High Resolution Timer: Burst Mode Trigger Register @@ -342134,9 +350689,14 @@ pub const types = struct { MSTRST: u1, /// Master repetition MSTREP: u1, - /// Master Compare X - MSTCMP: u1, - reserved7: u3, + /// (1/4 of MSTCMP) Master Compare X + @"MSTCMP[0]": u1, + /// (2/4 of MSTCMP) Master Compare X + @"MSTCMP[1]": u1, + /// (3/4 of MSTCMP) Master Compare X + @"MSTCMP[2]": u1, + /// (4/4 of MSTCMP) Master Compare X + @"MSTCMP[3]": u1, /// Timer X reset or roll-over TRST: u1, /// Timer X repetition @@ -342191,14 +350751,26 @@ pub const types = struct { }), /// High Resolution Timer: ADC Trigger [1, 3] Register ADC1R: mmio.Mmio(packed struct(u32) { - /// ADC trigger X on Master Compare Y - ADCMC: u1, - reserved4: u3, + /// (1/4 of ADCMC) ADC trigger X on Master Compare Y + @"ADCMC[0]": u1, + /// (2/4 of ADCMC) ADC trigger X on Master Compare Y + @"ADCMC[1]": u1, + /// (3/4 of ADCMC) ADC trigger X on Master Compare Y + @"ADCMC[2]": u1, + /// (4/4 of ADCMC) ADC trigger X on Master Compare Y + @"ADCMC[3]": u1, /// ADC trigger X on Master Period ADCMPER: u1, - /// ADC trigger X on External Event Y - ADCEEV: u1, - reserved10: u4, + /// (1/5 of ADCEEV) ADC trigger X on External Event Y + @"ADCEEV[0]": u1, + /// (2/5 of ADCEEV) ADC trigger X on External Event Y + @"ADCEEV[1]": u1, + /// (3/5 of ADCEEV) ADC trigger X on External Event Y + @"ADCEEV[2]": u1, + /// (4/5 of ADCEEV) ADC trigger X on External Event Y + @"ADCEEV[3]": u1, + /// (5/5 of ADCEEV) ADC trigger X on External Event Y + @"ADCEEV[4]": u1, /// ADC trigger X on Timer Y Compare 2 ADCTC2: u1, /// ADC trigger X on Timer Y Compare 3 @@ -342213,14 +350785,26 @@ pub const types = struct { }), /// High Resolution Timer: ADC Trigger [2, 4] Register ADC2R: mmio.Mmio(packed struct(u32) { - /// ADC trigger X on Master Compare Y - ADCMC: u1, - reserved4: u3, + /// (1/4 of ADCMC) ADC trigger X on Master Compare Y + @"ADCMC[0]": u1, + /// (2/4 of ADCMC) ADC trigger X on Master Compare Y + @"ADCMC[1]": u1, + /// (3/4 of ADCMC) ADC trigger X on Master Compare Y + @"ADCMC[2]": u1, + /// (4/4 of ADCMC) ADC trigger X on Master Compare Y + @"ADCMC[3]": u1, /// ADC trigger X on Master Period ADCMPER: u1, - /// ADC trigger X on External Event Y - ADCEEV: u1, - reserved10: u4, + /// (1/5 of ADCEEV) ADC trigger X on External Event Y + @"ADCEEV[0]": u1, + /// (2/5 of ADCEEV) ADC trigger X on External Event Y + @"ADCEEV[1]": u1, + /// (3/5 of ADCEEV) ADC trigger X on External Event Y + @"ADCEEV[2]": u1, + /// (4/5 of ADCEEV) ADC trigger X on External Event Y + @"ADCEEV[3]": u1, + /// (5/5 of ADCEEV) ADC trigger X on External Event Y + @"ADCEEV[4]": u1, /// ADC trigger X on Timer Y Compare 2 ADCTC2: u1, /// ADC trigger X on Timer Y Compare 3 @@ -342274,9 +350858,15 @@ pub const types = struct { MPER: u1, /// MREP register update enable MREP: u1, - /// MCMP register X update enable - MCMP: u1, - padding: u25, + /// (1/4 of MCMP) MCMP register X update enable + @"MCMP[0]": u1, + /// (2/4 of MCMP) MCMP register X update enable + @"MCMP[1]": u1, + /// (3/4 of MCMP) MCMP register X update enable + @"MCMP[2]": u1, + /// (4/4 of MCMP) MCMP register X update enable + @"MCMP[3]": u1, + padding: u22, }), /// High Resolution Timer: Burst DMA Timer X update Register BDTUPR: [5]mmio.Mmio(packed struct(u32) { @@ -342292,9 +350882,15 @@ pub const types = struct { PER: u1, /// REP register update enable REP: u1, - /// CMP register X update enable - CMP: u1, - padding: u25, + /// (1/4 of CMP) CMP register X update enable + @"CMP[0]": u1, + /// (2/4 of CMP) CMP register X update enable + @"CMP[1]": u1, + /// (3/4 of CMP) CMP register X update enable + @"CMP[2]": u1, + /// (4/4 of CMP) CMP register X update enable + @"CMP[3]": u1, + padding: u22, }), /// High Resolution Timer: Burst DMA Data Register BDMADR: mmio.Mmio(packed struct(u32) { @@ -342353,17 +350949,23 @@ pub const types = struct { }), /// Timer X Interrupt Status Register ISR: mmio.Mmio(packed struct(u32) { - /// Compare X Interrupt Flag - CMP: u1, - reserved4: u3, + /// (1/4 of CMP) Compare X Interrupt Flag + @"CMP[0]": u1, + /// (2/4 of CMP) Compare X Interrupt Flag + @"CMP[1]": u1, + /// (3/4 of CMP) Compare X Interrupt Flag + @"CMP[2]": u1, + /// (4/4 of CMP) Compare X Interrupt Flag + @"CMP[3]": u1, /// Repetition Interrupt Flag REP: u1, reserved6: u1, /// Update Interrupt Flag UPD: u1, - /// Capture X Interrupt Flag - CPT: u1, - reserved9: u1, + /// (1/2 of CPT) Capture X Interrupt Flag + @"CPT[0]": u1, + /// (2/2 of CPT) Capture X Interrupt Flag + @"CPT[1]": u1, /// Output X Set Interrupt Flag SETR: u1, /// Output X Reset Interrupt Flag @@ -342378,26 +350980,35 @@ pub const types = struct { CPPSTAT: CPPSTAT, /// Idle Push Pull Status IPPSTAT: IPPSTAT, - /// Output X State - OSTAT: OUTPUTSTATE, - reserved20: u1, - /// Output X Copy - OCPY: OUTPUTSTATE, - padding: u11, + /// (1/2 of OSTAT) Output X State + @"OSTAT[0]": OUTPUTSTATE, + /// (2/2 of OSTAT) Output X State + @"OSTAT[1]": OUTPUTSTATE, + /// (1/2 of OCPY) Output X Copy + @"OCPY[0]": OUTPUTSTATE, + /// (2/2 of OCPY) Output X Copy + @"OCPY[1]": OUTPUTSTATE, + padding: u10, }), /// Timer X Interrupt Clear Register ICR: mmio.Mmio(packed struct(u32) { - /// Compare X Interrupt flag Clear - CMPC: u1, - reserved4: u3, + /// (1/4 of CMPC) Compare X Interrupt flag Clear + @"CMPC[0]": u1, + /// (2/4 of CMPC) Compare X Interrupt flag Clear + @"CMPC[1]": u1, + /// (3/4 of CMPC) Compare X Interrupt flag Clear + @"CMPC[2]": u1, + /// (4/4 of CMPC) Compare X Interrupt flag Clear + @"CMPC[3]": u1, /// Repetition Interrupt flag Clear REPC: u1, reserved6: u1, /// Update Interrupt flag Clear UPDC: u1, - /// Capture X Interrupt flag Clear - CPTC: u1, - reserved9: u1, + /// (1/2 of CPTC) Capture X Interrupt flag Clear + @"CPTC[0]": u1, + /// (2/2 of CPTC) Capture X Interrupt flag Clear + @"CPTC[1]": u1, /// Output X Set flag Clear SETRC: u1, /// Output X Reset flag Clear @@ -342411,17 +351022,23 @@ pub const types = struct { }), /// Timer X DMA / Interrupt Enable Register DIER: mmio.Mmio(packed struct(u32) { - /// Compare X Interrupt Enable - CMPIE: u1, - reserved4: u3, + /// (1/4 of CMPIE) Compare X Interrupt Enable + @"CMPIE[0]": u1, + /// (2/4 of CMPIE) Compare X Interrupt Enable + @"CMPIE[1]": u1, + /// (3/4 of CMPIE) Compare X Interrupt Enable + @"CMPIE[2]": u1, + /// (4/4 of CMPIE) Compare X Interrupt Enable + @"CMPIE[3]": u1, /// Repetition Interrupt Enable REPIE: u1, reserved6: u1, /// Update Interrupt Enable UPDIE: u1, - /// Capture Interrupt Enable - CPTIE: u1, - reserved9: u1, + /// (1/2 of CPTIE) Capture Interrupt Enable + @"CPTIE[0]": u1, + /// (2/2 of CPTIE) Capture Interrupt Enable + @"CPTIE[1]": u1, /// Output X Set Interrupt Enable SETRIE: u1, /// Output X Reset Interrupt Enable @@ -342432,17 +351049,23 @@ pub const types = struct { /// Delayed Protection Interrupt Enable DLYPRTIE: u1, reserved16: u1, - /// Compare X DMA request Enable - CMPDE: u1, - reserved20: u3, + /// (1/4 of CMPDE) Compare X DMA request Enable + @"CMPDE[0]": u1, + /// (2/4 of CMPDE) Compare X DMA request Enable + @"CMPDE[1]": u1, + /// (3/4 of CMPDE) Compare X DMA request Enable + @"CMPDE[2]": u1, + /// (4/4 of CMPDE) Compare X DMA request Enable + @"CMPDE[3]": u1, /// Repetition DMA request Enable REPDE: u1, reserved22: u1, /// Update DMA request Enable UPDDE: u1, - /// Capture X DMA request Enable - CPTDE: u1, - reserved25: u1, + /// (1/2 of CPTDE) Capture X DMA request Enable + @"CPTDE[0]": u1, + /// (2/2 of CPTDE) Capture X DMA request Enable + @"CPTDE[1]": u1, /// Output X Set DMA request Enable SETRDE: u1, /// Output X Reset DMA request Enable @@ -342524,20 +351147,62 @@ pub const types = struct { RESYNC: ACTIVEEFFECT, /// Timer X Period PER: ACTIVEEFFECT, - /// Timer X compare X - CMP: ACTIVEEFFECT, - reserved7: u3, + /// (1/4 of CMP) Timer X compare X + @"CMP[0]": ACTIVEEFFECT, + /// (2/4 of CMP) Timer X compare X + @"CMP[1]": ACTIVEEFFECT, + /// (3/4 of CMP) Timer X compare X + @"CMP[2]": ACTIVEEFFECT, + /// (4/4 of CMP) Timer X compare X + @"CMP[3]": ACTIVEEFFECT, /// Master Period MSTPER: ACTIVEEFFECT, - /// Master Compare X - MSTCMPX: ACTIVEEFFECT, - reserved12: u3, - /// Timer Event X - TIMEVNT: ACTIVEEFFECT, - reserved21: u8, - /// External Event X - EXTEVNT: ACTIVEEFFECT, - reserved31: u9, + /// (1/4 of MSTCMPX) Master Compare X + @"MSTCMPX[0]": ACTIVEEFFECT, + /// (2/4 of MSTCMPX) Master Compare X + @"MSTCMPX[1]": ACTIVEEFFECT, + /// (3/4 of MSTCMPX) Master Compare X + @"MSTCMPX[2]": ACTIVEEFFECT, + /// (4/4 of MSTCMPX) Master Compare X + @"MSTCMPX[3]": ACTIVEEFFECT, + /// (1/9 of TIMEVNT) Timer Event X + @"TIMEVNT[0]": ACTIVEEFFECT, + /// (2/9 of TIMEVNT) Timer Event X + @"TIMEVNT[1]": ACTIVEEFFECT, + /// (3/9 of TIMEVNT) Timer Event X + @"TIMEVNT[2]": ACTIVEEFFECT, + /// (4/9 of TIMEVNT) Timer Event X + @"TIMEVNT[3]": ACTIVEEFFECT, + /// (5/9 of TIMEVNT) Timer Event X + @"TIMEVNT[4]": ACTIVEEFFECT, + /// (6/9 of TIMEVNT) Timer Event X + @"TIMEVNT[5]": ACTIVEEFFECT, + /// (7/9 of TIMEVNT) Timer Event X + @"TIMEVNT[6]": ACTIVEEFFECT, + /// (8/9 of TIMEVNT) Timer Event X + @"TIMEVNT[7]": ACTIVEEFFECT, + /// (9/9 of TIMEVNT) Timer Event X + @"TIMEVNT[8]": ACTIVEEFFECT, + /// (1/10 of EXTEVNT) External Event X + @"EXTEVNT[0]": ACTIVEEFFECT, + /// (2/10 of EXTEVNT) External Event X + @"EXTEVNT[1]": ACTIVEEFFECT, + /// (3/10 of EXTEVNT) External Event X + @"EXTEVNT[2]": ACTIVEEFFECT, + /// (4/10 of EXTEVNT) External Event X + @"EXTEVNT[3]": ACTIVEEFFECT, + /// (5/10 of EXTEVNT) External Event X + @"EXTEVNT[4]": ACTIVEEFFECT, + /// (6/10 of EXTEVNT) External Event X + @"EXTEVNT[5]": ACTIVEEFFECT, + /// (7/10 of EXTEVNT) External Event X + @"EXTEVNT[6]": ACTIVEEFFECT, + /// (8/10 of EXTEVNT) External Event X + @"EXTEVNT[7]": ACTIVEEFFECT, + /// (9/10 of EXTEVNT) External Event X + @"EXTEVNT[8]": ACTIVEEFFECT, + /// (10/10 of EXTEVNT) External Event X + @"EXTEVNT[9]": ACTIVEEFFECT, /// Registers update (transfer preload to active) UPDATE: ACTIVEEFFECT, }), @@ -342549,31 +351214,93 @@ pub const types = struct { RESYNC: INACTIVEEFFECT, /// Timer X Period PER: INACTIVEEFFECT, - /// Timer X compare X - CMP: INACTIVEEFFECT, - reserved7: u3, + /// (1/4 of CMP) Timer X compare X + @"CMP[0]": INACTIVEEFFECT, + /// (2/4 of CMP) Timer X compare X + @"CMP[1]": INACTIVEEFFECT, + /// (3/4 of CMP) Timer X compare X + @"CMP[2]": INACTIVEEFFECT, + /// (4/4 of CMP) Timer X compare X + @"CMP[3]": INACTIVEEFFECT, /// Master Period MSTPER: INACTIVEEFFECT, - /// Master Compare X - MSTCMP: INACTIVEEFFECT, - reserved12: u3, - /// Timer Event X - TIMEVNT: INACTIVEEFFECT, - reserved21: u8, - /// External Event X - EXTEVNT: INACTIVEEFFECT, - reserved31: u9, + /// (1/4 of MSTCMP) Master Compare X + @"MSTCMP[0]": INACTIVEEFFECT, + /// (2/4 of MSTCMP) Master Compare X + @"MSTCMP[1]": INACTIVEEFFECT, + /// (3/4 of MSTCMP) Master Compare X + @"MSTCMP[2]": INACTIVEEFFECT, + /// (4/4 of MSTCMP) Master Compare X + @"MSTCMP[3]": INACTIVEEFFECT, + /// (1/9 of TIMEVNT) Timer Event X + @"TIMEVNT[0]": INACTIVEEFFECT, + /// (2/9 of TIMEVNT) Timer Event X + @"TIMEVNT[1]": INACTIVEEFFECT, + /// (3/9 of TIMEVNT) Timer Event X + @"TIMEVNT[2]": INACTIVEEFFECT, + /// (4/9 of TIMEVNT) Timer Event X + @"TIMEVNT[3]": INACTIVEEFFECT, + /// (5/9 of TIMEVNT) Timer Event X + @"TIMEVNT[4]": INACTIVEEFFECT, + /// (6/9 of TIMEVNT) Timer Event X + @"TIMEVNT[5]": INACTIVEEFFECT, + /// (7/9 of TIMEVNT) Timer Event X + @"TIMEVNT[6]": INACTIVEEFFECT, + /// (8/9 of TIMEVNT) Timer Event X + @"TIMEVNT[7]": INACTIVEEFFECT, + /// (9/9 of TIMEVNT) Timer Event X + @"TIMEVNT[8]": INACTIVEEFFECT, + /// (1/10 of EXTEVNT) External Event X + @"EXTEVNT[0]": INACTIVEEFFECT, + /// (2/10 of EXTEVNT) External Event X + @"EXTEVNT[1]": INACTIVEEFFECT, + /// (3/10 of EXTEVNT) External Event X + @"EXTEVNT[2]": INACTIVEEFFECT, + /// (4/10 of EXTEVNT) External Event X + @"EXTEVNT[3]": INACTIVEEFFECT, + /// (5/10 of EXTEVNT) External Event X + @"EXTEVNT[4]": INACTIVEEFFECT, + /// (6/10 of EXTEVNT) External Event X + @"EXTEVNT[5]": INACTIVEEFFECT, + /// (7/10 of EXTEVNT) External Event X + @"EXTEVNT[6]": INACTIVEEFFECT, + /// (8/10 of EXTEVNT) External Event X + @"EXTEVNT[7]": INACTIVEEFFECT, + /// (9/10 of EXTEVNT) External Event X + @"EXTEVNT[8]": INACTIVEEFFECT, + /// (10/10 of EXTEVNT) External Event X + @"EXTEVNT[9]": INACTIVEEFFECT, /// Registers update (transfer preload to active) UPDATE: INACTIVEEFFECT, }), reserved76: [8]u8, /// Timer X External Event Filtering Register 1 EEF: mmio.Mmio(packed struct(u32) { - /// External Event X latch - LTCH: u1, - /// External Event X filter - FLTR: EEFLTR, - padding: u27, + /// (1/5 of LTCH) External Event X latch + @"LTCH[0]": u1, + /// (1/5 of FLTR) External Event X filter + @"FLTR[0]": EEFLTR, + reserved6: u1, + /// (2/5 of LTCH) External Event X latch + @"LTCH[1]": u1, + /// (2/5 of FLTR) External Event X filter + @"FLTR[1]": EEFLTR, + reserved12: u1, + /// (3/5 of LTCH) External Event X latch + @"LTCH[2]": u1, + /// (3/5 of FLTR) External Event X filter + @"FLTR[2]": EEFLTR, + reserved18: u1, + /// (4/5 of LTCH) External Event X latch + @"LTCH[3]": u1, + /// (4/5 of FLTR) External Event X filter + @"FLTR[3]": EEFLTR, + reserved24: u1, + /// (5/5 of LTCH) External Event X latch + @"LTCH[4]": u1, + /// (5/5 of FLTR) External Event X filter + @"FLTR[4]": EEFLTR, + padding: u3, }), reserved84: [4]u8, /// Timer X Reset Register @@ -342581,17 +351308,40 @@ pub const types = struct { reserved1: u1, /// Timer X Update reset UPDT: RESETEFFECT, - /// Timer X compare X reset - CMP: RESETEFFECT, - reserved4: u1, + /// (1/2 of CMP) Timer X compare X reset + @"CMP[0]": RESETEFFECT, + /// (2/2 of CMP) Timer X compare X reset + @"CMP[1]": RESETEFFECT, /// Master timer Period MSTPER: RESETEFFECT, - /// Master compare X - MSTCMP: RESETEFFECT, - reserved9: u3, - /// External Event X - EXTEVNT: RESETEFFECT, - reserved19: u9, + /// (1/4 of MSTCMP) Master compare X + @"MSTCMP[0]": RESETEFFECT, + /// (2/4 of MSTCMP) Master compare X + @"MSTCMP[1]": RESETEFFECT, + /// (3/4 of MSTCMP) Master compare X + @"MSTCMP[2]": RESETEFFECT, + /// (4/4 of MSTCMP) Master compare X + @"MSTCMP[3]": RESETEFFECT, + /// (1/10 of EXTEVNT) External Event X + @"EXTEVNT[0]": RESETEFFECT, + /// (2/10 of EXTEVNT) External Event X + @"EXTEVNT[1]": RESETEFFECT, + /// (3/10 of EXTEVNT) External Event X + @"EXTEVNT[2]": RESETEFFECT, + /// (4/10 of EXTEVNT) External Event X + @"EXTEVNT[3]": RESETEFFECT, + /// (5/10 of EXTEVNT) External Event X + @"EXTEVNT[4]": RESETEFFECT, + /// (6/10 of EXTEVNT) External Event X + @"EXTEVNT[5]": RESETEFFECT, + /// (7/10 of EXTEVNT) External Event X + @"EXTEVNT[6]": RESETEFFECT, + /// (8/10 of EXTEVNT) External Event X + @"EXTEVNT[7]": RESETEFFECT, + /// (9/10 of EXTEVNT) External Event X + @"EXTEVNT[8]": RESETEFFECT, + /// (10/10 of EXTEVNT) External Event X + @"EXTEVNT[9]": RESETEFFECT, /// Timer X compare 1 event TCMP1: RESETEFFECT, /// Timer X compare 2 event @@ -342616,37 +351366,59 @@ pub const types = struct { SWCPT: CAPTUREEFFECT, /// Update Capture UPDCPT: CAPTUREEFFECT, - /// External Event X Capture - EXEVCPT: CAPTUREEFFECT, - reserved16: u13, + /// (1/10 of EXEVCPT) External Event X Capture + @"EXEVCPT[0]": CAPTUREEFFECT, + /// (2/10 of EXEVCPT) External Event X Capture + @"EXEVCPT[1]": CAPTUREEFFECT, + /// (3/10 of EXEVCPT) External Event X Capture + @"EXEVCPT[2]": CAPTUREEFFECT, + /// (4/10 of EXEVCPT) External Event X Capture + @"EXEVCPT[3]": CAPTUREEFFECT, + /// (5/10 of EXEVCPT) External Event X Capture + @"EXEVCPT[4]": CAPTUREEFFECT, + /// (6/10 of EXEVCPT) External Event X Capture + @"EXEVCPT[5]": CAPTUREEFFECT, + /// (7/10 of EXEVCPT) External Event X Capture + @"EXEVCPT[6]": CAPTUREEFFECT, + /// (8/10 of EXEVCPT) External Event X Capture + @"EXEVCPT[7]": CAPTUREEFFECT, + /// (9/10 of EXEVCPT) External Event X Capture + @"EXEVCPT[8]": CAPTUREEFFECT, + /// (10/10 of EXEVCPT) External Event X Capture + @"EXEVCPT[9]": CAPTUREEFFECT, + reserved16: u4, /// Timer X output Set TXSET: CAPTUREEFFECT, /// Timer X output Reset TXRST: CAPTUREEFFECT, - /// Timer X Compare X - TXCMP: CAPTUREEFFECT, - reserved20: u1, + /// (1/2 of TXCMP) Timer X Compare X + @"TXCMP[0]": CAPTUREEFFECT, + /// (2/2 of TXCMP) Timer X Compare X + @"TXCMP[1]": CAPTUREEFFECT, /// Timer Y output Set TYSET: CAPTUREEFFECT, /// Timer Y output Reset TYRST: CAPTUREEFFECT, - /// Timer Y Compare X - TYCMP: CAPTUREEFFECT, - reserved24: u1, + /// (1/2 of TYCMP) Timer Y Compare X + @"TYCMP[0]": CAPTUREEFFECT, + /// (2/2 of TYCMP) Timer Y Compare X + @"TYCMP[1]": CAPTUREEFFECT, /// Timer Z output Set TZSET: CAPTUREEFFECT, /// Timer Z output Reset TZRST: CAPTUREEFFECT, - /// Timer Z Compare X - TZCMP: CAPTUREEFFECT, - reserved28: u1, + /// (1/2 of TZCMP) Timer Z Compare X + @"TZCMP[0]": CAPTUREEFFECT, + /// (2/2 of TZCMP) Timer Z Compare X + @"TZCMP[1]": CAPTUREEFFECT, /// Timer T output Set TTSET: CAPTUREEFFECT, /// Timer T output Reset TTRST: CAPTUREEFFECT, - /// Timer T Compare X - TTCMP: CAPTUREEFFECT, - padding: u1, + /// (1/2 of TTCMP) Timer T Compare X + @"TTCMP[0]": CAPTUREEFFECT, + /// (2/2 of TTCMP) Timer T Compare X + @"TTCMP[1]": CAPTUREEFFECT, }), reserved100: [4]u8, /// Timer X Output Register @@ -342674,9 +351446,17 @@ pub const types = struct { }), /// Timer X Fault Register FLT: mmio.Mmio(packed struct(u32) { - /// Fault X enable - FLTEN: FLTEN, - reserved31: u30, + /// (1/5 of FLTEN) Fault X enable + @"FLTEN[0]": FLTEN, + /// (2/5 of FLTEN) Fault X enable + @"FLTEN[1]": FLTEN, + /// (3/5 of FLTEN) Fault X enable + @"FLTEN[2]": FLTEN, + /// (4/5 of FLTEN) Fault X enable + @"FLTEN[3]": FLTEN, + /// (5/5 of FLTEN) Fault X enable + @"FLTEN[4]": FLTEN, + reserved31: u26, /// Fault sources Lock FLTLCK: u1, }), @@ -342957,9 +351737,17 @@ pub const types = struct { SYNCSRC: SYNCSRC, /// Master Counter enable MCEN: u1, - /// Timer X counter enable - TCEN: u1, - reserved25: u7, + /// (1/5 of TCEN) Timer X counter enable + @"TCEN[0]": u1, + /// (2/5 of TCEN) Timer X counter enable + @"TCEN[1]": u1, + /// (3/5 of TCEN) Timer X counter enable + @"TCEN[2]": u1, + /// (4/5 of TCEN) Timer X counter enable + @"TCEN[3]": u1, + /// (5/5 of TCEN) Timer X counter enable + @"TCEN[4]": u1, + reserved25: u3, /// AC Synchronization DACSYNC: DACSYNC, /// Preload enable @@ -342972,9 +351760,14 @@ pub const types = struct { }), /// Master Timer Interrupt Status Register MISR: mmio.Mmio(packed struct(u32) { - /// Master Compare X Interrupt Flag - MCMP: u1, - reserved4: u3, + /// (1/4 of MCMP) Master Compare X Interrupt Flag + @"MCMP[0]": u1, + /// (2/4 of MCMP) Master Compare X Interrupt Flag + @"MCMP[1]": u1, + /// (3/4 of MCMP) Master Compare X Interrupt Flag + @"MCMP[2]": u1, + /// (4/4 of MCMP) Master Compare X Interrupt Flag + @"MCMP[3]": u1, /// Master Repetition Interrupt Flag MREP: u1, /// Sync Input Interrupt Flag @@ -342985,9 +351778,14 @@ pub const types = struct { }), /// Master Timer Interrupt Clear Register MICR: mmio.Mmio(packed struct(u32) { - /// Master Compare X Interrupt flag clear - MCMPC: u1, - reserved4: u3, + /// (1/4 of MCMPC) Master Compare X Interrupt flag clear + @"MCMPC[0]": u1, + /// (2/4 of MCMPC) Master Compare X Interrupt flag clear + @"MCMPC[1]": u1, + /// (3/4 of MCMPC) Master Compare X Interrupt flag clear + @"MCMPC[2]": u1, + /// (4/4 of MCMPC) Master Compare X Interrupt flag clear + @"MCMPC[3]": u1, /// Repetition Interrupt flag clear MREPC: u1, /// Sync Input Interrupt flag clear @@ -342998,9 +351796,14 @@ pub const types = struct { }), /// Master Timer DMA / Interrupt Enable Register MDIER: mmio.Mmio(packed struct(u32) { - /// Master Compare X Interrupt Enable - MCMPIE: u1, - reserved4: u3, + /// (1/4 of MCMPIE) Master Compare X Interrupt Enable + @"MCMPIE[0]": u1, + /// (2/4 of MCMPIE) Master Compare X Interrupt Enable + @"MCMPIE[1]": u1, + /// (3/4 of MCMPIE) Master Compare X Interrupt Enable + @"MCMPIE[2]": u1, + /// (4/4 of MCMPIE) Master Compare X Interrupt Enable + @"MCMPIE[3]": u1, /// Master Repetition Interrupt Enable MREPIE: u1, /// Sync Input Interrupt Enable @@ -343008,9 +351811,14 @@ pub const types = struct { /// Master Update Interrupt Enable MUPDIE: u1, reserved16: u9, - /// Master Compare X DMA request Enable - MCMPDE: u1, - reserved20: u3, + /// (1/4 of MCMPDE) Master Compare X DMA request Enable + @"MCMPDE[0]": u1, + /// (2/4 of MCMPDE) Master Compare X DMA request Enable + @"MCMPDE[1]": u1, + /// (3/4 of MCMPDE) Master Compare X DMA request Enable + @"MCMPDE[2]": u1, + /// (4/4 of MCMPDE) Master Compare X DMA request Enable + @"MCMPDE[3]": u1, /// Master Repetition DMA request Enable MREPDE: u1, /// Sync Input DMA request Enable @@ -343051,31 +351859,68 @@ pub const types = struct { CR1: mmio.Mmio(packed struct(u32) { /// Master Update Disable MUDIS: u1, - /// Timer X Update Disable - TUDIS: u1, - reserved16: u14, - /// ADC Trigger X Update Source - ADUSRC: u3, - padding: u13, + /// (1/5 of TUDIS) Timer X Update Disable + @"TUDIS[0]": u1, + /// (2/5 of TUDIS) Timer X Update Disable + @"TUDIS[1]": u1, + /// (3/5 of TUDIS) Timer X Update Disable + @"TUDIS[2]": u1, + /// (4/5 of TUDIS) Timer X Update Disable + @"TUDIS[3]": u1, + /// (5/5 of TUDIS) Timer X Update Disable + @"TUDIS[4]": u1, + reserved16: u10, + /// (1/4 of ADUSRC) ADC Trigger X Update Source + @"ADUSRC[0]": u3, + /// (2/4 of ADUSRC) ADC Trigger X Update Source + @"ADUSRC[1]": u3, + /// (3/4 of ADUSRC) ADC Trigger X Update Source + @"ADUSRC[2]": u3, + /// (4/4 of ADUSRC) ADC Trigger X Update Source + @"ADUSRC[3]": u3, + padding: u4, }), /// High Resolution Timer: Control Register 2 CR2: mmio.Mmio(packed struct(u32) { /// Master Timer Software Update MSWU: u1, - /// Timer X Software Update - TSWU: u1, - reserved8: u6, + /// (1/5 of TSWU) Timer X Software Update + @"TSWU[0]": u1, + /// (2/5 of TSWU) Timer X Software Update + @"TSWU[1]": u1, + /// (3/5 of TSWU) Timer X Software Update + @"TSWU[2]": u1, + /// (4/5 of TSWU) Timer X Software Update + @"TSWU[3]": u1, + /// (5/5 of TSWU) Timer X Software Update + @"TSWU[4]": u1, + reserved8: u2, /// Master Counter Software Reset MRST: u1, - /// Timer X Counter Software Reset - TRST: u1, - padding: u22, + /// (1/5 of TRST) Timer X Counter Software Reset + @"TRST[0]": u1, + /// (2/5 of TRST) Timer X Counter Software Reset + @"TRST[1]": u1, + /// (3/5 of TRST) Timer X Counter Software Reset + @"TRST[2]": u1, + /// (4/5 of TRST) Timer X Counter Software Reset + @"TRST[3]": u1, + /// (5/5 of TRST) Timer X Counter Software Reset + @"TRST[4]": u1, + padding: u18, }), /// High Resolution Timer: Interrupt Status Register ISR: mmio.Mmio(packed struct(u32) { - /// Fault X Interrupt Flag - FLT: u1, - reserved5: u4, + /// (1/5 of FLT) Fault X Interrupt Flag + @"FLT[0]": u1, + /// (2/5 of FLT) Fault X Interrupt Flag + @"FLT[1]": u1, + /// (3/5 of FLT) Fault X Interrupt Flag + @"FLT[2]": u1, + /// (4/5 of FLT) Fault X Interrupt Flag + @"FLT[3]": u1, + /// (5/5 of FLT) Fault X Interrupt Flag + @"FLT[4]": u1, /// System Fault Interrupt Flag SYSFLT: u1, reserved16: u10, @@ -343087,9 +351932,16 @@ pub const types = struct { }), /// High Resolution Timer: Interrupt Clear Register ICR: mmio.Mmio(packed struct(u32) { - /// Fault X Interrupt Flag Clear - FLT: u1, - reserved5: u4, + /// (1/5 of FLT) Fault X Interrupt Flag Clear + @"FLT[0]": u1, + /// (2/5 of FLT) Fault X Interrupt Flag Clear + @"FLT[1]": u1, + /// (3/5 of FLT) Fault X Interrupt Flag Clear + @"FLT[2]": u1, + /// (4/5 of FLT) Fault X Interrupt Flag Clear + @"FLT[3]": u1, + /// (5/5 of FLT) Fault X Interrupt Flag Clear + @"FLT[4]": u1, /// System Fault Interrupt Flag Clear SYSFLT: u1, reserved16: u10, @@ -343101,9 +351953,16 @@ pub const types = struct { }), /// High Resolution Timer: Interrupt Enable Register IER: mmio.Mmio(packed struct(u32) { - /// Fault X Interrupt Flag Enable - FLT: u1, - reserved5: u4, + /// (1/5 of FLT) Fault X Interrupt Flag Enable + @"FLT[0]": u1, + /// (2/5 of FLT) Fault X Interrupt Flag Enable + @"FLT[1]": u1, + /// (3/5 of FLT) Fault X Interrupt Flag Enable + @"FLT[2]": u1, + /// (4/5 of FLT) Fault X Interrupt Flag Enable + @"FLT[3]": u1, + /// (5/5 of FLT) Fault X Interrupt Flag Enable + @"FLT[4]": u1, /// System Fault Interrupt Flag Enable SYSFLT: u1, reserved16: u10, @@ -343154,9 +352013,17 @@ pub const types = struct { reserved16: u5, /// Master Timer Burst Mode MTBM: u1, - /// Timer X Burst Mode - TBM: u1, - reserved31: u13, + /// (1/5 of TBM) Timer X Burst Mode + @"TBM[0]": u1, + /// (2/5 of TBM) Timer X Burst Mode + @"TBM[1]": u1, + /// (3/5 of TBM) Timer X Burst Mode + @"TBM[2]": u1, + /// (4/5 of TBM) Timer X Burst Mode + @"TBM[3]": u1, + /// (5/5 of TBM) Timer X Burst Mode + @"TBM[4]": u1, + reserved31: u9, BMSTAT: u1, }), /// High Resolution Timer: Burst Mode Trigger Register @@ -343167,9 +352034,14 @@ pub const types = struct { MSTRST: u1, /// Master repetition MSTREP: u1, - /// Master Compare X - MSTCMP: u1, - reserved7: u3, + /// (1/4 of MSTCMP) Master Compare X + @"MSTCMP[0]": u1, + /// (2/4 of MSTCMP) Master Compare X + @"MSTCMP[1]": u1, + /// (3/4 of MSTCMP) Master Compare X + @"MSTCMP[2]": u1, + /// (4/4 of MSTCMP) Master Compare X + @"MSTCMP[3]": u1, /// Timer X reset or roll-over TRST: u1, /// Timer X repetition @@ -343224,14 +352096,26 @@ pub const types = struct { }), /// High Resolution Timer: ADC Trigger [1, 3] Register ADC1R: mmio.Mmio(packed struct(u32) { - /// ADC trigger X on Master Compare Y - ADCMC: u1, - reserved4: u3, + /// (1/4 of ADCMC) ADC trigger X on Master Compare Y + @"ADCMC[0]": u1, + /// (2/4 of ADCMC) ADC trigger X on Master Compare Y + @"ADCMC[1]": u1, + /// (3/4 of ADCMC) ADC trigger X on Master Compare Y + @"ADCMC[2]": u1, + /// (4/4 of ADCMC) ADC trigger X on Master Compare Y + @"ADCMC[3]": u1, /// ADC trigger X on Master Period ADCMPER: u1, - /// ADC trigger X on External Event Y - ADCEEV: u1, - reserved10: u4, + /// (1/5 of ADCEEV) ADC trigger X on External Event Y + @"ADCEEV[0]": u1, + /// (2/5 of ADCEEV) ADC trigger X on External Event Y + @"ADCEEV[1]": u1, + /// (3/5 of ADCEEV) ADC trigger X on External Event Y + @"ADCEEV[2]": u1, + /// (4/5 of ADCEEV) ADC trigger X on External Event Y + @"ADCEEV[3]": u1, + /// (5/5 of ADCEEV) ADC trigger X on External Event Y + @"ADCEEV[4]": u1, /// ADC trigger X on Timer Y Compare 2 ADCTC2: u1, /// ADC trigger X on Timer Y Compare 3 @@ -343246,14 +352130,26 @@ pub const types = struct { }), /// High Resolution Timer: ADC Trigger [2, 4] Register ADC2R: mmio.Mmio(packed struct(u32) { - /// ADC trigger X on Master Compare Y - ADCMC: u1, - reserved4: u3, + /// (1/4 of ADCMC) ADC trigger X on Master Compare Y + @"ADCMC[0]": u1, + /// (2/4 of ADCMC) ADC trigger X on Master Compare Y + @"ADCMC[1]": u1, + /// (3/4 of ADCMC) ADC trigger X on Master Compare Y + @"ADCMC[2]": u1, + /// (4/4 of ADCMC) ADC trigger X on Master Compare Y + @"ADCMC[3]": u1, /// ADC trigger X on Master Period ADCMPER: u1, - /// ADC trigger X on External Event Y - ADCEEV: u1, - reserved10: u4, + /// (1/5 of ADCEEV) ADC trigger X on External Event Y + @"ADCEEV[0]": u1, + /// (2/5 of ADCEEV) ADC trigger X on External Event Y + @"ADCEEV[1]": u1, + /// (3/5 of ADCEEV) ADC trigger X on External Event Y + @"ADCEEV[2]": u1, + /// (4/5 of ADCEEV) ADC trigger X on External Event Y + @"ADCEEV[3]": u1, + /// (5/5 of ADCEEV) ADC trigger X on External Event Y + @"ADCEEV[4]": u1, /// ADC trigger X on Timer Y Compare 2 ADCTC2: u1, reserved12: u1, @@ -343309,9 +352205,15 @@ pub const types = struct { MPER: u1, /// MREP register update enable MREP: u1, - /// MCMP register X update enable - MCMP: u1, - padding: u25, + /// (1/4 of MCMP) MCMP register X update enable + @"MCMP[0]": u1, + /// (2/4 of MCMP) MCMP register X update enable + @"MCMP[1]": u1, + /// (3/4 of MCMP) MCMP register X update enable + @"MCMP[2]": u1, + /// (4/4 of MCMP) MCMP register X update enable + @"MCMP[3]": u1, + padding: u22, }), /// High Resolution Timer: Burst DMA Timer X update Register BDTUPR: [5]mmio.Mmio(packed struct(u32) { @@ -343327,9 +352229,15 @@ pub const types = struct { PER: u1, /// REP register update enable REP: u1, - /// CMP register X update enable - CMP: u1, - padding: u25, + /// (1/4 of CMP) CMP register X update enable + @"CMP[0]": u1, + /// (2/4 of CMP) CMP register X update enable + @"CMP[1]": u1, + /// (3/4 of CMP) CMP register X update enable + @"CMP[2]": u1, + /// (4/4 of CMP) CMP register X update enable + @"CMP[3]": u1, + padding: u22, }), /// High Resolution Timer: Burst DMA Data Register BDMADR: mmio.Mmio(packed struct(u32) { @@ -343388,17 +352296,23 @@ pub const types = struct { }), /// Timer X Interrupt Status Register ISR: mmio.Mmio(packed struct(u32) { - /// Compare X Interrupt Flag - CMP: u1, - reserved4: u3, + /// (1/4 of CMP) Compare X Interrupt Flag + @"CMP[0]": u1, + /// (2/4 of CMP) Compare X Interrupt Flag + @"CMP[1]": u1, + /// (3/4 of CMP) Compare X Interrupt Flag + @"CMP[2]": u1, + /// (4/4 of CMP) Compare X Interrupt Flag + @"CMP[3]": u1, /// Repetition Interrupt Flag REP: u1, reserved6: u1, /// Update Interrupt Flag UPD: u1, - /// Capture X Interrupt Flag - CPT: u1, - reserved9: u1, + /// (1/2 of CPT) Capture X Interrupt Flag + @"CPT[0]": u1, + /// (2/2 of CPT) Capture X Interrupt Flag + @"CPT[1]": u1, /// Output X Set Interrupt Flag SETR: u1, /// Output X Reset Interrupt Flag @@ -343413,26 +352327,35 @@ pub const types = struct { CPPSTAT: CPPSTAT, /// Idle Push Pull Status IPPSTAT: IPPSTAT, - /// Output X State - OSTAT: OUTPUTSTATE, - reserved20: u1, - /// Output X Copy - OCPY: OUTPUTSTATE, - padding: u11, + /// (1/2 of OSTAT) Output X State + @"OSTAT[0]": OUTPUTSTATE, + /// (2/2 of OSTAT) Output X State + @"OSTAT[1]": OUTPUTSTATE, + /// (1/2 of OCPY) Output X Copy + @"OCPY[0]": OUTPUTSTATE, + /// (2/2 of OCPY) Output X Copy + @"OCPY[1]": OUTPUTSTATE, + padding: u10, }), /// Timer X Interrupt Clear Register ICR: mmio.Mmio(packed struct(u32) { - /// Compare X Interrupt flag Clear - CMPC: u1, - reserved4: u3, + /// (1/4 of CMPC) Compare X Interrupt flag Clear + @"CMPC[0]": u1, + /// (2/4 of CMPC) Compare X Interrupt flag Clear + @"CMPC[1]": u1, + /// (3/4 of CMPC) Compare X Interrupt flag Clear + @"CMPC[2]": u1, + /// (4/4 of CMPC) Compare X Interrupt flag Clear + @"CMPC[3]": u1, /// Repetition Interrupt flag Clear REPC: u1, reserved6: u1, /// Update Interrupt flag Clear UPDC: u1, - /// Capture X Interrupt flag Clear - CPTC: u1, - reserved9: u1, + /// (1/2 of CPTC) Capture X Interrupt flag Clear + @"CPTC[0]": u1, + /// (2/2 of CPTC) Capture X Interrupt flag Clear + @"CPTC[1]": u1, /// Output X Set flag Clear SETRC: u1, /// Output X Reset flag Clear @@ -343446,17 +352369,23 @@ pub const types = struct { }), /// Timer X DMA / Interrupt Enable Register DIER: mmio.Mmio(packed struct(u32) { - /// Compare X Interrupt Enable - CMPIE: u1, - reserved4: u3, + /// (1/4 of CMPIE) Compare X Interrupt Enable + @"CMPIE[0]": u1, + /// (2/4 of CMPIE) Compare X Interrupt Enable + @"CMPIE[1]": u1, + /// (3/4 of CMPIE) Compare X Interrupt Enable + @"CMPIE[2]": u1, + /// (4/4 of CMPIE) Compare X Interrupt Enable + @"CMPIE[3]": u1, /// Repetition Interrupt Enable REPIE: u1, reserved6: u1, /// Update Interrupt Enable UPDIE: u1, - /// Capture Interrupt Enable - CPTIE: u1, - reserved9: u1, + /// (1/2 of CPTIE) Capture Interrupt Enable + @"CPTIE[0]": u1, + /// (2/2 of CPTIE) Capture Interrupt Enable + @"CPTIE[1]": u1, /// Output X Set Interrupt Enable SETRIE: u1, /// Output X Reset Interrupt Enable @@ -343467,17 +352396,23 @@ pub const types = struct { /// Delayed Protection Interrupt Enable DLYPRTIE: u1, reserved16: u1, - /// Compare X DMA request Enable - CMPDE: u1, - reserved20: u3, + /// (1/4 of CMPDE) Compare X DMA request Enable + @"CMPDE[0]": u1, + /// (2/4 of CMPDE) Compare X DMA request Enable + @"CMPDE[1]": u1, + /// (3/4 of CMPDE) Compare X DMA request Enable + @"CMPDE[2]": u1, + /// (4/4 of CMPDE) Compare X DMA request Enable + @"CMPDE[3]": u1, /// Repetition DMA request Enable REPDE: u1, reserved22: u1, /// Update DMA request Enable UPDDE: u1, - /// Capture X DMA request Enable - CPTDE: u1, - reserved25: u1, + /// (1/2 of CPTDE) Capture X DMA request Enable + @"CPTDE[0]": u1, + /// (2/2 of CPTDE) Capture X DMA request Enable + @"CPTDE[1]": u1, /// Output X Set DMA request Enable SETRDE: u1, /// Output X Reset DMA request Enable @@ -343559,20 +352494,62 @@ pub const types = struct { RESYNC: ACTIVEEFFECT, /// Timer X Period PER: ACTIVEEFFECT, - /// Timer X compare X - CMP: ACTIVEEFFECT, - reserved7: u3, + /// (1/4 of CMP) Timer X compare X + @"CMP[0]": ACTIVEEFFECT, + /// (2/4 of CMP) Timer X compare X + @"CMP[1]": ACTIVEEFFECT, + /// (3/4 of CMP) Timer X compare X + @"CMP[2]": ACTIVEEFFECT, + /// (4/4 of CMP) Timer X compare X + @"CMP[3]": ACTIVEEFFECT, /// Master Period MSTPER: ACTIVEEFFECT, - /// Master Compare X - MSTCMPX: ACTIVEEFFECT, - reserved12: u3, - /// Timer Event X - TIMEVNT: ACTIVEEFFECT, - reserved21: u8, - /// External Event X - EXTEVNT: ACTIVEEFFECT, - reserved31: u9, + /// (1/4 of MSTCMPX) Master Compare X + @"MSTCMPX[0]": ACTIVEEFFECT, + /// (2/4 of MSTCMPX) Master Compare X + @"MSTCMPX[1]": ACTIVEEFFECT, + /// (3/4 of MSTCMPX) Master Compare X + @"MSTCMPX[2]": ACTIVEEFFECT, + /// (4/4 of MSTCMPX) Master Compare X + @"MSTCMPX[3]": ACTIVEEFFECT, + /// (1/9 of TIMEVNT) Timer Event X + @"TIMEVNT[0]": ACTIVEEFFECT, + /// (2/9 of TIMEVNT) Timer Event X + @"TIMEVNT[1]": ACTIVEEFFECT, + /// (3/9 of TIMEVNT) Timer Event X + @"TIMEVNT[2]": ACTIVEEFFECT, + /// (4/9 of TIMEVNT) Timer Event X + @"TIMEVNT[3]": ACTIVEEFFECT, + /// (5/9 of TIMEVNT) Timer Event X + @"TIMEVNT[4]": ACTIVEEFFECT, + /// (6/9 of TIMEVNT) Timer Event X + @"TIMEVNT[5]": ACTIVEEFFECT, + /// (7/9 of TIMEVNT) Timer Event X + @"TIMEVNT[6]": ACTIVEEFFECT, + /// (8/9 of TIMEVNT) Timer Event X + @"TIMEVNT[7]": ACTIVEEFFECT, + /// (9/9 of TIMEVNT) Timer Event X + @"TIMEVNT[8]": ACTIVEEFFECT, + /// (1/10 of EXTEVNT) External Event X + @"EXTEVNT[0]": ACTIVEEFFECT, + /// (2/10 of EXTEVNT) External Event X + @"EXTEVNT[1]": ACTIVEEFFECT, + /// (3/10 of EXTEVNT) External Event X + @"EXTEVNT[2]": ACTIVEEFFECT, + /// (4/10 of EXTEVNT) External Event X + @"EXTEVNT[3]": ACTIVEEFFECT, + /// (5/10 of EXTEVNT) External Event X + @"EXTEVNT[4]": ACTIVEEFFECT, + /// (6/10 of EXTEVNT) External Event X + @"EXTEVNT[5]": ACTIVEEFFECT, + /// (7/10 of EXTEVNT) External Event X + @"EXTEVNT[6]": ACTIVEEFFECT, + /// (8/10 of EXTEVNT) External Event X + @"EXTEVNT[7]": ACTIVEEFFECT, + /// (9/10 of EXTEVNT) External Event X + @"EXTEVNT[8]": ACTIVEEFFECT, + /// (10/10 of EXTEVNT) External Event X + @"EXTEVNT[9]": ACTIVEEFFECT, /// Registers update (transfer preload to active) UPDATE: ACTIVEEFFECT, }), @@ -343584,31 +352561,93 @@ pub const types = struct { RESYNC: INACTIVEEFFECT, /// Timer X Period PER: INACTIVEEFFECT, - /// Timer X compare X - CMP: INACTIVEEFFECT, - reserved7: u3, + /// (1/4 of CMP) Timer X compare X + @"CMP[0]": INACTIVEEFFECT, + /// (2/4 of CMP) Timer X compare X + @"CMP[1]": INACTIVEEFFECT, + /// (3/4 of CMP) Timer X compare X + @"CMP[2]": INACTIVEEFFECT, + /// (4/4 of CMP) Timer X compare X + @"CMP[3]": INACTIVEEFFECT, /// Master Period MSTPER: INACTIVEEFFECT, - /// Master Compare X - MSTCMP: INACTIVEEFFECT, - reserved12: u3, - /// Timer Event X - TIMEVNT: INACTIVEEFFECT, - reserved21: u8, - /// External Event X - EXTEVNT: INACTIVEEFFECT, - reserved31: u9, + /// (1/4 of MSTCMP) Master Compare X + @"MSTCMP[0]": INACTIVEEFFECT, + /// (2/4 of MSTCMP) Master Compare X + @"MSTCMP[1]": INACTIVEEFFECT, + /// (3/4 of MSTCMP) Master Compare X + @"MSTCMP[2]": INACTIVEEFFECT, + /// (4/4 of MSTCMP) Master Compare X + @"MSTCMP[3]": INACTIVEEFFECT, + /// (1/9 of TIMEVNT) Timer Event X + @"TIMEVNT[0]": INACTIVEEFFECT, + /// (2/9 of TIMEVNT) Timer Event X + @"TIMEVNT[1]": INACTIVEEFFECT, + /// (3/9 of TIMEVNT) Timer Event X + @"TIMEVNT[2]": INACTIVEEFFECT, + /// (4/9 of TIMEVNT) Timer Event X + @"TIMEVNT[3]": INACTIVEEFFECT, + /// (5/9 of TIMEVNT) Timer Event X + @"TIMEVNT[4]": INACTIVEEFFECT, + /// (6/9 of TIMEVNT) Timer Event X + @"TIMEVNT[5]": INACTIVEEFFECT, + /// (7/9 of TIMEVNT) Timer Event X + @"TIMEVNT[6]": INACTIVEEFFECT, + /// (8/9 of TIMEVNT) Timer Event X + @"TIMEVNT[7]": INACTIVEEFFECT, + /// (9/9 of TIMEVNT) Timer Event X + @"TIMEVNT[8]": INACTIVEEFFECT, + /// (1/10 of EXTEVNT) External Event X + @"EXTEVNT[0]": INACTIVEEFFECT, + /// (2/10 of EXTEVNT) External Event X + @"EXTEVNT[1]": INACTIVEEFFECT, + /// (3/10 of EXTEVNT) External Event X + @"EXTEVNT[2]": INACTIVEEFFECT, + /// (4/10 of EXTEVNT) External Event X + @"EXTEVNT[3]": INACTIVEEFFECT, + /// (5/10 of EXTEVNT) External Event X + @"EXTEVNT[4]": INACTIVEEFFECT, + /// (6/10 of EXTEVNT) External Event X + @"EXTEVNT[5]": INACTIVEEFFECT, + /// (7/10 of EXTEVNT) External Event X + @"EXTEVNT[6]": INACTIVEEFFECT, + /// (8/10 of EXTEVNT) External Event X + @"EXTEVNT[7]": INACTIVEEFFECT, + /// (9/10 of EXTEVNT) External Event X + @"EXTEVNT[8]": INACTIVEEFFECT, + /// (10/10 of EXTEVNT) External Event X + @"EXTEVNT[9]": INACTIVEEFFECT, /// Registers update (transfer preload to active) UPDATE: INACTIVEEFFECT, }), reserved76: [8]u8, /// Timer X External Event Filtering Register 1 EEF: mmio.Mmio(packed struct(u32) { - /// External Event X latch - LTCH: u1, - /// External Event X filter - FLTR: EEFLTR, - padding: u27, + /// (1/5 of LTCH) External Event X latch + @"LTCH[0]": u1, + /// (1/5 of FLTR) External Event X filter + @"FLTR[0]": EEFLTR, + reserved6: u1, + /// (2/5 of LTCH) External Event X latch + @"LTCH[1]": u1, + /// (2/5 of FLTR) External Event X filter + @"FLTR[1]": EEFLTR, + reserved12: u1, + /// (3/5 of LTCH) External Event X latch + @"LTCH[2]": u1, + /// (3/5 of FLTR) External Event X filter + @"FLTR[2]": EEFLTR, + reserved18: u1, + /// (4/5 of LTCH) External Event X latch + @"LTCH[3]": u1, + /// (4/5 of FLTR) External Event X filter + @"FLTR[3]": EEFLTR, + reserved24: u1, + /// (5/5 of LTCH) External Event X latch + @"LTCH[4]": u1, + /// (5/5 of FLTR) External Event X filter + @"FLTR[4]": EEFLTR, + padding: u3, }), reserved84: [4]u8, /// Timer X Reset Register @@ -343617,17 +352656,41 @@ pub const types = struct { TCMP1: RESETEFFECT, /// Timer X Update reset UPDT: RESETEFFECT, - /// Timer X compare X reset - CMP: RESETEFFECT, - reserved4: u1, + /// (1/2 of CMP) Timer X compare X reset + @"CMP[0]": RESETEFFECT, + /// (2/2 of CMP) Timer X compare X reset + @"CMP[1]": RESETEFFECT, /// Master timer Period MSTPER: RESETEFFECT, - /// Master compare X - MSTCMP: RESETEFFECT, - reserved9: u3, - /// External Event X - EXTEVNT: RESETEFFECT, - reserved20: u10, + /// (1/4 of MSTCMP) Master compare X + @"MSTCMP[0]": RESETEFFECT, + /// (2/4 of MSTCMP) Master compare X + @"MSTCMP[1]": RESETEFFECT, + /// (3/4 of MSTCMP) Master compare X + @"MSTCMP[2]": RESETEFFECT, + /// (4/4 of MSTCMP) Master compare X + @"MSTCMP[3]": RESETEFFECT, + /// (1/10 of EXTEVNT) External Event X + @"EXTEVNT[0]": RESETEFFECT, + /// (2/10 of EXTEVNT) External Event X + @"EXTEVNT[1]": RESETEFFECT, + /// (3/10 of EXTEVNT) External Event X + @"EXTEVNT[2]": RESETEFFECT, + /// (4/10 of EXTEVNT) External Event X + @"EXTEVNT[3]": RESETEFFECT, + /// (5/10 of EXTEVNT) External Event X + @"EXTEVNT[4]": RESETEFFECT, + /// (6/10 of EXTEVNT) External Event X + @"EXTEVNT[5]": RESETEFFECT, + /// (7/10 of EXTEVNT) External Event X + @"EXTEVNT[6]": RESETEFFECT, + /// (8/10 of EXTEVNT) External Event X + @"EXTEVNT[7]": RESETEFFECT, + /// (9/10 of EXTEVNT) External Event X + @"EXTEVNT[8]": RESETEFFECT, + /// (10/10 of EXTEVNT) External Event X + @"EXTEVNT[9]": RESETEFFECT, + reserved20: u1, /// Timer X compare 2 event TCMP2: RESETEFFECT, /// Timer X compare 4 event @@ -343650,37 +352713,59 @@ pub const types = struct { SWCPT: CAPTUREEFFECT, /// Update Capture UPDCPT: CAPTUREEFFECT, - /// External Event X Capture - EXEVCPT: CAPTUREEFFECT, - reserved16: u13, + /// (1/10 of EXEVCPT) External Event X Capture + @"EXEVCPT[0]": CAPTUREEFFECT, + /// (2/10 of EXEVCPT) External Event X Capture + @"EXEVCPT[1]": CAPTUREEFFECT, + /// (3/10 of EXEVCPT) External Event X Capture + @"EXEVCPT[2]": CAPTUREEFFECT, + /// (4/10 of EXEVCPT) External Event X Capture + @"EXEVCPT[3]": CAPTUREEFFECT, + /// (5/10 of EXEVCPT) External Event X Capture + @"EXEVCPT[4]": CAPTUREEFFECT, + /// (6/10 of EXEVCPT) External Event X Capture + @"EXEVCPT[5]": CAPTUREEFFECT, + /// (7/10 of EXEVCPT) External Event X Capture + @"EXEVCPT[6]": CAPTUREEFFECT, + /// (8/10 of EXEVCPT) External Event X Capture + @"EXEVCPT[7]": CAPTUREEFFECT, + /// (9/10 of EXEVCPT) External Event X Capture + @"EXEVCPT[8]": CAPTUREEFFECT, + /// (10/10 of EXEVCPT) External Event X Capture + @"EXEVCPT[9]": CAPTUREEFFECT, + reserved16: u4, /// Timer X output Set TXSET: CAPTUREEFFECT, /// Timer X output Reset TXRST: CAPTUREEFFECT, - /// Timer X Compare X - TXCMP: CAPTUREEFFECT, - reserved20: u1, + /// (1/2 of TXCMP) Timer X Compare X + @"TXCMP[0]": CAPTUREEFFECT, + /// (2/2 of TXCMP) Timer X Compare X + @"TXCMP[1]": CAPTUREEFFECT, /// Timer Y output Set TYSET: CAPTUREEFFECT, /// Timer Y output Reset TYRST: CAPTUREEFFECT, - /// Timer Y Compare X - TYCMP: CAPTUREEFFECT, - reserved24: u1, + /// (1/2 of TYCMP) Timer Y Compare X + @"TYCMP[0]": CAPTUREEFFECT, + /// (2/2 of TYCMP) Timer Y Compare X + @"TYCMP[1]": CAPTUREEFFECT, /// Timer Z output Set TZSET: CAPTUREEFFECT, /// Timer Z output Reset TZRST: CAPTUREEFFECT, - /// Timer Z Compare X - TZCMP: CAPTUREEFFECT, - reserved28: u1, + /// (1/2 of TZCMP) Timer Z Compare X + @"TZCMP[0]": CAPTUREEFFECT, + /// (2/2 of TZCMP) Timer Z Compare X + @"TZCMP[1]": CAPTUREEFFECT, /// Timer T output Set TTSET: CAPTUREEFFECT, /// Timer T output Reset TTRST: CAPTUREEFFECT, - /// Timer T Compare X - TTCMP: CAPTUREEFFECT, - padding: u1, + /// (1/2 of TTCMP) Timer T Compare X + @"TTCMP[0]": CAPTUREEFFECT, + /// (2/2 of TTCMP) Timer T Compare X + @"TTCMP[1]": CAPTUREEFFECT, }), reserved100: [4]u8, /// Timer X Output Register @@ -343708,9 +352793,17 @@ pub const types = struct { }), /// Timer X Fault Register FLT: mmio.Mmio(packed struct(u32) { - /// Fault X enable - FLTEN: FLTEN, - reserved31: u30, + /// (1/5 of FLTEN) Fault X enable + @"FLTEN[0]": FLTEN, + /// (2/5 of FLTEN) Fault X enable + @"FLTEN[1]": FLTEN, + /// (3/5 of FLTEN) Fault X enable + @"FLTEN[2]": FLTEN, + /// (4/5 of FLTEN) Fault X enable + @"FLTEN[3]": FLTEN, + /// (5/5 of FLTEN) Fault X enable + @"FLTEN[4]": FLTEN, + reserved31: u26, /// Fault sources Lock FLTLCK: u1, }), @@ -343742,27 +352835,271 @@ pub const types = struct { }), /// HSEM Interrupt enable register. IER: mmio.Mmio(packed struct(u32) { - /// Interrupt semaphore x enable bit. - ISE: u1, - padding: u31, + /// (1/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[0]": u1, + /// (2/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[1]": u1, + /// (3/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[2]": u1, + /// (4/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[3]": u1, + /// (5/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[4]": u1, + /// (6/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[5]": u1, + /// (7/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[6]": u1, + /// (8/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[7]": u1, + /// (9/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[8]": u1, + /// (10/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[9]": u1, + /// (11/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[10]": u1, + /// (12/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[11]": u1, + /// (13/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[12]": u1, + /// (14/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[13]": u1, + /// (15/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[14]": u1, + /// (16/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[15]": u1, + /// (17/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[16]": u1, + /// (18/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[17]": u1, + /// (19/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[18]": u1, + /// (20/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[19]": u1, + /// (21/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[20]": u1, + /// (22/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[21]": u1, + /// (23/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[22]": u1, + /// (24/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[23]": u1, + /// (25/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[24]": u1, + /// (26/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[25]": u1, + /// (27/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[26]": u1, + /// (28/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[27]": u1, + /// (29/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[28]": u1, + /// (30/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[29]": u1, + /// (31/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[30]": u1, + /// (32/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[31]": u1, }), /// HSEM Interrupt clear register. ICR: mmio.Mmio(packed struct(u32) { - /// Interrupt semaphore x clear bit. - ISC: u1, - padding: u31, + /// (1/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[0]": u1, + /// (2/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[1]": u1, + /// (3/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[2]": u1, + /// (4/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[3]": u1, + /// (5/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[4]": u1, + /// (6/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[5]": u1, + /// (7/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[6]": u1, + /// (8/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[7]": u1, + /// (9/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[8]": u1, + /// (10/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[9]": u1, + /// (11/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[10]": u1, + /// (12/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[11]": u1, + /// (13/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[12]": u1, + /// (14/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[13]": u1, + /// (15/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[14]": u1, + /// (16/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[15]": u1, + /// (17/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[16]": u1, + /// (18/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[17]": u1, + /// (19/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[18]": u1, + /// (20/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[19]": u1, + /// (21/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[20]": u1, + /// (22/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[21]": u1, + /// (23/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[22]": u1, + /// (24/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[23]": u1, + /// (25/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[24]": u1, + /// (26/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[25]": u1, + /// (27/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[26]": u1, + /// (28/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[27]": u1, + /// (29/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[28]": u1, + /// (30/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[29]": u1, + /// (31/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[30]": u1, + /// (32/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[31]": u1, }), /// HSEM Interrupt status register. ISR: mmio.Mmio(packed struct(u32) { - /// Interrupt semaphore x status bit before enable (mask). - ISF: u1, - padding: u31, + /// (1/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[0]": u1, + /// (2/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[1]": u1, + /// (3/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[2]": u1, + /// (4/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[3]": u1, + /// (5/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[4]": u1, + /// (6/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[5]": u1, + /// (7/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[6]": u1, + /// (8/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[7]": u1, + /// (9/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[8]": u1, + /// (10/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[9]": u1, + /// (11/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[10]": u1, + /// (12/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[11]": u1, + /// (13/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[12]": u1, + /// (14/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[13]": u1, + /// (15/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[14]": u1, + /// (16/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[15]": u1, + /// (17/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[16]": u1, + /// (18/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[17]": u1, + /// (19/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[18]": u1, + /// (20/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[19]": u1, + /// (21/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[20]": u1, + /// (22/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[21]": u1, + /// (23/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[22]": u1, + /// (24/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[23]": u1, + /// (25/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[24]": u1, + /// (26/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[25]": u1, + /// (27/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[26]": u1, + /// (28/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[27]": u1, + /// (29/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[28]": u1, + /// (30/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[29]": u1, + /// (31/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[30]": u1, + /// (32/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[31]": u1, }), /// HSEM Masked interrupt status register. MISR: mmio.Mmio(packed struct(u32) { - /// masked interrupt semaphore x status bit after enable (mask). - MISF: u1, - padding: u31, + /// (1/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[0]": u1, + /// (2/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[1]": u1, + /// (3/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[2]": u1, + /// (4/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[3]": u1, + /// (5/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[4]": u1, + /// (6/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[5]": u1, + /// (7/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[6]": u1, + /// (8/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[7]": u1, + /// (9/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[8]": u1, + /// (10/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[9]": u1, + /// (11/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[10]": u1, + /// (12/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[11]": u1, + /// (13/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[12]": u1, + /// (14/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[13]": u1, + /// (15/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[14]": u1, + /// (16/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[15]": u1, + /// (17/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[16]": u1, + /// (18/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[17]": u1, + /// (19/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[18]": u1, + /// (20/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[19]": u1, + /// (21/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[20]": u1, + /// (22/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[21]": u1, + /// (23/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[22]": u1, + /// (24/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[23]": u1, + /// (25/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[24]": u1, + /// (26/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[25]": u1, + /// (27/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[26]": u1, + /// (28/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[27]": u1, + /// (29/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[28]": u1, + /// (30/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[29]": u1, + /// (31/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[30]": u1, + /// (32/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[31]": u1, }), reserved320: [48]u8, /// HSEM Clear register. @@ -343808,27 +353145,271 @@ pub const types = struct { }), /// HSEM Interrupt enable register. IER: mmio.Mmio(packed struct(u32) { - /// Interrupt semaphore x enable bit. - ISE: u1, - padding: u31, + /// (1/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[0]": u1, + /// (2/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[1]": u1, + /// (3/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[2]": u1, + /// (4/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[3]": u1, + /// (5/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[4]": u1, + /// (6/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[5]": u1, + /// (7/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[6]": u1, + /// (8/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[7]": u1, + /// (9/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[8]": u1, + /// (10/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[9]": u1, + /// (11/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[10]": u1, + /// (12/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[11]": u1, + /// (13/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[12]": u1, + /// (14/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[13]": u1, + /// (15/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[14]": u1, + /// (16/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[15]": u1, + /// (17/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[16]": u1, + /// (18/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[17]": u1, + /// (19/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[18]": u1, + /// (20/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[19]": u1, + /// (21/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[20]": u1, + /// (22/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[21]": u1, + /// (23/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[22]": u1, + /// (24/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[23]": u1, + /// (25/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[24]": u1, + /// (26/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[25]": u1, + /// (27/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[26]": u1, + /// (28/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[27]": u1, + /// (29/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[28]": u1, + /// (30/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[29]": u1, + /// (31/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[30]": u1, + /// (32/32 of ISE) Interrupt semaphore x enable bit. + @"ISE[31]": u1, }), /// HSEM Interrupt clear register. ICR: mmio.Mmio(packed struct(u32) { - /// Interrupt semaphore x clear bit. - ISC: u1, - padding: u31, + /// (1/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[0]": u1, + /// (2/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[1]": u1, + /// (3/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[2]": u1, + /// (4/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[3]": u1, + /// (5/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[4]": u1, + /// (6/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[5]": u1, + /// (7/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[6]": u1, + /// (8/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[7]": u1, + /// (9/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[8]": u1, + /// (10/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[9]": u1, + /// (11/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[10]": u1, + /// (12/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[11]": u1, + /// (13/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[12]": u1, + /// (14/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[13]": u1, + /// (15/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[14]": u1, + /// (16/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[15]": u1, + /// (17/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[16]": u1, + /// (18/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[17]": u1, + /// (19/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[18]": u1, + /// (20/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[19]": u1, + /// (21/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[20]": u1, + /// (22/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[21]": u1, + /// (23/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[22]": u1, + /// (24/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[23]": u1, + /// (25/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[24]": u1, + /// (26/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[25]": u1, + /// (27/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[26]": u1, + /// (28/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[27]": u1, + /// (29/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[28]": u1, + /// (30/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[29]": u1, + /// (31/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[30]": u1, + /// (32/32 of ISC) Interrupt semaphore x clear bit. + @"ISC[31]": u1, }), /// HSEM Interrupt status register. ISR: mmio.Mmio(packed struct(u32) { - /// Interrupt semaphore x status bit before enable (mask). - ISF: u1, - padding: u31, + /// (1/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[0]": u1, + /// (2/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[1]": u1, + /// (3/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[2]": u1, + /// (4/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[3]": u1, + /// (5/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[4]": u1, + /// (6/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[5]": u1, + /// (7/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[6]": u1, + /// (8/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[7]": u1, + /// (9/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[8]": u1, + /// (10/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[9]": u1, + /// (11/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[10]": u1, + /// (12/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[11]": u1, + /// (13/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[12]": u1, + /// (14/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[13]": u1, + /// (15/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[14]": u1, + /// (16/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[15]": u1, + /// (17/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[16]": u1, + /// (18/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[17]": u1, + /// (19/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[18]": u1, + /// (20/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[19]": u1, + /// (21/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[20]": u1, + /// (22/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[21]": u1, + /// (23/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[22]": u1, + /// (24/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[23]": u1, + /// (25/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[24]": u1, + /// (26/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[25]": u1, + /// (27/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[26]": u1, + /// (28/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[27]": u1, + /// (29/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[28]": u1, + /// (30/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[29]": u1, + /// (31/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[30]": u1, + /// (32/32 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[31]": u1, }), /// HSEM Masked interrupt status register. MISR: mmio.Mmio(packed struct(u32) { - /// masked interrupt semaphore x status bit after enable (mask). - MISF: u1, - padding: u31, + /// (1/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[0]": u1, + /// (2/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[1]": u1, + /// (3/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[2]": u1, + /// (4/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[3]": u1, + /// (5/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[4]": u1, + /// (6/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[5]": u1, + /// (7/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[6]": u1, + /// (8/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[7]": u1, + /// (9/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[8]": u1, + /// (10/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[9]": u1, + /// (11/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[10]": u1, + /// (12/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[11]": u1, + /// (13/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[12]": u1, + /// (14/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[13]": u1, + /// (15/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[14]": u1, + /// (16/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[15]": u1, + /// (17/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[16]": u1, + /// (18/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[17]": u1, + /// (19/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[18]": u1, + /// (20/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[19]": u1, + /// (21/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[20]": u1, + /// (22/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[21]": u1, + /// (23/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[22]": u1, + /// (24/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[23]": u1, + /// (25/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[24]": u1, + /// (26/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[25]": u1, + /// (27/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[26]": u1, + /// (28/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[27]": u1, + /// (29/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[28]": u1, + /// (30/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[29]": u1, + /// (31/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[30]": u1, + /// (32/32 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[31]": u1, }), reserved320: [48]u8, /// HSEM Clear register. @@ -343876,27 +353457,147 @@ pub const types = struct { reserved256: [64]u8, /// HSEM Interrupt enable register. IER: mmio.Mmio(packed struct(u32) { - /// Interrupt semaphore x enable bit. - ISE: u1, - padding: u31, + /// (1/16 of ISE) Interrupt semaphore x enable bit. + @"ISE[0]": u1, + /// (2/16 of ISE) Interrupt semaphore x enable bit. + @"ISE[1]": u1, + /// (3/16 of ISE) Interrupt semaphore x enable bit. + @"ISE[2]": u1, + /// (4/16 of ISE) Interrupt semaphore x enable bit. + @"ISE[3]": u1, + /// (5/16 of ISE) Interrupt semaphore x enable bit. + @"ISE[4]": u1, + /// (6/16 of ISE) Interrupt semaphore x enable bit. + @"ISE[5]": u1, + /// (7/16 of ISE) Interrupt semaphore x enable bit. + @"ISE[6]": u1, + /// (8/16 of ISE) Interrupt semaphore x enable bit. + @"ISE[7]": u1, + /// (9/16 of ISE) Interrupt semaphore x enable bit. + @"ISE[8]": u1, + /// (10/16 of ISE) Interrupt semaphore x enable bit. + @"ISE[9]": u1, + /// (11/16 of ISE) Interrupt semaphore x enable bit. + @"ISE[10]": u1, + /// (12/16 of ISE) Interrupt semaphore x enable bit. + @"ISE[11]": u1, + /// (13/16 of ISE) Interrupt semaphore x enable bit. + @"ISE[12]": u1, + /// (14/16 of ISE) Interrupt semaphore x enable bit. + @"ISE[13]": u1, + /// (15/16 of ISE) Interrupt semaphore x enable bit. + @"ISE[14]": u1, + /// (16/16 of ISE) Interrupt semaphore x enable bit. + @"ISE[15]": u1, + padding: u16, }), /// HSEM Interrupt clear register. ICR: mmio.Mmio(packed struct(u32) { - /// Interrupt semaphore x clear bit. - ISC: u1, - padding: u31, + /// (1/16 of ISC) Interrupt semaphore x clear bit. + @"ISC[0]": u1, + /// (2/16 of ISC) Interrupt semaphore x clear bit. + @"ISC[1]": u1, + /// (3/16 of ISC) Interrupt semaphore x clear bit. + @"ISC[2]": u1, + /// (4/16 of ISC) Interrupt semaphore x clear bit. + @"ISC[3]": u1, + /// (5/16 of ISC) Interrupt semaphore x clear bit. + @"ISC[4]": u1, + /// (6/16 of ISC) Interrupt semaphore x clear bit. + @"ISC[5]": u1, + /// (7/16 of ISC) Interrupt semaphore x clear bit. + @"ISC[6]": u1, + /// (8/16 of ISC) Interrupt semaphore x clear bit. + @"ISC[7]": u1, + /// (9/16 of ISC) Interrupt semaphore x clear bit. + @"ISC[8]": u1, + /// (10/16 of ISC) Interrupt semaphore x clear bit. + @"ISC[9]": u1, + /// (11/16 of ISC) Interrupt semaphore x clear bit. + @"ISC[10]": u1, + /// (12/16 of ISC) Interrupt semaphore x clear bit. + @"ISC[11]": u1, + /// (13/16 of ISC) Interrupt semaphore x clear bit. + @"ISC[12]": u1, + /// (14/16 of ISC) Interrupt semaphore x clear bit. + @"ISC[13]": u1, + /// (15/16 of ISC) Interrupt semaphore x clear bit. + @"ISC[14]": u1, + /// (16/16 of ISC) Interrupt semaphore x clear bit. + @"ISC[15]": u1, + padding: u16, }), /// HSEM Interrupt status register. ISR: mmio.Mmio(packed struct(u32) { - /// Interrupt semaphore x status bit before enable (mask). - ISF: u1, - padding: u31, + /// (1/16 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[0]": u1, + /// (2/16 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[1]": u1, + /// (3/16 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[2]": u1, + /// (4/16 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[3]": u1, + /// (5/16 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[4]": u1, + /// (6/16 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[5]": u1, + /// (7/16 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[6]": u1, + /// (8/16 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[7]": u1, + /// (9/16 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[8]": u1, + /// (10/16 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[9]": u1, + /// (11/16 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[10]": u1, + /// (12/16 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[11]": u1, + /// (13/16 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[12]": u1, + /// (14/16 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[13]": u1, + /// (15/16 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[14]": u1, + /// (16/16 of ISF) Interrupt semaphore x status bit before enable (mask). + @"ISF[15]": u1, + padding: u16, }), /// HSEM Masked interrupt status register. MISR: mmio.Mmio(packed struct(u32) { - /// masked interrupt semaphore x status bit after enable (mask). - MISF: u1, - padding: u31, + /// (1/16 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[0]": u1, + /// (2/16 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[1]": u1, + /// (3/16 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[2]": u1, + /// (4/16 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[3]": u1, + /// (5/16 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[4]": u1, + /// (6/16 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[5]": u1, + /// (7/16 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[6]": u1, + /// (8/16 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[7]": u1, + /// (9/16 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[8]": u1, + /// (10/16 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[9]": u1, + /// (11/16 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[10]": u1, + /// (12/16 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[11]": u1, + /// (13/16 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[12]": u1, + /// (14/16 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[13]": u1, + /// (15/16 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[14]": u1, + /// (16/16 of MISF) masked interrupt semaphore x status bit after enable (mask). + @"MISF[15]": u1, + padding: u16, }), reserved320: [48]u8, /// HSEM Clear register. @@ -343944,27 +353645,147 @@ pub const types = struct { reserved256: [64]u8, /// HSEM Interrupt enable register. IER: mmio.Mmio(packed struct(u32) { - /// Interrupt semaphore n enable bit. - ISE: u1, - padding: u31, + /// (1/16 of ISE) Interrupt semaphore n enable bit. + @"ISE[0]": u1, + /// (2/16 of ISE) Interrupt semaphore n enable bit. + @"ISE[1]": u1, + /// (3/16 of ISE) Interrupt semaphore n enable bit. + @"ISE[2]": u1, + /// (4/16 of ISE) Interrupt semaphore n enable bit. + @"ISE[3]": u1, + /// (5/16 of ISE) Interrupt semaphore n enable bit. + @"ISE[4]": u1, + /// (6/16 of ISE) Interrupt semaphore n enable bit. + @"ISE[5]": u1, + /// (7/16 of ISE) Interrupt semaphore n enable bit. + @"ISE[6]": u1, + /// (8/16 of ISE) Interrupt semaphore n enable bit. + @"ISE[7]": u1, + /// (9/16 of ISE) Interrupt semaphore n enable bit. + @"ISE[8]": u1, + /// (10/16 of ISE) Interrupt semaphore n enable bit. + @"ISE[9]": u1, + /// (11/16 of ISE) Interrupt semaphore n enable bit. + @"ISE[10]": u1, + /// (12/16 of ISE) Interrupt semaphore n enable bit. + @"ISE[11]": u1, + /// (13/16 of ISE) Interrupt semaphore n enable bit. + @"ISE[12]": u1, + /// (14/16 of ISE) Interrupt semaphore n enable bit. + @"ISE[13]": u1, + /// (15/16 of ISE) Interrupt semaphore n enable bit. + @"ISE[14]": u1, + /// (16/16 of ISE) Interrupt semaphore n enable bit. + @"ISE[15]": u1, + padding: u16, }), /// HSEM Interrupt clear register. ICR: mmio.Mmio(packed struct(u32) { - /// Interrupt(N) semaphore n clear bit. - ISC: u1, - padding: u31, + /// (1/16 of ISC) Interrupt(N) semaphore n clear bit. + @"ISC[0]": u1, + /// (2/16 of ISC) Interrupt(N) semaphore n clear bit. + @"ISC[1]": u1, + /// (3/16 of ISC) Interrupt(N) semaphore n clear bit. + @"ISC[2]": u1, + /// (4/16 of ISC) Interrupt(N) semaphore n clear bit. + @"ISC[3]": u1, + /// (5/16 of ISC) Interrupt(N) semaphore n clear bit. + @"ISC[4]": u1, + /// (6/16 of ISC) Interrupt(N) semaphore n clear bit. + @"ISC[5]": u1, + /// (7/16 of ISC) Interrupt(N) semaphore n clear bit. + @"ISC[6]": u1, + /// (8/16 of ISC) Interrupt(N) semaphore n clear bit. + @"ISC[7]": u1, + /// (9/16 of ISC) Interrupt(N) semaphore n clear bit. + @"ISC[8]": u1, + /// (10/16 of ISC) Interrupt(N) semaphore n clear bit. + @"ISC[9]": u1, + /// (11/16 of ISC) Interrupt(N) semaphore n clear bit. + @"ISC[10]": u1, + /// (12/16 of ISC) Interrupt(N) semaphore n clear bit. + @"ISC[11]": u1, + /// (13/16 of ISC) Interrupt(N) semaphore n clear bit. + @"ISC[12]": u1, + /// (14/16 of ISC) Interrupt(N) semaphore n clear bit. + @"ISC[13]": u1, + /// (15/16 of ISC) Interrupt(N) semaphore n clear bit. + @"ISC[14]": u1, + /// (16/16 of ISC) Interrupt(N) semaphore n clear bit. + @"ISC[15]": u1, + padding: u16, }), /// HSEM Interrupt status register. ISR: mmio.Mmio(packed struct(u32) { - /// Interrupt(N) semaphore n status bit before enable (mask). - ISF: u1, - padding: u31, + /// (1/16 of ISF) Interrupt(N) semaphore n status bit before enable (mask). + @"ISF[0]": u1, + /// (2/16 of ISF) Interrupt(N) semaphore n status bit before enable (mask). + @"ISF[1]": u1, + /// (3/16 of ISF) Interrupt(N) semaphore n status bit before enable (mask). + @"ISF[2]": u1, + /// (4/16 of ISF) Interrupt(N) semaphore n status bit before enable (mask). + @"ISF[3]": u1, + /// (5/16 of ISF) Interrupt(N) semaphore n status bit before enable (mask). + @"ISF[4]": u1, + /// (6/16 of ISF) Interrupt(N) semaphore n status bit before enable (mask). + @"ISF[5]": u1, + /// (7/16 of ISF) Interrupt(N) semaphore n status bit before enable (mask). + @"ISF[6]": u1, + /// (8/16 of ISF) Interrupt(N) semaphore n status bit before enable (mask). + @"ISF[7]": u1, + /// (9/16 of ISF) Interrupt(N) semaphore n status bit before enable (mask). + @"ISF[8]": u1, + /// (10/16 of ISF) Interrupt(N) semaphore n status bit before enable (mask). + @"ISF[9]": u1, + /// (11/16 of ISF) Interrupt(N) semaphore n status bit before enable (mask). + @"ISF[10]": u1, + /// (12/16 of ISF) Interrupt(N) semaphore n status bit before enable (mask). + @"ISF[11]": u1, + /// (13/16 of ISF) Interrupt(N) semaphore n status bit before enable (mask). + @"ISF[12]": u1, + /// (14/16 of ISF) Interrupt(N) semaphore n status bit before enable (mask). + @"ISF[13]": u1, + /// (15/16 of ISF) Interrupt(N) semaphore n status bit before enable (mask). + @"ISF[14]": u1, + /// (16/16 of ISF) Interrupt(N) semaphore n status bit before enable (mask). + @"ISF[15]": u1, + padding: u16, }), /// HSEM Masked interrupt status register. MISR: mmio.Mmio(packed struct(u32) { - /// masked interrupt(N) semaphore n status bit after enable (mask). - MISF: u1, - padding: u31, + /// (1/16 of MISF) masked interrupt(N) semaphore n status bit after enable (mask). + @"MISF[0]": u1, + /// (2/16 of MISF) masked interrupt(N) semaphore n status bit after enable (mask). + @"MISF[1]": u1, + /// (3/16 of MISF) masked interrupt(N) semaphore n status bit after enable (mask). + @"MISF[2]": u1, + /// (4/16 of MISF) masked interrupt(N) semaphore n status bit after enable (mask). + @"MISF[3]": u1, + /// (5/16 of MISF) masked interrupt(N) semaphore n status bit after enable (mask). + @"MISF[4]": u1, + /// (6/16 of MISF) masked interrupt(N) semaphore n status bit after enable (mask). + @"MISF[5]": u1, + /// (7/16 of MISF) masked interrupt(N) semaphore n status bit after enable (mask). + @"MISF[6]": u1, + /// (8/16 of MISF) masked interrupt(N) semaphore n status bit after enable (mask). + @"MISF[7]": u1, + /// (9/16 of MISF) masked interrupt(N) semaphore n status bit after enable (mask). + @"MISF[8]": u1, + /// (10/16 of MISF) masked interrupt(N) semaphore n status bit after enable (mask). + @"MISF[9]": u1, + /// (11/16 of MISF) masked interrupt(N) semaphore n status bit after enable (mask). + @"MISF[10]": u1, + /// (12/16 of MISF) masked interrupt(N) semaphore n status bit after enable (mask). + @"MISF[11]": u1, + /// (13/16 of MISF) masked interrupt(N) semaphore n status bit after enable (mask). + @"MISF[12]": u1, + /// (14/16 of MISF) masked interrupt(N) semaphore n status bit after enable (mask). + @"MISF[13]": u1, + /// (15/16 of MISF) masked interrupt(N) semaphore n status bit after enable (mask). + @"MISF[14]": u1, + /// (16/16 of MISF) masked interrupt(N) semaphore n status bit after enable (mask). + @"MISF[15]": u1, + padding: u16, }), reserved320: [48]u8, /// HSEM Clear register. @@ -344921,9 +354742,14 @@ pub const types = struct { }), /// I3C receive data word register. DWR: mmio.Mmio(packed struct(u32) { - /// 8-bit received data (earliest byte on I3C bus). - DB: u8, - padding: u24, + /// (1/4 of DB) 8-bit received data (earliest byte on I3C bus). + @"DB[0]": u8, + /// (2/4 of DB) 8-bit received data (earliest byte on I3C bus). + @"DB[1]": u8, + /// (3/4 of DB) 8-bit received data (earliest byte on I3C bus). + @"DB[2]": u8, + /// (4/4 of DB) 8-bit received data (earliest byte on I3C bus). + @"DB[3]": u8, }), }; @@ -344998,9 +354824,14 @@ pub const types = struct { reserved32: [4]u8, /// I3C IBI payload data register. IBIDR: mmio.Mmio(packed struct(u32) { - /// 8-bit IBI payload data (earliest byte on I3C bus, i.e. MDB[7:0] mandatory data byte). - IBIDB: u8, - padding: u24, + /// (1/4 of IBIDB) 8-bit IBI payload data (earliest byte on I3C bus, i.e. MDB[7:0] mandatory data byte). + @"IBIDB[0]": u8, + /// (2/4 of IBIDB) 8-bit IBI payload data (earliest byte on I3C bus, i.e. MDB[7:0] mandatory data byte). + @"IBIDB[1]": u8, + /// (3/4 of IBIDB) 8-bit IBI payload data (earliest byte on I3C bus, i.e. MDB[7:0] mandatory data byte). + @"IBIDB[2]": u8, + /// (4/4 of IBIDB) 8-bit IBI payload data (earliest byte on I3C bus, i.e. MDB[7:0] mandatory data byte). + @"IBIDB[3]": u8, }), /// I3C target transmit configuration register. TGTTDR: mmio.Mmio(packed struct(u32) { @@ -345680,27 +355511,77 @@ pub const types = struct { }), /// Mask register CPUx MR: mmio.Mmio(packed struct(u32) { - /// processor x Receive channel y occupied interrupt enable - CHOM: u1, - reserved16: u15, - /// processor x Transmit channel y free interrupt mask - CHFM: u1, - padding: u15, + /// (1/6 of CHOM) processor x Receive channel y occupied interrupt enable + @"CHOM[0]": u1, + /// (2/6 of CHOM) processor x Receive channel y occupied interrupt enable + @"CHOM[1]": u1, + /// (3/6 of CHOM) processor x Receive channel y occupied interrupt enable + @"CHOM[2]": u1, + /// (4/6 of CHOM) processor x Receive channel y occupied interrupt enable + @"CHOM[3]": u1, + /// (5/6 of CHOM) processor x Receive channel y occupied interrupt enable + @"CHOM[4]": u1, + /// (6/6 of CHOM) processor x Receive channel y occupied interrupt enable + @"CHOM[5]": u1, + reserved16: u10, + /// (1/6 of CHFM) processor x Transmit channel y free interrupt mask + @"CHFM[0]": u1, + /// (2/6 of CHFM) processor x Transmit channel y free interrupt mask + @"CHFM[1]": u1, + /// (3/6 of CHFM) processor x Transmit channel y free interrupt mask + @"CHFM[2]": u1, + /// (4/6 of CHFM) processor x Transmit channel y free interrupt mask + @"CHFM[3]": u1, + /// (5/6 of CHFM) processor x Transmit channel y free interrupt mask + @"CHFM[4]": u1, + /// (6/6 of CHFM) processor x Transmit channel y free interrupt mask + @"CHFM[5]": u1, + padding: u10, }), /// Status Set or Clear register CPUx SCR: mmio.Mmio(packed struct(u32) { - /// processor x Receive channel y status clear - CHC: u1, - reserved16: u15, - /// processor x Transmit channel y status set - CHS: u1, - padding: u15, + /// (1/6 of CHC) processor x Receive channel y status clear + @"CHC[0]": u1, + /// (2/6 of CHC) processor x Receive channel y status clear + @"CHC[1]": u1, + /// (3/6 of CHC) processor x Receive channel y status clear + @"CHC[2]": u1, + /// (4/6 of CHC) processor x Receive channel y status clear + @"CHC[3]": u1, + /// (5/6 of CHC) processor x Receive channel y status clear + @"CHC[4]": u1, + /// (6/6 of CHC) processor x Receive channel y status clear + @"CHC[5]": u1, + reserved16: u10, + /// (1/6 of CHS) processor x Transmit channel y status set + @"CHS[0]": u1, + /// (2/6 of CHS) processor x Transmit channel y status set + @"CHS[1]": u1, + /// (3/6 of CHS) processor x Transmit channel y status set + @"CHS[2]": u1, + /// (4/6 of CHS) processor x Transmit channel y status set + @"CHS[3]": u1, + /// (5/6 of CHS) processor x Transmit channel y status set + @"CHS[4]": u1, + /// (6/6 of CHS) processor x Transmit channel y status set + @"CHS[5]": u1, + padding: u10, }), /// CPUx to CPUy status register SR: mmio.Mmio(packed struct(u32) { - /// processor x transmit to process y Receive channel z status flag - CHF: u1, - padding: u31, + /// (1/6 of CHF) processor x transmit to process y Receive channel z status flag + @"CHF[0]": u1, + /// (2/6 of CHF) processor x transmit to process y Receive channel z status flag + @"CHF[1]": u1, + /// (3/6 of CHF) processor x transmit to process y Receive channel z status flag + @"CHF[2]": u1, + /// (4/6 of CHF) processor x transmit to process y Receive channel z status flag + @"CHF[3]": u1, + /// (5/6 of CHF) processor x transmit to process y Receive channel z status flag + @"CHF[4]": u1, + /// (6/6 of CHF) processor x transmit to process y Receive channel z status flag + @"CHF[5]": u1, + padding: u26, }), }; }; @@ -349137,33 +359018,183 @@ pub const types = struct { pub const LPDMA = extern struct { /// LPDMA secure configuration register SECCFGR: mmio.Mmio(packed struct(u32) { - /// SEC0 - SEC: u1, - padding: u31, + /// (1/16 of SEC) SEC0 + @"SEC[0]": u1, + /// (2/16 of SEC) SEC0 + @"SEC[1]": u1, + /// (3/16 of SEC) SEC0 + @"SEC[2]": u1, + /// (4/16 of SEC) SEC0 + @"SEC[3]": u1, + /// (5/16 of SEC) SEC0 + @"SEC[4]": u1, + /// (6/16 of SEC) SEC0 + @"SEC[5]": u1, + /// (7/16 of SEC) SEC0 + @"SEC[6]": u1, + /// (8/16 of SEC) SEC0 + @"SEC[7]": u1, + /// (9/16 of SEC) SEC0 + @"SEC[8]": u1, + /// (10/16 of SEC) SEC0 + @"SEC[9]": u1, + /// (11/16 of SEC) SEC0 + @"SEC[10]": u1, + /// (12/16 of SEC) SEC0 + @"SEC[11]": u1, + /// (13/16 of SEC) SEC0 + @"SEC[12]": u1, + /// (14/16 of SEC) SEC0 + @"SEC[13]": u1, + /// (15/16 of SEC) SEC0 + @"SEC[14]": u1, + /// (16/16 of SEC) SEC0 + @"SEC[15]": u1, + padding: u16, }), /// LPDMA privileged configuration register PRIVCFGR: mmio.Mmio(packed struct(u32) { - /// PRIV0 - PRIV: u1, - padding: u31, + /// (1/16 of PRIV) PRIV0 + @"PRIV[0]": u1, + /// (2/16 of PRIV) PRIV0 + @"PRIV[1]": u1, + /// (3/16 of PRIV) PRIV0 + @"PRIV[2]": u1, + /// (4/16 of PRIV) PRIV0 + @"PRIV[3]": u1, + /// (5/16 of PRIV) PRIV0 + @"PRIV[4]": u1, + /// (6/16 of PRIV) PRIV0 + @"PRIV[5]": u1, + /// (7/16 of PRIV) PRIV0 + @"PRIV[6]": u1, + /// (8/16 of PRIV) PRIV0 + @"PRIV[7]": u1, + /// (9/16 of PRIV) PRIV0 + @"PRIV[8]": u1, + /// (10/16 of PRIV) PRIV0 + @"PRIV[9]": u1, + /// (11/16 of PRIV) PRIV0 + @"PRIV[10]": u1, + /// (12/16 of PRIV) PRIV0 + @"PRIV[11]": u1, + /// (13/16 of PRIV) PRIV0 + @"PRIV[12]": u1, + /// (14/16 of PRIV) PRIV0 + @"PRIV[13]": u1, + /// (15/16 of PRIV) PRIV0 + @"PRIV[14]": u1, + /// (16/16 of PRIV) PRIV0 + @"PRIV[15]": u1, + padding: u16, }), /// LPDMA configuration lock register RCFGLOCKR: mmio.Mmio(packed struct(u32) { - /// LOCK0 - LOCK: u1, - padding: u31, + /// (1/16 of LOCK) LOCK0 + @"LOCK[0]": u1, + /// (2/16 of LOCK) LOCK0 + @"LOCK[1]": u1, + /// (3/16 of LOCK) LOCK0 + @"LOCK[2]": u1, + /// (4/16 of LOCK) LOCK0 + @"LOCK[3]": u1, + /// (5/16 of LOCK) LOCK0 + @"LOCK[4]": u1, + /// (6/16 of LOCK) LOCK0 + @"LOCK[5]": u1, + /// (7/16 of LOCK) LOCK0 + @"LOCK[6]": u1, + /// (8/16 of LOCK) LOCK0 + @"LOCK[7]": u1, + /// (9/16 of LOCK) LOCK0 + @"LOCK[8]": u1, + /// (10/16 of LOCK) LOCK0 + @"LOCK[9]": u1, + /// (11/16 of LOCK) LOCK0 + @"LOCK[10]": u1, + /// (12/16 of LOCK) LOCK0 + @"LOCK[11]": u1, + /// (13/16 of LOCK) LOCK0 + @"LOCK[12]": u1, + /// (14/16 of LOCK) LOCK0 + @"LOCK[13]": u1, + /// (15/16 of LOCK) LOCK0 + @"LOCK[14]": u1, + /// (16/16 of LOCK) LOCK0 + @"LOCK[15]": u1, + padding: u16, }), /// LPDMA non-secure masked interrupt status register MISR: mmio.Mmio(packed struct(u32) { - /// MIS0 - MIS: u1, - padding: u31, + /// (1/16 of MIS) MIS0 + @"MIS[0]": u1, + /// (2/16 of MIS) MIS0 + @"MIS[1]": u1, + /// (3/16 of MIS) MIS0 + @"MIS[2]": u1, + /// (4/16 of MIS) MIS0 + @"MIS[3]": u1, + /// (5/16 of MIS) MIS0 + @"MIS[4]": u1, + /// (6/16 of MIS) MIS0 + @"MIS[5]": u1, + /// (7/16 of MIS) MIS0 + @"MIS[6]": u1, + /// (8/16 of MIS) MIS0 + @"MIS[7]": u1, + /// (9/16 of MIS) MIS0 + @"MIS[8]": u1, + /// (10/16 of MIS) MIS0 + @"MIS[9]": u1, + /// (11/16 of MIS) MIS0 + @"MIS[10]": u1, + /// (12/16 of MIS) MIS0 + @"MIS[11]": u1, + /// (13/16 of MIS) MIS0 + @"MIS[12]": u1, + /// (14/16 of MIS) MIS0 + @"MIS[13]": u1, + /// (15/16 of MIS) MIS0 + @"MIS[14]": u1, + /// (16/16 of MIS) MIS0 + @"MIS[15]": u1, + padding: u16, }), /// LPDMA secure masked interrupt status register SMISR: mmio.Mmio(packed struct(u32) { - /// MIS0 - MIS: u1, - padding: u31, + /// (1/16 of MIS) MIS0 + @"MIS[0]": u1, + /// (2/16 of MIS) MIS0 + @"MIS[1]": u1, + /// (3/16 of MIS) MIS0 + @"MIS[2]": u1, + /// (4/16 of MIS) MIS0 + @"MIS[3]": u1, + /// (5/16 of MIS) MIS0 + @"MIS[4]": u1, + /// (6/16 of MIS) MIS0 + @"MIS[5]": u1, + /// (7/16 of MIS) MIS0 + @"MIS[6]": u1, + /// (8/16 of MIS) MIS0 + @"MIS[7]": u1, + /// (9/16 of MIS) MIS0 + @"MIS[8]": u1, + /// (10/16 of MIS) MIS0 + @"MIS[9]": u1, + /// (11/16 of MIS) MIS0 + @"MIS[10]": u1, + /// (12/16 of MIS) MIS0 + @"MIS[11]": u1, + /// (13/16 of MIS) MIS0 + @"MIS[12]": u1, + /// (14/16 of MIS) MIS0 + @"MIS[13]": u1, + /// (15/16 of MIS) MIS0 + @"MIS[14]": u1, + /// (16/16 of MIS) MIS0 + @"MIS[15]": u1, + padding: u16, }), reserved80: [60]u8, CH: u32, @@ -349228,14 +359259,14 @@ pub const types = struct { pub const LPTIM = extern struct { /// LPTIM interrupt and status register. ISR: mmio.Mmio(packed struct(u32) { - /// Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. - CCIF: u1, + /// (1/1 of CCIF) Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + @"CCIF[0]": u1, /// Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. ARRM: u1, /// External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. EXTTRIG: u1, - /// Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. - CMPOK: u1, + /// (1/1 of CMPOK) Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + @"CMPOK[0]": u1, /// Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. ARROK: u1, /// Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. @@ -349246,14 +359277,14 @@ pub const types = struct { }), /// LPTIM interrupt clear register. ICR: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. - CCCF: u1, + /// (1/1 of CCCF) Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + @"CCCF[0]": u1, /// Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. ARRMCF: u1, /// External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. EXTTRIGCF: u1, - /// Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. - CMPOKCF: u1, + /// (1/1 of CMPOKCF) Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + @"CMPOKCF[0]": u1, /// Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. ARROKCF: u1, /// Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. @@ -349264,14 +359295,14 @@ pub const types = struct { }), /// LPTIM interrupt enable register. IER: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 interrupt enable. - CCIE: u1, + /// (1/1 of CCIE) Capture/compare 1 interrupt enable. + @"CCIE[0]": u1, /// Autoreload match Interrupt Enable. ARRMIE: u1, /// External trigger valid edge Interrupt Enable. EXTTRIGIE: u1, - /// Compare register 1 update OK interrupt enable. - CMPOKIE: u1, + /// (1/1 of CMPOKIE) Compare register 1 update OK interrupt enable. + @"CMPOKIE[0]": u1, /// Autoreload register update OK Interrupt Enable. ARROKIE: u1, /// Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. @@ -349403,14 +359434,14 @@ pub const types = struct { pub const LPTIM = extern struct { /// LPTIM interrupt and status register. ISR: mmio.Mmio(packed struct(u32) { - /// Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. - CCIF: u1, + /// (1/1 of CCIF) Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + @"CCIF[0]": u1, /// Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. ARRM: u1, /// External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. EXTTRIG: u1, - /// Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. - CMPOK: u1, + /// (1/1 of CMPOK) Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + @"CMPOK[0]": u1, /// Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. ARROK: u1, /// Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. @@ -349421,14 +359452,14 @@ pub const types = struct { }), /// LPTIM interrupt clear register. ICR: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. - CCCF: u1, + /// (1/1 of CCCF) Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + @"CCCF[0]": u1, /// Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. ARRMCF: u1, /// External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. EXTTRIGCF: u1, - /// Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. - CMPOKCF: u1, + /// (1/1 of CMPOKCF) Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + @"CMPOKCF[0]": u1, /// Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. ARROKCF: u1, /// Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. @@ -349439,14 +359470,14 @@ pub const types = struct { }), /// LPTIM interrupt enable register. IER: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 interrupt enable. - CCIE: u1, + /// (1/1 of CCIE) Capture/compare 1 interrupt enable. + @"CCIE[0]": u1, /// Autoreload match Interrupt Enable. ARRMIE: u1, /// External trigger valid edge Interrupt Enable. EXTTRIGIE: u1, - /// Compare register 1 update OK interrupt enable. - CMPOKIE: u1, + /// (1/1 of CMPOKIE) Compare register 1 update OK interrupt enable. + @"CMPOKIE[0]": u1, /// Autoreload register update OK Interrupt Enable. ARROKIE: u1, /// Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. @@ -349580,14 +359611,14 @@ pub const types = struct { pub const LPTIM = extern struct { /// LPTIM interrupt and status register. ISR: mmio.Mmio(packed struct(u32) { - /// Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. - CCIF: u1, + /// (1/1 of CCIF) Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + @"CCIF[0]": u1, /// Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. ARRM: u1, /// External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. EXTTRIG: u1, - /// Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. - CMPOK: u1, + /// (1/1 of CMPOK) Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + @"CMPOK[0]": u1, /// Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. ARROK: u1, /// Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. @@ -349598,14 +359629,14 @@ pub const types = struct { }), /// LPTIM interrupt clear register. ICR: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. - CCCF: u1, + /// (1/1 of CCCF) Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + @"CCCF[0]": u1, /// Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. ARRMCF: u1, /// External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. EXTTRIGCF: u1, - /// Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. - CMPOKCF: u1, + /// (1/1 of CMPOKCF) Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + @"CMPOKCF[0]": u1, /// Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. ARROKCF: u1, /// Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. @@ -349616,14 +359647,14 @@ pub const types = struct { }), /// LPTIM interrupt enable register. IER: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 interrupt enable. - CCIE: u1, + /// (1/1 of CCIE) Capture/compare 1 interrupt enable. + @"CCIE[0]": u1, /// Autoreload match Interrupt Enable. ARRMIE: u1, /// External trigger valid edge Interrupt Enable. EXTTRIGIE: u1, - /// Compare register 1 update OK interrupt enable. - CMPOKIE: u1, + /// (1/1 of CMPOKIE) Compare register 1 update OK interrupt enable. + @"CMPOKIE[0]": u1, /// Autoreload register update OK Interrupt Enable. ARROKIE: u1, /// Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. @@ -349761,14 +359792,14 @@ pub const types = struct { pub const LPTIM = extern struct { /// LPTIM interrupt and status register. ISR: mmio.Mmio(packed struct(u32) { - /// Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. - CCIF: u1, + /// (1/1 of CCIF) Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + @"CCIF[0]": u1, /// Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. ARRM: u1, /// External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. EXTTRIG: u1, - /// Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. - CMPOK: u1, + /// (1/1 of CMPOK) Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + @"CMPOK[0]": u1, /// Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. ARROK: u1, /// Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. @@ -349779,14 +359810,14 @@ pub const types = struct { }), /// LPTIM interrupt clear register. ICR: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. - CCCF: u1, + /// (1/1 of CCCF) Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + @"CCCF[0]": u1, /// Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. ARRMCF: u1, /// External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. EXTTRIGCF: u1, - /// Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. - CMPOKCF: u1, + /// (1/1 of CMPOKCF) Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + @"CMPOKCF[0]": u1, /// Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. ARROKCF: u1, /// Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. @@ -349797,14 +359828,14 @@ pub const types = struct { }), /// LPTIM interrupt enable register. IER: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 interrupt enable. - CCIE: u1, + /// (1/1 of CCIE) Capture/compare 1 interrupt enable. + @"CCIE[0]": u1, /// Autoreload match Interrupt Enable. ARRMIE: u1, /// External trigger valid edge Interrupt Enable. EXTTRIGIE: u1, - /// Compare register 1 update OK interrupt enable. - CMPOKIE: u1, + /// (1/1 of CMPOKIE) Compare register 1 update OK interrupt enable. + @"CMPOKIE[0]": u1, /// Autoreload register update OK Interrupt Enable. ARROKIE: u1, /// Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. @@ -349924,14 +359955,14 @@ pub const types = struct { pub const LPTIM = extern struct { /// LPTIM interrupt and status register. ISR: mmio.Mmio(packed struct(u32) { - /// Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. - CCIF: u1, + /// (1/1 of CCIF) Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + @"CCIF[0]": u1, /// Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. ARRM: u1, /// External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. EXTTRIG: u1, - /// Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. - CMPOK: u1, + /// (1/1 of CMPOK) Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + @"CMPOK[0]": u1, /// Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. ARROK: u1, /// Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. @@ -349942,14 +359973,14 @@ pub const types = struct { }), /// LPTIM interrupt clear register. ICR: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. - CCCF: u1, + /// (1/1 of CCCF) Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + @"CCCF[0]": u1, /// Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. ARRMCF: u1, /// External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. EXTTRIGCF: u1, - /// Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. - CMPOKCF: u1, + /// (1/1 of CMPOKCF) Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + @"CMPOKCF[0]": u1, /// Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. ARROKCF: u1, /// Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. @@ -349960,14 +359991,14 @@ pub const types = struct { }), /// LPTIM interrupt enable register. IER: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 interrupt enable. - CCIE: u1, + /// (1/1 of CCIE) Capture/compare 1 interrupt enable. + @"CCIE[0]": u1, /// Autoreload match Interrupt Enable. ARRMIE: u1, /// External trigger valid edge Interrupt Enable. EXTTRIGIE: u1, - /// Compare register 1 update OK interrupt enable. - CMPOKIE: u1, + /// (1/1 of CMPOKIE) Compare register 1 update OK interrupt enable. + @"CMPOKIE[0]": u1, /// Autoreload register update OK Interrupt Enable. ARROKIE: u1, /// Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. @@ -350045,9 +360076,12 @@ pub const types = struct { reserved36: [4]u8, /// LPTIM configuration register 2. CFGR2: mmio.Mmio(packed struct(u32) { - /// LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to. - INSEL: u2, - padding: u30, + /// (1/2 of INSEL) LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to. + @"INSEL[0]": u2, + reserved4: u2, + /// (2/2 of INSEL) LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to. + @"INSEL[1]": u2, + padding: u26, }), }; }; @@ -350110,14 +360144,14 @@ pub const types = struct { pub const LPTIM = extern struct { /// LPTIM interrupt and status register. ISR: mmio.Mmio(packed struct(u32) { - /// Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. - CCIF: u1, + /// (1/1 of CCIF) Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + @"CCIF[0]": u1, /// Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. ARRM: u1, /// External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. EXTTRIG: u1, - /// Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. - CMPOK: u1, + /// (1/1 of CMPOK) Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + @"CMPOK[0]": u1, /// Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. ARROK: u1, /// Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. @@ -350132,14 +360166,14 @@ pub const types = struct { }), /// LPTIM interrupt clear register. ICR: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. - CCCF: u1, + /// (1/1 of CCCF) Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + @"CCCF[0]": u1, /// Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. ARRMCF: u1, /// External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. EXTTRIGCF: u1, - /// Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. - CMPOKCF: u1, + /// (1/1 of CMPOKCF) Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + @"CMPOKCF[0]": u1, /// Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. ARROKCF: u1, /// Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. @@ -350154,14 +360188,14 @@ pub const types = struct { }), /// LPTIM interrupt enable register. IER: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 interrupt enable. - CCIE: u1, + /// (1/1 of CCIE) Capture/compare 1 interrupt enable. + @"CCIE[0]": u1, /// Autoreload match Interrupt Enable. ARRMIE: u1, /// External trigger valid edge Interrupt Enable. EXTTRIGIE: u1, - /// Compare register 1 update OK interrupt enable. - CMPOKIE: u1, + /// (1/1 of CMPOKIE) Compare register 1 update OK interrupt enable. + @"CMPOKIE[0]": u1, /// Autoreload register update OK Interrupt Enable. ARROKIE: u1, /// Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. @@ -350330,42 +360364,69 @@ pub const types = struct { pub const LPTIM = extern struct { /// LPTIM interrupt and status register. ISR: mmio.Mmio(packed struct(u32) { - /// Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. - CCIF: u1, + /// (1/2 of CCIF) Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + @"CCIF[0]": u1, reserved3: u2, - /// Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. - CMPOK: u1, - reserved12: u8, - /// Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. - CCOF: u1, - padding: u19, + /// (1/2 of CMPOK) Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + @"CMPOK[0]": u1, + reserved9: u5, + /// (2/2 of CCIF) Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + @"CCIF[1]": u1, + reserved12: u2, + /// (1/2 of CCOF) Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + @"CCOF[0]": u1, + /// (2/2 of CCOF) Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + @"CCOF[1]": u1, + reserved19: u5, + /// (2/2 of CMPOK) Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + @"CMPOK[1]": u1, + padding: u12, }), /// LPTIM interrupt clear register. ICR: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. - CCCF: u1, + /// (1/2 of CCCF) Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + @"CCCF[0]": u1, reserved3: u2, - /// Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. - CMPOKCF: u1, - reserved12: u8, - /// Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. - CCOCF: u1, - padding: u19, + /// (1/2 of CMPOKCF) Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + @"CMPOKCF[0]": u1, + reserved9: u5, + /// (2/2 of CCCF) Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + @"CCCF[1]": u1, + reserved12: u2, + /// (1/2 of CCOCF) Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + @"CCOCF[0]": u1, + /// (2/2 of CCOCF) Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + @"CCOCF[1]": u1, + reserved19: u5, + /// (2/2 of CMPOKCF) Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + @"CMPOKCF[1]": u1, + padding: u12, }), /// LPTIM interrupt enable register. DIER: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 interrupt enable. - CCIE: u1, + /// (1/2 of CCIE) Capture/compare 1 interrupt enable. + @"CCIE[0]": u1, reserved3: u2, - /// Compare register 1 update OK interrupt enable. - CMPOKIE: u1, - reserved12: u8, - /// Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. - CCOIE: u1, - reserved16: u3, - /// Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. - CCDE: u1, - padding: u15, + /// (1/2 of CMPOKIE) Compare register 1 update OK interrupt enable. + @"CMPOKIE[0]": u1, + reserved9: u5, + /// (2/2 of CCIE) Capture/compare 1 interrupt enable. + @"CCIE[1]": u1, + reserved12: u2, + /// (1/2 of CCOIE) Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + @"CCOIE[0]": u1, + /// (2/2 of CCOIE) Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + @"CCOIE[1]": u1, + reserved16: u2, + /// (1/2 of CCDE) Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + @"CCDE[0]": u1, + reserved19: u2, + /// (2/2 of CMPOKIE) Compare register 1 update OK interrupt enable. + @"CMPOKIE[1]": u1, + reserved25: u5, + /// (2/2 of CCDE) Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + @"CCDE[1]": u1, + padding: u6, }), reserved20: [8]u8, /// LPTIM compare register 1. @@ -350377,19 +360438,32 @@ pub const types = struct { reserved44: [20]u8, /// LPTIM capture/compare mode register 1. CCMR: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 selection This bitfield defines the direction of the channel input (capture) or output mode. - CCSEL: CCSEL, - /// Capture/compare 1 output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM_CCR1) or not. - CCE: u1, - /// Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations. - CCP_Input: CCP_Input, + /// (1/2 of CCSEL) Capture/compare 1 selection This bitfield defines the direction of the channel input (capture) or output mode. + @"CCSEL[0]": CCSEL, + /// (1/2 of CCE) Capture/compare 1 output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM_CCR1) or not. + @"CCE[0]": u1, + /// (1/2 of CCP_Input) Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations. + @"CCP_Input[0]": CCP_Input, reserved8: u4, - /// Input capture 1 prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). - ICPSC: Filter, + /// (1/2 of ICPSC) Input capture 1 prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). + @"ICPSC[0]": Filter, reserved12: u2, - /// Input capture 1 filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. - ICF: Filter, - padding: u18, + /// (1/2 of ICF) Input capture 1 filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + @"ICF[0]": Filter, + reserved16: u2, + /// (2/2 of CCSEL) Capture/compare 1 selection This bitfield defines the direction of the channel input (capture) or output mode. + @"CCSEL[1]": CCSEL, + /// (2/2 of CCE) Capture/compare 1 output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM_CCR1) or not. + @"CCE[1]": u1, + /// (2/2 of CCP_Input) Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations. + @"CCP_Input[1]": CCP_Input, + reserved24: u4, + /// (2/2 of ICPSC) Input capture 1 prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). + @"ICPSC[1]": Filter, + reserved28: u2, + /// (2/2 of ICF) Input capture 1 filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + @"ICF[1]": Filter, + padding: u2, }), }; @@ -350397,14 +360471,14 @@ pub const types = struct { pub const LPTIM_BASIC = extern struct { /// LPTIM interrupt and status register. ISR: mmio.Mmio(packed struct(u32) { - /// Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. - CCIF: u1, + /// (1/1 of CCIF) Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + @"CCIF[0]": u1, /// Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. ARRM: u1, /// External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. EXTTRIG: u1, - /// Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. - CMPOK: u1, + /// (1/1 of CMPOK) Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + @"CMPOK[0]": u1, /// Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. ARROK: u1, /// Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. @@ -350422,14 +360496,14 @@ pub const types = struct { }), /// LPTIM interrupt clear register. ICR: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. - CCCF: u1, + /// (1/1 of CCCF) Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + @"CCCF[0]": u1, /// Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. ARRMCF: u1, /// External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. EXTTRIGCF: u1, - /// Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. - CMPOKCF: u1, + /// (1/1 of CMPOKCF) Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + @"CMPOKCF[0]": u1, /// Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. ARROKCF: u1, /// Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. @@ -350447,14 +360521,14 @@ pub const types = struct { }), /// LPTIM interrupt enable register. DIER: mmio.Mmio(packed struct(u32) { - /// Capture/compare 1 interrupt enable. - CCIE: u1, + /// (1/1 of CCIE) Capture/compare 1 interrupt enable. + @"CCIE[0]": u1, /// Autoreload match Interrupt Enable. ARRMIE: u1, /// External trigger valid edge Interrupt Enable. EXTTRIGIE: u1, - /// Compare register 1 update OK interrupt enable. - CMPOKIE: u1, + /// (1/1 of CMPOKIE) Compare register 1 update OK interrupt enable. + @"CMPOKIE[0]": u1, /// Autoreload register update OK Interrupt Enable. ARROKIE: u1, /// Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to. @@ -350536,12 +360610,18 @@ pub const types = struct { reserved36: [4]u8, /// LPTIM configuration register 2. CFGR2: mmio.Mmio(packed struct(u32) { - /// LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to. - INSEL: u2, - reserved16: u14, - /// LPTIM input capture 1 selection The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture 1 to one of the available inputs. For connection details refer to. - ICSEL: u2, - padding: u14, + /// (1/2 of INSEL) LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to. + @"INSEL[0]": u2, + reserved4: u2, + /// (2/2 of INSEL) LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to. + @"INSEL[1]": u2, + reserved16: u10, + /// (1/2 of ICSEL) LPTIM input capture 1 selection The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture 1 to one of the available inputs. For connection details refer to. + @"ICSEL[0]": u2, + reserved20: u2, + /// (2/2 of ICSEL) LPTIM input capture 1 selection The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture 1 to one of the available inputs. For connection details refer to. + @"ICSEL[1]": u2, + padding: u10, }), /// LPTIM repetition register. RCR: mmio.Mmio(packed struct(u32) { @@ -350642,9 +360722,15 @@ pub const types = struct { /// Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. REPOK: u1, reserved12: u3, - /// Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. - CCOF: u1, - reserved24: u11, + /// (1/4 of CCOF) Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + @"CCOF[0]": u1, + /// (2/4 of CCOF) Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + @"CCOF[1]": u1, + /// (3/4 of CCOF) Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + @"CCOF[2]": u1, + /// (4/4 of CCOF) Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + @"CCOF[3]": u1, + reserved24: u8, /// Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. DIEROK: u1, padding: u7, @@ -350670,9 +360756,15 @@ pub const types = struct { /// Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. REPOKCF: u1, reserved12: u3, - /// Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. - CCOCF: u1, - reserved24: u11, + /// (1/4 of CCOCF) Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + @"CCOCF[0]": u1, + /// (2/4 of CCOCF) Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + @"CCOCF[1]": u1, + /// (3/4 of CCOCF) Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + @"CCOCF[2]": u1, + /// (4/4 of CCOCF) Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + @"CCOCF[3]": u1, + reserved24: u8, /// Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. DIEROKCF: u1, padding: u7, @@ -350698,9 +360790,14 @@ pub const types = struct { /// Repetition register update OK interrupt Enable. REPOKIE: u1, reserved12: u3, - /// Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. - CCOIE: u1, - reserved16: u3, + /// (1/4 of CCOIE) Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + @"CCOIE[0]": u1, + /// (2/4 of CCOIE) Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + @"CCOIE[1]": u1, + /// (3/4 of CCOIE) Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + @"CCOIE[2]": u1, + /// (4/4 of CCOIE) Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. + @"CCOIE[3]": u1, /// Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to. CCDE: u1, padding: u15, @@ -350773,12 +360870,18 @@ pub const types = struct { reserved36: [4]u8, /// LPTIM configuration register 2. CFGR2: mmio.Mmio(packed struct(u32) { - /// LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to. - INSEL: u2, - reserved16: u14, - /// LPTIM input capture 1 selection The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture 1 to one of the available inputs. For connection details refer to. - ICSEL: u2, - padding: u14, + /// (1/2 of INSEL) LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to. + @"INSEL[0]": u2, + reserved4: u2, + /// (2/2 of INSEL) LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to. + @"INSEL[1]": u2, + reserved16: u10, + /// (1/2 of ICSEL) LPTIM input capture 1 selection The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture 1 to one of the available inputs. For connection details refer to. + @"ICSEL[0]": u2, + reserved20: u2, + /// (2/2 of ICSEL) LPTIM input capture 1 selection The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture 1 to one of the available inputs. For connection details refer to. + @"ICSEL[1]": u2, + padding: u10, }), /// LPTIM repetition register. RCR: mmio.Mmio(packed struct(u32) { @@ -350788,19 +360891,32 @@ pub const types = struct { }), /// LPTIM capture/compare mode register. CCMR: mmio.Mmio(packed struct(u32) { - /// Capture/compare selection. This bitfield defines the direction of the channel input (capture) or output mode. - CCSEL: CCSEL, - /// Capture/compare output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM_CCR1) or not. - CCE: u1, - /// Capture/compare output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations. - CCP_Input: CCP_Input, + /// (1/2 of CCSEL) Capture/compare selection. This bitfield defines the direction of the channel input (capture) or output mode. + @"CCSEL[0]": CCSEL, + /// (1/2 of CCE) Capture/compare output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM_CCR1) or not. + @"CCE[0]": u1, + /// (1/2 of CCP_Input) Capture/compare output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations. + @"CCP_Input[0]": CCP_Input, reserved8: u4, - /// Input capture prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). - ICPSC: Filter, + /// (1/2 of ICPSC) Input capture prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). + @"ICPSC[0]": Filter, reserved12: u2, - /// Input capture filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. - ICF: Filter, - padding: u18, + /// (1/2 of ICF) Input capture filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + @"ICF[0]": Filter, + reserved16: u2, + /// (2/2 of CCSEL) Capture/compare selection. This bitfield defines the direction of the channel input (capture) or output mode. + @"CCSEL[1]": CCSEL, + /// (2/2 of CCE) Capture/compare output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM_CCR1) or not. + @"CCE[1]": u1, + /// (2/2 of CCP_Input) Capture/compare output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations. + @"CCP_Input[1]": CCP_Input, + reserved24: u4, + /// (2/2 of ICPSC) Input capture prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). + @"ICPSC[1]": Filter, + reserved28: u2, + /// (2/2 of ICF) Input capture filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + @"ICF[1]": Filter, + padding: u2, }), }; }; @@ -354253,9 +364369,14 @@ pub const types = struct { reserved40: [16]u8, /// PSSI data register. DR: mmio.Mmio(packed struct(u32) { - /// Data byte 0. - BYTE: u8, - padding: u24, + /// (1/4 of BYTE) Data byte 0. + @"BYTE[0]": u8, + /// (2/4 of BYTE) Data byte 0. + @"BYTE[1]": u8, + /// (3/4 of BYTE) Data byte 0. + @"BYTE[2]": u8, + /// (4/4 of BYTE) Data byte 0. + @"BYTE[3]": u8, }), }; }; @@ -354277,9 +364398,19 @@ pub const types = struct { reserved8: [4]u8, /// PWR control register 3 CR3: mmio.Mmio(packed struct(u32) { - /// Enable Wakeup pin - EWUP: u1, - reserved10: u9, + /// (1/6 of EWUP) Enable Wakeup pin + @"EWUP[0]": u1, + /// (2/6 of EWUP) Enable Wakeup pin + @"EWUP[1]": u1, + /// (3/6 of EWUP) Enable Wakeup pin + @"EWUP[2]": u1, + /// (4/6 of EWUP) Enable Wakeup pin + @"EWUP[3]": u1, + /// (5/6 of EWUP) Enable Wakeup pin + @"EWUP[4]": u1, + /// (6/6 of EWUP) Enable Wakeup pin + @"EWUP[5]": u1, + reserved10: u4, /// Apply pull-up and pull-down configuration This bit determines whether the I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied. APC: u1, reserved15: u4, @@ -354289,15 +364420,35 @@ pub const types = struct { }), /// PWR control register 4 CR4: mmio.Mmio(packed struct(u32) { - /// Wakeup pin WKUP1 polarity - WP: u1, - padding: u31, + /// (1/6 of WP) Wakeup pin WKUP1 polarity + @"WP[0]": u1, + /// (2/6 of WP) Wakeup pin WKUP1 polarity + @"WP[1]": u1, + /// (3/6 of WP) Wakeup pin WKUP1 polarity + @"WP[2]": u1, + /// (4/6 of WP) Wakeup pin WKUP1 polarity + @"WP[3]": u1, + /// (5/6 of WP) Wakeup pin WKUP1 polarity + @"WP[4]": u1, + /// (6/6 of WP) Wakeup pin WKUP1 polarity + @"WP[5]": u1, + padding: u26, }), /// PWR status register 1 SR1: mmio.Mmio(packed struct(u32) { - /// Wakeup flag - WUF: u1, - reserved8: u7, + /// (1/6 of WUF) Wakeup flag + @"WUF[0]": u1, + /// (2/6 of WUF) Wakeup flag + @"WUF[1]": u1, + /// (3/6 of WUF) Wakeup flag + @"WUF[2]": u1, + /// (4/6 of WUF) Wakeup flag + @"WUF[3]": u1, + /// (5/6 of WUF) Wakeup flag + @"WUF[4]": u1, + /// (6/6 of WUF) Wakeup flag + @"WUF[5]": u1, + reserved8: u2, /// Standby/Shutdown flag This bit is set by hardware when the device enters Standby or Shutdown mode and is cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset. SBF: u1, reserved15: u6, @@ -354314,9 +364465,19 @@ pub const types = struct { }), /// PWR status clear register SCR: mmio.Mmio(packed struct(u32) { - /// Clear Wakeup flag - CWUF: u1, - reserved8: u7, + /// (1/6 of CWUF) Clear Wakeup flag + @"CWUF[0]": u1, + /// (2/6 of CWUF) Clear Wakeup flag + @"CWUF[1]": u1, + /// (3/6 of CWUF) Clear Wakeup flag + @"CWUF[2]": u1, + /// (4/6 of CWUF) Clear Wakeup flag + @"CWUF[3]": u1, + /// (5/6 of CWUF) Clear Wakeup flag + @"CWUF[4]": u1, + /// (6/6 of CWUF) Clear Wakeup flag + @"CWUF[5]": u1, + reserved8: u2, /// Clear standby flag Setting this bit clears the SBF flag in the PWR_SR1 register. CSBF: u1, padding: u23, @@ -354324,15 +364485,75 @@ pub const types = struct { reserved32: [4]u8, /// PWR Port pull-up control register PUCR: mmio.Mmio(packed struct(u32) { - /// Port pull bit y (y=0..15) - P: u1, - padding: u31, + /// (1/16 of P) Port pull bit y (y=0..15) + @"P[0]": u1, + /// (2/16 of P) Port pull bit y (y=0..15) + @"P[1]": u1, + /// (3/16 of P) Port pull bit y (y=0..15) + @"P[2]": u1, + /// (4/16 of P) Port pull bit y (y=0..15) + @"P[3]": u1, + /// (5/16 of P) Port pull bit y (y=0..15) + @"P[4]": u1, + /// (6/16 of P) Port pull bit y (y=0..15) + @"P[5]": u1, + /// (7/16 of P) Port pull bit y (y=0..15) + @"P[6]": u1, + /// (8/16 of P) Port pull bit y (y=0..15) + @"P[7]": u1, + /// (9/16 of P) Port pull bit y (y=0..15) + @"P[8]": u1, + /// (10/16 of P) Port pull bit y (y=0..15) + @"P[9]": u1, + /// (11/16 of P) Port pull bit y (y=0..15) + @"P[10]": u1, + /// (12/16 of P) Port pull bit y (y=0..15) + @"P[11]": u1, + /// (13/16 of P) Port pull bit y (y=0..15) + @"P[12]": u1, + /// (14/16 of P) Port pull bit y (y=0..15) + @"P[13]": u1, + /// (15/16 of P) Port pull bit y (y=0..15) + @"P[14]": u1, + /// (16/16 of P) Port pull bit y (y=0..15) + @"P[15]": u1, + padding: u16, }), /// PWR Port pull-down control register PDCR: mmio.Mmio(packed struct(u32) { - /// Port pull bit y (y=0..15) - P: u1, - padding: u31, + /// (1/16 of P) Port pull bit y (y=0..15) + @"P[0]": u1, + /// (2/16 of P) Port pull bit y (y=0..15) + @"P[1]": u1, + /// (3/16 of P) Port pull bit y (y=0..15) + @"P[2]": u1, + /// (4/16 of P) Port pull bit y (y=0..15) + @"P[3]": u1, + /// (5/16 of P) Port pull bit y (y=0..15) + @"P[4]": u1, + /// (6/16 of P) Port pull bit y (y=0..15) + @"P[5]": u1, + /// (7/16 of P) Port pull bit y (y=0..15) + @"P[6]": u1, + /// (8/16 of P) Port pull bit y (y=0..15) + @"P[7]": u1, + /// (9/16 of P) Port pull bit y (y=0..15) + @"P[8]": u1, + /// (10/16 of P) Port pull bit y (y=0..15) + @"P[9]": u1, + /// (11/16 of P) Port pull bit y (y=0..15) + @"P[10]": u1, + /// (12/16 of P) Port pull bit y (y=0..15) + @"P[11]": u1, + /// (13/16 of P) Port pull bit y (y=0..15) + @"P[12]": u1, + /// (14/16 of P) Port pull bit y (y=0..15) + @"P[13]": u1, + /// (15/16 of P) Port pull bit y (y=0..15) + @"P[14]": u1, + /// (16/16 of P) Port pull bit y (y=0..15) + @"P[15]": u1, + padding: u16, }), }; }; @@ -354376,9 +364597,23 @@ pub const types = struct { /// VREFINT reference voltage ready VREFINTRDY: u1, reserved8: u4, - /// Enable WKUP pin 1 - EWUP: u1, - padding: u23, + /// (1/8 of EWUP) Enable WKUP pin 1 + @"EWUP[0]": u1, + /// (2/8 of EWUP) Enable WKUP pin 1 + @"EWUP[1]": u1, + /// (3/8 of EWUP) Enable WKUP pin 1 + @"EWUP[2]": u1, + /// (4/8 of EWUP) Enable WKUP pin 1 + @"EWUP[3]": u1, + /// (5/8 of EWUP) Enable WKUP pin 1 + @"EWUP[4]": u1, + /// (6/8 of EWUP) Enable WKUP pin 1 + @"EWUP[5]": u1, + /// (7/8 of EWUP) Enable WKUP pin 1 + @"EWUP[6]": u1, + /// (8/8 of EWUP) Enable WKUP pin 1 + @"EWUP[7]": u1, + padding: u16, }), }; }; @@ -354415,9 +364650,23 @@ pub const types = struct { /// Standby flag SBF: u1, reserved8: u6, - /// Enable WKUP pin 1 - EWUP: u1, - padding: u23, + /// (1/8 of EWUP) Enable WKUP pin 1 + @"EWUP[0]": u1, + /// (2/8 of EWUP) Enable WKUP pin 1 + @"EWUP[1]": u1, + /// (3/8 of EWUP) Enable WKUP pin 1 + @"EWUP[2]": u1, + /// (4/8 of EWUP) Enable WKUP pin 1 + @"EWUP[3]": u1, + /// (5/8 of EWUP) Enable WKUP pin 1 + @"EWUP[4]": u1, + /// (6/8 of EWUP) Enable WKUP pin 1 + @"EWUP[5]": u1, + /// (7/8 of EWUP) Enable WKUP pin 1 + @"EWUP[6]": u1, + /// (8/8 of EWUP) Enable WKUP pin 1 + @"EWUP[7]": u1, + padding: u16, }), }; }; @@ -354542,9 +364791,13 @@ pub const types = struct { PLS: u3, /// Disable backup domain write protection DBP: u1, - /// ENable SD1 ADC - ENSD: u1, - padding: u22, + /// (1/3 of ENSD) ENable SD1 ADC + @"ENSD[0]": u1, + /// (2/3 of ENSD) ENable SD1 ADC + @"ENSD[1]": u1, + /// (3/3 of ENSD) ENable SD1 ADC + @"ENSD[2]": u1, + padding: u20, }), /// power control/status register CSR: mmio.Mmio(packed struct(u32) { @@ -354557,9 +364810,11 @@ pub const types = struct { /// Internal voltage reference ready flag VREFINTRDYF: u1, reserved8: u4, - /// Enable WKUP1 pin - EWUP: u1, - padding: u23, + /// (1/2 of EWUP) Enable WKUP1 pin + @"EWUP[0]": u1, + /// (2/2 of EWUP) Enable WKUP1 pin + @"EWUP[1]": u1, + padding: u22, }), }; }; @@ -354738,21 +364993,61 @@ pub const types = struct { }), /// power control register CR2: mmio.Mmio(packed struct(u32) { - /// Clear Wakeup Pin flag for PA0 - CWUPF: u1, - reserved8: u7, - /// Wakeup pin polarity bit for PA0 - WUPP: u1, - padding: u23, + /// (1/6 of CWUPF) Clear Wakeup Pin flag for PA0 + @"CWUPF[0]": u1, + /// (2/6 of CWUPF) Clear Wakeup Pin flag for PA0 + @"CWUPF[1]": u1, + /// (3/6 of CWUPF) Clear Wakeup Pin flag for PA0 + @"CWUPF[2]": u1, + /// (4/6 of CWUPF) Clear Wakeup Pin flag for PA0 + @"CWUPF[3]": u1, + /// (5/6 of CWUPF) Clear Wakeup Pin flag for PA0 + @"CWUPF[4]": u1, + /// (6/6 of CWUPF) Clear Wakeup Pin flag for PA0 + @"CWUPF[5]": u1, + reserved8: u2, + /// (1/6 of WUPP) Wakeup pin polarity bit for PA0 + @"WUPP[0]": u1, + /// (2/6 of WUPP) Wakeup pin polarity bit for PA0 + @"WUPP[1]": u1, + /// (3/6 of WUPP) Wakeup pin polarity bit for PA0 + @"WUPP[2]": u1, + /// (4/6 of WUPP) Wakeup pin polarity bit for PA0 + @"WUPP[3]": u1, + /// (5/6 of WUPP) Wakeup pin polarity bit for PA0 + @"WUPP[4]": u1, + /// (6/6 of WUPP) Wakeup pin polarity bit for PA0 + @"WUPP[5]": u1, + padding: u18, }), /// power control/status register CSR2: mmio.Mmio(packed struct(u32) { - /// Wakeup Pin flag for PA0 - WUPF: u1, - reserved8: u7, - /// Enable Wakeup pin for PA0 - EWUP: u1, - padding: u23, + /// (1/6 of WUPF) Wakeup Pin flag for PA0 + @"WUPF[0]": u1, + /// (2/6 of WUPF) Wakeup Pin flag for PA0 + @"WUPF[1]": u1, + /// (3/6 of WUPF) Wakeup Pin flag for PA0 + @"WUPF[2]": u1, + /// (4/6 of WUPF) Wakeup Pin flag for PA0 + @"WUPF[3]": u1, + /// (5/6 of WUPF) Wakeup Pin flag for PA0 + @"WUPF[4]": u1, + /// (6/6 of WUPF) Wakeup Pin flag for PA0 + @"WUPF[5]": u1, + reserved8: u2, + /// (1/6 of EWUP) Enable Wakeup pin for PA0 + @"EWUP[0]": u1, + /// (2/6 of EWUP) Enable Wakeup pin for PA0 + @"EWUP[1]": u1, + /// (3/6 of EWUP) Enable Wakeup pin for PA0 + @"EWUP[2]": u1, + /// (4/6 of EWUP) Enable Wakeup pin for PA0 + @"EWUP[3]": u1, + /// (5/6 of EWUP) Enable Wakeup pin for PA0 + @"EWUP[4]": u1, + /// (6/6 of EWUP) Enable Wakeup pin for PA0 + @"EWUP[5]": u1, + padding: u18, }), }; }; @@ -354798,9 +365093,19 @@ pub const types = struct { }), /// Power control register 3 CR3: mmio.Mmio(packed struct(u32) { - /// Enable Wakeup pin - EWUP: u1, - reserved8: u7, + /// (1/6 of EWUP) Enable Wakeup pin + @"EWUP[0]": u1, + /// (2/6 of EWUP) Enable Wakeup pin + @"EWUP[1]": u1, + /// (3/6 of EWUP) Enable Wakeup pin + @"EWUP[2]": u1, + /// (4/6 of EWUP) Enable Wakeup pin + @"EWUP[3]": u1, + /// (5/6 of EWUP) Enable Wakeup pin + @"EWUP[4]": u1, + /// (6/6 of EWUP) Enable Wakeup pin + @"EWUP[5]": u1, + reserved8: u2, /// SRAM retention in Standby mode RRS: u1, /// Enable the periodical sampling mode for PDR detection @@ -354814,9 +365119,19 @@ pub const types = struct { }), /// Power control register 4 CR4: mmio.Mmio(packed struct(u32) { - /// Wakeup pin WKUP1 polarity - WP: u1, - reserved8: u7, + /// (1/6 of WP) Wakeup pin WKUP1 polarity + @"WP[0]": u1, + /// (2/6 of WP) Wakeup pin WKUP1 polarity + @"WP[1]": u1, + /// (3/6 of WP) Wakeup pin WKUP1 polarity + @"WP[2]": u1, + /// (4/6 of WP) Wakeup pin WKUP1 polarity + @"WP[3]": u1, + /// (5/6 of WP) Wakeup pin WKUP1 polarity + @"WP[4]": u1, + /// (6/6 of WP) Wakeup pin WKUP1 polarity + @"WP[5]": u1, + reserved8: u2, /// VBAT battery charging enable VBE: u1, /// VBAT battery charging resistor selection @@ -354825,9 +365140,19 @@ pub const types = struct { }), /// Power status register 1 SR1: mmio.Mmio(packed struct(u32) { - /// Wakeup flag - WUF: u1, - reserved8: u7, + /// (1/6 of WUF) Wakeup flag + @"WUF[0]": u1, + /// (2/6 of WUF) Wakeup flag + @"WUF[1]": u1, + /// (3/6 of WUF) Wakeup flag + @"WUF[2]": u1, + /// (4/6 of WUF) Wakeup flag + @"WUF[3]": u1, + /// (5/6 of WUF) Wakeup flag + @"WUF[4]": u1, + /// (6/6 of WUF) Wakeup flag + @"WUF[5]": u1, + reserved8: u2, /// Standby flag SBF: u1, reserved15: u6, @@ -354852,9 +365177,19 @@ pub const types = struct { }), /// Power status clear register SCR: mmio.Mmio(packed struct(u32) { - /// Clear Wakeup flag - CWUF: u1, - reserved8: u7, + /// (1/6 of CWUF) Clear Wakeup flag + @"CWUF[0]": u1, + /// (2/6 of CWUF) Clear Wakeup flag + @"CWUF[1]": u1, + /// (3/6 of CWUF) Clear Wakeup flag + @"CWUF[2]": u1, + /// (4/6 of CWUF) Clear Wakeup flag + @"CWUF[3]": u1, + /// (5/6 of CWUF) Clear Wakeup flag + @"CWUF[4]": u1, + /// (6/6 of CWUF) Clear Wakeup flag + @"CWUF[5]": u1, + reserved8: u2, /// Clear standby flag CSBF: u1, padding: u23, @@ -354862,15 +365197,75 @@ pub const types = struct { reserved32: [4]u8, /// Power Port pull-up control register PUCR: mmio.Mmio(packed struct(u32) { - /// Port pull bit y (y=0..15) - P: u1, - padding: u31, + /// (1/16 of P) Port pull bit y (y=0..15) + @"P[0]": u1, + /// (2/16 of P) Port pull bit y (y=0..15) + @"P[1]": u1, + /// (3/16 of P) Port pull bit y (y=0..15) + @"P[2]": u1, + /// (4/16 of P) Port pull bit y (y=0..15) + @"P[3]": u1, + /// (5/16 of P) Port pull bit y (y=0..15) + @"P[4]": u1, + /// (6/16 of P) Port pull bit y (y=0..15) + @"P[5]": u1, + /// (7/16 of P) Port pull bit y (y=0..15) + @"P[6]": u1, + /// (8/16 of P) Port pull bit y (y=0..15) + @"P[7]": u1, + /// (9/16 of P) Port pull bit y (y=0..15) + @"P[8]": u1, + /// (10/16 of P) Port pull bit y (y=0..15) + @"P[9]": u1, + /// (11/16 of P) Port pull bit y (y=0..15) + @"P[10]": u1, + /// (12/16 of P) Port pull bit y (y=0..15) + @"P[11]": u1, + /// (13/16 of P) Port pull bit y (y=0..15) + @"P[12]": u1, + /// (14/16 of P) Port pull bit y (y=0..15) + @"P[13]": u1, + /// (15/16 of P) Port pull bit y (y=0..15) + @"P[14]": u1, + /// (16/16 of P) Port pull bit y (y=0..15) + @"P[15]": u1, + padding: u16, }), /// Power Port pull-down control register PDCR: mmio.Mmio(packed struct(u32) { - /// Port pull bit y (y=0..15) - P: u1, - padding: u31, + /// (1/16 of P) Port pull bit y (y=0..15) + @"P[0]": u1, + /// (2/16 of P) Port pull bit y (y=0..15) + @"P[1]": u1, + /// (3/16 of P) Port pull bit y (y=0..15) + @"P[2]": u1, + /// (4/16 of P) Port pull bit y (y=0..15) + @"P[3]": u1, + /// (5/16 of P) Port pull bit y (y=0..15) + @"P[4]": u1, + /// (6/16 of P) Port pull bit y (y=0..15) + @"P[5]": u1, + /// (7/16 of P) Port pull bit y (y=0..15) + @"P[6]": u1, + /// (8/16 of P) Port pull bit y (y=0..15) + @"P[7]": u1, + /// (9/16 of P) Port pull bit y (y=0..15) + @"P[8]": u1, + /// (10/16 of P) Port pull bit y (y=0..15) + @"P[9]": u1, + /// (11/16 of P) Port pull bit y (y=0..15) + @"P[10]": u1, + /// (12/16 of P) Port pull bit y (y=0..15) + @"P[11]": u1, + /// (13/16 of P) Port pull bit y (y=0..15) + @"P[12]": u1, + /// (14/16 of P) Port pull bit y (y=0..15) + @"P[13]": u1, + /// (15/16 of P) Port pull bit y (y=0..15) + @"P[14]": u1, + /// (16/16 of P) Port pull bit y (y=0..15) + @"P[15]": u1, + padding: u16, }), }; }; @@ -355021,15 +365416,75 @@ pub const types = struct { reserved32: [4]u8, /// Power Port pull-up control register PUCR: mmio.Mmio(packed struct(u32) { - /// Port pull bit y (y=0..15) - P: u1, - padding: u31, + /// (1/16 of P) Port pull bit y (y=0..15) + @"P[0]": u1, + /// (2/16 of P) Port pull bit y (y=0..15) + @"P[1]": u1, + /// (3/16 of P) Port pull bit y (y=0..15) + @"P[2]": u1, + /// (4/16 of P) Port pull bit y (y=0..15) + @"P[3]": u1, + /// (5/16 of P) Port pull bit y (y=0..15) + @"P[4]": u1, + /// (6/16 of P) Port pull bit y (y=0..15) + @"P[5]": u1, + /// (7/16 of P) Port pull bit y (y=0..15) + @"P[6]": u1, + /// (8/16 of P) Port pull bit y (y=0..15) + @"P[7]": u1, + /// (9/16 of P) Port pull bit y (y=0..15) + @"P[8]": u1, + /// (10/16 of P) Port pull bit y (y=0..15) + @"P[9]": u1, + /// (11/16 of P) Port pull bit y (y=0..15) + @"P[10]": u1, + /// (12/16 of P) Port pull bit y (y=0..15) + @"P[11]": u1, + /// (13/16 of P) Port pull bit y (y=0..15) + @"P[12]": u1, + /// (14/16 of P) Port pull bit y (y=0..15) + @"P[13]": u1, + /// (15/16 of P) Port pull bit y (y=0..15) + @"P[14]": u1, + /// (16/16 of P) Port pull bit y (y=0..15) + @"P[15]": u1, + padding: u16, }), /// Power Port pull-down control register PDCR: mmio.Mmio(packed struct(u32) { - /// Port pull bit y (y=0..15) - P: u1, - padding: u31, + /// (1/16 of P) Port pull bit y (y=0..15) + @"P[0]": u1, + /// (2/16 of P) Port pull bit y (y=0..15) + @"P[1]": u1, + /// (3/16 of P) Port pull bit y (y=0..15) + @"P[2]": u1, + /// (4/16 of P) Port pull bit y (y=0..15) + @"P[3]": u1, + /// (5/16 of P) Port pull bit y (y=0..15) + @"P[4]": u1, + /// (6/16 of P) Port pull bit y (y=0..15) + @"P[5]": u1, + /// (7/16 of P) Port pull bit y (y=0..15) + @"P[6]": u1, + /// (8/16 of P) Port pull bit y (y=0..15) + @"P[7]": u1, + /// (9/16 of P) Port pull bit y (y=0..15) + @"P[8]": u1, + /// (10/16 of P) Port pull bit y (y=0..15) + @"P[9]": u1, + /// (11/16 of P) Port pull bit y (y=0..15) + @"P[10]": u1, + /// (12/16 of P) Port pull bit y (y=0..15) + @"P[11]": u1, + /// (13/16 of P) Port pull bit y (y=0..15) + @"P[12]": u1, + /// (14/16 of P) Port pull bit y (y=0..15) + @"P[13]": u1, + /// (15/16 of P) Port pull bit y (y=0..15) + @"P[14]": u1, + /// (16/16 of P) Port pull bit y (y=0..15) + @"P[15]": u1, + padding: u16, }), reserved128: [88]u8, /// Power control register 5 @@ -355295,27 +365750,94 @@ pub const types = struct { }), /// PWR wakeup status clear register. WUSCR: mmio.Mmio(packed struct(u32) { - /// clear wakeup pin flag for WUFx These bits are always read as 0. - CWUF: u1, - padding: u31, + /// (1/8 of CWUF) clear wakeup pin flag for WUFx These bits are always read as 0. + @"CWUF[0]": u1, + /// (2/8 of CWUF) clear wakeup pin flag for WUFx These bits are always read as 0. + @"CWUF[1]": u1, + /// (3/8 of CWUF) clear wakeup pin flag for WUFx These bits are always read as 0. + @"CWUF[2]": u1, + /// (4/8 of CWUF) clear wakeup pin flag for WUFx These bits are always read as 0. + @"CWUF[3]": u1, + /// (5/8 of CWUF) clear wakeup pin flag for WUFx These bits are always read as 0. + @"CWUF[4]": u1, + /// (6/8 of CWUF) clear wakeup pin flag for WUFx These bits are always read as 0. + @"CWUF[5]": u1, + /// (7/8 of CWUF) clear wakeup pin flag for WUFx These bits are always read as 0. + @"CWUF[6]": u1, + /// (8/8 of CWUF) clear wakeup pin flag for WUFx These bits are always read as 0. + @"CWUF[7]": u1, + padding: u24, }), /// PWR wakeup status register. WUSR: mmio.Mmio(packed struct(u32) { - /// wakeup pin WUFx flag This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register. - WUF: u1, - padding: u31, + /// (1/8 of WUF) wakeup pin WUFx flag This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register. + @"WUF[0]": u1, + /// (2/8 of WUF) wakeup pin WUFx flag This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register. + @"WUF[1]": u1, + /// (3/8 of WUF) wakeup pin WUFx flag This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register. + @"WUF[2]": u1, + /// (4/8 of WUF) wakeup pin WUFx flag This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register. + @"WUF[3]": u1, + /// (5/8 of WUF) wakeup pin WUFx flag This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register. + @"WUF[4]": u1, + /// (6/8 of WUF) wakeup pin WUFx flag This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register. + @"WUF[5]": u1, + /// (7/8 of WUF) wakeup pin WUFx flag This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register. + @"WUF[6]": u1, + /// (8/8 of WUF) wakeup pin WUFx flag This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register. + @"WUF[7]": u1, + padding: u24, }), /// PWR wakeup configuration register. WUCR: mmio.Mmio(packed struct(u32) { - /// enable wakeup pin WUPx These bits are set and cleared by software. Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge. - WUPEN: u1, - reserved8: u7, - /// wakeup pin polarity bit for WUPx These bits define the polarity used for event detection on WUPx external wakeup pin. - WUPP: WUPP, - reserved16: u7, - /// wakeup pin pull configuration for WKUPx These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode. - WUPPUPD: WUPPUPD, - padding: u14, + /// (1/8 of WUPEN) enable wakeup pin WUPx These bits are set and cleared by software. Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge. + @"WUPEN[0]": u1, + /// (2/8 of WUPEN) enable wakeup pin WUPx These bits are set and cleared by software. Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge. + @"WUPEN[1]": u1, + /// (3/8 of WUPEN) enable wakeup pin WUPx These bits are set and cleared by software. Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge. + @"WUPEN[2]": u1, + /// (4/8 of WUPEN) enable wakeup pin WUPx These bits are set and cleared by software. Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge. + @"WUPEN[3]": u1, + /// (5/8 of WUPEN) enable wakeup pin WUPx These bits are set and cleared by software. Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge. + @"WUPEN[4]": u1, + /// (6/8 of WUPEN) enable wakeup pin WUPx These bits are set and cleared by software. Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge. + @"WUPEN[5]": u1, + /// (7/8 of WUPEN) enable wakeup pin WUPx These bits are set and cleared by software. Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge. + @"WUPEN[6]": u1, + /// (8/8 of WUPEN) enable wakeup pin WUPx These bits are set and cleared by software. Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge. + @"WUPEN[7]": u1, + /// (1/8 of WUPP) wakeup pin polarity bit for WUPx These bits define the polarity used for event detection on WUPx external wakeup pin. + @"WUPP[0]": WUPP, + /// (2/8 of WUPP) wakeup pin polarity bit for WUPx These bits define the polarity used for event detection on WUPx external wakeup pin. + @"WUPP[1]": WUPP, + /// (3/8 of WUPP) wakeup pin polarity bit for WUPx These bits define the polarity used for event detection on WUPx external wakeup pin. + @"WUPP[2]": WUPP, + /// (4/8 of WUPP) wakeup pin polarity bit for WUPx These bits define the polarity used for event detection on WUPx external wakeup pin. + @"WUPP[3]": WUPP, + /// (5/8 of WUPP) wakeup pin polarity bit for WUPx These bits define the polarity used for event detection on WUPx external wakeup pin. + @"WUPP[4]": WUPP, + /// (6/8 of WUPP) wakeup pin polarity bit for WUPx These bits define the polarity used for event detection on WUPx external wakeup pin. + @"WUPP[5]": WUPP, + /// (7/8 of WUPP) wakeup pin polarity bit for WUPx These bits define the polarity used for event detection on WUPx external wakeup pin. + @"WUPP[6]": WUPP, + /// (8/8 of WUPP) wakeup pin polarity bit for WUPx These bits define the polarity used for event detection on WUPx external wakeup pin. + @"WUPP[7]": WUPP, + /// (1/8 of WUPPUPD) wakeup pin pull configuration for WKUPx These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode. + @"WUPPUPD[0]": WUPPUPD, + /// (2/8 of WUPPUPD) wakeup pin pull configuration for WKUPx These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode. + @"WUPPUPD[1]": WUPPUPD, + /// (3/8 of WUPPUPD) wakeup pin pull configuration for WKUPx These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode. + @"WUPPUPD[2]": WUPPUPD, + /// (4/8 of WUPPUPD) wakeup pin pull configuration for WKUPx These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode. + @"WUPPUPD[3]": WUPPUPD, + /// (5/8 of WUPPUPD) wakeup pin pull configuration for WKUPx These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode. + @"WUPPUPD[4]": WUPPUPD, + /// (6/8 of WUPPUPD) wakeup pin pull configuration for WKUPx These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode. + @"WUPPUPD[5]": WUPPUPD, + /// (7/8 of WUPPUPD) wakeup pin pull configuration for WKUPx These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode. + @"WUPPUPD[6]": WUPPUPD, + /// (8/8 of WUPPUPD) wakeup pin pull configuration for WKUPx These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode. + @"WUPPUPD[7]": WUPPUPD, }), reserved80: [4]u8, /// PWR I/O retention register. @@ -355330,9 +365852,23 @@ pub const types = struct { reserved256: [172]u8, /// PWR security configuration register. SECCFGR: mmio.Mmio(packed struct(u32) { - /// WUPx secure protection. - WUPSEC: u1, - reserved11: u10, + /// (1/8 of WUPSEC) WUPx secure protection. + @"WUPSEC[0]": u1, + /// (2/8 of WUPSEC) WUPx secure protection. + @"WUPSEC[1]": u1, + /// (3/8 of WUPSEC) WUPx secure protection. + @"WUPSEC[2]": u1, + /// (4/8 of WUPSEC) WUPx secure protection. + @"WUPSEC[3]": u1, + /// (5/8 of WUPSEC) WUPx secure protection. + @"WUPSEC[4]": u1, + /// (6/8 of WUPSEC) WUPx secure protection. + @"WUPSEC[5]": u1, + /// (7/8 of WUPSEC) WUPx secure protection. + @"WUPSEC[6]": u1, + /// (8/8 of WUPSEC) WUPx secure protection. + @"WUPSEC[7]": u1, + reserved11: u3, /// retention secure protection. RETSEC: u1, /// low-power modes secure protection. @@ -355583,27 +366119,67 @@ pub const types = struct { }), /// PWR wakeup status clear register. WUSCR: mmio.Mmio(packed struct(u32) { - /// clear wakeup pin flag for WUFx These bits are always read as 0. - CWUF: u1, - padding: u31, + /// (1/5 of CWUF) clear wakeup pin flag for WUFx These bits are always read as 0. + @"CWUF[0]": u1, + /// (2/5 of CWUF) clear wakeup pin flag for WUFx These bits are always read as 0. + @"CWUF[1]": u1, + /// (3/5 of CWUF) clear wakeup pin flag for WUFx These bits are always read as 0. + @"CWUF[2]": u1, + /// (4/5 of CWUF) clear wakeup pin flag for WUFx These bits are always read as 0. + @"CWUF[3]": u1, + /// (5/5 of CWUF) clear wakeup pin flag for WUFx These bits are always read as 0. + @"CWUF[4]": u1, + padding: u27, }), /// PWR wakeup status register. WUSR: mmio.Mmio(packed struct(u32) { - /// wakeup pin WUFx flag This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register. - WUF: u1, - padding: u31, + /// (1/5 of WUF) wakeup pin WUFx flag This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register. + @"WUF[0]": u1, + /// (2/5 of WUF) wakeup pin WUFx flag This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register. + @"WUF[1]": u1, + /// (3/5 of WUF) wakeup pin WUFx flag This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register. + @"WUF[2]": u1, + /// (4/5 of WUF) wakeup pin WUFx flag This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register. + @"WUF[3]": u1, + /// (5/5 of WUF) wakeup pin WUFx flag This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register. + @"WUF[4]": u1, + padding: u27, }), /// PWR wakeup configuration register. WUCR: mmio.Mmio(packed struct(u32) { - /// enable wakeup pin WUPx These bits are set and cleared by software. Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge. - WUPEN: u1, - reserved8: u7, - /// wakeup pin polarity bit for WUPx These bits define the polarity used for event detection on WUPx external wakeup pin. - WUPP: WUPP, - reserved16: u7, - /// wakeup pin pull configuration for WKUPx These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode. - WUPPUPD: WUPPUPD, - padding: u14, + /// (1/5 of WUPEN) enable wakeup pin WUPx These bits are set and cleared by software. Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge. + @"WUPEN[0]": u1, + /// (2/5 of WUPEN) enable wakeup pin WUPx These bits are set and cleared by software. Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge. + @"WUPEN[1]": u1, + /// (3/5 of WUPEN) enable wakeup pin WUPx These bits are set and cleared by software. Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge. + @"WUPEN[2]": u1, + /// (4/5 of WUPEN) enable wakeup pin WUPx These bits are set and cleared by software. Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge. + @"WUPEN[3]": u1, + /// (5/5 of WUPEN) enable wakeup pin WUPx These bits are set and cleared by software. Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge. + @"WUPEN[4]": u1, + reserved8: u3, + /// (1/5 of WUPP) wakeup pin polarity bit for WUPx These bits define the polarity used for event detection on WUPx external wakeup pin. + @"WUPP[0]": WUPP, + /// (2/5 of WUPP) wakeup pin polarity bit for WUPx These bits define the polarity used for event detection on WUPx external wakeup pin. + @"WUPP[1]": WUPP, + /// (3/5 of WUPP) wakeup pin polarity bit for WUPx These bits define the polarity used for event detection on WUPx external wakeup pin. + @"WUPP[2]": WUPP, + /// (4/5 of WUPP) wakeup pin polarity bit for WUPx These bits define the polarity used for event detection on WUPx external wakeup pin. + @"WUPP[3]": WUPP, + /// (5/5 of WUPP) wakeup pin polarity bit for WUPx These bits define the polarity used for event detection on WUPx external wakeup pin. + @"WUPP[4]": WUPP, + reserved16: u3, + /// (1/5 of WUPPUPD) wakeup pin pull configuration for WKUPx These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode. + @"WUPPUPD[0]": WUPPUPD, + /// (2/5 of WUPPUPD) wakeup pin pull configuration for WKUPx These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode. + @"WUPPUPD[1]": WUPPUPD, + /// (3/5 of WUPPUPD) wakeup pin pull configuration for WKUPx These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode. + @"WUPPUPD[2]": WUPPUPD, + /// (4/5 of WUPPUPD) wakeup pin pull configuration for WKUPx These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode. + @"WUPPUPD[3]": WUPPUPD, + /// (5/5 of WUPPUPD) wakeup pin pull configuration for WKUPx These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode. + @"WUPPUPD[4]": WUPPUPD, + padding: u6, }), reserved80: [4]u8, /// PWR I/O retention register. @@ -355782,21 +366358,61 @@ pub const types = struct { }), /// reset only by system reset, not reset by wakeup from Standby mode WKUPFR: mmio.Mmio(packed struct(u32) { - /// Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). - WKUPF: u1, - padding: u31, + /// (1/6 of WKUPF) Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + @"WKUPF[0]": u1, + /// (2/6 of WKUPF) Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + @"WKUPF[1]": u1, + /// (3/6 of WKUPF) Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + @"WKUPF[2]": u1, + /// (4/6 of WKUPF) Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + @"WKUPF[3]": u1, + /// (5/6 of WKUPF) Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + @"WKUPF[4]": u1, + /// (6/6 of WKUPF) Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + @"WKUPF[5]": u1, + padding: u26, }), /// Reset only by system reset, not reset by wakeup from Standby mode WKUPEPR: mmio.Mmio(packed struct(u32) { - /// Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. - WKUPEN: u1, - reserved8: u7, - /// Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. - WKUPP: u1, - reserved16: u7, - /// Wakeup pin pull configuration - WKUPPUPD: WKUPPUPD, - padding: u14, + /// (1/6 of WKUPEN) Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. + @"WKUPEN[0]": u1, + /// (2/6 of WKUPEN) Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. + @"WKUPEN[1]": u1, + /// (3/6 of WKUPEN) Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. + @"WKUPEN[2]": u1, + /// (4/6 of WKUPEN) Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. + @"WKUPEN[3]": u1, + /// (5/6 of WKUPEN) Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. + @"WKUPEN[4]": u1, + /// (6/6 of WKUPEN) Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. + @"WKUPEN[5]": u1, + reserved8: u2, + /// (1/6 of WKUPP) Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + @"WKUPP[0]": u1, + /// (2/6 of WKUPP) Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + @"WKUPP[1]": u1, + /// (3/6 of WKUPP) Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + @"WKUPP[2]": u1, + /// (4/6 of WKUPP) Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + @"WKUPP[3]": u1, + /// (5/6 of WKUPP) Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + @"WKUPP[4]": u1, + /// (6/6 of WKUPP) Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + @"WKUPP[5]": u1, + reserved16: u2, + /// (1/6 of WKUPPUPD) Wakeup pin pull configuration + @"WKUPPUPD[0]": WKUPPUPD, + /// (2/6 of WKUPPUPD) Wakeup pin pull configuration + @"WKUPPUPD[1]": WKUPPUPD, + /// (3/6 of WKUPPUPD) Wakeup pin pull configuration + @"WKUPPUPD[2]": WKUPPUPD, + /// (4/6 of WKUPPUPD) Wakeup pin pull configuration + @"WKUPPUPD[3]": WKUPPUPD, + /// (5/6 of WKUPPUPD) Wakeup pin pull configuration + @"WKUPPUPD[4]": WKUPPUPD, + /// (6/6 of WKUPPUPD) Wakeup pin pull configuration + @"WKUPPUPD[5]": WKUPPUPD, + padding: u4, }), }; }; @@ -355943,21 +366559,61 @@ pub const types = struct { }), /// reset only by system reset, not reset by wakeup from Standby mode WKUPFR: mmio.Mmio(packed struct(u32) { - /// Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). - WKUPF: u1, - padding: u31, + /// (1/6 of WKUPF) Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + @"WKUPF[0]": u1, + /// (2/6 of WKUPF) Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + @"WKUPF[1]": u1, + /// (3/6 of WKUPF) Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + @"WKUPF[2]": u1, + /// (4/6 of WKUPF) Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + @"WKUPF[3]": u1, + /// (5/6 of WKUPF) Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + @"WKUPF[4]": u1, + /// (6/6 of WKUPF) Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + @"WKUPF[5]": u1, + padding: u26, }), /// Reset only by system reset, not reset by wakeup from Standby mode WKUPEPR: mmio.Mmio(packed struct(u32) { - /// Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. - WKUPEN: u1, - reserved8: u7, - /// Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. - WKUPP: u1, - reserved16: u7, - /// Wakeup pin pull configuration - WKUPPUPD: WKUPPUPD, - padding: u14, + /// (1/6 of WKUPEN) Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. + @"WKUPEN[0]": u1, + /// (2/6 of WKUPEN) Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. + @"WKUPEN[1]": u1, + /// (3/6 of WKUPEN) Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. + @"WKUPEN[2]": u1, + /// (4/6 of WKUPEN) Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. + @"WKUPEN[3]": u1, + /// (5/6 of WKUPEN) Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. + @"WKUPEN[4]": u1, + /// (6/6 of WKUPEN) Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. + @"WKUPEN[5]": u1, + reserved8: u2, + /// (1/6 of WKUPP) Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + @"WKUPP[0]": u1, + /// (2/6 of WKUPP) Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + @"WKUPP[1]": u1, + /// (3/6 of WKUPP) Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + @"WKUPP[2]": u1, + /// (4/6 of WKUPP) Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + @"WKUPP[3]": u1, + /// (5/6 of WKUPP) Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + @"WKUPP[4]": u1, + /// (6/6 of WKUPP) Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + @"WKUPP[5]": u1, + reserved16: u2, + /// (1/6 of WKUPPUPD) Wakeup pin pull configuration + @"WKUPPUPD[0]": WKUPPUPD, + /// (2/6 of WKUPPUPD) Wakeup pin pull configuration + @"WKUPPUPD[1]": WKUPPUPD, + /// (3/6 of WKUPPUPD) Wakeup pin pull configuration + @"WKUPPUPD[2]": WKUPPUPD, + /// (4/6 of WKUPPUPD) Wakeup pin pull configuration + @"WKUPPUPD[3]": WKUPPUPD, + /// (5/6 of WKUPPUPD) Wakeup pin pull configuration + @"WKUPPUPD[4]": WKUPPUPD, + /// (6/6 of WKUPPUPD) Wakeup pin pull configuration + @"WKUPPUPD[5]": WKUPPUPD, + padding: u4, }), }; }; @@ -356118,21 +366774,61 @@ pub const types = struct { }), /// reset only by system reset, not reset by wakeup from Standby mode WKUPFR: mmio.Mmio(packed struct(u32) { - /// Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). - WKUPF: u1, - padding: u31, + /// (1/6 of WKUPF) Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + @"WKUPF[0]": u1, + /// (2/6 of WKUPF) Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + @"WKUPF[1]": u1, + /// (3/6 of WKUPF) Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + @"WKUPF[2]": u1, + /// (4/6 of WKUPF) Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + @"WKUPF[3]": u1, + /// (5/6 of WKUPF) Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + @"WKUPF[4]": u1, + /// (6/6 of WKUPF) Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + @"WKUPF[5]": u1, + padding: u26, }), /// Reset only by system reset, not reset by wakeup from Standby mode WKUPEPR: mmio.Mmio(packed struct(u32) { - /// Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. - WKUPEN: u1, - reserved8: u7, - /// Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. - WKUPP: u1, - reserved16: u7, - /// Wakeup pin pull configuration - WKUPPUPD: WKUPPUPD, - padding: u14, + /// (1/6 of WKUPEN) Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. + @"WKUPEN[0]": u1, + /// (2/6 of WKUPEN) Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. + @"WKUPEN[1]": u1, + /// (3/6 of WKUPEN) Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. + @"WKUPEN[2]": u1, + /// (4/6 of WKUPEN) Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. + @"WKUPEN[3]": u1, + /// (5/6 of WKUPEN) Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. + @"WKUPEN[4]": u1, + /// (6/6 of WKUPEN) Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. + @"WKUPEN[5]": u1, + reserved8: u2, + /// (1/6 of WKUPP) Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + @"WKUPP[0]": u1, + /// (2/6 of WKUPP) Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + @"WKUPP[1]": u1, + /// (3/6 of WKUPP) Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + @"WKUPP[2]": u1, + /// (4/6 of WKUPP) Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + @"WKUPP[3]": u1, + /// (5/6 of WKUPP) Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + @"WKUPP[4]": u1, + /// (6/6 of WKUPP) Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + @"WKUPP[5]": u1, + reserved16: u2, + /// (1/6 of WKUPPUPD) Wakeup pin pull configuration + @"WKUPPUPD[0]": WKUPPUPD, + /// (2/6 of WKUPPUPD) Wakeup pin pull configuration + @"WKUPPUPD[1]": WKUPPUPD, + /// (3/6 of WKUPPUPD) Wakeup pin pull configuration + @"WKUPPUPD[2]": WKUPPUPD, + /// (4/6 of WKUPPUPD) Wakeup pin pull configuration + @"WKUPPUPD[3]": WKUPPUPD, + /// (5/6 of WKUPPUPD) Wakeup pin pull configuration + @"WKUPPUPD[4]": WKUPPUPD, + /// (6/6 of WKUPPUPD) Wakeup pin pull configuration + @"WKUPPUPD[5]": WKUPPUPD, + padding: u4, }), }; }; @@ -356293,21 +366989,61 @@ pub const types = struct { }), /// reset only by system reset, not reset by wakeup from Standby mode WKUPFR: mmio.Mmio(packed struct(u32) { - /// Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). - WKUPF: u1, - padding: u31, + /// (1/6 of WKUPF) Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + @"WKUPF[0]": u1, + /// (2/6 of WKUPF) Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + @"WKUPF[1]": u1, + /// (3/6 of WKUPF) Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + @"WKUPF[2]": u1, + /// (4/6 of WKUPF) Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + @"WKUPF[3]": u1, + /// (5/6 of WKUPF) Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + @"WKUPF[4]": u1, + /// (6/6 of WKUPF) Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + @"WKUPF[5]": u1, + padding: u26, }), /// Reset only by system reset, not reset by wakeup from Standby mode WKUPEPR: mmio.Mmio(packed struct(u32) { - /// Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. - WKUPEN: u1, - reserved8: u7, - /// Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. - WKUPP: u1, - reserved16: u7, - /// Wakeup pin pull configuration - WKUPPUPD: WKUPPUPD, - padding: u14, + /// (1/6 of WKUPEN) Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. + @"WKUPEN[0]": u1, + /// (2/6 of WKUPEN) Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. + @"WKUPEN[1]": u1, + /// (3/6 of WKUPEN) Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. + @"WKUPEN[2]": u1, + /// (4/6 of WKUPEN) Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. + @"WKUPEN[3]": u1, + /// (5/6 of WKUPEN) Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. + @"WKUPEN[4]": u1, + /// (6/6 of WKUPEN) Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. + @"WKUPEN[5]": u1, + reserved8: u2, + /// (1/6 of WKUPP) Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + @"WKUPP[0]": u1, + /// (2/6 of WKUPP) Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + @"WKUPP[1]": u1, + /// (3/6 of WKUPP) Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + @"WKUPP[2]": u1, + /// (4/6 of WKUPP) Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + @"WKUPP[3]": u1, + /// (5/6 of WKUPP) Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + @"WKUPP[4]": u1, + /// (6/6 of WKUPP) Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + @"WKUPP[5]": u1, + reserved16: u2, + /// (1/6 of WKUPPUPD) Wakeup pin pull configuration + @"WKUPPUPD[0]": WKUPPUPD, + /// (2/6 of WKUPPUPD) Wakeup pin pull configuration + @"WKUPPUPD[1]": WKUPPUPD, + /// (3/6 of WKUPPUPD) Wakeup pin pull configuration + @"WKUPPUPD[2]": WKUPPUPD, + /// (4/6 of WKUPPUPD) Wakeup pin pull configuration + @"WKUPPUPD[3]": WKUPPUPD, + /// (5/6 of WKUPPUPD) Wakeup pin pull configuration + @"WKUPPUPD[4]": WKUPPUPD, + /// (6/6 of WKUPPUPD) Wakeup pin pull configuration + @"WKUPPUPD[5]": WKUPPUPD, + padding: u4, }), }; }; @@ -356563,27 +367299,57 @@ pub const types = struct { reserved32: [8]u8, /// PWR wakeup clear register. WKUPCR: mmio.Mmio(packed struct(u32) { - /// Clear Wakeup pin flag for WKUP1 These bits are always read as 0. - WKUPC: u1, - padding: u31, + /// (1/4 of WKUPC) Clear Wakeup pin flag for WKUP1 These bits are always read as 0. + @"WKUPC[0]": u1, + /// (2/4 of WKUPC) Clear Wakeup pin flag for WKUP1 These bits are always read as 0. + @"WKUPC[1]": u1, + /// (3/4 of WKUPC) Clear Wakeup pin flag for WKUP1 These bits are always read as 0. + @"WKUPC[2]": u1, + /// (4/4 of WKUPC) Clear Wakeup pin flag for WKUP1 These bits are always read as 0. + @"WKUPC[3]": u1, + padding: u28, }), /// PWR wakeup flag register. WKUPFR: mmio.Mmio(packed struct(u32) { - /// Wakeup pin WKUP flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPC1 bit in the PWR wakeup clear register (PWR_WKUPCR). - WKUPF: u1, - padding: u31, + /// (1/4 of WKUPF) Wakeup pin WKUP flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPC1 bit in the PWR wakeup clear register (PWR_WKUPCR). + @"WKUPF[0]": u1, + /// (2/4 of WKUPF) Wakeup pin WKUP flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPC1 bit in the PWR wakeup clear register (PWR_WKUPCR). + @"WKUPF[1]": u1, + /// (3/4 of WKUPF) Wakeup pin WKUP flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPC1 bit in the PWR wakeup clear register (PWR_WKUPCR). + @"WKUPF[2]": u1, + /// (4/4 of WKUPF) Wakeup pin WKUP flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPC1 bit in the PWR wakeup clear register (PWR_WKUPCR). + @"WKUPF[3]": u1, + padding: u28, }), /// PWR wakeup enable and polarity register. WKUPEPR: mmio.Mmio(packed struct(u32) { - /// Enable Wakeup Pin WKUPn, (n = 4, 3, 2, 1) Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn bit) when WKUPn pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn selects falling edge. - WKUPEN: u1, - reserved8: u7, - /// Wakeup pin polarity bit for WKUPn, (n = 4, 3, 2, 1) These bits define the polarity used for event detection on WKUPn external wakeup pin. - WKUPP: WKUPP, - reserved16: u7, - /// Wakeup pin pull configuration - WKUPPUPD: WKUPPUPD, - padding: u14, + /// (1/4 of WKUPEN) Enable Wakeup Pin WKUPn, (n = 4, 3, 2, 1) Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn bit) when WKUPn pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn selects falling edge. + @"WKUPEN[0]": u1, + /// (2/4 of WKUPEN) Enable Wakeup Pin WKUPn, (n = 4, 3, 2, 1) Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn bit) when WKUPn pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn selects falling edge. + @"WKUPEN[1]": u1, + /// (3/4 of WKUPEN) Enable Wakeup Pin WKUPn, (n = 4, 3, 2, 1) Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn bit) when WKUPn pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn selects falling edge. + @"WKUPEN[2]": u1, + /// (4/4 of WKUPEN) Enable Wakeup Pin WKUPn, (n = 4, 3, 2, 1) Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn bit) when WKUPn pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn selects falling edge. + @"WKUPEN[3]": u1, + reserved8: u4, + /// (1/4 of WKUPP) Wakeup pin polarity bit for WKUPn, (n = 4, 3, 2, 1) These bits define the polarity used for event detection on WKUPn external wakeup pin. + @"WKUPP[0]": WKUPP, + /// (2/4 of WKUPP) Wakeup pin polarity bit for WKUPn, (n = 4, 3, 2, 1) These bits define the polarity used for event detection on WKUPn external wakeup pin. + @"WKUPP[1]": WKUPP, + /// (3/4 of WKUPP) Wakeup pin polarity bit for WKUPn, (n = 4, 3, 2, 1) These bits define the polarity used for event detection on WKUPn external wakeup pin. + @"WKUPP[2]": WKUPP, + /// (4/4 of WKUPP) Wakeup pin polarity bit for WKUPn, (n = 4, 3, 2, 1) These bits define the polarity used for event detection on WKUPn external wakeup pin. + @"WKUPP[3]": WKUPP, + reserved16: u4, + /// (1/4 of WKUPPUPD) Wakeup pin pull configuration + @"WKUPPUPD[0]": WKUPPUPD, + /// (2/4 of WKUPPUPD) Wakeup pin pull configuration + @"WKUPPUPD[1]": WKUPPUPD, + /// (3/4 of WKUPPUPD) Wakeup pin pull configuration + @"WKUPPUPD[2]": WKUPPUPD, + /// (4/4 of WKUPPUPD) Wakeup pin pull configuration + @"WKUPPUPD[3]": WKUPPUPD, + padding: u8, }), /// PWR USB Type-C and Power Delivery register. UCPDR: mmio.Mmio(packed struct(u32) { @@ -356872,9 +367638,13 @@ pub const types = struct { /// Regulator LP flag REGLPF: u1, reserved8: u2, - /// Enable WKUP pin 1 - EWUP: u1, - padding: u23, + /// (1/3 of EWUP) Enable WKUP pin 1 + @"EWUP[0]": u1, + /// (2/3 of EWUP) Enable WKUP pin 1 + @"EWUP[1]": u1, + /// (3/3 of EWUP) Enable WKUP pin 1 + @"EWUP[2]": u1, + padding: u21, }), }; }; @@ -356974,9 +367744,17 @@ pub const types = struct { }), /// Power control register 3 CR3: mmio.Mmio(packed struct(u32) { - /// Enable Wakeup pin WKUP - EWUP: u1, - reserved8: u7, + /// (1/5 of EWUP) Enable Wakeup pin WKUP + @"EWUP[0]": u1, + /// (2/5 of EWUP) Enable Wakeup pin WKUP + @"EWUP[1]": u1, + /// (3/5 of EWUP) Enable Wakeup pin WKUP + @"EWUP[2]": u1, + /// (4/5 of EWUP) Enable Wakeup pin WKUP + @"EWUP[3]": u1, + /// (5/5 of EWUP) Enable Wakeup pin WKUP + @"EWUP[4]": u1, + reserved8: u3, /// SRAM2 retention in Standby mode RRS: RRS, reserved10: u1, @@ -357049,9 +367827,17 @@ pub const types = struct { }), /// Power status clear register SCR: mmio.Mmio(packed struct(u32) { - /// Clear wakeup flag - CWUF: u1, - reserved8: u7, + /// (1/5 of CWUF) Clear wakeup flag + @"CWUF[0]": u1, + /// (2/5 of CWUF) Clear wakeup flag + @"CWUF[1]": u1, + /// (3/5 of CWUF) Clear wakeup flag + @"CWUF[2]": u1, + /// (4/5 of CWUF) Clear wakeup flag + @"CWUF[3]": u1, + /// (5/5 of CWUF) Clear wakeup flag + @"CWUF[4]": u1, + reserved8: u3, /// Clear standby flag SBF: u1, padding: u23, @@ -357059,15 +367845,75 @@ pub const types = struct { reserved32: [4]u8, /// Power Port A pull-up control register PUCR: mmio.Mmio(packed struct(u32) { - /// Port pull bit y (y=0..15) - P: u1, - padding: u31, + /// (1/16 of P) Port pull bit y (y=0..15) + @"P[0]": u1, + /// (2/16 of P) Port pull bit y (y=0..15) + @"P[1]": u1, + /// (3/16 of P) Port pull bit y (y=0..15) + @"P[2]": u1, + /// (4/16 of P) Port pull bit y (y=0..15) + @"P[3]": u1, + /// (5/16 of P) Port pull bit y (y=0..15) + @"P[4]": u1, + /// (6/16 of P) Port pull bit y (y=0..15) + @"P[5]": u1, + /// (7/16 of P) Port pull bit y (y=0..15) + @"P[6]": u1, + /// (8/16 of P) Port pull bit y (y=0..15) + @"P[7]": u1, + /// (9/16 of P) Port pull bit y (y=0..15) + @"P[8]": u1, + /// (10/16 of P) Port pull bit y (y=0..15) + @"P[9]": u1, + /// (11/16 of P) Port pull bit y (y=0..15) + @"P[10]": u1, + /// (12/16 of P) Port pull bit y (y=0..15) + @"P[11]": u1, + /// (13/16 of P) Port pull bit y (y=0..15) + @"P[12]": u1, + /// (14/16 of P) Port pull bit y (y=0..15) + @"P[13]": u1, + /// (15/16 of P) Port pull bit y (y=0..15) + @"P[14]": u1, + /// (16/16 of P) Port pull bit y (y=0..15) + @"P[15]": u1, + padding: u16, }), /// Power Port A pull-down control register PDCR: mmio.Mmio(packed struct(u32) { - /// Port pull bit y (y=0..15) - P: u1, - padding: u31, + /// (1/16 of P) Port pull bit y (y=0..15) + @"P[0]": u1, + /// (2/16 of P) Port pull bit y (y=0..15) + @"P[1]": u1, + /// (3/16 of P) Port pull bit y (y=0..15) + @"P[2]": u1, + /// (4/16 of P) Port pull bit y (y=0..15) + @"P[3]": u1, + /// (5/16 of P) Port pull bit y (y=0..15) + @"P[4]": u1, + /// (6/16 of P) Port pull bit y (y=0..15) + @"P[5]": u1, + /// (7/16 of P) Port pull bit y (y=0..15) + @"P[6]": u1, + /// (8/16 of P) Port pull bit y (y=0..15) + @"P[7]": u1, + /// (9/16 of P) Port pull bit y (y=0..15) + @"P[8]": u1, + /// (10/16 of P) Port pull bit y (y=0..15) + @"P[9]": u1, + /// (11/16 of P) Port pull bit y (y=0..15) + @"P[10]": u1, + /// (12/16 of P) Port pull bit y (y=0..15) + @"P[11]": u1, + /// (13/16 of P) Port pull bit y (y=0..15) + @"P[12]": u1, + /// (14/16 of P) Port pull bit y (y=0..15) + @"P[13]": u1, + /// (15/16 of P) Port pull bit y (y=0..15) + @"P[14]": u1, + /// (16/16 of P) Port pull bit y (y=0..15) + @"P[15]": u1, + padding: u16, }), }; }; @@ -357172,9 +368018,17 @@ pub const types = struct { }), /// Power control register 3 CR3: mmio.Mmio(packed struct(u32) { - /// Enable Wakeup pin WKUP - EWUP: u1, - reserved8: u7, + /// (1/5 of EWUP) Enable Wakeup pin WKUP + @"EWUP[0]": u1, + /// (2/5 of EWUP) Enable Wakeup pin WKUP + @"EWUP[1]": u1, + /// (3/5 of EWUP) Enable Wakeup pin WKUP + @"EWUP[2]": u1, + /// (4/5 of EWUP) Enable Wakeup pin WKUP + @"EWUP[3]": u1, + /// (5/5 of EWUP) Enable Wakeup pin WKUP + @"EWUP[4]": u1, + reserved8: u3, /// SRAM2 retention in Standby mode RRS: RRS, /// Apply pull-up and pull-down configuration @@ -357259,9 +368113,17 @@ pub const types = struct { }), /// Power status clear register SCR: mmio.Mmio(packed struct(u32) { - /// Clear wakeup flag - CWUF: u1, - reserved8: u7, + /// (1/5 of CWUF) Clear wakeup flag + @"CWUF[0]": u1, + /// (2/5 of CWUF) Clear wakeup flag + @"CWUF[1]": u1, + /// (3/5 of CWUF) Clear wakeup flag + @"CWUF[2]": u1, + /// (4/5 of CWUF) Clear wakeup flag + @"CWUF[3]": u1, + /// (5/5 of CWUF) Clear wakeup flag + @"CWUF[4]": u1, + reserved8: u3, /// Clear standby flag SBF: u1, padding: u23, @@ -357269,15 +368131,75 @@ pub const types = struct { reserved32: [4]u8, /// Power Port A pull-up control register PUCR: mmio.Mmio(packed struct(u32) { - /// Port pull bit y (y=0..15) - P: u1, - padding: u31, + /// (1/16 of P) Port pull bit y (y=0..15) + @"P[0]": u1, + /// (2/16 of P) Port pull bit y (y=0..15) + @"P[1]": u1, + /// (3/16 of P) Port pull bit y (y=0..15) + @"P[2]": u1, + /// (4/16 of P) Port pull bit y (y=0..15) + @"P[3]": u1, + /// (5/16 of P) Port pull bit y (y=0..15) + @"P[4]": u1, + /// (6/16 of P) Port pull bit y (y=0..15) + @"P[5]": u1, + /// (7/16 of P) Port pull bit y (y=0..15) + @"P[6]": u1, + /// (8/16 of P) Port pull bit y (y=0..15) + @"P[7]": u1, + /// (9/16 of P) Port pull bit y (y=0..15) + @"P[8]": u1, + /// (10/16 of P) Port pull bit y (y=0..15) + @"P[9]": u1, + /// (11/16 of P) Port pull bit y (y=0..15) + @"P[10]": u1, + /// (12/16 of P) Port pull bit y (y=0..15) + @"P[11]": u1, + /// (13/16 of P) Port pull bit y (y=0..15) + @"P[12]": u1, + /// (14/16 of P) Port pull bit y (y=0..15) + @"P[13]": u1, + /// (15/16 of P) Port pull bit y (y=0..15) + @"P[14]": u1, + /// (16/16 of P) Port pull bit y (y=0..15) + @"P[15]": u1, + padding: u16, }), /// Power Port A pull-down control register PDCR: mmio.Mmio(packed struct(u32) { - /// Port pull bit y (y=0..15) - P: u1, - padding: u31, + /// (1/16 of P) Port pull bit y (y=0..15) + @"P[0]": u1, + /// (2/16 of P) Port pull bit y (y=0..15) + @"P[1]": u1, + /// (3/16 of P) Port pull bit y (y=0..15) + @"P[2]": u1, + /// (4/16 of P) Port pull bit y (y=0..15) + @"P[3]": u1, + /// (5/16 of P) Port pull bit y (y=0..15) + @"P[4]": u1, + /// (6/16 of P) Port pull bit y (y=0..15) + @"P[5]": u1, + /// (7/16 of P) Port pull bit y (y=0..15) + @"P[6]": u1, + /// (8/16 of P) Port pull bit y (y=0..15) + @"P[7]": u1, + /// (9/16 of P) Port pull bit y (y=0..15) + @"P[8]": u1, + /// (10/16 of P) Port pull bit y (y=0..15) + @"P[9]": u1, + /// (11/16 of P) Port pull bit y (y=0..15) + @"P[10]": u1, + /// (12/16 of P) Port pull bit y (y=0..15) + @"P[11]": u1, + /// (13/16 of P) Port pull bit y (y=0..15) + @"P[12]": u1, + /// (14/16 of P) Port pull bit y (y=0..15) + @"P[13]": u1, + /// (15/16 of P) Port pull bit y (y=0..15) + @"P[14]": u1, + /// (16/16 of P) Port pull bit y (y=0..15) + @"P[15]": u1, + padding: u16, }), reserved120: [80]u8, /// Power secure configuration register @@ -358125,15 +369047,43 @@ pub const types = struct { }), /// wakeup control register 1 WUCR1: mmio.Mmio(packed struct(u32) { - /// Wakeup pin WKUP1 enable - WUPEN: u1, - padding: u31, + /// (1/8 of WUPEN) Wakeup pin WKUP1 enable + @"WUPEN[0]": u1, + /// (2/8 of WUPEN) Wakeup pin WKUP1 enable + @"WUPEN[1]": u1, + /// (3/8 of WUPEN) Wakeup pin WKUP1 enable + @"WUPEN[2]": u1, + /// (4/8 of WUPEN) Wakeup pin WKUP1 enable + @"WUPEN[3]": u1, + /// (5/8 of WUPEN) Wakeup pin WKUP1 enable + @"WUPEN[4]": u1, + /// (6/8 of WUPEN) Wakeup pin WKUP1 enable + @"WUPEN[5]": u1, + /// (7/8 of WUPEN) Wakeup pin WKUP1 enable + @"WUPEN[6]": u1, + /// (8/8 of WUPEN) Wakeup pin WKUP1 enable + @"WUPEN[7]": u1, + padding: u24, }), /// wakeup control register 2 WUCR2: mmio.Mmio(packed struct(u32) { - /// Wakeup pin WKUP1 polarity. This bit must be configured when WUPEN1 = 0. - WUPP: WUPP, - padding: u31, + /// (1/8 of WUPP) Wakeup pin WKUP1 polarity. This bit must be configured when WUPEN1 = 0. + @"WUPP[0]": WUPP, + /// (2/8 of WUPP) Wakeup pin WKUP1 polarity. This bit must be configured when WUPEN1 = 0. + @"WUPP[1]": WUPP, + /// (3/8 of WUPP) Wakeup pin WKUP1 polarity. This bit must be configured when WUPEN1 = 0. + @"WUPP[2]": WUPP, + /// (4/8 of WUPP) Wakeup pin WKUP1 polarity. This bit must be configured when WUPEN1 = 0. + @"WUPP[3]": WUPP, + /// (5/8 of WUPP) Wakeup pin WKUP1 polarity. This bit must be configured when WUPEN1 = 0. + @"WUPP[4]": WUPP, + /// (6/8 of WUPP) Wakeup pin WKUP1 polarity. This bit must be configured when WUPEN1 = 0. + @"WUPP[5]": WUPP, + /// (7/8 of WUPP) Wakeup pin WKUP1 polarity. This bit must be configured when WUPEN1 = 0. + @"WUPP[6]": WUPP, + /// (8/8 of WUPP) Wakeup pin WKUP1 polarity. This bit must be configured when WUPEN1 = 0. + @"WUPP[7]": WUPP, + padding: u24, }), /// wakeup control register 3 WUCR3: mmio.Mmio(packed struct(u32) { @@ -358188,9 +369138,23 @@ pub const types = struct { }), /// security configuration register SECCFGR: mmio.Mmio(packed struct(u32) { - /// WUP1 secure protection - WUP1SEC: u1, - reserved12: u11, + /// (1/8 of WUP1SEC) WUP1 secure protection + @"WUP1SEC[0]": u1, + /// (2/8 of WUP1SEC) WUP1 secure protection + @"WUP1SEC[1]": u1, + /// (3/8 of WUP1SEC) WUP1 secure protection + @"WUP1SEC[2]": u1, + /// (4/8 of WUP1SEC) WUP1 secure protection + @"WUP1SEC[3]": u1, + /// (5/8 of WUP1SEC) WUP1 secure protection + @"WUP1SEC[4]": u1, + /// (6/8 of WUP1SEC) WUP1 secure protection + @"WUP1SEC[5]": u1, + /// (7/8 of WUP1SEC) WUP1 secure protection + @"WUP1SEC[6]": u1, + /// (8/8 of WUP1SEC) WUP1 secure protection + @"WUP1SEC[7]": u1, + reserved12: u4, /// Low-power modes secure protection LPMSEC: u1, /// Voltage detection and monitoring secure protection @@ -358301,15 +369265,75 @@ pub const types = struct { }), /// Power Port pull-up control register PUCR: mmio.Mmio(packed struct(u32) { - /// Port pull bit y (y=0..15) - P: u1, - padding: u31, + /// (1/16 of P) Port pull bit y (y=0..15) + @"P[0]": u1, + /// (2/16 of P) Port pull bit y (y=0..15) + @"P[1]": u1, + /// (3/16 of P) Port pull bit y (y=0..15) + @"P[2]": u1, + /// (4/16 of P) Port pull bit y (y=0..15) + @"P[3]": u1, + /// (5/16 of P) Port pull bit y (y=0..15) + @"P[4]": u1, + /// (6/16 of P) Port pull bit y (y=0..15) + @"P[5]": u1, + /// (7/16 of P) Port pull bit y (y=0..15) + @"P[6]": u1, + /// (8/16 of P) Port pull bit y (y=0..15) + @"P[7]": u1, + /// (9/16 of P) Port pull bit y (y=0..15) + @"P[8]": u1, + /// (10/16 of P) Port pull bit y (y=0..15) + @"P[9]": u1, + /// (11/16 of P) Port pull bit y (y=0..15) + @"P[10]": u1, + /// (12/16 of P) Port pull bit y (y=0..15) + @"P[11]": u1, + /// (13/16 of P) Port pull bit y (y=0..15) + @"P[12]": u1, + /// (14/16 of P) Port pull bit y (y=0..15) + @"P[13]": u1, + /// (15/16 of P) Port pull bit y (y=0..15) + @"P[14]": u1, + /// (16/16 of P) Port pull bit y (y=0..15) + @"P[15]": u1, + padding: u16, }), /// Power Port pull-down control register PDCR: mmio.Mmio(packed struct(u32) { - /// Port pull bit y (y=0..15) - P: u1, - padding: u31, + /// (1/16 of P) Port pull bit y (y=0..15) + @"P[0]": u1, + /// (2/16 of P) Port pull bit y (y=0..15) + @"P[1]": u1, + /// (3/16 of P) Port pull bit y (y=0..15) + @"P[2]": u1, + /// (4/16 of P) Port pull bit y (y=0..15) + @"P[3]": u1, + /// (5/16 of P) Port pull bit y (y=0..15) + @"P[4]": u1, + /// (6/16 of P) Port pull bit y (y=0..15) + @"P[5]": u1, + /// (7/16 of P) Port pull bit y (y=0..15) + @"P[6]": u1, + /// (8/16 of P) Port pull bit y (y=0..15) + @"P[7]": u1, + /// (9/16 of P) Port pull bit y (y=0..15) + @"P[8]": u1, + /// (10/16 of P) Port pull bit y (y=0..15) + @"P[9]": u1, + /// (11/16 of P) Port pull bit y (y=0..15) + @"P[10]": u1, + /// (12/16 of P) Port pull bit y (y=0..15) + @"P[11]": u1, + /// (13/16 of P) Port pull bit y (y=0..15) + @"P[12]": u1, + /// (14/16 of P) Port pull bit y (y=0..15) + @"P[13]": u1, + /// (15/16 of P) Port pull bit y (y=0..15) + @"P[14]": u1, + /// (16/16 of P) Port pull bit y (y=0..15) + @"P[15]": u1, + padding: u16, }), }; }; @@ -358344,9 +369368,17 @@ pub const types = struct { }), /// Power control register 3 CR3: mmio.Mmio(packed struct(u32) { - /// Enable Wakeup pin - EWUP: u1, - reserved8: u7, + /// (1/5 of EWUP) Enable Wakeup pin + @"EWUP[0]": u1, + /// (2/5 of EWUP) Enable Wakeup pin + @"EWUP[1]": u1, + /// (3/5 of EWUP) Enable Wakeup pin + @"EWUP[2]": u1, + /// (4/5 of EWUP) Enable Wakeup pin + @"EWUP[3]": u1, + /// (5/5 of EWUP) Enable Wakeup pin + @"EWUP[4]": u1, + reserved8: u3, /// Enable BORH and Step Down counverter forced in Bypass interrups for CPU1 EBORHSDFB: u1, /// SRAM2a retention in Standby mode @@ -358367,9 +369399,17 @@ pub const types = struct { }), /// Power control register 4 CR4: mmio.Mmio(packed struct(u32) { - /// Wakeup pin WKUP1 polarity - WP1: u1, - reserved8: u7, + /// (1/5 of WP1) Wakeup pin WKUP1 polarity + @"WP1[0]": u1, + /// (2/5 of WP1) Wakeup pin WKUP1 polarity + @"WP1[1]": u1, + /// (3/5 of WP1) Wakeup pin WKUP1 polarity + @"WP1[2]": u1, + /// (4/5 of WP1) Wakeup pin WKUP1 polarity + @"WP1[3]": u1, + /// (5/5 of WP1) Wakeup pin WKUP1 polarity + @"WP1[4]": u1, + reserved8: u3, /// VBAT battery charging enable VBE: u1, /// VBAT battery charging resistor selection @@ -358381,9 +369421,17 @@ pub const types = struct { }), /// Power status register 1 SR1: mmio.Mmio(packed struct(u32) { - /// Wakeup flag 1 - CWUF: u1, - reserved7: u6, + /// (1/5 of CWUF) Wakeup flag 1 + @"CWUF[0]": u1, + /// (2/5 of CWUF) Wakeup flag 1 + @"CWUF[1]": u1, + /// (3/5 of CWUF) Wakeup flag 1 + @"CWUF[2]": u1, + /// (4/5 of CWUF) Wakeup flag 1 + @"CWUF[3]": u1, + /// (5/5 of CWUF) Wakeup flag 1 + @"CWUF[4]": u1, + reserved7: u2, /// Step Down converter forced in Bypass interrupt flag SDFBF: u1, /// BORH interrupt flag @@ -358428,9 +369476,17 @@ pub const types = struct { }), /// Power status clear register SCR: mmio.Mmio(packed struct(u32) { - /// Clear wakeup flag 1 - CWUF: u1, - reserved7: u6, + /// (1/5 of CWUF) Clear wakeup flag 1 + @"CWUF[0]": u1, + /// (2/5 of CWUF) Clear wakeup flag 1 + @"CWUF[1]": u1, + /// (3/5 of CWUF) Clear wakeup flag 1 + @"CWUF[2]": u1, + /// (4/5 of CWUF) Clear wakeup flag 1 + @"CWUF[3]": u1, + /// (5/5 of CWUF) Clear wakeup flag 1 + @"CWUF[4]": u1, + reserved7: u2, /// Clear SMPS Step Down converter forced in Bypass interrupt flag CSMPSFBF: u1, /// Clear BORH interrupt flag @@ -358469,76 +369525,436 @@ pub const types = struct { }), /// Power Port A pull-up control register PUCRA: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// (1/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[0]": u1, + /// (2/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[1]": u1, + /// (3/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[2]": u1, + /// (4/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[3]": u1, + /// (5/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[4]": u1, + /// (6/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[5]": u1, + /// (7/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[6]": u1, + /// (8/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[7]": u1, + /// (9/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[8]": u1, + /// (10/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[9]": u1, + /// (11/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[10]": u1, + /// (12/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[11]": u1, + /// (13/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[12]": u1, + /// (14/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[13]": u1, + /// (15/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[14]": u1, + /// (16/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[15]": u1, + padding: u16, }), /// Power Port A pull-down control register PDCRA: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// (1/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[0]": u1, + /// (2/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[1]": u1, + /// (3/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[2]": u1, + /// (4/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[3]": u1, + /// (5/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[4]": u1, + /// (6/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[5]": u1, + /// (7/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[6]": u1, + /// (8/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[7]": u1, + /// (9/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[8]": u1, + /// (10/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[9]": u1, + /// (11/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[10]": u1, + /// (12/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[11]": u1, + /// (13/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[12]": u1, + /// (14/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[13]": u1, + /// (15/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[14]": u1, + /// (16/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[15]": u1, + padding: u16, }), /// Power Port B pull-up control register PUCRB: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// (1/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[0]": u1, + /// (2/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[1]": u1, + /// (3/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[2]": u1, + /// (4/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[3]": u1, + /// (5/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[4]": u1, + /// (6/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[5]": u1, + /// (7/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[6]": u1, + /// (8/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[7]": u1, + /// (9/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[8]": u1, + /// (10/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[9]": u1, + /// (11/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[10]": u1, + /// (12/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[11]": u1, + /// (13/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[12]": u1, + /// (14/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[13]": u1, + /// (15/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[14]": u1, + /// (16/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[15]": u1, + padding: u16, }), /// Power Port B pull-down control register PDCRB: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// (1/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[0]": u1, + /// (2/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[1]": u1, + /// (3/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[2]": u1, + /// (4/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[3]": u1, + /// (5/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[4]": u1, + /// (6/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[5]": u1, + /// (7/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[6]": u1, + /// (8/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[7]": u1, + /// (9/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[8]": u1, + /// (10/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[9]": u1, + /// (11/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[10]": u1, + /// (12/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[11]": u1, + /// (13/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[12]": u1, + /// (14/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[13]": u1, + /// (15/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[14]": u1, + /// (16/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[15]": u1, + padding: u16, }), /// Power Port C pull-up control register PUCRC: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// (1/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[0]": u1, + /// (2/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[1]": u1, + /// (3/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[2]": u1, + /// (4/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[3]": u1, + /// (5/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[4]": u1, + /// (6/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[5]": u1, + /// (7/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[6]": u1, + /// (8/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[7]": u1, + /// (9/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[8]": u1, + /// (10/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[9]": u1, + /// (11/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[10]": u1, + /// (12/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[11]": u1, + /// (13/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[12]": u1, + /// (14/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[13]": u1, + /// (15/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[14]": u1, + /// (16/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[15]": u1, + padding: u16, }), /// Power Port C pull-down control register PDCRC: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// (1/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[0]": u1, + /// (2/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[1]": u1, + /// (3/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[2]": u1, + /// (4/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[3]": u1, + /// (5/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[4]": u1, + /// (6/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[5]": u1, + /// (7/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[6]": u1, + /// (8/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[7]": u1, + /// (9/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[8]": u1, + /// (10/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[9]": u1, + /// (11/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[10]": u1, + /// (12/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[11]": u1, + /// (13/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[12]": u1, + /// (14/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[13]": u1, + /// (15/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[14]": u1, + /// (16/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[15]": u1, + padding: u16, }), /// Power Port D pull-up control register PUCRD: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// (1/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[0]": u1, + /// (2/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[1]": u1, + /// (3/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[2]": u1, + /// (4/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[3]": u1, + /// (5/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[4]": u1, + /// (6/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[5]": u1, + /// (7/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[6]": u1, + /// (8/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[7]": u1, + /// (9/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[8]": u1, + /// (10/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[9]": u1, + /// (11/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[10]": u1, + /// (12/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[11]": u1, + /// (13/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[12]": u1, + /// (14/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[13]": u1, + /// (15/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[14]": u1, + /// (16/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[15]": u1, + padding: u16, }), /// Power Port D pull-down control register PDCRD: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// (1/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[0]": u1, + /// (2/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[1]": u1, + /// (3/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[2]": u1, + /// (4/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[3]": u1, + /// (5/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[4]": u1, + /// (6/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[5]": u1, + /// (7/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[6]": u1, + /// (8/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[7]": u1, + /// (9/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[8]": u1, + /// (10/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[9]": u1, + /// (11/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[10]": u1, + /// (12/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[11]": u1, + /// (13/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[12]": u1, + /// (14/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[13]": u1, + /// (15/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[14]": u1, + /// (16/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[15]": u1, + padding: u16, }), /// Power Port E pull-up control register PUCRE: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// (1/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[0]": u1, + /// (2/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[1]": u1, + /// (3/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[2]": u1, + /// (4/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[3]": u1, + /// (5/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[4]": u1, + /// (6/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[5]": u1, + /// (7/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[6]": u1, + /// (8/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[7]": u1, + /// (9/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[8]": u1, + /// (10/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[9]": u1, + /// (11/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[10]": u1, + /// (12/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[11]": u1, + /// (13/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[12]": u1, + /// (14/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[13]": u1, + /// (15/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[14]": u1, + /// (16/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[15]": u1, + padding: u16, }), /// Power Port E pull-down control register PDCRE: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// (1/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[0]": u1, + /// (2/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[1]": u1, + /// (3/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[2]": u1, + /// (4/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[3]": u1, + /// (5/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[4]": u1, + /// (6/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[5]": u1, + /// (7/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[6]": u1, + /// (8/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[7]": u1, + /// (9/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[8]": u1, + /// (10/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[9]": u1, + /// (11/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[10]": u1, + /// (12/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[11]": u1, + /// (13/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[12]": u1, + /// (14/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[13]": u1, + /// (15/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[14]": u1, + /// (16/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[15]": u1, + padding: u16, }), reserved88: [16]u8, /// Power Port H pull-up control register PUCRH: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// (1/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[0]": u1, + /// (2/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[1]": u1, + /// (3/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[2]": u1, + /// (4/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[3]": u1, + /// (5/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[4]": u1, + /// (6/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[5]": u1, + /// (7/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[6]": u1, + /// (8/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[7]": u1, + /// (9/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[8]": u1, + /// (10/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[9]": u1, + /// (11/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[10]": u1, + /// (12/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[11]": u1, + /// (13/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[12]": u1, + /// (14/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[13]": u1, + /// (15/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[14]": u1, + /// (16/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[15]": u1, + padding: u16, }), /// Power Port H pull-down control register PDCRH: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// (1/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[0]": u1, + /// (2/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[1]": u1, + /// (3/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[2]": u1, + /// (4/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[3]": u1, + /// (5/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[4]": u1, + /// (6/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[5]": u1, + /// (7/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[6]": u1, + /// (8/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[7]": u1, + /// (9/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[8]": u1, + /// (10/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[9]": u1, + /// (11/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[10]": u1, + /// (12/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[11]": u1, + /// (13/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[12]": u1, + /// (14/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[13]": u1, + /// (15/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[14]": u1, + /// (16/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[15]": u1, + padding: u16, }), reserved128: [32]u8, /// CPU2 Power control register 1 @@ -358559,9 +369975,17 @@ pub const types = struct { }), /// CPU2 Power control register 3 C2CR3: mmio.Mmio(packed struct(u32) { - /// Enable Wakeup pin - EWUP: u1, - reserved9: u8, + /// (1/5 of EWUP) Enable Wakeup pin + @"EWUP[0]": u1, + /// (2/5 of EWUP) Enable Wakeup pin + @"EWUP[1]": u1, + /// (3/5 of EWUP) Enable Wakeup pin + @"EWUP[2]": u1, + /// (4/5 of EWUP) Enable Wakeup pin + @"EWUP[3]": u1, + /// (5/5 of EWUP) Enable Wakeup pin + @"EWUP[4]": u1, + reserved9: u4, /// Enable BLE host wakeup interrupt for CPU2 EBLEWUP: u1, /// Enable 802.15.4 host wakeup interrupt for CPU2 @@ -358651,9 +370075,17 @@ pub const types = struct { }), /// Power control register 3 CR3: mmio.Mmio(packed struct(u32) { - /// Enable Wakeup pin - EWUP: u1, - reserved8: u7, + /// (1/5 of EWUP) Enable Wakeup pin + @"EWUP[0]": u1, + /// (2/5 of EWUP) Enable Wakeup pin + @"EWUP[1]": u1, + /// (3/5 of EWUP) Enable Wakeup pin + @"EWUP[2]": u1, + /// (4/5 of EWUP) Enable Wakeup pin + @"EWUP[3]": u1, + /// (5/5 of EWUP) Enable Wakeup pin + @"EWUP[4]": u1, + reserved8: u3, /// Enable BORH and Step Down counverter forced in Bypass interrups for CPU1 EBORHSDFB: u1, /// SRAM2a retention in Standby mode @@ -358674,9 +370106,17 @@ pub const types = struct { }), /// Power control register 4 CR4: mmio.Mmio(packed struct(u32) { - /// Wakeup pin WKUP1 polarity - WP1: u1, - reserved8: u7, + /// (1/5 of WP1) Wakeup pin WKUP1 polarity + @"WP1[0]": u1, + /// (2/5 of WP1) Wakeup pin WKUP1 polarity + @"WP1[1]": u1, + /// (3/5 of WP1) Wakeup pin WKUP1 polarity + @"WP1[2]": u1, + /// (4/5 of WP1) Wakeup pin WKUP1 polarity + @"WP1[3]": u1, + /// (5/5 of WP1) Wakeup pin WKUP1 polarity + @"WP1[4]": u1, + reserved8: u3, /// VBAT battery charging enable VBE: u1, /// VBAT battery charging resistor selection @@ -358688,9 +370128,17 @@ pub const types = struct { }), /// Power status register 1 SR1: mmio.Mmio(packed struct(u32) { - /// Wakeup flag 1 - CWUF: u1, - reserved7: u6, + /// (1/5 of CWUF) Wakeup flag 1 + @"CWUF[0]": u1, + /// (2/5 of CWUF) Wakeup flag 1 + @"CWUF[1]": u1, + /// (3/5 of CWUF) Wakeup flag 1 + @"CWUF[2]": u1, + /// (4/5 of CWUF) Wakeup flag 1 + @"CWUF[3]": u1, + /// (5/5 of CWUF) Wakeup flag 1 + @"CWUF[4]": u1, + reserved7: u2, /// Step Down converter forced in Bypass interrupt flag SDFBF: u1, /// BORH interrupt flag @@ -358735,9 +370183,17 @@ pub const types = struct { }), /// Power status clear register SCR: mmio.Mmio(packed struct(u32) { - /// Clear wakeup flag 1 - CWUF: u1, - reserved7: u6, + /// (1/5 of CWUF) Clear wakeup flag 1 + @"CWUF[0]": u1, + /// (2/5 of CWUF) Clear wakeup flag 1 + @"CWUF[1]": u1, + /// (3/5 of CWUF) Clear wakeup flag 1 + @"CWUF[2]": u1, + /// (4/5 of CWUF) Clear wakeup flag 1 + @"CWUF[3]": u1, + /// (5/5 of CWUF) Clear wakeup flag 1 + @"CWUF[4]": u1, + reserved7: u2, /// Clear SMPS Step Down converter forced in Bypass interrupt flag CSMPSFBF: u1, /// Clear BORH interrupt flag @@ -358776,76 +370232,436 @@ pub const types = struct { }), /// Power Port A pull-up control register PUCRA: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// (1/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[0]": u1, + /// (2/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[1]": u1, + /// (3/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[2]": u1, + /// (4/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[3]": u1, + /// (5/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[4]": u1, + /// (6/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[5]": u1, + /// (7/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[6]": u1, + /// (8/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[7]": u1, + /// (9/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[8]": u1, + /// (10/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[9]": u1, + /// (11/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[10]": u1, + /// (12/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[11]": u1, + /// (13/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[12]": u1, + /// (14/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[13]": u1, + /// (15/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[14]": u1, + /// (16/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[15]": u1, + padding: u16, }), /// Power Port A pull-down control register PDCRA: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// (1/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[0]": u1, + /// (2/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[1]": u1, + /// (3/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[2]": u1, + /// (4/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[3]": u1, + /// (5/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[4]": u1, + /// (6/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[5]": u1, + /// (7/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[6]": u1, + /// (8/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[7]": u1, + /// (9/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[8]": u1, + /// (10/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[9]": u1, + /// (11/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[10]": u1, + /// (12/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[11]": u1, + /// (13/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[12]": u1, + /// (14/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[13]": u1, + /// (15/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[14]": u1, + /// (16/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[15]": u1, + padding: u16, }), /// Power Port B pull-up control register PUCRB: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// (1/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[0]": u1, + /// (2/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[1]": u1, + /// (3/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[2]": u1, + /// (4/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[3]": u1, + /// (5/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[4]": u1, + /// (6/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[5]": u1, + /// (7/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[6]": u1, + /// (8/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[7]": u1, + /// (9/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[8]": u1, + /// (10/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[9]": u1, + /// (11/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[10]": u1, + /// (12/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[11]": u1, + /// (13/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[12]": u1, + /// (14/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[13]": u1, + /// (15/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[14]": u1, + /// (16/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[15]": u1, + padding: u16, }), /// Power Port B pull-down control register PDCRB: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// (1/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[0]": u1, + /// (2/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[1]": u1, + /// (3/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[2]": u1, + /// (4/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[3]": u1, + /// (5/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[4]": u1, + /// (6/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[5]": u1, + /// (7/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[6]": u1, + /// (8/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[7]": u1, + /// (9/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[8]": u1, + /// (10/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[9]": u1, + /// (11/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[10]": u1, + /// (12/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[11]": u1, + /// (13/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[12]": u1, + /// (14/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[13]": u1, + /// (15/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[14]": u1, + /// (16/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[15]": u1, + padding: u16, }), /// Power Port C pull-up control register PUCRC: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// (1/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[0]": u1, + /// (2/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[1]": u1, + /// (3/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[2]": u1, + /// (4/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[3]": u1, + /// (5/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[4]": u1, + /// (6/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[5]": u1, + /// (7/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[6]": u1, + /// (8/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[7]": u1, + /// (9/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[8]": u1, + /// (10/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[9]": u1, + /// (11/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[10]": u1, + /// (12/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[11]": u1, + /// (13/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[12]": u1, + /// (14/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[13]": u1, + /// (15/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[14]": u1, + /// (16/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[15]": u1, + padding: u16, }), /// Power Port C pull-down control register PDCRC: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// (1/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[0]": u1, + /// (2/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[1]": u1, + /// (3/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[2]": u1, + /// (4/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[3]": u1, + /// (5/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[4]": u1, + /// (6/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[5]": u1, + /// (7/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[6]": u1, + /// (8/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[7]": u1, + /// (9/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[8]": u1, + /// (10/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[9]": u1, + /// (11/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[10]": u1, + /// (12/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[11]": u1, + /// (13/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[12]": u1, + /// (14/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[13]": u1, + /// (15/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[14]": u1, + /// (16/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[15]": u1, + padding: u16, }), /// Power Port D pull-up control register PUCRD: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// (1/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[0]": u1, + /// (2/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[1]": u1, + /// (3/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[2]": u1, + /// (4/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[3]": u1, + /// (5/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[4]": u1, + /// (6/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[5]": u1, + /// (7/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[6]": u1, + /// (8/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[7]": u1, + /// (9/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[8]": u1, + /// (10/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[9]": u1, + /// (11/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[10]": u1, + /// (12/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[11]": u1, + /// (13/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[12]": u1, + /// (14/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[13]": u1, + /// (15/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[14]": u1, + /// (16/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[15]": u1, + padding: u16, }), /// Power Port D pull-down control register PDCRD: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// (1/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[0]": u1, + /// (2/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[1]": u1, + /// (3/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[2]": u1, + /// (4/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[3]": u1, + /// (5/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[4]": u1, + /// (6/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[5]": u1, + /// (7/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[6]": u1, + /// (8/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[7]": u1, + /// (9/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[8]": u1, + /// (10/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[9]": u1, + /// (11/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[10]": u1, + /// (12/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[11]": u1, + /// (13/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[12]": u1, + /// (14/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[13]": u1, + /// (15/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[14]": u1, + /// (16/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[15]": u1, + padding: u16, }), /// Power Port E pull-up control register PUCRE: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// (1/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[0]": u1, + /// (2/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[1]": u1, + /// (3/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[2]": u1, + /// (4/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[3]": u1, + /// (5/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[4]": u1, + /// (6/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[5]": u1, + /// (7/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[6]": u1, + /// (8/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[7]": u1, + /// (9/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[8]": u1, + /// (10/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[9]": u1, + /// (11/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[10]": u1, + /// (12/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[11]": u1, + /// (13/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[12]": u1, + /// (14/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[13]": u1, + /// (15/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[14]": u1, + /// (16/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[15]": u1, + padding: u16, }), /// Power Port E pull-down control register PDCRE: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// (1/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[0]": u1, + /// (2/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[1]": u1, + /// (3/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[2]": u1, + /// (4/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[3]": u1, + /// (5/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[4]": u1, + /// (6/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[5]": u1, + /// (7/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[6]": u1, + /// (8/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[7]": u1, + /// (9/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[8]": u1, + /// (10/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[9]": u1, + /// (11/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[10]": u1, + /// (12/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[11]": u1, + /// (13/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[12]": u1, + /// (14/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[13]": u1, + /// (15/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[14]": u1, + /// (16/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[15]": u1, + padding: u16, }), reserved88: [16]u8, /// Power Port H pull-up control register PUCRH: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// (1/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[0]": u1, + /// (2/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[1]": u1, + /// (3/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[2]": u1, + /// (4/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[3]": u1, + /// (5/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[4]": u1, + /// (6/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[5]": u1, + /// (7/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[6]": u1, + /// (8/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[7]": u1, + /// (9/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[8]": u1, + /// (10/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[9]": u1, + /// (11/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[10]": u1, + /// (12/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[11]": u1, + /// (13/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[12]": u1, + /// (14/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[13]": u1, + /// (15/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[14]": u1, + /// (16/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[15]": u1, + padding: u16, }), /// Power Port H pull-down control register PDCRH: mmio.Mmio(packed struct(u32) { - /// Port A pull-up/down bit y (y=0..15) - PD: u1, - padding: u31, + /// (1/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[0]": u1, + /// (2/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[1]": u1, + /// (3/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[2]": u1, + /// (4/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[3]": u1, + /// (5/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[4]": u1, + /// (6/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[5]": u1, + /// (7/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[6]": u1, + /// (8/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[7]": u1, + /// (9/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[8]": u1, + /// (10/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[9]": u1, + /// (11/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[10]": u1, + /// (12/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[11]": u1, + /// (13/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[12]": u1, + /// (14/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[13]": u1, + /// (15/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[14]": u1, + /// (16/16 of PD) Port A pull-up/down bit y (y=0..15) + @"PD[15]": u1, + padding: u16, }), reserved128: [32]u8, /// CPU2 Power control register 1 @@ -358866,9 +370682,17 @@ pub const types = struct { }), /// CPU2 Power control register 3 C2CR3: mmio.Mmio(packed struct(u32) { - /// Enable Wakeup pin - EWUP: u1, - reserved9: u8, + /// (1/5 of EWUP) Enable Wakeup pin + @"EWUP[0]": u1, + /// (2/5 of EWUP) Enable Wakeup pin + @"EWUP[1]": u1, + /// (3/5 of EWUP) Enable Wakeup pin + @"EWUP[2]": u1, + /// (4/5 of EWUP) Enable Wakeup pin + @"EWUP[3]": u1, + /// (5/5 of EWUP) Enable Wakeup pin + @"EWUP[4]": u1, + reserved9: u4, /// Enable BLE host wakeup interrupt for CPU2 EBLEWUP: u1, /// Enable 802.15.4 host wakeup interrupt for CPU2 @@ -359068,15 +370892,43 @@ pub const types = struct { }), /// wakeup control register 1 WUCR1: mmio.Mmio(packed struct(u32) { - /// Wakeup and interrupt pin WKUP1 enable Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. - WUPEN: u1, - padding: u31, + /// (1/8 of WUPEN) Wakeup and interrupt pin WKUP1 enable Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. + @"WUPEN[0]": u1, + /// (2/8 of WUPEN) Wakeup and interrupt pin WKUP1 enable Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. + @"WUPEN[1]": u1, + /// (3/8 of WUPEN) Wakeup and interrupt pin WKUP1 enable Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. + @"WUPEN[2]": u1, + /// (4/8 of WUPEN) Wakeup and interrupt pin WKUP1 enable Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. + @"WUPEN[3]": u1, + /// (5/8 of WUPEN) Wakeup and interrupt pin WKUP1 enable Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. + @"WUPEN[4]": u1, + /// (6/8 of WUPEN) Wakeup and interrupt pin WKUP1 enable Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. + @"WUPEN[5]": u1, + /// (7/8 of WUPEN) Wakeup and interrupt pin WKUP1 enable Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. + @"WUPEN[6]": u1, + /// (8/8 of WUPEN) Wakeup and interrupt pin WKUP1 enable Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. + @"WUPEN[7]": u1, + padding: u24, }), /// wakeup control register 2 WUCR2: mmio.Mmio(packed struct(u32) { - /// Wakeup pin WKUP1 polarity. This bit must be configured when WUPEN1 = 0. Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. - WUPP: WUPP, - padding: u31, + /// (1/8 of WUPP) Wakeup pin WKUP1 polarity. This bit must be configured when WUPEN1 = 0. Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. + @"WUPP[0]": WUPP, + /// (2/8 of WUPP) Wakeup pin WKUP1 polarity. This bit must be configured when WUPEN1 = 0. Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. + @"WUPP[1]": WUPP, + /// (3/8 of WUPP) Wakeup pin WKUP1 polarity. This bit must be configured when WUPEN1 = 0. Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. + @"WUPP[2]": WUPP, + /// (4/8 of WUPP) Wakeup pin WKUP1 polarity. This bit must be configured when WUPEN1 = 0. Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. + @"WUPP[3]": WUPP, + /// (5/8 of WUPP) Wakeup pin WKUP1 polarity. This bit must be configured when WUPEN1 = 0. Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. + @"WUPP[4]": WUPP, + /// (6/8 of WUPP) Wakeup pin WKUP1 polarity. This bit must be configured when WUPEN1 = 0. Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. + @"WUPP[5]": WUPP, + /// (7/8 of WUPP) Wakeup pin WKUP1 polarity. This bit must be configured when WUPEN1 = 0. Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. + @"WUPP[6]": WUPP, + /// (8/8 of WUPP) Wakeup pin WKUP1 polarity. This bit must be configured when WUPEN1 = 0. Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. + @"WUPP[7]": WUPP, + padding: u24, }), /// wakeup control register 3 WUCR3: mmio.Mmio(packed struct(u32) { @@ -359108,9 +370960,23 @@ pub const types = struct { reserved48: [4]u8, /// security configuration register SECCFGR: mmio.Mmio(packed struct(u32) { - /// WUP1 secure protection - WUP1SEC: u1, - reserved12: u11, + /// (1/8 of WUP1SEC) WUP1 secure protection + @"WUP1SEC[0]": u1, + /// (2/8 of WUP1SEC) WUP1 secure protection + @"WUP1SEC[1]": u1, + /// (3/8 of WUP1SEC) WUP1 secure protection + @"WUP1SEC[2]": u1, + /// (4/8 of WUP1SEC) WUP1 secure protection + @"WUP1SEC[3]": u1, + /// (5/8 of WUP1SEC) WUP1 secure protection + @"WUP1SEC[4]": u1, + /// (6/8 of WUP1SEC) WUP1 secure protection + @"WUP1SEC[5]": u1, + /// (7/8 of WUP1SEC) WUP1 secure protection + @"WUP1SEC[6]": u1, + /// (8/8 of WUP1SEC) WUP1 secure protection + @"WUP1SEC[7]": u1, + reserved12: u4, /// Low-power modes secure protection LPMSEC: u1, /// Voltage detection secure protection @@ -359152,28 +371018,116 @@ pub const types = struct { reserved68: [4]u8, /// wakeup status register WUSR: mmio.Mmio(packed struct(u32) { - /// Wakeup and interrupt pending flag 1 This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of WUSCR or by hardware when WUPEN1 = 0. - WUF: u1, - padding: u31, + /// (1/8 of WUF) Wakeup and interrupt pending flag 1 This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of WUSCR or by hardware when WUPEN1 = 0. + @"WUF[0]": u1, + /// (2/8 of WUF) Wakeup and interrupt pending flag 1 This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of WUSCR or by hardware when WUPEN1 = 0. + @"WUF[1]": u1, + /// (3/8 of WUF) Wakeup and interrupt pending flag 1 This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of WUSCR or by hardware when WUPEN1 = 0. + @"WUF[2]": u1, + /// (4/8 of WUF) Wakeup and interrupt pending flag 1 This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of WUSCR or by hardware when WUPEN1 = 0. + @"WUF[3]": u1, + /// (5/8 of WUF) Wakeup and interrupt pending flag 1 This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of WUSCR or by hardware when WUPEN1 = 0. + @"WUF[4]": u1, + /// (6/8 of WUF) Wakeup and interrupt pending flag 1 This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of WUSCR or by hardware when WUPEN1 = 0. + @"WUF[5]": u1, + /// (7/8 of WUF) Wakeup and interrupt pending flag 1 This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of WUSCR or by hardware when WUPEN1 = 0. + @"WUF[6]": u1, + /// (8/8 of WUF) Wakeup and interrupt pending flag 1 This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of WUSCR or by hardware when WUPEN1 = 0. + @"WUF[7]": u1, + padding: u24, }), /// wakeup status clear register WUSCR: mmio.Mmio(packed struct(u32) { - /// Clear wakeup flag 1 Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. Writing 1 to this bit clears the WUF1 flag in WUSR. - CWUF: u1, - padding: u31, + /// (1/8 of CWUF) Clear wakeup flag 1 Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. Writing 1 to this bit clears the WUF1 flag in WUSR. + @"CWUF[0]": u1, + /// (2/8 of CWUF) Clear wakeup flag 1 Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. Writing 1 to this bit clears the WUF1 flag in WUSR. + @"CWUF[1]": u1, + /// (3/8 of CWUF) Clear wakeup flag 1 Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. Writing 1 to this bit clears the WUF1 flag in WUSR. + @"CWUF[2]": u1, + /// (4/8 of CWUF) Clear wakeup flag 1 Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. Writing 1 to this bit clears the WUF1 flag in WUSR. + @"CWUF[3]": u1, + /// (5/8 of CWUF) Clear wakeup flag 1 Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. Writing 1 to this bit clears the WUF1 flag in WUSR. + @"CWUF[4]": u1, + /// (6/8 of CWUF) Clear wakeup flag 1 Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. Writing 1 to this bit clears the WUF1 flag in WUSR. + @"CWUF[5]": u1, + /// (7/8 of CWUF) Clear wakeup flag 1 Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. Writing 1 to this bit clears the WUF1 flag in WUSR. + @"CWUF[6]": u1, + /// (8/8 of CWUF) Clear wakeup flag 1 Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. Writing 1 to this bit clears the WUF1 flag in WUSR. + @"CWUF[7]": u1, + padding: u24, }), reserved80: [4]u8, /// port Standby IO retention enable register IORETENR: mmio.Mmio(packed struct(u32) { - /// Port A Standby GPIO retention enable Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. When set, each bit enables the Standby GPIO retention feature for PAy - EN: u1, - padding: u31, + /// (1/16 of EN) Port A Standby GPIO retention enable Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. When set, each bit enables the Standby GPIO retention feature for PAy + @"EN[0]": u1, + /// (2/16 of EN) Port A Standby GPIO retention enable Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. When set, each bit enables the Standby GPIO retention feature for PAy + @"EN[1]": u1, + /// (3/16 of EN) Port A Standby GPIO retention enable Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. When set, each bit enables the Standby GPIO retention feature for PAy + @"EN[2]": u1, + /// (4/16 of EN) Port A Standby GPIO retention enable Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. When set, each bit enables the Standby GPIO retention feature for PAy + @"EN[3]": u1, + /// (5/16 of EN) Port A Standby GPIO retention enable Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. When set, each bit enables the Standby GPIO retention feature for PAy + @"EN[4]": u1, + /// (6/16 of EN) Port A Standby GPIO retention enable Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. When set, each bit enables the Standby GPIO retention feature for PAy + @"EN[5]": u1, + /// (7/16 of EN) Port A Standby GPIO retention enable Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. When set, each bit enables the Standby GPIO retention feature for PAy + @"EN[6]": u1, + /// (8/16 of EN) Port A Standby GPIO retention enable Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. When set, each bit enables the Standby GPIO retention feature for PAy + @"EN[7]": u1, + /// (9/16 of EN) Port A Standby GPIO retention enable Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. When set, each bit enables the Standby GPIO retention feature for PAy + @"EN[8]": u1, + /// (10/16 of EN) Port A Standby GPIO retention enable Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. When set, each bit enables the Standby GPIO retention feature for PAy + @"EN[9]": u1, + /// (11/16 of EN) Port A Standby GPIO retention enable Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. When set, each bit enables the Standby GPIO retention feature for PAy + @"EN[10]": u1, + /// (12/16 of EN) Port A Standby GPIO retention enable Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. When set, each bit enables the Standby GPIO retention feature for PAy + @"EN[11]": u1, + /// (13/16 of EN) Port A Standby GPIO retention enable Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. When set, each bit enables the Standby GPIO retention feature for PAy + @"EN[12]": u1, + /// (14/16 of EN) Port A Standby GPIO retention enable Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. When set, each bit enables the Standby GPIO retention feature for PAy + @"EN[13]": u1, + /// (15/16 of EN) Port A Standby GPIO retention enable Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. When set, each bit enables the Standby GPIO retention feature for PAy + @"EN[14]": u1, + /// (16/16 of EN) Port A Standby GPIO retention enable Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. When set, each bit enables the Standby GPIO retention feature for PAy + @"EN[15]": u1, + padding: u16, }), /// port Standby IO retention status register IORETRA: mmio.Mmio(packed struct(u32) { - /// Port A Standby GPIO retention active Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. - RET: u1, - padding: u31, + /// (1/16 of RET) Port A Standby GPIO retention active Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. + @"RET[0]": u1, + /// (2/16 of RET) Port A Standby GPIO retention active Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. + @"RET[1]": u1, + /// (3/16 of RET) Port A Standby GPIO retention active Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. + @"RET[2]": u1, + /// (4/16 of RET) Port A Standby GPIO retention active Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. + @"RET[3]": u1, + /// (5/16 of RET) Port A Standby GPIO retention active Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. + @"RET[4]": u1, + /// (6/16 of RET) Port A Standby GPIO retention active Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. + @"RET[5]": u1, + /// (7/16 of RET) Port A Standby GPIO retention active Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. + @"RET[6]": u1, + /// (8/16 of RET) Port A Standby GPIO retention active Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. + @"RET[7]": u1, + /// (9/16 of RET) Port A Standby GPIO retention active Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. + @"RET[8]": u1, + /// (10/16 of RET) Port A Standby GPIO retention active Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. + @"RET[9]": u1, + /// (11/16 of RET) Port A Standby GPIO retention active Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. + @"RET[10]": u1, + /// (12/16 of RET) Port A Standby GPIO retention active Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. + @"RET[11]": u1, + /// (13/16 of RET) Port A Standby GPIO retention active Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. + @"RET[12]": u1, + /// (14/16 of RET) Port A Standby GPIO retention active Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. + @"RET[13]": u1, + /// (15/16 of RET) Port A Standby GPIO retention active Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. + @"RET[14]": u1, + /// (16/16 of RET) Port A Standby GPIO retention active Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV. + @"RET[15]": u1, + padding: u16, }), reserved256: [168]u8, /// 2.4 GHz RADIO status and control register @@ -359321,9 +371275,13 @@ pub const types = struct { }), /// Power control register 3 CR3: mmio.Mmio(packed struct(u32) { - /// Enable Wakeup pin WKUP1 for CPU1 - EWUP: u1, - reserved7: u6, + /// (1/3 of EWUP) Enable Wakeup pin WKUP1 for CPU1 + @"EWUP[0]": u1, + /// (2/3 of EWUP) Enable Wakeup pin WKUP1 for CPU1 + @"EWUP[1]": u1, + /// (3/3 of EWUP) Enable Wakeup pin WKUP1 for CPU1 + @"EWUP[2]": u1, + reserved7: u4, /// Ultra-low-power enable EULPEN: u1, /// Enable wakeup PVD for CPU1 @@ -359345,9 +371303,13 @@ pub const types = struct { }), /// Power control register 4 CR4: mmio.Mmio(packed struct(u32) { - /// Wakeup pin WKUP1 polarity - WP: WP, - reserved8: u7, + /// (1/3 of WP) Wakeup pin WKUP1 polarity + @"WP[0]": WP, + /// (2/3 of WP) Wakeup pin WKUP1 polarity + @"WP[1]": WP, + /// (3/3 of WP) Wakeup pin WKUP1 polarity + @"WP[2]": WP, + reserved8: u5, /// VBAT battery charging enable VBE: u1, /// VBAT battery charging resistor selection @@ -359362,9 +371324,13 @@ pub const types = struct { }), /// Power status register 1 SR1: mmio.Mmio(packed struct(u32) { - /// Wakeup flag 1 - WUF: u1, - reserved8: u7, + /// (1/3 of WUF) Wakeup flag 1 + @"WUF[0]": u1, + /// (2/3 of WUF) Wakeup flag 1 + @"WUF[1]": u1, + /// (3/3 of WUF) Wakeup flag 1 + @"WUF[2]": u1, + reserved8: u5, /// Wakeup PVD flag WPVDF: u1, reserved11: u2, @@ -359410,9 +371376,13 @@ pub const types = struct { }), /// Power status clear register SCR: mmio.Mmio(packed struct(u32) { - /// Clear wakeup flag 1 - CWUF: u1, - reserved8: u7, + /// (1/3 of CWUF) Clear wakeup flag 1 + @"CWUF[0]": u1, + /// (2/3 of CWUF) Clear wakeup flag 1 + @"CWUF[1]": u1, + /// (3/3 of CWUF) Clear wakeup flag 1 + @"CWUF[2]": u1, + reserved8: u5, /// Clear wakeup PVD interrupt flag CWPVDF: u1, reserved11: u2, @@ -359434,15 +371404,75 @@ pub const types = struct { }), /// Power Port pull-up control register PUCR: mmio.Mmio(packed struct(u32) { - /// Port pull bit y (y=0..15) - P: u1, - padding: u31, + /// (1/16 of P) Port pull bit y (y=0..15) + @"P[0]": u1, + /// (2/16 of P) Port pull bit y (y=0..15) + @"P[1]": u1, + /// (3/16 of P) Port pull bit y (y=0..15) + @"P[2]": u1, + /// (4/16 of P) Port pull bit y (y=0..15) + @"P[3]": u1, + /// (5/16 of P) Port pull bit y (y=0..15) + @"P[4]": u1, + /// (6/16 of P) Port pull bit y (y=0..15) + @"P[5]": u1, + /// (7/16 of P) Port pull bit y (y=0..15) + @"P[6]": u1, + /// (8/16 of P) Port pull bit y (y=0..15) + @"P[7]": u1, + /// (9/16 of P) Port pull bit y (y=0..15) + @"P[8]": u1, + /// (10/16 of P) Port pull bit y (y=0..15) + @"P[9]": u1, + /// (11/16 of P) Port pull bit y (y=0..15) + @"P[10]": u1, + /// (12/16 of P) Port pull bit y (y=0..15) + @"P[11]": u1, + /// (13/16 of P) Port pull bit y (y=0..15) + @"P[12]": u1, + /// (14/16 of P) Port pull bit y (y=0..15) + @"P[13]": u1, + /// (15/16 of P) Port pull bit y (y=0..15) + @"P[14]": u1, + /// (16/16 of P) Port pull bit y (y=0..15) + @"P[15]": u1, + padding: u16, }), /// Power Port pull-down control register PDCR: mmio.Mmio(packed struct(u32) { - /// Port pull bit y (y=0..15) - P: u1, - padding: u31, + /// (1/16 of P) Port pull bit y (y=0..15) + @"P[0]": u1, + /// (2/16 of P) Port pull bit y (y=0..15) + @"P[1]": u1, + /// (3/16 of P) Port pull bit y (y=0..15) + @"P[2]": u1, + /// (4/16 of P) Port pull bit y (y=0..15) + @"P[3]": u1, + /// (5/16 of P) Port pull bit y (y=0..15) + @"P[4]": u1, + /// (6/16 of P) Port pull bit y (y=0..15) + @"P[5]": u1, + /// (7/16 of P) Port pull bit y (y=0..15) + @"P[6]": u1, + /// (8/16 of P) Port pull bit y (y=0..15) + @"P[7]": u1, + /// (9/16 of P) Port pull bit y (y=0..15) + @"P[8]": u1, + /// (10/16 of P) Port pull bit y (y=0..15) + @"P[9]": u1, + /// (11/16 of P) Port pull bit y (y=0..15) + @"P[10]": u1, + /// (12/16 of P) Port pull bit y (y=0..15) + @"P[11]": u1, + /// (13/16 of P) Port pull bit y (y=0..15) + @"P[12]": u1, + /// (14/16 of P) Port pull bit y (y=0..15) + @"P[13]": u1, + /// (15/16 of P) Port pull bit y (y=0..15) + @"P[14]": u1, + /// (16/16 of P) Port pull bit y (y=0..15) + @"P[15]": u1, + padding: u16, }), reserved128: [88]u8, /// Power CPU2 control register 1 [dual core device only] @@ -359458,9 +371488,13 @@ pub const types = struct { }), /// Power CPU2 control register 3 [dual core device only] C2CR3: mmio.Mmio(packed struct(u32) { - /// Enable Wakeup pin WKUP1 for CPU2 - EWUP: u1, - reserved8: u7, + /// (1/3 of EWUP) Enable Wakeup pin WKUP1 for CPU2 + @"EWUP[0]": u1, + /// (2/3 of EWUP) Enable Wakeup pin WKUP1 for CPU2 + @"EWUP[1]": u1, + /// (3/3 of EWUP) Enable Wakeup pin WKUP1 for CPU2 + @"EWUP[2]": u1, + reserved8: u5, /// Enable wakeup PVD for CPU2 EWPVD: u1, reserved10: u1, @@ -368090,6 +380124,7 @@ pub const types = struct { PPRE2: PPRE, /// ADC prescaler ADCPRE: ADCPRE, + // skipped overlapping field PLLSRC at offset 15 bits reserved17: u1, /// HSE divider for PLL entry. Note: This bit is the same as the LSB of PREDIV in CFGR2, for compatibility with other STM32 products. PLLXTPRE: PLLXTPRE, @@ -376779,11 +388814,19 @@ pub const types = struct { /// external high speed clock type in Bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the HSEON bit to be used by the device. The HSEEXT bit can be written only if the HSE oscillator is disabled. HSEEXT: HSEEXT, reserved24: u3, - /// PLL1 enable Set and cleared by software to enable PLL1. Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock. - PLLON: u1, - /// PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked. - PLLRDY: u1, - padding: u6, + /// (1/3 of PLLON) PLL1 enable Set and cleared by software to enable PLL1. Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock. + @"PLLON[0]": u1, + /// (1/3 of PLLRDY) PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked. + @"PLLRDY[0]": u1, + /// (2/3 of PLLON) PLL1 enable Set and cleared by software to enable PLL1. Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock. + @"PLLON[1]": u1, + /// (2/3 of PLLRDY) PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked. + @"PLLRDY[1]": u1, + /// (3/3 of PLLON) PLL1 enable Set and cleared by software to enable PLL1. Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock. + @"PLLON[2]": u1, + /// (3/3 of PLLRDY) PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked. + @"PLLRDY[2]": u1, + padding: u2, }), reserved16: [12]u8, /// RCC HSI calibration register @@ -376921,9 +388964,13 @@ pub const types = struct { HSERDYIE: u1, /// HSI48 ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI48 oscillator stabilization. HSI48RDYIE: u1, - /// PLL1 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL1 lock. - PLLRDYIE: u1, - padding: u25, + /// (1/3 of PLLRDYIE) PLL1 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL1 lock. + @"PLLRDYIE[0]": u1, + /// (2/3 of PLLRDYIE) PLL1 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL1 lock. + @"PLLRDYIE[1]": u1, + /// (3/3 of PLLRDYIE) PLL1 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL1 lock. + @"PLLRDYIE[2]": u1, + padding: u23, }), /// RCC clock source interrupt flag register CIFR: mmio.Mmio(packed struct(u32) { @@ -376939,9 +388986,13 @@ pub const types = struct { HSERDYF: u1, /// HSI48 ready interrupt flag Reset by software by writing HSI48RDYC bit. Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set. HSI48RDYF: u1, - /// PLL1 ready interrupt flag Reset by software by writing PLL1RDYC bit. Set by hardware when the PLL1 locks and PLL1RDYIE is set. - PLLRDYF: u1, - reserved10: u3, + /// (1/3 of PLLRDYF) PLL1 ready interrupt flag Reset by software by writing PLL1RDYC bit. Set by hardware when the PLL1 locks and PLL1RDYIE is set. + @"PLLRDYF[0]": u1, + /// (2/3 of PLLRDYF) PLL1 ready interrupt flag Reset by software by writing PLL1RDYC bit. Set by hardware when the PLL1 locks and PLL1RDYIE is set. + @"PLLRDYF[1]": u1, + /// (3/3 of PLLRDYF) PLL1 ready interrupt flag Reset by software by writing PLL1RDYC bit. Set by hardware when the PLL1 locks and PLL1RDYIE is set. + @"PLLRDYF[2]": u1, + reserved10: u1, /// HSE clock security system interrupt flag Reset by software by writing HSECSSC bit. Set by hardware in case of HSE clock failure. HSECSSF: u1, padding: u21, @@ -376960,9 +389011,13 @@ pub const types = struct { HSERDYC: u1, /// HSI48 ready interrupt clear Set by software to clear HSI48RDYF. Reset by hardware when clear done. HSI48RDYC: u1, - /// PLL1 ready interrupt clear Set by software to clear PLL1RDYF. Reset by hardware when clear done. - PLLRDYC: u1, - reserved10: u3, + /// (1/3 of PLLRDYC) PLL1 ready interrupt clear Set by software to clear PLL1RDYF. Reset by hardware when clear done. + @"PLLRDYC[0]": u1, + /// (2/3 of PLLRDYC) PLL1 ready interrupt clear Set by software to clear PLL1RDYF. Reset by hardware when clear done. + @"PLLRDYC[1]": u1, + /// (3/3 of PLLRDYC) PLL1 ready interrupt clear Set by software to clear PLL1RDYF. Reset by hardware when clear done. + @"PLLRDYC[2]": u1, + reserved10: u1, /// HSE clock security system interrupt clear Set by software to clear HSECSSF. Reset by hardware when clear done. HSECSSC: u1, padding: u21, @@ -377873,9 +389928,13 @@ pub const types = struct { SYSCLKSEC: u1, /// AHBx/APBx prescaler configuration bits security Set and reset by software. PRESCSEC: u1, - /// PLL1 clock configuration and status bits security Set and reset by software. - PLLSEC: u1, - reserved11: u3, + /// (1/3 of PLLSEC) PLL1 clock configuration and status bits security Set and reset by software. + @"PLLSEC[0]": u1, + /// (2/3 of PLLSEC) PLL1 clock configuration and status bits security Set and reset by software. + @"PLLSEC[1]": u1, + /// (3/3 of PLLSEC) PLL1 clock configuration and status bits security Set and reset by software. + @"PLLSEC[2]": u1, + reserved11: u1, /// HSI48 clock configuration and status bits security Set and reset by software. HSI48SEC: u1, /// Remove reset flag security Set and reset by software. @@ -379044,11 +391103,15 @@ pub const types = struct { /// external high speed clock type in Bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the HSEON bit to be used by the device. The HSEEXT bit can be written only if the HSE oscillator is disabled. HSEEXT: HSEEXT, reserved24: u3, - /// PLL1 enable Set and cleared by software to enable PLL1. Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock. - PLLON: u1, - /// PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked. - PLLRDY: u1, - padding: u6, + /// (1/2 of PLLON) PLL1 enable Set and cleared by software to enable PLL1. Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock. + @"PLLON[0]": u1, + /// (1/2 of PLLRDY) PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked. + @"PLLRDY[0]": u1, + /// (2/2 of PLLON) PLL1 enable Set and cleared by software to enable PLL1. Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock. + @"PLLON[1]": u1, + /// (2/2 of PLLRDY) PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked. + @"PLLRDY[1]": u1, + padding: u4, }), reserved16: [12]u8, /// RCC HSI calibration register @@ -379187,9 +391250,11 @@ pub const types = struct { HSERDYIE: u1, /// HSI48 ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI48 oscillator stabilization. HSI48RDYIE: u1, - /// PLL1 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL1 lock. - PLLRDYIE: u1, - padding: u25, + /// (1/2 of PLLRDYIE) PLL1 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL1 lock. + @"PLLRDYIE[0]": u1, + /// (2/2 of PLLRDYIE) PLL1 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL1 lock. + @"PLLRDYIE[1]": u1, + padding: u24, }), /// RCC clock source interrupt flag register CIFR: mmio.Mmio(packed struct(u32) { @@ -379205,9 +391270,11 @@ pub const types = struct { HSERDYF: u1, /// HSI48 ready interrupt flag Reset by software by writing HSI48RDYC bit. Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set. HSI48RDYF: u1, - /// PLL1 ready interrupt flag Reset by software by writing PLL1RDYC bit. Set by hardware when the PLL1 locks and PLL1RDYIE is set. - PLLRDYF: u1, - reserved10: u3, + /// (1/2 of PLLRDYF) PLL1 ready interrupt flag Reset by software by writing PLL1RDYC bit. Set by hardware when the PLL1 locks and PLL1RDYIE is set. + @"PLLRDYF[0]": u1, + /// (2/2 of PLLRDYF) PLL1 ready interrupt flag Reset by software by writing PLL1RDYC bit. Set by hardware when the PLL1 locks and PLL1RDYIE is set. + @"PLLRDYF[1]": u1, + reserved10: u2, /// HSE clock security system interrupt flag Reset by software by writing HSECSSC bit. Set by hardware in case of HSE clock failure. HSECSSF: u1, padding: u21, @@ -379226,9 +391293,11 @@ pub const types = struct { HSERDYC: u1, /// HSI48 ready interrupt clear Set by software to clear HSI48RDYF. Reset by hardware when clear done. HSI48RDYC: u1, - /// PLL1 ready interrupt clear Set by software to clear PLL1RDYF. Reset by hardware when clear done. - PLLRDYC: u1, - reserved10: u3, + /// (1/2 of PLLRDYC) PLL1 ready interrupt clear Set by software to clear PLL1RDYF. Reset by hardware when clear done. + @"PLLRDYC[0]": u1, + /// (2/2 of PLLRDYC) PLL1 ready interrupt clear Set by software to clear PLL1RDYF. Reset by hardware when clear done. + @"PLLRDYC[1]": u1, + reserved10: u2, /// HSE clock security system interrupt clear Set by software to clear HSECSSF. Reset by hardware when clear done. HSECSSC: u1, padding: u21, @@ -380982,11 +393051,19 @@ pub const types = struct { /// HSE Clock Security System enable HSECSSON: u1, reserved24: u4, - /// PLL1 enable - PLLON: u1, - /// PLL1 clock ready flag - PLLRDY: u1, - padding: u6, + /// (1/3 of PLLON) PLL1 enable + @"PLLON[0]": u1, + /// (1/3 of PLLRDY) PLL1 clock ready flag + @"PLLRDY[0]": u1, + /// (2/3 of PLLON) PLL1 enable + @"PLLON[1]": u1, + /// (2/3 of PLLRDY) PLL1 clock ready flag + @"PLLRDY[1]": u1, + /// (3/3 of PLLON) PLL1 enable + @"PLLON[2]": u1, + /// (3/3 of PLLRDY) PLL1 clock ready flag + @"PLLRDY[2]": u1, + padding: u2, }), /// RCC HSI configuration register HSICFGR: mmio.Mmio(packed struct(u32) { @@ -381073,26 +393150,56 @@ pub const types = struct { /// DIVMx and PLLs clock source selection PLLSRC: PLLSRC, reserved4: u2, - /// Prescaler for PLL1 - DIVM: PLLM, - padding: u22, + /// (1/3 of DIVM) Prescaler for PLL1 + @"DIVM[0]": PLLM, + reserved12: u2, + /// (2/3 of DIVM) Prescaler for PLL1 + @"DIVM[1]": PLLM, + reserved20: u2, + /// (3/3 of DIVM) Prescaler for PLL1 + @"DIVM[2]": PLLM, + padding: u6, }), /// RCC PLLs Configuration Register PLLCFGR: mmio.Mmio(packed struct(u32) { - /// PLL1 fractional latch enable - PLLFRACEN: u1, - /// PLL1 VCO selection - PLLVCOSEL: PLLVCOSEL, - /// PLL1 input frequency range - PLLRGE: PLLRGE, - reserved16: u12, - /// PLL1 DIVP divider output enable - DIVPEN: u1, - /// PLL1 DIVQ divider output enable - DIVQEN: u1, - /// PLL1 DIVR divider output enable - DIVREN: u1, - padding: u13, + /// (1/3 of PLLFRACEN) PLL1 fractional latch enable + @"PLLFRACEN[0]": u1, + /// (1/3 of PLLVCOSEL) PLL1 VCO selection + @"PLLVCOSEL[0]": PLLVCOSEL, + /// (1/3 of PLLRGE) PLL1 input frequency range + @"PLLRGE[0]": PLLRGE, + /// (2/3 of PLLFRACEN) PLL1 fractional latch enable + @"PLLFRACEN[1]": u1, + /// (2/3 of PLLVCOSEL) PLL1 VCO selection + @"PLLVCOSEL[1]": PLLVCOSEL, + /// (2/3 of PLLRGE) PLL1 input frequency range + @"PLLRGE[1]": PLLRGE, + /// (3/3 of PLLFRACEN) PLL1 fractional latch enable + @"PLLFRACEN[2]": u1, + /// (3/3 of PLLVCOSEL) PLL1 VCO selection + @"PLLVCOSEL[2]": PLLVCOSEL, + /// (3/3 of PLLRGE) PLL1 input frequency range + @"PLLRGE[2]": PLLRGE, + reserved16: u4, + /// (1/3 of DIVPEN) PLL1 DIVP divider output enable + @"DIVPEN[0]": u1, + /// (1/3 of DIVQEN) PLL1 DIVQ divider output enable + @"DIVQEN[0]": u1, + /// (1/3 of DIVREN) PLL1 DIVR divider output enable + @"DIVREN[0]": u1, + /// (2/3 of DIVPEN) PLL1 DIVP divider output enable + @"DIVPEN[1]": u1, + /// (2/3 of DIVQEN) PLL1 DIVQ divider output enable + @"DIVQEN[1]": u1, + /// (2/3 of DIVREN) PLL1 DIVR divider output enable + @"DIVREN[1]": u1, + /// (3/3 of DIVPEN) PLL1 DIVP divider output enable + @"DIVPEN[2]": u1, + /// (3/3 of DIVQEN) PLL1 DIVQ divider output enable + @"DIVQEN[2]": u1, + /// (3/3 of DIVREN) PLL1 DIVR divider output enable + @"DIVREN[2]": u1, + padding: u7, }), /// RCC PLL1 Dividers Configuration Register PLLDIVR: mmio.Mmio(packed struct(u32) { @@ -381220,9 +393327,12 @@ pub const types = struct { CSIRDYIE: u1, /// RC48 ready Interrupt Enable HSI48RDYIE: u1, - /// PLL1 ready Interrupt Enable - PLLRDYIE: u1, - reserved9: u2, + /// (1/3 of PLLRDYIE) PLL1 ready Interrupt Enable + @"PLLRDYIE[0]": u1, + /// (2/3 of PLLRDYIE) PLL1 ready Interrupt Enable + @"PLLRDYIE[1]": u1, + /// (3/3 of PLLRDYIE) PLL1 ready Interrupt Enable + @"PLLRDYIE[2]": u1, /// LSE clock security system Interrupt Enable LSECSSIE: u1, padding: u22, @@ -381241,9 +393351,12 @@ pub const types = struct { CSIRDY: u1, /// RC48 ready Interrupt Flag HSI48RDYF: u1, - /// PLL1 ready Interrupt Flag - PLLRDYF: u1, - reserved9: u2, + /// (1/3 of PLLRDYF) PLL1 ready Interrupt Flag + @"PLLRDYF[0]": u1, + /// (2/3 of PLLRDYF) PLL1 ready Interrupt Flag + @"PLLRDYF[1]": u1, + /// (3/3 of PLLRDYF) PLL1 ready Interrupt Flag + @"PLLRDYF[2]": u1, /// LSE clock security system Interrupt Flag LSECSSF: u1, /// HSE clock security system Interrupt Flag @@ -381264,9 +393377,12 @@ pub const types = struct { HSE_ready_Interrupt_Clear: u1, /// RC48 ready Interrupt Clear HSI48RDYC: u1, - /// PLL1 ready Interrupt Clear - PLLRDYC: u1, - reserved9: u2, + /// (1/3 of PLLRDYC) PLL1 ready Interrupt Clear + @"PLLRDYC[0]": u1, + /// (2/3 of PLLRDYC) PLL1 ready Interrupt Clear + @"PLLRDYC[1]": u1, + /// (3/3 of PLLRDYC) PLL1 ready Interrupt Clear + @"PLLRDYC[2]": u1, /// LSE clock security system Interrupt Clear LSECSSC: u1, /// HSE clock security system Interrupt Clear @@ -384140,11 +396256,19 @@ pub const types = struct { /// HSE Clock Security System enable HSECSSON: u1, reserved24: u4, - /// PLL1 enable - PLLON: u1, - /// PLL1 clock ready flag - PLLRDY: u1, - padding: u6, + /// (1/3 of PLLON) PLL1 enable + @"PLLON[0]": u1, + /// (1/3 of PLLRDY) PLL1 clock ready flag + @"PLLRDY[0]": u1, + /// (2/3 of PLLON) PLL1 enable + @"PLLON[1]": u1, + /// (2/3 of PLLRDY) PLL1 clock ready flag + @"PLLRDY[1]": u1, + /// (3/3 of PLLON) PLL1 enable + @"PLLON[2]": u1, + /// (3/3 of PLLRDY) PLL1 clock ready flag + @"PLLRDY[2]": u1, + padding: u2, }), /// RCC HSI configuration register HSICFGR: mmio.Mmio(packed struct(u32) { @@ -384231,26 +396355,56 @@ pub const types = struct { /// DIVMx and PLLs clock source selection PLLSRC: PLLSRC, reserved4: u2, - /// Prescaler for PLL1 - DIVM: PLLM, - padding: u22, + /// (1/3 of DIVM) Prescaler for PLL1 + @"DIVM[0]": PLLM, + reserved12: u2, + /// (2/3 of DIVM) Prescaler for PLL1 + @"DIVM[1]": PLLM, + reserved20: u2, + /// (3/3 of DIVM) Prescaler for PLL1 + @"DIVM[2]": PLLM, + padding: u6, }), /// RCC PLLs Configuration Register PLLCFGR: mmio.Mmio(packed struct(u32) { - /// PLL1 fractional latch enable - PLLFRACEN: u1, - /// PLL1 VCO selection - PLLVCOSEL: PLLVCOSEL, - /// PLL1 input frequency range - PLLRGE: PLLRGE, - reserved16: u12, - /// PLL1 DIVP divider output enable - DIVPEN: u1, - /// PLL1 DIVQ divider output enable - DIVQEN: u1, - /// PLL1 DIVR divider output enable - DIVREN: u1, - padding: u13, + /// (1/3 of PLLFRACEN) PLL1 fractional latch enable + @"PLLFRACEN[0]": u1, + /// (1/3 of PLLVCOSEL) PLL1 VCO selection + @"PLLVCOSEL[0]": PLLVCOSEL, + /// (1/3 of PLLRGE) PLL1 input frequency range + @"PLLRGE[0]": PLLRGE, + /// (2/3 of PLLFRACEN) PLL1 fractional latch enable + @"PLLFRACEN[1]": u1, + /// (2/3 of PLLVCOSEL) PLL1 VCO selection + @"PLLVCOSEL[1]": PLLVCOSEL, + /// (2/3 of PLLRGE) PLL1 input frequency range + @"PLLRGE[1]": PLLRGE, + /// (3/3 of PLLFRACEN) PLL1 fractional latch enable + @"PLLFRACEN[2]": u1, + /// (3/3 of PLLVCOSEL) PLL1 VCO selection + @"PLLVCOSEL[2]": PLLVCOSEL, + /// (3/3 of PLLRGE) PLL1 input frequency range + @"PLLRGE[2]": PLLRGE, + reserved16: u4, + /// (1/3 of DIVPEN) PLL1 DIVP divider output enable + @"DIVPEN[0]": u1, + /// (1/3 of DIVQEN) PLL1 DIVQ divider output enable + @"DIVQEN[0]": u1, + /// (1/3 of DIVREN) PLL1 DIVR divider output enable + @"DIVREN[0]": u1, + /// (2/3 of DIVPEN) PLL1 DIVP divider output enable + @"DIVPEN[1]": u1, + /// (2/3 of DIVQEN) PLL1 DIVQ divider output enable + @"DIVQEN[1]": u1, + /// (2/3 of DIVREN) PLL1 DIVR divider output enable + @"DIVREN[1]": u1, + /// (3/3 of DIVPEN) PLL1 DIVP divider output enable + @"DIVPEN[2]": u1, + /// (3/3 of DIVQEN) PLL1 DIVQ divider output enable + @"DIVQEN[2]": u1, + /// (3/3 of DIVREN) PLL1 DIVR divider output enable + @"DIVREN[2]": u1, + padding: u7, }), /// RCC PLL1 Dividers Configuration Register PLLDIVR: mmio.Mmio(packed struct(u32) { @@ -384372,9 +396526,12 @@ pub const types = struct { CSIRDYIE: u1, /// RC48 ready Interrupt Enable HSI48RDYIE: u1, - /// PLL1 ready Interrupt Enable - PLLRDYIE: u1, - reserved9: u2, + /// (1/3 of PLLRDYIE) PLL1 ready Interrupt Enable + @"PLLRDYIE[0]": u1, + /// (2/3 of PLLRDYIE) PLL1 ready Interrupt Enable + @"PLLRDYIE[1]": u1, + /// (3/3 of PLLRDYIE) PLL1 ready Interrupt Enable + @"PLLRDYIE[2]": u1, /// LSE clock security system Interrupt Enable LSECSSIE: u1, padding: u22, @@ -384393,9 +396550,12 @@ pub const types = struct { CSIRDYF: u1, /// RC48 ready Interrupt Flag HSI48RDYF: u1, - /// PLL1 ready Interrupt Flag - PLLRDYF: u1, - reserved9: u2, + /// (1/3 of PLLRDYF) PLL1 ready Interrupt Flag + @"PLLRDYF[0]": u1, + /// (2/3 of PLLRDYF) PLL1 ready Interrupt Flag + @"PLLRDYF[1]": u1, + /// (3/3 of PLLRDYF) PLL1 ready Interrupt Flag + @"PLLRDYF[2]": u1, /// LSE clock security system Interrupt Flag LSECSSF: u1, /// HSE clock security system Interrupt Flag @@ -384416,9 +396576,12 @@ pub const types = struct { HSE_ready_Interrupt_Clear: u1, /// RC48 ready Interrupt Clear HSI48RDYC: u1, - /// PLL1 ready Interrupt Clear - PLLRDYC: u1, - reserved9: u2, + /// (1/3 of PLLRDYC) PLL1 ready Interrupt Clear + @"PLLRDYC[0]": u1, + /// (2/3 of PLLRDYC) PLL1 ready Interrupt Clear + @"PLLRDYC[1]": u1, + /// (3/3 of PLLRDYC) PLL1 ready Interrupt Clear + @"PLLRDYC[2]": u1, /// LSE clock security system Interrupt Clear LSECSSC: u1, /// HSE clock security system Interrupt Clear @@ -386674,11 +398837,19 @@ pub const types = struct { /// HSE Clock Security System enable HSECSSON: u1, reserved24: u4, - /// PLL1 enable - PLLON: u1, - /// PLL1 clock ready flag - PLLRDY: u1, - padding: u6, + /// (1/3 of PLLON) PLL1 enable + @"PLLON[0]": u1, + /// (1/3 of PLLRDY) PLL1 clock ready flag + @"PLLRDY[0]": u1, + /// (2/3 of PLLON) PLL1 enable + @"PLLON[1]": u1, + /// (2/3 of PLLRDY) PLL1 clock ready flag + @"PLLRDY[1]": u1, + /// (3/3 of PLLON) PLL1 enable + @"PLLON[2]": u1, + /// (3/3 of PLLRDY) PLL1 clock ready flag + @"PLLRDY[2]": u1, + padding: u2, }), /// RCC HSI configuration register HSICFGR: mmio.Mmio(packed struct(u32) { @@ -386765,26 +398936,56 @@ pub const types = struct { /// DIVMx and PLLs clock source selection PLLSRC: PLLSRC, reserved4: u2, - /// Prescaler for PLLx - DIVM: PLLM, - padding: u22, + /// (1/3 of DIVM) Prescaler for PLLx + @"DIVM[0]": PLLM, + reserved12: u2, + /// (2/3 of DIVM) Prescaler for PLLx + @"DIVM[1]": PLLM, + reserved20: u2, + /// (3/3 of DIVM) Prescaler for PLLx + @"DIVM[2]": PLLM, + padding: u6, }), /// RCC PLLs Configuration Register PLLCFGR: mmio.Mmio(packed struct(u32) { - /// PLL1 fractional latch enable - PLLFRACEN: u1, - /// PLL1 VCO selection - PLLVCOSEL: PLLVCOSEL, - /// PLL1 input frequency range - PLLRGE: PLLRGE, - reserved16: u12, - /// PLL1 DIVP divider output enable - DIVPEN: u1, - /// PLL1 DIVQ divider output enable - DIVQEN: u1, - /// PLL1 DIVR divider output enable - DIVREN: u1, - padding: u13, + /// (1/3 of PLLFRACEN) PLL1 fractional latch enable + @"PLLFRACEN[0]": u1, + /// (1/3 of PLLVCOSEL) PLL1 VCO selection + @"PLLVCOSEL[0]": PLLVCOSEL, + /// (1/3 of PLLRGE) PLL1 input frequency range + @"PLLRGE[0]": PLLRGE, + /// (2/3 of PLLFRACEN) PLL1 fractional latch enable + @"PLLFRACEN[1]": u1, + /// (2/3 of PLLVCOSEL) PLL1 VCO selection + @"PLLVCOSEL[1]": PLLVCOSEL, + /// (2/3 of PLLRGE) PLL1 input frequency range + @"PLLRGE[1]": PLLRGE, + /// (3/3 of PLLFRACEN) PLL1 fractional latch enable + @"PLLFRACEN[2]": u1, + /// (3/3 of PLLVCOSEL) PLL1 VCO selection + @"PLLVCOSEL[2]": PLLVCOSEL, + /// (3/3 of PLLRGE) PLL1 input frequency range + @"PLLRGE[2]": PLLRGE, + reserved16: u4, + /// (1/3 of DIVPEN) PLL1 DIVP divider output enable + @"DIVPEN[0]": u1, + /// (1/3 of DIVQEN) PLL1 DIVQ divider output enable + @"DIVQEN[0]": u1, + /// (1/3 of DIVREN) PLL1 DIVR divider output enable + @"DIVREN[0]": u1, + /// (2/3 of DIVPEN) PLL1 DIVP divider output enable + @"DIVPEN[1]": u1, + /// (2/3 of DIVQEN) PLL1 DIVQ divider output enable + @"DIVQEN[1]": u1, + /// (2/3 of DIVREN) PLL1 DIVR divider output enable + @"DIVREN[1]": u1, + /// (3/3 of DIVPEN) PLL1 DIVP divider output enable + @"DIVPEN[2]": u1, + /// (3/3 of DIVQEN) PLL1 DIVQ divider output enable + @"DIVQEN[2]": u1, + /// (3/3 of DIVREN) PLL1 DIVR divider output enable + @"DIVREN[2]": u1, + padding: u7, }), /// RCC PLL1 Dividers Configuration Register PLLDIVR: mmio.Mmio(packed struct(u32) { @@ -386909,9 +399110,12 @@ pub const types = struct { CSIRDYIE: u1, /// RC48 ready Interrupt Enable HSI48RDYIE: u1, - /// PLL1 ready Interrupt Enable - PLLRDYIE: u1, - reserved9: u2, + /// (1/3 of PLLRDYIE) PLL1 ready Interrupt Enable + @"PLLRDYIE[0]": u1, + /// (2/3 of PLLRDYIE) PLL1 ready Interrupt Enable + @"PLLRDYIE[1]": u1, + /// (3/3 of PLLRDYIE) PLL1 ready Interrupt Enable + @"PLLRDYIE[2]": u1, /// LSE clock security system Interrupt Enable LSECSSIE: u1, padding: u22, @@ -386930,9 +399134,12 @@ pub const types = struct { CSIRDY: u1, /// RC48 ready Interrupt Flag HSI48RDYF: u1, - /// PLL1 ready Interrupt Flag - PLLRDYF: u1, - reserved9: u2, + /// (1/3 of PLLRDYF) PLL1 ready Interrupt Flag + @"PLLRDYF[0]": u1, + /// (2/3 of PLLRDYF) PLL1 ready Interrupt Flag + @"PLLRDYF[1]": u1, + /// (3/3 of PLLRDYF) PLL1 ready Interrupt Flag + @"PLLRDYF[2]": u1, /// LSE clock security system Interrupt Flag LSECSSF: u1, /// HSE clock security system Interrupt Flag @@ -386953,9 +399160,12 @@ pub const types = struct { HSE_ready_Interrupt_Clear: u1, /// RC48 ready Interrupt Clear HSI48RDYC: u1, - /// PLL1 ready Interrupt Clear - PLLRDYC: u1, - reserved9: u2, + /// (1/3 of PLLRDYC) PLL1 ready Interrupt Clear + @"PLLRDYC[0]": u1, + /// (2/3 of PLLRDYC) PLL1 ready Interrupt Clear + @"PLLRDYC[1]": u1, + /// (3/3 of PLLRDYC) PLL1 ready Interrupt Clear + @"PLLRDYC[2]": u1, /// LSE clock security system Interrupt Clear LSECSSC: u1, /// HSE clock security system Interrupt Clear @@ -389843,11 +402053,19 @@ pub const types = struct { /// HSE clock security system enable Set by software to enable clock security system on HSE. This bit is set only (disabled by a system reset or when the system enters in Standby mode). When HSECSSON is set, the clock detector is enabled by hardware when the HSE is ready and disabled by hardware if an oscillator failure is detected. HSECSSON: u1, reserved24: u3, - /// PLL1 enable Set and cleared by software to enable PLL1. Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock (SW=3) or if FMCCKP = 1, or if XSPICKP = 1. - PLLON: u1, - /// PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked. - PLLRDY: u1, - padding: u6, + /// (1/3 of PLLON) PLL1 enable Set and cleared by software to enable PLL1. Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock (SW=3) or if FMCCKP = 1, or if XSPICKP = 1. + @"PLLON[0]": u1, + /// (1/3 of PLLRDY) PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked. + @"PLLRDY[0]": u1, + /// (2/3 of PLLON) PLL1 enable Set and cleared by software to enable PLL1. Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock (SW=3) or if FMCCKP = 1, or if XSPICKP = 1. + @"PLLON[1]": u1, + /// (2/3 of PLLRDY) PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked. + @"PLLRDY[1]": u1, + /// (3/3 of PLLON) PLL1 enable Set and cleared by software to enable PLL1. Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock (SW=3) or if FMCCKP = 1, or if XSPICKP = 1. + @"PLLON[2]": u1, + /// (3/3 of PLLRDY) PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked. + @"PLLRDY[2]": u1, + padding: u2, }), /// RCC HSI calibration register. HSICFGR: mmio.Mmio(packed struct(u32) { @@ -389932,31 +402150,74 @@ pub const types = struct { /// DIVMx and PLLs clock source selection Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled. In order to save power, when no PLL is used, PLLSRC must be set to 11. PLLSRC: PLLSRC, reserved4: u2, - /// prescaler for PLL1 Set and cleared by software to configure the prescaler of the PLL1. The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1). In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0. ... ... - DIVM: PLLM, - padding: u22, + /// (1/3 of DIVM) prescaler for PLL1 Set and cleared by software to configure the prescaler of the PLL1. The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1). In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0. ... ... + @"DIVM[0]": PLLM, + reserved12: u2, + /// (2/3 of DIVM) prescaler for PLL1 Set and cleared by software to configure the prescaler of the PLL1. The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1). In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0. ... ... + @"DIVM[1]": PLLM, + reserved20: u2, + /// (3/3 of DIVM) prescaler for PLL1 Set and cleared by software to configure the prescaler of the PLL1. The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1). In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0. ... ... + @"DIVM[2]": PLLM, + padding: u6, }), /// RCC PLLs configuration register. PLLCFGR: mmio.Mmio(packed struct(u32) { - /// PLL1 fractional latch enable Set and reset by software to latch the content of FRACN into the sigma-delta modulator. In order to latch the FRACN value into the sigma-delta modulator, PLL1FRACLE must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN into the modulator. Refer to PLL initialization procedure on page 444 for additional information. - PLLFRACEN: u1, - /// PLL1 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL1. This bit must be written before enabling the PLL1. It allows the application to select the VCO range: VCOH: working from 400 to 1600 MHz (Fref1_ck must be between 2 and 16 MHz) VCOL: working from 150 to 420 MHz (Fref1_ck must be between 1 and 2 MHz). - PLLVCOSEL: PLLVCOSEL, - /// PLL1 SSCG enable Set and reset by software to enable the Spread Spectrum Clock Generator of PLL1, in order to reduce the amount of EMI peaks. - PLLSSCGEN: u1, - /// PLL1 input frequency range Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1. - PLLRGE: PLLRGE, - /// PLL1 DIVP divider output enable Set and reset by software to enable the pll1_p_ck output of the PLL1. The hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock (SW=3). In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled. - DIVPEN: u1, - /// PLL1 DIVQ divider output enable Set and reset by software to enable the pll1_q_ck output of the PLL1. The hardware prevents writing this bit if FMCCKP = 1. In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled. - DIVQEN: u1, - /// PLL1 DIVR divider output enable Set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, PLL1DIVREN and DIVR1 bits must be set to 0 when the pll1_r_ck is not used. - DIVREN: u1, - /// PLL1 DIVS divider output enable Set and reset by software to enable the pll1_s_ck output of the PLL1. To save power, PLL1DIVSEN must be set to 0 when the pll1_s_ck is not used. - DIVSEN: u1, - /// PLL1 DIVT divider output enable Set and reset by software to enable the pll1_t_ck output of the PLL1. To save power, PLL1DIVTEN must be set to 0 when the pll1_t_ck is not used. - DIVTEN: u1, - padding: u22, + /// (1/3 of PLLFRACEN) PLL1 fractional latch enable Set and reset by software to latch the content of FRACN into the sigma-delta modulator. In order to latch the FRACN value into the sigma-delta modulator, PLL1FRACLE must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN into the modulator. Refer to PLL initialization procedure on page 444 for additional information. + @"PLLFRACEN[0]": u1, + /// (1/3 of PLLVCOSEL) PLL1 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL1. This bit must be written before enabling the PLL1. It allows the application to select the VCO range: VCOH: working from 400 to 1600 MHz (Fref1_ck must be between 2 and 16 MHz) VCOL: working from 150 to 420 MHz (Fref1_ck must be between 1 and 2 MHz). + @"PLLVCOSEL[0]": PLLVCOSEL, + /// (1/3 of PLLSSCGEN) PLL1 SSCG enable Set and reset by software to enable the Spread Spectrum Clock Generator of PLL1, in order to reduce the amount of EMI peaks. + @"PLLSSCGEN[0]": u1, + /// (1/3 of PLLRGE) PLL1 input frequency range Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1. + @"PLLRGE[0]": PLLRGE, + /// (1/3 of DIVPEN) PLL1 DIVP divider output enable Set and reset by software to enable the pll1_p_ck output of the PLL1. The hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock (SW=3). In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled. + @"DIVPEN[0]": u1, + /// (1/3 of DIVQEN) PLL1 DIVQ divider output enable Set and reset by software to enable the pll1_q_ck output of the PLL1. The hardware prevents writing this bit if FMCCKP = 1. In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled. + @"DIVQEN[0]": u1, + /// (1/3 of DIVREN) PLL1 DIVR divider output enable Set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, PLL1DIVREN and DIVR1 bits must be set to 0 when the pll1_r_ck is not used. + @"DIVREN[0]": u1, + /// (1/3 of DIVSEN) PLL1 DIVS divider output enable Set and reset by software to enable the pll1_s_ck output of the PLL1. To save power, PLL1DIVSEN must be set to 0 when the pll1_s_ck is not used. + @"DIVSEN[0]": u1, + /// (1/3 of DIVTEN) PLL1 DIVT divider output enable Set and reset by software to enable the pll1_t_ck output of the PLL1. To save power, PLL1DIVTEN must be set to 0 when the pll1_t_ck is not used. + @"DIVTEN[0]": u1, + reserved11: u1, + /// (2/3 of PLLFRACEN) PLL1 fractional latch enable Set and reset by software to latch the content of FRACN into the sigma-delta modulator. In order to latch the FRACN value into the sigma-delta modulator, PLL1FRACLE must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN into the modulator. Refer to PLL initialization procedure on page 444 for additional information. + @"PLLFRACEN[1]": u1, + /// (2/3 of PLLVCOSEL) PLL1 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL1. This bit must be written before enabling the PLL1. It allows the application to select the VCO range: VCOH: working from 400 to 1600 MHz (Fref1_ck must be between 2 and 16 MHz) VCOL: working from 150 to 420 MHz (Fref1_ck must be between 1 and 2 MHz). + @"PLLVCOSEL[1]": PLLVCOSEL, + /// (2/3 of PLLSSCGEN) PLL1 SSCG enable Set and reset by software to enable the Spread Spectrum Clock Generator of PLL1, in order to reduce the amount of EMI peaks. + @"PLLSSCGEN[1]": u1, + /// (2/3 of PLLRGE) PLL1 input frequency range Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1. + @"PLLRGE[1]": PLLRGE, + /// (2/3 of DIVPEN) PLL1 DIVP divider output enable Set and reset by software to enable the pll1_p_ck output of the PLL1. The hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock (SW=3). In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled. + @"DIVPEN[1]": u1, + /// (2/3 of DIVQEN) PLL1 DIVQ divider output enable Set and reset by software to enable the pll1_q_ck output of the PLL1. The hardware prevents writing this bit if FMCCKP = 1. In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled. + @"DIVQEN[1]": u1, + /// (2/3 of DIVREN) PLL1 DIVR divider output enable Set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, PLL1DIVREN and DIVR1 bits must be set to 0 when the pll1_r_ck is not used. + @"DIVREN[1]": u1, + /// (2/3 of DIVSEN) PLL1 DIVS divider output enable Set and reset by software to enable the pll1_s_ck output of the PLL1. To save power, PLL1DIVSEN must be set to 0 when the pll1_s_ck is not used. + @"DIVSEN[1]": u1, + /// (2/3 of DIVTEN) PLL1 DIVT divider output enable Set and reset by software to enable the pll1_t_ck output of the PLL1. To save power, PLL1DIVTEN must be set to 0 when the pll1_t_ck is not used. + @"DIVTEN[1]": u1, + reserved22: u1, + /// (3/3 of PLLFRACEN) PLL1 fractional latch enable Set and reset by software to latch the content of FRACN into the sigma-delta modulator. In order to latch the FRACN value into the sigma-delta modulator, PLL1FRACLE must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN into the modulator. Refer to PLL initialization procedure on page 444 for additional information. + @"PLLFRACEN[2]": u1, + /// (3/3 of PLLVCOSEL) PLL1 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL1. This bit must be written before enabling the PLL1. It allows the application to select the VCO range: VCOH: working from 400 to 1600 MHz (Fref1_ck must be between 2 and 16 MHz) VCOL: working from 150 to 420 MHz (Fref1_ck must be between 1 and 2 MHz). + @"PLLVCOSEL[2]": PLLVCOSEL, + /// (3/3 of PLLSSCGEN) PLL1 SSCG enable Set and reset by software to enable the Spread Spectrum Clock Generator of PLL1, in order to reduce the amount of EMI peaks. + @"PLLSSCGEN[2]": u1, + /// (3/3 of PLLRGE) PLL1 input frequency range Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1. + @"PLLRGE[2]": PLLRGE, + /// (3/3 of DIVPEN) PLL1 DIVP divider output enable Set and reset by software to enable the pll1_p_ck output of the PLL1. The hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock (SW=3). In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled. + @"DIVPEN[2]": u1, + /// (3/3 of DIVQEN) PLL1 DIVQ divider output enable Set and reset by software to enable the pll1_q_ck output of the PLL1. The hardware prevents writing this bit if FMCCKP = 1. In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled. + @"DIVQEN[2]": u1, + /// (3/3 of DIVREN) PLL1 DIVR divider output enable Set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, PLL1DIVREN and DIVR1 bits must be set to 0 when the pll1_r_ck is not used. + @"DIVREN[2]": u1, + /// (3/3 of DIVSEN) PLL1 DIVS divider output enable Set and reset by software to enable the pll1_s_ck output of the PLL1. To save power, PLL1DIVSEN must be set to 0 when the pll1_s_ck is not used. + @"DIVSEN[2]": u1, + /// (3/3 of DIVTEN) PLL1 DIVT divider output enable Set and reset by software to enable the pll1_t_ck output of the PLL1. To save power, PLL1DIVTEN must be set to 0 when the pll1_t_ck is not used. + @"DIVTEN[2]": u1, }), /// RCC PLL dividers configuration register 1. PLLDIVR: mmio.Mmio(packed struct(u32) { @@ -390087,9 +402348,12 @@ pub const types = struct { CSIRDYIE: u1, /// HSI48 ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI48 oscillator stabilization. HSI48RDYIE: u1, - /// PLL1 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL1 lock. - PLLRDYIE: u1, - reserved9: u2, + /// (1/3 of PLLRDYIE) PLL1 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL1 lock. + @"PLLRDYIE[0]": u1, + /// (2/3 of PLLRDYIE) PLL1 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL1 lock. + @"PLLRDYIE[1]": u1, + /// (3/3 of PLLRDYIE) PLL1 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL1 lock. + @"PLLRDYIE[2]": u1, /// LSE clock security system interrupt enable Set and reset by software to enable/disable interrupt caused by the clock security system (CSS) on external 32 kHz oscillator. LSECSSIE: u1, padding: u22, @@ -390108,9 +402372,12 @@ pub const types = struct { CSIRDYF: u1, /// HSI48 ready interrupt flag Reset by software by writing HSI48RDYC bit. Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set. HSI48RDYF: u1, - /// PLL1 ready interrupt flag Reset by software by writing PLL1RDYC bit. Set by hardware when the PLL1 locks and PLL1RDYIE is set. - PLLRDYF: u1, - reserved9: u2, + /// (1/3 of PLLRDYF) PLL1 ready interrupt flag Reset by software by writing PLL1RDYC bit. Set by hardware when the PLL1 locks and PLL1RDYIE is set. + @"PLLRDYF[0]": u1, + /// (2/3 of PLLRDYF) PLL1 ready interrupt flag Reset by software by writing PLL1RDYC bit. Set by hardware when the PLL1 locks and PLL1RDYIE is set. + @"PLLRDYF[1]": u1, + /// (3/3 of PLLRDYF) PLL1 ready interrupt flag Reset by software by writing PLL1RDYC bit. Set by hardware when the PLL1 locks and PLL1RDYIE is set. + @"PLLRDYF[2]": u1, /// LSE clock security system interrupt flag Reset by software by writing LSECSSC bit. Set by hardware when a failure is detected on the external 32 kHz oscillator and LSECSSIE is set. LSECSSF: u1, /// HSE clock security system interrupt flag Reset by software by writing HSECSSC bit. Set by hardware in case of HSE clock failure. @@ -390131,9 +402398,12 @@ pub const types = struct { CSIRDYC: u1, /// HSI48 ready interrupt clear Set by software to clear HSI48RDYF. Reset by hardware when clear done. HSI48RDYC: u1, - /// PLL1 ready interrupt clear Set by software to clear PLL1RDYF. Reset by hardware when clear done. - PLLRDYC: u1, - reserved9: u2, + /// (1/3 of PLLRDYC) PLL1 ready interrupt clear Set by software to clear PLL1RDYF. Reset by hardware when clear done. + @"PLLRDYC[0]": u1, + /// (2/3 of PLLRDYC) PLL1 ready interrupt clear Set by software to clear PLL1RDYF. Reset by hardware when clear done. + @"PLLRDYC[1]": u1, + /// (3/3 of PLLRDYC) PLL1 ready interrupt clear Set by software to clear PLL1RDYF. Reset by hardware when clear done. + @"PLLRDYC[2]": u1, /// LSE clock security system interrupt clear Set by software to clear LSECSSF. Reset by hardware when clear done. LSECSSC: u1, /// HSE clock security system interrupt clear Set by software to clear HSECSSF. Reset by hardware when clear done. @@ -399970,11 +412240,19 @@ pub const types = struct { /// HSE external clock bypass mode Set and reset by software to select the external clock mode in bypass mode. External clock mode must be configured with HSEON bit to be used by the device. This bit can be written only if the HSE oscillator is disabled. This bit is active only if the HSE bypass mode is enabled. HSEEXT: HSEEXT, reserved24: u3, - /// PLL1 enable Set and cleared by software to enable the main PLL. Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL1 clock is used as the system clock. - PLLON: u1, - /// PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked. - PLLRDY: u1, - padding: u6, + /// (1/3 of PLLON) PLL1 enable Set and cleared by software to enable the main PLL. Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL1 clock is used as the system clock. + @"PLLON[0]": u1, + /// (1/3 of PLLRDY) PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked. + @"PLLRDY[0]": u1, + /// (2/3 of PLLON) PLL1 enable Set and cleared by software to enable the main PLL. Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL1 clock is used as the system clock. + @"PLLON[1]": u1, + /// (2/3 of PLLRDY) PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked. + @"PLLRDY[1]": u1, + /// (3/3 of PLLON) PLL1 enable Set and cleared by software to enable the main PLL. Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL1 clock is used as the system clock. + @"PLLON[2]": u1, + /// (3/3 of PLLRDY) PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked. + @"PLLRDY[2]": u1, + padding: u2, }), reserved8: [4]u8, /// RCC internal clock sources calibration register 1 @@ -400215,9 +412493,13 @@ pub const types = struct { HSERDYIE: u1, /// HSI48 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI48 oscillator stabilization. HSI48RDYIE: u1, - /// PLL ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL1 lock. - PLLRDYIE: u1, - reserved11: u4, + /// (1/3 of PLLRDYIE) PLL ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL1 lock. + @"PLLRDYIE[0]": u1, + /// (2/3 of PLLRDYIE) PLL ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL1 lock. + @"PLLRDYIE[1]": u1, + /// (3/3 of PLLRDYIE) PLL ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL1 lock. + @"PLLRDYIE[2]": u1, + reserved11: u2, /// MSIK ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the MSIK oscillator stabilization. MSIKRDYIE: u1, /// SHSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the SHSI oscillator stabilization. @@ -400238,9 +412520,13 @@ pub const types = struct { HSERDYF: u1, /// HSI48 ready interrupt flag Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set. Cleared by software setting the HSI48RDYC bit. HSI48RDYF: u1, - /// PLL1 ready interrupt flag Set by hardware when the PLL1 locks and PLL1RDYIE is set. Cleared by software setting the PLL1RDYC bit. - PLLRDYF: u1, - reserved10: u3, + /// (1/3 of PLLRDYF) PLL1 ready interrupt flag Set by hardware when the PLL1 locks and PLL1RDYIE is set. Cleared by software setting the PLL1RDYC bit. + @"PLLRDYF[0]": u1, + /// (2/3 of PLLRDYF) PLL1 ready interrupt flag Set by hardware when the PLL1 locks and PLL1RDYIE is set. Cleared by software setting the PLL1RDYC bit. + @"PLLRDYF[1]": u1, + /// (3/3 of PLLRDYF) PLL1 ready interrupt flag Set by hardware when the PLL1 locks and PLL1RDYIE is set. Cleared by software setting the PLL1RDYC bit. + @"PLLRDYF[2]": u1, + reserved10: u1, /// Clock security system interrupt flag Set by hardware when a failure is detected in the HSE oscillator. Cleared by software setting the CSSC bit. CSSF: u1, /// MSIK ready interrupt flag Set by hardware when the MSIK clock becomes stable and MSIKRDYIE is set. Cleared by software setting the MSIKRDYC bit. @@ -400263,9 +412549,13 @@ pub const types = struct { HSERDYC: u1, /// HSI48 ready interrupt clear Writing this bit to 1 clears the HSI48RDYF flag. Writing 0 has no effect. HSI48RDYC: u1, - /// PLL1 ready interrupt clear Writing this bit to 1 clears the PLL1RDYF flag. Writing 0 has no effect. - PLLRDYC: u1, - reserved10: u3, + /// (1/3 of PLLRDYC) PLL1 ready interrupt clear Writing this bit to 1 clears the PLL1RDYF flag. Writing 0 has no effect. + @"PLLRDYC[0]": u1, + /// (2/3 of PLLRDYC) PLL1 ready interrupt clear Writing this bit to 1 clears the PLL1RDYF flag. Writing 0 has no effect. + @"PLLRDYC[1]": u1, + /// (3/3 of PLLRDYC) PLL1 ready interrupt clear Writing this bit to 1 clears the PLL1RDYF flag. Writing 0 has no effect. + @"PLLRDYC[2]": u1, + reserved10: u1, /// Clock security system interrupt clear Writing this bit to 1 clears the CSSF flag. Writing 0 has no effect. CSSC: u1, /// MSIK oscillator ready interrupt clear Writing this bit to 1 clears the MSIKRDYF flag. Writing 0 has no effect. @@ -401270,9 +413560,12 @@ pub const types = struct { SYSCLKSEC: SECURITY, /// AHBx/APBx prescaler configuration bits security Set and reset by software. PRESCSEC: SECURITY, - /// PLL1 clock configuration and status bits security Set and reset by software. - PLLSEC: SECURITY, - reserved10: u2, + /// (1/3 of PLLSEC) PLL1 clock configuration and status bits security Set and reset by software. + @"PLLSEC[0]": SECURITY, + /// (2/3 of PLLSEC) PLL1 clock configuration and status bits security Set and reset by software. + @"PLLSEC[1]": SECURITY, + /// (3/3 of PLLSEC) PLL1 clock configuration and status bits security Set and reset by software. + @"PLLSEC[2]": SECURITY, /// intermediate clock source selection security Set and reset by software. ICLKSEC: SECURITY, /// HSI48 clock configuration and status bits security Set and reset by software. @@ -406562,15 +418855,15 @@ pub const types = struct { /// Hour format FMT: FMT, reserved8: u1, - /// Alarm enable - ALRE: u1, + /// (1/1 of ALRE) Alarm enable + @"ALRE[0]": u1, reserved10: u1, /// Wakeup timer enable WUTE: u1, /// Timestamp enable TSE: u1, - /// Alarm interrupt enable - ALRIE: u1, + /// (1/1 of ALRIE) Alarm interrupt enable + @"ALRIE[0]": u1, reserved14: u1, /// Wakeup timer interrupt enable WUTIE: u1, @@ -406594,8 +418887,8 @@ pub const types = struct { }), /// Initialization and status register ISR: mmio.Mmio(packed struct(u32) { - /// Alarm write enabled - ALRWF: u1, + /// (1/1 of ALRWF) Alarm write enabled + @"ALRWF[0]": u1, reserved2: u1, /// Wakeup timer write enabled WUTWF: u1, @@ -406609,8 +418902,8 @@ pub const types = struct { INITF: u1, /// Enter Initialization mode INIT: u1, - /// Alarm flag - ALRF: u1, + /// (1/1 of ALRF) Alarm flag + @"ALRF[0]": u1, reserved10: u1, /// Wakeup timer flag WUTF: u1, @@ -406618,9 +418911,12 @@ pub const types = struct { TSF: u1, /// Timestamp overflow flag TSOVF: u1, - /// Tamper detection flag - TAMPF: u1, - reserved16: u2, + /// (1/3 of TAMPF) Tamper detection flag + @"TAMPF[0]": u1, + /// (2/3 of TAMPF) Tamper detection flag + @"TAMPF[1]": u1, + /// (3/3 of TAMPF) Tamper detection flag + @"TAMPF[2]": u1, /// Recalibration pending flag RECALPF: u1, padding: u15, @@ -406930,16 +419226,18 @@ pub const types = struct { FMT: u1, /// Coarse digital calibration enable DCE: u1, - /// Alarm enable - ALRE: u1, - reserved10: u1, + /// (1/2 of ALRE) Alarm enable + @"ALRE[0]": u1, + /// (2/2 of ALRE) Alarm enable + @"ALRE[1]": u1, /// Wakeup timer enable WUTE: u1, /// Timestamp enable TSE: u1, - /// Alarm interrupt enable - ALRIE: u1, - reserved14: u1, + /// (1/2 of ALRIE) Alarm interrupt enable + @"ALRIE[0]": u1, + /// (2/2 of ALRIE) Alarm interrupt enable + @"ALRIE[1]": u1, /// Wakeup timer interrupt enable WUTIE: u1, /// Timestamp interrupt enable @@ -406961,9 +419259,10 @@ pub const types = struct { }), /// Initialization and status register ISR: mmio.Mmio(packed struct(u32) { - /// Alarm write enabled - ALRWF: u1, - reserved2: u1, + /// (1/2 of ALRWF) Alarm write enabled + @"ALRWF[0]": u1, + /// (2/2 of ALRWF) Alarm write enabled + @"ALRWF[1]": u1, /// Wakeup timer write enabled WUTWF: u1, reserved4: u1, @@ -406975,17 +419274,18 @@ pub const types = struct { INITF: u1, /// Enter Initialization mode INIT: u1, - /// Alarm flag - ALRF: u1, - reserved10: u1, + /// (1/2 of ALRF) Alarm flag + @"ALRF[0]": u1, + /// (2/2 of ALRF) Alarm flag + @"ALRF[1]": u1, /// Wakeup timer flag WUTF: u1, /// Timestamp flag TSF: u1, /// Timestamp overflow flag TSOVF: u1, - /// Tamper detection flag - TAMPF: u1, + /// (1/1 of TAMPF) Tamper detection flag + @"TAMPF[0]": u1, padding: u18, }), /// Prescaler register @@ -407344,16 +419644,18 @@ pub const types = struct { /// Hour format FMT: FMT, reserved8: u1, - /// Alarm enable - ALRE: u1, - reserved10: u1, + /// (1/2 of ALRE) Alarm enable + @"ALRE[0]": u1, + /// (2/2 of ALRE) Alarm enable + @"ALRE[1]": u1, /// Wakeup timer enable WUTE: u1, /// Timestamp enable TSE: u1, - /// Alarm interrupt enable - ALRIE: u1, - reserved14: u1, + /// (1/2 of ALRIE) Alarm interrupt enable + @"ALRIE[0]": u1, + /// (2/2 of ALRIE) Alarm interrupt enable + @"ALRIE[1]": u1, /// Wakeup timer interrupt enable WUTIE: u1, /// Timestamp interrupt enable @@ -407376,9 +419678,10 @@ pub const types = struct { }), /// Initialization and status register ISR: mmio.Mmio(packed struct(u32) { - /// Alarm write enabled - ALRWF: u1, - reserved2: u1, + /// (1/2 of ALRWF) Alarm write enabled + @"ALRWF[0]": u1, + /// (2/2 of ALRWF) Alarm write enabled + @"ALRWF[1]": u1, /// Wakeup timer write enabled WUTWF: u1, /// Shift operation pending @@ -407391,18 +419694,22 @@ pub const types = struct { INITF: u1, /// Enter Initialization mode INIT: u1, - /// Alarm flag - ALRF: u1, - reserved10: u1, + /// (1/2 of ALRF) Alarm flag + @"ALRF[0]": u1, + /// (2/2 of ALRF) Alarm flag + @"ALRF[1]": u1, /// Wakeup timer flag WUTF: u1, /// Timestamp flag TSF: u1, /// Timestamp overflow flag TSOVF: u1, - /// Tamper detection flag - TAMPF: u1, - reserved16: u2, + /// (1/3 of TAMPF) Tamper detection flag + @"TAMPF[0]": u1, + /// (2/3 of TAMPF) Tamper detection flag + @"TAMPF[1]": u1, + /// (3/3 of TAMPF) Tamper detection flag + @"TAMPF[2]": u1, /// Recalibration pending flag RECALPF: RECALPF, padding: u15, @@ -407799,16 +420106,18 @@ pub const types = struct { FMT: FMT, /// Coarse digital calibration enable DCE: u1, - /// Alarm enable - ALRE: u1, - reserved10: u1, + /// (1/2 of ALRE) Alarm enable + @"ALRE[0]": u1, + /// (2/2 of ALRE) Alarm enable + @"ALRE[1]": u1, /// Wakeup timer enable WUTE: u1, /// Timestamp enable TSE: u1, - /// Alarm interrupt enable - ALRIE: u1, - reserved14: u1, + /// (1/2 of ALRIE) Alarm interrupt enable + @"ALRIE[0]": u1, + /// (2/2 of ALRIE) Alarm interrupt enable + @"ALRIE[1]": u1, /// Wakeup timer interrupt enable WUTIE: u1, /// Timestamp interrupt enable @@ -407831,9 +420140,10 @@ pub const types = struct { }), /// Initialization and status register ISR: mmio.Mmio(packed struct(u32) { - /// Alarm write allowed - ALRWF: u1, - reserved2: u1, + /// (1/2 of ALRWF) Alarm write allowed + @"ALRWF[0]": u1, + /// (2/2 of ALRWF) Alarm write allowed + @"ALRWF[1]": u1, /// Wakeup timer write allowed WUTWF: u1, /// Shift operation pending @@ -407846,18 +420156,22 @@ pub const types = struct { INITF: u1, /// Enter Initialization mode INIT: u1, - /// Alarm flag - ALRF: u1, - reserved10: u1, + /// (1/2 of ALRF) Alarm flag + @"ALRF[0]": u1, + /// (2/2 of ALRF) Alarm flag + @"ALRF[1]": u1, /// Wakeup timer flag WUTF: u1, /// Timestamp flag TSF: u1, /// Timestamp overflow flag TSOVF: u1, - /// Tamper detection flag - TAMPF: u1, - reserved16: u2, + /// (1/3 of TAMPF) Tamper detection flag + @"TAMPF[0]": u1, + /// (2/3 of TAMPF) Tamper detection flag + @"TAMPF[1]": u1, + /// (3/3 of TAMPF) Tamper detection flag + @"TAMPF[2]": u1, /// Recalibration pending flag RECALPF: RECALPF, padding: u15, @@ -408254,16 +420568,18 @@ pub const types = struct { /// Hour format FMT: FMT, reserved8: u1, - /// Alarm enable - ALRE: u1, - reserved10: u1, + /// (1/2 of ALRE) Alarm enable + @"ALRE[0]": u1, + /// (2/2 of ALRE) Alarm enable + @"ALRE[1]": u1, /// Wakeup timer enable WUTE: u1, /// Timestamp enable TSE: u1, - /// Alarm interrupt enable - ALRIE: u1, - reserved14: u1, + /// (1/2 of ALRIE) Alarm interrupt enable + @"ALRIE[0]": u1, + /// (2/2 of ALRIE) Alarm interrupt enable + @"ALRIE[1]": u1, /// Wakeup timer interrupt enable WUTIE: u1, /// Timestamp interrupt enable @@ -408288,9 +420604,10 @@ pub const types = struct { }), /// Initialization and status register ISR: mmio.Mmio(packed struct(u32) { - /// Alarm write enabled - ALRWF: u1, - reserved2: u1, + /// (1/2 of ALRWF) Alarm write enabled + @"ALRWF[0]": u1, + /// (2/2 of ALRWF) Alarm write enabled + @"ALRWF[1]": u1, /// Wakeup timer write enabled WUTWF: u1, /// Shift operation pending @@ -408303,18 +420620,22 @@ pub const types = struct { INITF: u1, /// Enter Initialization mode INIT: u1, - /// Alarm flag - ALRF: u1, - reserved10: u1, + /// (1/2 of ALRF) Alarm flag + @"ALRF[0]": u1, + /// (2/2 of ALRF) Alarm flag + @"ALRF[1]": u1, /// Wakeup timer flag WUTF: u1, /// Timestamp flag TSF: u1, /// Timestamp overflow flag TSOVF: u1, - /// Tamper detection flag - TAMPF: u1, - reserved16: u2, + /// (1/3 of TAMPF) Tamper detection flag + @"TAMPF[0]": u1, + /// (2/3 of TAMPF) Tamper detection flag + @"TAMPF[1]": u1, + /// (3/3 of TAMPF) Tamper detection flag + @"TAMPF[2]": u1, /// Recalibration pending flag RECALPF: RECALPF, /// Internal time-stamp flag @@ -408461,13 +420782,25 @@ pub const types = struct { TAMPPRCH: TAMPPRCH, /// Tamper pull-up disable TAMPPUDIS: TAMPPUDIS, - /// Tamper interrupt enable - TAMPXIE: u1, - /// Tamper no erase - TAMPXNOERASE: u1, - /// Tamper mask flag - TAMPXMF: u1, - padding: u13, + /// (1/3 of TAMPXIE) Tamper interrupt enable + @"TAMPXIE[0]": u1, + /// (1/3 of TAMPXNOERASE) Tamper no erase + @"TAMPXNOERASE[0]": u1, + /// (1/3 of TAMPXMF) Tamper mask flag + @"TAMPXMF[0]": u1, + /// (2/3 of TAMPXIE) Tamper interrupt enable + @"TAMPXIE[1]": u1, + /// (2/3 of TAMPXNOERASE) Tamper no erase + @"TAMPXNOERASE[1]": u1, + /// (2/3 of TAMPXMF) Tamper mask flag + @"TAMPXMF[1]": u1, + /// (3/3 of TAMPXIE) Tamper interrupt enable + @"TAMPXIE[2]": u1, + /// (3/3 of TAMPXNOERASE) Tamper no erase + @"TAMPXNOERASE[2]": u1, + /// (3/3 of TAMPXMF) Tamper mask flag + @"TAMPXMF[2]": u1, + padding: u7, }), /// Alarm sub second register ALRMSSR: [2]mmio.Mmio(packed struct(u32) { @@ -408713,16 +421046,18 @@ pub const types = struct { /// Hour format FMT: FMT, reserved8: u1, - /// Alarm enable - ALRE: u1, - reserved10: u1, + /// (1/2 of ALRE) Alarm enable + @"ALRE[0]": u1, + /// (2/2 of ALRE) Alarm enable + @"ALRE[1]": u1, /// Wakeup timer enable WUTE: u1, /// Timestamp enable TSE: u1, - /// Alarm interrupt enable - ALRIE: u1, - reserved14: u1, + /// (1/2 of ALRIE) Alarm interrupt enable + @"ALRIE[0]": u1, + /// (2/2 of ALRIE) Alarm interrupt enable + @"ALRIE[1]": u1, /// Wakeup timer interrupt enable WUTIE: u1, /// Timestamp interrupt enable @@ -408747,9 +421082,10 @@ pub const types = struct { }), /// Initialization and status register ISR: mmio.Mmio(packed struct(u32) { - /// Alarm write enabled - ALRWF: u1, - reserved2: u1, + /// (1/2 of ALRWF) Alarm write enabled + @"ALRWF[0]": u1, + /// (2/2 of ALRWF) Alarm write enabled + @"ALRWF[1]": u1, /// Wakeup timer write enabled WUTWF: u1, /// Shift operation pending @@ -408762,18 +421098,22 @@ pub const types = struct { INITF: u1, /// Enter Initialization mode INIT: u1, - /// Alarm flag - ALRF: u1, - reserved10: u1, + /// (1/2 of ALRF) Alarm flag + @"ALRF[0]": u1, + /// (2/2 of ALRF) Alarm flag + @"ALRF[1]": u1, /// Wakeup timer flag WUTF: u1, /// Timestamp flag TSF: u1, /// Timestamp overflow flag TSOVF: u1, - /// Tamper detection flag - TAMPF: u1, - reserved16: u2, + /// (1/3 of TAMPF) Tamper detection flag + @"TAMPF[0]": u1, + /// (2/3 of TAMPF) Tamper detection flag + @"TAMPF[1]": u1, + /// (3/3 of TAMPF) Tamper detection flag + @"TAMPF[2]": u1, /// Recalibration pending flag RECALPF: RECALPF, /// Internal time-stamp flag @@ -408920,13 +421260,25 @@ pub const types = struct { TAMPPRCH: TAMPPRCH, /// Tamper pull-up disable TAMPPUDIS: TAMPPUDIS, - /// Tamper interrupt enable - TAMPXIE: u1, - /// Tamper no erase - TAMPXNOERASE: u1, - /// Tamper mask flag - TAMPXMF: u1, - padding: u13, + /// (1/3 of TAMPXIE) Tamper interrupt enable + @"TAMPXIE[0]": u1, + /// (1/3 of TAMPXNOERASE) Tamper no erase + @"TAMPXNOERASE[0]": u1, + /// (1/3 of TAMPXMF) Tamper mask flag + @"TAMPXMF[0]": u1, + /// (2/3 of TAMPXIE) Tamper interrupt enable + @"TAMPXIE[1]": u1, + /// (2/3 of TAMPXNOERASE) Tamper no erase + @"TAMPXNOERASE[1]": u1, + /// (2/3 of TAMPXMF) Tamper mask flag + @"TAMPXMF[1]": u1, + /// (3/3 of TAMPXIE) Tamper interrupt enable + @"TAMPXIE[2]": u1, + /// (3/3 of TAMPXNOERASE) Tamper no erase + @"TAMPXNOERASE[2]": u1, + /// (3/3 of TAMPXMF) Tamper mask flag + @"TAMPXMF[2]": u1, + padding: u7, }), /// Alarm sub second register ALRMSSR: [2]mmio.Mmio(packed struct(u32) { @@ -409171,16 +421523,18 @@ pub const types = struct { /// Hour format FMT: FMT, reserved8: u1, - /// Alarm enable - ALRE: u1, - reserved10: u1, + /// (1/2 of ALRE) Alarm enable + @"ALRE[0]": u1, + /// (2/2 of ALRE) Alarm enable + @"ALRE[1]": u1, /// Wakeup timer enable WUTE: u1, /// Timestamp enable TSE: u1, - /// Alarm interrupt enable - ALRIE: u1, - reserved14: u1, + /// (1/2 of ALRIE) Alarm interrupt enable + @"ALRIE[0]": u1, + /// (2/2 of ALRIE) Alarm interrupt enable + @"ALRIE[1]": u1, /// Wakeup timer interrupt enable WUTIE: u1, /// Timestamp interrupt enable @@ -409203,9 +421557,10 @@ pub const types = struct { }), /// Initialization and status register ISR: mmio.Mmio(packed struct(u32) { - /// Alarm write enabled - ALRWF: u1, - reserved2: u1, + /// (1/2 of ALRWF) Alarm write enabled + @"ALRWF[0]": u1, + /// (2/2 of ALRWF) Alarm write enabled + @"ALRWF[1]": u1, /// Wakeup timer write enabled WUTWF: u1, /// Shift operation pending @@ -409218,18 +421573,22 @@ pub const types = struct { INITF: u1, /// Enter Initialization mode INIT: u1, - /// Alarm flag - ALRF: u1, - reserved10: u1, + /// (1/2 of ALRF) Alarm flag + @"ALRF[0]": u1, + /// (2/2 of ALRF) Alarm flag + @"ALRF[1]": u1, /// Wakeup timer flag WUTF: u1, /// Timestamp flag TSF: u1, /// Timestamp overflow flag TSOVF: u1, - /// Tamper detection flag - TAMPF: u1, - reserved16: u2, + /// (1/3 of TAMPF) Tamper detection flag + @"TAMPF[0]": u1, + /// (2/3 of TAMPF) Tamper detection flag + @"TAMPF[1]": u1, + /// (3/3 of TAMPF) Tamper detection flag + @"TAMPF[2]": u1, /// Recalibration pending flag RECALPF: RECALPF, padding: u15, @@ -409374,13 +421733,25 @@ pub const types = struct { TAMPPRCH: TAMPPRCH, /// Tamper pull-up disable TAMPPUDIS: TAMPPUDIS, - /// Tamper interrupt enable - TAMPXIE: u1, - /// Tamper no erase - TAMPXNOERASE: u1, - /// Tamper mask flag - TAMPXMF: u1, - padding: u13, + /// (1/3 of TAMPXIE) Tamper interrupt enable + @"TAMPXIE[0]": u1, + /// (1/3 of TAMPXNOERASE) Tamper no erase + @"TAMPXNOERASE[0]": u1, + /// (1/3 of TAMPXMF) Tamper mask flag + @"TAMPXMF[0]": u1, + /// (2/3 of TAMPXIE) Tamper interrupt enable + @"TAMPXIE[1]": u1, + /// (2/3 of TAMPXNOERASE) Tamper no erase + @"TAMPXNOERASE[1]": u1, + /// (2/3 of TAMPXMF) Tamper mask flag + @"TAMPXMF[1]": u1, + /// (3/3 of TAMPXIE) Tamper interrupt enable + @"TAMPXIE[2]": u1, + /// (3/3 of TAMPXNOERASE) Tamper no erase + @"TAMPXNOERASE[2]": u1, + /// (3/3 of TAMPXMF) Tamper mask flag + @"TAMPXMF[2]": u1, + padding: u7, }), /// Alarm sub second register ALRMSSR: [2]mmio.Mmio(packed struct(u32) { @@ -409626,16 +421997,18 @@ pub const types = struct { FMT: FMT, /// Coarse digital calibration enable DCE: u1, - /// Alarm enable - ALRE: u1, - reserved10: u1, + /// (1/2 of ALRE) Alarm enable + @"ALRE[0]": u1, + /// (2/2 of ALRE) Alarm enable + @"ALRE[1]": u1, /// Wakeup timer enable WUTE: u1, /// Timestamp enable TSE: u1, - /// Alarm interrupt enable - ALRIE: u1, - reserved14: u1, + /// (1/2 of ALRIE) Alarm interrupt enable + @"ALRIE[0]": u1, + /// (2/2 of ALRIE) Alarm interrupt enable + @"ALRIE[1]": u1, /// Wakeup timer interrupt enable WUTIE: u1, /// Timestamp interrupt enable @@ -409658,9 +422031,10 @@ pub const types = struct { }), /// Initialization and status register ISR: mmio.Mmio(packed struct(u32) { - /// Alarm write enabled - ALRWF: u1, - reserved2: u1, + /// (1/2 of ALRWF) Alarm write enabled + @"ALRWF[0]": u1, + /// (2/2 of ALRWF) Alarm write enabled + @"ALRWF[1]": u1, /// Wakeup timer write enabled WUTWF: u1, /// Shift operation pending @@ -409673,18 +422047,22 @@ pub const types = struct { INITF: u1, /// Enter Initialization mode INIT: u1, - /// Alarm flag - ALRF: u1, - reserved10: u1, + /// (1/2 of ALRF) Alarm flag + @"ALRF[0]": u1, + /// (2/2 of ALRF) Alarm flag + @"ALRF[1]": u1, /// Wakeup timer flag WUTF: u1, /// Timestamp flag TSF: u1, /// Timestamp overflow flag TSOVF: u1, - /// Tamper detection flag - TAMPF: u1, - reserved16: u2, + /// (1/3 of TAMPF) Tamper detection flag + @"TAMPF[0]": u1, + /// (2/3 of TAMPF) Tamper detection flag + @"TAMPF[1]": u1, + /// (3/3 of TAMPF) Tamper detection flag + @"TAMPF[2]": u1, /// Recalibration pending flag RECALPF: RECALPF, padding: u15, @@ -410078,16 +422456,18 @@ pub const types = struct { /// Hour format FMT: FMT, reserved8: u1, - /// Alarm enable - ALRE: u1, - reserved10: u1, + /// (1/2 of ALRE) Alarm enable + @"ALRE[0]": u1, + /// (2/2 of ALRE) Alarm enable + @"ALRE[1]": u1, /// Wakeup timer enable WUTE: u1, /// Timestamp enable TSE: u1, - /// Alarm interrupt enable - ALRIE: u1, - reserved14: u1, + /// (1/2 of ALRIE) Alarm interrupt enable + @"ALRIE[0]": u1, + /// (2/2 of ALRIE) Alarm interrupt enable + @"ALRIE[1]": u1, /// Wakeup timer interrupt enable WUTIE: u1, /// Timestamp interrupt enable @@ -410112,9 +422492,10 @@ pub const types = struct { }), /// Initialization and status register ISR: mmio.Mmio(packed struct(u32) { - /// Alarm write enabled - ALRWF: u1, - reserved2: u1, + /// (1/2 of ALRWF) Alarm write enabled + @"ALRWF[0]": u1, + /// (2/2 of ALRWF) Alarm write enabled + @"ALRWF[1]": u1, /// Wakeup timer write enabled WUTWF: u1, /// Shift operation pending @@ -410127,18 +422508,22 @@ pub const types = struct { INITF: u1, /// Enter Initialization mode INIT: u1, - /// Alarm flag - ALRF: u1, - reserved10: u1, + /// (1/2 of ALRF) Alarm flag + @"ALRF[0]": u1, + /// (2/2 of ALRF) Alarm flag + @"ALRF[1]": u1, /// Wakeup timer flag WUTF: u1, /// Timestamp flag TSF: u1, /// Timestamp overflow flag TSOVF: u1, - /// Tamper detection flag - TAMPF: u1, - reserved16: u2, + /// (1/3 of TAMPF) Tamper detection flag + @"TAMPF[0]": u1, + /// (2/3 of TAMPF) Tamper detection flag + @"TAMPF[1]": u1, + /// (3/3 of TAMPF) Tamper detection flag + @"TAMPF[2]": u1, /// Recalibration pending flag RECALPF: RECALPF, padding: u15, @@ -410283,13 +422668,25 @@ pub const types = struct { TAMPPRCH: TAMPPRCH, /// Tamper pull-up disable TAMPPUDIS: TAMPPUDIS, - /// Tamper interrupt enable - TAMPXIE: u1, - /// Tamper no erase - TAMPXNOERASE: u1, - /// Tamper mask flag - TAMPXMF: u1, - padding: u13, + /// (1/3 of TAMPXIE) Tamper interrupt enable + @"TAMPXIE[0]": u1, + /// (1/3 of TAMPXNOERASE) Tamper no erase + @"TAMPXNOERASE[0]": u1, + /// (1/3 of TAMPXMF) Tamper mask flag + @"TAMPXMF[0]": u1, + /// (2/3 of TAMPXIE) Tamper interrupt enable + @"TAMPXIE[1]": u1, + /// (2/3 of TAMPXNOERASE) Tamper no erase + @"TAMPXNOERASE[1]": u1, + /// (2/3 of TAMPXMF) Tamper mask flag + @"TAMPXMF[1]": u1, + /// (3/3 of TAMPXIE) Tamper interrupt enable + @"TAMPXIE[2]": u1, + /// (3/3 of TAMPXNOERASE) Tamper no erase + @"TAMPXNOERASE[2]": u1, + /// (3/3 of TAMPXMF) Tamper mask flag + @"TAMPXMF[2]": u1, + padding: u7, }), /// Alarm sub second register ALRMSSR: [2]mmio.Mmio(packed struct(u32) { @@ -410534,16 +422931,18 @@ pub const types = struct { /// Hour format FMT: FMT, reserved8: u1, - /// Alarm enable - ALRE: u1, - reserved10: u1, + /// (1/2 of ALRE) Alarm enable + @"ALRE[0]": u1, + /// (2/2 of ALRE) Alarm enable + @"ALRE[1]": u1, /// Wakeup timer enable WUTE: u1, /// Timestamp enable TSE: u1, - /// Alarm interrupt enable - ALRIE: u1, - reserved14: u1, + /// (1/2 of ALRIE) Alarm interrupt enable + @"ALRIE[0]": u1, + /// (2/2 of ALRIE) Alarm interrupt enable + @"ALRIE[1]": u1, /// Wakeup timer interrupt enable WUTIE: u1, /// Timestamp interrupt enable @@ -410568,9 +422967,10 @@ pub const types = struct { }), /// Initialization and status register ISR: mmio.Mmio(packed struct(u32) { - /// Alarm write enabled - ALRWF: u1, - reserved2: u1, + /// (1/2 of ALRWF) Alarm write enabled + @"ALRWF[0]": u1, + /// (2/2 of ALRWF) Alarm write enabled + @"ALRWF[1]": u1, /// Wakeup timer write enabled WUTWF: u1, /// Shift operation pending @@ -410583,18 +422983,22 @@ pub const types = struct { INITF: u1, /// Enter Initialization mode INIT: u1, - /// Alarm flag - ALRF: u1, - reserved10: u1, + /// (1/2 of ALRF) Alarm flag + @"ALRF[0]": u1, + /// (2/2 of ALRF) Alarm flag + @"ALRF[1]": u1, /// Wakeup timer flag WUTF: u1, /// Timestamp flag TSF: u1, /// Timestamp overflow flag TSOVF: u1, - /// Tamper detection flag - TAMPF: u1, - reserved16: u2, + /// (1/3 of TAMPF) Tamper detection flag + @"TAMPF[0]": u1, + /// (2/3 of TAMPF) Tamper detection flag + @"TAMPF[1]": u1, + /// (3/3 of TAMPF) Tamper detection flag + @"TAMPF[2]": u1, /// Recalibration pending flag RECALPF: RECALPF, /// Internal time-stamp flag @@ -410741,13 +423145,25 @@ pub const types = struct { TAMPPRCH: TAMPPRCH, /// Tamper pull-up disable TAMPPUDIS: TAMPPUDIS, - /// Tamper interrupt enable - TAMPXIE: u1, - /// Tamper no erase - TAMPXNOERASE: u1, - /// Tamper mask flag - TAMPXMF: u1, - padding: u13, + /// (1/3 of TAMPXIE) Tamper interrupt enable + @"TAMPXIE[0]": u1, + /// (1/3 of TAMPXNOERASE) Tamper no erase + @"TAMPXNOERASE[0]": u1, + /// (1/3 of TAMPXMF) Tamper mask flag + @"TAMPXMF[0]": u1, + /// (2/3 of TAMPXIE) Tamper interrupt enable + @"TAMPXIE[1]": u1, + /// (2/3 of TAMPXNOERASE) Tamper no erase + @"TAMPXNOERASE[1]": u1, + /// (2/3 of TAMPXMF) Tamper mask flag + @"TAMPXMF[1]": u1, + /// (3/3 of TAMPXIE) Tamper interrupt enable + @"TAMPXIE[2]": u1, + /// (3/3 of TAMPXNOERASE) Tamper no erase + @"TAMPXNOERASE[2]": u1, + /// (3/3 of TAMPXMF) Tamper mask flag + @"TAMPXMF[2]": u1, + padding: u7, }), /// Alarm sub second register ALRMSSR: [2]mmio.Mmio(packed struct(u32) { @@ -411122,16 +423538,18 @@ pub const types = struct { FMT: FMT, /// SSR underflow interrupt enable SSRUIE: u1, - /// Alarm enable - ALRE: u1, - reserved10: u1, + /// (1/2 of ALRE) Alarm enable + @"ALRE[0]": u1, + /// (2/2 of ALRE) Alarm enable + @"ALRE[1]": u1, /// Wakeup timer enable WUTE: u1, /// Timestamp enable TSE: u1, - /// Alarm interrupt enable - ALRAIE: u1, - reserved14: u1, + /// (1/2 of ALRAIE) Alarm interrupt enable + @"ALRAIE[0]": u1, + /// (2/2 of ALRAIE) Alarm interrupt enable + @"ALRAIE[1]": u1, /// Wakeup timer interrupt enable WUTIE: u1, /// Timestamp interrupt enable @@ -411280,9 +423698,10 @@ pub const types = struct { reserved80: [8]u8, /// Status register SR: mmio.Mmio(packed struct(u32) { - /// Alarm flag - ALRF: ALRF, - reserved2: u1, + /// (1/2 of ALRF) Alarm flag + @"ALRF[0]": ALRF, + /// (2/2 of ALRF) Alarm flag + @"ALRF[1]": ALRF, /// Wakeup timer flag WUTF: WUTF, /// Timestamp flag @@ -411297,9 +423716,10 @@ pub const types = struct { }), /// Masked interrupt status register MISR: mmio.Mmio(packed struct(u32) { - /// Alarm masked flag - ALRMF: ALRMF, - reserved2: u1, + /// (1/2 of ALRMF) Alarm masked flag + @"ALRMF[0]": ALRMF, + /// (2/2 of ALRMF) Alarm masked flag + @"ALRMF[1]": ALRMF, /// Wakeup timer masked flag WUTMF: WUTMF, /// Timestamp masked flag @@ -411315,9 +423735,10 @@ pub const types = struct { reserved92: [4]u8, /// Status clear register SCR: mmio.Mmio(packed struct(u32) { - /// Clear alarm A flag - CALRF: CALRF, - reserved2: u1, + /// (1/2 of CALRF) Clear alarm A flag + @"CALRF[0]": CALRF, + /// (2/2 of CALRF) Clear alarm A flag + @"CALRF[1]": CALRF, /// Clear wakeup timer flag CWUTF: CALRF, /// Clear timestamp flag @@ -411634,16 +424055,18 @@ pub const types = struct { /// Hour format FMT: FMT, reserved8: u1, - /// Alarm enable - ALRE: u1, - reserved10: u1, + /// (1/2 of ALRE) Alarm enable + @"ALRE[0]": u1, + /// (2/2 of ALRE) Alarm enable + @"ALRE[1]": u1, /// Wakeup timer enable WUTE: u1, /// Timestamp enable TSE: u1, - /// Alarm interrupt enable - ALRIE: u1, - reserved14: u1, + /// (1/2 of ALRIE) Alarm interrupt enable + @"ALRIE[0]": u1, + /// (2/2 of ALRIE) Alarm interrupt enable + @"ALRIE[1]": u1, /// Wakeup timer interrupt enable WUTIE: u1, /// Timestamp interrupt enable @@ -411678,9 +424101,10 @@ pub const types = struct { }), /// Privilege mode control register PRIVCR: mmio.Mmio(packed struct(u32) { - /// ALRAPRIV - ALRPRIV: u1, - reserved2: u1, + /// (1/2 of ALRPRIV) ALRAPRIV + @"ALRPRIV[0]": u1, + /// (2/2 of ALRPRIV) ALRAPRIV + @"ALRPRIV[1]": u1, /// WUTPRIV WUTPRIV: u1, /// TSPRIV @@ -411695,9 +424119,10 @@ pub const types = struct { padding: u16, }), SMCR: mmio.Mmio(packed struct(u32) { - /// Alarm x protection - ALRDPROT: u1, - reserved2: u1, + /// (1/2 of ALRDPROT) Alarm x protection + @"ALRDPROT[0]": u1, + /// (2/2 of ALRDPROT) Alarm x protection + @"ALRDPROT[1]": u1, /// Wakeup timer protection WUTDPROT: u1, /// Timestamp protection @@ -411825,9 +424250,10 @@ pub const types = struct { reserved80: [8]u8, /// Status register SR: mmio.Mmio(packed struct(u32) { - /// Alarm flag - ALRF: ALRF, - reserved2: u1, + /// (1/2 of ALRF) Alarm flag + @"ALRF[0]": ALRF, + /// (2/2 of ALRF) Alarm flag + @"ALRF[1]": ALRF, /// Wakeup timer flag WUTF: WUTF, /// Timestamp flag @@ -411840,9 +424266,10 @@ pub const types = struct { }), /// Masked interrupt status register MISR: mmio.Mmio(packed struct(u32) { - /// Alarm masked flag - ALRMF: ALRMF, - reserved2: u1, + /// (1/2 of ALRMF) Alarm masked flag + @"ALRMF[0]": ALRMF, + /// (2/2 of ALRMF) Alarm masked flag + @"ALRMF[1]": ALRMF, /// Wakeup timer masked flag WUTMF: WUTMF, /// Timestamp masked flag @@ -411855,9 +424282,10 @@ pub const types = struct { }), /// Secure masked interrupt status register SMISR: mmio.Mmio(packed struct(u32) { - /// Alarm x interrupt secure masked flag - ALRMF: u1, - reserved2: u1, + /// (1/2 of ALRMF) Alarm x interrupt secure masked flag + @"ALRMF[0]": u1, + /// (2/2 of ALRMF) Alarm x interrupt secure masked flag + @"ALRMF[1]": u1, /// WUTMF WUTMF: u1, /// TSMF @@ -411870,9 +424298,10 @@ pub const types = struct { }), /// Status clear register SCR: mmio.Mmio(packed struct(u32) { - /// Clear alarm x flag - CALRF: CALRF, - reserved2: u1, + /// (1/2 of CALRF) Clear alarm x flag + @"CALRF[0]": CALRF, + /// (2/2 of CALRF) Clear alarm x flag + @"CALRF[1]": CALRF, /// Clear wakeup timer flag CWUTF: CALRF, /// Clear timestamp flag @@ -412234,16 +424663,18 @@ pub const types = struct { FMT: FMT, /// SSR underflow interrupt enable SSRUIE: u1, - /// Alarm enable - ALRE: u1, - reserved10: u1, + /// (1/2 of ALRE) Alarm enable + @"ALRE[0]": u1, + /// (2/2 of ALRE) Alarm enable + @"ALRE[1]": u1, /// Wakeup timer enable WUTE: u1, /// Timestamp enable TSE: u1, - /// Alarm interrupt enable - ALRIE: u1, - reserved14: u1, + /// (1/2 of ALRIE) Alarm interrupt enable + @"ALRIE[0]": u1, + /// (2/2 of ALRIE) Alarm interrupt enable + @"ALRIE[1]": u1, /// Wakeup timer interrupt enable WUTIE: u1, /// Timestamp interrupt enable @@ -412268,9 +424699,10 @@ pub const types = struct { TAMPTS: u1, /// Tamper detection output enable on TAMPALRM TAMPOE: u1, - /// ALRFCLR - ALRFCLR: u1, - reserved29: u1, + /// (1/2 of ALRFCLR) ALRFCLR + @"ALRFCLR[0]": u1, + /// (2/2 of ALRFCLR) ALRFCLR + @"ALRFCLR[1]": u1, /// TAMPALRM pull-up enable TAMPALRM_PU: u1, /// TAMPALRM output type @@ -412280,9 +424712,10 @@ pub const types = struct { }), /// Privilege mode control register PRIVCR: mmio.Mmio(packed struct(u32) { - /// ALRPRIV - ALRPRIV: u1, - reserved2: u1, + /// (1/2 of ALRPRIV) ALRPRIV + @"ALRPRIV[0]": u1, + /// (2/2 of ALRPRIV) ALRPRIV + @"ALRPRIV[1]": u1, /// WUTPRIV WUTPRIV: u1, /// TSPRIV @@ -412430,9 +424863,10 @@ pub const types = struct { reserved80: [8]u8, /// Status register SR: mmio.Mmio(packed struct(u32) { - /// Alarm flag - ALRF: ALRF, - reserved2: u1, + /// (1/2 of ALRF) Alarm flag + @"ALRF[0]": ALRF, + /// (2/2 of ALRF) Alarm flag + @"ALRF[1]": ALRF, /// Wakeup timer flag WUTF: WUTF, /// Timestamp flag @@ -412447,9 +424881,10 @@ pub const types = struct { }), /// Masked interrupt status register MISR: mmio.Mmio(packed struct(u32) { - /// Alarm masked flag - ALRMF: ALRMF, - reserved2: u1, + /// (1/2 of ALRMF) Alarm masked flag + @"ALRMF[0]": ALRMF, + /// (2/2 of ALRMF) Alarm masked flag + @"ALRMF[1]": ALRMF, /// Wakeup timer masked flag WUTMF: WUTMF, /// Timestamp masked flag @@ -412464,9 +424899,10 @@ pub const types = struct { }), /// Secure masked interrupt status register SMISR: mmio.Mmio(packed struct(u32) { - /// Alarm x interrupt secure masked flag - ALRMF: u1, - reserved2: u1, + /// (1/2 of ALRMF) Alarm x interrupt secure masked flag + @"ALRMF[0]": u1, + /// (2/2 of ALRMF) Alarm x interrupt secure masked flag + @"ALRMF[1]": u1, /// WUTMF WUTMF: u1, /// TSMF @@ -412481,9 +424917,10 @@ pub const types = struct { }), /// Status clear register SCR: mmio.Mmio(packed struct(u32) { - /// Clear alarm x flag - CALRF: CALRF, - reserved2: u1, + /// (1/2 of CALRF) Clear alarm x flag + @"CALRF[0]": CALRF, + /// (2/2 of CALRF) Clear alarm x flag + @"CALRF[1]": CALRF, /// Clear wakeup timer flag CWUTF: CALRF, /// Clear timestamp flag @@ -413839,18 +426276,38 @@ pub const types = struct { /// Number of microphones MICNBR: u2, reserved8: u2, - /// Clock enable of bitstream clock number 1 - CKEN: u1, - padding: u23, + /// (1/2 of CKEN) Clock enable of bitstream clock number 1 + @"CKEN[0]": u1, + /// (2/2 of CKEN) Clock enable of bitstream clock number 1 + @"CKEN[1]": u1, + padding: u22, }), /// PDM delay register PDMDLY: mmio.Mmio(packed struct(u32) { - /// Delay line adjust for first microphone of pair 1 - DLYML: u3, + /// (1/4 of DLYML) Delay line adjust for first microphone of pair 1 + @"DLYML[0]": u3, reserved4: u1, - /// Delay line adjust for second microphone of pair 1 - DLYMR: u3, - padding: u25, + /// (1/4 of DLYMR) Delay line adjust for second microphone of pair 1 + @"DLYMR[0]": u3, + reserved8: u1, + /// (2/4 of DLYML) Delay line adjust for first microphone of pair 1 + @"DLYML[1]": u3, + reserved12: u1, + /// (2/4 of DLYMR) Delay line adjust for second microphone of pair 1 + @"DLYMR[1]": u3, + reserved16: u1, + /// (3/4 of DLYML) Delay line adjust for first microphone of pair 1 + @"DLYML[2]": u3, + reserved20: u1, + /// (3/4 of DLYMR) Delay line adjust for second microphone of pair 1 + @"DLYMR[2]": u3, + reserved24: u1, + /// (4/4 of DLYML) Delay line adjust for first microphone of pair 1 + @"DLYML[3]": u3, + reserved28: u1, + /// (4/4 of DLYMR) Delay line adjust for second microphone of pair 1 + @"DLYMR[3]": u3, + padding: u1, }), }; }; @@ -414206,18 +426663,42 @@ pub const types = struct { /// Number of microphones MICNBR: u2, reserved8: u2, - /// Clock enable of bitstream clock number 1 - CKEN: u1, - padding: u23, + /// (1/4 of CKEN) Clock enable of bitstream clock number 1 + @"CKEN[0]": u1, + /// (2/4 of CKEN) Clock enable of bitstream clock number 1 + @"CKEN[1]": u1, + /// (3/4 of CKEN) Clock enable of bitstream clock number 1 + @"CKEN[2]": u1, + /// (4/4 of CKEN) Clock enable of bitstream clock number 1 + @"CKEN[3]": u1, + padding: u20, }), /// PDM delay register PDMDLY: mmio.Mmio(packed struct(u32) { - /// Delay line adjust for first microphone of pair 1 - DLYML: u3, + /// (1/4 of DLYML) Delay line adjust for first microphone of pair 1 + @"DLYML[0]": u3, reserved4: u1, - /// Delay line adjust for second microphone of pair 1 - DLYMR: u3, - padding: u25, + /// (1/4 of DLYMR) Delay line adjust for second microphone of pair 1 + @"DLYMR[0]": u3, + reserved8: u1, + /// (2/4 of DLYML) Delay line adjust for first microphone of pair 1 + @"DLYML[1]": u3, + reserved12: u1, + /// (2/4 of DLYMR) Delay line adjust for second microphone of pair 1 + @"DLYMR[1]": u3, + reserved16: u1, + /// (3/4 of DLYML) Delay line adjust for first microphone of pair 1 + @"DLYML[2]": u3, + reserved20: u1, + /// (3/4 of DLYMR) Delay line adjust for second microphone of pair 1 + @"DLYMR[2]": u3, + reserved24: u1, + /// (4/4 of DLYML) Delay line adjust for first microphone of pair 1 + @"DLYML[3]": u3, + reserved28: u1, + /// (4/4 of DLYMR) Delay line adjust for second microphone of pair 1 + @"DLYMR[3]": u3, + padding: u1, }), }; }; @@ -414575,18 +427056,38 @@ pub const types = struct { /// Number of microphones MICNBR: u2, reserved8: u2, - /// Clock enable of bitstream clock number 1 - CKEN: u1, - padding: u23, + /// (1/2 of CKEN) Clock enable of bitstream clock number 1 + @"CKEN[0]": u1, + /// (2/2 of CKEN) Clock enable of bitstream clock number 1 + @"CKEN[1]": u1, + padding: u22, }), /// PDM delay register PDMDLY: mmio.Mmio(packed struct(u32) { - /// Delay line adjust for first microphone of pair 1 - DLYML: u3, + /// (1/4 of DLYML) Delay line adjust for first microphone of pair 1 + @"DLYML[0]": u3, reserved4: u1, - /// Delay line adjust for second microphone of pair 1 - DLYMR: u3, - padding: u25, + /// (1/4 of DLYMR) Delay line adjust for second microphone of pair 1 + @"DLYMR[0]": u3, + reserved8: u1, + /// (2/4 of DLYML) Delay line adjust for first microphone of pair 1 + @"DLYML[1]": u3, + reserved12: u1, + /// (2/4 of DLYMR) Delay line adjust for second microphone of pair 1 + @"DLYMR[1]": u3, + reserved16: u1, + /// (3/4 of DLYML) Delay line adjust for first microphone of pair 1 + @"DLYML[2]": u3, + reserved20: u1, + /// (3/4 of DLYMR) Delay line adjust for second microphone of pair 1 + @"DLYMR[2]": u3, + reserved24: u1, + /// (4/4 of DLYML) Delay line adjust for first microphone of pair 1 + @"DLYML[3]": u3, + reserved28: u1, + /// (4/4 of DLYMR) Delay line adjust for second microphone of pair 1 + @"DLYMR[3]": u3, + padding: u1, }), }; }; @@ -414944,18 +427445,42 @@ pub const types = struct { /// Number of microphones MICNBR: u2, reserved8: u2, - /// Clock enable of bitstream clock number 1 - CKEN: u1, - padding: u23, + /// (1/4 of CKEN) Clock enable of bitstream clock number 1 + @"CKEN[0]": u1, + /// (2/4 of CKEN) Clock enable of bitstream clock number 1 + @"CKEN[1]": u1, + /// (3/4 of CKEN) Clock enable of bitstream clock number 1 + @"CKEN[2]": u1, + /// (4/4 of CKEN) Clock enable of bitstream clock number 1 + @"CKEN[3]": u1, + padding: u20, }), /// PDM delay register PDMDLY: mmio.Mmio(packed struct(u32) { - /// Delay line adjust for first microphone of pair 1 - DLYML: u3, + /// (1/4 of DLYML) Delay line adjust for first microphone of pair 1 + @"DLYML[0]": u3, reserved4: u1, - /// Delay line adjust for second microphone of pair 1 - DLYMR: u3, - padding: u25, + /// (1/4 of DLYMR) Delay line adjust for second microphone of pair 1 + @"DLYMR[0]": u3, + reserved8: u1, + /// (2/4 of DLYML) Delay line adjust for first microphone of pair 1 + @"DLYML[1]": u3, + reserved12: u1, + /// (2/4 of DLYMR) Delay line adjust for second microphone of pair 1 + @"DLYMR[1]": u3, + reserved16: u1, + /// (3/4 of DLYML) Delay line adjust for first microphone of pair 1 + @"DLYML[2]": u3, + reserved20: u1, + /// (3/4 of DLYMR) Delay line adjust for second microphone of pair 1 + @"DLYMR[2]": u3, + reserved24: u1, + /// (4/4 of DLYML) Delay line adjust for first microphone of pair 1 + @"DLYML[3]": u3, + reserved28: u1, + /// (4/4 of DLYMR) Delay line adjust for second microphone of pair 1 + @"DLYMR[3]": u3, + padding: u1, }), }; }; @@ -415091,14 +427616,35 @@ pub const types = struct { reserved64: [20]u8, /// channel configuration register 1. CONFCHR1: mmio.Mmio(packed struct(u32) { - /// CONFCH0. - CONFCH: u2, - padding: u30, + /// (1/8 of CONFCH) CONFCH0. + @"CONFCH[0]": u2, + reserved4: u2, + /// (2/8 of CONFCH) CONFCH0. + @"CONFCH[1]": u2, + reserved8: u2, + /// (3/8 of CONFCH) CONFCH0. + @"CONFCH[2]": u2, + reserved12: u2, + /// (4/8 of CONFCH) CONFCH0. + @"CONFCH[3]": u2, + reserved16: u2, + /// (5/8 of CONFCH) CONFCH0. + @"CONFCH[4]": u2, + reserved20: u2, + /// (6/8 of CONFCH) CONFCH0. + @"CONFCH[5]": u2, + reserved24: u2, + /// (7/8 of CONFCH) CONFCH0. + @"CONFCH[6]": u2, + reserved28: u2, + /// (8/8 of CONFCH) CONFCH0. + @"CONFCH[7]": u2, + padding: u2, }), /// channel configuration register 2. CONFCHR2: mmio.Mmio(packed struct(u32) { - /// Channel 8 configuration. - CONFCH: u2, + /// (1/1 of CONFCH) Channel 8 configuration. + @"CONFCH[0]": u2, padding: u30, }), reserved96: [24]u8, @@ -418365,21 +430911,47 @@ pub const types = struct { }), /// interrupt line 5 status register ITLINE5: mmio.Mmio(packed struct(u32) { - /// EXTI - EXTI: u1, - padding: u31, + /// (1/2 of EXTI) EXTI + @"EXTI[0]": u1, + /// (2/2 of EXTI) EXTI + @"EXTI[1]": u1, + padding: u30, }), /// interrupt line 6 status register ITLINE6: mmio.Mmio(packed struct(u32) { - /// EXTI - EXTI: u1, - padding: u31, + /// (1/2 of EXTI) EXTI + @"EXTI[0]": u1, + /// (2/2 of EXTI) EXTI + @"EXTI[1]": u1, + padding: u30, }), /// interrupt line 7 status register ITLINE7: mmio.Mmio(packed struct(u32) { - /// EXTI - EXTI: u1, - padding: u31, + /// (1/12 of EXTI) EXTI + @"EXTI[0]": u1, + /// (2/12 of EXTI) EXTI + @"EXTI[1]": u1, + /// (3/12 of EXTI) EXTI + @"EXTI[2]": u1, + /// (4/12 of EXTI) EXTI + @"EXTI[3]": u1, + /// (5/12 of EXTI) EXTI + @"EXTI[4]": u1, + /// (6/12 of EXTI) EXTI + @"EXTI[5]": u1, + /// (7/12 of EXTI) EXTI + @"EXTI[6]": u1, + /// (8/12 of EXTI) EXTI + @"EXTI[7]": u1, + /// (9/12 of EXTI) EXTI + @"EXTI[8]": u1, + /// (10/12 of EXTI) EXTI + @"EXTI[9]": u1, + /// (11/12 of EXTI) EXTI + @"EXTI[10]": u1, + /// (12/12 of EXTI) EXTI + @"EXTI[11]": u1, + padding: u20, }), reserved164: [4]u8, /// interrupt line 9 status register @@ -418573,9 +431145,15 @@ pub const types = struct { reserved8: [4]u8, /// external interrupt configuration register 1 EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI configuration bits - EXTI: u4, - padding: u28, + /// (1/4 of EXTI) EXTI configuration bits + @"EXTI[0]": u4, + /// (2/4 of EXTI) EXTI configuration bits + @"EXTI[1]": u4, + /// (3/4 of EXTI) EXTI configuration bits + @"EXTI[2]": u4, + /// (4/4 of EXTI) EXTI configuration bits + @"EXTI[3]": u4, + padding: u16, }), /// configuration register 2 CFGR2: mmio.Mmio(packed struct(u32) { @@ -418622,9 +431200,15 @@ pub const types = struct { }), /// external interrupt configuration register 1 EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI x configuration (x = 0 to 3) - EXTI: u4, - padding: u28, + /// (1/4 of EXTI) EXTI x configuration (x = 0 to 3) + @"EXTI[0]": u4, + /// (2/4 of EXTI) EXTI x configuration (x = 0 to 3) + @"EXTI[1]": u4, + /// (3/4 of EXTI) EXTI x configuration (x = 0 to 3) + @"EXTI[2]": u4, + /// (4/4 of EXTI) EXTI x configuration (x = 0 to 3) + @"EXTI[3]": u4, + padding: u16, }), reserved32: [8]u8, /// Compensation cell control register @@ -418864,21 +431448,66 @@ pub const types = struct { /// I2C3 Fast Mode Plus 0: FM+ mode is controlled by I2C_Pxx_FMP bits only 1: FM+ mode is enabled on all I2C3 pins selected through selection trhough IOPORT control registers AF selection bits I2C3_FMP: FMP, reserved26: u1, - /// Idx 0: Invalid operation interrupt enable; Idx 1: Devide-by-zero interrupt enable; Idx 2: Underflow interrupt enable; Idx 3: Overflow interrupt enable; Idx 4: Input denormal interrupt enable; Idx 5: Inexact interrupt enable - FPU_IE: u1, - padding: u5, + /// (1/6 of FPU_IE) Idx 0: Invalid operation interrupt enable; Idx 1: Devide-by-zero interrupt enable; Idx 2: Underflow interrupt enable; Idx 3: Overflow interrupt enable; Idx 4: Input denormal interrupt enable; Idx 5: Inexact interrupt enable + @"FPU_IE[0]": u1, + /// (2/6 of FPU_IE) Idx 0: Invalid operation interrupt enable; Idx 1: Devide-by-zero interrupt enable; Idx 2: Underflow interrupt enable; Idx 3: Overflow interrupt enable; Idx 4: Input denormal interrupt enable; Idx 5: Inexact interrupt enable + @"FPU_IE[1]": u1, + /// (3/6 of FPU_IE) Idx 0: Invalid operation interrupt enable; Idx 1: Devide-by-zero interrupt enable; Idx 2: Underflow interrupt enable; Idx 3: Overflow interrupt enable; Idx 4: Input denormal interrupt enable; Idx 5: Inexact interrupt enable + @"FPU_IE[2]": u1, + /// (4/6 of FPU_IE) Idx 0: Invalid operation interrupt enable; Idx 1: Devide-by-zero interrupt enable; Idx 2: Underflow interrupt enable; Idx 3: Overflow interrupt enable; Idx 4: Input denormal interrupt enable; Idx 5: Inexact interrupt enable + @"FPU_IE[3]": u1, + /// (5/6 of FPU_IE) Idx 0: Invalid operation interrupt enable; Idx 1: Devide-by-zero interrupt enable; Idx 2: Underflow interrupt enable; Idx 3: Overflow interrupt enable; Idx 4: Input denormal interrupt enable; Idx 5: Inexact interrupt enable + @"FPU_IE[4]": u1, + /// (6/6 of FPU_IE) Idx 0: Invalid operation interrupt enable; Idx 1: Devide-by-zero interrupt enable; Idx 2: Underflow interrupt enable; Idx 3: Overflow interrupt enable; Idx 4: Input denormal interrupt enable; Idx 5: Inexact interrupt enable + @"FPU_IE[5]": u1, }), /// CCM SRAM protection register RCR: mmio.Mmio(packed struct(u32) { - /// CCM SRAM page x write protection enabled - PAGE_WP: u1, - padding: u31, + /// (1/16 of PAGE_WP) CCM SRAM page x write protection enabled + @"PAGE_WP[0]": u1, + /// (2/16 of PAGE_WP) CCM SRAM page x write protection enabled + @"PAGE_WP[1]": u1, + /// (3/16 of PAGE_WP) CCM SRAM page x write protection enabled + @"PAGE_WP[2]": u1, + /// (4/16 of PAGE_WP) CCM SRAM page x write protection enabled + @"PAGE_WP[3]": u1, + /// (5/16 of PAGE_WP) CCM SRAM page x write protection enabled + @"PAGE_WP[4]": u1, + /// (6/16 of PAGE_WP) CCM SRAM page x write protection enabled + @"PAGE_WP[5]": u1, + /// (7/16 of PAGE_WP) CCM SRAM page x write protection enabled + @"PAGE_WP[6]": u1, + /// (8/16 of PAGE_WP) CCM SRAM page x write protection enabled + @"PAGE_WP[7]": u1, + /// (9/16 of PAGE_WP) CCM SRAM page x write protection enabled + @"PAGE_WP[8]": u1, + /// (10/16 of PAGE_WP) CCM SRAM page x write protection enabled + @"PAGE_WP[9]": u1, + /// (11/16 of PAGE_WP) CCM SRAM page x write protection enabled + @"PAGE_WP[10]": u1, + /// (12/16 of PAGE_WP) CCM SRAM page x write protection enabled + @"PAGE_WP[11]": u1, + /// (13/16 of PAGE_WP) CCM SRAM page x write protection enabled + @"PAGE_WP[12]": u1, + /// (14/16 of PAGE_WP) CCM SRAM page x write protection enabled + @"PAGE_WP[13]": u1, + /// (15/16 of PAGE_WP) CCM SRAM page x write protection enabled + @"PAGE_WP[14]": u1, + /// (16/16 of PAGE_WP) CCM SRAM page x write protection enabled + @"PAGE_WP[15]": u1, + padding: u16, }), /// external interrupt configuration register EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI x configuration - EXTI: u4, - padding: u28, + /// (1/4 of EXTI) EXTI x configuration + @"EXTI[0]": u4, + /// (2/4 of EXTI) EXTI x configuration + @"EXTI[1]": u4, + /// (3/4 of EXTI) EXTI x configuration + @"EXTI[2]": u4, + /// (4/4 of EXTI) EXTI x configuration + @"EXTI[3]": u4, + padding: u16, }), /// configuration register 2 CFGR2: mmio.Mmio(packed struct(u32) { @@ -418983,9 +431612,15 @@ pub const types = struct { }), /// external interrupt configuration register EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI x configuration - EXTI: u4, - padding: u28, + /// (1/4 of EXTI) EXTI x configuration + @"EXTI[0]": u4, + /// (2/4 of EXTI) EXTI x configuration + @"EXTI[1]": u4, + /// (3/4 of EXTI) EXTI x configuration + @"EXTI[2]": u4, + /// (4/4 of EXTI) EXTI x configuration + @"EXTI[3]": u4, + padding: u16, }), reserved32: [8]u8, /// Compensation cell control register @@ -419047,9 +431682,15 @@ pub const types = struct { }), /// external interrupt configuration register 1 EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI x configuration (x = 0 to 3) - EXTI: u4, - padding: u28, + /// (1/4 of EXTI) EXTI x configuration (x = 0 to 3) + @"EXTI[0]": u4, + /// (2/4 of EXTI) EXTI x configuration (x = 0 to 3) + @"EXTI[1]": u4, + /// (3/4 of EXTI) EXTI x configuration (x = 0 to 3) + @"EXTI[2]": u4, + /// (4/4 of EXTI) EXTI x configuration (x = 0 to 3) + @"EXTI[3]": u4, + padding: u16, }), reserved32: [8]u8, /// Compensation cell control register @@ -419464,9 +432105,15 @@ pub const types = struct { }), /// external interrupt configuration register 1 EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI x configuration - EXTI: u4, - padding: u28, + /// (1/4 of EXTI) EXTI x configuration + @"EXTI[0]": u4, + /// (2/4 of EXTI) EXTI x configuration + @"EXTI[1]": u4, + /// (3/4 of EXTI) EXTI x configuration + @"EXTI[2]": u4, + /// (4/4 of EXTI) EXTI x configuration + @"EXTI[3]": u4, + padding: u16, }), /// CCM SRAM control and status register SCSR: mmio.Mmio(packed struct(u32) { @@ -419493,9 +432140,70 @@ pub const types = struct { }), /// SRAM Write protection register 1 SWPR: mmio.Mmio(packed struct(u32) { - /// Write protection - Page_WP: u1, - padding: u31, + /// (1/32 of Page_WP) Write protection + @"Page_WP[0]": u1, + /// (2/32 of Page_WP) Write protection + @"Page_WP[1]": u1, + /// (3/32 of Page_WP) Write protection + @"Page_WP[2]": u1, + /// (4/32 of Page_WP) Write protection + @"Page_WP[3]": u1, + /// (5/32 of Page_WP) Write protection + @"Page_WP[4]": u1, + /// (6/32 of Page_WP) Write protection + @"Page_WP[5]": u1, + /// (7/32 of Page_WP) Write protection + @"Page_WP[6]": u1, + /// (8/32 of Page_WP) Write protection + @"Page_WP[7]": u1, + /// (9/32 of Page_WP) Write protection + @"Page_WP[8]": u1, + /// (10/32 of Page_WP) Write protection + @"Page_WP[9]": u1, + /// (11/32 of Page_WP) Write protection + @"Page_WP[10]": u1, + /// (12/32 of Page_WP) Write protection + @"Page_WP[11]": u1, + /// (13/32 of Page_WP) Write protection + @"Page_WP[12]": u1, + /// (14/32 of Page_WP) Write protection + @"Page_WP[13]": u1, + /// (15/32 of Page_WP) Write protection + @"Page_WP[14]": u1, + /// (16/32 of Page_WP) Write protection + @"Page_WP[15]": u1, + /// (17/32 of Page_WP) Write protection + @"Page_WP[16]": u1, + /// (18/32 of Page_WP) Write protection + @"Page_WP[17]": u1, + /// (19/32 of Page_WP) Write protection + @"Page_WP[18]": u1, + /// (20/32 of Page_WP) Write protection + @"Page_WP[19]": u1, + /// (21/32 of Page_WP) Write protection + @"Page_WP[20]": u1, + /// (22/32 of Page_WP) Write protection + @"Page_WP[21]": u1, + /// (23/32 of Page_WP) Write protection + @"Page_WP[22]": u1, + /// (24/32 of Page_WP) Write protection + @"Page_WP[23]": u1, + /// (25/32 of Page_WP) Write protection + @"Page_WP[24]": u1, + /// (26/32 of Page_WP) Write protection + @"Page_WP[25]": u1, + /// (27/32 of Page_WP) Write protection + @"Page_WP[26]": u1, + /// (28/32 of Page_WP) Write protection + @"Page_WP[27]": u1, + /// (29/32 of Page_WP) Write protection + @"Page_WP[28]": u1, + /// (30/32 of Page_WP) Write protection + @"Page_WP[29]": u1, + /// (31/32 of Page_WP) Write protection + @"Page_WP[30]": u1, + /// (32/32 of Page_WP) Write protection + @"Page_WP[31]": u1, }), /// SRAM2 Key Register SKR: mmio.Mmio(packed struct(u32) { @@ -419682,14 +432390,20 @@ pub const types = struct { reserved272: [4]u8, /// SBS compensation cell for I/Os control and status register CCCSR: mmio.Mmio(packed struct(u32) { - /// enable compensation cell for VDDIO power rail This bit enables the I/O compensation cell. - EN: u1, - /// code selection for VDDIO power rail (reset value set to 1) This bit selects the code to be applied for the I/O compensation cell. - CS: CS, - reserved8: u6, - /// VDDIO compensation cell ready flag This bit provides the status of the compensation cell. - RDY: u1, - padding: u23, + /// (1/2 of EN) enable compensation cell for VDDIO power rail This bit enables the I/O compensation cell. + @"EN[0]": u1, + /// (1/2 of CS) code selection for VDDIO power rail (reset value set to 1) This bit selects the code to be applied for the I/O compensation cell. + @"CS[0]": CS, + /// (2/2 of EN) enable compensation cell for VDDIO power rail This bit enables the I/O compensation cell. + @"EN[1]": u1, + /// (2/2 of CS) code selection for VDDIO power rail (reset value set to 1) This bit selects the code to be applied for the I/O compensation cell. + @"CS[1]": CS, + reserved8: u4, + /// (1/2 of RDY) VDDIO compensation cell ready flag This bit provides the status of the compensation cell. + @"RDY[0]": u1, + /// (2/2 of RDY) VDDIO compensation cell ready flag This bit provides the status of the compensation cell. + @"RDY[1]": u1, + padding: u22, }), /// SBS compensation cell for I/Os value register CCVALR: mmio.Mmio(packed struct(u32) { @@ -419867,14 +432581,20 @@ pub const types = struct { reserved272: [4]u8, /// SBS compensation cell for I/Os control and status register CCCSR: mmio.Mmio(packed struct(u32) { - /// enable compensation cell for VDDIO power rail This bit enables the I/O compensation cell. - EN: u1, - /// code selection for VDDIO power rail (reset value set to 1) This bit selects the code to be applied for the I/O compensation cell. - CS: CS, - reserved8: u6, - /// VDDIO compensation cell ready flag This bit provides the status of the compensation cell. - RDY: u1, - padding: u23, + /// (1/2 of EN) enable compensation cell for VDDIO power rail This bit enables the I/O compensation cell. + @"EN[0]": u1, + /// (1/2 of CS) code selection for VDDIO power rail (reset value set to 1) This bit selects the code to be applied for the I/O compensation cell. + @"CS[0]": CS, + /// (2/2 of EN) enable compensation cell for VDDIO power rail This bit enables the I/O compensation cell. + @"EN[1]": u1, + /// (2/2 of CS) code selection for VDDIO power rail (reset value set to 1) This bit selects the code to be applied for the I/O compensation cell. + @"CS[1]": CS, + reserved8: u4, + /// (1/2 of RDY) VDDIO compensation cell ready flag This bit provides the status of the compensation cell. + @"RDY[0]": u1, + /// (2/2 of RDY) VDDIO compensation cell ready flag This bit provides the status of the compensation cell. + @"RDY[1]": u1, + padding: u22, }), /// SBS compensation cell for I/Os value register CCVALR: mmio.Mmio(packed struct(u32) { @@ -419992,9 +432712,15 @@ pub const types = struct { }), /// external interrupt configuration register EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI x configuration (x = 4 to 7) - EXTI: u4, - padding: u28, + /// (1/4 of EXTI) EXTI x configuration (x = 4 to 7) + @"EXTI[0]": u4, + /// (2/4 of EXTI) EXTI x configuration (x = 4 to 7) + @"EXTI[1]": u4, + /// (3/4 of EXTI) EXTI x configuration (x = 4 to 7) + @"EXTI[2]": u4, + /// (4/4 of EXTI) EXTI x configuration (x = 4 to 7) + @"EXTI[3]": u4, + padding: u16, }), reserved32: [8]u8, /// compensation cell control/status register @@ -420234,9 +432960,15 @@ pub const types = struct { }), /// external interrupt configuration register EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI x configuration (x = 4 to 7) - EXTI: u4, - padding: u28, + /// (1/4 of EXTI) EXTI x configuration (x = 4 to 7) + @"EXTI[0]": u4, + /// (2/4 of EXTI) EXTI x configuration (x = 4 to 7) + @"EXTI[1]": u4, + /// (3/4 of EXTI) EXTI x configuration (x = 4 to 7) + @"EXTI[2]": u4, + /// (4/4 of EXTI) EXTI x configuration (x = 4 to 7) + @"EXTI[3]": u4, + padding: u16, }), reserved32: [8]u8, /// compensation cell control/status register @@ -420638,9 +433370,15 @@ pub const types = struct { reserved304: [12]u8, /// external interrupt configuration register EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI x configuration (x = 4 to 7) - EXTI: u4, - padding: u28, + /// (1/4 of EXTI) EXTI x configuration (x = 4 to 7) + @"EXTI[0]": u4, + /// (2/4 of EXTI) EXTI x configuration (x = 4 to 7) + @"EXTI[1]": u4, + /// (3/4 of EXTI) EXTI x configuration (x = 4 to 7) + @"EXTI[2]": u4, + /// (4/4 of EXTI) EXTI x configuration (x = 4 to 7) + @"EXTI[3]": u4, + padding: u16, }), }; }; @@ -420683,9 +433421,15 @@ pub const types = struct { }), /// external interrupt configuration register EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI configuration bits - EXTI: u4, - padding: u28, + /// (1/4 of EXTI) EXTI configuration bits + @"EXTI[0]": u4, + /// (2/4 of EXTI) EXTI configuration bits + @"EXTI[1]": u4, + /// (3/4 of EXTI) EXTI configuration bits + @"EXTI[2]": u4, + /// (4/4 of EXTI) EXTI configuration bits + @"EXTI[3]": u4, + padding: u16, }), reserved32: [8]u8, /// CFGR3 @@ -420736,9 +433480,15 @@ pub const types = struct { }), /// external interrupt configuration register 1 EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI x configuration (x = 8 to 11) - EXTI: u4, - padding: u28, + /// (1/4 of EXTI) EXTI x configuration (x = 8 to 11) + @"EXTI[0]": u4, + /// (2/4 of EXTI) EXTI x configuration (x = 8 to 11) + @"EXTI[1]": u4, + /// (3/4 of EXTI) EXTI x configuration (x = 8 to 11) + @"EXTI[2]": u4, + /// (4/4 of EXTI) EXTI x configuration (x = 8 to 11) + @"EXTI[3]": u4, + padding: u16, }), }; }; @@ -420785,9 +433535,15 @@ pub const types = struct { }), /// external interrupt configuration register 1 EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI12 configuration bits - EXTI: u4, - padding: u28, + /// (1/4 of EXTI) EXTI12 configuration bits + @"EXTI[0]": u4, + /// (2/4 of EXTI) EXTI12 configuration bits + @"EXTI[1]": u4, + /// (3/4 of EXTI) EXTI12 configuration bits + @"EXTI[2]": u4, + /// (4/4 of EXTI) EXTI12 configuration bits + @"EXTI[3]": u4, + padding: u16, }), /// SCSR SCSR: mmio.Mmio(packed struct(u32) { @@ -420814,9 +433570,70 @@ pub const types = struct { }), /// SWPR SWPR: mmio.Mmio(packed struct(u32) { - /// SRAWM2 write protection. - PWP: u1, - padding: u31, + /// (1/32 of PWP) SRAWM2 write protection. + @"PWP[0]": u1, + /// (2/32 of PWP) SRAWM2 write protection. + @"PWP[1]": u1, + /// (3/32 of PWP) SRAWM2 write protection. + @"PWP[2]": u1, + /// (4/32 of PWP) SRAWM2 write protection. + @"PWP[3]": u1, + /// (5/32 of PWP) SRAWM2 write protection. + @"PWP[4]": u1, + /// (6/32 of PWP) SRAWM2 write protection. + @"PWP[5]": u1, + /// (7/32 of PWP) SRAWM2 write protection. + @"PWP[6]": u1, + /// (8/32 of PWP) SRAWM2 write protection. + @"PWP[7]": u1, + /// (9/32 of PWP) SRAWM2 write protection. + @"PWP[8]": u1, + /// (10/32 of PWP) SRAWM2 write protection. + @"PWP[9]": u1, + /// (11/32 of PWP) SRAWM2 write protection. + @"PWP[10]": u1, + /// (12/32 of PWP) SRAWM2 write protection. + @"PWP[11]": u1, + /// (13/32 of PWP) SRAWM2 write protection. + @"PWP[12]": u1, + /// (14/32 of PWP) SRAWM2 write protection. + @"PWP[13]": u1, + /// (15/32 of PWP) SRAWM2 write protection. + @"PWP[14]": u1, + /// (16/32 of PWP) SRAWM2 write protection. + @"PWP[15]": u1, + /// (17/32 of PWP) SRAWM2 write protection. + @"PWP[16]": u1, + /// (18/32 of PWP) SRAWM2 write protection. + @"PWP[17]": u1, + /// (19/32 of PWP) SRAWM2 write protection. + @"PWP[18]": u1, + /// (20/32 of PWP) SRAWM2 write protection. + @"PWP[19]": u1, + /// (21/32 of PWP) SRAWM2 write protection. + @"PWP[20]": u1, + /// (22/32 of PWP) SRAWM2 write protection. + @"PWP[21]": u1, + /// (23/32 of PWP) SRAWM2 write protection. + @"PWP[22]": u1, + /// (24/32 of PWP) SRAWM2 write protection. + @"PWP[23]": u1, + /// (25/32 of PWP) SRAWM2 write protection. + @"PWP[24]": u1, + /// (26/32 of PWP) SRAWM2 write protection. + @"PWP[25]": u1, + /// (27/32 of PWP) SRAWM2 write protection. + @"PWP[26]": u1, + /// (28/32 of PWP) SRAWM2 write protection. + @"PWP[27]": u1, + /// (29/32 of PWP) SRAWM2 write protection. + @"PWP[28]": u1, + /// (30/32 of PWP) SRAWM2 write protection. + @"PWP[29]": u1, + /// (31/32 of PWP) SRAWM2 write protection. + @"PWP[30]": u1, + /// (32/32 of PWP) SRAWM2 write protection. + @"PWP[31]": u1, }), /// SKR SKR: mmio.Mmio(packed struct(u32) { @@ -421634,9 +434451,18 @@ pub const types = struct { }), /// external interrupt configuration register 1 EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI 0 configuration bits - EXTI: u3, - padding: u29, + /// (1/4 of EXTI) EXTI 0 configuration bits + @"EXTI[0]": u3, + reserved4: u1, + /// (2/4 of EXTI) EXTI 0 configuration bits + @"EXTI[1]": u3, + reserved8: u1, + /// (3/4 of EXTI) EXTI 0 configuration bits + @"EXTI[2]": u3, + reserved12: u1, + /// (4/4 of EXTI) EXTI 0 configuration bits + @"EXTI[3]": u3, + padding: u17, }), /// SCSR SCSR: mmio.Mmio(packed struct(u32) { @@ -421665,9 +434491,70 @@ pub const types = struct { }), /// SRAM2 write protection register SWPR: mmio.Mmio(packed struct(u32) { - /// P0WP - PWP: u1, - padding: u31, + /// (1/32 of PWP) P0WP + @"PWP[0]": u1, + /// (2/32 of PWP) P0WP + @"PWP[1]": u1, + /// (3/32 of PWP) P0WP + @"PWP[2]": u1, + /// (4/32 of PWP) P0WP + @"PWP[3]": u1, + /// (5/32 of PWP) P0WP + @"PWP[4]": u1, + /// (6/32 of PWP) P0WP + @"PWP[5]": u1, + /// (7/32 of PWP) P0WP + @"PWP[6]": u1, + /// (8/32 of PWP) P0WP + @"PWP[7]": u1, + /// (9/32 of PWP) P0WP + @"PWP[8]": u1, + /// (10/32 of PWP) P0WP + @"PWP[9]": u1, + /// (11/32 of PWP) P0WP + @"PWP[10]": u1, + /// (12/32 of PWP) P0WP + @"PWP[11]": u1, + /// (13/32 of PWP) P0WP + @"PWP[12]": u1, + /// (14/32 of PWP) P0WP + @"PWP[13]": u1, + /// (15/32 of PWP) P0WP + @"PWP[14]": u1, + /// (16/32 of PWP) P0WP + @"PWP[15]": u1, + /// (17/32 of PWP) P0WP + @"PWP[16]": u1, + /// (18/32 of PWP) P0WP + @"PWP[17]": u1, + /// (19/32 of PWP) P0WP + @"PWP[18]": u1, + /// (20/32 of PWP) P0WP + @"PWP[19]": u1, + /// (21/32 of PWP) P0WP + @"PWP[20]": u1, + /// (22/32 of PWP) P0WP + @"PWP[21]": u1, + /// (23/32 of PWP) P0WP + @"PWP[22]": u1, + /// (24/32 of PWP) P0WP + @"PWP[23]": u1, + /// (25/32 of PWP) P0WP + @"PWP[24]": u1, + /// (26/32 of PWP) P0WP + @"PWP[25]": u1, + /// (27/32 of PWP) P0WP + @"PWP[26]": u1, + /// (28/32 of PWP) P0WP + @"PWP[27]": u1, + /// (29/32 of PWP) P0WP + @"PWP[28]": u1, + /// (30/32 of PWP) P0WP + @"PWP[29]": u1, + /// (31/32 of PWP) P0WP + @"PWP[30]": u1, + /// (32/32 of PWP) P0WP + @"PWP[31]": u1, }), /// SKR SKR: mmio.Mmio(packed struct(u32) { @@ -421677,9 +434564,70 @@ pub const types = struct { }), /// SRAM2 write protection register 2 SWPR2: mmio.Mmio(packed struct(u32) { - /// P32WP - PWP: u1, - padding: u31, + /// (1/32 of PWP) P32WP + @"PWP[0]": u1, + /// (2/32 of PWP) P32WP + @"PWP[1]": u1, + /// (3/32 of PWP) P32WP + @"PWP[2]": u1, + /// (4/32 of PWP) P32WP + @"PWP[3]": u1, + /// (5/32 of PWP) P32WP + @"PWP[4]": u1, + /// (6/32 of PWP) P32WP + @"PWP[5]": u1, + /// (7/32 of PWP) P32WP + @"PWP[6]": u1, + /// (8/32 of PWP) P32WP + @"PWP[7]": u1, + /// (9/32 of PWP) P32WP + @"PWP[8]": u1, + /// (10/32 of PWP) P32WP + @"PWP[9]": u1, + /// (11/32 of PWP) P32WP + @"PWP[10]": u1, + /// (12/32 of PWP) P32WP + @"PWP[11]": u1, + /// (13/32 of PWP) P32WP + @"PWP[12]": u1, + /// (14/32 of PWP) P32WP + @"PWP[13]": u1, + /// (15/32 of PWP) P32WP + @"PWP[14]": u1, + /// (16/32 of PWP) P32WP + @"PWP[15]": u1, + /// (17/32 of PWP) P32WP + @"PWP[16]": u1, + /// (18/32 of PWP) P32WP + @"PWP[17]": u1, + /// (19/32 of PWP) P32WP + @"PWP[18]": u1, + /// (20/32 of PWP) P32WP + @"PWP[19]": u1, + /// (21/32 of PWP) P32WP + @"PWP[20]": u1, + /// (22/32 of PWP) P32WP + @"PWP[21]": u1, + /// (23/32 of PWP) P32WP + @"PWP[22]": u1, + /// (24/32 of PWP) P32WP + @"PWP[23]": u1, + /// (25/32 of PWP) P32WP + @"PWP[24]": u1, + /// (26/32 of PWP) P32WP + @"PWP[25]": u1, + /// (27/32 of PWP) P32WP + @"PWP[26]": u1, + /// (28/32 of PWP) P32WP + @"PWP[27]": u1, + /// (29/32 of PWP) P32WP + @"PWP[28]": u1, + /// (30/32 of PWP) P32WP + @"PWP[29]": u1, + /// (31/32 of PWP) P32WP + @"PWP[30]": u1, + /// (32/32 of PWP) P32WP + @"PWP[31]": u1, }), reserved256: [212]u8, /// CPU1 interrupt mask register 1 @@ -421803,9 +434751,10 @@ pub const types = struct { }), /// secure IP control register SIPCR: mmio.Mmio(packed struct(u32) { - /// Enable AES1 KEY[7:0] security. - SAES: u1, - reserved2: u1, + /// (1/2 of SAES) Enable AES1 KEY[7:0] security. + @"SAES[0]": u1, + /// (2/2 of SAES) Enable AES1 KEY[7:0] security. + @"SAES[1]": u1, /// Enable PKA security SPKA: u1, /// Enable True RNG security @@ -421962,9 +434911,18 @@ pub const types = struct { }), /// external interrupt configuration register 1 EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI12 configuration bits - EXTI: u3, - padding: u29, + /// (1/4 of EXTI) EXTI12 configuration bits + @"EXTI[0]": u3, + reserved4: u1, + /// (2/4 of EXTI) EXTI12 configuration bits + @"EXTI[1]": u3, + reserved8: u1, + /// (3/4 of EXTI) EXTI12 configuration bits + @"EXTI[2]": u3, + reserved12: u1, + /// (4/4 of EXTI) EXTI12 configuration bits + @"EXTI[3]": u3, + padding: u17, }), /// SCSR SCSR: mmio.Mmio(packed struct(u32) { @@ -421994,9 +434952,70 @@ pub const types = struct { }), /// SWPR SWPR: mmio.Mmio(packed struct(u32) { - /// SRAM2 1Kbyte page 0 write protection - PWP: u1, - padding: u31, + /// (1/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[0]": u1, + /// (2/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[1]": u1, + /// (3/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[2]": u1, + /// (4/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[3]": u1, + /// (5/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[4]": u1, + /// (6/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[5]": u1, + /// (7/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[6]": u1, + /// (8/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[7]": u1, + /// (9/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[8]": u1, + /// (10/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[9]": u1, + /// (11/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[10]": u1, + /// (12/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[11]": u1, + /// (13/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[12]": u1, + /// (14/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[13]": u1, + /// (15/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[14]": u1, + /// (16/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[15]": u1, + /// (17/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[16]": u1, + /// (18/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[17]": u1, + /// (19/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[18]": u1, + /// (20/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[19]": u1, + /// (21/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[20]": u1, + /// (22/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[21]": u1, + /// (23/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[22]": u1, + /// (24/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[23]": u1, + /// (25/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[24]": u1, + /// (26/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[25]": u1, + /// (27/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[26]": u1, + /// (28/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[27]": u1, + /// (29/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[28]": u1, + /// (30/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[29]": u1, + /// (31/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[30]": u1, + /// (32/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[31]": u1, }), /// SKR SKR: mmio.Mmio(packed struct(u32) { @@ -422191,9 +435210,18 @@ pub const types = struct { }), /// external interrupt configuration register 1 EXTICR: [4]mmio.Mmio(packed struct(u32) { - /// EXTI12 configuration bits - EXTI: u3, - padding: u29, + /// (1/4 of EXTI) EXTI12 configuration bits + @"EXTI[0]": u3, + reserved4: u1, + /// (2/4 of EXTI) EXTI12 configuration bits + @"EXTI[1]": u3, + reserved8: u1, + /// (3/4 of EXTI) EXTI12 configuration bits + @"EXTI[2]": u3, + reserved12: u1, + /// (4/4 of EXTI) EXTI12 configuration bits + @"EXTI[3]": u3, + padding: u17, }), /// SCSR SCSR: mmio.Mmio(packed struct(u32) { @@ -422223,9 +435251,70 @@ pub const types = struct { }), /// SWPR SWPR: mmio.Mmio(packed struct(u32) { - /// SRAM2 1Kbyte page 0 write protection - PWP: u1, - padding: u31, + /// (1/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[0]": u1, + /// (2/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[1]": u1, + /// (3/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[2]": u1, + /// (4/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[3]": u1, + /// (5/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[4]": u1, + /// (6/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[5]": u1, + /// (7/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[6]": u1, + /// (8/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[7]": u1, + /// (9/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[8]": u1, + /// (10/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[9]": u1, + /// (11/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[10]": u1, + /// (12/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[11]": u1, + /// (13/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[12]": u1, + /// (14/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[13]": u1, + /// (15/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[14]": u1, + /// (16/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[15]": u1, + /// (17/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[16]": u1, + /// (18/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[17]": u1, + /// (19/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[18]": u1, + /// (20/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[19]": u1, + /// (21/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[20]": u1, + /// (22/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[21]": u1, + /// (23/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[22]": u1, + /// (24/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[23]": u1, + /// (25/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[24]": u1, + /// (26/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[25]": u1, + /// (27/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[26]": u1, + /// (28/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[27]": u1, + /// (29/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[28]": u1, + /// (30/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[29]": u1, + /// (31/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[30]": u1, + /// (32/32 of PWP) SRAM2 1Kbyte page 0 write protection + @"PWP[31]": u1, }), /// SKR SKR: mmio.Mmio(packed struct(u32) { @@ -422248,24 +435337,42 @@ pub const types = struct { pub const TAMP = extern struct { /// control register 1 CR1: mmio.Mmio(packed struct(u32) { - /// Tamper detection on IN X enable - TAMPE: u1, - reserved16: u15, - /// Internal tamper X enable - ITAMPE: u1, - padding: u15, + /// (1/2 of TAMPE) Tamper detection on IN X enable + @"TAMPE[0]": u1, + /// (2/2 of TAMPE) Tamper detection on IN X enable + @"TAMPE[1]": u1, + reserved16: u14, + /// (1/6 of ITAMPE) Internal tamper X enable + @"ITAMPE[0]": u1, + /// (2/6 of ITAMPE) Internal tamper X enable + @"ITAMPE[1]": u1, + /// (3/6 of ITAMPE) Internal tamper X enable + @"ITAMPE[2]": u1, + /// (4/6 of ITAMPE) Internal tamper X enable + @"ITAMPE[3]": u1, + /// (5/6 of ITAMPE) Internal tamper X enable + @"ITAMPE[4]": u1, + /// (6/6 of ITAMPE) Internal tamper X enable + @"ITAMPE[5]": u1, + padding: u10, }), /// control register 2 CR2: mmio.Mmio(packed struct(u32) { - /// Tamper X no erase - TAMPNOER: u1, - reserved16: u15, - /// Tamper X mask - TAMPMSK: u1, - reserved24: u7, - /// Active level for tamper X input - TAMPTRG: u1, - padding: u7, + /// (1/2 of TAMPNOER) Tamper X no erase + @"TAMPNOER[0]": u1, + /// (2/2 of TAMPNOER) Tamper X no erase + @"TAMPNOER[1]": u1, + reserved16: u14, + /// (1/2 of TAMPMSK) Tamper X mask + @"TAMPMSK[0]": u1, + /// (2/2 of TAMPMSK) Tamper X mask + @"TAMPMSK[1]": u1, + reserved24: u6, + /// (1/2 of TAMPTRG) Active level for tamper X input + @"TAMPTRG[0]": u1, + /// (2/2 of TAMPTRG) Active level for tamper X input + @"TAMPTRG[1]": u1, + padding: u6, }), reserved12: [4]u8, /// TAMP filter control register @@ -422283,40 +435390,92 @@ pub const types = struct { reserved44: [28]u8, /// TAMP interrupt enable register IER: mmio.Mmio(packed struct(u32) { - /// Tamper X interrupt enable - TAMPIE: u1, - reserved16: u15, - /// Internal tamper X interrupt enable - ITAMPIE: u1, - padding: u15, + /// (1/2 of TAMPIE) Tamper X interrupt enable + @"TAMPIE[0]": u1, + /// (2/2 of TAMPIE) Tamper X interrupt enable + @"TAMPIE[1]": u1, + reserved16: u14, + /// (1/6 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[0]": u1, + /// (2/6 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[1]": u1, + /// (3/6 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[2]": u1, + /// (4/6 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[3]": u1, + /// (5/6 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[4]": u1, + /// (6/6 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[5]": u1, + padding: u10, }), /// TAMP status register SR: mmio.Mmio(packed struct(u32) { - /// Tamper X detection flag - TAMPF: u1, - reserved16: u15, - /// Internal tamper X detection flag - ITAMPF: u1, - padding: u15, + /// (1/2 of TAMPF) Tamper X detection flag + @"TAMPF[0]": u1, + /// (2/2 of TAMPF) Tamper X detection flag + @"TAMPF[1]": u1, + reserved16: u14, + /// (1/7 of ITAMPF) Internal tamper X detection flag + @"ITAMPF[0]": u1, + /// (2/7 of ITAMPF) Internal tamper X detection flag + @"ITAMPF[1]": u1, + /// (3/7 of ITAMPF) Internal tamper X detection flag + @"ITAMPF[2]": u1, + /// (4/7 of ITAMPF) Internal tamper X detection flag + @"ITAMPF[3]": u1, + /// (5/7 of ITAMPF) Internal tamper X detection flag + @"ITAMPF[4]": u1, + /// (6/7 of ITAMPF) Internal tamper X detection flag + @"ITAMPF[5]": u1, + /// (7/7 of ITAMPF) Internal tamper X detection flag + @"ITAMPF[6]": u1, + padding: u9, }), /// TAMP masked interrupt status register MISR: mmio.Mmio(packed struct(u32) { - /// Tamper X interrupt masked flag - TAMPMF: u1, - reserved16: u15, - /// Internal tamper X interrupt masked flag - ITAMPMF: u1, - padding: u15, + /// (1/2 of TAMPMF) Tamper X interrupt masked flag + @"TAMPMF[0]": u1, + /// (2/2 of TAMPMF) Tamper X interrupt masked flag + @"TAMPMF[1]": u1, + reserved16: u14, + /// (1/6 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[0]": u1, + /// (2/6 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[1]": u1, + /// (3/6 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[2]": u1, + /// (4/6 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[3]": u1, + /// (5/6 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[4]": u1, + /// (6/6 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[5]": u1, + padding: u10, }), reserved60: [4]u8, /// TAMP status clear register SCR: mmio.Mmio(packed struct(u32) { - /// Clear tamper X detection flag - CTAMPF: u1, - reserved16: u15, - /// Clear internal tamper X detection flag - CITAMPF: u1, - padding: u15, + /// (1/2 of CTAMPF) Clear tamper X detection flag + @"CTAMPF[0]": u1, + /// (2/2 of CTAMPF) Clear tamper X detection flag + @"CTAMPF[1]": u1, + reserved16: u14, + /// (1/7 of CITAMPF) Clear internal tamper X detection flag + @"CITAMPF[0]": u1, + /// (2/7 of CITAMPF) Clear internal tamper X detection flag + @"CITAMPF[1]": u1, + /// (3/7 of CITAMPF) Clear internal tamper X detection flag + @"CITAMPF[2]": u1, + /// (4/7 of CITAMPF) Clear internal tamper X detection flag + @"CITAMPF[3]": u1, + /// (5/7 of CITAMPF) Clear internal tamper X detection flag + @"CITAMPF[4]": u1, + /// (6/7 of CITAMPF) Clear internal tamper X detection flag + @"CITAMPF[5]": u1, + /// (7/7 of CITAMPF) Clear internal tamper X detection flag + @"CITAMPF[6]": u1, + padding: u9, }), reserved256: [192]u8, /// TAMP backup register @@ -422370,24 +435529,50 @@ pub const types = struct { pub const TAMP = extern struct { /// control register 1 CR1: mmio.Mmio(packed struct(u32) { - /// Tamper detection on IN X enable - TAMPE: u1, - reserved16: u15, - /// Internal tamper X enable - ITAMPE: u1, - padding: u15, + /// (1/3 of TAMPE) Tamper detection on IN X enable + @"TAMPE[0]": u1, + /// (2/3 of TAMPE) Tamper detection on IN X enable + @"TAMPE[1]": u1, + /// (3/3 of TAMPE) Tamper detection on IN X enable + @"TAMPE[2]": u1, + reserved16: u13, + /// (1/6 of ITAMPE) Internal tamper X enable + @"ITAMPE[0]": u1, + /// (2/6 of ITAMPE) Internal tamper X enable + @"ITAMPE[1]": u1, + /// (3/6 of ITAMPE) Internal tamper X enable + @"ITAMPE[2]": u1, + /// (4/6 of ITAMPE) Internal tamper X enable + @"ITAMPE[3]": u1, + /// (5/6 of ITAMPE) Internal tamper X enable + @"ITAMPE[4]": u1, + /// (6/6 of ITAMPE) Internal tamper X enable + @"ITAMPE[5]": u1, + padding: u10, }), /// control register 2 CR2: mmio.Mmio(packed struct(u32) { - /// Tamper X no erase - TAMPNOER: u1, - reserved16: u15, - /// Tamper X mask. - TAMPMSK: u1, - reserved24: u7, - /// Active level for tamper X input. - TAMPTRG: u1, - padding: u7, + /// (1/3 of TAMPNOER) Tamper X no erase + @"TAMPNOER[0]": u1, + /// (2/3 of TAMPNOER) Tamper X no erase + @"TAMPNOER[1]": u1, + /// (3/3 of TAMPNOER) Tamper X no erase + @"TAMPNOER[2]": u1, + reserved16: u13, + /// (1/3 of TAMPMSK) Tamper X mask. + @"TAMPMSK[0]": u1, + /// (2/3 of TAMPMSK) Tamper X mask. + @"TAMPMSK[1]": u1, + /// (3/3 of TAMPMSK) Tamper X mask. + @"TAMPMSK[2]": u1, + reserved24: u5, + /// (1/3 of TAMPTRG) Active level for tamper X input. + @"TAMPTRG[0]": u1, + /// (2/3 of TAMPTRG) Active level for tamper X input. + @"TAMPTRG[1]": u1, + /// (3/3 of TAMPTRG) Active level for tamper X input. + @"TAMPTRG[2]": u1, + padding: u5, }), reserved12: [4]u8, /// TAMP filter control register @@ -422405,40 +435590,96 @@ pub const types = struct { reserved44: [28]u8, /// TAMP interrupt enable register IER: mmio.Mmio(packed struct(u32) { - /// Tamper X interrupt enable - TAMPIE: u1, - reserved16: u15, - /// Internal tamper X interrupt enable - ITAMPIE: u1, - padding: u15, + /// (1/3 of TAMPIE) Tamper X interrupt enable + @"TAMPIE[0]": u1, + /// (2/3 of TAMPIE) Tamper X interrupt enable + @"TAMPIE[1]": u1, + /// (3/3 of TAMPIE) Tamper X interrupt enable + @"TAMPIE[2]": u1, + reserved16: u13, + /// (1/6 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[0]": u1, + /// (2/6 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[1]": u1, + /// (3/6 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[2]": u1, + /// (4/6 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[3]": u1, + /// (5/6 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[4]": u1, + /// (6/6 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[5]": u1, + padding: u10, }), /// TAMP status register SR: mmio.Mmio(packed struct(u32) { - /// Tamper X detection flag - TAMPF: u1, - reserved16: u15, - /// Internal tamper X detection flag - ITAMPF: u1, - padding: u15, + /// (1/3 of TAMPF) Tamper X detection flag + @"TAMPF[0]": u1, + /// (2/3 of TAMPF) Tamper X detection flag + @"TAMPF[1]": u1, + /// (3/3 of TAMPF) Tamper X detection flag + @"TAMPF[2]": u1, + reserved16: u13, + /// (1/6 of ITAMPF) Internal tamper X detection flag + @"ITAMPF[0]": u1, + /// (2/6 of ITAMPF) Internal tamper X detection flag + @"ITAMPF[1]": u1, + /// (3/6 of ITAMPF) Internal tamper X detection flag + @"ITAMPF[2]": u1, + /// (4/6 of ITAMPF) Internal tamper X detection flag + @"ITAMPF[3]": u1, + /// (5/6 of ITAMPF) Internal tamper X detection flag + @"ITAMPF[4]": u1, + /// (6/6 of ITAMPF) Internal tamper X detection flag + @"ITAMPF[5]": u1, + padding: u10, }), /// TAMP masked interrupt status register MISR: mmio.Mmio(packed struct(u32) { - /// Tamper X interrupt masked flag - TAMPMF: u1, - reserved16: u15, - /// Internal tamper X interrupt masked flag - ITAMPMF: u1, - padding: u15, + /// (1/3 of TAMPMF) Tamper X interrupt masked flag + @"TAMPMF[0]": u1, + /// (2/3 of TAMPMF) Tamper X interrupt masked flag + @"TAMPMF[1]": u1, + /// (3/3 of TAMPMF) Tamper X interrupt masked flag + @"TAMPMF[2]": u1, + reserved16: u13, + /// (1/6 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[0]": u1, + /// (2/6 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[1]": u1, + /// (3/6 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[2]": u1, + /// (4/6 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[3]": u1, + /// (5/6 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[4]": u1, + /// (6/6 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[5]": u1, + padding: u10, }), reserved60: [4]u8, /// TAMP status clear register SCR: mmio.Mmio(packed struct(u32) { - /// Clear tamper X detection flag - CTAMPF: u1, - reserved16: u15, - /// Clear internal tamper X detection flag - CITAMPF: u1, - padding: u15, + /// (1/3 of CTAMPF) Clear tamper X detection flag + @"CTAMPF[0]": u1, + /// (2/3 of CTAMPF) Clear tamper X detection flag + @"CTAMPF[1]": u1, + /// (3/3 of CTAMPF) Clear tamper X detection flag + @"CTAMPF[2]": u1, + reserved16: u13, + /// (1/6 of CITAMPF) Clear internal tamper X detection flag + @"CITAMPF[0]": u1, + /// (2/6 of CITAMPF) Clear internal tamper X detection flag + @"CITAMPF[1]": u1, + /// (3/6 of CITAMPF) Clear internal tamper X detection flag + @"CITAMPF[2]": u1, + /// (4/6 of CITAMPF) Clear internal tamper X detection flag + @"CITAMPF[3]": u1, + /// (5/6 of CITAMPF) Clear internal tamper X detection flag + @"CITAMPF[4]": u1, + /// (6/6 of CITAMPF) Clear internal tamper X detection flag + @"CITAMPF[5]": u1, + padding: u10, }), reserved256: [192]u8, /// TAMP backup register @@ -422454,9 +435695,23 @@ pub const types = struct { pub const TAMP = extern struct { /// TAMP control register 1. CR1: mmio.Mmio(packed struct(u32) { - /// Tamper detection on TAMP_INx enable. (x=1-8) - TAMPE: u1, - reserved16: u15, + /// (1/8 of TAMPE) Tamper detection on TAMP_INx enable. (x=1-8) + @"TAMPE[0]": u1, + /// (2/8 of TAMPE) Tamper detection on TAMP_INx enable. (x=1-8) + @"TAMPE[1]": u1, + /// (3/8 of TAMPE) Tamper detection on TAMP_INx enable. (x=1-8) + @"TAMPE[2]": u1, + /// (4/8 of TAMPE) Tamper detection on TAMP_INx enable. (x=1-8) + @"TAMPE[3]": u1, + /// (5/8 of TAMPE) Tamper detection on TAMP_INx enable. (x=1-8) + @"TAMPE[4]": u1, + /// (6/8 of TAMPE) Tamper detection on TAMP_INx enable. (x=1-8) + @"TAMPE[5]": u1, + /// (7/8 of TAMPE) Tamper detection on TAMP_INx enable. (x=1-8) + @"TAMPE[6]": u1, + /// (8/8 of TAMPE) Tamper detection on TAMP_INx enable. (x=1-8) + @"TAMPE[7]": u1, + reserved16: u8, /// Internal tamper 1 enable. ITAMP1E: u1, /// Internal tamper 2 enable. @@ -422489,19 +435744,50 @@ pub const types = struct { }), /// TAMP control register 2. CR2: mmio.Mmio(packed struct(u32) { - /// Tamper x potential mode. (x=1-8) - TAMPPOM: u1, - reserved16: u15, - /// Tamper x mask. The tamper x interrupt must not be enabled when TAMPxMSK is set. (x=1-3) - TAMPMSK: u1, - reserved22: u5, + /// (1/8 of TAMPPOM) Tamper x potential mode. (x=1-8) + @"TAMPPOM[0]": u1, + /// (2/8 of TAMPPOM) Tamper x potential mode. (x=1-8) + @"TAMPPOM[1]": u1, + /// (3/8 of TAMPPOM) Tamper x potential mode. (x=1-8) + @"TAMPPOM[2]": u1, + /// (4/8 of TAMPPOM) Tamper x potential mode. (x=1-8) + @"TAMPPOM[3]": u1, + /// (5/8 of TAMPPOM) Tamper x potential mode. (x=1-8) + @"TAMPPOM[4]": u1, + /// (6/8 of TAMPPOM) Tamper x potential mode. (x=1-8) + @"TAMPPOM[5]": u1, + /// (7/8 of TAMPPOM) Tamper x potential mode. (x=1-8) + @"TAMPPOM[6]": u1, + /// (8/8 of TAMPPOM) Tamper x potential mode. (x=1-8) + @"TAMPPOM[7]": u1, + reserved16: u8, + /// (1/3 of TAMPMSK) Tamper x mask. The tamper x interrupt must not be enabled when TAMPxMSK is set. (x=1-3) + @"TAMPMSK[0]": u1, + /// (2/3 of TAMPMSK) Tamper x mask. The tamper x interrupt must not be enabled when TAMPxMSK is set. (x=1-3) + @"TAMPMSK[1]": u1, + /// (3/3 of TAMPMSK) Tamper x mask. The tamper x interrupt must not be enabled when TAMPxMSK is set. (x=1-3) + @"TAMPMSK[2]": u1, + reserved22: u3, /// Backup registers and device secrets access blocked. BKBLOCK: u1, /// Backup registers and device secrets erase Writing ‘1’ to this bit reset the backup registers and device secrets(1). Writing 0 has no effect. This bit is always read as 0. BKERASE: u1, - /// Active level for tamper x input If TAMPFLT = 00 Tamper x input rising edge triggers a tamper detection event. If TAMPFLT = 00 Tamper x input falling edge triggers a tamper detection event. (x=1-8) - TAMPTRG: u1, - padding: u7, + /// (1/8 of TAMPTRG) Active level for tamper x input If TAMPFLT = 00 Tamper x input rising edge triggers a tamper detection event. If TAMPFLT = 00 Tamper x input falling edge triggers a tamper detection event. (x=1-8) + @"TAMPTRG[0]": u1, + /// (2/8 of TAMPTRG) Active level for tamper x input If TAMPFLT = 00 Tamper x input rising edge triggers a tamper detection event. If TAMPFLT = 00 Tamper x input falling edge triggers a tamper detection event. (x=1-8) + @"TAMPTRG[1]": u1, + /// (3/8 of TAMPTRG) Active level for tamper x input If TAMPFLT = 00 Tamper x input rising edge triggers a tamper detection event. If TAMPFLT = 00 Tamper x input falling edge triggers a tamper detection event. (x=1-8) + @"TAMPTRG[2]": u1, + /// (4/8 of TAMPTRG) Active level for tamper x input If TAMPFLT = 00 Tamper x input rising edge triggers a tamper detection event. If TAMPFLT = 00 Tamper x input falling edge triggers a tamper detection event. (x=1-8) + @"TAMPTRG[3]": u1, + /// (5/8 of TAMPTRG) Active level for tamper x input If TAMPFLT = 00 Tamper x input rising edge triggers a tamper detection event. If TAMPFLT = 00 Tamper x input falling edge triggers a tamper detection event. (x=1-8) + @"TAMPTRG[4]": u1, + /// (6/8 of TAMPTRG) Active level for tamper x input If TAMPFLT = 00 Tamper x input rising edge triggers a tamper detection event. If TAMPFLT = 00 Tamper x input falling edge triggers a tamper detection event. (x=1-8) + @"TAMPTRG[5]": u1, + /// (7/8 of TAMPTRG) Active level for tamper x input If TAMPFLT = 00 Tamper x input rising edge triggers a tamper detection event. If TAMPFLT = 00 Tamper x input falling edge triggers a tamper detection event. (x=1-8) + @"TAMPTRG[6]": u1, + /// (8/8 of TAMPTRG) Active level for tamper x input If TAMPFLT = 00 Tamper x input rising edge triggers a tamper detection event. If TAMPFLT = 00 Tamper x input falling edge triggers a tamper detection event. (x=1-8) + @"TAMPTRG[7]": u1, }), /// TAMP control register 3. CR3: mmio.Mmio(packed struct(u32) { @@ -422549,12 +435835,30 @@ pub const types = struct { }), /// TAMP active tamper control register 1. ATCR1: mmio.Mmio(packed struct(u32) { - /// Tamper x active mode. (x=1-8) - TAMPAM: u1, - reserved8: u7, - /// Active tamper shared output x selection The selected output must be available in the package pinout. (x=1-4) - ATOSEL: u2, - reserved16: u6, + /// (1/8 of TAMPAM) Tamper x active mode. (x=1-8) + @"TAMPAM[0]": u1, + /// (2/8 of TAMPAM) Tamper x active mode. (x=1-8) + @"TAMPAM[1]": u1, + /// (3/8 of TAMPAM) Tamper x active mode. (x=1-8) + @"TAMPAM[2]": u1, + /// (4/8 of TAMPAM) Tamper x active mode. (x=1-8) + @"TAMPAM[3]": u1, + /// (5/8 of TAMPAM) Tamper x active mode. (x=1-8) + @"TAMPAM[4]": u1, + /// (6/8 of TAMPAM) Tamper x active mode. (x=1-8) + @"TAMPAM[5]": u1, + /// (7/8 of TAMPAM) Tamper x active mode. (x=1-8) + @"TAMPAM[6]": u1, + /// (8/8 of TAMPAM) Tamper x active mode. (x=1-8) + @"TAMPAM[7]": u1, + /// (1/4 of ATOSEL) Active tamper shared output x selection The selected output must be available in the package pinout. (x=1-4) + @"ATOSEL[0]": u2, + /// (2/4 of ATOSEL) Active tamper shared output x selection The selected output must be available in the package pinout. (x=1-4) + @"ATOSEL[1]": u2, + /// (3/4 of ATOSEL) Active tamper shared output x selection The selected output must be available in the package pinout. (x=1-4) + @"ATOSEL[2]": u2, + /// (4/4 of ATOSEL) Active tamper shared output x selection The selected output must be available in the package pinout. (x=1-4) + @"ATOSEL[3]": u2, /// Active tamper RTC asynchronous prescaler clock selection These bits selects the RTC asynchronous prescaler stage output.The selected clock is CK_ATPRE. fCK_ATPRE = fRTCCLK / 2ATCKSEL when (PREDIV_A+1) = 128. ... These bits can be written only when all active tampers are disabled. The write protection remains for up to 1.5 ck_atpre cycles after all the active tampers are disable. ATCKSEL: u3, reserved24: u5, @@ -422582,9 +435886,22 @@ pub const types = struct { /// TAMP active tamper control register 2. ATCR2: mmio.Mmio(packed struct(u32) { reserved8: u8, - /// Active tamper shared output x selection The selected output must be available in the package pinout. Bits 9:8 are the mirror of ATOSELx[1:0] in the TAMP_ATCR1, and so can also be read or written through TAMP_ATCR1. (x=1-8) - ATOSEL: u3, - padding: u21, + /// (1/8 of ATOSEL) Active tamper shared output x selection The selected output must be available in the package pinout. Bits 9:8 are the mirror of ATOSELx[1:0] in the TAMP_ATCR1, and so can also be read or written through TAMP_ATCR1. (x=1-8) + @"ATOSEL[0]": u3, + /// (2/8 of ATOSEL) Active tamper shared output x selection The selected output must be available in the package pinout. Bits 9:8 are the mirror of ATOSELx[1:0] in the TAMP_ATCR1, and so can also be read or written through TAMP_ATCR1. (x=1-8) + @"ATOSEL[1]": u3, + /// (3/8 of ATOSEL) Active tamper shared output x selection The selected output must be available in the package pinout. Bits 9:8 are the mirror of ATOSELx[1:0] in the TAMP_ATCR1, and so can also be read or written through TAMP_ATCR1. (x=1-8) + @"ATOSEL[2]": u3, + /// (4/8 of ATOSEL) Active tamper shared output x selection The selected output must be available in the package pinout. Bits 9:8 are the mirror of ATOSELx[1:0] in the TAMP_ATCR1, and so can also be read or written through TAMP_ATCR1. (x=1-8) + @"ATOSEL[3]": u3, + /// (5/8 of ATOSEL) Active tamper shared output x selection The selected output must be available in the package pinout. Bits 9:8 are the mirror of ATOSELx[1:0] in the TAMP_ATCR1, and so can also be read or written through TAMP_ATCR1. (x=1-8) + @"ATOSEL[4]": u3, + /// (6/8 of ATOSEL) Active tamper shared output x selection The selected output must be available in the package pinout. Bits 9:8 are the mirror of ATOSELx[1:0] in the TAMP_ATCR1, and so can also be read or written through TAMP_ATCR1. (x=1-8) + @"ATOSEL[5]": u3, + /// (7/8 of ATOSEL) Active tamper shared output x selection The selected output must be available in the package pinout. Bits 9:8 are the mirror of ATOSELx[1:0] in the TAMP_ATCR1, and so can also be read or written through TAMP_ATCR1. (x=1-8) + @"ATOSEL[6]": u3, + /// (8/8 of ATOSEL) Active tamper shared output x selection The selected output must be available in the package pinout. Bits 9:8 are the mirror of ATOSELx[1:0] in the TAMP_ATCR1, and so can also be read or written through TAMP_ATCR1. (x=1-8) + @"ATOSEL[7]": u3, }), /// TAMP secure mode register. SECCFGR: mmio.Mmio(packed struct(u32) { @@ -422617,9 +435934,23 @@ pub const types = struct { reserved44: [4]u8, /// TAMP interrupt enable register. IER: mmio.Mmio(packed struct(u32) { - /// Tamper x interrupt enable. (x=1-8) - TAMPIE: u1, - reserved16: u15, + /// (1/8 of TAMPIE) Tamper x interrupt enable. (x=1-8) + @"TAMPIE[0]": u1, + /// (2/8 of TAMPIE) Tamper x interrupt enable. (x=1-8) + @"TAMPIE[1]": u1, + /// (3/8 of TAMPIE) Tamper x interrupt enable. (x=1-8) + @"TAMPIE[2]": u1, + /// (4/8 of TAMPIE) Tamper x interrupt enable. (x=1-8) + @"TAMPIE[3]": u1, + /// (5/8 of TAMPIE) Tamper x interrupt enable. (x=1-8) + @"TAMPIE[4]": u1, + /// (6/8 of TAMPIE) Tamper x interrupt enable. (x=1-8) + @"TAMPIE[5]": u1, + /// (7/8 of TAMPIE) Tamper x interrupt enable. (x=1-8) + @"TAMPIE[6]": u1, + /// (8/8 of TAMPIE) Tamper x interrupt enable. (x=1-8) + @"TAMPIE[7]": u1, + reserved16: u8, /// Internal tamper 1 interrupt enable. ITAMP1IE: u1, /// Internal tamper 2 interrupt enable. @@ -422652,9 +435983,23 @@ pub const types = struct { }), /// TAMP status register. SR: mmio.Mmio(packed struct(u32) { - /// TAMPx detection flag. This flag is set by hardware when a tamper detection event is detected on the TAMPx input. (x=1-8) - TAMPF: u1, - reserved16: u15, + /// (1/8 of TAMPF) TAMPx detection flag. This flag is set by hardware when a tamper detection event is detected on the TAMPx input. (x=1-8) + @"TAMPF[0]": u1, + /// (2/8 of TAMPF) TAMPx detection flag. This flag is set by hardware when a tamper detection event is detected on the TAMPx input. (x=1-8) + @"TAMPF[1]": u1, + /// (3/8 of TAMPF) TAMPx detection flag. This flag is set by hardware when a tamper detection event is detected on the TAMPx input. (x=1-8) + @"TAMPF[2]": u1, + /// (4/8 of TAMPF) TAMPx detection flag. This flag is set by hardware when a tamper detection event is detected on the TAMPx input. (x=1-8) + @"TAMPF[3]": u1, + /// (5/8 of TAMPF) TAMPx detection flag. This flag is set by hardware when a tamper detection event is detected on the TAMPx input. (x=1-8) + @"TAMPF[4]": u1, + /// (6/8 of TAMPF) TAMPx detection flag. This flag is set by hardware when a tamper detection event is detected on the TAMPx input. (x=1-8) + @"TAMPF[5]": u1, + /// (7/8 of TAMPF) TAMPx detection flag. This flag is set by hardware when a tamper detection event is detected on the TAMPx input. (x=1-8) + @"TAMPF[6]": u1, + /// (8/8 of TAMPF) TAMPx detection flag. This flag is set by hardware when a tamper detection event is detected on the TAMPx input. (x=1-8) + @"TAMPF[7]": u1, + reserved16: u8, /// Internal tamper 1 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 1. ITAMP1F: u1, /// Internal tamper 2 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 2. @@ -422687,9 +436032,23 @@ pub const types = struct { }), /// TAMP non-secure masked interrupt status register. MISR: mmio.Mmio(packed struct(u32) { - /// TAMP1 non-secure interrupt masked flag This flag is set by hardware when the tamper 1 non-secure interrupt is raised. - TAMPMF: u1, - reserved16: u15, + /// (1/8 of TAMPMF) TAMP1 non-secure interrupt masked flag This flag is set by hardware when the tamper 1 non-secure interrupt is raised. + @"TAMPMF[0]": u1, + /// (2/8 of TAMPMF) TAMP1 non-secure interrupt masked flag This flag is set by hardware when the tamper 1 non-secure interrupt is raised. + @"TAMPMF[1]": u1, + /// (3/8 of TAMPMF) TAMP1 non-secure interrupt masked flag This flag is set by hardware when the tamper 1 non-secure interrupt is raised. + @"TAMPMF[2]": u1, + /// (4/8 of TAMPMF) TAMP1 non-secure interrupt masked flag This flag is set by hardware when the tamper 1 non-secure interrupt is raised. + @"TAMPMF[3]": u1, + /// (5/8 of TAMPMF) TAMP1 non-secure interrupt masked flag This flag is set by hardware when the tamper 1 non-secure interrupt is raised. + @"TAMPMF[4]": u1, + /// (6/8 of TAMPMF) TAMP1 non-secure interrupt masked flag This flag is set by hardware when the tamper 1 non-secure interrupt is raised. + @"TAMPMF[5]": u1, + /// (7/8 of TAMPMF) TAMP1 non-secure interrupt masked flag This flag is set by hardware when the tamper 1 non-secure interrupt is raised. + @"TAMPMF[6]": u1, + /// (8/8 of TAMPMF) TAMP1 non-secure interrupt masked flag This flag is set by hardware when the tamper 1 non-secure interrupt is raised. + @"TAMPMF[7]": u1, + reserved16: u8, /// Internal tamper 1 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 1 non-secure interrupt is raised. ITAMP1MF: u1, /// Internal tamper 2 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 2 non-secure interrupt is raised. @@ -422722,9 +436081,23 @@ pub const types = struct { }), /// TAMP secure masked interrupt status register. SMISR: mmio.Mmio(packed struct(u32) { - /// TAMPx secure interrupt masked flag. This flag is set by hardware when the tamper x secure interrupt is raised. (x=1-8) - TAMPMF: u1, - reserved16: u15, + /// (1/8 of TAMPMF) TAMPx secure interrupt masked flag. This flag is set by hardware when the tamper x secure interrupt is raised. (x=1-8) + @"TAMPMF[0]": u1, + /// (2/8 of TAMPMF) TAMPx secure interrupt masked flag. This flag is set by hardware when the tamper x secure interrupt is raised. (x=1-8) + @"TAMPMF[1]": u1, + /// (3/8 of TAMPMF) TAMPx secure interrupt masked flag. This flag is set by hardware when the tamper x secure interrupt is raised. (x=1-8) + @"TAMPMF[2]": u1, + /// (4/8 of TAMPMF) TAMPx secure interrupt masked flag. This flag is set by hardware when the tamper x secure interrupt is raised. (x=1-8) + @"TAMPMF[3]": u1, + /// (5/8 of TAMPMF) TAMPx secure interrupt masked flag. This flag is set by hardware when the tamper x secure interrupt is raised. (x=1-8) + @"TAMPMF[4]": u1, + /// (6/8 of TAMPMF) TAMPx secure interrupt masked flag. This flag is set by hardware when the tamper x secure interrupt is raised. (x=1-8) + @"TAMPMF[5]": u1, + /// (7/8 of TAMPMF) TAMPx secure interrupt masked flag. This flag is set by hardware when the tamper x secure interrupt is raised. (x=1-8) + @"TAMPMF[6]": u1, + /// (8/8 of TAMPMF) TAMPx secure interrupt masked flag. This flag is set by hardware when the tamper x secure interrupt is raised. (x=1-8) + @"TAMPMF[7]": u1, + reserved16: u8, /// Internal tamper 1 secure interrupt masked flag This flag is set by hardware when the internal tamper 1 secure interrupt is raised. ITAMP1MF: u1, /// Internal tamper 2 secure interrupt masked flag This flag is set by hardware when the internal tamper 2 secure interrupt is raised. @@ -422757,9 +436130,23 @@ pub const types = struct { }), /// TAMP status clear register. SCR: mmio.Mmio(packed struct(u32) { - /// Clear TAMPx detection flag. Writing 1 in this bit clears the TAMPxF bit in the TAMP_SR register. (x=1-8) - CTAMPF: u1, - reserved16: u15, + /// (1/8 of CTAMPF) Clear TAMPx detection flag. Writing 1 in this bit clears the TAMPxF bit in the TAMP_SR register. (x=1-8) + @"CTAMPF[0]": u1, + /// (2/8 of CTAMPF) Clear TAMPx detection flag. Writing 1 in this bit clears the TAMPxF bit in the TAMP_SR register. (x=1-8) + @"CTAMPF[1]": u1, + /// (3/8 of CTAMPF) Clear TAMPx detection flag. Writing 1 in this bit clears the TAMPxF bit in the TAMP_SR register. (x=1-8) + @"CTAMPF[2]": u1, + /// (4/8 of CTAMPF) Clear TAMPx detection flag. Writing 1 in this bit clears the TAMPxF bit in the TAMP_SR register. (x=1-8) + @"CTAMPF[3]": u1, + /// (5/8 of CTAMPF) Clear TAMPx detection flag. Writing 1 in this bit clears the TAMPxF bit in the TAMP_SR register. (x=1-8) + @"CTAMPF[4]": u1, + /// (6/8 of CTAMPF) Clear TAMPx detection flag. Writing 1 in this bit clears the TAMPxF bit in the TAMP_SR register. (x=1-8) + @"CTAMPF[5]": u1, + /// (7/8 of CTAMPF) Clear TAMPx detection flag. Writing 1 in this bit clears the TAMPxF bit in the TAMP_SR register. (x=1-8) + @"CTAMPF[6]": u1, + /// (8/8 of CTAMPF) Clear TAMPx detection flag. Writing 1 in this bit clears the TAMPxF bit in the TAMP_SR register. (x=1-8) + @"CTAMPF[7]": u1, + reserved16: u8, /// Clear ITAMP1 detection flag Writing 1 in this bit clears the ITAMP1F bit in the TAMP_SR register. CITAMP1F: u1, /// Clear ITAMP2 detection flag Writing 1 in this bit clears the ITAMP2F bit in the TAMP_SR register. @@ -422826,32 +436213,105 @@ pub const types = struct { pub const TAMP = extern struct { /// control register 1 CR1: mmio.Mmio(packed struct(u32) { - /// TAMPE - TAMPE: u1, - reserved16: u15, - /// ITAMPE - ITAMPE: u1, - padding: u15, + /// (1/8 of TAMPE) TAMPE + @"TAMPE[0]": u1, + /// (2/8 of TAMPE) TAMPE + @"TAMPE[1]": u1, + /// (3/8 of TAMPE) TAMPE + @"TAMPE[2]": u1, + /// (4/8 of TAMPE) TAMPE + @"TAMPE[3]": u1, + /// (5/8 of TAMPE) TAMPE + @"TAMPE[4]": u1, + /// (6/8 of TAMPE) TAMPE + @"TAMPE[5]": u1, + /// (7/8 of TAMPE) TAMPE + @"TAMPE[6]": u1, + /// (8/8 of TAMPE) TAMPE + @"TAMPE[7]": u1, + reserved16: u8, + /// (1/8 of ITAMPE) ITAMPE + @"ITAMPE[0]": u1, + /// (2/8 of ITAMPE) ITAMPE + @"ITAMPE[1]": u1, + /// (3/8 of ITAMPE) ITAMPE + @"ITAMPE[2]": u1, + /// (4/8 of ITAMPE) ITAMPE + @"ITAMPE[3]": u1, + /// (5/8 of ITAMPE) ITAMPE + @"ITAMPE[4]": u1, + /// (6/8 of ITAMPE) ITAMPE + @"ITAMPE[5]": u1, + /// (7/8 of ITAMPE) ITAMPE + @"ITAMPE[6]": u1, + /// (8/8 of ITAMPE) ITAMPE + @"ITAMPE[7]": u1, + padding: u8, }), /// control register 2 CR2: mmio.Mmio(packed struct(u32) { - /// Tamper X no erase - TAMPNOER: u1, - reserved16: u15, - /// Tamper X mask - TAMPMSK: u1, - reserved23: u6, + /// (1/8 of TAMPNOER) Tamper X no erase + @"TAMPNOER[0]": u1, + /// (2/8 of TAMPNOER) Tamper X no erase + @"TAMPNOER[1]": u1, + /// (3/8 of TAMPNOER) Tamper X no erase + @"TAMPNOER[2]": u1, + /// (4/8 of TAMPNOER) Tamper X no erase + @"TAMPNOER[3]": u1, + /// (5/8 of TAMPNOER) Tamper X no erase + @"TAMPNOER[4]": u1, + /// (6/8 of TAMPNOER) Tamper X no erase + @"TAMPNOER[5]": u1, + /// (7/8 of TAMPNOER) Tamper X no erase + @"TAMPNOER[6]": u1, + /// (8/8 of TAMPNOER) Tamper X no erase + @"TAMPNOER[7]": u1, + reserved16: u8, + /// (1/3 of TAMPMSK) Tamper X mask + @"TAMPMSK[0]": u1, + /// (2/3 of TAMPMSK) Tamper X mask + @"TAMPMSK[1]": u1, + /// (3/3 of TAMPMSK) Tamper X mask + @"TAMPMSK[2]": u1, + reserved23: u4, /// BKERASE BKERASE: u1, - /// Active level for tamper X input - TAMPTRG: u1, - padding: u7, + /// (1/8 of TAMPTRG) Active level for tamper X input + @"TAMPTRG[0]": u1, + /// (2/8 of TAMPTRG) Active level for tamper X input + @"TAMPTRG[1]": u1, + /// (3/8 of TAMPTRG) Active level for tamper X input + @"TAMPTRG[2]": u1, + /// (4/8 of TAMPTRG) Active level for tamper X input + @"TAMPTRG[3]": u1, + /// (5/8 of TAMPTRG) Active level for tamper X input + @"TAMPTRG[4]": u1, + /// (6/8 of TAMPTRG) Active level for tamper X input + @"TAMPTRG[5]": u1, + /// (7/8 of TAMPTRG) Active level for tamper X input + @"TAMPTRG[6]": u1, + /// (8/8 of TAMPTRG) Active level for tamper X input + @"TAMPTRG[7]": u1, }), /// control register 3 CR3: mmio.Mmio(packed struct(u32) { - /// Internal Tamper X no erase - ITAMPNOER: u1, - padding: u31, + /// (1/8 of ITAMPNOER) Internal Tamper X no erase + @"ITAMPNOER[0]": u1, + /// (2/8 of ITAMPNOER) Internal Tamper X no erase + @"ITAMPNOER[1]": u1, + /// (3/8 of ITAMPNOER) Internal Tamper X no erase + @"ITAMPNOER[2]": u1, + /// (4/8 of ITAMPNOER) Internal Tamper X no erase + @"ITAMPNOER[3]": u1, + /// (5/8 of ITAMPNOER) Internal Tamper X no erase + @"ITAMPNOER[4]": u1, + /// (6/8 of ITAMPNOER) Internal Tamper X no erase + @"ITAMPNOER[5]": u1, + /// (7/8 of ITAMPNOER) Internal Tamper X no erase + @"ITAMPNOER[6]": u1, + /// (8/8 of ITAMPNOER) Internal Tamper X no erase + @"ITAMPNOER[7]": u1, + padding: u24, }), /// TAMP filter control register FLTCR: mmio.Mmio(packed struct(u32) { @@ -422867,12 +436327,30 @@ pub const types = struct { }), /// TAMP active tamper control register 1 ATCR1: mmio.Mmio(packed struct(u32) { - /// TAMPAM - TAMPAM: u1, - reserved8: u7, - /// ATOSEL - ATOSEL: u2, - reserved16: u6, + /// (1/8 of TAMPAM) TAMPAM + @"TAMPAM[0]": u1, + /// (2/8 of TAMPAM) TAMPAM + @"TAMPAM[1]": u1, + /// (3/8 of TAMPAM) TAMPAM + @"TAMPAM[2]": u1, + /// (4/8 of TAMPAM) TAMPAM + @"TAMPAM[3]": u1, + /// (5/8 of TAMPAM) TAMPAM + @"TAMPAM[4]": u1, + /// (6/8 of TAMPAM) TAMPAM + @"TAMPAM[5]": u1, + /// (7/8 of TAMPAM) TAMPAM + @"TAMPAM[6]": u1, + /// (8/8 of TAMPAM) TAMPAM + @"TAMPAM[7]": u1, + /// (1/4 of ATOSEL) ATOSEL + @"ATOSEL[0]": u2, + /// (2/4 of ATOSEL) ATOSEL + @"ATOSEL[1]": u2, + /// (3/4 of ATOSEL) ATOSEL + @"ATOSEL[2]": u2, + /// (4/4 of ATOSEL) ATOSEL + @"ATOSEL[3]": u2, /// ATCKSEL ATCKSEL: u2, reserved24: u6, @@ -422903,9 +436381,22 @@ pub const types = struct { /// TAMP active tamper control register 2 ATCR2: mmio.Mmio(packed struct(u32) { reserved8: u8, - /// ATOSEL - ATOSEL: u3, - padding: u21, + /// (1/8 of ATOSEL) ATOSEL + @"ATOSEL[0]": u3, + /// (2/8 of ATOSEL) ATOSEL + @"ATOSEL[1]": u3, + /// (3/8 of ATOSEL) ATOSEL + @"ATOSEL[2]": u3, + /// (4/8 of ATOSEL) ATOSEL + @"ATOSEL[3]": u3, + /// (5/8 of ATOSEL) ATOSEL + @"ATOSEL[4]": u3, + /// (6/8 of ATOSEL) ATOSEL + @"ATOSEL[5]": u3, + /// (7/8 of ATOSEL) ATOSEL + @"ATOSEL[6]": u3, + /// (8/8 of ATOSEL) ATOSEL + @"ATOSEL[7]": u3, }), /// TAMP secure mode register SMCR: mmio.Mmio(packed struct(u32) { @@ -422931,48 +436422,188 @@ pub const types = struct { reserved44: [4]u8, /// TAMP interrupt enable register IER: mmio.Mmio(packed struct(u32) { - /// Tamper X interrupt enable - TAMPIE: u1, - reserved16: u15, - /// Internal tamper X interrupt enable - ITAMPIE: u1, - padding: u15, + /// (1/8 of TAMPIE) Tamper X interrupt enable + @"TAMPIE[0]": u1, + /// (2/8 of TAMPIE) Tamper X interrupt enable + @"TAMPIE[1]": u1, + /// (3/8 of TAMPIE) Tamper X interrupt enable + @"TAMPIE[2]": u1, + /// (4/8 of TAMPIE) Tamper X interrupt enable + @"TAMPIE[3]": u1, + /// (5/8 of TAMPIE) Tamper X interrupt enable + @"TAMPIE[4]": u1, + /// (6/8 of TAMPIE) Tamper X interrupt enable + @"TAMPIE[5]": u1, + /// (7/8 of TAMPIE) Tamper X interrupt enable + @"TAMPIE[6]": u1, + /// (8/8 of TAMPIE) Tamper X interrupt enable + @"TAMPIE[7]": u1, + reserved16: u8, + /// (1/8 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[0]": u1, + /// (2/8 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[1]": u1, + /// (3/8 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[2]": u1, + /// (4/8 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[3]": u1, + /// (5/8 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[4]": u1, + /// (6/8 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[5]": u1, + /// (7/8 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[6]": u1, + /// (8/8 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[7]": u1, + padding: u8, }), /// TAMP status register SR: mmio.Mmio(packed struct(u32) { - /// Tamper X detection flag - TAMPF: u1, - reserved16: u15, - /// Internal tamper X detection flag - ITAMPF: u1, - padding: u15, + /// (1/8 of TAMPF) Tamper X detection flag + @"TAMPF[0]": u1, + /// (2/8 of TAMPF) Tamper X detection flag + @"TAMPF[1]": u1, + /// (3/8 of TAMPF) Tamper X detection flag + @"TAMPF[2]": u1, + /// (4/8 of TAMPF) Tamper X detection flag + @"TAMPF[3]": u1, + /// (5/8 of TAMPF) Tamper X detection flag + @"TAMPF[4]": u1, + /// (6/8 of TAMPF) Tamper X detection flag + @"TAMPF[5]": u1, + /// (7/8 of TAMPF) Tamper X detection flag + @"TAMPF[6]": u1, + /// (8/8 of TAMPF) Tamper X detection flag + @"TAMPF[7]": u1, + reserved16: u8, + /// (1/8 of ITAMPF) Internal tamper X detection flag + @"ITAMPF[0]": u1, + /// (2/8 of ITAMPF) Internal tamper X detection flag + @"ITAMPF[1]": u1, + /// (3/8 of ITAMPF) Internal tamper X detection flag + @"ITAMPF[2]": u1, + /// (4/8 of ITAMPF) Internal tamper X detection flag + @"ITAMPF[3]": u1, + /// (5/8 of ITAMPF) Internal tamper X detection flag + @"ITAMPF[4]": u1, + /// (6/8 of ITAMPF) Internal tamper X detection flag + @"ITAMPF[5]": u1, + /// (7/8 of ITAMPF) Internal tamper X detection flag + @"ITAMPF[6]": u1, + /// (8/8 of ITAMPF) Internal tamper X detection flag + @"ITAMPF[7]": u1, + padding: u8, }), /// TAMP masked interrupt status register MISR: mmio.Mmio(packed struct(u32) { - /// Tamper X interrupt masked flag - TAMPMF: u1, - reserved16: u15, - /// Internal tamper X interrupt masked flag - ITAMPMF: u1, - padding: u15, + /// (1/8 of TAMPMF) Tamper X interrupt masked flag + @"TAMPMF[0]": u1, + /// (2/8 of TAMPMF) Tamper X interrupt masked flag + @"TAMPMF[1]": u1, + /// (3/8 of TAMPMF) Tamper X interrupt masked flag + @"TAMPMF[2]": u1, + /// (4/8 of TAMPMF) Tamper X interrupt masked flag + @"TAMPMF[3]": u1, + /// (5/8 of TAMPMF) Tamper X interrupt masked flag + @"TAMPMF[4]": u1, + /// (6/8 of TAMPMF) Tamper X interrupt masked flag + @"TAMPMF[5]": u1, + /// (7/8 of TAMPMF) Tamper X interrupt masked flag + @"TAMPMF[6]": u1, + /// (8/8 of TAMPMF) Tamper X interrupt masked flag + @"TAMPMF[7]": u1, + reserved16: u8, + /// (1/8 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[0]": u1, + /// (2/8 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[1]": u1, + /// (3/8 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[2]": u1, + /// (4/8 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[3]": u1, + /// (5/8 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[4]": u1, + /// (6/8 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[5]": u1, + /// (7/8 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[6]": u1, + /// (8/8 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[7]": u1, + padding: u8, }), /// TAMP secure masked interrupt status register SMISR: mmio.Mmio(packed struct(u32) { - /// Tamper X interrupt masked flag - TAMPMF: u1, - reserved16: u15, - /// Internal tamper X interrupt masked flag - ITAMPMF: u1, - padding: u15, + /// (1/8 of TAMPMF) Tamper X interrupt masked flag + @"TAMPMF[0]": u1, + /// (2/8 of TAMPMF) Tamper X interrupt masked flag + @"TAMPMF[1]": u1, + /// (3/8 of TAMPMF) Tamper X interrupt masked flag + @"TAMPMF[2]": u1, + /// (4/8 of TAMPMF) Tamper X interrupt masked flag + @"TAMPMF[3]": u1, + /// (5/8 of TAMPMF) Tamper X interrupt masked flag + @"TAMPMF[4]": u1, + /// (6/8 of TAMPMF) Tamper X interrupt masked flag + @"TAMPMF[5]": u1, + /// (7/8 of TAMPMF) Tamper X interrupt masked flag + @"TAMPMF[6]": u1, + /// (8/8 of TAMPMF) Tamper X interrupt masked flag + @"TAMPMF[7]": u1, + reserved16: u8, + /// (1/8 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[0]": u1, + /// (2/8 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[1]": u1, + /// (3/8 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[2]": u1, + /// (4/8 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[3]": u1, + /// (5/8 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[4]": u1, + /// (6/8 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[5]": u1, + /// (7/8 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[6]": u1, + /// (8/8 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[7]": u1, + padding: u8, }), /// TAMP status clear register SCR: mmio.Mmio(packed struct(u32) { - /// Clear tamper X detection flag - CTAMPF: u1, - reserved16: u15, - /// Clear internal tamper X detection flag - CITAMPF: u1, - padding: u15, + /// (1/8 of CTAMPF) Clear tamper X detection flag + @"CTAMPF[0]": u1, + /// (2/8 of CTAMPF) Clear tamper X detection flag + @"CTAMPF[1]": u1, + /// (3/8 of CTAMPF) Clear tamper X detection flag + @"CTAMPF[2]": u1, + /// (4/8 of CTAMPF) Clear tamper X detection flag + @"CTAMPF[3]": u1, + /// (5/8 of CTAMPF) Clear tamper X detection flag + @"CTAMPF[4]": u1, + /// (6/8 of CTAMPF) Clear tamper X detection flag + @"CTAMPF[5]": u1, + /// (7/8 of CTAMPF) Clear tamper X detection flag + @"CTAMPF[6]": u1, + /// (8/8 of CTAMPF) Clear tamper X detection flag + @"CTAMPF[7]": u1, + reserved16: u8, + /// (1/8 of CITAMPF) Clear internal tamper X detection flag + @"CITAMPF[0]": u1, + /// (2/8 of CITAMPF) Clear internal tamper X detection flag + @"CITAMPF[1]": u1, + /// (3/8 of CITAMPF) Clear internal tamper X detection flag + @"CITAMPF[2]": u1, + /// (4/8 of CITAMPF) Clear internal tamper X detection flag + @"CITAMPF[3]": u1, + /// (5/8 of CITAMPF) Clear internal tamper X detection flag + @"CITAMPF[4]": u1, + /// (6/8 of CITAMPF) Clear internal tamper X detection flag + @"CITAMPF[5]": u1, + /// (7/8 of CITAMPF) Clear internal tamper X detection flag + @"CITAMPF[6]": u1, + /// (8/8 of CITAMPF) Clear internal tamper X detection flag + @"CITAMPF[7]": u1, + padding: u8, }), /// TAMP monotonic counter register COUNTR: mmio.Mmio(packed struct(u32) { @@ -423065,34 +436696,127 @@ pub const types = struct { pub const TAMP = extern struct { /// TAMP control register 1 CR1: mmio.Mmio(packed struct(u32) { - /// Tamper detection on INx enable - TAMPE: u1, - reserved16: u15, - /// Internal tamper X enable - ITAMPE: u1, - padding: u15, + /// (1/8 of TAMPE) Tamper detection on INx enable + @"TAMPE[0]": u1, + /// (2/8 of TAMPE) Tamper detection on INx enable + @"TAMPE[1]": u1, + /// (3/8 of TAMPE) Tamper detection on INx enable + @"TAMPE[2]": u1, + /// (4/8 of TAMPE) Tamper detection on INx enable + @"TAMPE[3]": u1, + /// (5/8 of TAMPE) Tamper detection on INx enable + @"TAMPE[4]": u1, + /// (6/8 of TAMPE) Tamper detection on INx enable + @"TAMPE[5]": u1, + /// (7/8 of TAMPE) Tamper detection on INx enable + @"TAMPE[6]": u1, + /// (8/8 of TAMPE) Tamper detection on INx enable + @"TAMPE[7]": u1, + reserved16: u8, + /// (1/13 of ITAMPE) Internal tamper X enable + @"ITAMPE[0]": u1, + /// (2/13 of ITAMPE) Internal tamper X enable + @"ITAMPE[1]": u1, + /// (3/13 of ITAMPE) Internal tamper X enable + @"ITAMPE[2]": u1, + /// (4/13 of ITAMPE) Internal tamper X enable + @"ITAMPE[3]": u1, + /// (5/13 of ITAMPE) Internal tamper X enable + @"ITAMPE[4]": u1, + /// (6/13 of ITAMPE) Internal tamper X enable + @"ITAMPE[5]": u1, + /// (7/13 of ITAMPE) Internal tamper X enable + @"ITAMPE[6]": u1, + /// (8/13 of ITAMPE) Internal tamper X enable + @"ITAMPE[7]": u1, + /// (9/13 of ITAMPE) Internal tamper X enable + @"ITAMPE[8]": u1, + /// (10/13 of ITAMPE) Internal tamper X enable + @"ITAMPE[9]": u1, + /// (11/13 of ITAMPE) Internal tamper X enable + @"ITAMPE[10]": u1, + /// (12/13 of ITAMPE) Internal tamper X enable + @"ITAMPE[11]": u1, + /// (13/13 of ITAMPE) Internal tamper X enable + @"ITAMPE[12]": u1, + padding: u3, }), /// TAMP control register 2 CR2: mmio.Mmio(packed struct(u32) { - /// Tamper X no erase - TAMPNOER: u1, - reserved16: u15, - /// Tamper X mask. The tamper 1 interrupt must not be enabled when TAMP1MSK is set. - TAMPMSK: u1, - reserved22: u5, + /// (1/8 of TAMPNOER) Tamper X no erase + @"TAMPNOER[0]": u1, + /// (2/8 of TAMPNOER) Tamper X no erase + @"TAMPNOER[1]": u1, + /// (3/8 of TAMPNOER) Tamper X no erase + @"TAMPNOER[2]": u1, + /// (4/8 of TAMPNOER) Tamper X no erase + @"TAMPNOER[3]": u1, + /// (5/8 of TAMPNOER) Tamper X no erase + @"TAMPNOER[4]": u1, + /// (6/8 of TAMPNOER) Tamper X no erase + @"TAMPNOER[5]": u1, + /// (7/8 of TAMPNOER) Tamper X no erase + @"TAMPNOER[6]": u1, + /// (8/8 of TAMPNOER) Tamper X no erase + @"TAMPNOER[7]": u1, + reserved16: u8, + /// (1/3 of TAMPMSK) Tamper X mask. The tamper 1 interrupt must not be enabled when TAMP1MSK is set. + @"TAMPMSK[0]": u1, + /// (2/3 of TAMPMSK) Tamper X mask. The tamper 1 interrupt must not be enabled when TAMP1MSK is set. + @"TAMPMSK[1]": u1, + /// (3/3 of TAMPMSK) Tamper X mask. The tamper 1 interrupt must not be enabled when TAMP1MSK is set. + @"TAMPMSK[2]": u1, + reserved22: u3, /// Backup registers and device secrets access blocked BKBLOCK: u1, /// Backup registers and device secrets erase. Writing '1 to this bit reset the backup registers and device secrets(1). Writing 0 has no effect. This bit is always read as 0. BKERASE: u1, - /// Active level for tamper 1 input. - TAMPTRG: TAMPTRG, - padding: u7, + /// (1/8 of TAMPTRG) Active level for tamper 1 input. + @"TAMPTRG[0]": TAMPTRG, + /// (2/8 of TAMPTRG) Active level for tamper 1 input. + @"TAMPTRG[1]": TAMPTRG, + /// (3/8 of TAMPTRG) Active level for tamper 1 input. + @"TAMPTRG[2]": TAMPTRG, + /// (4/8 of TAMPTRG) Active level for tamper 1 input. + @"TAMPTRG[3]": TAMPTRG, + /// (5/8 of TAMPTRG) Active level for tamper 1 input. + @"TAMPTRG[4]": TAMPTRG, + /// (6/8 of TAMPTRG) Active level for tamper 1 input. + @"TAMPTRG[5]": TAMPTRG, + /// (7/8 of TAMPTRG) Active level for tamper 1 input. + @"TAMPTRG[6]": TAMPTRG, + /// (8/8 of TAMPTRG) Active level for tamper 1 input. + @"TAMPTRG[7]": TAMPTRG, }), /// TAMP control register 3 CR3: mmio.Mmio(packed struct(u32) { - /// Internal Tamper X no erase - ITAMPNOER: u1, - padding: u31, + /// (1/13 of ITAMPNOER) Internal Tamper X no erase + @"ITAMPNOER[0]": u1, + /// (2/13 of ITAMPNOER) Internal Tamper X no erase + @"ITAMPNOER[1]": u1, + /// (3/13 of ITAMPNOER) Internal Tamper X no erase + @"ITAMPNOER[2]": u1, + /// (4/13 of ITAMPNOER) Internal Tamper X no erase + @"ITAMPNOER[3]": u1, + /// (5/13 of ITAMPNOER) Internal Tamper X no erase + @"ITAMPNOER[4]": u1, + /// (6/13 of ITAMPNOER) Internal Tamper X no erase + @"ITAMPNOER[5]": u1, + /// (7/13 of ITAMPNOER) Internal Tamper X no erase + @"ITAMPNOER[6]": u1, + /// (8/13 of ITAMPNOER) Internal Tamper X no erase + @"ITAMPNOER[7]": u1, + /// (9/13 of ITAMPNOER) Internal Tamper X no erase + @"ITAMPNOER[8]": u1, + /// (10/13 of ITAMPNOER) Internal Tamper X no erase + @"ITAMPNOER[9]": u1, + /// (11/13 of ITAMPNOER) Internal Tamper X no erase + @"ITAMPNOER[10]": u1, + /// (12/13 of ITAMPNOER) Internal Tamper X no erase + @"ITAMPNOER[11]": u1, + /// (13/13 of ITAMPNOER) Internal Tamper X no erase + @"ITAMPNOER[12]": u1, + padding: u19, }), /// TAMP filter control register FLTCR: mmio.Mmio(packed struct(u32) { @@ -423108,12 +436832,30 @@ pub const types = struct { }), /// TAMP active tamper control register 1 ATCR1: mmio.Mmio(packed struct(u32) { - /// Tamper X active mode - TAMPAM: u1, - reserved8: u7, - /// Active tamper shared output X selection. The selected output must be available in the package pinout - ATOSEL: u2, - reserved16: u6, + /// (1/8 of TAMPAM) Tamper X active mode + @"TAMPAM[0]": u1, + /// (2/8 of TAMPAM) Tamper X active mode + @"TAMPAM[1]": u1, + /// (3/8 of TAMPAM) Tamper X active mode + @"TAMPAM[2]": u1, + /// (4/8 of TAMPAM) Tamper X active mode + @"TAMPAM[3]": u1, + /// (5/8 of TAMPAM) Tamper X active mode + @"TAMPAM[4]": u1, + /// (6/8 of TAMPAM) Tamper X active mode + @"TAMPAM[5]": u1, + /// (7/8 of TAMPAM) Tamper X active mode + @"TAMPAM[6]": u1, + /// (8/8 of TAMPAM) Tamper X active mode + @"TAMPAM[7]": u1, + /// (1/4 of ATOSEL) Active tamper shared output X selection. The selected output must be available in the package pinout + @"ATOSEL[0]": u2, + /// (2/4 of ATOSEL) Active tamper shared output X selection. The selected output must be available in the package pinout + @"ATOSEL[1]": u2, + /// (3/4 of ATOSEL) Active tamper shared output X selection. The selected output must be available in the package pinout + @"ATOSEL[2]": u2, + /// (4/4 of ATOSEL) Active tamper shared output X selection. The selected output must be available in the package pinout + @"ATOSEL[3]": u2, /// Active tamper RTC asynchronous prescaler clock selection. These bits selects the RTC asynchronous prescaler stage output.The selected clock is CK_ATPRE.. fCK_ATPRE = fRTCCLK / 2ATCKSEL when (PREDIV_A+1) = 128.. .... These bits can be written only when all active tampers are disabled. The write protection remains for up to 1.5 ck_atpre cycles after all the active tampers are disable. ATCKSEL: ATCKSEL, reserved24: u5, @@ -423144,9 +436886,22 @@ pub const types = struct { /// TAMP active tamper control register 2 ATCR2: mmio.Mmio(packed struct(u32) { reserved8: u8, - /// Active tamper shared output X selection. The selected output must be available in the package pinout. Bits 9:8 are the mirror of ATOSEL1[1:0] in the ATCR1, and so can also be read or. written through ATCR1. - ATOSEL: u3, - padding: u21, + /// (1/8 of ATOSEL) Active tamper shared output X selection. The selected output must be available in the package pinout. Bits 9:8 are the mirror of ATOSEL1[1:0] in the ATCR1, and so can also be read or. written through ATCR1. + @"ATOSEL[0]": u3, + /// (2/8 of ATOSEL) Active tamper shared output X selection. The selected output must be available in the package pinout. Bits 9:8 are the mirror of ATOSEL1[1:0] in the ATCR1, and so can also be read or. written through ATCR1. + @"ATOSEL[1]": u3, + /// (3/8 of ATOSEL) Active tamper shared output X selection. The selected output must be available in the package pinout. Bits 9:8 are the mirror of ATOSEL1[1:0] in the ATCR1, and so can also be read or. written through ATCR1. + @"ATOSEL[2]": u3, + /// (4/8 of ATOSEL) Active tamper shared output X selection. The selected output must be available in the package pinout. Bits 9:8 are the mirror of ATOSEL1[1:0] in the ATCR1, and so can also be read or. written through ATCR1. + @"ATOSEL[3]": u3, + /// (5/8 of ATOSEL) Active tamper shared output X selection. The selected output must be available in the package pinout. Bits 9:8 are the mirror of ATOSEL1[1:0] in the ATCR1, and so can also be read or. written through ATCR1. + @"ATOSEL[4]": u3, + /// (6/8 of ATOSEL) Active tamper shared output X selection. The selected output must be available in the package pinout. Bits 9:8 are the mirror of ATOSEL1[1:0] in the ATCR1, and so can also be read or. written through ATCR1. + @"ATOSEL[5]": u3, + /// (7/8 of ATOSEL) Active tamper shared output X selection. The selected output must be available in the package pinout. Bits 9:8 are the mirror of ATOSEL1[1:0] in the ATCR1, and so can also be read or. written through ATCR1. + @"ATOSEL[6]": u3, + /// (8/8 of ATOSEL) Active tamper shared output X selection. The selected output must be available in the package pinout. Bits 9:8 are the mirror of ATOSEL1[1:0] in the ATCR1, and so can also be read or. written through ATCR1. + @"ATOSEL[7]": u3, }), /// TAMP secure mode register SECCFGR: mmio.Mmio(packed struct(u32) { @@ -423179,48 +436934,238 @@ pub const types = struct { reserved44: [4]u8, /// TAMP interrupt enable register IER: mmio.Mmio(packed struct(u32) { - /// Tamper X interrupt enable - TAMPIE: u1, - reserved16: u15, - /// Internal tamper X interrupt enable - ITAMPIE: u1, - padding: u15, + /// (1/8 of TAMPIE) Tamper X interrupt enable + @"TAMPIE[0]": u1, + /// (2/8 of TAMPIE) Tamper X interrupt enable + @"TAMPIE[1]": u1, + /// (3/8 of TAMPIE) Tamper X interrupt enable + @"TAMPIE[2]": u1, + /// (4/8 of TAMPIE) Tamper X interrupt enable + @"TAMPIE[3]": u1, + /// (5/8 of TAMPIE) Tamper X interrupt enable + @"TAMPIE[4]": u1, + /// (6/8 of TAMPIE) Tamper X interrupt enable + @"TAMPIE[5]": u1, + /// (7/8 of TAMPIE) Tamper X interrupt enable + @"TAMPIE[6]": u1, + /// (8/8 of TAMPIE) Tamper X interrupt enable + @"TAMPIE[7]": u1, + reserved16: u8, + /// (1/13 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[0]": u1, + /// (2/13 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[1]": u1, + /// (3/13 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[2]": u1, + /// (4/13 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[3]": u1, + /// (5/13 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[4]": u1, + /// (6/13 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[5]": u1, + /// (7/13 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[6]": u1, + /// (8/13 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[7]": u1, + /// (9/13 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[8]": u1, + /// (10/13 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[9]": u1, + /// (11/13 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[10]": u1, + /// (12/13 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[11]": u1, + /// (13/13 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[12]": u1, + padding: u3, }), /// TAMP status register SR: mmio.Mmio(packed struct(u32) { - /// TAMPx detection flag. This flag is set by hardware when a tamper detection event is detected on the TAMPx input. - TAMPF: u1, - reserved16: u15, - /// Internal tamper X flag. This flag is set by hardware when a tamper detection event is detected on the internal tamper X. - ITAMPF: u1, - padding: u15, + /// (1/8 of TAMPF) TAMPx detection flag. This flag is set by hardware when a tamper detection event is detected on the TAMPx input. + @"TAMPF[0]": u1, + /// (2/8 of TAMPF) TAMPx detection flag. This flag is set by hardware when a tamper detection event is detected on the TAMPx input. + @"TAMPF[1]": u1, + /// (3/8 of TAMPF) TAMPx detection flag. This flag is set by hardware when a tamper detection event is detected on the TAMPx input. + @"TAMPF[2]": u1, + /// (4/8 of TAMPF) TAMPx detection flag. This flag is set by hardware when a tamper detection event is detected on the TAMPx input. + @"TAMPF[3]": u1, + /// (5/8 of TAMPF) TAMPx detection flag. This flag is set by hardware when a tamper detection event is detected on the TAMPx input. + @"TAMPF[4]": u1, + /// (6/8 of TAMPF) TAMPx detection flag. This flag is set by hardware when a tamper detection event is detected on the TAMPx input. + @"TAMPF[5]": u1, + /// (7/8 of TAMPF) TAMPx detection flag. This flag is set by hardware when a tamper detection event is detected on the TAMPx input. + @"TAMPF[6]": u1, + /// (8/8 of TAMPF) TAMPx detection flag. This flag is set by hardware when a tamper detection event is detected on the TAMPx input. + @"TAMPF[7]": u1, + reserved16: u8, + /// (1/13 of ITAMPF) Internal tamper X flag. This flag is set by hardware when a tamper detection event is detected on the internal tamper X. + @"ITAMPF[0]": u1, + /// (2/13 of ITAMPF) Internal tamper X flag. This flag is set by hardware when a tamper detection event is detected on the internal tamper X. + @"ITAMPF[1]": u1, + /// (3/13 of ITAMPF) Internal tamper X flag. This flag is set by hardware when a tamper detection event is detected on the internal tamper X. + @"ITAMPF[2]": u1, + /// (4/13 of ITAMPF) Internal tamper X flag. This flag is set by hardware when a tamper detection event is detected on the internal tamper X. + @"ITAMPF[3]": u1, + /// (5/13 of ITAMPF) Internal tamper X flag. This flag is set by hardware when a tamper detection event is detected on the internal tamper X. + @"ITAMPF[4]": u1, + /// (6/13 of ITAMPF) Internal tamper X flag. This flag is set by hardware when a tamper detection event is detected on the internal tamper X. + @"ITAMPF[5]": u1, + /// (7/13 of ITAMPF) Internal tamper X flag. This flag is set by hardware when a tamper detection event is detected on the internal tamper X. + @"ITAMPF[6]": u1, + /// (8/13 of ITAMPF) Internal tamper X flag. This flag is set by hardware when a tamper detection event is detected on the internal tamper X. + @"ITAMPF[7]": u1, + /// (9/13 of ITAMPF) Internal tamper X flag. This flag is set by hardware when a tamper detection event is detected on the internal tamper X. + @"ITAMPF[8]": u1, + /// (10/13 of ITAMPF) Internal tamper X flag. This flag is set by hardware when a tamper detection event is detected on the internal tamper X. + @"ITAMPF[9]": u1, + /// (11/13 of ITAMPF) Internal tamper X flag. This flag is set by hardware when a tamper detection event is detected on the internal tamper X. + @"ITAMPF[10]": u1, + /// (12/13 of ITAMPF) Internal tamper X flag. This flag is set by hardware when a tamper detection event is detected on the internal tamper X. + @"ITAMPF[11]": u1, + /// (13/13 of ITAMPF) Internal tamper X flag. This flag is set by hardware when a tamper detection event is detected on the internal tamper X. + @"ITAMPF[12]": u1, + padding: u3, }), /// TAMP non-secure masked interrupt status register MISR: mmio.Mmio(packed struct(u32) { - /// TAMPx non-secure interrupt masked flag. This flag is set by hardware when the tamper X non-secure interrupt is raised. - TAMPMF: u1, - reserved16: u15, - /// Internal tamper X non-secure interrupt masked flag. This flag is set by hardware when the internal tamper X non-secure interrupt is raised. - ITAMPMF: u1, - padding: u15, + /// (1/8 of TAMPMF) TAMPx non-secure interrupt masked flag. This flag is set by hardware when the tamper X non-secure interrupt is raised. + @"TAMPMF[0]": u1, + /// (2/8 of TAMPMF) TAMPx non-secure interrupt masked flag. This flag is set by hardware when the tamper X non-secure interrupt is raised. + @"TAMPMF[1]": u1, + /// (3/8 of TAMPMF) TAMPx non-secure interrupt masked flag. This flag is set by hardware when the tamper X non-secure interrupt is raised. + @"TAMPMF[2]": u1, + /// (4/8 of TAMPMF) TAMPx non-secure interrupt masked flag. This flag is set by hardware when the tamper X non-secure interrupt is raised. + @"TAMPMF[3]": u1, + /// (5/8 of TAMPMF) TAMPx non-secure interrupt masked flag. This flag is set by hardware when the tamper X non-secure interrupt is raised. + @"TAMPMF[4]": u1, + /// (6/8 of TAMPMF) TAMPx non-secure interrupt masked flag. This flag is set by hardware when the tamper X non-secure interrupt is raised. + @"TAMPMF[5]": u1, + /// (7/8 of TAMPMF) TAMPx non-secure interrupt masked flag. This flag is set by hardware when the tamper X non-secure interrupt is raised. + @"TAMPMF[6]": u1, + /// (8/8 of TAMPMF) TAMPx non-secure interrupt masked flag. This flag is set by hardware when the tamper X non-secure interrupt is raised. + @"TAMPMF[7]": u1, + reserved16: u8, + /// (1/13 of ITAMPMF) Internal tamper X non-secure interrupt masked flag. This flag is set by hardware when the internal tamper X non-secure interrupt is raised. + @"ITAMPMF[0]": u1, + /// (2/13 of ITAMPMF) Internal tamper X non-secure interrupt masked flag. This flag is set by hardware when the internal tamper X non-secure interrupt is raised. + @"ITAMPMF[1]": u1, + /// (3/13 of ITAMPMF) Internal tamper X non-secure interrupt masked flag. This flag is set by hardware when the internal tamper X non-secure interrupt is raised. + @"ITAMPMF[2]": u1, + /// (4/13 of ITAMPMF) Internal tamper X non-secure interrupt masked flag. This flag is set by hardware when the internal tamper X non-secure interrupt is raised. + @"ITAMPMF[3]": u1, + /// (5/13 of ITAMPMF) Internal tamper X non-secure interrupt masked flag. This flag is set by hardware when the internal tamper X non-secure interrupt is raised. + @"ITAMPMF[4]": u1, + /// (6/13 of ITAMPMF) Internal tamper X non-secure interrupt masked flag. This flag is set by hardware when the internal tamper X non-secure interrupt is raised. + @"ITAMPMF[5]": u1, + /// (7/13 of ITAMPMF) Internal tamper X non-secure interrupt masked flag. This flag is set by hardware when the internal tamper X non-secure interrupt is raised. + @"ITAMPMF[6]": u1, + /// (8/13 of ITAMPMF) Internal tamper X non-secure interrupt masked flag. This flag is set by hardware when the internal tamper X non-secure interrupt is raised. + @"ITAMPMF[7]": u1, + /// (9/13 of ITAMPMF) Internal tamper X non-secure interrupt masked flag. This flag is set by hardware when the internal tamper X non-secure interrupt is raised. + @"ITAMPMF[8]": u1, + /// (10/13 of ITAMPMF) Internal tamper X non-secure interrupt masked flag. This flag is set by hardware when the internal tamper X non-secure interrupt is raised. + @"ITAMPMF[9]": u1, + /// (11/13 of ITAMPMF) Internal tamper X non-secure interrupt masked flag. This flag is set by hardware when the internal tamper X non-secure interrupt is raised. + @"ITAMPMF[10]": u1, + /// (12/13 of ITAMPMF) Internal tamper X non-secure interrupt masked flag. This flag is set by hardware when the internal tamper X non-secure interrupt is raised. + @"ITAMPMF[11]": u1, + /// (13/13 of ITAMPMF) Internal tamper X non-secure interrupt masked flag. This flag is set by hardware when the internal tamper X non-secure interrupt is raised. + @"ITAMPMF[12]": u1, + padding: u3, }), /// TAMP secure masked interrupt status register SMISR: mmio.Mmio(packed struct(u32) { - /// TAMPx secure interrupt masked flag. This flag is set by hardware when the tamper X secure interrupt is raised. - TAMPMF: u1, - reserved16: u15, - /// Internal tamper X secure interrupt masked flag. This flag is set by hardware when the internal tamper X secure interrupt is raised. - ITAMPMF: u1, - padding: u15, + /// (1/8 of TAMPMF) TAMPx secure interrupt masked flag. This flag is set by hardware when the tamper X secure interrupt is raised. + @"TAMPMF[0]": u1, + /// (2/8 of TAMPMF) TAMPx secure interrupt masked flag. This flag is set by hardware when the tamper X secure interrupt is raised. + @"TAMPMF[1]": u1, + /// (3/8 of TAMPMF) TAMPx secure interrupt masked flag. This flag is set by hardware when the tamper X secure interrupt is raised. + @"TAMPMF[2]": u1, + /// (4/8 of TAMPMF) TAMPx secure interrupt masked flag. This flag is set by hardware when the tamper X secure interrupt is raised. + @"TAMPMF[3]": u1, + /// (5/8 of TAMPMF) TAMPx secure interrupt masked flag. This flag is set by hardware when the tamper X secure interrupt is raised. + @"TAMPMF[4]": u1, + /// (6/8 of TAMPMF) TAMPx secure interrupt masked flag. This flag is set by hardware when the tamper X secure interrupt is raised. + @"TAMPMF[5]": u1, + /// (7/8 of TAMPMF) TAMPx secure interrupt masked flag. This flag is set by hardware when the tamper X secure interrupt is raised. + @"TAMPMF[6]": u1, + /// (8/8 of TAMPMF) TAMPx secure interrupt masked flag. This flag is set by hardware when the tamper X secure interrupt is raised. + @"TAMPMF[7]": u1, + reserved16: u8, + /// (1/13 of ITAMPMF) Internal tamper X secure interrupt masked flag. This flag is set by hardware when the internal tamper X secure interrupt is raised. + @"ITAMPMF[0]": u1, + /// (2/13 of ITAMPMF) Internal tamper X secure interrupt masked flag. This flag is set by hardware when the internal tamper X secure interrupt is raised. + @"ITAMPMF[1]": u1, + /// (3/13 of ITAMPMF) Internal tamper X secure interrupt masked flag. This flag is set by hardware when the internal tamper X secure interrupt is raised. + @"ITAMPMF[2]": u1, + /// (4/13 of ITAMPMF) Internal tamper X secure interrupt masked flag. This flag is set by hardware when the internal tamper X secure interrupt is raised. + @"ITAMPMF[3]": u1, + /// (5/13 of ITAMPMF) Internal tamper X secure interrupt masked flag. This flag is set by hardware when the internal tamper X secure interrupt is raised. + @"ITAMPMF[4]": u1, + /// (6/13 of ITAMPMF) Internal tamper X secure interrupt masked flag. This flag is set by hardware when the internal tamper X secure interrupt is raised. + @"ITAMPMF[5]": u1, + /// (7/13 of ITAMPMF) Internal tamper X secure interrupt masked flag. This flag is set by hardware when the internal tamper X secure interrupt is raised. + @"ITAMPMF[6]": u1, + /// (8/13 of ITAMPMF) Internal tamper X secure interrupt masked flag. This flag is set by hardware when the internal tamper X secure interrupt is raised. + @"ITAMPMF[7]": u1, + /// (9/13 of ITAMPMF) Internal tamper X secure interrupt masked flag. This flag is set by hardware when the internal tamper X secure interrupt is raised. + @"ITAMPMF[8]": u1, + /// (10/13 of ITAMPMF) Internal tamper X secure interrupt masked flag. This flag is set by hardware when the internal tamper X secure interrupt is raised. + @"ITAMPMF[9]": u1, + /// (11/13 of ITAMPMF) Internal tamper X secure interrupt masked flag. This flag is set by hardware when the internal tamper X secure interrupt is raised. + @"ITAMPMF[10]": u1, + /// (12/13 of ITAMPMF) Internal tamper X secure interrupt masked flag. This flag is set by hardware when the internal tamper X secure interrupt is raised. + @"ITAMPMF[11]": u1, + /// (13/13 of ITAMPMF) Internal tamper X secure interrupt masked flag. This flag is set by hardware when the internal tamper X secure interrupt is raised. + @"ITAMPMF[12]": u1, + padding: u3, }), /// TAMP status clear register SCR: mmio.Mmio(packed struct(u32) { - /// Clear TAMPx detection flag. Writing 1 in this bit clears the TAMPxF bit in the SR register. - CTAMPF: u1, - reserved16: u15, - /// Clear ITAMPx detection flag. Writing 1 in this bit clears the ITAMPxF bit in the SR register. - CITAMPF: u1, - padding: u15, + /// (1/8 of CTAMPF) Clear TAMPx detection flag. Writing 1 in this bit clears the TAMPxF bit in the SR register. + @"CTAMPF[0]": u1, + /// (2/8 of CTAMPF) Clear TAMPx detection flag. Writing 1 in this bit clears the TAMPxF bit in the SR register. + @"CTAMPF[1]": u1, + /// (3/8 of CTAMPF) Clear TAMPx detection flag. Writing 1 in this bit clears the TAMPxF bit in the SR register. + @"CTAMPF[2]": u1, + /// (4/8 of CTAMPF) Clear TAMPx detection flag. Writing 1 in this bit clears the TAMPxF bit in the SR register. + @"CTAMPF[3]": u1, + /// (5/8 of CTAMPF) Clear TAMPx detection flag. Writing 1 in this bit clears the TAMPxF bit in the SR register. + @"CTAMPF[4]": u1, + /// (6/8 of CTAMPF) Clear TAMPx detection flag. Writing 1 in this bit clears the TAMPxF bit in the SR register. + @"CTAMPF[5]": u1, + /// (7/8 of CTAMPF) Clear TAMPx detection flag. Writing 1 in this bit clears the TAMPxF bit in the SR register. + @"CTAMPF[6]": u1, + /// (8/8 of CTAMPF) Clear TAMPx detection flag. Writing 1 in this bit clears the TAMPxF bit in the SR register. + @"CTAMPF[7]": u1, + reserved16: u8, + /// (1/13 of CITAMPF) Clear ITAMPx detection flag. Writing 1 in this bit clears the ITAMPxF bit in the SR register. + @"CITAMPF[0]": u1, + /// (2/13 of CITAMPF) Clear ITAMPx detection flag. Writing 1 in this bit clears the ITAMPxF bit in the SR register. + @"CITAMPF[1]": u1, + /// (3/13 of CITAMPF) Clear ITAMPx detection flag. Writing 1 in this bit clears the ITAMPxF bit in the SR register. + @"CITAMPF[2]": u1, + /// (4/13 of CITAMPF) Clear ITAMPx detection flag. Writing 1 in this bit clears the ITAMPxF bit in the SR register. + @"CITAMPF[3]": u1, + /// (5/13 of CITAMPF) Clear ITAMPx detection flag. Writing 1 in this bit clears the ITAMPxF bit in the SR register. + @"CITAMPF[4]": u1, + /// (6/13 of CITAMPF) Clear ITAMPx detection flag. Writing 1 in this bit clears the ITAMPxF bit in the SR register. + @"CITAMPF[5]": u1, + /// (7/13 of CITAMPF) Clear ITAMPx detection flag. Writing 1 in this bit clears the ITAMPxF bit in the SR register. + @"CITAMPF[6]": u1, + /// (8/13 of CITAMPF) Clear ITAMPx detection flag. Writing 1 in this bit clears the ITAMPxF bit in the SR register. + @"CITAMPF[7]": u1, + /// (9/13 of CITAMPF) Clear ITAMPx detection flag. Writing 1 in this bit clears the ITAMPxF bit in the SR register. + @"CITAMPF[8]": u1, + /// (10/13 of CITAMPF) Clear ITAMPx detection flag. Writing 1 in this bit clears the ITAMPxF bit in the SR register. + @"CITAMPF[9]": u1, + /// (11/13 of CITAMPF) Clear ITAMPx detection flag. Writing 1 in this bit clears the ITAMPxF bit in the SR register. + @"CITAMPF[10]": u1, + /// (12/13 of CITAMPF) Clear ITAMPx detection flag. Writing 1 in this bit clears the ITAMPxF bit in the SR register. + @"CITAMPF[11]": u1, + /// (13/13 of CITAMPF) Clear ITAMPx detection flag. Writing 1 in this bit clears the ITAMPxF bit in the SR register. + @"CITAMPF[12]": u1, + padding: u3, }), /// TAMP monotonic counter 1 register COUNTR: mmio.Mmio(packed struct(u32) { @@ -423309,32 +437254,76 @@ pub const types = struct { pub const TAMP = extern struct { /// control register 1 CR1: mmio.Mmio(packed struct(u32) { - /// Tamper detection on IN X enable - TAMPE: u1, - reserved16: u15, - /// Internal tamper X enable - ITAMPE: u1, - padding: u15, + /// (1/3 of TAMPE) Tamper detection on IN X enable + @"TAMPE[0]": u1, + /// (2/3 of TAMPE) Tamper detection on IN X enable + @"TAMPE[1]": u1, + /// (3/3 of TAMPE) Tamper detection on IN X enable + @"TAMPE[2]": u1, + reserved16: u13, + /// (1/8 of ITAMPE) Internal tamper X enable + @"ITAMPE[0]": u1, + /// (2/8 of ITAMPE) Internal tamper X enable + @"ITAMPE[1]": u1, + /// (3/8 of ITAMPE) Internal tamper X enable + @"ITAMPE[2]": u1, + /// (4/8 of ITAMPE) Internal tamper X enable + @"ITAMPE[3]": u1, + /// (5/8 of ITAMPE) Internal tamper X enable + @"ITAMPE[4]": u1, + /// (6/8 of ITAMPE) Internal tamper X enable + @"ITAMPE[5]": u1, + /// (7/8 of ITAMPE) Internal tamper X enable + @"ITAMPE[6]": u1, + /// (8/8 of ITAMPE) Internal tamper X enable + @"ITAMPE[7]": u1, + padding: u8, }), /// control register 2 CR2: mmio.Mmio(packed struct(u32) { - /// Tamper X no erase - TAMPNOER: u1, - reserved16: u15, - /// Tamper X mask. The tamper X interrupt must not be enabled when TAMPMSK is set. - TAMPMSK: TAMPMSK, - reserved23: u6, + /// (1/3 of TAMPNOER) Tamper X no erase + @"TAMPNOER[0]": u1, + /// (2/3 of TAMPNOER) Tamper X no erase + @"TAMPNOER[1]": u1, + /// (3/3 of TAMPNOER) Tamper X no erase + @"TAMPNOER[2]": u1, + reserved16: u13, + /// (1/3 of TAMPMSK) Tamper X mask. The tamper X interrupt must not be enabled when TAMPMSK is set. + @"TAMPMSK[0]": TAMPMSK, + /// (2/3 of TAMPMSK) Tamper X mask. The tamper X interrupt must not be enabled when TAMPMSK is set. + @"TAMPMSK[1]": TAMPMSK, + /// (3/3 of TAMPMSK) Tamper X mask. The tamper X interrupt must not be enabled when TAMPMSK is set. + @"TAMPMSK[2]": TAMPMSK, + reserved23: u4, /// Backup registers erase BKERASE: BKERASE, - /// Active level for tamper X input - TAMPTRG: TAMPTRG, - padding: u7, + /// (1/3 of TAMPTRG) Active level for tamper X input + @"TAMPTRG[0]": TAMPTRG, + /// (2/3 of TAMPTRG) Active level for tamper X input + @"TAMPTRG[1]": TAMPTRG, + /// (3/3 of TAMPTRG) Active level for tamper X input + @"TAMPTRG[2]": TAMPTRG, + padding: u5, }), /// TAMP control register 3 CR3: mmio.Mmio(packed struct(u32) { - /// Internal Tamper X no erase - ITAMPNOER: u1, - padding: u31, + /// (1/8 of ITAMPNOER) Internal Tamper X no erase + @"ITAMPNOER[0]": u1, + /// (2/8 of ITAMPNOER) Internal Tamper X no erase + @"ITAMPNOER[1]": u1, + /// (3/8 of ITAMPNOER) Internal Tamper X no erase + @"ITAMPNOER[2]": u1, + /// (4/8 of ITAMPNOER) Internal Tamper X no erase + @"ITAMPNOER[3]": u1, + /// (5/8 of ITAMPNOER) Internal Tamper X no erase + @"ITAMPNOER[4]": u1, + /// (6/8 of ITAMPNOER) Internal Tamper X no erase + @"ITAMPNOER[5]": u1, + /// (7/8 of ITAMPNOER) Internal Tamper X no erase + @"ITAMPNOER[6]": u1, + /// (8/8 of ITAMPNOER) Internal Tamper X no erase + @"ITAMPNOER[7]": u1, + padding: u24, }), /// TAMP filter control register FLTCR: mmio.Mmio(packed struct(u32) { @@ -423351,40 +437340,112 @@ pub const types = struct { reserved44: [28]u8, /// TAMP interrupt enable register IER: mmio.Mmio(packed struct(u32) { - /// Tamper X interrupt enable - TAMPIE: u1, - reserved16: u15, - /// Internal tamper X interrupt enable - ITAMPIE: u1, - padding: u15, + /// (1/3 of TAMPIE) Tamper X interrupt enable + @"TAMPIE[0]": u1, + /// (2/3 of TAMPIE) Tamper X interrupt enable + @"TAMPIE[1]": u1, + /// (3/3 of TAMPIE) Tamper X interrupt enable + @"TAMPIE[2]": u1, + reserved16: u13, + /// (1/8 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[0]": u1, + /// (2/8 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[1]": u1, + /// (3/8 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[2]": u1, + /// (4/8 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[3]": u1, + /// (5/8 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[4]": u1, + /// (6/8 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[5]": u1, + /// (7/8 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[6]": u1, + /// (8/8 of ITAMPIE) Internal tamper X interrupt enable + @"ITAMPIE[7]": u1, + padding: u8, }), /// TAMP status register SR: mmio.Mmio(packed struct(u32) { - /// Tamper X detection flag - TAMPF: u1, - reserved16: u15, - /// Internal tamper X detection flag - ITAMPF: u1, - padding: u15, + /// (1/3 of TAMPF) Tamper X detection flag + @"TAMPF[0]": u1, + /// (2/3 of TAMPF) Tamper X detection flag + @"TAMPF[1]": u1, + /// (3/3 of TAMPF) Tamper X detection flag + @"TAMPF[2]": u1, + reserved16: u13, + /// (1/8 of ITAMPF) Internal tamper X detection flag + @"ITAMPF[0]": u1, + /// (2/8 of ITAMPF) Internal tamper X detection flag + @"ITAMPF[1]": u1, + /// (3/8 of ITAMPF) Internal tamper X detection flag + @"ITAMPF[2]": u1, + /// (4/8 of ITAMPF) Internal tamper X detection flag + @"ITAMPF[3]": u1, + /// (5/8 of ITAMPF) Internal tamper X detection flag + @"ITAMPF[4]": u1, + /// (6/8 of ITAMPF) Internal tamper X detection flag + @"ITAMPF[5]": u1, + /// (7/8 of ITAMPF) Internal tamper X detection flag + @"ITAMPF[6]": u1, + /// (8/8 of ITAMPF) Internal tamper X detection flag + @"ITAMPF[7]": u1, + padding: u8, }), /// TAMP masked interrupt status register MISR: mmio.Mmio(packed struct(u32) { - /// Tamper X interrupt masked flag - TAMPMF: u1, - reserved16: u15, - /// Internal tamper X interrupt masked flag - ITAMPMF: u1, - padding: u15, + /// (1/3 of TAMPMF) Tamper X interrupt masked flag + @"TAMPMF[0]": u1, + /// (2/3 of TAMPMF) Tamper X interrupt masked flag + @"TAMPMF[1]": u1, + /// (3/3 of TAMPMF) Tamper X interrupt masked flag + @"TAMPMF[2]": u1, + reserved16: u13, + /// (1/8 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[0]": u1, + /// (2/8 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[1]": u1, + /// (3/8 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[2]": u1, + /// (4/8 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[3]": u1, + /// (5/8 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[4]": u1, + /// (6/8 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[5]": u1, + /// (7/8 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[6]": u1, + /// (8/8 of ITAMPMF) Internal tamper X interrupt masked flag + @"ITAMPMF[7]": u1, + padding: u8, }), reserved60: [4]u8, /// TAMP status clear register SCR: mmio.Mmio(packed struct(u32) { - /// Clear tamper X detection flag - CTAMPF: u1, - reserved16: u15, - /// Clear internal tamper X detection flag - CITAMPF: u1, - padding: u15, + /// (1/3 of CTAMPF) Clear tamper X detection flag + @"CTAMPF[0]": u1, + /// (2/3 of CTAMPF) Clear tamper X detection flag + @"CTAMPF[1]": u1, + /// (3/3 of CTAMPF) Clear tamper X detection flag + @"CTAMPF[2]": u1, + reserved16: u13, + /// (1/8 of CITAMPF) Clear internal tamper X detection flag + @"CITAMPF[0]": u1, + /// (2/8 of CITAMPF) Clear internal tamper X detection flag + @"CITAMPF[1]": u1, + /// (3/8 of CITAMPF) Clear internal tamper X detection flag + @"CITAMPF[2]": u1, + /// (4/8 of CITAMPF) Clear internal tamper X detection flag + @"CITAMPF[3]": u1, + /// (5/8 of CITAMPF) Clear internal tamper X detection flag + @"CITAMPF[4]": u1, + /// (6/8 of CITAMPF) Clear internal tamper X detection flag + @"CITAMPF[5]": u1, + /// (7/8 of CITAMPF) Clear internal tamper X detection flag + @"CITAMPF[6]": u1, + /// (8/8 of CITAMPF) Clear internal tamper X detection flag + @"CITAMPF[7]": u1, + padding: u8, }), /// monotonic counter register COUNTR: mmio.Mmio(packed struct(u32) { @@ -423615,47 +437676,47 @@ pub const types = struct { /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/Compare x (x=1) interrupt enable - CCIE: u1, + /// (1/1 of CCIE) Capture/Compare x (x=1) interrupt enable + @"CCIE[0]": u1, padding: u30, }), /// status register SR: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/compare x (x=1) interrupt flag - CCIF: u1, + /// (1/1 of CCIF) Capture/compare x (x=1) interrupt flag + @"CCIF[0]": u1, reserved9: u7, - /// Capture/Compare x (x=1) overcapture flag - CCOF: u1, + /// (1/1 of CCOF) Capture/Compare x (x=1) overcapture flag + @"CCOF[0]": u1, padding: u22, }), /// event generation register EGR: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/compare x (x=1) generation - CCG: u1, + /// (1/1 of CCG) Capture/compare x (x=1) generation + @"CCG[0]": u1, padding: u30, }), /// capture/compare mode register 1 (input mode) CCMR_Input: [1]mmio.Mmio(packed struct(u32) { - /// Capture/Compare y selection - CCS: CCMR_Input_CCS, - /// Input capture y prescaler - ICPSC: u2, - /// Input capture y filter - ICF: FilterValue, + /// (1/1 of CCS) Capture/Compare y selection + @"CCS[0]": CCMR_Input_CCS, + /// (1/1 of ICPSC) Input capture y prescaler + @"ICPSC[0]": u2, + /// (1/1 of ICF) Input capture y filter + @"ICF[0]": FilterValue, padding: u24, }), reserved32: [4]u8, /// capture/compare enable register CCER: mmio.Mmio(packed struct(u32) { - /// Capture/Compare x (x=1) output enable - CCE: u1, - /// Capture/Compare x (x=1) output Polarity - CCP: u1, + /// (1/1 of CCE) Capture/Compare x (x=1) output enable + @"CCE[0]": u1, + /// (1/1 of CCP) Capture/Compare x (x=1) output Polarity + @"CCP[0]": u1, reserved3: u1, - /// Capture/Compare x (x=1) output Polarity - CCNP: u1, + /// (1/1 of CCNP) Capture/Compare x (x=1) output Polarity + @"CCNP[0]": u1, padding: u28, }), reserved52: [16]u8, @@ -423704,9 +437765,11 @@ pub const types = struct { /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/Compare x (x=1-2) interrupt enable - CCIE: u1, - reserved6: u4, + /// (1/2 of CCIE) Capture/Compare x (x=1-2) interrupt enable + @"CCIE[0]": u1, + /// (2/2 of CCIE) Capture/Compare x (x=1-2) interrupt enable + @"CCIE[1]": u1, + reserved6: u3, /// Trigger interrupt enable TIE: u1, padding: u25, @@ -423714,47 +437777,66 @@ pub const types = struct { /// status register SR: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/compare x (x=1-2) interrupt flag - CCIF: u1, - reserved6: u4, + /// (1/2 of CCIF) Capture/compare x (x=1-2) interrupt flag + @"CCIF[0]": u1, + /// (2/2 of CCIF) Capture/compare x (x=1-2) interrupt flag + @"CCIF[1]": u1, + reserved6: u3, /// Trigger interrupt flag TIF: u1, reserved9: u2, - /// Capture/Compare x (x=1-2) overcapture flag - CCOF: u1, - padding: u22, + /// (1/2 of CCOF) Capture/Compare x (x=1-2) overcapture flag + @"CCOF[0]": u1, + /// (2/2 of CCOF) Capture/Compare x (x=1-2) overcapture flag + @"CCOF[1]": u1, + padding: u21, }), /// event generation register EGR: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/compare x (x=1-2) generation - CCG: u1, - reserved6: u4, + /// (1/2 of CCG) Capture/compare x (x=1-2) generation + @"CCG[0]": u1, + /// (2/2 of CCG) Capture/compare x (x=1-2) generation + @"CCG[1]": u1, + reserved6: u3, /// Trigger generation TG: u1, padding: u25, }), /// capture/compare mode register 1 (input mode) CCMR_Input: [1]mmio.Mmio(packed struct(u32) { - /// Capture/Compare y selection - CCS: CCMR_Input_CCS, - /// Input capture y prescaler - ICPSC: u2, - /// Input capture y filter - ICF: FilterValue, - padding: u24, + /// (1/2 of CCS) Capture/Compare y selection + @"CCS[0]": CCMR_Input_CCS, + /// (1/2 of ICPSC) Input capture y prescaler + @"ICPSC[0]": u2, + /// (1/2 of ICF) Input capture y filter + @"ICF[0]": FilterValue, + /// (2/2 of CCS) Capture/Compare y selection + @"CCS[1]": CCMR_Input_CCS, + /// (2/2 of ICPSC) Input capture y prescaler + @"ICPSC[1]": u2, + /// (2/2 of ICF) Input capture y filter + @"ICF[1]": FilterValue, + padding: u16, }), reserved32: [4]u8, /// capture/compare enable register CCER: mmio.Mmio(packed struct(u32) { - /// Capture/Compare x (x=1-2) output enable - CCE: u1, - /// Capture/Compare x (x=1-2) output Polarity - CCP: u1, + /// (1/2 of CCE) Capture/Compare x (x=1-2) output enable + @"CCE[0]": u1, + /// (1/2 of CCP) Capture/Compare x (x=1-2) output Polarity + @"CCP[0]": u1, reserved3: u1, - /// Capture/Compare x (x=1-2) output Polarity - CCNP: u1, - padding: u28, + /// (1/2 of CCNP) Capture/Compare x (x=1-2) output Polarity + @"CCNP[0]": u1, + /// (2/2 of CCE) Capture/Compare x (x=1-2) output enable + @"CCE[1]": u1, + /// (2/2 of CCP) Capture/Compare x (x=1-2) output Polarity + @"CCP[1]": u1, + reserved7: u1, + /// (2/2 of CCNP) Capture/Compare x (x=1-2) output Polarity + @"CCNP[1]": u1, + padding: u24, }), reserved52: [16]u8, /// capture/compare register x (x=1-2) @@ -423893,15 +437975,27 @@ pub const types = struct { /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/Compare x (x=1-4) interrupt enable - CCIE: u1, - reserved6: u4, + /// (1/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable + @"CCIE[0]": u1, + /// (2/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable + @"CCIE[1]": u1, + /// (3/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable + @"CCIE[2]": u1, + /// (4/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable + @"CCIE[3]": u1, + reserved6: u1, /// Trigger interrupt enable TIE: u1, reserved9: u2, - /// Capture/Compare x (x=1-4) DMA request enable - CCDE: u1, - reserved14: u4, + /// (1/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable + @"CCDE[0]": u1, + /// (2/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable + @"CCDE[1]": u1, + /// (3/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable + @"CCDE[2]": u1, + /// (4/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable + @"CCDE[3]": u1, + reserved14: u1, /// Trigger DMA request enable TDE: u1, padding: u17, @@ -423909,46 +438003,91 @@ pub const types = struct { /// status register SR: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/compare x (x=1-4) interrupt flag - CCIF: u1, - reserved6: u4, + /// (1/4 of CCIF) Capture/compare x (x=1-4) interrupt flag + @"CCIF[0]": u1, + /// (2/4 of CCIF) Capture/compare x (x=1-4) interrupt flag + @"CCIF[1]": u1, + /// (3/4 of CCIF) Capture/compare x (x=1-4) interrupt flag + @"CCIF[2]": u1, + /// (4/4 of CCIF) Capture/compare x (x=1-4) interrupt flag + @"CCIF[3]": u1, + reserved6: u1, /// Trigger interrupt flag TIF: u1, reserved9: u2, - /// Capture/Compare x (x=1-4) overcapture flag - CCOF: u1, - padding: u22, + /// (1/4 of CCOF) Capture/Compare x (x=1-4) overcapture flag + @"CCOF[0]": u1, + /// (2/4 of CCOF) Capture/Compare x (x=1-4) overcapture flag + @"CCOF[1]": u1, + /// (3/4 of CCOF) Capture/Compare x (x=1-4) overcapture flag + @"CCOF[2]": u1, + /// (4/4 of CCOF) Capture/Compare x (x=1-4) overcapture flag + @"CCOF[3]": u1, + padding: u19, }), /// event generation register EGR: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/compare x (x=1-4) generation - CCG: u1, - reserved6: u4, + /// (1/4 of CCG) Capture/compare x (x=1-4) generation + @"CCG[0]": u1, + /// (2/4 of CCG) Capture/compare x (x=1-4) generation + @"CCG[1]": u1, + /// (3/4 of CCG) Capture/compare x (x=1-4) generation + @"CCG[2]": u1, + /// (4/4 of CCG) Capture/compare x (x=1-4) generation + @"CCG[3]": u1, + reserved6: u1, /// Trigger generation TG: u1, padding: u25, }), /// capture/compare mode register 1-2 (input mode) CCMR_Input: [2]mmio.Mmio(packed struct(u32) { - /// Capture/Compare y selection - CCS: CCMR_Input_CCS, - /// Input capture y prescaler - ICPSC: u2, - /// Input capture y filter - ICF: FilterValue, - padding: u24, + /// (1/2 of CCS) Capture/Compare y selection + @"CCS[0]": CCMR_Input_CCS, + /// (1/2 of ICPSC) Input capture y prescaler + @"ICPSC[0]": u2, + /// (1/2 of ICF) Input capture y filter + @"ICF[0]": FilterValue, + /// (2/2 of CCS) Capture/Compare y selection + @"CCS[1]": CCMR_Input_CCS, + /// (2/2 of ICPSC) Input capture y prescaler + @"ICPSC[1]": u2, + /// (2/2 of ICF) Input capture y filter + @"ICF[1]": FilterValue, + padding: u16, }), /// capture/compare enable register CCER: mmio.Mmio(packed struct(u32) { - /// Capture/Compare x (x=1-4) output enable - CCE: u1, - /// Capture/Compare x (x=1-4) output Polarity - CCP: u1, + /// (1/4 of CCE) Capture/Compare x (x=1-4) output enable + @"CCE[0]": u1, + /// (1/4 of CCP) Capture/Compare x (x=1-4) output Polarity + @"CCP[0]": u1, reserved3: u1, - /// Capture/Compare x (x=1-4) output Polarity - CCNP: u1, - padding: u28, + /// (1/4 of CCNP) Capture/Compare x (x=1-4) output Polarity + @"CCNP[0]": u1, + /// (2/4 of CCE) Capture/Compare x (x=1-4) output enable + @"CCE[1]": u1, + /// (2/4 of CCP) Capture/Compare x (x=1-4) output Polarity + @"CCP[1]": u1, + reserved7: u1, + /// (2/4 of CCNP) Capture/Compare x (x=1-4) output Polarity + @"CCNP[1]": u1, + /// (3/4 of CCE) Capture/Compare x (x=1-4) output enable + @"CCE[2]": u1, + /// (3/4 of CCP) Capture/Compare x (x=1-4) output Polarity + @"CCP[2]": u1, + reserved11: u1, + /// (3/4 of CCNP) Capture/Compare x (x=1-4) output Polarity + @"CCNP[2]": u1, + /// (4/4 of CCE) Capture/Compare x (x=1-4) output enable + @"CCE[3]": u1, + /// (4/4 of CCP) Capture/Compare x (x=1-4) output Polarity + @"CCP[3]": u1, + reserved15: u1, + /// (4/4 of CCNP) Capture/Compare x (x=1-4) output Polarity + @"CCNP[3]": u1, + padding: u16, }), reserved52: [16]u8, /// capture/compare register x (x=1-4) @@ -424276,47 +438415,47 @@ pub const types = struct { /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/Compare x (x=1) interrupt enable - CCIE: u1, + /// (1/1 of CCIE) Capture/Compare x (x=1) interrupt enable + @"CCIE[0]": u1, padding: u30, }), /// status register SR: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/compare x (x=1) interrupt flag - CCIF: u1, + /// (1/1 of CCIF) Capture/compare x (x=1) interrupt flag + @"CCIF[0]": u1, reserved9: u7, - /// Capture/Compare x (x=1) overcapture flag - CCOF: u1, + /// (1/1 of CCOF) Capture/Compare x (x=1) overcapture flag + @"CCOF[0]": u1, padding: u22, }), /// event generation register EGR: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/compare x (x=1) generation - CCG: u1, + /// (1/1 of CCG) Capture/compare x (x=1) generation + @"CCG[0]": u1, padding: u30, }), /// capture/compare mode register 1 (input mode) CCMR_Input: [1]mmio.Mmio(packed struct(u32) { - /// Capture/Compare y selection - CCS: CCMR_Input_CCS, - /// Input capture y prescaler - ICPSC: u2, - /// Input capture y filter - ICF: FilterValue, + /// (1/1 of CCS) Capture/Compare y selection + @"CCS[0]": CCMR_Input_CCS, + /// (1/1 of ICPSC) Input capture y prescaler + @"ICPSC[0]": u2, + /// (1/1 of ICF) Input capture y filter + @"ICF[0]": FilterValue, padding: u24, }), reserved32: [4]u8, /// capture/compare enable register CCER: mmio.Mmio(packed struct(u32) { - /// Capture/Compare x (x=1) output enable - CCE: u1, - /// Capture/Compare x (x=1) output Polarity - CCP: u1, + /// (1/1 of CCE) Capture/Compare x (x=1) output enable + @"CCE[0]": u1, + /// (1/1 of CCP) Capture/Compare x (x=1) output Polarity + @"CCP[0]": u1, reserved3: u1, - /// Capture/Compare x (x=1) output Polarity - CCNP: u1, + /// (1/1 of CCNP) Capture/Compare x (x=1) output Polarity + @"CCNP[0]": u1, padding: u28, }), reserved52: [16]u8, @@ -424332,8 +438471,8 @@ pub const types = struct { reserved104: [20]u8, /// input selection register TISEL: mmio.Mmio(packed struct(u32) { - /// Selects TIM_TIx (x=1) input - TISEL: u4, + /// (1/1 of TISEL) Selects TIM_TIx (x=1) input + @"TISEL[0]": u4, padding: u28, }), }; @@ -424351,10 +438490,10 @@ pub const types = struct { /// Capture/compare DMA selection CCDS: CCDS, reserved8: u4, - /// Output Idle state x (x=1) - OIS: u1, - /// Output Idle state x (x=1) - OISN: u1, + /// (1/1 of OIS) Output Idle state x (x=1) + @"OIS[0]": u1, + /// (1/1 of OISN) Output Idle state x (x=1) + @"OISN[0]": u1, padding: u22, }), reserved12: [4]u8, @@ -424368,8 +438507,8 @@ pub const types = struct { BIE: u1, /// Update DMA request enable UDE: u1, - /// Capture/Compare x (x=1) DMA request enable - CCDE: u1, + /// (1/1 of CCDE) Capture/Compare x (x=1) DMA request enable + @"CCDE[0]": u1, padding: u22, }), /// status register @@ -424378,8 +438517,8 @@ pub const types = struct { /// COM interrupt flag COMIF: u1, reserved7: u1, - /// Break x (x=1) interrupt flag - BIF: u1, + /// (1/1 of BIF) Break x (x=1) interrupt flag + @"BIF[0]": u1, padding: u24, }), /// event generation register @@ -424388,16 +438527,16 @@ pub const types = struct { /// Capture/Compare control update generation COMG: u1, reserved7: u1, - /// Break x (x=1) generation - BG: u1, + /// (1/1 of BG) Break x (x=1) generation + @"BG[0]": u1, padding: u24, }), reserved32: [8]u8, /// capture/compare enable register CCER: mmio.Mmio(packed struct(u32) { reserved2: u2, - /// Capture/Compare x (x=1) complementary output enable - CCNE: u1, + /// (1/1 of CCNE) Capture/Compare x (x=1) complementary output enable + @"CCNE[0]": u1, padding: u29, }), reserved48: [12]u8, @@ -424418,16 +438557,16 @@ pub const types = struct { OSSI: OSSI, /// Off-state selection for Run mode OSSR: OSSR, - /// Break x (x=1) enable - BKE: u1, - /// Break x (x=1) polarity - BKP: BKP, + /// (1/1 of BKE) Break x (x=1) enable + @"BKE[0]": u1, + /// (1/1 of BKP) Break x (x=1) polarity + @"BKP[0]": BKP, /// Automatic output enable AOE: u1, /// Main output enable MOE: u1, - /// Break x (x=1) filter - BKF: FilterValue, + /// (1/1 of BKF) Break x (x=1) filter + @"BKF[0]": FilterValue, padding: u12, }), /// DMA control register @@ -424450,16 +438589,20 @@ pub const types = struct { AF1: mmio.Mmio(packed struct(u32) { /// TIMx_BKIN input enable BKINE: u1, - /// TIM_BRK_CMPx (x=1-2) enable - BKCMPE: u1, - reserved8: u6, + /// (1/2 of BKCMPE) TIM_BRK_CMPx (x=1-2) enable + @"BKCMPE[0]": u1, + /// (2/2 of BKCMPE) TIM_BRK_CMPx (x=1-2) enable + @"BKCMPE[1]": u1, + reserved8: u5, /// BRK DFSDM1_BREAKx enable (x=0 if TIM15, x=1 if TIM16, x=2 if TIM17) BKDF1BKE: u1, /// TIMx_BKIN input polarity BKINP: BKINP, - /// TIM_BRK_CMPx (x=1-2) input polarity - BKCMPP: BKINP, - padding: u21, + /// (1/2 of BKCMPP) TIM_BRK_CMPx (x=1-2) input polarity + @"BKCMPP[0]": BKINP, + /// (2/2 of BKCMPP) TIM_BRK_CMPx (x=1-2) input polarity + @"BKCMPP[1]": BKINP, + padding: u20, }), }; @@ -424480,9 +438623,11 @@ pub const types = struct { /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/Compare x (x=1-2) interrupt enable - CCIE: u1, - reserved6: u4, + /// (1/2 of CCIE) Capture/Compare x (x=1-2) interrupt enable + @"CCIE[0]": u1, + /// (2/2 of CCIE) Capture/Compare x (x=1-2) interrupt enable + @"CCIE[1]": u1, + reserved6: u3, /// Trigger interrupt enable TIE: u1, padding: u25, @@ -424490,47 +438635,66 @@ pub const types = struct { /// status register SR: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/compare x (x=1-2) interrupt flag - CCIF: u1, - reserved6: u4, + /// (1/2 of CCIF) Capture/compare x (x=1-2) interrupt flag + @"CCIF[0]": u1, + /// (2/2 of CCIF) Capture/compare x (x=1-2) interrupt flag + @"CCIF[1]": u1, + reserved6: u3, /// Trigger interrupt flag TIF: u1, reserved9: u2, - /// Capture/Compare x (x=1-2) overcapture flag - CCOF: u1, - padding: u22, + /// (1/2 of CCOF) Capture/Compare x (x=1-2) overcapture flag + @"CCOF[0]": u1, + /// (2/2 of CCOF) Capture/Compare x (x=1-2) overcapture flag + @"CCOF[1]": u1, + padding: u21, }), /// event generation register EGR: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/compare x (x=1-2) generation - CCG: u1, - reserved6: u4, + /// (1/2 of CCG) Capture/compare x (x=1-2) generation + @"CCG[0]": u1, + /// (2/2 of CCG) Capture/compare x (x=1-2) generation + @"CCG[1]": u1, + reserved6: u3, /// Trigger generation TG: u1, padding: u25, }), /// capture/compare mode register 1 (input mode) CCMR_Input: [1]mmio.Mmio(packed struct(u32) { - /// Capture/Compare y selection - CCS: CCMR_Input_CCS, - /// Input capture y prescaler - ICPSC: u2, - /// Input capture y filter - ICF: FilterValue, - padding: u24, + /// (1/2 of CCS) Capture/Compare y selection + @"CCS[0]": CCMR_Input_CCS, + /// (1/2 of ICPSC) Input capture y prescaler + @"ICPSC[0]": u2, + /// (1/2 of ICF) Input capture y filter + @"ICF[0]": FilterValue, + /// (2/2 of CCS) Capture/Compare y selection + @"CCS[1]": CCMR_Input_CCS, + /// (2/2 of ICPSC) Input capture y prescaler + @"ICPSC[1]": u2, + /// (2/2 of ICF) Input capture y filter + @"ICF[1]": FilterValue, + padding: u16, }), reserved32: [4]u8, /// capture/compare enable register CCER: mmio.Mmio(packed struct(u32) { - /// Capture/Compare x (x=1-2) output enable - CCE: u1, - /// Capture/Compare x (x=1-2) output Polarity - CCP: u1, + /// (1/2 of CCE) Capture/Compare x (x=1-2) output enable + @"CCE[0]": u1, + /// (1/2 of CCP) Capture/Compare x (x=1-2) output Polarity + @"CCP[0]": u1, reserved3: u1, - /// Capture/Compare x (x=1-2) output Polarity - CCNP: u1, - padding: u28, + /// (1/2 of CCNP) Capture/Compare x (x=1-2) output Polarity + @"CCNP[0]": u1, + /// (2/2 of CCE) Capture/Compare x (x=1-2) output enable + @"CCE[1]": u1, + /// (2/2 of CCP) Capture/Compare x (x=1-2) output Polarity + @"CCP[1]": u1, + reserved7: u1, + /// (2/2 of CCNP) Capture/Compare x (x=1-2) output Polarity + @"CCNP[1]": u1, + padding: u24, }), reserved52: [16]u8, /// capture/compare register x (x=1-2) @@ -424542,9 +438706,12 @@ pub const types = struct { reserved104: [44]u8, /// input selection register TISEL: mmio.Mmio(packed struct(u32) { - /// Selects TIM_TIx (x=1-2) input - TISEL: u4, - padding: u28, + /// (1/2 of TISEL) Selects TIM_TIx (x=1-2) input + @"TISEL[0]": u4, + reserved8: u4, + /// (2/2 of TISEL) Selects TIM_TIx (x=1-2) input + @"TISEL[1]": u4, + padding: u20, }), }; @@ -424558,9 +438725,12 @@ pub const types = struct { MMS: MMS, /// TI1 selection TI1S: TI1S, - /// Output Idle state x (x=1,2) - OIS: u1, - padding: u23, + /// (1/2 of OIS) Output Idle state x (x=1,2) + @"OIS[0]": u1, + reserved10: u1, + /// (2/2 of OIS) Output Idle state x (x=1,2) + @"OIS[1]": u1, + padding: u21, }), /// slave mode control register SMCR: u32, @@ -424579,41 +438749,47 @@ pub const types = struct { /// status register SR: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/compare x (x=1,2) interrupt flag - CCIF: u1, - reserved6: u4, + /// (1/2 of CCIF) Capture/compare x (x=1,2) interrupt flag + @"CCIF[0]": u1, + /// (2/2 of CCIF) Capture/compare x (x=1,2) interrupt flag + @"CCIF[1]": u1, + reserved6: u3, /// Trigger interrupt flag TIF: u1, reserved9: u2, - /// Capture/Compare x (x=1,2) overcapture flag - CCOF: u1, - padding: u22, + /// (1/2 of CCOF) Capture/Compare x (x=1,2) overcapture flag + @"CCOF[0]": u1, + /// (2/2 of CCOF) Capture/Compare x (x=1,2) overcapture flag + @"CCOF[1]": u1, + padding: u21, }), /// event generation register EGR: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/compare x (x=1,2) generation - CCG: u1, - reserved6: u4, + /// (1/2 of CCG) Capture/compare x (x=1,2) generation + @"CCG[0]": u1, + /// (2/2 of CCG) Capture/compare x (x=1,2) generation + @"CCG[1]": u1, + reserved6: u3, /// Trigger generation TG: u1, padding: u25, }), /// capture/compare mode register 1 (input mode) CCMR_Input: [2]mmio.Mmio(packed struct(u32) { - /// Capture/Compare y selection - CCS: CCMR_Input_CCS, - /// Input capture y prescaler - ICPSC: u2, - /// Input capture y filter - ICF: FilterValue, + /// (1/1 of CCS) Capture/Compare y selection + @"CCS[0]": CCMR_Input_CCS, + /// (1/1 of ICPSC) Input capture y prescaler + @"ICPSC[0]": u2, + /// (1/1 of ICF) Input capture y filter + @"ICF[0]": FilterValue, padding: u24, }), /// capture/compare enable register CCER: mmio.Mmio(packed struct(u32) { reserved2: u2, - /// Capture/Compare x (x=1) complementary output enable - CCNE: u1, + /// (1/1 of CCNE) Capture/Compare x (x=1) complementary output enable + @"CCNE[0]": u1, padding: u29, }), reserved52: [16]u8, @@ -424634,24 +438810,27 @@ pub const types = struct { OSSI: OSSI, /// Off-state selection for Run mode OSSR: OSSR, - /// Break x (x=1) enable - BKE: u1, - /// Break x (x=1) polarity - BKP: BKP, + /// (1/1 of BKE) Break x (x=1) enable + @"BKE[0]": u1, + /// (1/1 of BKP) Break x (x=1) polarity + @"BKP[0]": BKP, /// Automatic output enable AOE: u1, /// Main output enable MOE: u1, - /// Break x (x=1) filter - BKF: FilterValue, + /// (1/1 of BKF) Break x (x=1) filter + @"BKF[0]": FilterValue, padding: u12, }), reserved104: [32]u8, /// input selection register TISEL: mmio.Mmio(packed struct(u32) { - /// Selects TIM_TIx (x=1-2) input - TISEL: u4, - padding: u28, + /// (1/2 of TISEL) Selects TIM_TIx (x=1-2) input + @"TISEL[0]": u4, + reserved8: u4, + /// (2/2 of TISEL) Selects TIM_TIx (x=1-2) input + @"TISEL[1]": u4, + padding: u20, }), }; @@ -424672,11 +438851,28 @@ pub const types = struct { /// control register 2 CR2: mmio.Mmio(packed struct(u32) { reserved8: u8, - /// Output Idle state x (x=1-6) - OIS: u1, - /// Output Idle state x N x (x=1-4) - OISN: u1, - reserved20: u10, + /// (1/6 of OIS) Output Idle state x (x=1-6) + @"OIS[0]": u1, + /// (1/4 of OISN) Output Idle state x N x (x=1-4) + @"OISN[0]": u1, + /// (2/6 of OIS) Output Idle state x (x=1-6) + @"OIS[1]": u1, + /// (2/4 of OISN) Output Idle state x N x (x=1-4) + @"OISN[1]": u1, + /// (3/6 of OIS) Output Idle state x (x=1-6) + @"OIS[2]": u1, + /// (3/4 of OISN) Output Idle state x N x (x=1-4) + @"OISN[2]": u1, + /// (4/6 of OIS) Output Idle state x (x=1-6) + @"OIS[3]": u1, + /// (4/4 of OISN) Output Idle state x N x (x=1-4) + @"OISN[3]": u1, + /// (5/6 of OIS) Output Idle state x (x=1-6) + @"OIS[4]": u1, + reserved18: u1, + /// (6/6 of OIS) Output Idle state x (x=1-6) + @"OIS[5]": u1, + reserved20: u1, /// Master mode selection 2 MMS2: MMS2, padding: u8, @@ -424697,25 +438893,49 @@ pub const types = struct { /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/Compare x (x=1-4) interrupt enable - CCIE: u1, - reserved9: u7, - /// Capture/Compare x (x=1-4) DMA request enable - CCDE: u1, - padding: u22, + /// (1/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable + @"CCIE[0]": u1, + /// (2/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable + @"CCIE[1]": u1, + /// (3/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable + @"CCIE[2]": u1, + /// (4/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable + @"CCIE[3]": u1, + reserved9: u4, + /// (1/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable + @"CCDE[0]": u1, + /// (2/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable + @"CCDE[1]": u1, + /// (3/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable + @"CCDE[2]": u1, + /// (4/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable + @"CCDE[3]": u1, + padding: u19, }), /// status register SR: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/compare x (x=1-4) interrupt flag - CCIF: u1, - reserved7: u5, - /// Break x (x=1,2) interrupt flag - BIF: u1, - reserved9: u1, - /// Capture/Compare x (x=1-4) overcapture flag - CCOF: u1, - reserved13: u3, + /// (1/4 of CCIF) Capture/compare x (x=1-4) interrupt flag + @"CCIF[0]": u1, + /// (2/4 of CCIF) Capture/compare x (x=1-4) interrupt flag + @"CCIF[1]": u1, + /// (3/4 of CCIF) Capture/compare x (x=1-4) interrupt flag + @"CCIF[2]": u1, + /// (4/4 of CCIF) Capture/compare x (x=1-4) interrupt flag + @"CCIF[3]": u1, + reserved7: u2, + /// (1/2 of BIF) Break x (x=1,2) interrupt flag + @"BIF[0]": u1, + /// (2/2 of BIF) Break x (x=1,2) interrupt flag + @"BIF[1]": u1, + /// (1/4 of CCOF) Capture/Compare x (x=1-4) overcapture flag + @"CCOF[0]": u1, + /// (2/4 of CCOF) Capture/Compare x (x=1-4) overcapture flag + @"CCOF[1]": u1, + /// (3/4 of CCOF) Capture/Compare x (x=1-4) overcapture flag + @"CCOF[2]": u1, + /// (4/4 of CCOF) Capture/Compare x (x=1-4) overcapture flag + @"CCOF[3]": u1, /// System break interrupt flag SBIF: u1, reserved16: u2, @@ -424728,34 +438948,80 @@ pub const types = struct { /// event generation register EGR: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/compare x (x=1-4) generation - CCG: u1, - reserved7: u5, - /// Break x (x=1-2) generation - BG: u1, - padding: u24, + /// (1/4 of CCG) Capture/compare x (x=1-4) generation + @"CCG[0]": u1, + /// (2/4 of CCG) Capture/compare x (x=1-4) generation + @"CCG[1]": u1, + /// (3/4 of CCG) Capture/compare x (x=1-4) generation + @"CCG[2]": u1, + /// (4/4 of CCG) Capture/compare x (x=1-4) generation + @"CCG[3]": u1, + reserved7: u2, + /// (1/2 of BG) Break x (x=1-2) generation + @"BG[0]": u1, + /// (2/2 of BG) Break x (x=1-2) generation + @"BG[1]": u1, + padding: u23, }), /// capture/compare mode register 1-2 (input mode) CCMR_Input: [2]mmio.Mmio(packed struct(u32) { - /// Capture/Compare y selection - CCS: CCMR_Input_CCS, - /// Input capture y prescaler - ICPSC: u2, - /// Input capture y filter - ICF: FilterValue, - padding: u24, + /// (1/2 of CCS) Capture/Compare y selection + @"CCS[0]": CCMR_Input_CCS, + /// (1/2 of ICPSC) Input capture y prescaler + @"ICPSC[0]": u2, + /// (1/2 of ICF) Input capture y filter + @"ICF[0]": FilterValue, + /// (2/2 of CCS) Capture/Compare y selection + @"CCS[1]": CCMR_Input_CCS, + /// (2/2 of ICPSC) Input capture y prescaler + @"ICPSC[1]": u2, + /// (2/2 of ICF) Input capture y filter + @"ICF[1]": FilterValue, + padding: u16, }), /// capture/compare enable register CCER: mmio.Mmio(packed struct(u32) { - /// Capture/Compare x (x=1-6) output enable - CCE: u1, - /// Capture/Compare x (x=1-6) output Polarity - CCP: u1, - /// Capture/Compare x (x=1-3) complementary output enable - CCNE: u1, - /// Capture/Compare x (x=1-4) output Polarity - CCNP: u1, - padding: u28, + /// (1/6 of CCE) Capture/Compare x (x=1-6) output enable + @"CCE[0]": u1, + /// (1/6 of CCP) Capture/Compare x (x=1-6) output Polarity + @"CCP[0]": u1, + /// (1/3 of CCNE) Capture/Compare x (x=1-3) complementary output enable + @"CCNE[0]": u1, + /// (1/4 of CCNP) Capture/Compare x (x=1-4) output Polarity + @"CCNP[0]": u1, + /// (2/6 of CCE) Capture/Compare x (x=1-6) output enable + @"CCE[1]": u1, + /// (2/6 of CCP) Capture/Compare x (x=1-6) output Polarity + @"CCP[1]": u1, + /// (2/3 of CCNE) Capture/Compare x (x=1-3) complementary output enable + @"CCNE[1]": u1, + /// (2/4 of CCNP) Capture/Compare x (x=1-4) output Polarity + @"CCNP[1]": u1, + /// (3/6 of CCE) Capture/Compare x (x=1-6) output enable + @"CCE[2]": u1, + /// (3/6 of CCP) Capture/Compare x (x=1-6) output Polarity + @"CCP[2]": u1, + /// (3/3 of CCNE) Capture/Compare x (x=1-3) complementary output enable + @"CCNE[2]": u1, + /// (3/4 of CCNP) Capture/Compare x (x=1-4) output Polarity + @"CCNP[2]": u1, + /// (4/6 of CCE) Capture/Compare x (x=1-6) output enable + @"CCE[3]": u1, + /// (4/6 of CCP) Capture/Compare x (x=1-6) output Polarity + @"CCP[3]": u1, + reserved15: u1, + /// (4/4 of CCNP) Capture/Compare x (x=1-4) output Polarity + @"CCNP[3]": u1, + /// (5/6 of CCE) Capture/Compare x (x=1-6) output enable + @"CCE[4]": u1, + /// (5/6 of CCP) Capture/Compare x (x=1-6) output Polarity + @"CCP[4]": u1, + reserved20: u2, + /// (6/6 of CCE) Capture/Compare x (x=1-6) output enable + @"CCE[5]": u1, + /// (6/6 of CCP) Capture/Compare x (x=1-6) output Polarity + @"CCP[5]": u1, + padding: u10, }), reserved48: [12]u8, /// repetition counter register @@ -424773,14 +439039,20 @@ pub const types = struct { /// break and dead-time register BDTR: mmio.Mmio(packed struct(u32) { reserved12: u12, - /// Break x (x=1,2) enable - BKE: u1, - /// Break x (x=1,2) polarity - BKP: BKP, + /// (1/2 of BKE) Break x (x=1,2) enable + @"BKE[0]": u1, + /// (1/2 of BKP) Break x (x=1,2) polarity + @"BKP[0]": BKP, reserved16: u2, - /// Break x (x=1,2) filter - BKF: FilterValue, - padding: u12, + /// (1/2 of BKF) Break x (x=1,2) filter + @"BKF[0]": FilterValue, + /// (2/2 of BKF) Break x (x=1,2) filter + @"BKF[1]": FilterValue, + /// (2/2 of BKE) Break x (x=1,2) enable + @"BKE[1]": u1, + /// (2/2 of BKP) Break x (x=1,2) polarity + @"BKP[1]": BKP, + padding: u6, }), reserved76: [4]u8, /// DMA address for full transfer @@ -424789,22 +439061,34 @@ pub const types = struct { /// capture/compare mode register 3 CCMR3: mmio.Mmio(packed struct(u32) { reserved2: u2, - /// Output compare x (x=5,6) fast enable - OCFE: u1, - /// Output compare x (x=5,6) preload enable - OCPE: u1, - /// Output compare x (x=5,6) mode - OCM: OCM, - /// Output compare x (x=5,6) clear enable - OCCE: u1, - padding: u24, + /// (1/2 of OCFE) Output compare x (x=5,6) fast enable + @"OCFE[0]": u1, + /// (1/2 of OCPE) Output compare x (x=5,6) preload enable + @"OCPE[0]": u1, + /// (1/2 of OCM) Output compare x (x=5,6) mode + @"OCM[0]": OCM, + /// (1/2 of OCCE) Output compare x (x=5,6) clear enable + @"OCCE[0]": u1, + reserved10: u2, + /// (2/2 of OCFE) Output compare x (x=5,6) fast enable + @"OCFE[1]": u1, + /// (2/2 of OCPE) Output compare x (x=5,6) preload enable + @"OCPE[1]": u1, + /// (2/2 of OCM) Output compare x (x=5,6) mode + @"OCM[1]": OCM, + /// (2/2 of OCCE) Output compare x (x=5,6) clear enable + @"OCCE[1]": u1, + padding: u16, }), /// capture/compare register 5 CCR5: mmio.Mmio(packed struct(u32) { reserved29: u29, - /// Group channel 5 and channel x (x=1-3) - GC5C: GC5C, - padding: u2, + /// (1/3 of GC5C) Group channel 5 and channel x (x=1-3) + @"GC5C[0]": GC5C, + /// (2/3 of GC5C) Group channel 5 and channel x (x=1-3) + @"GC5C[1]": GC5C, + /// (3/3 of GC5C) Group channel 5 and channel x (x=1-3) + @"GC5C[2]": GC5C, }), /// capture/compare register 6 CCR6: mmio.Mmio(packed struct(u32) { @@ -424823,22 +439107,33 @@ pub const types = struct { AF2: mmio.Mmio(packed struct(u32) { /// TIMx_BKIN2 input enable BK2INE: u1, - /// TIM_BRK2_CMPx (x=1-8) enable - BK2CMPE: u1, + /// (1/1 of BK2CMPE) TIM_BRK2_CMPx (x=1-8) enable + @"BK2CMPE[0]": u1, reserved8: u6, /// BRK2 DFSDM1_BREAK1 enable BK2DF1BK1E: u1, /// TIMx_BK2IN input polarity BK2INP: BKINP, - /// TIM_BRK2_CMPx (x=1-4) input polarity - BK2CMPP: BKINP, - padding: u21, + /// (1/2 of BK2CMPP) TIM_BRK2_CMPx (x=1-4) input polarity + @"BK2CMPP[0]": BKINP, + /// (2/2 of BK2CMPP) TIM_BRK2_CMPx (x=1-4) input polarity + @"BK2CMPP[1]": BKINP, + padding: u20, }), /// input selection register TISEL: mmio.Mmio(packed struct(u32) { - /// Selects TIM_TIx (x=1-4) input - TISEL: u4, - padding: u28, + /// (1/4 of TISEL) Selects TIM_TIx (x=1-4) input + @"TISEL[0]": u4, + reserved8: u4, + /// (2/4 of TISEL) Selects TIM_TIx (x=1-4) input + @"TISEL[1]": u4, + reserved16: u4, + /// (3/4 of TISEL) Selects TIM_TIx (x=1-4) input + @"TISEL[2]": u4, + reserved24: u4, + /// (4/4 of TISEL) Selects TIM_TIx (x=1-4) input + @"TISEL[3]": u4, + padding: u4, }), }; @@ -424964,15 +439259,27 @@ pub const types = struct { /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/Compare x (x=1-4) interrupt enable - CCIE: u1, - reserved6: u4, + /// (1/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable + @"CCIE[0]": u1, + /// (2/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable + @"CCIE[1]": u1, + /// (3/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable + @"CCIE[2]": u1, + /// (4/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable + @"CCIE[3]": u1, + reserved6: u1, /// Trigger interrupt enable TIE: u1, reserved9: u2, - /// Capture/Compare x (x=1-4) DMA request enable - CCDE: u1, - reserved14: u4, + /// (1/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable + @"CCDE[0]": u1, + /// (2/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable + @"CCDE[1]": u1, + /// (3/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable + @"CCDE[2]": u1, + /// (4/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable + @"CCDE[3]": u1, + reserved14: u1, /// Trigger DMA request enable TDE: u1, padding: u17, @@ -424980,46 +439287,91 @@ pub const types = struct { /// status register SR: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/compare x (x=1-4) interrupt flag - CCIF: u1, - reserved6: u4, + /// (1/4 of CCIF) Capture/compare x (x=1-4) interrupt flag + @"CCIF[0]": u1, + /// (2/4 of CCIF) Capture/compare x (x=1-4) interrupt flag + @"CCIF[1]": u1, + /// (3/4 of CCIF) Capture/compare x (x=1-4) interrupt flag + @"CCIF[2]": u1, + /// (4/4 of CCIF) Capture/compare x (x=1-4) interrupt flag + @"CCIF[3]": u1, + reserved6: u1, /// Trigger interrupt flag TIF: u1, reserved9: u2, - /// Capture/Compare x (x=1-4) overcapture flag - CCOF: u1, - padding: u22, + /// (1/4 of CCOF) Capture/Compare x (x=1-4) overcapture flag + @"CCOF[0]": u1, + /// (2/4 of CCOF) Capture/Compare x (x=1-4) overcapture flag + @"CCOF[1]": u1, + /// (3/4 of CCOF) Capture/Compare x (x=1-4) overcapture flag + @"CCOF[2]": u1, + /// (4/4 of CCOF) Capture/Compare x (x=1-4) overcapture flag + @"CCOF[3]": u1, + padding: u19, }), /// event generation register EGR: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/compare x (x=1-4) generation - CCG: u1, - reserved6: u4, + /// (1/4 of CCG) Capture/compare x (x=1-4) generation + @"CCG[0]": u1, + /// (2/4 of CCG) Capture/compare x (x=1-4) generation + @"CCG[1]": u1, + /// (3/4 of CCG) Capture/compare x (x=1-4) generation + @"CCG[2]": u1, + /// (4/4 of CCG) Capture/compare x (x=1-4) generation + @"CCG[3]": u1, + reserved6: u1, /// Trigger generation TG: u1, padding: u25, }), /// capture/compare mode register 1-2 (input mode) CCMR_Input: [2]mmio.Mmio(packed struct(u32) { - /// Capture/Compare y selection - CCS: CCMR_Input_CCS, - /// Input capture y prescaler - ICPSC: u2, - /// Input capture y filter - ICF: FilterValue, - padding: u24, + /// (1/2 of CCS) Capture/Compare y selection + @"CCS[0]": CCMR_Input_CCS, + /// (1/2 of ICPSC) Input capture y prescaler + @"ICPSC[0]": u2, + /// (1/2 of ICF) Input capture y filter + @"ICF[0]": FilterValue, + /// (2/2 of CCS) Capture/Compare y selection + @"CCS[1]": CCMR_Input_CCS, + /// (2/2 of ICPSC) Input capture y prescaler + @"ICPSC[1]": u2, + /// (2/2 of ICF) Input capture y filter + @"ICF[1]": FilterValue, + padding: u16, }), /// capture/compare enable register CCER: mmio.Mmio(packed struct(u32) { - /// Capture/Compare x (x=1-4) output enable - CCE: u1, - /// Capture/Compare x (x=1-4) output Polarity - CCP: u1, + /// (1/4 of CCE) Capture/Compare x (x=1-4) output enable + @"CCE[0]": u1, + /// (1/4 of CCP) Capture/Compare x (x=1-4) output Polarity + @"CCP[0]": u1, reserved3: u1, - /// Capture/Compare x (x=1-4) output Polarity - CCNP: u1, - padding: u28, + /// (1/4 of CCNP) Capture/Compare x (x=1-4) output Polarity + @"CCNP[0]": u1, + /// (2/4 of CCE) Capture/Compare x (x=1-4) output enable + @"CCE[1]": u1, + /// (2/4 of CCP) Capture/Compare x (x=1-4) output Polarity + @"CCP[1]": u1, + reserved7: u1, + /// (2/4 of CCNP) Capture/Compare x (x=1-4) output Polarity + @"CCNP[1]": u1, + /// (3/4 of CCE) Capture/Compare x (x=1-4) output enable + @"CCE[2]": u1, + /// (3/4 of CCP) Capture/Compare x (x=1-4) output Polarity + @"CCP[2]": u1, + reserved11: u1, + /// (3/4 of CCNP) Capture/Compare x (x=1-4) output Polarity + @"CCNP[2]": u1, + /// (4/4 of CCE) Capture/Compare x (x=1-4) output enable + @"CCE[3]": u1, + /// (4/4 of CCP) Capture/Compare x (x=1-4) output Polarity + @"CCP[3]": u1, + reserved15: u1, + /// (4/4 of CCNP) Capture/Compare x (x=1-4) output Polarity + @"CCNP[3]": u1, + padding: u16, }), reserved52: [16]u8, /// capture/compare register x (x=1-4) @@ -425055,9 +439407,18 @@ pub const types = struct { reserved104: [4]u8, /// input selection register TISEL: mmio.Mmio(packed struct(u32) { - /// Selects TIM_TIx (x=1-4) input - TISEL: u4, - padding: u28, + /// (1/4 of TISEL) Selects TIM_TIx (x=1-4) input + @"TISEL[0]": u4, + reserved8: u4, + /// (2/4 of TISEL) Selects TIM_TIx (x=1-4) input + @"TISEL[1]": u4, + reserved16: u4, + /// (3/4 of TISEL) Selects TIM_TIx (x=1-4) input + @"TISEL[2]": u4, + reserved24: u4, + /// (4/4 of TISEL) Selects TIM_TIx (x=1-4) input + @"TISEL[3]": u4, + padding: u4, }), }; @@ -425511,47 +439872,47 @@ pub const types = struct { /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/Compare x (x=1) interrupt enable - CCIE: u1, + /// (1/1 of CCIE) Capture/Compare x (x=1) interrupt enable + @"CCIE[0]": u1, padding: u30, }), /// status register SR: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/compare x (x=1) interrupt flag - CCIF: u1, + /// (1/1 of CCIF) Capture/compare x (x=1) interrupt flag + @"CCIF[0]": u1, reserved9: u7, - /// Capture/Compare x (x=1) overcapture flag - CCOF: u1, + /// (1/1 of CCOF) Capture/Compare x (x=1) overcapture flag + @"CCOF[0]": u1, padding: u22, }), /// event generation register EGR: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/compare x (x=1) generation - CCG: u1, + /// (1/1 of CCG) Capture/compare x (x=1) generation + @"CCG[0]": u1, padding: u30, }), /// capture/compare mode register 1 (input mode) CCMR_Input: [1]mmio.Mmio(packed struct(u32) { - /// Capture/Compare y selection - CCS: CCMR_Input_CCS, - /// Input capture y prescaler - ICPSC: u2, - /// Input capture y filter - ICF: FilterValue, + /// (1/1 of CCS) Capture/Compare y selection + @"CCS[0]": CCMR_Input_CCS, + /// (1/1 of ICPSC) Input capture y prescaler + @"ICPSC[0]": u2, + /// (1/1 of ICF) Input capture y filter + @"ICF[0]": FilterValue, padding: u24, }), reserved32: [4]u8, /// capture/compare enable register CCER: mmio.Mmio(packed struct(u32) { - /// Capture/Compare x (x=1) output enable - CCE: u1, - /// Capture/Compare x (x=1) output Polarity - CCP: u1, + /// (1/1 of CCE) Capture/Compare x (x=1) output enable + @"CCE[0]": u1, + /// (1/1 of CCP) Capture/Compare x (x=1) output Polarity + @"CCP[0]": u1, reserved3: u1, - /// Capture/Compare x (x=1) output Polarity - CCNP: u1, + /// (1/1 of CCNP) Capture/Compare x (x=1) output Polarity + @"CCNP[0]": u1, padding: u28, }), reserved52: [16]u8, @@ -425564,8 +439925,8 @@ pub const types = struct { reserved92: [36]u8, /// input selection register TISEL: mmio.Mmio(packed struct(u32) { - /// Selects TIM_TIx (x=1) input - TISEL: u4, + /// (1/1 of TISEL) Selects TIM_TIx (x=1) input + @"TISEL[0]": u4, padding: u28, }), reserved104: [8]u8, @@ -425586,10 +439947,10 @@ pub const types = struct { /// Capture/compare DMA selection CCDS: CCDS, reserved8: u4, - /// Output Idle state x (x=1) - OIS: u1, - /// Output Idle state x (x=1) - OISN: u1, + /// (1/1 of OIS) Output Idle state x (x=1) + @"OIS[0]": u1, + /// (1/1 of OISN) Output Idle state x (x=1) + @"OISN[0]": u1, padding: u22, }), reserved12: [4]u8, @@ -425603,8 +439964,8 @@ pub const types = struct { BIE: u1, /// Update DMA request enable UDE: u1, - /// Capture/Compare x (x=1) DMA request enable - CCDE: u1, + /// (1/1 of CCDE) Capture/Compare x (x=1) DMA request enable + @"CCDE[0]": u1, padding: u22, }), /// status register @@ -425613,8 +439974,8 @@ pub const types = struct { /// COM interrupt flag COMIF: u1, reserved7: u1, - /// Break x (x=1) interrupt flag - BIF: u1, + /// (1/1 of BIF) Break x (x=1) interrupt flag + @"BIF[0]": u1, padding: u24, }), /// event generation register @@ -425623,16 +439984,16 @@ pub const types = struct { /// Capture/Compare control update generation COMG: u1, reserved7: u1, - /// Break x (x=1) generation - BG: u1, + /// (1/1 of BG) Break x (x=1) generation + @"BG[0]": u1, padding: u24, }), reserved32: [8]u8, /// capture/compare enable register CCER: mmio.Mmio(packed struct(u32) { reserved2: u2, - /// Capture/Compare x (x=1) complementary output enable - CCNE: u1, + /// (1/1 of CCNE) Capture/Compare x (x=1) complementary output enable + @"CCNE[0]": u1, padding: u29, }), reserved48: [12]u8, @@ -425653,22 +440014,22 @@ pub const types = struct { OSSI: OSSI, /// Off-state selection for Run mode OSSR: OSSR, - /// Break x (x=1) enable - BKE: u1, - /// Break x (x=1) polarity - BKP: BKP, + /// (1/1 of BKE) Break x (x=1) enable + @"BKE[0]": u1, + /// (1/1 of BKP) Break x (x=1) polarity + @"BKP[0]": BKP, /// Automatic output enable AOE: u1, /// Main output enable MOE: u1, - /// Break x (x=1) filter - BKF: FilterValue, + /// (1/1 of BKF) Break x (x=1) filter + @"BKF[0]": FilterValue, reserved26: u6, - /// Break x (x=1) Disarm - BKDSRM: BKDSRM, + /// (1/1 of BKDSRM) Break x (x=1) Disarm + @"BKDSRM[0]": BKDSRM, reserved28: u1, - /// Break x (x=1) bidirectional - BKBID: BKBID, + /// (1/1 of BKBID) Break x (x=1) bidirectional + @"BKBID[0]": BKBID, padding: u3, }), reserved84: [12]u8, @@ -425688,14 +440049,33 @@ pub const types = struct { AF1: mmio.Mmio(packed struct(u32) { /// TIMx_BKIN input enable BKINE: u1, - /// TIM_BRK_CMPx (x=1-8) enable - BKCMPE: u1, - reserved9: u7, + /// (1/8 of BKCMPE) TIM_BRK_CMPx (x=1-8) enable + @"BKCMPE[0]": u1, + /// (2/8 of BKCMPE) TIM_BRK_CMPx (x=1-8) enable + @"BKCMPE[1]": u1, + /// (3/8 of BKCMPE) TIM_BRK_CMPx (x=1-8) enable + @"BKCMPE[2]": u1, + /// (4/8 of BKCMPE) TIM_BRK_CMPx (x=1-8) enable + @"BKCMPE[3]": u1, + /// (5/8 of BKCMPE) TIM_BRK_CMPx (x=1-8) enable + @"BKCMPE[4]": u1, + /// (6/8 of BKCMPE) TIM_BRK_CMPx (x=1-8) enable + @"BKCMPE[5]": u1, + /// (7/8 of BKCMPE) TIM_BRK_CMPx (x=1-8) enable + @"BKCMPE[6]": u1, + /// (8/8 of BKCMPE) TIM_BRK_CMPx (x=1-8) enable + @"BKCMPE[7]": u1, /// TIMx_BKIN input polarity BKINP: BKINP, - /// TIM_BRK_CMPx (x=1-4) input polarity - BKCMPP: BKINP, - padding: u21, + /// (1/4 of BKCMPP) TIM_BRK_CMPx (x=1-4) input polarity + @"BKCMPP[0]": BKINP, + /// (2/4 of BKCMPP) TIM_BRK_CMPx (x=1-4) input polarity + @"BKCMPP[1]": BKINP, + /// (3/4 of BKCMPP) TIM_BRK_CMPx (x=1-4) input polarity + @"BKCMPP[2]": BKINP, + /// (4/4 of BKCMPP) TIM_BRK_CMPx (x=1-4) input polarity + @"BKCMPP[3]": BKINP, + padding: u18, }), /// alternate function register 2 AF2: mmio.Mmio(packed struct(u32) { @@ -425731,9 +440111,11 @@ pub const types = struct { /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/Compare x (x=1-2) interrupt enable - CCIE: u1, - reserved6: u4, + /// (1/2 of CCIE) Capture/Compare x (x=1-2) interrupt enable + @"CCIE[0]": u1, + /// (2/2 of CCIE) Capture/Compare x (x=1-2) interrupt enable + @"CCIE[1]": u1, + reserved6: u3, /// Trigger interrupt enable TIE: u1, padding: u25, @@ -425741,47 +440123,66 @@ pub const types = struct { /// status register SR: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/compare x (x=1-2) interrupt flag - CCIF: u1, - reserved6: u4, + /// (1/2 of CCIF) Capture/compare x (x=1-2) interrupt flag + @"CCIF[0]": u1, + /// (2/2 of CCIF) Capture/compare x (x=1-2) interrupt flag + @"CCIF[1]": u1, + reserved6: u3, /// Trigger interrupt flag TIF: u1, reserved9: u2, - /// Capture/Compare x (x=1-2) overcapture flag - CCOF: u1, - padding: u22, + /// (1/2 of CCOF) Capture/Compare x (x=1-2) overcapture flag + @"CCOF[0]": u1, + /// (2/2 of CCOF) Capture/Compare x (x=1-2) overcapture flag + @"CCOF[1]": u1, + padding: u21, }), /// event generation register EGR: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/compare x (x=1-2) generation - CCG: u1, - reserved6: u4, + /// (1/2 of CCG) Capture/compare x (x=1-2) generation + @"CCG[0]": u1, + /// (2/2 of CCG) Capture/compare x (x=1-2) generation + @"CCG[1]": u1, + reserved6: u3, /// Trigger generation TG: u1, padding: u25, }), /// capture/compare mode register 1 (input mode) CCMR_Input: [1]mmio.Mmio(packed struct(u32) { - /// Capture/Compare y selection - CCS: CCMR_Input_CCS, - /// Input capture y prescaler - ICPSC: u2, - /// Input capture y filter - ICF: FilterValue, - padding: u24, + /// (1/2 of CCS) Capture/Compare y selection + @"CCS[0]": CCMR_Input_CCS, + /// (1/2 of ICPSC) Input capture y prescaler + @"ICPSC[0]": u2, + /// (1/2 of ICF) Input capture y filter + @"ICF[0]": FilterValue, + /// (2/2 of CCS) Capture/Compare y selection + @"CCS[1]": CCMR_Input_CCS, + /// (2/2 of ICPSC) Input capture y prescaler + @"ICPSC[1]": u2, + /// (2/2 of ICF) Input capture y filter + @"ICF[1]": FilterValue, + padding: u16, }), reserved32: [4]u8, /// capture/compare enable register CCER: mmio.Mmio(packed struct(u32) { - /// Capture/Compare x (x=1-2) output enable - CCE: u1, - /// Capture/Compare x (x=1-2) output Polarity - CCP: u1, + /// (1/2 of CCE) Capture/Compare x (x=1-2) output enable + @"CCE[0]": u1, + /// (1/2 of CCP) Capture/Compare x (x=1-2) output Polarity + @"CCP[0]": u1, reserved3: u1, - /// Capture/Compare x (x=1-2) output Polarity - CCNP: u1, - padding: u28, + /// (1/2 of CCNP) Capture/Compare x (x=1-2) output Polarity + @"CCNP[0]": u1, + /// (2/2 of CCE) Capture/Compare x (x=1-2) output enable + @"CCE[1]": u1, + /// (2/2 of CCP) Capture/Compare x (x=1-2) output Polarity + @"CCP[1]": u1, + reserved7: u1, + /// (2/2 of CCNP) Capture/Compare x (x=1-2) output Polarity + @"CCNP[1]": u1, + padding: u24, }), reserved52: [16]u8, /// capture/compare register x (x=1-2) (Dither mode disabled) @@ -425793,9 +440194,12 @@ pub const types = struct { reserved92: [32]u8, /// input selection register TISEL: mmio.Mmio(packed struct(u32) { - /// Selects TIM_TIx (x=1-2) input - TISEL: u4, - padding: u28, + /// (1/2 of TISEL) Selects TIM_TIx (x=1-2) input + @"TISEL[0]": u4, + reserved8: u4, + /// (2/2 of TISEL) Selects TIM_TIx (x=1-2) input + @"TISEL[1]": u4, + padding: u20, }), }; @@ -425826,41 +440230,47 @@ pub const types = struct { /// status register SR: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/compare x (x=1,2) interrupt flag - CCIF: u1, - reserved6: u4, + /// (1/2 of CCIF) Capture/compare x (x=1,2) interrupt flag + @"CCIF[0]": u1, + /// (2/2 of CCIF) Capture/compare x (x=1,2) interrupt flag + @"CCIF[1]": u1, + reserved6: u3, /// Trigger interrupt flag TIF: u1, reserved9: u2, - /// Capture/Compare x (x=1,2) overcapture flag - CCOF: u1, - padding: u22, + /// (1/2 of CCOF) Capture/Compare x (x=1,2) overcapture flag + @"CCOF[0]": u1, + /// (2/2 of CCOF) Capture/Compare x (x=1,2) overcapture flag + @"CCOF[1]": u1, + padding: u21, }), /// event generation register EGR: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/compare x (x=1,2) generation - CCG: u1, - reserved6: u4, + /// (1/2 of CCG) Capture/compare x (x=1,2) generation + @"CCG[0]": u1, + /// (2/2 of CCG) Capture/compare x (x=1,2) generation + @"CCG[1]": u1, + reserved6: u3, /// Trigger generation TG: u1, padding: u25, }), /// capture/compare mode register 1 (input mode) CCMR_Input: [2]mmio.Mmio(packed struct(u32) { - /// Capture/Compare y selection - CCS: CCMR_Input_CCS, - /// Input capture y prescaler - ICPSC: u2, - /// Input capture y filter - ICF: FilterValue, + /// (1/1 of CCS) Capture/Compare y selection + @"CCS[0]": CCMR_Input_CCS, + /// (1/1 of ICPSC) Input capture y prescaler + @"ICPSC[0]": u2, + /// (1/1 of ICF) Input capture y filter + @"ICF[0]": FilterValue, padding: u24, }), /// capture/compare enable register CCER: mmio.Mmio(packed struct(u32) { reserved2: u2, - /// Capture/Compare x (x=1) complementary output enable - CCNE: u1, + /// (1/1 of CCNE) Capture/Compare x (x=1) complementary output enable + @"CCNE[0]": u1, padding: u29, }), reserved52: [16]u8, @@ -425881,30 +440291,33 @@ pub const types = struct { OSSI: OSSI, /// Off-state selection for Run mode OSSR: OSSR, - /// Break x (x=1) enable - BKE: u1, - /// Break x (x=1) polarity - BKP: BKP, + /// (1/1 of BKE) Break x (x=1) enable + @"BKE[0]": u1, + /// (1/1 of BKP) Break x (x=1) polarity + @"BKP[0]": BKP, /// Automatic output enable AOE: u1, /// Main output enable MOE: u1, - /// Break x (x=1) filter - BKF: FilterValue, + /// (1/1 of BKF) Break x (x=1) filter + @"BKF[0]": FilterValue, reserved26: u6, - /// Break x (x=1) Disarm - BKDSRM: BKDSRM, + /// (1/1 of BKDSRM) Break x (x=1) Disarm + @"BKDSRM[0]": BKDSRM, reserved28: u1, - /// Break x (x=1) bidirectional - BKBID: BKBID, + /// (1/1 of BKBID) Break x (x=1) bidirectional + @"BKBID[0]": BKBID, padding: u3, }), reserved92: [20]u8, /// input selection register TISEL: mmio.Mmio(packed struct(u32) { - /// Selects TIM_TIx (x=1-2) input - TISEL: u4, - padding: u28, + /// (1/2 of TISEL) Selects TIM_TIx (x=1-2) input + @"TISEL[0]": u4, + reserved8: u4, + /// (2/2 of TISEL) Selects TIM_TIx (x=1-2) input + @"TISEL[1]": u4, + padding: u20, }), }; @@ -425925,11 +440338,28 @@ pub const types = struct { /// control register 2 CR2: mmio.Mmio(packed struct(u32) { reserved8: u8, - /// Output Idle state x (x=1-6) - OIS: u1, - /// Output Idle state x N x (x=1-4) - OISN: u1, - reserved20: u10, + /// (1/6 of OIS) Output Idle state x (x=1-6) + @"OIS[0]": u1, + /// (1/4 of OISN) Output Idle state x N x (x=1-4) + @"OISN[0]": u1, + /// (2/6 of OIS) Output Idle state x (x=1-6) + @"OIS[1]": u1, + /// (2/4 of OISN) Output Idle state x N x (x=1-4) + @"OISN[1]": u1, + /// (3/6 of OIS) Output Idle state x (x=1-6) + @"OIS[2]": u1, + /// (3/4 of OISN) Output Idle state x N x (x=1-4) + @"OISN[2]": u1, + /// (4/6 of OIS) Output Idle state x (x=1-6) + @"OIS[3]": u1, + /// (4/4 of OISN) Output Idle state x N x (x=1-4) + @"OISN[3]": u1, + /// (5/6 of OIS) Output Idle state x (x=1-6) + @"OIS[4]": u1, + reserved18: u1, + /// (6/6 of OIS) Output Idle state x (x=1-6) + @"OIS[5]": u1, + reserved20: u1, /// Master mode selection 2 MMS2: MMS2, padding: u8, @@ -425956,15 +440386,27 @@ pub const types = struct { /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/Compare x (x=1-4) interrupt enable - CCIE: u1, - reserved7: u5, + /// (1/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable + @"CCIE[0]": u1, + /// (2/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable + @"CCIE[1]": u1, + /// (3/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable + @"CCIE[2]": u1, + /// (4/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable + @"CCIE[3]": u1, + reserved7: u2, /// Break interrupt enable BIE: u1, reserved9: u1, - /// Capture/Compare x (x=1) DMA request enable - CCDE: u1, - reserved20: u10, + /// (1/4 of CCDE) Capture/Compare x (x=1) DMA request enable + @"CCDE[0]": u1, + /// (2/4 of CCDE) Capture/Compare x (x=1) DMA request enable + @"CCDE[1]": u1, + /// (3/4 of CCDE) Capture/Compare x (x=1) DMA request enable + @"CCDE[2]": u1, + /// (4/4 of CCDE) Capture/Compare x (x=1) DMA request enable + @"CCDE[3]": u1, + reserved20: u7, /// Index interrupt enable IDXIE: u1, /// Direction change interrupt enable @@ -425978,15 +440420,27 @@ pub const types = struct { /// status register SR: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/compare x (x=1-4) interrupt flag - CCIF: u1, - reserved7: u5, - /// Break x (x=1,2) interrupt flag - BIF: u1, - reserved9: u1, - /// Capture/Compare x (x=1-4) overcapture flag - CCOF: u1, - reserved13: u3, + /// (1/4 of CCIF) Capture/compare x (x=1-4) interrupt flag + @"CCIF[0]": u1, + /// (2/4 of CCIF) Capture/compare x (x=1-4) interrupt flag + @"CCIF[1]": u1, + /// (3/4 of CCIF) Capture/compare x (x=1-4) interrupt flag + @"CCIF[2]": u1, + /// (4/4 of CCIF) Capture/compare x (x=1-4) interrupt flag + @"CCIF[3]": u1, + reserved7: u2, + /// (1/2 of BIF) Break x (x=1,2) interrupt flag + @"BIF[0]": u1, + /// (2/2 of BIF) Break x (x=1,2) interrupt flag + @"BIF[1]": u1, + /// (1/4 of CCOF) Capture/Compare x (x=1-4) overcapture flag + @"CCOF[0]": u1, + /// (2/4 of CCOF) Capture/Compare x (x=1-4) overcapture flag + @"CCOF[1]": u1, + /// (3/4 of CCOF) Capture/Compare x (x=1-4) overcapture flag + @"CCOF[2]": u1, + /// (4/4 of CCOF) Capture/Compare x (x=1-4) overcapture flag + @"CCOF[3]": u1, /// System break interrupt flag SBIF: u1, reserved16: u2, @@ -426008,34 +440462,81 @@ pub const types = struct { /// event generation register EGR: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/compare x (x=1-4) generation - CCG: u1, - reserved7: u5, - /// Break x (x=1-2) generation - BG: u1, - padding: u24, + /// (1/4 of CCG) Capture/compare x (x=1-4) generation + @"CCG[0]": u1, + /// (2/4 of CCG) Capture/compare x (x=1-4) generation + @"CCG[1]": u1, + /// (3/4 of CCG) Capture/compare x (x=1-4) generation + @"CCG[2]": u1, + /// (4/4 of CCG) Capture/compare x (x=1-4) generation + @"CCG[3]": u1, + reserved7: u2, + /// (1/2 of BG) Break x (x=1-2) generation + @"BG[0]": u1, + /// (2/2 of BG) Break x (x=1-2) generation + @"BG[1]": u1, + padding: u23, }), /// capture/compare mode register 1-2 (input mode) CCMR_Input: [2]mmio.Mmio(packed struct(u32) { - /// Capture/Compare y selection - CCS: CCMR_Input_CCS, - /// Input capture y prescaler - ICPSC: u2, - /// Input capture y filter - ICF: FilterValue, - padding: u24, + /// (1/2 of CCS) Capture/Compare y selection + @"CCS[0]": CCMR_Input_CCS, + /// (1/2 of ICPSC) Input capture y prescaler + @"ICPSC[0]": u2, + /// (1/2 of ICF) Input capture y filter + @"ICF[0]": FilterValue, + /// (2/2 of CCS) Capture/Compare y selection + @"CCS[1]": CCMR_Input_CCS, + /// (2/2 of ICPSC) Input capture y prescaler + @"ICPSC[1]": u2, + /// (2/2 of ICF) Input capture y filter + @"ICF[1]": FilterValue, + padding: u16, }), /// capture/compare enable register CCER: mmio.Mmio(packed struct(u32) { - /// Capture/Compare x (x=1-6) output enable - CCE: u1, - /// Capture/Compare x (x=1-6) output Polarity - CCP: u1, - /// Capture/Compare x (x=1-4) complementary output enable - CCNE: u1, - /// Capture/Compare x (x=1-4) output Polarity - CCNP: u1, - padding: u28, + /// (1/6 of CCE) Capture/Compare x (x=1-6) output enable + @"CCE[0]": u1, + /// (1/6 of CCP) Capture/Compare x (x=1-6) output Polarity + @"CCP[0]": u1, + /// (1/4 of CCNE) Capture/Compare x (x=1-4) complementary output enable + @"CCNE[0]": u1, + /// (1/4 of CCNP) Capture/Compare x (x=1-4) output Polarity + @"CCNP[0]": u1, + /// (2/6 of CCE) Capture/Compare x (x=1-6) output enable + @"CCE[1]": u1, + /// (2/6 of CCP) Capture/Compare x (x=1-6) output Polarity + @"CCP[1]": u1, + /// (2/4 of CCNE) Capture/Compare x (x=1-4) complementary output enable + @"CCNE[1]": u1, + /// (2/4 of CCNP) Capture/Compare x (x=1-4) output Polarity + @"CCNP[1]": u1, + /// (3/6 of CCE) Capture/Compare x (x=1-6) output enable + @"CCE[2]": u1, + /// (3/6 of CCP) Capture/Compare x (x=1-6) output Polarity + @"CCP[2]": u1, + /// (3/4 of CCNE) Capture/Compare x (x=1-4) complementary output enable + @"CCNE[2]": u1, + /// (3/4 of CCNP) Capture/Compare x (x=1-4) output Polarity + @"CCNP[2]": u1, + /// (4/6 of CCE) Capture/Compare x (x=1-6) output enable + @"CCE[3]": u1, + /// (4/6 of CCP) Capture/Compare x (x=1-6) output Polarity + @"CCP[3]": u1, + /// (4/4 of CCNE) Capture/Compare x (x=1-4) complementary output enable + @"CCNE[3]": u1, + /// (4/4 of CCNP) Capture/Compare x (x=1-4) output Polarity + @"CCNP[3]": u1, + /// (5/6 of CCE) Capture/Compare x (x=1-6) output enable + @"CCE[4]": u1, + /// (5/6 of CCP) Capture/Compare x (x=1-6) output Polarity + @"CCP[4]": u1, + reserved20: u2, + /// (6/6 of CCE) Capture/Compare x (x=1-6) output enable + @"CCE[5]": u1, + /// (6/6 of CCP) Capture/Compare x (x=1-6) output Polarity + @"CCP[5]": u1, + padding: u10, }), reserved48: [12]u8, /// repetition counter register @@ -426053,27 +440554,38 @@ pub const types = struct { /// break and dead-time register BDTR: mmio.Mmio(packed struct(u32) { reserved12: u12, - /// Break x (x=1,2) enable - BKE: u1, - /// Break x (x=1,2) polarity - BKP: BKP, + /// (1/2 of BKE) Break x (x=1,2) enable + @"BKE[0]": u1, + /// (1/2 of BKP) Break x (x=1,2) polarity + @"BKP[0]": BKP, reserved16: u2, - /// Break x (x=1,2) filter - BKF: FilterValue, - reserved26: u6, - /// Break x (x=1,2) Disarm - BKDSRM: BKDSRM, - reserved28: u1, - /// Break x (x=1,2) bidirectional - BKBID: BKBID, - padding: u3, + /// (1/2 of BKF) Break x (x=1,2) filter + @"BKF[0]": FilterValue, + /// (2/2 of BKF) Break x (x=1,2) filter + @"BKF[1]": FilterValue, + /// (2/2 of BKE) Break x (x=1,2) enable + @"BKE[1]": u1, + /// (2/2 of BKP) Break x (x=1,2) polarity + @"BKP[1]": BKP, + /// (1/2 of BKDSRM) Break x (x=1,2) Disarm + @"BKDSRM[0]": BKDSRM, + /// (2/2 of BKDSRM) Break x (x=1,2) Disarm + @"BKDSRM[1]": BKDSRM, + /// (1/2 of BKBID) Break x (x=1,2) bidirectional + @"BKBID[0]": BKBID, + /// (2/2 of BKBID) Break x (x=1,2) bidirectional + @"BKBID[1]": BKBID, + padding: u2, }), /// capture/compare register 5 (Dither mode disabled) CCR5: mmio.Mmio(packed struct(u32) { reserved29: u29, - /// Group channel 5 and channel x (x=1-3) - GC5C: GC5C, - padding: u2, + /// (1/3 of GC5C) Group channel 5 and channel x (x=1-3) + @"GC5C[0]": GC5C, + /// (2/3 of GC5C) Group channel 5 and channel x (x=1-3) + @"GC5C[1]": GC5C, + /// (3/3 of GC5C) Group channel 5 and channel x (x=1-3) + @"GC5C[2]": GC5C, }), /// capture/compare register 6 (Dither mode disabled) CCR6: mmio.Mmio(packed struct(u32) { @@ -426084,11 +440596,16 @@ pub const types = struct { /// capture/compare mode register 3 CCMR3: mmio.Mmio(packed struct(u32) { reserved2: u2, - /// Output compare x (x=5,6) fast enable - OCFE: u1, - /// Output compare x (x=5,6) preload enable - OCPE: u1, - padding: u28, + /// (1/2 of OCFE) Output compare x (x=5,6) fast enable + @"OCFE[0]": u1, + /// (1/2 of OCPE) Output compare x (x=5,6) preload enable + @"OCPE[0]": u1, + reserved10: u6, + /// (2/2 of OCFE) Output compare x (x=5,6) fast enable + @"OCFE[1]": u1, + /// (2/2 of OCPE) Output compare x (x=5,6) preload enable + @"OCPE[1]": u1, + padding: u20, }), reserved88: [4]u8, /// encoder control register @@ -426112,9 +440629,18 @@ pub const types = struct { }), /// input selection register TISEL: mmio.Mmio(packed struct(u32) { - /// Selects TIM_TIx (x=1-4) input - TISEL: u4, - padding: u28, + /// (1/4 of TISEL) Selects TIM_TIx (x=1-4) input + @"TISEL[0]": u4, + reserved8: u4, + /// (2/4 of TISEL) Selects TIM_TIx (x=1-4) input + @"TISEL[1]": u4, + reserved16: u4, + /// (3/4 of TISEL) Selects TIM_TIx (x=1-4) input + @"TISEL[2]": u4, + reserved24: u4, + /// (4/4 of TISEL) Selects TIM_TIx (x=1-4) input + @"TISEL[3]": u4, + padding: u4, }), /// alternate function register 1 AF1: mmio.Mmio(packed struct(u32) { @@ -426127,14 +440653,33 @@ pub const types = struct { AF2: mmio.Mmio(packed struct(u32) { /// TIMx_BKIN2 input enable BK2INE: u1, - /// TIM_BRK2_CMPx (x=1-8) enable - BK2CMPE: u1, - reserved9: u7, + /// (1/8 of BK2CMPE) TIM_BRK2_CMPx (x=1-8) enable + @"BK2CMPE[0]": u1, + /// (2/8 of BK2CMPE) TIM_BRK2_CMPx (x=1-8) enable + @"BK2CMPE[1]": u1, + /// (3/8 of BK2CMPE) TIM_BRK2_CMPx (x=1-8) enable + @"BK2CMPE[2]": u1, + /// (4/8 of BK2CMPE) TIM_BRK2_CMPx (x=1-8) enable + @"BK2CMPE[3]": u1, + /// (5/8 of BK2CMPE) TIM_BRK2_CMPx (x=1-8) enable + @"BK2CMPE[4]": u1, + /// (6/8 of BK2CMPE) TIM_BRK2_CMPx (x=1-8) enable + @"BK2CMPE[5]": u1, + /// (7/8 of BK2CMPE) TIM_BRK2_CMPx (x=1-8) enable + @"BK2CMPE[6]": u1, + /// (8/8 of BK2CMPE) TIM_BRK2_CMPx (x=1-8) enable + @"BK2CMPE[7]": u1, /// TIMx_BK2IN input polarity BK2INP: BKINP, - /// TIM_BRK2_CMPx (x=1-4) input polarity - BK2CMPP: BKINP, - padding: u21, + /// (1/4 of BK2CMPP) TIM_BRK2_CMPx (x=1-4) input polarity + @"BK2CMPP[0]": BKINP, + /// (2/4 of BK2CMPP) TIM_BRK2_CMPx (x=1-4) input polarity + @"BK2CMPP[1]": BKINP, + /// (3/4 of BK2CMPP) TIM_BRK2_CMPx (x=1-4) input polarity + @"BK2CMPP[2]": BKINP, + /// (4/4 of BK2CMPP) TIM_BRK2_CMPx (x=1-4) input polarity + @"BK2CMPP[3]": BKINP, + padding: u18, }), }; @@ -426262,15 +440807,27 @@ pub const types = struct { /// DMA/Interrupt enable register DIER: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/Compare x (x=1-4) interrupt enable - CCIE: u1, - reserved6: u4, + /// (1/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable + @"CCIE[0]": u1, + /// (2/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable + @"CCIE[1]": u1, + /// (3/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable + @"CCIE[2]": u1, + /// (4/4 of CCIE) Capture/Compare x (x=1-4) interrupt enable + @"CCIE[3]": u1, + reserved6: u1, /// Trigger interrupt enable TIE: u1, reserved9: u2, - /// Capture/Compare x (x=1-4) DMA request enable - CCDE: u1, - reserved14: u4, + /// (1/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable + @"CCDE[0]": u1, + /// (2/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable + @"CCDE[1]": u1, + /// (3/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable + @"CCDE[2]": u1, + /// (4/4 of CCDE) Capture/Compare x (x=1-4) DMA request enable + @"CCDE[3]": u1, + reserved14: u1, /// Trigger DMA request enable TDE: u1, reserved20: u5, @@ -426287,15 +440844,27 @@ pub const types = struct { /// status register SR: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/compare x (x=1-4) interrupt flag - CCIF: u1, - reserved6: u4, + /// (1/4 of CCIF) Capture/compare x (x=1-4) interrupt flag + @"CCIF[0]": u1, + /// (2/4 of CCIF) Capture/compare x (x=1-4) interrupt flag + @"CCIF[1]": u1, + /// (3/4 of CCIF) Capture/compare x (x=1-4) interrupt flag + @"CCIF[2]": u1, + /// (4/4 of CCIF) Capture/compare x (x=1-4) interrupt flag + @"CCIF[3]": u1, + reserved6: u1, /// Trigger interrupt flag TIF: u1, reserved9: u2, - /// Capture/Compare x (x=1-4) overcapture flag - CCOF: u1, - reserved20: u10, + /// (1/4 of CCOF) Capture/Compare x (x=1-4) overcapture flag + @"CCOF[0]": u1, + /// (2/4 of CCOF) Capture/Compare x (x=1-4) overcapture flag + @"CCOF[1]": u1, + /// (3/4 of CCOF) Capture/Compare x (x=1-4) overcapture flag + @"CCOF[2]": u1, + /// (4/4 of CCOF) Capture/Compare x (x=1-4) overcapture flag + @"CCOF[3]": u1, + reserved20: u7, /// Index interrupt flag IDXIF: u1, /// Direction change interrupt flag @@ -426309,33 +440878,66 @@ pub const types = struct { /// event generation register EGR: mmio.Mmio(packed struct(u32) { reserved1: u1, - /// Capture/compare x (x=1-4) generation - CCG: u1, - reserved6: u4, + /// (1/4 of CCG) Capture/compare x (x=1-4) generation + @"CCG[0]": u1, + /// (2/4 of CCG) Capture/compare x (x=1-4) generation + @"CCG[1]": u1, + /// (3/4 of CCG) Capture/compare x (x=1-4) generation + @"CCG[2]": u1, + /// (4/4 of CCG) Capture/compare x (x=1-4) generation + @"CCG[3]": u1, + reserved6: u1, /// Trigger generation TG: u1, padding: u25, }), /// capture/compare mode register 1-2 (input mode) CCMR_Input: [2]mmio.Mmio(packed struct(u32) { - /// Capture/Compare y selection - CCS: CCMR_Input_CCS, - /// Input capture y prescaler - ICPSC: u2, - /// Input capture y filter - ICF: FilterValue, - padding: u24, + /// (1/2 of CCS) Capture/Compare y selection + @"CCS[0]": CCMR_Input_CCS, + /// (1/2 of ICPSC) Input capture y prescaler + @"ICPSC[0]": u2, + /// (1/2 of ICF) Input capture y filter + @"ICF[0]": FilterValue, + /// (2/2 of CCS) Capture/Compare y selection + @"CCS[1]": CCMR_Input_CCS, + /// (2/2 of ICPSC) Input capture y prescaler + @"ICPSC[1]": u2, + /// (2/2 of ICF) Input capture y filter + @"ICF[1]": FilterValue, + padding: u16, }), /// capture/compare enable register CCER: mmio.Mmio(packed struct(u32) { - /// Capture/Compare x (x=1-4) output enable - CCE: u1, - /// Capture/Compare x (x=1-4) output Polarity - CCP: u1, + /// (1/4 of CCE) Capture/Compare x (x=1-4) output enable + @"CCE[0]": u1, + /// (1/4 of CCP) Capture/Compare x (x=1-4) output Polarity + @"CCP[0]": u1, reserved3: u1, - /// Capture/Compare x (x=1-4) output Polarity - CCNP: u1, - padding: u28, + /// (1/4 of CCNP) Capture/Compare x (x=1-4) output Polarity + @"CCNP[0]": u1, + /// (2/4 of CCE) Capture/Compare x (x=1-4) output enable + @"CCE[1]": u1, + /// (2/4 of CCP) Capture/Compare x (x=1-4) output Polarity + @"CCP[1]": u1, + reserved7: u1, + /// (2/4 of CCNP) Capture/Compare x (x=1-4) output Polarity + @"CCNP[1]": u1, + /// (3/4 of CCE) Capture/Compare x (x=1-4) output enable + @"CCE[2]": u1, + /// (3/4 of CCP) Capture/Compare x (x=1-4) output Polarity + @"CCP[2]": u1, + reserved11: u1, + /// (3/4 of CCNP) Capture/Compare x (x=1-4) output Polarity + @"CCNP[2]": u1, + /// (4/4 of CCE) Capture/Compare x (x=1-4) output enable + @"CCE[3]": u1, + /// (4/4 of CCP) Capture/Compare x (x=1-4) output Polarity + @"CCP[3]": u1, + reserved15: u1, + /// (4/4 of CCNP) Capture/Compare x (x=1-4) output Polarity + @"CCNP[3]": u1, + padding: u16, }), reserved52: [16]u8, /// capture/compare register x (x=1-4) (Dither mode disabled) @@ -426366,9 +440968,18 @@ pub const types = struct { }), /// input selection register TISEL: mmio.Mmio(packed struct(u32) { - /// Selects TIM_TIx (x=1-4) input - TISEL: u4, - padding: u28, + /// (1/4 of TISEL) Selects TIM_TIx (x=1-4) input + @"TISEL[0]": u4, + reserved8: u4, + /// (2/4 of TISEL) Selects TIM_TIx (x=1-4) input + @"TISEL[1]": u4, + reserved16: u4, + /// (3/4 of TISEL) Selects TIM_TIx (x=1-4) input + @"TISEL[2]": u4, + reserved24: u4, + /// (4/4 of TISEL) Selects TIM_TIx (x=1-4) input + @"TISEL[3]": u4, + padding: u4, }), /// alternate function register 1 AF1: mmio.Mmio(packed struct(u32) { diff --git a/port/stmicro/stm32/src/generate.zig b/port/stmicro/stm32/src/generate.zig index 67cca90f..62b036cb 100644 --- a/port/stmicro/stm32/src/generate.zig +++ b/port/stmicro/stm32/src/generate.zig @@ -310,7 +310,7 @@ pub fn main() !void { // it's in bytes const stride = array.object.get("stride").?.integer; if (stride != 4) { - std.log.warn("found stride: {} for {s} in {s} in {s}", .{ stride, register_name, key["block/".len..], name }); + std.log.warn("ignoring register array with unsupported stride: {} != 4 for register {s} in {s} in {s}", .{ stride, register_name, key["block/".len..], name }); break :blk null; } @@ -340,6 +340,12 @@ pub fn main() !void { if (enums.get(enum_name.string)) |enum_id| enum_id else null else null; + var array_count: ?u16 = null; + var array_stride: ?u8 = null; + if (field.object.get("array")) |array| { + array_count = if (array.object.get("len")) |len| @intCast(len.integer) else null; + array_stride = if (array.object.get("stride")) |stride| @intCast(stride.integer) else null; + } try db.add_register_field(register_id, .{ .name = field_name, @@ -347,6 +353,8 @@ pub fn main() !void { .offset_bits = @intCast(bit_offset), .size_bits = @intCast(bit_size), .enum_id = enum_id, + .count = array_count, + .stride = array_stride, }); } } diff --git a/tools/regz/src/Database.zig b/tools/regz/src/Database.zig index 1b8a231e..e116dacb 100644 --- a/tools/regz/src/Database.zig +++ b/tools/regz/src/Database.zig @@ -201,7 +201,8 @@ pub const StructField = struct { size_bits: u8, offset_bits: u8, enum_id: ?EnumID, - count: ?u64, + count: ?u16, + stride: ?u8, pub const sql_opts = SQL_Options{ .foreign_keys = &.{ @@ -217,6 +218,8 @@ pub const StructField = struct { }; pub fn get_size_bits(field: *const StructField) u32 { + if (field.count != null and field.count.? > 1 and field.stride > field.size_bits) + log.warn("get_size_bits() result is unreliable for field array {s} with stride {d} bits > size {d} bits", .{ field.name, field.stride, field.size_bits }); return if (field.count) |count| @intCast(field.size_bits * count) else @@ -1141,6 +1144,7 @@ pub fn get_register_fields( \\ sf.offset_bits, \\ sf.enum_id, \\ sf.count, + \\ sf.stride, \\ ROW_NUMBER() OVER ( \\ PARTITION BY sf.struct_id, sf.offset_bits \\ ORDER BY sf.offset_bits ASC, sf.size_bits ASC @@ -1157,7 +1161,8 @@ pub fn get_register_fields( \\ size_bits, \\ offset_bits, \\ enum_id, - \\ count + \\ count, + \\ stride \\ FROM OrderedFields \\ WHERE row_num = 1 \\) @@ -1714,6 +1719,7 @@ pub const AddStructFieldOptions = struct { offset_bits: u8, enum_id: ?EnumID = null, count: ?u16 = null, + stride: ?u8 = null, }; pub fn add_register_field(db: *Database, parent: RegisterID, opts: AddStructFieldOptions) !void { @@ -1743,9 +1749,9 @@ pub fn add_struct_field(db: *Database, parent: StructID, opts: AddStructFieldOpt try db.exec( \\INSERT INTO struct_fields - \\ (struct_id, name, description, size_bits, offset_bits, enum_id, count) + \\ (struct_id, name, description, size_bits, offset_bits, enum_id, count, stride) \\VALUES - \\ (?, ?, ?, ?, ?, ?, ?) + \\ (?, ?, ?, ?, ?, ?, ?, ?) , .{ .struct_id = parent, .name = opts.name, @@ -1754,17 +1760,19 @@ pub fn add_struct_field(db: *Database, parent: StructID, opts: AddStructFieldOpt .offset_bits = opts.offset_bits, .enum_id = opts.enum_id, .count = opts.count, + .stride = opts.stride, }); savepoint.commit(); - log.debug("add_struct_field: parent={} name='{s}' offset_bits={} size_bits={} enum_id={?} count={?}", .{ + log.debug("add_struct_field: parent={} name='{s}' offset_bits={} size_bits={} enum_id={?} count={?} stride={?}", .{ parent, opts.name, opts.offset_bits, opts.size_bits, opts.enum_id, opts.count, + opts.stride, }); } diff --git a/tools/regz/src/arch/arm.zig b/tools/regz/src/arch/arm.zig index 697899ed..51e9412b 100644 --- a/tools/regz/src/arch/arm.zig +++ b/tools/regz/src/arch/arm.zig @@ -127,7 +127,7 @@ pub fn write_interrupt_vector( } if (interrupt.description) |description| - try gen.write_comment(db.gpa, description, writer); + try gen.write_doc_comment(db.gpa, description, writer); try writer.print("{}: Handler = unhandled,\n", .{ std.zig.fmtId(interrupt.name), diff --git a/tools/regz/src/arch/avr.zig b/tools/regz/src/arch/avr.zig index f27247cd..b936c892 100644 --- a/tools/regz/src/arch/avr.zig +++ b/tools/regz/src/arch/avr.zig @@ -47,7 +47,7 @@ pub fn write_interrupt_vector( } if (interrupt.description) |description| - try gen.write_comment(arena, description, writer); + try gen.write_doc_comment(arena, description, writer); try writer.print("{}: Handler = unhandled,\n", .{ std.zig.fmtId(interrupt.name), diff --git a/tools/regz/src/arch/riscv.zig b/tools/regz/src/arch/riscv.zig index 9d89ed28..df7711e8 100644 --- a/tools/regz/src/arch/riscv.zig +++ b/tools/regz/src/arch/riscv.zig @@ -95,7 +95,7 @@ pub fn write_interrupt_vector( } if (interrupt.description) |description| - try gen.write_comment(db.gpa, description, writer); + try gen.write_doc_comment(db.gpa, description, writer); try writer.print("{}: Handler = unhandled,\n", .{ std.zig.fmtId(interrupt.name), diff --git a/tools/regz/src/gen.zig b/tools/regz/src/gen.zig index 16a2961a..2c1ee2d5 100644 --- a/tools/regz/src/gen.zig +++ b/tools/regz/src/gen.zig @@ -83,7 +83,15 @@ fn write_devices(db: *Database, arena: Allocator, writer: anytype) !void { try writer.writeAll("};\n"); } -pub fn write_comment(allocator: Allocator, comment: []const u8, writer: anytype) !void { +pub fn write_doc_comment(allocator: Allocator, comment: []const u8, writer: anytype) !void { + try write_comment(allocator, "///", comment, writer); +} + +pub fn write_regular_comment(allocator: Allocator, comment: []const u8, writer: anytype) !void { + try write_comment(allocator, "//", comment, writer); +} + +fn write_comment(allocator: Allocator, comptime comment_prefix: []const u8, comment: []const u8, writer: anytype) !void { var tokenized = std.ArrayList(u8).init(allocator); defer tokenized.deinit(); @@ -103,7 +111,7 @@ pub fn write_comment(allocator: Allocator, comment: []const u8, writer: anytype) var line_it = std.mem.tokenizeScalar(u8, unescaped, '\n'); while (line_it.next()) |line| - try writer.print("///{s}\n", .{line}); + try writer.print("{s}{s}\n", .{ comment_prefix, line }); } fn write_string(str: []const u8, writer: anytype) !void { @@ -123,7 +131,7 @@ fn write_device(db: *Database, arena: Allocator, device: *const Database.Device, const writer = buffer.writer(); if (device.description) |description| { - try write_comment(arena, description, writer); + try write_doc_comment(arena, description, writer); } try writer.print( @@ -294,11 +302,11 @@ fn write_device_peripheral( const type_ref = try types_reference(db, arena, .{ .@"struct" = instance.struct_id }); if (try get_device_peripheral_description(db, arena, instance)) |description| - try write_comment(arena, description, writer); + try write_doc_comment(arena, description, writer); // TODO: get description //else if (s.description) |desc| - // try write_comment(arena, desc, writer); + // try write_doc_comment(arena, desc, writer); var array_prefix_buf: [80]u8 = undefined; const array_prefix = if (instance.count) |count| @@ -362,7 +370,7 @@ fn write_struct_decl( const writer = buffer.writer(); try writer.writeByte('\n'); if (description) |d| - try write_comment(arena, d, writer); + try write_doc_comment(arena, d, writer); const zero_sized = registers.len == 0; const has_modes = modes.len > 0; @@ -445,7 +453,7 @@ fn write_enum(db: *Database, arena: Allocator, e: *const Enum, out_writer: anyty // assert(std.math.ceilPowerOfTwo(field_set.count()) <= size); if (e.description) |description| - try write_comment(arena, description, writer); + try write_doc_comment(arena, description, writer); try writer.print("pub const {} = enum(u{}) {{\n", .{ std.zig.fmtId(e.name.?), @@ -483,7 +491,7 @@ fn write_enum_field( // TODO: use size to print the hex value (pad with zeroes accordingly) _ = size; if (enum_field.description) |description| - try write_comment(arena, description, writer); + try write_doc_comment(arena, description, writer); try writer.print("{} = 0x{x},\n", .{ std.zig.fmtId(enum_field.name), enum_field.value }); } @@ -666,7 +674,7 @@ fn write_register( const writer = buffer.writer(); if (register.description) |description| - try write_comment(arena, description, writer); + try write_doc_comment(arena, description, writer); var array_prefix_buf: [80]u8 = undefined; const array_prefix: []const u8 = if (register.count) |count| @@ -696,6 +704,12 @@ fn write_register( try out_writer.writeAll(buffer.items); } +/// Determine if a field comes before another, i.e. has a lower bit offset in the register +/// (or should be preferred to another, if they incorrectly have the same offset). +fn field_comes_before(_: void, a: Database.StructField, b: Database.StructField) bool { + return a.offset_bits < b.offset_bits or (a.offset_bits == b.offset_bits and a.size_bits < b.size_bits); +} + fn write_fields( db: *Database, arena: Allocator, @@ -703,71 +717,71 @@ fn write_fields( register_size_bits: u64, out_writer: anytype, ) !void { - // Fields are assumed to be in order of offset, it's possible there are - // fields that overlap so we're going to filter out some fields so there's - // no overlap - var non_overlapping = std.ArrayList(Database.StructField).init(arena); + // We first expand every 'array field' into its consituent fields, + // named e.g. `@OISN[0]`, `@OISN[1]`, etc. for `field.name` OISN. + var expanded_fields = std.ArrayList(Database.StructField).init(arena); for (fields) |field| { - if (non_overlapping.items.len == 0) { - try non_overlapping.append(field); - continue; - } - - const last_field = &non_overlapping.items[non_overlapping.items.len - 1]; - const last_field_end_bits = last_field.offset_bits + last_field.get_size_bits(); - - // If there's no overlap then append and continue - if (last_field_end_bits <= field.offset_bits) { - try non_overlapping.append(field); - } else if (last_field.offset_bits == field.offset_bits and - field.get_size_bits() < last_field.get_size_bits()) - { - // Edge case for overlapping - // - // If a field's offset comes before another, it has precedence, but if - // the offsets are the exact same, and the new one is smaller, then the - // new will replace the old. - last_field.* = field; - } + if (field.count) |count| { + var stride = field.stride orelse field.size_bits; + if (stride < field.size_bits) { + log.warn("array field stride {d} for field {s} is too small, assuming stride == field size ({d}) instead", .{ stride, field.name, field.size_bits }); + stride = field.size_bits; + } + for (0..count) |i| { + var subfield = field; + subfield.count = undefined; + subfield.stride = undefined; + subfield.offset_bits = field.offset_bits + @as(u8, @intCast(stride * i)); + subfield.name = try std.fmt.allocPrint(arena, "{s}[{d}]", .{ field.name, i }); + subfield.description = try std.fmt.allocPrint(arena, "({d}/{d} of {s}) {s}", .{ i + 1, count, field.name, field.description orelse "" }); + try expanded_fields.append(subfield); + } + } else try expanded_fields.append(field); } + // the 'count' and 'stride' of each entry of `expanded_fields` are never used below - // TODO: Remove any fields that don't fit in the register + // Fields are not assumed to be in order of offset, but they often are, + // so we use a stable sort algorithm that is fast on almost sorted data. + // (One examples where fields are not in order, is with array fields that 'interleave', + // where both have stride > size_bits: Above those are appended out of order.) + std.sort.insertion(Database.StructField, expanded_fields.items, {}, field_comes_before); var buffer = std.ArrayList(u8).init(arena); defer buffer.deinit(); const writer = buffer.writer(); var offset: u64 = 0; - for (non_overlapping.items) |field| { - assert(offset <= field.offset_bits); + for (expanded_fields.items) |field| { + if (offset > field.offset_bits) { + // It's possible there are fields that overlap so + // we're going to filter out some fields so there's no overlap. + // + // Edge case for overlapping + // + // If the offset of this field is the exact same as for another shorter field, + // then (because of the `field_comes_before()` sort order) we will already have seen the shorter field, + // and here we are skipping the longer field. + const message = try std.fmt.allocPrint(arena, "skipped overlapping field {s} at offset {d} bits", .{ field.name, field.offset_bits }); + log.warn("{s}", .{message}); + try write_regular_comment(arena, message, writer); + continue; + } + if (offset + field.size_bits > register_size_bits) { + const message = try std.fmt.allocPrint(arena, "skipped too long field {s} at offset {d} bits, length {d} bits", .{ field.name, field.offset_bits, field.size_bits }); + log.warn("{s}", .{message}); + try write_regular_comment(arena, message, writer); + continue; + } if (offset < field.offset_bits) { try writer.print("reserved{}: u{},\n", .{ field.offset_bits, field.offset_bits - offset }); offset = field.offset_bits; } - assert(offset == field.offset_bits); - if (field.description) |description| - try write_comment(arena, description, writer); - if (field.count) |count| { - if (field.enum_id != null) - log.warn("TODO: field array with enums", .{}); - - try writer.print("{}: packed struct(u{}) {{ ", .{ - std.zig.fmtId(field.name), - field.get_size_bits(), - }); - - var j: u32 = 0; - while (j < count) : (j += 1) { - if (j > 0) - try writer.writeAll(", "); - - try writer.print("u{}", .{field.size_bits}); - } + if (field.description) |description| + try write_doc_comment(arena, description, writer); - try writer.writeAll(" },\n"); - } else if (field.enum_id) |enum_id| { + if (field.enum_id) |enum_id| { const e = try db.get_enum(arena, enum_id); if (e.name) |enum_name| { if (e.struct_id == null or try db.enum_has_name_collision(enum_id)) { @@ -803,10 +817,10 @@ fn write_fields( try writer.writeAll("},\n"); } } else { - try writer.print("{}: u{},\n", .{ std.zig.fmtId(field.name), field.get_size_bits() }); + try writer.print("{}: u{},\n", .{ std.zig.fmtId(field.name), field.size_bits }); } - offset += field.get_size_bits(); + offset += field.size_bits; } assert(offset <= register_size_bits); @@ -1296,7 +1310,16 @@ test "gen.field with count, width of one, offset, and padding" { \\ pub const PORTB = extern struct { \\ PORTB: mmio.Mmio(packed struct(u8) { \\ reserved2: u2, - \\ TEST_FIELD: packed struct(u5) { u1, u1, u1, u1, u1 }, + \\ /// (1/5 of TEST_FIELD) + \\ @"TEST_FIELD[0]": u1, + \\ /// (2/5 of TEST_FIELD) + \\ @"TEST_FIELD[1]": u1, + \\ /// (3/5 of TEST_FIELD) + \\ @"TEST_FIELD[2]": u1, + \\ /// (4/5 of TEST_FIELD) + \\ @"TEST_FIELD[3]": u1, + \\ /// (5/5 of TEST_FIELD) + \\ @"TEST_FIELD[4]": u1, \\ padding: u1, \\ }), \\ }; @@ -1323,7 +1346,10 @@ test "gen.field with count, multi-bit width, offset, and padding" { \\ pub const PORTB = extern struct { \\ PORTB: mmio.Mmio(packed struct(u8) { \\ reserved2: u2, - \\ TEST_FIELD: packed struct(u4) { u2, u2 }, + \\ /// (1/2 of TEST_FIELD) + \\ @"TEST_FIELD[0]": u2, + \\ /// (2/2 of TEST_FIELD) + \\ @"TEST_FIELD[1]": u2, \\ padding: u2, \\ }), \\ };