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<!DOCTYPE html>
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<meta charset="utf-8">
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<title>The ZipCPU by Gisselquist Technology</title>
<meta name="description" content="The ZipCPU blog, featuring how to discussions of FPGA and soft-core CPU design. This site will be focused on Verilog solutions, using exclusively OpenSource IP products for FPGA design. Particular focus areas include topics often left out of more mainstream FPGA design courses such as how to debug an FPGA design.
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<li>Main/Blog
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<div class="home">
<h1 class="page-heading">Blog Posts</h1>
<ul class="post-list">
<li>
<span class="post-meta">Nov 6, 2024</span>
<h2>
<a class="post-link" href="/blog/2024/11/06/not-axi.html">Your problem is not AXI</a>
</h2>
<DIV ID=<post-meta"><P>This is response to a student's question about not being able to get an AXI slave to work. Sometimes the problem is simply more fundamental.</P></DIV>
</li>
<li>
<span class="post-meta">Jul 6, 2024</span>
<h2>
<a class="post-link" href="/formal/2024/07/06/verifjourney.html">My Personal Journey in Verification</a>
</h2>
<DIV ID=<post-meta"><P>I've now gone from hardware-only verification, to simulation, through formal verification, to automated test suites. This article attempts to discuss why I've used all these steps together with some of the lessons learned along the way.</P></DIV>
</li>
<li>
<span class="post-meta">Jun 22, 2024</span>
<h2>
<a class="post-link" href="/video/2024/06/22/vidbug.html">Debugging video from across the ocean</a>
</h2>
<DIV ID=<post-meta"><P>Two years ago, I built and verified several data display modules. They passed simulation, and looked great on my screen. Now, only two years later, I've finally been able to discover why the waterfall display didn't work in hardware kept on the other side of the Atlantic Ocean.</P></DIV>
</li>
<li>
<span class="post-meta">Jun 13, 2024</span>
<h2>
<a class="post-link" href="/blog/2024/06/13/kimos.html">Bringing up Kimos</a>
</h2>
<DIV ID=<post-meta"><P>Hardware is hard. Even the simplest of bugs takes time. Let's talk about the Kimos project today, and the challenge to get the DDR3 SDRAM up and running.</P></DIV>
</li>
<li>
<span class="post-meta">Apr 1, 2024</span>
<h2>
<a class="post-link" href="/blog/2024/04/01/chasing-resets.html">Chasing resets</a>
</h2>
<DIV ID=<post-meta"><P>A true story of a design, delivered late, due to (several) unexpected problems.</P></DIV>
</li>
<li>
<span class="post-meta">Jan 20, 2024</span>
<h2>
<a class="post-link" href="/blog/2024/01/20/2023-in-review.html">2023, Year in review</a>
</h2>
<DIV ID=<post-meta"><P>Let's look back over 2023 from the standpoint of the ZipCPU blog, and Gisselquist Technology's business</P></DIV>
</li>
<li>
<span class="post-meta">Nov 25, 2023</span>
<h2>
<a class="post-link" href="/blog/2023/11/25/eth10g.html">An Overview of a 10Gb Ethernet Switch</a>
</h2>
<DIV ID=<post-meta"><P>Our 10Gb Ethernet Switch is an open design, from the RTL to the PCB the FPGA is hosted on. This article presents an overview of the networking handling within the router, what components form that path, and a quick introduction to how the routing works within the switch.</P></DIV>
</li>
<li>
<span class="post-meta">Jul 18, 2023</span>
<h2>
<a class="post-link" href="/formal/2023/07/18/sdrxframe.html">SDIO RX: Bugs found w/ Formal methods</a>
</h2>
<DIV ID=<post-meta"><P>My SDIO controller has now been tested, successfully, via simulation with success. It builds on hardware. What value, therefore, is left for formally verifying it? Let's therefore examine and count the number of bugs found while formally verifying the receive portion of this controller.</P></DIV>
</li>
<li>
<span class="post-meta">Jun 28, 2023</span>
<h2>
<a class="post-link" href="/blog/2023/06/28/sdiopkt.html">Using a Verilog task to simulate a packet generator for an SDIO controller</a>
</h2>
<DIV ID=<post-meta"><P>This article tells the story of the ongoing development of an SDIO controller, paying particular attention to how a Verilog task can be used to generate data to test one part of that controller.</P></DIV>
</li>
<li>
<span class="post-meta">May 29, 2023</span>
<h2>
<a class="post-link" href="/zipcpu/2023/05/29/zipcpu-3p0.html">Introducing the ZipCPU v3.0</a>
</h2>
<DIV ID=<post-meta"><P>It's time to announce a new version of the ZipCPU: ZipCPU v3.0! This article discusses the differences between this version of the ZipCPU and prior versions.</P></DIV>
</li>
<li>
<span class="post-meta">Apr 8, 2023</span>
<h2>
<a class="post-link" href="/blog/2023/04/08/vpktfifo.html">What is a Virtual Packet FIFO?</a>
</h2>
<DIV ID=<post-meta"><P>We know what FIFOs are, but what's a virtual packet FIFO?</P></DIV>
</li>
<li>
<span class="post-meta">Mar 13, 2023</span>
<h2>
<a class="post-link" href="/zipcpu/2023/03/13/swic.html">What is a SwiC?</a>
</h2>
<DIV ID=<post-meta"><P>Central to the motivation behind the ZipCPU is the concept of a System within a Chip, or SwiC. Let's look at what defines a SwiC, and see how that applies to the ZipCPU.</P></DIV>
</li>
<li>
<span class="post-meta">Feb 13, 2023</span>
<h2>
<a class="post-link" href="/blog/2023/02/13/eccdbg.html">Debugging the Hard Stuff</a>
</h2>
<DIV ID=<post-meta"><P>Some digital design spaces are just really hard to debug: ECC, FFTs, and cryptography are good examples of these. Let's look at some ways faults in these types of designs can be isolated.</P></DIV>
</li>
<li>
<span class="post-meta">Dec 3, 2022</span>
<h2>
<a class="post-link" href="/zipcpu/2022/12/03/no-boot.html">Your soft-core CPU won't boot. Where should you start debugging?</a>
</h2>
<DIV ID=<post-meta"><P>Let's look into several things you can do in order to find and diagnose boot failures on a soft-core CPU.</P></DIV>
</li>
<li>
<span class="post-meta">Nov 24, 2022</span>
<h2>
<a class="post-link" href="/blog/2022/11/24/thanksgiving.html">Thanksgiving! I have much to be thankful for</a>
</h2>
<DIV ID=<post-meta"><P>This thanksgiving, I have much to be thankful for. The greatest among these are my salvation, family, and business.</P></DIV>
</li>
<li>
<span class="post-meta">Nov 24, 2022</span>
<h2>
<a class="post-link" href="/quiz/2022/11/24/quiz23.html">Quiz #23: Can this assertion fail?</a>
</h2>
</li>
<li>
<span class="post-meta">Nov 12, 2022</span>
<h2>
<a class="post-link" href="/blog/2022/11/12/honesty.html">A first lesson in sales pitches: Honesty</a>
</h2>
<DIV ID=<post-meta"><P>Since my spam box seems to be filled with offers to redesign my web site, I thought I might take a moment to respond to these requests.</P></DIV>
</li>
<li>
<span class="post-meta">Nov 1, 2022</span>
<h2>
<a class="post-link" href="/quiz/2022/11/01/quiz22.html">Quiz #22: Handling cover failures</a>
</h2>
</li>
<li>
<span class="post-meta">Nov 1, 2022</span>
<h2>
<a class="post-link" href="/formal/2022/11/01/design-checkoff.html">Measuring the Steps to Design Checkoff</a>
</h2>
<DIV ID=<post-meta"><P>Before delivering a design to a customer, it's important to have a strong confidence it will work. Prior to that time, it's important to know how much time and work remain in the project. In this article, I'll demonstrate a tool I've now used with great success for that purpose.</P></DIV>
</li>
<li>
<span class="post-meta">Sep 21, 2022</span>
<h2>
<a class="post-link" href="/blog/2022/09/21/vlog-wait.html">Assignment delay's and Verilog's wait statement</a>
</h2>
<DIV ID=<post-meta"><P>I'm now spent more time than I want to admit to debugging simulation issues when using Verilog's simulation semantics. This article is an attempt to capture the lessons I've learned along the way.</P></DIV>
</li>
<li>
<span class="post-meta">Aug 30, 2022</span>
<h2>
<a class="post-link" href="/zipcpu/2022/08/30/not-my-fault.html">It's not my fault! Your code is broken.</a>
</h2>
<DIV ID=<post-meta"><P>Getting verification right is not a simple task. It takes patience and hard, methodical work.</P></DIV>
</li>
<li>
<span class="post-meta">Aug 24, 2022</span>
<h2>
<a class="post-link" href="/blog/2022/08/24/protocol-design.html">Protocol Design for Network Debugging</a>
</h2>
<DIV ID=<post-meta"><P>TCP can be a challenge in an FPGA. What shall be done when you need TCP's reliability, but can't afford the logic required?</P></DIV>
</li>
<li>
<span class="post-meta">Jul 16, 2022</span>
<h2>
<a class="post-link" href="/quiz/2022/07/16/quiz21.html">Quiz #21: Verifying all configurations of a design</a>
</h2>
</li>
<li>
<span class="post-meta">Jul 4, 2022</span>
<h2>
<a class="post-link" href="/zipcpu/2022/07/04/zipsim.html">ZipCPU Lesson: If it's not tested, it doesn't work.</a>
</h2>
<DIV ID=<post-meta"><P>A single test is often not sufficient to fully test a complex and highly configurable design. Let's look a how a flexible script can help test multiple configurations of the ZipCPU.</P></DIV>
</li>
<li>
<span class="post-meta">Jun 21, 2022</span>
<h2>
<a class="post-link" href="/blog/2022/06/21/cornerstone.html">A Coming Economic Downturn? or Worse?</a>
</h2>
<DIV ID=<post-meta"><P>Every economist I read is discussing the impending disaster. Today, let's discuss how to prepare.</P></DIV>
</li>
<li>
<span class="post-meta">May 16, 2022</span>
<h2>
<a class="post-link" href="/quiz/2022/05/16/quiz20.html">Quiz #20: Using $stable in a multiclock environment</a>
</h2>
</li>
<li>
<span class="post-meta">May 7, 2022</span>
<h2>
<a class="post-link" href="/blog/2022/05/07/learning-axi.html">Learning AXI: Where to start?</a>
</h2>
<DIV ID=<post-meta"><P>The AXI specification is the wrong place to start learning AXI. Here's a list of some ZipCPU articles that'll help you get started.</P></DIV>
</li>
<li>
<span class="post-meta">Apr 29, 2022</span>
<h2>
<a class="post-link" href="/blog/2022/04/29/proto-bringup.html">Bringing up a new piece of hardware -- what can go wrong?</a>
</h2>
<DIV ID=<post-meta"><P>This last week was the first time we fired up our SONAR system. How do you think it went?</P></DIV>
</li>
<li>
<span class="post-meta">Mar 14, 2022</span>
<h2>
<a class="post-link" href="/video/2022/03/14/axis-video.html">Rethinking Video with AXI video streams</a>
</h2>
<DIV ID=<post-meta"><P>My original video work has seen a revitalization with AXI Stream</P></DIV>
</li>
<li>
<span class="post-meta">Feb 23, 2022</span>
<h2>
<a class="post-link" href="/blog/2022/02/23/axis-abort.html">AXI Stream is broken</a>
</h2>
<DIV ID=<post-meta"><P>Few AXI stream sources can truly handle backpressure. Here I offer a solution for network packet data, via a packet ABORT signal.</P></DIV>
</li>
<li>
<span class="post-meta">Jan 3, 2022</span>
<h2>
<a class="post-link" href="/blog/2022/01/03/2021-in-review.html">2020 and 2021 in review</a>
</h2>
<DIV ID=<post-meta"><P>In honour of the new year, let's take a look back at the last two years and highlight the best posts from among them.</P></DIV>
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<span class="post-meta">Jan 1, 2022</span>
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<a class="post-link" href="/quiz/2022/01/01/quiz19.html">Quiz #19: Using disable iff in a concurrent assertion</a>
</h2>
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<span class="post-meta">Dec 30, 2021</span>
<h2>
<a class="post-link" href="/blog/2021/12/30/dbgaxil.html">Creating a Simple AXI-Lite Master for the Hexbus</a>
</h2>
<DIV ID=<post-meta"><P>While much of my recent AXI work has focused on building bursting AXI masters, the debugging AXI-lite master makes a nice example of how simple an AXI master can be.</P></DIV>
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<span class="post-meta">Nov 15, 2021</span>
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<a class="post-link" href="/blog/2021/11/15/ultimate-i2c.html">Envisioning the Ultimate I2C Controller</a>
</h2>
<DIV ID=<post-meta"><P>Just a quick thought regarding the design of what I consider will be an ultimate I2C controller</P></DIV>
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<span class="post-meta">Oct 26, 2021</span>
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<a class="post-link" href="/blog/2021/10/26/clkgate.html">Clock Gating</a>
</h2>
<DIV ID=<post-meta"><P>Can clock gating be used to improve simulation performance? Let's take a look.</P></DIV>
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<span class="post-meta">Sep 30, 2021</span>
<h2>
<a class="post-link" href="/zipcpu/2021/09/30/axiops.html">Upgrading the ZipCPU's memory unit from AXI4-lite to AXI4</a>
</h2>
<DIV ID=<post-meta"><P>AXI4 offers an opportunity for exclusive access and bursting capabilities not present in AXI4-lite. Let's look at the changes, therefore, made to the ZipCPU's memory controller to upgrade it from AXI4-lite to AXI4.</P></DIV>
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<span class="post-meta">Sep 11, 2021</span>
<h2>
<a class="post-link" href="/quiz/2021/09/11/quiz18.html">Quiz #18: Failures in clocked immediate assertions</a>
</h2>
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<span class="post-meta">Aug 28, 2021</span>
<h2>
<a class="post-link" href="/blog/2021/08/28/axi-rules.html">AXI Handshaking Rules</a>
</h2>
<DIV ID=<post-meta"><P>Let's look at some simple AXI handshaking rules for success, follow them up with example templates showing how to following them and then how to verify the rules are followed. We'll also look at some broken example designs along the way to see examples of what can go wrong.</P></DIV>
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<span class="post-meta">Aug 14, 2021</span>
<h2>
<a class="post-link" href="/blog/2021/08/14/axiperf.html">Measuring AXI latency and throughput performance</a>
</h2>
<DIV ID=<post-meta"><P>It's important when using any tool to know how well it performs. This article discusses how to measure the performance of any link in an AXI system.</P></DIV>
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<span class="post-meta">Aug 5, 2021</span>
<h2>
<a class="post-link" href="/quiz/2021/08/05/quiz17.html">Quiz #17: Induction failures</a>
</h2>
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<span class="post-meta">Jul 25, 2021</span>
<h2>
<a class="post-link" href="/blog/2021/07/25/healing.html">The other half of the Gospel</a>
</h2>
<DIV ID=<post-meta"><P>The other half of the Gospel is healing. Jesus healed men then. He still heals men today.</P></DIV>
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<span class="post-meta">Jul 23, 2021</span>
<h2>
<a class="post-link" href="/zipcpu/2021/07/23/cpusim.html">CPU based simulation, first thoughts</a>
</h2>
<DIV ID=<post-meta"><P>When testing, something needs to drive your test--a script of some type. This article explores the question of whether or not that script should be written in software to run on a soft-core CPU, or in Verilog/VHDL?</P></DIV>
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<span class="post-meta">Jul 10, 2021</span>
<h2>
<a class="post-link" href="/quiz/2021/07/10/quiz16.html">Quiz #16: Immediate assertions in the presence of asynchronous resets</a>
</h2>
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<span class="post-meta">Jul 3, 2021</span>
<h2>
<a class="post-link" href="/zipcpu/2021/07/03/slowmpy.html">Building a Better Verilog Multiply for the ZipCPU</a>
</h2>
<DIV ID=<post-meta"><P>Low logic and soft multiplies don't often go together. Here we discuss how to create a slow multiply in hardware, using a minimum amount of logic, for the case where no hardware accelerators are available.</P></DIV>
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<span class="post-meta">Jun 28, 2021</span>
<h2>
<a class="post-link" href="/blog/2021/06/28/master-examples.html">Examples of AXI4 bus masters</a>
</h2>
<DIV ID=<post-meta"><P>At user request, here's a list of AXI4 master's I've recently built, and two of the test beds I've been using to test them.</P></DIV>
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<li>
<span class="post-meta">Jun 12, 2021</span>
<h2>
<a class="post-link" href="/quiz/2021/06/12/quiz15.html">Quiz #15: Pass-through memory</a>
</h2>
</li>
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<span class="post-meta">May 22, 2021</span>
<h2>
<a class="post-link" href="/blog/2021/05/22/vhdlaxil.html">Fixing Xilinx's Broken AXI-lite Design in VHDL</a>
</h2>
<DIV ID=<post-meta"><P>While I don't normally do VHDL work, I recently had the opportunity to verify Xilinx's AXI-lite demonstration design (again)--this time in VHDL. So I thought I'd write about it, and offer some quick and easy fixes to the design along the way.</P></DIV>
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<li>
<span class="post-meta">Apr 17, 2021</span>
<h2>
<a class="post-link" href="/zipcpu/2021/04/17/axilops.html">Building a Simple AXI-lite Memory Controller</a>
</h2>
<DIV ID=<post-meta"><P>When building a CPU memory controller, I like to start with the simplest memory controller that will do the task. Here is a very basic AXI-lite memory controller for the ZipCPU.</P></DIV>
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<span class="post-meta">Mar 20, 2021</span>
<h2>
<a class="post-link" href="/blog/2021/03/20/xilinx-forums.html">Common AXI Themes on Xilinx's Forum</a>
</h2>
<DIV ID=<post-meta"><P>Let's take a quick look through Xilinx's forums, to see if there are some common AXI themes among the forum help requests.</P></DIV>
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<span class="post-meta">Mar 18, 2021</span>
<h2>
<a class="post-link" href="/zipcpu/2021/03/18/zipos.html">Whatever happened to the ZipOS?</a>
</h2>
<DIV ID=<post-meta"><P>The ZipOS was used early on with the ZipCPU in the S6SoC project, and then we haven't heard of it again since. What happened to it?</P></DIV>
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<li>
<span class="post-meta">Mar 6, 2021</span>
<h2>
<a class="post-link" href="/blog/2021/03/06/asic-lsns.html">Lessons learned while building an ASIC design</a>
</h2>
<DIV ID=<post-meta"><P>With a background in FPGA design, I was asked to try my skill in an ASIC design. Here are some things I learned.</P></DIV>
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<li>
<span class="post-meta">Jan 29, 2021</span>
<h2>
<a class="post-link" href="/blog/2021/01/29/hiring.html">The FPGA designer who didn't get the job</a>
</h2>
<DIV ID=<post-meta"><P>Lots of people will claim an ability in digital logic design these days. Finding someone with character, someone who will be easy to work with who also has that ability isn't nearly as easy.</P></DIV>
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<li>
<span class="post-meta">Jan 9, 2021</span>
<h2>
<a class="post-link" href="/formal/2021/01/09/ultimate.html">Ultimate Logic</a>
</h2>
<DIV ID=<post-meta"><P>Logic can be used to prove that certain assertions must follow from the given assumptions. How then shall the assumptions be validated? What about the assumptions behind the assumptions?</P></DIV>
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<li>
<span class="post-meta">Dec 24, 2020</span>
<h2>
<a class="post-link" href="/quiz/2020/12/24/quiz14.html">Quiz #14: Two nearly identical frequencies</a>
</h2>
</li>
<li>
<span class="post-meta">Dec 19, 2020</span>
<h2>
<a class="post-link" href="/blog/2020/12/19/axil-register-checking.html">Formally verifying register handling</a>
</h2>
<DIV ID=<post-meta"><P>We've already discussed how to build a peripheral, and to verify its bus interaction. Let's now look at how to verify the register contents.</P></DIV>
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<li>
<span class="post-meta">Nov 26, 2020</span>
<h2>
<a class="post-link" href="/blog/2020/11/26/zipcpu-biz.html">Is it possible to make a living as a solo digital design engineer?</a>
</h2>
<DIV ID=<post-meta"><P>For Thanksgiving this year, let me share a bit of the story about how Gisselquist Technology came to be.</P></DIV>
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<li>
<span class="post-meta">Nov 21, 2020</span>
<h2>
<a class="post-link" href="/dsp/2020/11/21/spectrogram.html">Spectrograms need Window Functions</a>
</h2>
<DIV ID=<post-meta"><P>Let's examine the basics of localizing signal energy in time and frequency bins, showing from first principles the need for a window function how overlap choice affects this choice of taper. We'll then look at how to implement a window function in both C++ and Verilog.</P></DIV>
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<li>
<span class="post-meta">Oct 17, 2020</span>
<h2>
<a class="post-link" href="/formal/2020/10/17/friday.html">A fun Friday evening--verifying an AXI-lite slave</a>
</h2>
<DIV ID=<post-meta"><P>Can an AXI-lite slave design be formally verified, from scratch, while others look on?</P></DIV>
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<li>
<span class="post-meta">Oct 3, 2020</span>
<h2>
<a class="post-link" href="/blog/2020/10/03/tfrvalue.html">Moving values and strobes cross clock domains</a>
</h2>
<DIV ID=<post-meta"><P>Let's build a two-phase clock-domain crossing algorithm to move words from one domain to another, beating our prior four-phase method in performance and logic.</P></DIV>
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<li>
<span class="post-meta">Sep 14, 2020</span>
<h2>
<a class="post-link" href="/quiz/2020/09/14/quiz13.html">Quiz #13: Temporal assertion equivalences</a>
</h2>
</li>
<li>
<span class="post-meta">Aug 31, 2020</span>
<h2>
<a class="post-link" href="/blog/2020/08/31/run-length-encoding.html">Run length encoding an AXI stream</a>
</h2>
<DIV ID=<post-meta"><P>Run length encoding makes a nice complement to any logic analyzer. Let's take a look at how to build and verify a run-length encoder in Verilog.</P></DIV>
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<li>
<span class="post-meta">Aug 22, 2020</span>
<h2>
<a class="post-link" href="/blog/2020/08/22/oddr.html">Driving an output on both edges of the clock</a>
</h2>
<DIV ID=<post-meta"><P>Every now and then you need a replacement for a library element. Today, we look at generating an ODDR output component to output logic on both edges of the clock.</P></DIV>
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<span class="post-meta">Jul 28, 2020</span>
<h2>
<a class="post-link" href="/dsp/2020/07/28/down-sampler.html">Building a Downsampling Filter</a>
</h2>
<DIV ID=<post-meta"><P>A digital downsampler is a combination of both a digital filter and an every Nth element selector. It's basic. Formally verifying it, perhaps not quite so basic.</P></DIV>
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<span class="post-meta">Jul 21, 2020</span>
<h2>
<a class="post-link" href="/formal/2020/07/21/formal-plan.html">I have a brand new piece of IP. How shall I verify it?</a>
</h2>
<DIV ID=<post-meta"><P>Verification doesn't begin once a design is complete. It needs to begin long before that, ideally before the design is ever simulated in the first place</P></DIV>
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<li>
<span class="post-meta">Jul 4, 2020</span>
<h2>
<a class="post-link" href="/blog/2020/07/04/clkcounter.html">Measuring clock speed</a>
</h2>
<DIV ID=<post-meta"><P>A counter makes a very simple means of measuring clock speed. Let's take a look at how to do that.</P></DIV>
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<li>
<span class="post-meta">Jun 16, 2020</span>
<h2>
<a class="post-link" href="/blog/2020/06/16/axiaddr-limits.html">The hard part of building a bursting AXI Master</a>
</h2>
<DIV ID=<post-meta"><P>Getting an AXI master to generate high throughput burst requests involves some challenging criteria which can compete with a high clock speed.</P></DIV>
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<li>
<span class="post-meta">Jun 12, 2020</span>
<h2>
<a class="post-link" href="/formal/2020/06/12/four-keys.html">Four keys to getting your design to work the first time</a>
</h2>
<DIV ID=<post-meta"><P>No, it's not a magical cure, just a general observation: there are four key pieces to verification that come back over and over again in designs that just work the first time</P></DIV>
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<li>
<span class="post-meta">May 16, 2020</span>
<h2>
<a class="post-link" href="/quiz/2020/05/16/quiz12.html">Quiz #12: Catching extraneous acknowledgments</a>
</h2>
</li>
<li>
<span class="post-meta">May 16, 2020</span>
<h2>
<a class="post-link" href="/formal/2020/05/16/firewall.html">Building a Protocol Firewall</a>
</h2>
<DIV ID=<post-meta"><P>A bus fault isolator can be a very useful tool for debugging an AXI interaction within an active design. Once the bus faults and the design locks up, further debugging is a challenge. However, if a fault isolator can keep things from locking up and perhaps even reset the quarrelsome component following a fault, then finding the bug gets a lot easier.</P></DIV>
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<li>
<span class="post-meta">Apr 20, 2020</span>
<h2>
<a class="post-link" href="/dsp/2020/04/20/axil2axis.html">Debugging AXI Streams</a>
</h2>
<DIV ID=<post-meta"><P>Debugging a broken AXI stream is a common problem appearing over and over again on various forums. In-Circuit Logic Analyzers don't do the problem justice, and often instead hide critical details of the stream protocol. In this article, we'll look at how to build a key piece of scaffolding you might use to debug an AXI stream processor.</P></DIV>
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<li>
<span class="post-meta">Apr 8, 2020</span>
<h2>
<a class="post-link" href="/blog/2020/04/08/axitb.html">Adding an AXI-Lite interface to your Verilator test script</a>
</h2>
<DIV ID=<post-meta"><P>There are lots of ways to test AXI components, my favorite being formal methods. Every now and again, though, you need a simulation where you can script AXI interactions. This article explores how to do that from a C++ Verilator test bench--something that can be used to (nearly) simulate an on-board CPU.</P></DIV>
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<li>
<span class="post-meta">Apr 1, 2020</span>
<h2>
<a class="post-link" href="/blog/2020/04/01/design-flow.html">Re: What does your design flow look like?</a>
</h2>
<DIV ID=<post-meta"><P>Someone recently asked me if I had a post or something that described the tool chain I used for my own development. This article walks through my preferred tools, and how or when I might use them. It also contains several examples of lessons learned along the way.</P></DIV>
</li>
<li>
<span class="post-meta">Mar 23, 2020</span>
<h2>
<a class="post-link" href="/blog/2020/03/23/wbm2axisp.html">Building a basic AXI Master</a>
</h2>
<DIV ID=<post-meta"><P>A bridge from Wisbone to AXI makes a marvelous example of how one might build an AXI master</P></DIV>
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<li>
<span class="post-meta">Mar 17, 2020</span>
<h2>
<a class="post-link" href="/dsp/2020/03/17/cheap-spectra.html">Cheap Spectral Estimation</a>
</h2>
<DIV ID=<post-meta"><P>Placing an FFT inside an FPGA just to debug what may be going right or wrong with your DSP algorithm can be a costly addition. Let's look instead at an AutoCorrelation based alternative which can get us to roughly the same result, while moving the difficult math out of the real-time flow and into a nearby processor.</P></DIV>
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<li>
<span class="post-meta">Mar 14, 2020</span>
<h2>
<a class="post-link" href="/blog/2020/03/14/axi-reset.html">Locally resetting an AXI component</a>
</h2>
<DIV ID=<post-meta"><P>It's often advantageous to bring a single component within a design back to a known reset state. Doing this without impacting the other items within the design can be a challenge. Here, we'll look at examples of resetting both an AXI slave and an AXI master without resetting the rest of the surrounding design.</P></DIV>
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<li>
<span class="post-meta">Mar 12, 2020</span>
<h2>
<a class="post-link" href="/dsp/2020/03/12/quadpll.html">Adjusting our logic PLL to handle I&Q</a>
</h2>
<DIV ID=<post-meta"><P>By making some simple changes to the phase estimator of our logic PLL, it can be made to run in a quadrature I+Q context</P></DIV>
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<li>
<span class="post-meta">Mar 8, 2020</span>
<h2>
<a class="post-link" href="/blog/2020/03/08/easyaxil.html">Buidilng an AXI-Lite slave the easy way</a>
</h2>
<DIV ID=<post-meta"><P>After building several AXI-Lite slave interfaces, they've become almost routine and easy to build. In this article, we examine how easy and simple a fully functional AXI-Lite slave interface can be to build.</P></DIV>
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<li>
<span class="post-meta">Feb 17, 2020</span>
<h2>
<a class="post-link" href="/blog/2020/02/17/mustard-seed.html">The Faith of a Mustard Seed</a>
</h2>
<DIV ID=<post-meta"><P>Whether or not a man has faith as a grain of mustard seed was never about the size, quantity, or amount of his faith. If you look at what a mustard seed does, you'll realize that a mustard seed is an amazing example of what faith is in the first place.</P></DIV>
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<li>
<span class="post-meta">Feb 7, 2020</span>
<h2>
<a class="post-link" href="/dsp/2020/02/07/bad-histogram.html">A Histogram Gone Bad</a>
</h2>
<DIV ID=<post-meta"><P>I took my working histogram component, and placed it into a full design. It didn't work. Let's take a look at what happened.</P></DIV>
</li>
<li>
<span class="post-meta">Jan 23, 2020</span>
<h2>
<a class="post-link" href="/quiz/2020/01/23/quiz11.html">Quiz #11: Induction and clock enables</a>
</h2>
</li>
<li>
<span class="post-meta">Jan 17, 2020</span>
<h2>
<a class="post-link" href="/quiz/2020/01/17/quiz10.html">Quiz #10: Checking stall conditions</a>
</h2>
</li>
<li>
<span class="post-meta">Jan 13, 2020</span>
<h2>
<a class="post-link" href="/blog/2020/01/13/reuse.html">Lessons in Hardware Reuse</a>
</h2>
<DIV ID=<post-meta"><P>Hardware component reuse has been a goal of digital designers for a long time. Let's look at some lessons learned regarding hardware reuse within a company, where reuse should be easy.</P></DIV>
</li>
<li>
<span class="post-meta">Jan 1, 2020</span>
<h2>
<a class="post-link" href="/blog/2020/01/01/2019-in-review.html">2019: AXI Meets Formal Verification</a>
</h2>
<DIV ID=<post-meta"><P>This article looks over 2019 in review from the perspective of the ZipCPU blog. In particular, the top ZipCPU blog articles across all of 2019 are reviewed.</P></DIV>
</li>
<li>
<span class="post-meta">Dec 25, 2019</span>
<h2>
<a class="post-link" href="/blog/2019/12/25/christmas-gospel.html">The Christmas Gospel</a>
</h2>
<DIV ID=<post-meta"><P>Let's trace the origins of Christmas, from beginning to end</P></DIV>
</li>
<li>
<span class="post-meta">Dec 21, 2019</span>
<h2>
<a class="post-link" href="/dsp/2019/12/21/histogram.html">Using a Histogram to Debug A/D Data Streams</a>
</h2>
<DIV ID=<post-meta"><P>Histograms are an important part of debugging a data channel. Let's take a look at some pictures, and then discuss how to go about implementing one</P></DIV>
</li>
<li>
<span class="post-meta">Dec 12, 2019</span>
<h2>
<a class="post-link" href="/quiz/2019/12/12/quiz09.html">Quiz #9: Immediate assertions midst blocking assignments</a>
</h2>
</li>