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I have two of these boards, one I use in the IIe and one in a ROM1 IIGS (in slot 3). It works great in both machines, however something interesting happens on the IIgs, and only in some software. I know I have seen it elsewhere but I can't remember the software title.
I will say that it is reproducable every time with the FTA demo "modulae". Sometimes these lines appear as shown in the screenshots. I have an actual IIgs monitor connected at the same time as the flat panel, and this is not happening on the IIgs RGB monitor itself. This line anomaly is only happening on the A2FPGA HDMI output.
Do you have any what this could be?
I have tested both A2FPGA boards with the same result, so it is not a matter of a faulty board. The core is up to date as well to the 12/14 release.
The text was updated successfully, but these errors were encountered:
If I had to guess, it looks like a bug in the A2FPGA's handling of the IIgs pixel fill in super hires graphics mode. I'm not familar with modulae. Can you provide a link to it?
When you launch it and press the mouse button to get past the opening intro, turn off "automatix" in the interface and then to can manually move through the modules to "fill node three dee!".
The lines will either be immediately apparent or you may have to wait a minute or two for it to run. Sometimes for me they are immediate, sometimes it takes a few minutes.
Hello,
I have two of these boards, one I use in the IIe and one in a ROM1 IIGS (in slot 3). It works great in both machines, however something interesting happens on the IIgs, and only in some software. I know I have seen it elsewhere but I can't remember the software title.
I will say that it is reproducable every time with the FTA demo "modulae". Sometimes these lines appear as shown in the screenshots. I have an actual IIgs monitor connected at the same time as the flat panel, and this is not happening on the IIgs RGB monitor itself. This line anomaly is only happening on the A2FPGA HDMI output.
Do you have any what this could be?
I have tested both A2FPGA boards with the same result, so it is not a matter of a faulty board. The core is up to date as well to the 12/14 release.
The text was updated successfully, but these errors were encountered: