-
Notifications
You must be signed in to change notification settings - Fork 91
/
Copy pathAssembler.cpp
3017 lines (2715 loc) · 108 KB
/
Assembler.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/* -*- Mode: C++; c-basic-offset: 4; indent-tabs-mode: nil; tab-width: 4 -*- */
/* vi: set ts=4 sw=4 expandtab: (add to ~/.vimrc: set modeline modelines=5) */
/* This Source Code Form is subject to the terms of the Mozilla Public
* License, v. 2.0. If a copy of the MPL was not distributed with this
* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
#include "nanojit.h"
#ifdef FEATURE_NANOJIT
#ifdef VMCFG_VTUNE
#include "../core/CodegenLIR.h"
#endif
#ifdef _MSC_VER
// disable some specific warnings which are normally useful, but pervasive in the code-gen macros
#pragma warning(disable:4310) // cast truncates constant value
#endif
#ifdef VMCFG_VTUNE
namespace vtune {
using namespace nanojit;
void vtuneStart(void*, NIns*);
void vtuneEnd(void*, NIns*);
void vtuneLine(void*, int, NIns*);
void vtuneFile(void*, void*);
}
using namespace vtune;
#endif // VMCFG_VTUNE
namespace nanojit
{
// #if defined(NANOJIT_THUMB2) && defined(NJ_VERBOSE) && defined(AVMPLUS_UNIX)
#if 0
#include <dlfcn.h>
//
/* convenience typedefs */
typedef void* (*decode_instructions_event_callback_ftype) (void*, const char*, void*);
typedef int (*decode_instructions_printf_callback_ftype) (void*, const char*, ...);
typedef void* (*decode_instructions_ftype) (void* start, void* end,
decode_instructions_event_callback_ftype event_callback,
void* event_stream,
decode_instructions_printf_callback_ftype printf_callback,
void* printf_stream,
const char* options);
#define DECODE_INSTRUCTIONS_NAME "decode_instructions"
#define HSDIS_NAME "hsdis"
#define LIBARCH "arm"
#define LIB_EXT ".so"
static void* decode_instructions_pv = 0;
static const char* hsdis_path[] = {
HSDIS_NAME"-"LIBARCH LIB_EXT,
"./" HSDIS_NAME"-"LIBARCH LIB_EXT,
NULL
};
static const char* load_decode_instructions() {
void* dllib = NULL;
const char* *next_in_path = hsdis_path;
while (1) {
decode_instructions_pv = dlsym(dllib, DECODE_INSTRUCTIONS_NAME);
if (decode_instructions_pv != NULL)
return NULL;
if (dllib != NULL)
return "plugin does not defined "DECODE_INSTRUCTIONS_NAME;
for (dllib = NULL; dllib == NULL; ) {
const char* next_lib = (*next_in_path++);
if (next_lib == NULL)
return "cannot find plugin "HSDIS_NAME LIB_EXT;
dllib = dlopen(next_lib, RTLD_LAZY);
}
}
}
/* does the event match the tag, followed by a null, space, or slash? */
#define MATCH(event, tag) \
(!strncmp(event, tag, sizeof(tag)-1) && \
(!event[sizeof(tag)-1] || strchr(" /", event[sizeof(tag)-1])))
int Assembler::disassembler_printf(void* arg, const char* format, ...) {
nanojit::Assembler* assembler = (nanojit::Assembler*)arg;
va_list args;
va_start(args, format);
vsprintf(assembler->outline + strlen(assembler->outline), format, args);
return 0;
}
void* Assembler::disassembler_event(void* cookie, const char* event, void* arg) {
nanojit::Assembler* assembler = (nanojit::Assembler*)cookie;
if (MATCH(event, "insn")) {
sprintf(assembler->outline + strlen(assembler->outline), "%p ", arg);
if (assembler->_logc->lcbits & LC_Bytes) {
unsigned char* bytes = (unsigned char*)arg;
sprintf(assembler->outline + strlen(assembler->outline), " %02x %02x %02x %02x",
bytes[0], bytes[1], bytes[2], bytes[3]);
}
sprintf(assembler->outline + strlen(assembler->outline), " ");
} else if (MATCH(event, "/insn")) {
} else if (MATCH(event, "mach")) {
} else if (MATCH(event, "addr")) {
}
/* null return is always safe; can mean "I ignored it" */
return NULL;
}
void Assembler::disassemble(void* from, void* to) {
from = (void*)(((intptr_t)from) & ~1);
to = (void*)(((intptr_t)to) & ~1);
const char* options = "force-thumb,reg-names-std";
const char* err = load_decode_instructions();
if (err != NULL) {
static int once = 0;
if (!once) {
printf("%s: %s\n", err, dlerror());
once = 1;
}
return;
}
outline[0] = '\0';
decode_instructions_ftype decode_instructions
= (decode_instructions_ftype) decode_instructions_pv;
void* res = (*decode_instructions)(from, to,
disassembler_event, (void*)this,
disassembler_printf, (void*)this,
options);
output();
if (res != to)
printf("*** Error while disassembling: %p!\n", res);
}
#endif //defined(NANOJIT_THUMB2) && defined(NJ_VERBOSE)
/**
* Need the following:
*
* - merging paths ( build a graph? ), possibly use external rep to drive codegen
*/
Assembler::Assembler(CodeAlloc& codeAlloc, Allocator& dataAlloc, Allocator& alloc, LogControl* logc, const Config& config, MetaDataWriter* mdWriter)
: alloc(alloc)
, _codeAlloc(codeAlloc)
, _dataAlloc(dataAlloc)
, _thisfrag(NULL)
, _branchStateMap(alloc)
, _patches(alloc)
, _labels(alloc)
, _noise(NULL)
#if NJ_USES_IMMD_POOL
, _immDPool(alloc)
#endif
#if NJ_USES_IMMF4_POOL
, _immF4Pool(alloc)
#endif
, codeList(NULL)
, _epilogue(NULL)
, _err(None)
#if PEDANTIC
, pedanticTop(NULL)
#endif
#ifdef VMCFG_VTUNE
, vtuneHandle(NULL)
#endif
, _mdWriter(mdWriter)
, _blindMask32(0)
#ifdef NANOJIT_64BIT
, _blindMask64(0L)
#endif
, _config(config)
{
(void)logc;
verbose_only( _logc = logc; )
verbose_only( _outputCache = 0; )
verbose_only( outline[0] = '\0'; )
verbose_only( outlineEOL[0] = '\0'; )
reset();
}
#ifdef _DEBUG
/*static*/ LIns* const AR::BAD_ENTRY = (LIns*)0xdeadbeef;
void AR::validateQuick()
{
NanoAssert(_highWaterMark < NJ_MAX_STACK_ENTRY);
NanoAssert(_entries[0] == NULL);
// Only check a few entries around _highWaterMark.
uint32_t const RADIUS = 4;
uint32_t const lo = (_highWaterMark > 1 + RADIUS ? _highWaterMark - RADIUS : 1);
uint32_t const hi = (_highWaterMark + 1 + RADIUS < NJ_MAX_STACK_ENTRY ? _highWaterMark + 1 + RADIUS : NJ_MAX_STACK_ENTRY);
for (uint32_t i = lo; i <= _highWaterMark; ++i)
NanoAssert(_entries[i] != BAD_ENTRY);
for (uint32_t i = _highWaterMark+1; i < hi; ++i)
NanoAssert(_entries[i] == BAD_ENTRY);
}
void AR::validateFull()
{
NanoAssert(_highWaterMark < NJ_MAX_STACK_ENTRY);
NanoAssert(_entries[0] == NULL);
for (uint32_t i = 1; i <= _highWaterMark; ++i)
NanoAssert(_entries[i] != BAD_ENTRY);
for (uint32_t i = _highWaterMark+1; i < NJ_MAX_STACK_ENTRY; ++i)
NanoAssert(_entries[i] == BAD_ENTRY);
}
void AR::validate()
{
static uint32_t validateCounter = 0;
if (++validateCounter >= 100)
{
validateFull();
validateCounter = 0;
}
else
{
validateQuick();
}
}
#endif
inline void AR::clear()
{
_highWaterMark = 0;
NanoAssert(_entries[0] == NULL);
#ifdef _DEBUG
for (uint32_t i = 1; i < NJ_MAX_STACK_ENTRY; ++i)
_entries[i] = BAD_ENTRY;
#endif
}
bool AR::Iter::next(LIns*& ins, uint32_t& nStackSlots, int32_t& arIndex)
{
while (_i <= _ar._highWaterMark) {
ins = _ar._entries[_i];
if (ins) {
arIndex = _i;
nStackSlots = nStackSlotsFor(ins);
_i += nStackSlots;
return true;
}
_i++;
}
ins = NULL;
nStackSlots = 0;
arIndex = 0;
return false;
}
void Assembler::arReset()
{
_activation.clear();
_branchStateMap.clear();
_patches.clear();
_labels.clear();
#if NJ_USES_IMMD_POOL
_immDPool.clear();
#endif
#if NJ_USES_IMMF4_POOL
_immF4Pool.clear();
#endif
}
void Assembler::codeAlloc(NIns *&start, NIns *&end, NIns *&eip
verbose_only(, size_t &nBytes)
, size_t byteLimit)
{
// save the block we just filled
if (start)
CodeAlloc::add(codeList, start, end);
// CodeAlloc contract: allocations never fail
_codeAlloc.alloc(start, end, byteLimit);
verbose_only( nBytes += (end - start) * sizeof(NIns); )
NanoAssert(uintptr_t(end) - uintptr_t(start) >= (size_t)LARGEST_UNDERRUN_PROT);
eip = end;
verbose_only( _nInsAfter = eip; )
}
void Assembler::clearNInsPtrs()
{
_nIns = 0;
_nExitIns = 0;
codeStart = codeEnd = 0;
exitStart = exitEnd = 0;
codeList = 0;
}
void Assembler::reset()
{
clearNInsPtrs();
nativePageReset();
_allocator.initialize(this);
arReset();
}
#ifdef _DEBUG
void Assembler::pageValidate()
{
if (error()) return;
// This may be a normal code chunk or an exit code chunk.
NanoAssertMsg(codeStart <= _nIns && _nIns <= codeEnd,
"Native instruction pointer overstep paging bounds; check overrideProtect for last instruction");
}
#endif
#ifdef _DEBUG
bool AR::isValidEntry(uint32_t idx, LIns* ins) const
{
return idx > 0 && idx <= _highWaterMark && _entries[idx] == ins;
}
void AR::checkForResourceConsistency(const RegAlloc& regs)
{
validate();
for (uint32_t i = 1; i <= _highWaterMark; ++i)
{
LIns* ins = _entries[i];
if (!ins)
continue;
uint32_t arIndex = ins->getArIndex();
NanoAssert(arIndex != 0);
if (ins->isop(LIR_allocp)) {
int const n = i + (ins->size()>>2);
for (int j=i+1; j < n; j++) {
NanoAssert(_entries[j]==ins);
}
NanoAssert(arIndex == (uint32_t)n-1);
i = n-1;
}
else if (ins->isQorD()) {
NanoAssert(_entries[i + 1]==ins);
i += 1; // skip high word
}
else if (ins->isF4()) {
NanoAssert(_entries[i + 1]==ins);
NanoAssert(_entries[i + 2]==ins);
NanoAssert(_entries[i + 3]==ins);
i += 3; // skip high words
}
else {
NanoAssertMsg(arIndex == i, "Stack record index mismatch");
}
NanoAssertMsg(!ins->isInReg() || regs.isConsistent(ins->getReg(), ins),
"Register record mismatch");
}
}
void Assembler::resourceConsistencyCheck()
{
NanoAssert(!error());
#ifdef NANOJIT_IA32
// Within the expansion of a single LIR instruction, we may use the x87
// stack for unmanaged temporaries. Otherwise, we do not use the x87 stack
// as such, but use the top element alone as a single allocatable FP register.
// Compensation code must be inserted to keep the stack balanced and avoid
// overflow, and the mechanisms for this are rather fragile and IA32-specific.
// The predicate below should hold between any pair of instructions within
// a basic block, at labels, and just after a conditional branch. Currently,
// we enforce this condition between all pairs of instructions, but this is
// overly restrictive, and would fail if we did not generate unreachable x87
// stack pops following unconditional branches.
NanoAssert((_allocator.getActive(FST0) && _fpuStkDepth == -1) ||
(!_allocator.getActive(FST0) && _fpuStkDepth == 0));
#endif
_activation.checkForResourceConsistency(_allocator);
registerConsistencyCheck();
}
void Assembler::registerConsistencyCheck()
{
RegisterMask managed = _allocator.getManagedSet();
for (Register r = lsReg(managed); managed; r = nextLsReg(managed, r)) {
// A register managed by register allocation must be either
// free or active, but not both.
if (_allocator.isFree(r)) {
NanoAssertMsgf(_allocator.getActive(r)==0,
"register %s is free but assigned to ins", gpn(r));
} else {
// An LIns defining a register must have that register in
// its reservation.
LIns* ins = _allocator.getActive(r);
NanoAssert(ins);
NanoAssert(ins->isInReg());
/* note: registers may overlap; but if they do, the primary reg. defined by the instruction must completely contain
all the overlapping registers. */
NanoAssertMsg( (rmask(r) & rmask(ins->getReg()) ) == rmask(r), "Register record mismatch");
}
}
RegisterMask not_managed = ~_allocator.getManagedSet();
for (Register r = lsReg(not_managed); not_managed; r = nextLsReg(not_managed, r)) {
// A register not managed by register allocation must be
// neither free nor active.
if (REGNUM(r) <= LastRegNum) {
NanoAssert(!_allocator.isFree(r));
NanoAssert(!_allocator.getActive(r));
}
}
}
#endif /* _DEBUG */
void Assembler::findRegFor2(RegisterMask allowa, LIns* ia, Register& ra,
RegisterMask allowb, LIns* ib, Register& rb)
{
// There should be some overlap between 'allowa' and 'allowb', else
// there's no point calling this function.
NanoAssert(allowa & allowb);
if (ia == ib) {
ra = rb = findRegFor(ia, allowa & allowb); // use intersection(allowa, allowb)
} else if (ib->isInRegMask(allowb)) {
// 'ib' is already in an allowable reg -- don't let it get evicted
// when finding 'ra'.
rb = ib->getReg();
ra = findRegFor(ia, allowa & ~rmask(rb));
} else {
ra = findRegFor(ia, allowa);
rb = findRegFor(ib, allowb & ~rmask(ra));
}
}
Register Assembler::findSpecificRegFor(LIns* i, Register w)
{
return findRegFor(i, rmask(w));
}
// Like findRegFor(), but called when the LIns is used as a pointer. It
// doesn't have to be called, findRegFor() can still be used, but it can
// optimize the LIR_allocp case by indexing off FP, thus saving the use of
// a GpReg.
//
Register Assembler::getBaseReg(LIns* base, int &d, RegisterMask allow)
{
#if !PEDANTIC
if (base->isop(LIR_allocp)) {
// The value of a LIR_allocp is a pointer to its stack memory,
// which is always relative to FP. So we can just return FP if we
// also adjust 'd' (and can do so in a valid manner). Or, in the
// PEDANTIC case, we can just assign a register as normal;
// findRegFor() will allocate the stack memory for LIR_allocp if
// necessary.
d += findMemFor(base);
return FP;
}
#else
(void) d;
#endif
return findRegFor(base, allow);
}
// Like findRegFor2(), but used for stores where the base value has the
// same type as the stored value, eg. in asm_store32() on 32-bit platforms
// and asm_store64() on 64-bit platforms. Similar to getBaseReg(),
// findRegFor2() can be called instead, but this function can optimize the
// case where the base value is a LIR_allocp.
void Assembler::getBaseReg2(RegisterMask allowValue, LIns* value, Register& rv,
RegisterMask allowBase, LIns* base, Register& rb, int &d)
{
#if !PEDANTIC
if (base->isop(LIR_allocp)) {
rb = FP;
d += findMemFor(base);
rv = findRegFor(value, allowValue);
return;
}
#else
(void) d;
#endif
findRegFor2(allowValue, value, rv, allowBase, base, rb);
}
// Finds a register in 'allow' to hold the result of 'ins'. Used when we
// encounter a use of 'ins'. The actions depend on the prior regstate of
// 'ins':
// - If the result of 'ins' is not in any register, we find an allowed
// one, evicting one if necessary.
// - If the result of 'ins' is already in an allowed register, we use that.
// - If the result of 'ins' is already in a not-allowed register, we find an
// allowed one and move it.
//
Register Assembler::findRegFor(LIns* ins, RegisterMask allow)
{
if (ins->isop(LIR_allocp)) {
// Never allocate a reg for this without stack space too.
findMemFor(ins);
}
Register r;
/* Make sure we'll get a register from a proper class */
RegisterMask copyCandidates;
NanoAssert(allow);
if (!ins->isInReg()) {
// 'ins' isn't in a register (must be in a spill slot or nowhere).
r = _allocator.allocReg(ins, allow);
} else {
r = ins->getReg();
RegisterMask rm = rmask(r);
if ( (rm & allow) == rm) {
// 'ins' is in an allowed register.
_allocator.useActive(r);
} else {
// 'ins' is in a register (r) that's not in 'allow'.
copyCandidates = _allocator.nRegCopyCandidates(r, allow);
if( copyCandidates )
{
allow = copyCandidates;
// The post-state register holding 'ins' is 's', the pre-state
// register holding 'ins' is 'r'. For example, if s=eax and
// r=ecx:
//
// pre-state: ecx(ins)
// instruction: mov eax, ecx
// post-state: eax(ins)
//
Register s = r;
_allocator.retire(r);
r = _allocator.allocReg(ins, allow);
// 'ins' is in 'allow', in register r (different to the old r);
// s is the old r.
if ((rmask(s) & GpRegs) && (rmask(r) & GpRegs)) {
MR(s, r); // move 'ins' from its pre-state reg (r) to its post-state reg (s)
} else {
asm_nongp_copy(s, r);
}
} else // register cannot be copied to one in "allow"; spill it
{
evict(ins);
r = _allocator.allocReg(ins, allow);
};
}
}
return r;
}
// Like findSpecificRegFor(), but only for when 'r' is known to be free
// and 'ins' is known to not already have a register allocated. Updates
// the regstate (maintaining the invariants) but does not generate any
// code. The return value is redundant, always being 'r', but it's
// sometimes useful to have it there for assignments.
Register Assembler::findSpecificRegForUnallocated(LIns* ins, Register r)
{
if (ins->isop(LIR_allocp)) {
// never allocate a reg for this w/out stack space too
findMemFor(ins);
}
NanoAssert(!ins->isInReg());
_allocator.allocSpecificReg(ins,r);
return r;
}
#if NJ_USES_IMMD_POOL
const uint64_t* Assembler::findImmDFromPool(uint64_t q)
{
uint64_t* p = _immDPool.get(q);
if (!p)
{
p = new (_dataAlloc) uint64_t;
*p = q;
_immDPool.put(q, p);
}
return p;
}
#endif
#if NJ_USES_IMMF4_POOL
const float4_t* Assembler::findImmF4FromPool(const float4_t& q)
{
float4_t* p = _immF4Pool.get(q);
if (!p)
{
p = new (_dataAlloc, alignof<float4_t>()) float4_t;
*p = q;
_immF4Pool.put(q, p);
}
return p;
}
#endif
int Assembler::findMemFor(LIns *ins)
{
NanoAssert(!NJ_USES_IMMD_POOL || !(ins->isImmD() || ins->isImmF()));
NanoAssert(!NJ_USES_IMMF4_POOL || !ins->isImmF4());
if (!ins->isInAr()) {
uint32_t const arIndex = arReserve(ins);
ins->setArIndex(arIndex);
NanoAssert(_activation.isValidEntry(ins->getArIndex(), ins) == (arIndex != 0));
}
return arDisp(ins);
}
// XXX: this function is dangerous and should be phased out;
// See bug 513615. Calls to it should replaced it with a
// prepareResultReg() / generate code / freeResourcesOf() sequence.
Register Assembler::deprecated_prepResultReg(LIns *ins, RegisterMask allow)
{
#ifdef NANOJIT_IA32
// We used to have to worry about possibly popping the x87 stack here.
// But this function is no longer used on i386, and this assertion
// ensures that.
NanoAssert(0);
#endif
Register r = findRegFor(ins, allow);
deprecated_freeRsrcOf(ins);
return r;
}
// Finds a register in 'allow' to hold the result of 'ins'. Also
// generates code to spill the result if necessary. Called just prior to
// generating the code for 'ins' (because we generate code backwards).
//
// An example where no spill is necessary. Lines marked '*' are those
// done by this function.
//
// regstate: R
// asm: define res into r
// * regstate: R + r(res)
// ...
// asm: use res in r
//
// An example where a spill is necessary.
//
// regstate: R
// asm: define res into r
// * regstate: R + r(res)
// * asm: spill res from r
// regstate: R
// ...
// asm: restore res into r2
// regstate: R + r2(res) + other changes from "..."
// asm: use res in r2
//
Register Assembler::prepareResultReg(LIns *ins, RegisterMask allow)
{
// At this point, we know the result of 'ins' is used later in the
// code, unless it is a call to an impure function that must be
// included for effect even though its result is ignored. It may have
// had to be evicted, in which case the restore will have already been
// generated, so we now generate the spill. QUERY: Is there any attempt
// to elide the spill if we know that all restores can be rematerialized?
#ifdef NANOJIT_IA32
const bool notInFST0 = (!ins->isInReg() || ins->getReg() != FST0);
Register r = findRegFor(ins, allow);
// If the result register is FST0, but FST0 is not in the post-regstate,
// then we must pop the x87 stack. This may occur because the result is
// unused, or because it has been stored to a spill slot or an XMM register.
const bool needPop = notInFST0 && (r == FST0);
const bool didSpill = asm_maybe_spill(ins, needPop);
if (!didSpill && needPop) {
// If the instruction is spilled, then the pop will have already
// been performed by the store to the stack slot. Otherwise, we
// must pop now. This may occur when the result of a LIR_calld
// to an impure (side-effecting) function is not used.
FSTP(FST0);
}
#else
Register r = findRegFor(ins, allow);
asm_maybe_spill(ins, false);
#endif
return r;
}
bool Assembler::asm_maybe_spill(LIns* ins, bool pop)
{
if (ins->isInAr()) {
int d = arDisp(ins);
Register r = ins->getReg();
verbose_only( RefBuf b;
if (_logc->lcbits & LC_Native) {
setOutputForEOL(" <= spill %s",
_thisfrag->lirbuf->printer->formatRef(&b, ins)); } )
int8_t nWords = ins->isF4() ? 4 :
( ins->isQorD() ? 2 : 1 );
#ifdef NANOJIT_IA32
asm_spill(r, d, pop, nWords);
#else
asm_spill(r, d, nWords); (void) pop;
#endif
return true;
}
return false;
}
// XXX: This function is error-prone and should be phased out; see bug 513615.
void Assembler::deprecated_freeRsrcOf(LIns *ins)
{
if (ins->isInReg()) {
asm_maybe_spill(ins, /*pop*/false);
_allocator.retire(ins->getReg()); // free any register associated with entry
ins->clearReg();
}
if (ins->isInAr()) {
arFree(ins); // free any AR space associated with entry
ins->clearArIndex();
}
}
// Frees all record of registers and spill slots used by 'ins'.
void Assembler::freeResourcesOf(LIns *ins)
{
if (ins->isInReg()) {
_allocator.retire(ins->getReg()); // free any register associated with entry
ins->clearReg();
}
if (ins->isInAr()) {
arFree(ins); // free any AR space associated with entry
ins->clearArIndex();
}
}
// Frees 'r' in the RegAlloc regstate, if it's not already free.
void Assembler::evictIfActive(Register r)
{
if (LIns* vic = _allocator.getActive(r)) {
NanoAssert(vic->getReg() == r);
evict(vic);
}
}
// Frees 'r' (which currently holds the result of 'vic') in the regstate.
// An example:
//
// pre-regstate: eax(ld1)
// instruction: mov ebx,-4(ebp) <= restore add1 # %ebx is dest
// post-regstate: eax(ld1) ebx(add1)
//
// At run-time we are *restoring* 'add1' into %ebx, hence the call to
// asm_restore(). But at regalloc-time we are moving backwards through
// the code, so in that sense we are *evicting* 'add1' from %ebx.
//
void Assembler::evict(LIns* vic)
{
// Not free, need to steal.
Register r = vic->getReg();
NanoAssert(!_allocator.isFree(r));
NanoAssert(vic == _allocator.getActive(r));
verbose_only( RefBuf b;
if (_logc->lcbits & LC_Native) {
setOutputForEOL(" <= restore %s",
_thisfrag->lirbuf->printer->formatRef(&b, vic)); } )
asm_restore(vic, r);
_allocator.retire(r);
vic->clearReg();
// At this point 'vic' is unused (if rematerializable), or in a spill
// slot (if not).
}
// If we have this:
//
// W = ld(addp(B, lshp(I, k)))[d] , where int(1) <= k <= int(3)
//
// then we set base=B, index=I, scale=k.
//
// Otherwise, we must have this:
//
// W = ld(addp(B, I))[d]
//
// and we set base=B, index=I, scale=0.
//
void Assembler::getBaseIndexScale(LIns* addp, LIns** base, LIns** index, int* scale)
{
NanoAssert(addp->isop(LIR_addp));
*base = addp->oprnd1();
LIns* rhs = addp->oprnd2();
int k;
if (rhs->opcode() == LIR_lshp && rhs->oprnd2()->isImmI() &&
(k = rhs->oprnd2()->immI(), (1 <= k && k <= 3)))
{
*index = rhs->oprnd1();
*scale = k;
} else {
*index = rhs;
*scale = 0;
}
}
void Assembler::patch(GuardRecord *lr)
{
if (!lr->jmp) // the guard might have been eliminated as redundant
return;
Fragment *frag = lr->exit->target;
NanoAssert(frag->fragEntry != 0);
nPatchBranch((NIns*)lr->jmp, frag->fragEntry);
CodeAlloc::flushICache(lr->jmp, LARGEST_BRANCH_PATCH);
verbose_only(verbose_outputf("patching jump at %p to target %p\n",
lr->jmp, frag->fragEntry);)
}
void Assembler::patch(SideExit *exit)
{
GuardRecord *rec = exit->guards;
NanoAssert(rec);
while (rec) {
patch(rec);
rec = rec->next;
}
}
NIns* Assembler::asm_exit(LIns* guard)
{
SideExit *exit = guard->record()->exit;
NIns* at = 0;
if (!_branchStateMap.get(exit))
{
at = asm_leave_trace(guard);
}
else
{
RegAlloc* captured = _branchStateMap.get(exit);
intersectRegisterState(*captured);
at = exit->target->fragEntry;
NanoAssert(at != 0);
_branchStateMap.remove(exit);
}
return at;
}
NIns* Assembler::asm_leave_trace(LIns* guard)
{
verbose_only( verbose_outputf("----------------------------------- ## END exit block %p", guard);)
// This point is unreachable. So free all the registers. If an
// instruction has a stack entry we will leave it alone, otherwise we
// free it entirely. intersectRegisterState() will restore.
RegAlloc capture = _allocator;
releaseRegisters();
swapCodeChunks();
_inExit = true;
verbose_only( _nInsAfter = _nIns; )
#ifdef NANOJIT_IA32
debug_only( _sv_fpuStkDepth = _fpuStkDepth; _fpuStkDepth = 0; )
#endif
nFragExit(guard);
// Restore the callee-saved register and parameters.
assignSavedRegs();
assignParamRegs();
intersectRegisterState(capture);
// this can be useful for breaking whenever an exit is taken
//INT3();
//NOP();
// we are done producing the exit logic for the guard so demark where our exit block code begins
NIns* jmpTarget = _nIns; // target in exit path for our mainline conditional jump
// swap back pointers, effectively storing the last location used in the exit path
swapCodeChunks();
_inExit = false;
verbose_only( _nInsAfter = _nIns; )
//verbose_only( verbose_outputf(" LIR_xt/xf swapCodeChunks, _nIns is now %08X(%08X), _nExitIns is now %08X(%08X)",_nIns, *_nIns,_nExitIns,*_nExitIns) );
verbose_only( verbose_outputf("%p:", jmpTarget);)
verbose_only( verbose_outputf("----------------------------------- ## BEGIN exit block (LIR_xt|LIR_xf)") );
#ifdef NANOJIT_IA32
NanoAssertMsgf(_fpuStkDepth == _sv_fpuStkDepth, "LIR_xtf, _fpuStkDepth=%d, expect %d",_fpuStkDepth, _sv_fpuStkDepth);
debug_only( _fpuStkDepth = _sv_fpuStkDepth; _sv_fpuStkDepth = 9999; )
#endif
return jmpTarget;
}
void Assembler::compile(Fragment* frag, Allocator& alloc, bool optimize verbose_only(, LInsPrinter* printer))
{
verbose_only(
bool anyVerb = (_logc->lcbits & 0xFFFF & ~LC_FragProfile) > 0;
bool liveVerb = (_logc->lcbits & 0xFFFF & LC_Liveness) > 0;
)
/* BEGIN decorative preamble */
verbose_only(
if (anyVerb) {
_logc->printf("========================================"
"========================================\n");
_logc->printf("=== BEGIN LIR::compile(%p, %p)\n",
(void*)this, (void*)frag);
_logc->printf("===\n");
})
/* END decorative preamble */
verbose_only( if (liveVerb) {
_logc->printf("\n");
_logc->printf("=== Results of liveness analysis:\n");
_logc->printf("===\n");
LirReader br(frag->lastIns);
LirFilter* lir = &br;
if (optimize) {
StackFilter* sf = new (alloc) StackFilter(lir, alloc, frag->lirbuf->sp);
lir = sf;
}
live(lir, alloc, frag, _logc);
})
/* Set up the generic text output cache for the assembler */
verbose_only( StringList asmOutput(alloc); )
verbose_only( _outputCache = &asmOutput; )
beginAssembly(frag);
if (error())
return;
//_logc->printf("recompile trigger %X kind %d\n", (int)frag, frag->kind);
verbose_only( if (anyVerb) {
_logc->printf("=== Translating LIR fragments into assembly:\n");
})
// now the the main trunk
verbose_only( RefBuf b; )
verbose_only( if (anyVerb) {
_logc->printf("=== -- Compile trunk %s: begin\n", printer->formatAddr(&b, frag));
})
// Used for debug printing, if needed
debug_only(ValidateReader *validate = NULL;)
verbose_only(
ReverseLister *pp_init = NULL;
ReverseLister *pp_after_sf = NULL;
)
// The LIR passes through these filters as listed in this
// function, viz, top to bottom.
// set up backwards pipeline: assembler <- StackFilter <- LirReader
LirFilter* lir = new (alloc) LirReader(frag->lastIns);
#ifdef DEBUG
// VALIDATION
validate = new (alloc) ValidateReader(lir);
lir = validate;
#endif
// INITIAL PRINTING
verbose_only( if (_logc->lcbits & LC_ReadLIR) {
pp_init = new (alloc) ReverseLister(lir, alloc, frag->lirbuf->printer, _logc,
"Initial LIR");
lir = pp_init;
})
// STACKFILTER
if (optimize) {
StackFilter* stackfilter = new (alloc) StackFilter(lir, alloc, frag->lirbuf->sp);
lir = stackfilter;
}
verbose_only( if (_logc->lcbits & LC_AfterSF) {
pp_after_sf = new (alloc) ReverseLister(lir, alloc, frag->lirbuf->printer, _logc,
"After StackFilter");
lir = pp_after_sf;
})
assemble(frag, lir);
// If we were accumulating debug info in the various ReverseListers,
// call finish() to emit whatever contents they have accumulated.
verbose_only(
if (pp_init) pp_init->finish();
if (pp_after_sf) pp_after_sf->finish();
)
verbose_only( if (anyVerb) {
_logc->printf("=== -- Compile trunk %s: end\n", printer->formatAddr(&b, frag));
})
endAssembly(frag);