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<!DOCTYPE html>
<html>
<head>
<meta charset="utf-8"/>
<title>Test Report</title>
<link href="style.css" rel="stylesheet" type="text/css"/></head>
<body onLoad="init()">
<script>/* This Source Code Form is subject to the terms of the Mozilla Public
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resulttable.parentElement.insertBefore(showhideall, resulttable);
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<h1></h1>
<p>Report generated on 2022-03-18 19:48 GMT by <a href="https://pypi.python.org/pypi/riscof">riscof</a> v</p>
<h2>Environment</h2>
<table id="environment">
<tr>
<td>Riscof Version</td>
<td>1.23.4</td></tr>
<tr>
<td>Riscv-arch-test Version/Commit Id</td>
<td>2.7.1</td></tr>
<tr>
<td>DUT</td>
<td>nox</td></tr>
<tr>
<td>Reference</td>
<td>sail c simulator</td></tr>
<tr>
<td>ISA</td>
<td>RV32I</td></tr>
<tr>
<td>User Spec Version</td>
<td>2.3</td></tr>
<tr>
<td>Privilege Spec Version</td>
<td>1.11</td></tr>
</table>
<h2>Yaml</h2>
<table id="yaml-table">
<thead id="yaml-table-head">
<tr>
<th col="yname">Name</th>
</tr>
</thead>
<tbody>
<tr>
<td class="col-yname">/test/riscof_compliance/riscof_work/nox_isa_checked.yaml</td></tr>
<tr>
<td class="extra" colspan="1">
<div class="log">hart_ids: [0]
hart0:
ISA: RV32I
physical_addr_sz: 32
User_Spec_Version: '2.3'
Privilege_Spec_Version: '1.11'
hw_data_misaligned_support: false
supported_xlen:
- 32
misa:
reset-val: 0x40000100
rv32:
accessible: true
mxl:
implemented: true
type:
warl:
dependency_fields: []
legal:
- mxl[1:0] in [0x1]
wr_illegal:
- Unchanged
description: Encodes the native base integer ISA width.
shadow:
shadow_type: rw
msb: 31
lsb: 30
extensions:
implemented: true
type:
warl:
dependency_fields: []
legal:
- extensions[25:0] bitmask [0x0001104, 0x0000000]
wr_illegal:
- Unchanged
description: Encodes the presence of the standard extensions, with
a single bit per letter of the alphabet.
shadow:
shadow_type: rw
msb: 25
lsb: 0
fields:
- extensions
- mxl
-
-
- 26
- 29
description: misa is a read-write register reporting the ISA supported by
the hart.
address: 769
priv_mode: M
rv64:
accessible: false
pmp_granularity: 0
custom_exceptions:
custom_interrupts:
mstatus:
rv32:
accessible: true
fields:
- uie
- sie
- mie
- upie
- spie
- mpie
- spp
- mpp
- fs
- xs
- mprv
- sum
- mxr
- tvm
- tw
- tsr
- sd
-
-
- 2
-
- 6
-
- 9
- 10
-
- 23
- 30
uie:
implemented: false
description: Stores the state of the user mode interrupts.
shadow:
shadow_type: rw
msb: 0
lsb: 0
sie:
implemented: false
description: Stores the state of the supervisor mode interrupts.
shadow:
shadow_type: rw
msb: 1
lsb: 1
mie:
implemented: true
description: Stores the state of the machine mode interrupts.
shadow:
shadow_type: rw
msb: 3
lsb: 3
type:
wlrl:
- 0:1
upie:
implemented: false
description: Stores the state of the user mode interrupts prior to
the trap.
shadow:
shadow_type: rw
msb: 4
lsb: 4
spie:
implemented: false
description: Stores the state of the supervisor mode interrupts prior
to the trap.
shadow:
shadow_type: rw
msb: 5
lsb: 5
mpie:
implemented: true
description: Stores the state of the machine mode interrupts prior
to the trap.
shadow:
shadow_type: rw
msb: 7
lsb: 7
type:
wlrl:
- 0:1
spp:
implemented: false
description: Stores the previous priority mode for supervisor.
shadow:
shadow_type: rw
msb: 8
lsb: 8
mpp:
implemented: true
description: Stores the previous priority mode for machine.
shadow:
shadow_type: rw
msb: 12
lsb: 11
type: {ro_constant: 0}
fs:
implemented: false
description: Encodes the status of the floating-point unit, including
the CSR fcsr and floating-point data registers.
shadow:
shadow_type: rw
msb: 14
lsb: 13
xs:
implemented: false
description: Encodes the status of additional user-mode extensions
and associated state.
shadow:
shadow_type: rw
msb: 16
lsb: 15
mprv:
implemented: false
description: Modifies the privilege level at which loads and stores
execute in all privilege modes.
shadow:
shadow_type: rw
msb: 17
lsb: 17
sum:
implemented: false
description: Modifies the privilege with which S-mode loads and stores
access virtual memory.
shadow:
shadow_type: rw
msb: 18
lsb: 18
mxr:
implemented: false
description: Modifies the privilege with which loads access virtual
memory.
shadow:
shadow_type: rw
msb: 19
lsb: 19
tvm:
implemented: false
description: Supports intercepting supervisor virtual-memory management
operations.
shadow:
shadow_type: rw
msb: 20
lsb: 20
tw:
implemented: false
description: Supports intercepting the WFI instruction.
shadow:
shadow_type: rw
msb: 21
lsb: 21
tsr:
implemented: false
description: Supports intercepting the supervisor exception return
instruction.
shadow:
shadow_type: rw
msb: 22
lsb: 22
sd:
implemented: false
description: Read-only bit that summarizes whether either the FS field
or XS field signals the presence of some dirty state.
shadow:
shadow_type: rw
msb: 31
lsb: 31
rv64:
accessible: false
description: The mstatus register keeps track of and controls the hart’s current
operating state.
address: 768
priv_mode: M
reset-val: 0
mstatush:
rv32:
accessible: true
fields:
- sbe
- mbe
- gva
- mpv
-
-
- 0
- 3
-
- 8
- 31
mpv:
implemented: false
description: Stores the state of the user mode interrupts.
shadow:
shadow_type: rw
msb: 7
lsb: 7
gva:
implemented: false
description: Stores the state of the supervisor mode interrupts.
shadow:
shadow_type: rw
msb: 6
lsb: 6
mbe:
implemented: false
description: control the endianness of memory accesses other than
instruction fetches for machine mode
shadow:
shadow_type: rw
msb: 5
lsb: 5
sbe:
implemented: false
description: control the endianness of memory accesses other than
instruction fetches for supervisor mode
shadow:
shadow_type: rw
msb: 4
lsb: 4
rv64:
accessible: false
description: The mstatush register keeps track of and controls the hart’s
current operating state.
address: 768
priv_mode: M
reset-val: 0
mvendorid:
rv32:
accessible: true
fields: []
shadow:
shadow_type: rw
msb: 31
lsb: 0
type:
ro_constant: 0
rv64:
accessible: false
description: 32-bit read-only register providing the JEDEC manufacturer ID
of the provider of the core.
address: 3857
priv_mode: M
reset-val: 0
marchid:
rv32:
accessible: true
fields: []
shadow:
shadow_type: rw
msb: 31
lsb: 0
type:
ro_constant: 0
rv64:
accessible: false
description: MXLEN-bit read-only register encoding the base microarchitecture
of the hart.
address: 3858
priv_mode: M
reset-val: 0
mimpid:
rv32:
accessible: true
fields: []
shadow:
shadow_type: rw
msb: 31
lsb: 0
type:
ro_constant: 0
rv64:
accessible: false
description: Provides a unique encoding of the version of the processor implementation.
address: 3859
priv_mode: M
reset-val: 0
mhartid:
rv32:
accessible: true
fields: []
shadow:
shadow_type: rw
msb: 31
lsb: 0
type:
ro_constant: 0
rv64:
accessible: false
description: MXLEN-bit read-only register containing the integer ID of the
hardware thread running the code.
address: 3860
priv_mode: M
reset-val: 0
mtvec:
rv32:
accessible: true
fields:
- mode
- base
base:
implemented: true
description: Vector base address.
shadow:
shadow_type: rw
msb: 31
lsb: 2
type:
warl:
dependency_fields: []
legal:
- base[29:0] bitmask [0x3FFFFFFF, 0x00000000]
wr_illegal:
- Unchanged
mode:
implemented: true
description: Vector mode.
shadow:
shadow_type: rw
msb: 1
lsb: 0
type:
warl:
dependency_fields: []
legal:
- mode[1:0] in [0x0,0x1]
wr_illegal:
- Unchanged
rv64:
accessible: false
description: MXLEN-bit read/write register that holds trap vector configuration.
address: 773
priv_mode: M
reset-val: 0
mideleg:
rv32:
accessible: false
rv64:
accessible: false
description: Machine Interrupt delegation Register.
address: 771
priv_mode: M
reset-val: 0
medeleg:
rv32:
accessible: false
rv64:
accessible: false
description: Machine Exception delegation Register.
address: 770
priv_mode: M
reset-val: 0
mip:
rv32:
accessible: true
fields:
- usip
- ssip
- vssip
- msip
- utip
- stip
- vstip
- mtip
- ueip
- seip
- vseip
- meip
- sgeip
-
-
- 13
- 31
usip:
implemented: false
description: User Software Interrupt Pending.
shadow:
shadow_type: rw
msb: 0
lsb: 0
ssip:
implemented: false
description: Supervisor Software Interrupt Pending.
shadow:
shadow_type: rw
msb: 1
lsb: 1
vssip:
implemented: false
description: VS-level Software Interrupt Pending.
shadow:
shadow_type: rw
msb: 2
lsb: 2
msip:
implemented: true
description: Machine Software Interrupt Pending.
shadow:
shadow_type: rw
msb: 3
lsb: 3
type:
ro_variable: true
utip:
implemented: false
description: User Timer Interrupt Pending.
shadow:
shadow_type: rw
msb: 4
lsb: 4
stip:
implemented: false
description: Supervisor Timer Interrupt Pending.
shadow:
shadow_type: rw
msb: 5
lsb: 5
vstip:
implemented: false
description: VS-level Timer Interrupt Pending.
shadow:
shadow_type: rw
msb: 6
lsb: 6
mtip:
implemented: true
description: Machine Timer Interrupt Pending.
shadow:
shadow_type: rw
msb: 7
lsb: 7
type:
ro_variable: true
ueip:
implemented: false
description: User External Interrupt Pending.
shadow:
shadow_type: rw
msb: 8
lsb: 8
seip:
implemented: false
description: Supervisor External Interrupt Pending.
shadow:
shadow_type: rw
msb: 9
lsb: 9
vseip:
implemented: false
description: VS-level External Interrupt Pending.
shadow:
shadow_type: rw
msb: 10
lsb: 10
meip:
implemented: true
description: Machine External Interrupt Pending.
shadow:
shadow_type: rw
msb: 11
lsb: 11
type:
ro_variable: true
sgeip:
implemented: false
description: HS-level External Interrupt Pending.
shadow:
shadow_type: rw
msb: 12
lsb: 12
rv64:
accessible: false
description: The mip register is an MXLEN-bit read/write register containing
information on pending interrupts.
address: 836
priv_mode: M
reset-val: 0
hie:
rv32:
accessible: false
rv64:
accessible: false
description: The hie register is an HSXLEN-bit read/write register containing
interrupt enable bits.
address: 0x604
priv_mode: H
reset-val: 0
mie:
rv32:
accessible: true
fields:
- usie
- ssie
- vssie
- msie
- utie
- stie
- vstie
- mtie
- ueie
- seie
- vseie
- meie
- sgeie
-
-
- 13
- 31
usie:
implemented: false
description: User Software Interrupt enable.
shadow:
shadow_type: rw
msb: 0
lsb: 0
ssie:
implemented: false
description: Supervisor Software Interrupt enable.
shadow:
shadow_type: rw
msb: 1
lsb: 1
vssie:
implemented: false
description: VS-level Software Interrupt enable.
shadow:
shadow_type: rw
msb: 2
lsb: 2
msie:
implemented: true
description: Machine Software Interrupt enable.
shadow:
shadow_type: rw
msb: 3
lsb: 3
type:
wlrl:
- 0x0:0x1
utie:
implemented: false
description: User Timer Interrupt enable.
shadow:
shadow_type: rw
msb: 4
lsb: 4
stie:
implemented: false
description: Supervisor Timer Interrupt enable.
shadow:
shadow_type: rw
msb: 5
lsb: 5
vstie:
implemented: false
description: VS-level Timer Interrupt enable.
shadow:
shadow_type: rw
msb: 6
lsb: 6
mtie:
implemented: true
description: Machine Timer Interrupt enable.
shadow:
shadow_type: rw
msb: 7
lsb: 7
type:
wlrl:
- 0:1
ueie:
implemented: false
description: User External Interrupt enable.
shadow:
shadow_type: rw
msb: 8
lsb: 8
seie:
implemented: false
description: Supervisor External Interrupt enable.
shadow:
shadow_type: rw
msb: 9
lsb: 9
vseie:
implemented: false
description: VS-level External Interrupt enable.
shadow:
shadow_type: rw
msb: 10
lsb: 10
meie:
implemented: true
description: Machine External Interrupt enable.
shadow:
shadow_type: rw
msb: 11
lsb: 11
type:
wlrl:
- 0:1
sgeie:
implemented: false
description: HS-level External Interrupt enable.
shadow:
shadow_type: rw
msb: 12
lsb: 12
rv64:
accessible: false
description: The mie register is an MXLEN-bit read/write register containing
interrupt enable bits.
address: 772
priv_mode: M
reset-val: 0
mscratch:
rv32:
accessible: true
fields: []
shadow:
shadow_type: rw
msb: 31
lsb: 0
type:
warl:
dependency_fields: []
legal:
- mscratch[31:0] in [0x00000000:0xFFFFFFFF]
wr_illegal:
- unchanged
rv64:
accessible: false
description: The mscratch register is an MXLEN-bit read/write register dedicated
for use by machine mode.
address: 832
priv_mode: M