From 05e27138aef5dea54576d2916d92d2f7bd1f3956 Mon Sep 17 00:00:00 2001 From: Nguyen Anh Quynh Date: Mon, 10 Mar 2014 11:58:57 +0800 Subject: [PATCH] core: add Sparc arch --- COMPILE.TXT | 12 +- MCInst.h | 1 + Makefile | 20 +- README | 3 +- arch/Sparc/Sparc.h | 63 + arch/Sparc/SparcDisassembler.c | 471 +++ arch/Sparc/SparcDisassembler.h | 19 + arch/Sparc/SparcGenAsmWriter.inc | 1251 ++++++++ arch/Sparc/SparcGenDisassemblerTables.inc | 2016 +++++++++++++ arch/Sparc/SparcGenInstrInfo.inc | 511 ++++ arch/Sparc/SparcGenRegisterInfo.inc | 462 +++ arch/Sparc/SparcGenSubtargetInfo.inc | 27 + arch/Sparc/SparcInstPrinter.c | 266 ++ arch/Sparc/SparcInstPrinter.h | 15 + arch/Sparc/SparcMapping.c | 3179 +++++++++++++++++++++ arch/Sparc/SparcMapping.h | 22 + arch/Sparc/SparcModule.c | 54 + config.mk | 3 + cs.c | 25 +- include/capstone.h | 5 + tests/Makefile | 5 +- tests/test.c | 9 + tests/test_detail.c | 9 + tests/test_sparc.c | 135 + 24 files changed, 8572 insertions(+), 11 deletions(-) create mode 100644 arch/Sparc/Sparc.h create mode 100644 arch/Sparc/SparcDisassembler.c create mode 100644 arch/Sparc/SparcDisassembler.h create mode 100644 arch/Sparc/SparcGenAsmWriter.inc create mode 100644 arch/Sparc/SparcGenDisassemblerTables.inc create mode 100644 arch/Sparc/SparcGenInstrInfo.inc create mode 100644 arch/Sparc/SparcGenRegisterInfo.inc create mode 100644 arch/Sparc/SparcGenSubtargetInfo.inc create mode 100644 arch/Sparc/SparcInstPrinter.c create mode 100644 arch/Sparc/SparcInstPrinter.h create mode 100644 arch/Sparc/SparcMapping.c create mode 100644 arch/Sparc/SparcMapping.h create mode 100644 arch/Sparc/SparcModule.c create mode 100644 tests/test_sparc.c diff --git a/COMPILE.TXT b/COMPILE.TXT index a8b9855e7d..2d32ba2351 100644 --- a/COMPILE.TXT +++ b/COMPILE.TXT @@ -7,12 +7,14 @@ Capstone requires no prerequisite packages, so it is easy to compile & install. (0) Tailor Capstone to your need. - Out of 5 archtitectures supported by Capstone (Arm, Arm64, Mips, PPC & X86), - if you just need several selected archs, you can choose which ones you want - to compile in by modifying config.mk before going to next steps. + Out of 6 archtitectures supported by Capstone (Arm, Arm64, Mips, PPC, Sparc & + X86), if you just need several selected archs, you can choose which ones you + want to compile in by modifying "config.mk" before going to next steps. - By default, all 5 architectures are compiled. + By default, all 6 architectures are compiled. + Capstone also supports "diet" engine to minimize the binaries for embedding + purpose. See docs/README for further instructions. (1) Compile from source @@ -54,6 +56,8 @@ Capstone requires no prerequisite packages, so it is easy to compile & install. /usr/include/capstone/arm64.h /usr/include/capstone/mips.h /usr/include/capstone/ppc.h + /usr/include/capstone/sparc.h + /usr/include/capstone/diet.h /usr/lib/libcapstone.so (for Linux/*nix), or /usr/lib/libcapstone.dylib (OSX) /usr/lib/libcapstone.a diff --git a/MCInst.h b/MCInst.h index 87fb5a1bd2..ed5db3ce35 100644 --- a/MCInst.h +++ b/MCInst.h @@ -128,6 +128,7 @@ typedef struct cs_insn_flat { cs_arm arm; // ARM architecture (including Thumb/Thumb2) cs_mips mips; // MIPS architecture cs_ppc ppc; // PowerPC architecture + cs_sparc sparc; // PowerPC architecture }; } cs_insn_flat; diff --git a/Makefile b/Makefile index f5143c2180..49ecdaa91c 100644 --- a/Makefile +++ b/Makefile @@ -114,6 +114,23 @@ ifneq (,$(findstring powerpc,$(CAPSTONE_ARCHS))) endif +DEP_SPARC = +DEP_SPARC += arch/Sparc/SparcGenAsmWriter.inc +DEP_SPARC += arch/Sparc/SparcGenInstrInfo.inc +DEP_SPARC += arch/Sparc/SparcGenSubtargetInfo.inc +DEP_SPARC += arch/Sparc/SparcGenDisassemblerTables.inc +DEP_SPARC += arch/Sparc/SparcGenRegisterInfo.inc + +LIBOBJ_SPARC = +ifneq (,$(findstring sparc,$(CAPSTONE_ARCHS))) + CFLAGS += -DCAPSTONE_HAS_SPARC + LIBOBJ_SPARC += arch/Sparc/SparcDisassembler.o + LIBOBJ_SPARC += arch/Sparc/SparcInstPrinter.o + LIBOBJ_SPARC += arch/Sparc/SparcMapping.o + LIBOBJ_SPARC += arch/Sparc/SparcModule.o +endif + + DEP_X86 = DEP_X86 += arch/X86/X86GenAsmWriter.inc DEP_X86 += arch/X86/X86GenAsmWriter1.inc @@ -134,7 +151,7 @@ endif LIBOBJ = LIBOBJ += cs.o utils.o SStream.o MCInstrDesc.o MCRegisterInfo.o -LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_ARM64) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_X86) +LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_ARM64) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_SPARC) $(LIBOBJ_X86) LIBOBJ += MCInst.o @@ -202,6 +219,7 @@ $(LIBOBJ_ARM): $(DEP_ARM) $(LIBOBJ_ARM64): $(DEP_ARM64) $(LIBOBJ_MIPS): $(DEP_MIPS) $(LIBOBJ_PPC): $(DEP_PPC) +$(LIBOBJ_SPARC): $(DEP_SPARC) $(LIBOBJ_X86): $(DEP_X86) # auto-generate include/diet.h diff --git a/README b/README index 1c40b1ad90..61ea32d8ae 100644 --- a/README +++ b/README @@ -4,7 +4,8 @@ disasm engine for binary analysis and reversing in the security community. Created by Nguyen Anh Quynh, then developed and maintained by a small community, Capstone offers some unparalleled features: -- Support multiple hardware architectures: ARM, ARM64 (ARMv8), Mips, PPC & X86. +- Support multiple hardware architectures: ARM, ARM64 (ARMv8), Mips, PPC, Sparc + and X86. - Having clean/simple/lightweight/intuitive architecture-neutral API. diff --git a/arch/Sparc/Sparc.h b/arch/Sparc/Sparc.h new file mode 100644 index 0000000000..01331e76ad --- /dev/null +++ b/arch/Sparc/Sparc.h @@ -0,0 +1,63 @@ +//===-- Sparc.h - Top-level interface for Sparc representation --*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the entry points for global functions defined in the LLVM +// Sparc back-end. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2014 */ + +#ifndef CS_SPARC_TARGET_SPARC_H +#define CS_SPARC_TARGET_SPARC_H + +#include "../../include/sparc.h" + +inline static const char *SPARCCondCodeToString(sparc_cc CC) +{ + switch (CC) { + default: return NULL; // unreachable + case SPARC_CC_ICC_A: return "a"; + case SPARC_CC_ICC_N: return "n"; + case SPARC_CC_ICC_NE: return "ne"; + case SPARC_CC_ICC_E: return "e"; + case SPARC_CC_ICC_G: return "g"; + case SPARC_CC_ICC_LE: return "le"; + case SPARC_CC_ICC_GE: return "ge"; + case SPARC_CC_ICC_L: return "l"; + case SPARC_CC_ICC_GU: return "gu"; + case SPARC_CC_ICC_LEU: return "leu"; + case SPARC_CC_ICC_CC: return "cc"; + case SPARC_CC_ICC_CS: return "cs"; + case SPARC_CC_ICC_POS: return "pos"; + case SPARC_CC_ICC_NEG: return "neg"; + case SPARC_CC_ICC_VC: return "vc"; + case SPARC_CC_ICC_VS: return "vs"; + + case SPARC_CC_FCC_A: return "a"; + case SPARC_CC_FCC_N: return "n"; + case SPARC_CC_FCC_U: return "u"; + case SPARC_CC_FCC_G: return "g"; + case SPARC_CC_FCC_UG: return "ug"; + case SPARC_CC_FCC_L: return "l"; + case SPARC_CC_FCC_UL: return "ul"; + case SPARC_CC_FCC_LG: return "lg"; + case SPARC_CC_FCC_NE: return "ne"; + case SPARC_CC_FCC_E: return "e"; + case SPARC_CC_FCC_UE: return "ue"; + case SPARC_CC_FCC_GE: return "ge"; + case SPARC_CC_FCC_UGE: return "uge"; + case SPARC_CC_FCC_LE: return "le"; + case SPARC_CC_FCC_ULE: return "ule"; + case SPARC_CC_FCC_O: return "o"; + } +} + +#endif diff --git a/arch/Sparc/SparcDisassembler.c b/arch/Sparc/SparcDisassembler.c new file mode 100644 index 0000000000..dbde804e19 --- /dev/null +++ b/arch/Sparc/SparcDisassembler.c @@ -0,0 +1,471 @@ +//===------ SparcDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2014 */ + +#include // DEBUG +#include +#include + +#include "../../cs_priv.h" + +#include "../../SubtargetFeature.h" +#include "../../MCInst.h" +#include "../../MCInstrDesc.h" +#include "../../MCFixedLenDisassembler.h" +#include "../../MCRegisterInfo.h" +#include "../../MCDisassembler.h" +#include "../../MathExtras.h" + + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_ENUM +#include "SparcGenRegisterInfo.inc" +static const unsigned IntRegDecoderTable[] = { + SP_G0, SP_G1, SP_G2, SP_G3, + SP_G4, SP_G5, SP_G6, SP_G7, + SP_O0, SP_O1, SP_O2, SP_O3, + SP_O4, SP_O5, SP_O6, SP_O7, + SP_L0, SP_L1, SP_L2, SP_L3, + SP_L4, SP_L5, SP_L6, SP_L7, + SP_I0, SP_I1, SP_I2, SP_I3, + SP_I4, SP_I5, SP_I6, SP_I7 +}; + +static const unsigned FPRegDecoderTable[] = { + SP_F0, SP_F1, SP_F2, SP_F3, + SP_F4, SP_F5, SP_F6, SP_F7, + SP_F8, SP_F9, SP_F10, SP_F11, + SP_F12, SP_F13, SP_F14, SP_F15, + SP_F16, SP_F17, SP_F18, SP_F19, + SP_F20, SP_F21, SP_F22, SP_F23, + SP_F24, SP_F25, SP_F26, SP_F27, + SP_F28, SP_F29, SP_F30, SP_F31 +}; + +static const unsigned DFPRegDecoderTable[] = { + SP_D0, SP_D16, SP_D1, SP_D17, + SP_D2, SP_D18, SP_D3, SP_D19, + SP_D4, SP_D20, SP_D5, SP_D21, + SP_D6, SP_D22, SP_D7, SP_D23, + SP_D8, SP_D24, SP_D9, SP_D25, + SP_D10, SP_D26, SP_D11, SP_D27, + SP_D12, SP_D28, SP_D13, SP_D29, + SP_D14, SP_D30, SP_D15, SP_D31 +}; + +static const unsigned QFPRegDecoderTable[] = { + SP_Q0, SP_Q8, ~0U, ~0U, + SP_Q1, SP_Q9, ~0U, ~0U, + SP_Q2, SP_Q10, ~0U, ~0U, + SP_Q3, SP_Q11, ~0U, ~0U, + SP_Q4, SP_Q12, ~0U, ~0U, + SP_Q5, SP_Q13, ~0U, ~0U, + SP_Q6, SP_Q14, ~0U, ~0U, + SP_Q7, SP_Q15, ~0U, ~0U +}; + +static const unsigned FCCRegDecoderTable[] = { + SP_FCC0, SP_FCC1, SP_FCC2, SP_FCC3 +}; + +static uint64_t getFeatureBits(int mode) +{ + // support everything + return (uint64_t)-1; +} + +static DecodeStatus DecodeIntRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) +{ + unsigned Reg; + + if (RegNo > 31) + return MCDisassembler_Fail; + + Reg = IntRegDecoderTable[RegNo]; + MCInst_addOperand(Inst, MCOperand_CreateReg(Reg)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeI64RegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) +{ + unsigned Reg; + + if (RegNo > 31) + return MCDisassembler_Fail; + + Reg = IntRegDecoderTable[RegNo]; + MCInst_addOperand(Inst, MCOperand_CreateReg(Reg)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeFPRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) +{ + unsigned Reg; + + if (RegNo > 31) + return MCDisassembler_Fail; + + Reg = FPRegDecoderTable[RegNo]; + MCInst_addOperand(Inst, MCOperand_CreateReg(Reg)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeDFPRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) +{ + unsigned Reg; + + if (RegNo > 31) + return MCDisassembler_Fail; + + Reg = DFPRegDecoderTable[RegNo]; + MCInst_addOperand(Inst, MCOperand_CreateReg(Reg)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeQFPRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) +{ + unsigned Reg; + + if (RegNo > 31) + return MCDisassembler_Fail; + + Reg = QFPRegDecoderTable[RegNo]; + if (Reg == ~0U) + return MCDisassembler_Fail; + + MCInst_addOperand(Inst, MCOperand_CreateReg(Reg)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeFCCRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) +{ + if (RegNo > 3) + return MCDisassembler_Fail; + + MCInst_addOperand(Inst, MCOperand_CreateReg(FCCRegDecoderTable[RegNo])); + + return MCDisassembler_Success; +} + + +static DecodeStatus DecodeLoadInt(MCInst *Inst, unsigned insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeLoadFP(MCInst *Inst, unsigned insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeLoadDFP(MCInst *Inst, unsigned insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeLoadQFP(MCInst *Inst, unsigned insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeStoreInt(MCInst *Inst, unsigned insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeStoreFP(MCInst *Inst, unsigned insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeStoreDFP(MCInst *Inst, unsigned insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeStoreQFP(MCInst *Inst, unsigned insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeCall(MCInst *Inst, unsigned insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeSIMM13(MCInst *Inst, unsigned insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeJMPL(MCInst *Inst, unsigned insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeReturn(MCInst *MI, unsigned insn, uint64_t Address, + const void *Decoder); + +#define GET_SUBTARGETINFO_ENUM +#include "SparcGenSubtargetInfo.inc" +#include "SparcGenDisassemblerTables.inc" + +/// readInstruction - read four bytes and return 32 bit word. +static DecodeStatus readInstruction32(unsigned char *code, size_t len, uint32_t *Insn) +{ + uint8_t Bytes[4]; + + if (len < 4) + // not enough data + return MCDisassembler_Fail; + + memcpy(Bytes, code, 4); + + // Encoded as a big-endian 32-bit word in the stream. + *Insn = (Bytes[3] << 0) | + (Bytes[2] << 8) | + (Bytes[1] << 16) | + (Bytes[0] << 24); + + return MCDisassembler_Success; +} + +bool Sparc_getInstruction(csh ud, unsigned char *code, size_t code_len, MCInst *MI, + uint16_t *size, uint64_t address, void *info) +{ + uint32_t Insn; + DecodeStatus Result; + + Result = readInstruction32(code, code_len, &Insn); + if (Result == MCDisassembler_Fail) + return MCDisassembler_Fail; + + Result = decodeInstruction_4(DecoderTableSparc32, MI, Insn, address, + (MCRegisterInfo *)info, 0); + if (Result != MCDisassembler_Fail) { + *size = 4; + return Result; + } + + return MCDisassembler_Fail; +} + +typedef DecodeStatus (*DecodeFunc)(MCInst *MI, unsigned insn, uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeMem(MCInst *MI, unsigned insn, uint64_t Address, + const void *Decoder, + bool isLoad, DecodeFunc DecodeRD) +{ + DecodeStatus status; + unsigned rd = fieldFromInstruction_4(insn, 25, 5); + unsigned rs1 = fieldFromInstruction_4(insn, 14, 5); + bool isImm = fieldFromInstruction_4(insn, 13, 1); + unsigned rs2 = 0; + unsigned simm13 = 0; + + if (isImm) + simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13); + else + rs2 = fieldFromInstruction_4(insn, 0, 5); + + if (isLoad) { + status = DecodeRD(MI, rd, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + } + + // Decode rs1. + status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + + // Decode imm|rs2. + if (isImm) + MCInst_addOperand(MI, MCOperand_CreateImm(simm13)); + else { + status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + } + + if (!isLoad) { + status = DecodeRD(MI, rd, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + } + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeLoadInt(MCInst *Inst, unsigned insn, uint64_t Address, + const void *Decoder) +{ + return DecodeMem(Inst, insn, Address, Decoder, true, + DecodeIntRegsRegisterClass); +} + +static DecodeStatus DecodeLoadFP(MCInst *Inst, unsigned insn, uint64_t Address, + const void *Decoder) +{ + return DecodeMem(Inst, insn, Address, Decoder, true, + DecodeFPRegsRegisterClass); +} + +static DecodeStatus DecodeLoadDFP(MCInst *Inst, unsigned insn, uint64_t Address, + const void *Decoder) +{ + return DecodeMem(Inst, insn, Address, Decoder, true, + DecodeDFPRegsRegisterClass); +} + +static DecodeStatus DecodeLoadQFP(MCInst *Inst, unsigned insn, uint64_t Address, + const void *Decoder) +{ + return DecodeMem(Inst, insn, Address, Decoder, true, + DecodeQFPRegsRegisterClass); +} + +static DecodeStatus DecodeStoreInt(MCInst *Inst, unsigned insn, + uint64_t Address, const void *Decoder) +{ + return DecodeMem(Inst, insn, Address, Decoder, false, + DecodeIntRegsRegisterClass); +} + +static DecodeStatus DecodeStoreFP(MCInst *Inst, unsigned insn, uint64_t Address, + const void *Decoder) +{ + return DecodeMem(Inst, insn, Address, Decoder, false, + DecodeFPRegsRegisterClass); +} + +static DecodeStatus DecodeStoreDFP(MCInst *Inst, unsigned insn, + uint64_t Address, const void *Decoder) +{ + return DecodeMem(Inst, insn, Address, Decoder, false, + DecodeDFPRegsRegisterClass); +} + +static DecodeStatus DecodeStoreQFP(MCInst *Inst, unsigned insn, + uint64_t Address, const void *Decoder) +{ + return DecodeMem(Inst, insn, Address, Decoder, false, + DecodeQFPRegsRegisterClass); +} + +/* +static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, + uint64_t Address, uint64_t Offset, + uint64_t Width, MCInst *MI, + const void *Decoder) +{ + const MCDisassembler *Dis = static_cast(Decoder); + return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch, + Offset, Width); +} +*/ + +static DecodeStatus DecodeCall(MCInst *MI, unsigned insn, + uint64_t Address, const void *Decoder) +{ + unsigned tgt = fieldFromInstruction_4(insn, 0, 30); + tgt <<= 2; + + /* + if (!tryAddingSymbolicOperand(tgt+Address, false, Address, 0, 30, MI, Decoder)) + */ + + MCInst_addOperand(MI, MCOperand_CreateImm(tgt)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeSIMM13(MCInst *MI, unsigned insn, + uint64_t Address, const void *Decoder) +{ + unsigned tgt = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13); + + MCInst_addOperand(MI, MCOperand_CreateImm(tgt)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeJMPL(MCInst *MI, unsigned insn, uint64_t Address, + const void *Decoder) +{ + DecodeStatus status; + unsigned rd = fieldFromInstruction_4(insn, 25, 5); + unsigned rs1 = fieldFromInstruction_4(insn, 14, 5); + unsigned isImm = fieldFromInstruction_4(insn, 13, 1); + unsigned rs2 = 0; + unsigned simm13 = 0; + + if (isImm) + simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13); + else + rs2 = fieldFromInstruction_4(insn, 0, 5); + + // Decode RD. + status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + + // Decode RS1. + status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + + // Decode RS1 | SIMM13. + if (isImm) + MCInst_addOperand(MI, MCOperand_CreateImm(simm13)); + else { + status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + } + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeReturn(MCInst *MI, unsigned insn, uint64_t Address, + const void *Decoder) +{ + DecodeStatus status; + unsigned rs1 = fieldFromInstruction_4(insn, 14, 5); + unsigned isImm = fieldFromInstruction_4(insn, 13, 1); + unsigned rs2 = 0; + unsigned simm13 = 0; + if (isImm) + simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13); + else + rs2 = fieldFromInstruction_4(insn, 0, 5); + + // Decode RS1. + status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + + // Decode RS2 | SIMM13. + if (isImm) + MCInst_addOperand(MI, MCOperand_CreateImm(simm13)); + else { + status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + } + + return MCDisassembler_Success; +} + +void Sparc_init(MCRegisterInfo *MRI) +{ + /* + InitMCRegisterInfo(SparcRegDesc, 119, RA, PC, + SparcMCRegisterClasses, 8, + SparcRegUnitRoots, + 86, + SparcRegDiffLists, + SparcRegStrings, + SparcSubRegIdxLists, + 7, + SparcSubRegIdxRanges, + SparcRegEncodingTable); + */ + + MCRegisterInfo_InitMCRegisterInfo(MRI, SparcRegDesc, 119, + 0, 0, + SparcMCRegisterClasses, 8, + 0, 0, + SparcRegDiffLists, + 0, + SparcSubRegIdxLists, 7, + 0); +} + diff --git a/arch/Sparc/SparcDisassembler.h b/arch/Sparc/SparcDisassembler.h new file mode 100644 index 0000000000..bafa2307e4 --- /dev/null +++ b/arch/Sparc/SparcDisassembler.h @@ -0,0 +1,19 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2014 */ + +#ifndef CS_SPARCDISASSEMBLER_H +#define CS_SPARCDISASSEMBLER_H + +#include + +#include "../../include/capstone.h" +#include "../../MCRegisterInfo.h" +#include "../../MCInst.h" + +void Sparc_init(MCRegisterInfo *MRI); + +bool Sparc_getInstruction(csh ud, const uint8_t *code, size_t code_len, + MCInst *instr, uint16_t *size, uint64_t address, void *info); + +#endif + diff --git a/arch/Sparc/SparcGenAsmWriter.inc b/arch/Sparc/SparcGenAsmWriter.inc new file mode 100644 index 0000000000..004deefdf4 --- /dev/null +++ b/arch/Sparc/SparcGenAsmWriter.inc @@ -0,0 +1,1251 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*Assembly Writer Source Fragment *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2014 */ + +#include // debug +#include + + +/// printInstruction - This method is automatically generated by tablegen +/// from the instruction set description. +static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) +{ + static const uint32_t OpInfo[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 2452U, // DBG_VALUE + 0U, // REG_SEQUENCE + 0U, // COPY + 2445U, // BUNDLE + 2462U, // LIFETIME_START + 2432U, // LIFETIME_END + 0U, // STACKMAP + 0U, // PATCHPOINT + 4688U, // ADDCCri + 4688U, // ADDCCrr + 5925U, // ADDCri + 5925U, // ADDCrr + 4772U, // ADDEri + 4772U, // ADDErr + 4786U, // ADDXC + 4678U, // ADDXCCC + 4808U, // ADDXri + 4808U, // ADDXrr + 4808U, // ADDri + 4808U, // ADDrr + 74166U, // ADJCALLSTACKDOWN + 74185U, // ADJCALLSTACKUP + 5497U, // ALIGNADDR + 5127U, // ALIGNADDRL + 4695U, // ANDCCri + 4695U, // ANDCCrr + 4718U, // ANDNCCri + 4718U, // ANDNCCrr + 5182U, // ANDNri + 5182U, // ANDNrr + 5182U, // ANDXNrr + 4876U, // ANDXri + 4876U, // ANDXrr + 4876U, // ANDri + 4876U, // ANDrr + 4502U, // ARRAY16 + 4255U, // ARRAY32 + 4526U, // ARRAY8 + 0U, // ATOMIC_LOAD_ADD_32 + 0U, // ATOMIC_LOAD_ADD_64 + 0U, // ATOMIC_LOAD_AND_32 + 0U, // ATOMIC_LOAD_AND_64 + 0U, // ATOMIC_LOAD_MAX_32 + 0U, // ATOMIC_LOAD_MAX_64 + 0U, // ATOMIC_LOAD_MIN_32 + 0U, // ATOMIC_LOAD_MIN_64 + 0U, // ATOMIC_LOAD_NAND_32 + 0U, // ATOMIC_LOAD_NAND_64 + 0U, // ATOMIC_LOAD_OR_32 + 0U, // ATOMIC_LOAD_OR_64 + 0U, // ATOMIC_LOAD_SUB_32 + 0U, // ATOMIC_LOAD_SUB_64 + 0U, // ATOMIC_LOAD_UMAX_32 + 0U, // ATOMIC_LOAD_UMAX_64 + 0U, // ATOMIC_LOAD_UMIN_32 + 0U, // ATOMIC_LOAD_UMIN_64 + 0U, // ATOMIC_LOAD_XOR_32 + 0U, // ATOMIC_LOAD_XOR_64 + 0U, // ATOMIC_SWAP_64 + 74271U, // BA + 1194492U, // BCOND + 1260028U, // BCONDA + 17659U, // BINDri + 17659U, // BINDrr + 5065U, // BMASK + 145915U, // BPFCC + 211451U, // BPFCCA + 276987U, // BPFCCANT + 342523U, // BPFCCNT + 2106465U, // BPGEZapn + 2105838U, // BPGEZapt + 2106532U, // BPGEZnapn + 2107288U, // BPGEZnapt + 2106489U, // BPGZapn + 2105856U, // BPGZapt + 2106552U, // BPGZnapn + 2107384U, // BPGZnapt + 1456636U, // BPICC + 473596U, // BPICCA + 539132U, // BPICCANT + 604668U, // BPICCNT + 2106477U, // BPLEZapn + 2105847U, // BPLEZapt + 2106542U, // BPLEZnapn + 2107337U, // BPLEZnapt + 2106500U, // BPLZapn + 2105864U, // BPLZapt + 2106561U, // BPLZnapn + 2107428U, // BPLZnapt + 2106511U, // BPNZapn + 2105872U, // BPNZapt + 2106570U, // BPNZnapn + 2107472U, // BPNZnapt + 1718780U, // BPXCC + 735740U, // BPXCCA + 801276U, // BPXCCANT + 866812U, // BPXCCNT + 2106522U, // BPZapn + 2105880U, // BPZapt + 2106579U, // BPZnapn + 2107505U, // BPZnapt + 4983U, // BSHUFFLE + 74742U, // CALL + 17398U, // CALLri + 17398U, // CALLrr + 924148U, // CASXrr + 924129U, // CASrr + 74001U, // CMASK16 + 73833U, // CMASK32 + 74150U, // CMASK8 + 2106607U, // CMPri + 2106607U, // CMPrr + 4332U, // EDGE16 + 5081U, // EDGE16L + 5198U, // EDGE16LN + 5165U, // EDGE16N + 4164U, // EDGE32 + 5072U, // EDGE32L + 5188U, // EDGE32LN + 5156U, // EDGE32N + 4511U, // EDGE8 + 5090U, // EDGE8L + 5208U, // EDGE8LN + 5174U, // EDGE8N + 1053516U, // FABSD + 1054031U, // FABSQ + 1054376U, // FABSS + 4813U, // FADDD + 5383U, // FADDQ + 5645U, // FADDS + 4648U, // FALIGNADATA + 4875U, // FAND + 4112U, // FANDNOT1 + 5544U, // FANDNOT1S + 4271U, // FANDNOT2 + 5591U, // FANDNOT2S + 5677U, // FANDS + 1194491U, // FBCOND + 1260027U, // FBCONDA + 4394U, // FCHKSM16 + 2106173U, // FCMPD + 4413U, // FCMPEQ16 + 4226U, // FCMPEQ32 + 4432U, // FCMPGT16 + 4245U, // FCMPGT32 + 4340U, // FCMPLE16 + 4172U, // FCMPLE32 + 4350U, // FCMPNE16 + 4182U, // FCMPNE32 + 2106696U, // FCMPQ + 2107005U, // FCMPS + 4960U, // FDIVD + 5475U, // FDIVQ + 5815U, // FDIVS + 5405U, // FDMULQ + 1053620U, // FDTOI + 1053996U, // FDTOQ + 1054305U, // FDTOS + 1054536U, // FDTOX + 1053464U, // FEXPAND + 4820U, // FHADDD + 5652U, // FHADDS + 4800U, // FHSUBD + 5637U, // FHSUBS + 1053473U, // FITOD + 1054003U, // FITOQ + 1054312U, // FITOS + 6300484U, // FLCMPD + 6301316U, // FLCMPS + 2606U, // FLUSHW + 4404U, // FMEAN16 + 1053543U, // FMOVD + 1006078U, // FMOVD_FCC + 23484926U, // FMOVD_ICC + 23747070U, // FMOVD_XCC + 1054058U, // FMOVQ + 1006102U, // FMOVQ_FCC + 23484950U, // FMOVQ_ICC + 23747094U, // FMOVQ_XCC + 6018U, // FMOVRGEZD + 6029U, // FMOVRGEZQ + 6056U, // FMOVRGEZS + 6116U, // FMOVRGZD + 6126U, // FMOVRGZQ + 6150U, // FMOVRGZS + 6067U, // FMOVRLEZD + 6078U, // FMOVRLEZQ + 6105U, // FMOVRLEZS + 6160U, // FMOVRLZD + 6170U, // FMOVRLZQ + 6194U, // FMOVRLZS + 6204U, // FMOVRNZD + 6214U, // FMOVRNZQ + 6238U, // FMOVRNZS + 6009U, // FMOVRZD + 6248U, // FMOVRZQ + 6269U, // FMOVRZS + 1054398U, // FMOVS + 1006114U, // FMOVS_FCC + 23484962U, // FMOVS_ICC + 23747106U, // FMOVS_XCC + 4490U, // FMUL8SUX16 + 4465U, // FMUL8ULX16 + 4442U, // FMUL8X16 + 5098U, // FMUL8X16AL + 5849U, // FMUL8X16AU + 4860U, // FMULD + 4477U, // FMULD8SUX16 + 4452U, // FMULD8ULX16 + 5413U, // FMULQ + 5714U, // FMULS + 4837U, // FNADDD + 5669U, // FNADDS + 4881U, // FNAND + 5684U, // FNANDS + 1053429U, // FNEGD + 1053974U, // FNEGQ + 1054283U, // FNEGS + 4828U, // FNHADDD + 5660U, // FNHADDS + 4828U, // FNMULD + 5660U, // FNMULS + 5513U, // FNOR + 5778U, // FNORS + 1052698U, // FNOT1 + 1054131U, // FNOT1S + 1052857U, // FNOT2 + 1054178U, // FNOT2S + 5660U, // FNSMULD + 74625U, // FONE + 75324U, // FONES + 5508U, // FOR + 4129U, // FORNOT1 + 5563U, // FORNOT1S + 4288U, // FORNOT2 + 5610U, // FORNOT2S + 5772U, // FORS + 1052936U, // FPACK16 + 4192U, // FPACK32 + 1054507U, // FPACKFIX + 4323U, // FPADD16 + 5620U, // FPADD16S + 4155U, // FPADD32 + 5573U, // FPADD32S + 4297U, // FPADD64 + 4974U, // FPMERGE + 4314U, // FPSUB16 + 4580U, // FPSUB16S + 4146U, // FPSUB32 + 4570U, // FPSUB32S + 1053480U, // FQTOD + 1053627U, // FQTOI + 1054319U, // FQTOS + 1054552U, // FQTOX + 4423U, // FSLAS16 + 4236U, // FSLAS32 + 4378U, // FSLL16 + 4210U, // FSLL32 + 4867U, // FSMULD + 1053523U, // FSQRTD + 1054038U, // FSQRTQ + 1054383U, // FSQRTS + 4306U, // FSRA16 + 4138U, // FSRA32 + 1052681U, // FSRC1 + 1054112U, // FSRC1S + 1052840U, // FSRC2 + 1054159U, // FSRC2S + 4386U, // FSRL16 + 4218U, // FSRL32 + 1053487U, // FSTOD + 1053634U, // FSTOI + 1054010U, // FSTOQ + 1054559U, // FSTOX + 4793U, // FSUBD + 5376U, // FSUBQ + 5630U, // FSUBS + 5519U, // FXNOR + 5785U, // FXNORS + 5526U, // FXOR + 5793U, // FXORS + 1053494U, // FXTOD + 1054017U, // FXTOQ + 1054326U, // FXTOS + 74984U, // FZERO + 75353U, // FZEROS + 24584U, // GETPCX + 1078273U, // JMPLri + 1078273U, // JMPLrr + 1997243U, // LDDFri + 1997243U, // LDDFrr + 1997249U, // LDFri + 1997249U, // LDFrr + 1997275U, // LDQFri + 1997275U, // LDQFrr + 1997229U, // LDSBri + 1997229U, // LDSBrr + 1997254U, // LDSHri + 1997254U, // LDSHrr + 1997287U, // LDSWri + 1997287U, // LDSWrr + 1997236U, // LDUBri + 1997236U, // LDUBrr + 1997261U, // LDUHri + 1997261U, // LDUHrr + 1997294U, // LDXri + 1997294U, // LDXrr + 1997249U, // LDri + 1997249U, // LDrr + 33480U, // LEAX_ADDri + 33480U, // LEA_ADDri + 1054405U, // LZCNT + 75121U, // MEMBARi + 1054543U, // MOVDTOX + 1006122U, // MOVFCCri + 1006122U, // MOVFCCrr + 23484970U, // MOVICCri + 23484970U, // MOVICCrr + 6047U, // MOVRGEZri + 6047U, // MOVRGEZrr + 6142U, // MOVRGZri + 6142U, // MOVRGZrr + 6096U, // MOVRLEZri + 6096U, // MOVRLEZrr + 6186U, // MOVRLZri + 6186U, // MOVRLZrr + 6230U, // MOVRNZri + 6230U, // MOVRNZrr + 6262U, // MOVRRZri + 6262U, // MOVRRZrr + 1054469U, // MOVSTOSW + 1054479U, // MOVSTOUW + 1054543U, // MOVWTOS + 23747114U, // MOVXCCri + 23747114U, // MOVXCCrr + 1054543U, // MOVXTOD + 5954U, // MULXri + 5954U, // MULXrr + 2578U, // NOP + 4735U, // ORCCri + 4735U, // ORCCrr + 4726U, // ORNCCri + 4726U, // ORNCCrr + 5339U, // ORNri + 5339U, // ORNrr + 5339U, // ORXNrr + 5509U, // ORXri + 5509U, // ORXrr + 5509U, // ORri + 5509U, // ORrr + 5836U, // PDIST + 5344U, // PDISTN + 1053356U, // POPCrr + 73729U, // RDY + 4999U, // RESTOREri + 4999U, // RESTORErr + 76132U, // RET + 76141U, // RETL + 18131U, // RETTri + 18131U, // RETTrr + 5008U, // SAVEri + 5008U, // SAVErr + 4748U, // SDIVCCri + 4748U, // SDIVCCrr + 5995U, // SDIVXri + 5995U, // SDIVXrr + 5861U, // SDIVri + 5861U, // SDIVrr + 2182U, // SELECT_CC_DFP_FCC + 2293U, // SELECT_CC_DFP_ICC + 2238U, // SELECT_CC_FP_FCC + 2349U, // SELECT_CC_FP_ICC + 2265U, // SELECT_CC_Int_FCC + 2376U, // SELECT_CC_Int_ICC + 2210U, // SELECT_CC_QFP_FCC + 2321U, // SELECT_CC_QFP_ICC + 1053595U, // SETHIXi + 1053595U, // SETHIi + 2569U, // SHUTDOWN + 2564U, // SIAM + 5941U, // SLLXri + 5941U, // SLLXrr + 5116U, // SLLri + 5116U, // SLLrr + 4702U, // SMULCCri + 4702U, // SMULCCrr + 5144U, // SMULri + 5144U, // SMULrr + 5913U, // SRAXri + 5913U, // SRAXrr + 4643U, // SRAri + 4643U, // SRArr + 5947U, // SRLXri + 5947U, // SRLXrr + 5139U, // SRLri + 5139U, // SRLrr + 2588U, // STBAR + 37428U, // STBri + 37428U, // STBrr + 37723U, // STDFri + 37723U, // STDFrr + 38607U, // STFri + 38607U, // STFrr + 37782U, // STHri + 37782U, // STHrr + 38238U, // STQFri + 38238U, // STQFrr + 38758U, // STXri + 38758U, // STXrr + 38607U, // STri + 38607U, // STrr + 4671U, // SUBCCri + 4671U, // SUBCCrr + 5919U, // SUBCri + 5919U, // SUBCrr + 4764U, // SUBEri + 4764U, // SUBErr + 4665U, // SUBXri + 4665U, // SUBXrr + 4665U, // SUBri + 4665U, // SUBrr + 1997268U, // SWAPri + 1997268U, // SWAPrr + 2422U, // TA3 + 2427U, // TA5 + 5883U, // TADDCCTVri + 5883U, // TADDCCTVrr + 4687U, // TADDCCri + 4687U, // TADDCCrr + 9873960U, // TICCri + 9873960U, // TICCrr + 37753544U, // TLS_ADDXrr + 37753544U, // TLS_ADDrr + 2106358U, // TLS_CALL + 39746030U, // TLS_LDXrr + 39745985U, // TLS_LDrr + 5873U, // TSUBCCTVri + 5873U, // TSUBCCTVrr + 4670U, // TSUBCCri + 4670U, // TSUBCCrr + 10136104U, // TXCCri + 10136104U, // TXCCrr + 4756U, // UDIVCCri + 4756U, // UDIVCCrr + 6002U, // UDIVXri + 6002U, // UDIVXrr + 5867U, // UDIVri + 5867U, // UDIVrr + 4710U, // UMULCCri + 4710U, // UMULCCrr + 5026U, // UMULXHI + 5150U, // UMULri + 5150U, // UMULrr + 74996U, // UNIMP + 6300477U, // V9FCMPD + 6300397U, // V9FCMPED + 6300942U, // V9FCMPEQ + 6301251U, // V9FCMPES + 6301000U, // V9FCMPQ + 6301309U, // V9FCMPS + 47614U, // V9FMOVD_FCC + 47638U, // V9FMOVQ_FCC + 47650U, // V9FMOVS_FCC + 47658U, // V9MOVFCCri + 47658U, // V9MOVFCCrr + 14689692U, // WRYri + 14689692U, // WRYrr + 5953U, // XMULX + 5035U, // XMULXHI + 4733U, // XNORCCri + 4733U, // XNORCCrr + 5520U, // XNORXrr + 5520U, // XNORri + 5520U, // XNORrr + 4741U, // XORCCri + 4741U, // XORCCrr + 5527U, // XORXri + 5527U, // XORXrr + 5527U, // XORri + 5527U, // XORrr + 0U + }; + +#ifndef CAPSTONE_DIET + static char AsmStrs[] = { + /* 0 */ 'r', 'd', 32, '%', 'y', ',', 32, 0, + /* 8 */ 'f', 's', 'r', 'c', '1', 32, 0, + /* 15 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 32, 0, + /* 25 */ 'f', 'n', 'o', 't', '1', 32, 0, + /* 32 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 32, 0, + /* 41 */ 'f', 's', 'r', 'a', '3', '2', 32, 0, + /* 49 */ 'f', 'p', 's', 'u', 'b', '3', '2', 32, 0, + /* 58 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 32, 0, + /* 67 */ 'e', 'd', 'g', 'e', '3', '2', 32, 0, + /* 75 */ 'f', 'c', 'm', 'p', 'l', 'e', '3', '2', 32, 0, + /* 85 */ 'f', 'c', 'm', 'p', 'n', 'e', '3', '2', 32, 0, + /* 95 */ 'f', 'p', 'a', 'c', 'k', '3', '2', 32, 0, + /* 104 */ 'c', 'm', 'a', 's', 'k', '3', '2', 32, 0, + /* 113 */ 'f', 's', 'l', 'l', '3', '2', 32, 0, + /* 121 */ 'f', 's', 'r', 'l', '3', '2', 32, 0, + /* 129 */ 'f', 'c', 'm', 'p', 'e', 'q', '3', '2', 32, 0, + /* 139 */ 'f', 's', 'l', 'a', 's', '3', '2', 32, 0, + /* 148 */ 'f', 'c', 'm', 'p', 'g', 't', '3', '2', 32, 0, + /* 158 */ 'a', 'r', 'r', 'a', 'y', '3', '2', 32, 0, + /* 167 */ 'f', 's', 'r', 'c', '2', 32, 0, + /* 174 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 32, 0, + /* 184 */ 'f', 'n', 'o', 't', '2', 32, 0, + /* 191 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 32, 0, + /* 200 */ 'f', 'p', 'a', 'd', 'd', '6', '4', 32, 0, + /* 209 */ 'f', 's', 'r', 'a', '1', '6', 32, 0, + /* 217 */ 'f', 'p', 's', 'u', 'b', '1', '6', 32, 0, + /* 226 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 32, 0, + /* 235 */ 'e', 'd', 'g', 'e', '1', '6', 32, 0, + /* 243 */ 'f', 'c', 'm', 'p', 'l', 'e', '1', '6', 32, 0, + /* 253 */ 'f', 'c', 'm', 'p', 'n', 'e', '1', '6', 32, 0, + /* 263 */ 'f', 'p', 'a', 'c', 'k', '1', '6', 32, 0, + /* 272 */ 'c', 'm', 'a', 's', 'k', '1', '6', 32, 0, + /* 281 */ 'f', 's', 'l', 'l', '1', '6', 32, 0, + /* 289 */ 'f', 's', 'r', 'l', '1', '6', 32, 0, + /* 297 */ 'f', 'c', 'h', 'k', 's', 'm', '1', '6', 32, 0, + /* 307 */ 'f', 'm', 'e', 'a', 'n', '1', '6', 32, 0, + /* 316 */ 'f', 'c', 'm', 'p', 'e', 'q', '1', '6', 32, 0, + /* 326 */ 'f', 's', 'l', 'a', 's', '1', '6', 32, 0, + /* 335 */ 'f', 'c', 'm', 'p', 'g', 't', '1', '6', 32, 0, + /* 345 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 32, 0, + /* 355 */ 'f', 'm', 'u', 'l', 'd', '8', 'u', 'l', 'x', '1', '6', 32, 0, + /* 368 */ 'f', 'm', 'u', 'l', '8', 'u', 'l', 'x', '1', '6', 32, 0, + /* 380 */ 'f', 'm', 'u', 'l', 'd', '8', 's', 'u', 'x', '1', '6', 32, 0, + /* 393 */ 'f', 'm', 'u', 'l', '8', 's', 'u', 'x', '1', '6', 32, 0, + /* 405 */ 'a', 'r', 'r', 'a', 'y', '1', '6', 32, 0, + /* 414 */ 'e', 'd', 'g', 'e', '8', 32, 0, + /* 421 */ 'c', 'm', 'a', 's', 'k', '8', 32, 0, + /* 429 */ 'a', 'r', 'r', 'a', 'y', '8', 32, 0, + /* 437 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 32, 0, + /* 456 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 32, 0, + /* 473 */ 'f', 'p', 's', 'u', 'b', '3', '2', 'S', 32, 0, + /* 483 */ 'f', 'p', 's', 'u', 'b', '1', '6', 'S', 32, 0, + /* 493 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', 32, 0, + /* 502 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', 32, 0, + /* 511 */ 'b', 'r', 'g', 'z', ',', 'a', 32, 0, + /* 519 */ 'b', 'r', 'l', 'z', ',', 'a', 32, 0, + /* 527 */ 'b', 'r', 'n', 'z', ',', 'a', 32, 0, + /* 535 */ 'b', 'r', 'z', ',', 'a', 32, 0, + /* 542 */ 'b', 'a', 32, 0, + /* 546 */ 's', 'r', 'a', 32, 0, + /* 551 */ 'f', 'a', 'l', 'i', 'g', 'n', 'd', 'a', 't', 'a', 32, 0, + /* 563 */ 's', 't', 'b', 32, 0, + /* 568 */ 's', 'u', 'b', 32, 0, + /* 573 */ 't', 's', 'u', 'b', 'c', 'c', 32, 0, + /* 581 */ 'a', 'd', 'd', 'x', 'c', 'c', 'c', 32, 0, + /* 590 */ 't', 'a', 'd', 'd', 'c', 'c', 32, 0, + /* 598 */ 'a', 'n', 'd', 'c', 'c', 32, 0, + /* 605 */ 's', 'm', 'u', 'l', 'c', 'c', 32, 0, + /* 613 */ 'u', 'm', 'u', 'l', 'c', 'c', 32, 0, + /* 621 */ 'a', 'n', 'd', 'n', 'c', 'c', 32, 0, + /* 629 */ 'o', 'r', 'n', 'c', 'c', 32, 0, + /* 636 */ 'x', 'n', 'o', 'r', 'c', 'c', 32, 0, + /* 644 */ 'x', 'o', 'r', 'c', 'c', 32, 0, + /* 651 */ 's', 'd', 'i', 'v', 'c', 'c', 32, 0, + /* 659 */ 'u', 'd', 'i', 'v', 'c', 'c', 32, 0, + /* 667 */ 's', 'u', 'b', 'x', 'c', 'c', 32, 0, + /* 675 */ 'a', 'd', 'd', 'x', 'c', 'c', 32, 0, + /* 683 */ 'p', 'o', 'p', 'c', 32, 0, + /* 689 */ 'a', 'd', 'd', 'x', 'c', 32, 0, + /* 696 */ 'f', 's', 'u', 'b', 'd', 32, 0, + /* 703 */ 'f', 'h', 's', 'u', 'b', 'd', 32, 0, + /* 711 */ 'a', 'd', 'd', 32, 0, + /* 716 */ 'f', 'a', 'd', 'd', 'd', 32, 0, + /* 723 */ 'f', 'h', 'a', 'd', 'd', 'd', 32, 0, + /* 731 */ 'f', 'n', 'h', 'a', 'd', 'd', 'd', 32, 0, + /* 740 */ 'f', 'n', 'a', 'd', 'd', 'd', 32, 0, + /* 748 */ 'f', 'c', 'm', 'p', 'e', 'd', 32, 0, + /* 756 */ 'f', 'n', 'e', 'g', 'd', 32, 0, + /* 763 */ 'f', 'm', 'u', 'l', 'd', 32, 0, + /* 770 */ 'f', 's', 'm', 'u', 'l', 'd', 32, 0, + /* 778 */ 'f', 'a', 'n', 'd', 32, 0, + /* 784 */ 'f', 'n', 'a', 'n', 'd', 32, 0, + /* 791 */ 'f', 'e', 'x', 'p', 'a', 'n', 'd', 32, 0, + /* 800 */ 'f', 'i', 't', 'o', 'd', 32, 0, + /* 807 */ 'f', 'q', 't', 'o', 'd', 32, 0, + /* 814 */ 'f', 's', 't', 'o', 'd', 32, 0, + /* 821 */ 'f', 'x', 't', 'o', 'd', 32, 0, + /* 828 */ 'f', 'c', 'm', 'p', 'd', 32, 0, + /* 835 */ 'f', 'l', 'c', 'm', 'p', 'd', 32, 0, + /* 843 */ 'f', 'a', 'b', 's', 'd', 32, 0, + /* 850 */ 'f', 's', 'q', 'r', 't', 'd', 32, 0, + /* 858 */ 's', 't', 'd', 32, 0, + /* 863 */ 'f', 'd', 'i', 'v', 'd', 32, 0, + /* 870 */ 'f', 'm', 'o', 'v', 'd', 32, 0, + /* 877 */ 'f', 'p', 'm', 'e', 'r', 'g', 'e', 32, 0, + /* 886 */ 'b', 's', 'h', 'u', 'f', 'f', 'l', 'e', 32, 0, + /* 896 */ 'f', 'o', 'n', 'e', 32, 0, + /* 902 */ 'r', 'e', 's', 't', 'o', 'r', 'e', 32, 0, + /* 911 */ 's', 'a', 'v', 'e', 32, 0, + /* 917 */ 's', 't', 'h', 32, 0, + /* 922 */ 's', 'e', 't', 'h', 'i', 32, 0, + /* 929 */ 'u', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0, + /* 938 */ 'x', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0, + /* 947 */ 'f', 'd', 't', 'o', 'i', 32, 0, + /* 954 */ 'f', 'q', 't', 'o', 'i', 32, 0, + /* 961 */ 'f', 's', 't', 'o', 'i', 32, 0, + /* 968 */ 'b', 'm', 'a', 's', 'k', 32, 0, + /* 975 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 32, 0, + /* 984 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 32, 0, + /* 993 */ 'e', 'd', 'g', 'e', '8', 'l', 32, 0, + /* 1001 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'l', 32, 0, + /* 1013 */ 'c', 'a', 'l', 'l', 32, 0, + /* 1019 */ 's', 'l', 'l', 32, 0, + /* 1024 */ 'j', 'm', 'p', 'l', 32, 0, + /* 1030 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 'l', 32, 0, + /* 1042 */ 's', 'r', 'l', 32, 0, + /* 1047 */ 's', 'm', 'u', 'l', 32, 0, + /* 1053 */ 'u', 'm', 'u', 'l', 32, 0, + /* 1059 */ 'e', 'd', 'g', 'e', '3', '2', 'n', 32, 0, + /* 1068 */ 'e', 'd', 'g', 'e', '1', '6', 'n', 32, 0, + /* 1077 */ 'e', 'd', 'g', 'e', '8', 'n', 32, 0, + /* 1085 */ 'a', 'n', 'd', 'n', 32, 0, + /* 1091 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 'n', 32, 0, + /* 1101 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 'n', 32, 0, + /* 1111 */ 'e', 'd', 'g', 'e', '8', 'l', 'n', 32, 0, + /* 1120 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0, + /* 1132 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0, + /* 1144 */ 'b', 'r', 'g', 'z', ',', 'a', ',', 'p', 'n', 32, 0, + /* 1155 */ 'b', 'r', 'l', 'z', ',', 'a', ',', 'p', 'n', 32, 0, + /* 1166 */ 'b', 'r', 'n', 'z', ',', 'a', ',', 'p', 'n', 32, 0, + /* 1177 */ 'b', 'r', 'z', ',', 'a', ',', 'p', 'n', 32, 0, + /* 1187 */ 'b', 'r', 'g', 'e', 'z', ',', 'p', 'n', 32, 0, + /* 1197 */ 'b', 'r', 'l', 'e', 'z', ',', 'p', 'n', 32, 0, + /* 1207 */ 'b', 'r', 'g', 'z', ',', 'p', 'n', 32, 0, + /* 1216 */ 'b', 'r', 'l', 'z', ',', 'p', 'n', 32, 0, + /* 1225 */ 'b', 'r', 'n', 'z', ',', 'p', 'n', 32, 0, + /* 1234 */ 'b', 'r', 'z', ',', 'p', 'n', 32, 0, + /* 1242 */ 'o', 'r', 'n', 32, 0, + /* 1247 */ 'p', 'd', 'i', 's', 't', 'n', 32, 0, + /* 1255 */ 'f', 'z', 'e', 'r', 'o', 32, 0, + /* 1262 */ 'c', 'm', 'p', 32, 0, + /* 1267 */ 'u', 'n', 'i', 'm', 'p', 32, 0, + /* 1274 */ 'j', 'm', 'p', 32, 0, + /* 1279 */ 'f', 's', 'u', 'b', 'q', 32, 0, + /* 1286 */ 'f', 'a', 'd', 'd', 'q', 32, 0, + /* 1293 */ 'f', 'c', 'm', 'p', 'e', 'q', 32, 0, + /* 1301 */ 'f', 'n', 'e', 'g', 'q', 32, 0, + /* 1308 */ 'f', 'd', 'm', 'u', 'l', 'q', 32, 0, + /* 1316 */ 'f', 'm', 'u', 'l', 'q', 32, 0, + /* 1323 */ 'f', 'd', 't', 'o', 'q', 32, 0, + /* 1330 */ 'f', 'i', 't', 'o', 'q', 32, 0, + /* 1337 */ 'f', 's', 't', 'o', 'q', 32, 0, + /* 1344 */ 'f', 'x', 't', 'o', 'q', 32, 0, + /* 1351 */ 'f', 'c', 'm', 'p', 'q', 32, 0, + /* 1358 */ 'f', 'a', 'b', 's', 'q', 32, 0, + /* 1365 */ 'f', 's', 'q', 'r', 't', 'q', 32, 0, + /* 1373 */ 's', 't', 'q', 32, 0, + /* 1378 */ 'f', 'd', 'i', 'v', 'q', 32, 0, + /* 1385 */ 'f', 'm', 'o', 'v', 'q', 32, 0, + /* 1392 */ 'm', 'e', 'm', 'b', 'a', 'r', 32, 0, + /* 1400 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 32, 0, + /* 1411 */ 'f', 'o', 'r', 32, 0, + /* 1416 */ 'f', 'n', 'o', 'r', 32, 0, + /* 1422 */ 'f', 'x', 'n', 'o', 'r', 32, 0, + /* 1429 */ 'f', 'x', 'o', 'r', 32, 0, + /* 1435 */ 'w', 'r', 32, 0, + /* 1439 */ 'f', 's', 'r', 'c', '1', 's', 32, 0, + /* 1447 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 's', 32, 0, + /* 1458 */ 'f', 'n', 'o', 't', '1', 's', 32, 0, + /* 1466 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 's', 32, 0, + /* 1476 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 's', 32, 0, + /* 1486 */ 'f', 's', 'r', 'c', '2', 's', 32, 0, + /* 1494 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 's', 32, 0, + /* 1505 */ 'f', 'n', 'o', 't', '2', 's', 32, 0, + /* 1513 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 's', 32, 0, + /* 1523 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 's', 32, 0, + /* 1533 */ 'f', 's', 'u', 'b', 's', 32, 0, + /* 1540 */ 'f', 'h', 's', 'u', 'b', 's', 32, 0, + /* 1548 */ 'f', 'a', 'd', 'd', 's', 32, 0, + /* 1555 */ 'f', 'h', 'a', 'd', 'd', 's', 32, 0, + /* 1563 */ 'f', 'n', 'h', 'a', 'd', 'd', 's', 32, 0, + /* 1572 */ 'f', 'n', 'a', 'd', 'd', 's', 32, 0, + /* 1580 */ 'f', 'a', 'n', 'd', 's', 32, 0, + /* 1587 */ 'f', 'n', 'a', 'n', 'd', 's', 32, 0, + /* 1595 */ 'f', 'o', 'n', 'e', 's', 32, 0, + /* 1602 */ 'f', 'c', 'm', 'p', 'e', 's', 32, 0, + /* 1610 */ 'f', 'n', 'e', 'g', 's', 32, 0, + /* 1617 */ 'f', 'm', 'u', 'l', 's', 32, 0, + /* 1624 */ 'f', 'z', 'e', 'r', 'o', 's', 32, 0, + /* 1632 */ 'f', 'd', 't', 'o', 's', 32, 0, + /* 1639 */ 'f', 'i', 't', 'o', 's', 32, 0, + /* 1646 */ 'f', 'q', 't', 'o', 's', 32, 0, + /* 1653 */ 'f', 'x', 't', 'o', 's', 32, 0, + /* 1660 */ 'f', 'c', 'm', 'p', 's', 32, 0, + /* 1667 */ 'f', 'l', 'c', 'm', 'p', 's', 32, 0, + /* 1675 */ 'f', 'o', 'r', 's', 32, 0, + /* 1681 */ 'f', 'n', 'o', 'r', 's', 32, 0, + /* 1688 */ 'f', 'x', 'n', 'o', 'r', 's', 32, 0, + /* 1696 */ 'f', 'x', 'o', 'r', 's', 32, 0, + /* 1703 */ 'f', 'a', 'b', 's', 's', 32, 0, + /* 1710 */ 'f', 's', 'q', 'r', 't', 's', 32, 0, + /* 1718 */ 'f', 'd', 'i', 'v', 's', 32, 0, + /* 1725 */ 'f', 'm', 'o', 'v', 's', 32, 0, + /* 1732 */ 'l', 'z', 'c', 'n', 't', 32, 0, + /* 1739 */ 'p', 'd', 'i', 's', 't', 32, 0, + /* 1746 */ 'r', 'e', 't', 't', 32, 0, + /* 1752 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'u', 32, 0, + /* 1764 */ 's', 'd', 'i', 'v', 32, 0, + /* 1770 */ 'u', 'd', 'i', 'v', 32, 0, + /* 1776 */ 't', 's', 'u', 'b', 'c', 'c', 't', 'v', 32, 0, + /* 1786 */ 't', 'a', 'd', 'd', 'c', 'c', 't', 'v', 32, 0, + /* 1796 */ 'm', 'o', 'v', 's', 't', 'o', 's', 'w', 32, 0, + /* 1806 */ 'm', 'o', 'v', 's', 't', 'o', 'u', 'w', 32, 0, + /* 1816 */ 's', 'r', 'a', 'x', 32, 0, + /* 1822 */ 's', 'u', 'b', 'x', 32, 0, + /* 1828 */ 'a', 'd', 'd', 'x', 32, 0, + /* 1834 */ 'f', 'p', 'a', 'c', 'k', 'f', 'i', 'x', 32, 0, + /* 1844 */ 's', 'l', 'l', 'x', 32, 0, + /* 1850 */ 's', 'r', 'l', 'x', 32, 0, + /* 1856 */ 'x', 'm', 'u', 'l', 'x', 32, 0, + /* 1863 */ 'f', 'd', 't', 'o', 'x', 32, 0, + /* 1870 */ 'm', 'o', 'v', 'd', 't', 'o', 'x', 32, 0, + /* 1879 */ 'f', 'q', 't', 'o', 'x', 32, 0, + /* 1886 */ 'f', 's', 't', 'o', 'x', 32, 0, + /* 1893 */ 's', 't', 'x', 32, 0, + /* 1898 */ 's', 'd', 'i', 'v', 'x', 32, 0, + /* 1905 */ 'u', 'd', 'i', 'v', 'x', 32, 0, + /* 1912 */ 'f', 'm', 'o', 'v', 'r', 'd', 'z', 32, 0, + /* 1921 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'e', 'z', 32, 0, + /* 1932 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'e', 'z', 32, 0, + /* 1943 */ 'b', 'r', 'g', 'e', 'z', 32, 0, + /* 1950 */ 'm', 'o', 'v', 'r', 'g', 'e', 'z', 32, 0, + /* 1959 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'e', 'z', 32, 0, + /* 1970 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'e', 'z', 32, 0, + /* 1981 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'e', 'z', 32, 0, + /* 1992 */ 'b', 'r', 'l', 'e', 'z', 32, 0, + /* 1999 */ 'm', 'o', 'v', 'r', 'l', 'e', 'z', 32, 0, + /* 2008 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'e', 'z', 32, 0, + /* 2019 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'z', 32, 0, + /* 2029 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'z', 32, 0, + /* 2039 */ 'b', 'r', 'g', 'z', 32, 0, + /* 2045 */ 'm', 'o', 'v', 'r', 'g', 'z', 32, 0, + /* 2053 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'z', 32, 0, + /* 2063 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'z', 32, 0, + /* 2073 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'z', 32, 0, + /* 2083 */ 'b', 'r', 'l', 'z', 32, 0, + /* 2089 */ 'm', 'o', 'v', 'r', 'l', 'z', 32, 0, + /* 2097 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'z', 32, 0, + /* 2107 */ 'f', 'm', 'o', 'v', 'r', 'd', 'n', 'z', 32, 0, + /* 2117 */ 'f', 'm', 'o', 'v', 'r', 'q', 'n', 'z', 32, 0, + /* 2127 */ 'b', 'r', 'n', 'z', 32, 0, + /* 2133 */ 'm', 'o', 'v', 'r', 'n', 'z', 32, 0, + /* 2141 */ 'f', 'm', 'o', 'v', 'r', 's', 'n', 'z', 32, 0, + /* 2151 */ 'f', 'm', 'o', 'v', 'r', 'q', 'z', 32, 0, + /* 2160 */ 'b', 'r', 'z', 32, 0, + /* 2165 */ 'm', 'o', 'v', 'r', 'z', 32, 0, + /* 2172 */ 'f', 'm', 'o', 'v', 'r', 's', 'z', 32, 0, + /* 2181 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, + /* 2209 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, + /* 2237 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, + /* 2264 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, + /* 2292 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, + /* 2320 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, + /* 2348 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, + /* 2375 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, + /* 2403 */ 'j', 'm', 'p', 32, '%', 'i', '7', '+', 0, + /* 2412 */ 'j', 'm', 'p', 32, '%', 'o', '7', '+', 0, + /* 2421 */ 't', 'a', 32, '3', 0, + /* 2426 */ 't', 'a', 32, '5', 0, + /* 2431 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, + /* 2444 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, + /* 2451 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, + /* 2461 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, + /* 2476 */ 'l', 'd', 's', 'b', 32, '[', 0, + /* 2483 */ 'l', 'd', 'u', 'b', 32, '[', 0, + /* 2490 */ 'l', 'd', 'd', 32, '[', 0, + /* 2496 */ 'l', 'd', 32, '[', 0, + /* 2501 */ 'l', 'd', 's', 'h', 32, '[', 0, + /* 2508 */ 'l', 'd', 'u', 'h', 32, '[', 0, + /* 2515 */ 's', 'w', 'a', 'p', 32, '[', 0, + /* 2522 */ 'l', 'd', 'q', 32, '[', 0, + /* 2528 */ 'c', 'a', 's', 32, '[', 0, + /* 2534 */ 'l', 'd', 's', 'w', 32, '[', 0, + /* 2541 */ 'l', 'd', 'x', 32, '[', 0, + /* 2547 */ 'c', 'a', 's', 'x', 32, '[', 0, + /* 2554 */ 'f', 'b', 0, + /* 2557 */ 'f', 'm', 'o', 'v', 'd', 0, + /* 2563 */ 's', 'i', 'a', 'm', 0, + /* 2568 */ 's', 'h', 'u', 't', 'd', 'o', 'w', 'n', 0, + /* 2577 */ 'n', 'o', 'p', 0, + /* 2581 */ 'f', 'm', 'o', 'v', 'q', 0, + /* 2587 */ 's', 't', 'b', 'a', 'r', 0, + /* 2593 */ 'f', 'm', 'o', 'v', 's', 0, + /* 2599 */ 't', 0, + /* 2601 */ 'm', 'o', 'v', 0, + /* 2605 */ 'f', 'l', 'u', 's', 'h', 'w', 0, + }; +#endif + + // Emit the opcode for the instruction. + uint32_t Bits = OpInfo[MCInst_getOpcode(MI)]; +#ifndef CAPSTONE_DIET + // assert(Bits != 0 && "Cannot print this instruction."); + SStream_concat(O, "%s", AsmStrs+(Bits & 4095)-1); +#endif + + + // Fragment 0 encoded into 4 bits for 12 unique commands. + printf("Frag-0: %u\n", (Bits >> 12) & 15); + switch ((Bits >> 12) & 15) { + default: // unreachable. + case 0: + // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, FLUSHW, NOP, SELECT_C... + return; + break; + case 1: + // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX... + printOperand(MI, 1, O); + break; + case 2: + // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, BPGEZapn, BPGEZapt, BPGEZnapn, B... + printOperand(MI, 0, O); + break; + case 3: + // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA... + printCCOperand(MI, 1, O); + break; + case 4: + // BINDri, BINDrr, CALLri, CALLrr, RETTri, RETTrr + printMemOperand(MI, 0, O, NULL); + return; + break; + case 5: + // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV... + printCCOperand(MI, 3, O); + break; + case 6: + // GETPCX + printGetPCX(MI, 0, O); + return; + break; + case 7: + // JMPLri, JMPLrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, ... + printMemOperand(MI, 1, O, NULL); + break; + case 8: + // LEAX_ADDri, LEA_ADDri + printMemOperand(MI, 1, O, "arith"); + SStream_concat(O, "%s", ", "); + printOperand(MI, 0, O); + return; + break; + case 9: + // STBri, STBrr, STDFri, STDFrr, STFri, STFrr, STHri, STHrr, STQFri, STQF... + printOperand(MI, 2, O); + SStream_concat(O, "%s", ", ["); + printMemOperand(MI, 0, O, NULL); + SStream_concat(O, "%s", "]"); + return; + break; + case 10: + // TICCri, TICCrr, TXCCri, TXCCrr + printCCOperand(MI, 2, O); + break; + case 11: + // V9FMOVD_FCC, V9FMOVQ_FCC, V9FMOVS_FCC, V9MOVFCCri, V9MOVFCCrr + printCCOperand(MI, 4, O); + SStream_concat(O, "%s", " "); + printOperand(MI, 1, O); + SStream_concat(O, "%s", ", "); + printOperand(MI, 2, O); + SStream_concat(O, "%s", ", "); + printOperand(MI, 0, O); + return; + break; + } + + + // Fragment 1 encoded into 4 bits for 16 unique commands. + printf("Frag-1: %u\n", (Bits >> 16) & 15); + switch ((Bits >> 16) & 15) { + default: // unreachable. + case 0: + // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX... + SStream_concat(O, "%s", ", "); + break; + case 1: + // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, CALL, CMASK16, CMASK32, CMASK8, ... + return; + break; + case 2: + // BCOND, BPFCC, FBCOND + SStream_concat(O, "%s", " "); + break; + case 3: + // BCONDA, BPFCCA, FBCONDA + SStream_concat(O, "%s", ",a "); + break; + case 4: + // BPFCCANT + SStream_concat(O, "%s", ",a,pn "); + printOperand(MI, 2, O); + SStream_concat(O, "%s", ", "); + printOperand(MI, 0, O); + return; + break; + case 5: + // BPFCCNT + SStream_concat(O, "%s", ",pn "); + printOperand(MI, 2, O); + SStream_concat(O, "%s", ", "); + printOperand(MI, 0, O); + return; + break; + case 6: + // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI... + SStream_concat(O, "%s", " %icc, "); + break; + case 7: + // BPICCA + SStream_concat(O, "%s", ",a %icc, "); + printOperand(MI, 0, O); + return; + break; + case 8: + // BPICCANT + SStream_concat(O, "%s", ",a,pn %icc, "); + printOperand(MI, 0, O); + return; + break; + case 9: + // BPICCNT + SStream_concat(O, "%s", ",pn %icc, "); + printOperand(MI, 0, O); + return; + break; + case 10: + // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX... + SStream_concat(O, "%s", " %xcc, "); + break; + case 11: + // BPXCCA + SStream_concat(O, "%s", ",a %xcc, "); + printOperand(MI, 0, O); + return; + break; + case 12: + // BPXCCANT + SStream_concat(O, "%s", ",a,pn %xcc, "); + printOperand(MI, 0, O); + return; + break; + case 13: + // BPXCCNT + SStream_concat(O, "%s", ",pn %xcc, "); + printOperand(MI, 0, O); + return; + break; + case 14: + // CASXrr, CASrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, L... + SStream_concat(O, "%s", "], "); + break; + case 15: + // FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr + SStream_concat(O, "%s", " %fcc0, "); + printOperand(MI, 1, O); + SStream_concat(O, "%s", ", "); + printOperand(MI, 0, O); + return; + break; + } + + + // Fragment 2 encoded into 2 bits for 3 unique commands. + printf("Frag-2: %u\n", (Bits >> 20) & 3); + switch ((Bits >> 20) & 3) { + default: // unreachable. + case 0: + // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX... + printOperand(MI, 2, O); + SStream_concat(O, "%s", ", "); + printOperand(MI, 0, O); + break; + case 1: + // BCOND, BCONDA, BPICC, BPXCC, FABSD, FABSQ, FABSS, FBCOND, FBCONDA, FDT... + printOperand(MI, 0, O); + break; + case 2: + // BPGEZapn, BPGEZapt, BPGEZnapn, BPGEZnapt, BPGZapn, BPGZapt, BPGZnapn, ... + printOperand(MI, 1, O); + break; + } + + + // Fragment 3 encoded into 2 bits for 4 unique commands. + printf("Frag-3: %u\n", (Bits >> 22) & 3); + switch ((Bits >> 22) & 3) { + default: // unreachable. + case 0: + // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX... + return; + break; + case 1: + // FLCMPD, FLCMPS, FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC,... + SStream_concat(O, "%s", ", "); + break; + case 2: + // TICCri, TICCrr, TXCCri, TXCCrr + SStream_concat(O, "%s", " + "); + printOperand(MI, 1, O); + return; + break; + case 3: + // WRYri, WRYrr + SStream_concat(O, "%s", ", %y"); + return; + break; + } + + + // Fragment 4 encoded into 2 bits for 3 unique commands. + printf("Frag-4: %u\n", (Bits >> 24) & 3); + switch ((Bits >> 24) & 3) { + default: // unreachable. + case 0: + // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP... + printOperand(MI, 2, O); + return; + break; + case 1: + // FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC, FMOVS_XCC, MOVI... + printOperand(MI, 0, O); + return; + break; + case 2: + // TLS_ADDXrr, TLS_ADDrr, TLS_LDXrr, TLS_LDrr + printOperand(MI, 3, O); + return; + break; + } +} + + +/// getRegisterName - This method is automatically generated by tblgen +/// from the register set description. This returns the assembler name +/// for the specified register. +static const char *getRegisterName(unsigned RegNo) +{ + // assert(RegNo && RegNo < 119 && "Invalid register number!"); + +#ifndef CAPSTONE_DIET + static const char AsmStrs[] = { + /* 0 */ 'f', '1', '0', 0, + /* 4 */ 'f', '2', '0', 0, + /* 8 */ 'f', '3', '0', 0, + /* 12 */ 'f', '4', '0', 0, + /* 16 */ 'f', '5', '0', 0, + /* 20 */ 'f', '6', '0', 0, + /* 24 */ 'f', 'c', 'c', '0', 0, + /* 29 */ 'f', '0', 0, + /* 32 */ 'g', '0', 0, + /* 35 */ 'i', '0', 0, + /* 38 */ 'l', '0', 0, + /* 41 */ 'o', '0', 0, + /* 44 */ 'f', '1', '1', 0, + /* 48 */ 'f', '2', '1', 0, + /* 52 */ 'f', '3', '1', 0, + /* 56 */ 'f', 'c', 'c', '1', 0, + /* 61 */ 'f', '1', 0, + /* 64 */ 'g', '1', 0, + /* 67 */ 'i', '1', 0, + /* 70 */ 'l', '1', 0, + /* 73 */ 'o', '1', 0, + /* 76 */ 'f', '1', '2', 0, + /* 80 */ 'f', '2', '2', 0, + /* 84 */ 'f', '3', '2', 0, + /* 88 */ 'f', '4', '2', 0, + /* 92 */ 'f', '5', '2', 0, + /* 96 */ 'f', '6', '2', 0, + /* 100 */ 'f', 'c', 'c', '2', 0, + /* 105 */ 'f', '2', 0, + /* 108 */ 'g', '2', 0, + /* 111 */ 'i', '2', 0, + /* 114 */ 'l', '2', 0, + /* 117 */ 'o', '2', 0, + /* 120 */ 'f', '1', '3', 0, + /* 124 */ 'f', '2', '3', 0, + /* 128 */ 'f', 'c', 'c', '3', 0, + /* 133 */ 'f', '3', 0, + /* 136 */ 'g', '3', 0, + /* 139 */ 'i', '3', 0, + /* 142 */ 'l', '3', 0, + /* 145 */ 'o', '3', 0, + /* 148 */ 'f', '1', '4', 0, + /* 152 */ 'f', '2', '4', 0, + /* 156 */ 'f', '3', '4', 0, + /* 160 */ 'f', '4', '4', 0, + /* 164 */ 'f', '5', '4', 0, + /* 168 */ 'f', '4', 0, + /* 171 */ 'g', '4', 0, + /* 174 */ 'i', '4', 0, + /* 177 */ 'l', '4', 0, + /* 180 */ 'o', '4', 0, + /* 183 */ 'f', '1', '5', 0, + /* 187 */ 'f', '2', '5', 0, + /* 191 */ 'f', '5', 0, + /* 194 */ 'g', '5', 0, + /* 197 */ 'i', '5', 0, + /* 200 */ 'l', '5', 0, + /* 203 */ 'o', '5', 0, + /* 206 */ 'f', '1', '6', 0, + /* 210 */ 'f', '2', '6', 0, + /* 214 */ 'f', '3', '6', 0, + /* 218 */ 'f', '4', '6', 0, + /* 222 */ 'f', '5', '6', 0, + /* 226 */ 'f', '6', 0, + /* 229 */ 'g', '6', 0, + /* 232 */ 'l', '6', 0, + /* 235 */ 'f', '1', '7', 0, + /* 239 */ 'f', '2', '7', 0, + /* 243 */ 'f', '7', 0, + /* 246 */ 'g', '7', 0, + /* 249 */ 'i', '7', 0, + /* 252 */ 'l', '7', 0, + /* 255 */ 'o', '7', 0, + /* 258 */ 'f', '1', '8', 0, + /* 262 */ 'f', '2', '8', 0, + /* 266 */ 'f', '3', '8', 0, + /* 270 */ 'f', '4', '8', 0, + /* 274 */ 'f', '5', '8', 0, + /* 278 */ 'f', '8', 0, + /* 281 */ 'f', '1', '9', 0, + /* 285 */ 'f', '2', '9', 0, + /* 289 */ 'f', '9', 0, + /* 292 */ 'i', 'c', 'c', 0, + /* 296 */ 'f', 'p', 0, + /* 299 */ 's', 'p', 0, + /* 302 */ 'y', 0, + }; + + static const uint32_t RegAsmOffset[] = { + 292, 302, 29, 105, 168, 226, 278, 0, 76, 148, 206, 258, 4, 80, + 152, 210, 262, 8, 84, 156, 214, 266, 12, 88, 160, 218, 270, 16, + 92, 164, 222, 274, 20, 96, 29, 61, 105, 133, 168, 191, 226, 243, + 278, 289, 0, 44, 76, 120, 148, 183, 206, 235, 258, 281, 4, 48, + 80, 124, 152, 187, 210, 239, 262, 285, 8, 52, 24, 56, 100, 128, + 32, 64, 108, 136, 171, 194, 229, 246, 35, 67, 111, 139, 174, 197, + 296, 249, 38, 70, 114, 142, 177, 200, 232, 252, 41, 73, 117, 145, + 180, 203, 299, 255, 29, 168, 278, 76, 206, 4, 152, 262, 84, 214, + 12, 160, 270, 92, 222, 20, + }; + + //int i; + //for (i = 0; i < sizeof(RegAsmOffset)/4; i++) + // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1); + //printf("*************************\n"); + return AsmStrs+RegAsmOffset[RegNo-1]; +#else + return NULL; +#endif +} + +#ifdef PRINT_ALIAS_INSTR +#undef PRINT_ALIAS_INSTR + +static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) +{ +#define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) + const char *AsmString; + char *tmp, *AsmMnem, *AsmOps, *c; + switch (MCInst_getOpcode(MI)) { + default: return NULL; + case SP_RESTORErr: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == SP_G0) { + // (RESTORErr G0, G0, G0) + AsmString = "restore"; + break; + } + return NULL; + case SP_RET: + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) { + // (RET 8) + AsmString = "ret"; + break; + } + return NULL; + case SP_RETL: + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) { + // (RETL 8) + AsmString = "retl"; + break; + } + return NULL; + } + + tmp = cs_strdup(AsmString); + AsmMnem = tmp; + AsmOps = strchr(tmp, ' '); + if (AsmOps) { + *AsmOps = '\0'; + AsmOps += 1; + } + SStream_concat(OS, "%s", AsmMnem); + if (AsmOps) { + SStream_concat(OS, "\t"); + for (c = AsmOps; *c; c++) { + if (*c == '$') { + c += 1; + printOperand(MI, *c - 1, OS); + } else { + SStream_concat(OS, "%c", *c); + } + } + } + return tmp; +} + +#endif // PRINT_ALIAS_INSTR diff --git a/arch/Sparc/SparcGenDisassemblerTables.inc b/arch/Sparc/SparcGenDisassemblerTables.inc new file mode 100644 index 0000000000..649b6e02d6 --- /dev/null +++ b/arch/Sparc/SparcGenDisassemblerTables.inc @@ -0,0 +1,2016 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|* * Sparc Disassembler *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2014 */ + +#include "../../MCInst.h" +#include "../../LEB128.h" + +// Helper function for extracting fields from encoded instructions. +#define FieldFromInstruction(fname, InsnType) \ +static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ +{ \ + InsnType fieldMask; \ + if (numBits == sizeof(InsnType)*8) \ + fieldMask = (InsnType)(-1LL); \ + else \ + fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ + return (insn & fieldMask) >> startBit; \ +} + +static uint8_t DecoderTableSparc32[] = { +/* 0 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 3 */ MCD_OPC_FilterValue, 0, 13, 2, // Skip to: 532 +/* 7 */ MCD_OPC_ExtractField, 22, 3, // Inst{24-22} ... +/* 10 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 24 +/* 14 */ MCD_OPC_CheckField, 25, 5, 0, 160, 22, // Skip to: 5812 +/* 20 */ MCD_OPC_Decode, 208, 3, 0, // Opcode: UNIMP +/* 24 */ MCD_OPC_FilterValue, 1, 103, 0, // Skip to: 131 +/* 28 */ MCD_OPC_ExtractField, 19, 3, // Inst{21-19} ... +/* 31 */ MCD_OPC_FilterValue, 0, 25, 0, // Skip to: 60 +/* 35 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... +/* 38 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 49 +/* 42 */ MCD_OPC_CheckPredicate, 0, 134, 22, // Skip to: 5812 +/* 46 */ MCD_OPC_Decode, 91, 1, // Opcode: BPICCNT +/* 49 */ MCD_OPC_FilterValue, 1, 127, 22, // Skip to: 5812 +/* 53 */ MCD_OPC_CheckPredicate, 0, 123, 22, // Skip to: 5812 +/* 57 */ MCD_OPC_Decode, 90, 1, // Opcode: BPICCANT +/* 60 */ MCD_OPC_FilterValue, 1, 25, 0, // Skip to: 89 +/* 64 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... +/* 67 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 78 +/* 71 */ MCD_OPC_CheckPredicate, 0, 105, 22, // Skip to: 5812 +/* 75 */ MCD_OPC_Decode, 88, 1, // Opcode: BPICC +/* 78 */ MCD_OPC_FilterValue, 1, 98, 22, // Skip to: 5812 +/* 82 */ MCD_OPC_CheckPredicate, 0, 94, 22, // Skip to: 5812 +/* 86 */ MCD_OPC_Decode, 89, 1, // Opcode: BPICCA +/* 89 */ MCD_OPC_FilterValue, 4, 17, 0, // Skip to: 110 +/* 93 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... +/* 96 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 103 +/* 100 */ MCD_OPC_Decode, 107, 1, // Opcode: BPXCCNT +/* 103 */ MCD_OPC_FilterValue, 1, 73, 22, // Skip to: 5812 +/* 107 */ MCD_OPC_Decode, 106, 1, // Opcode: BPXCCANT +/* 110 */ MCD_OPC_FilterValue, 5, 66, 22, // Skip to: 5812 +/* 114 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... +/* 117 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 124 +/* 121 */ MCD_OPC_Decode, 104, 1, // Opcode: BPXCC +/* 124 */ MCD_OPC_FilterValue, 1, 52, 22, // Skip to: 5812 +/* 128 */ MCD_OPC_Decode, 105, 1, // Opcode: BPXCCA +/* 131 */ MCD_OPC_FilterValue, 2, 26, 0, // Skip to: 161 +/* 135 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... +/* 138 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 154 +/* 142 */ MCD_OPC_CheckField, 25, 4, 8, 3, 0, // Skip to: 151 +/* 148 */ MCD_OPC_Decode, 70, 0, // Opcode: BA +/* 151 */ MCD_OPC_Decode, 71, 2, // Opcode: BCOND +/* 154 */ MCD_OPC_FilterValue, 1, 22, 22, // Skip to: 5812 +/* 158 */ MCD_OPC_Decode, 72, 2, // Opcode: BCONDA +/* 161 */ MCD_OPC_FilterValue, 3, 255, 0, // Skip to: 420 +/* 165 */ MCD_OPC_ExtractField, 25, 5, // Inst{29-25} ... +/* 168 */ MCD_OPC_FilterValue, 1, 17, 0, // Skip to: 189 +/* 172 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 175 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 182 +/* 179 */ MCD_OPC_Decode, 110, 3, // Opcode: BPZnapn +/* 182 */ MCD_OPC_FilterValue, 1, 250, 21, // Skip to: 5812 +/* 186 */ MCD_OPC_Decode, 111, 3, // Opcode: BPZnapt +/* 189 */ MCD_OPC_FilterValue, 2, 17, 0, // Skip to: 210 +/* 193 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 196 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 203 +/* 200 */ MCD_OPC_Decode, 94, 3, // Opcode: BPLEZnapn +/* 203 */ MCD_OPC_FilterValue, 1, 229, 21, // Skip to: 5812 +/* 207 */ MCD_OPC_Decode, 95, 3, // Opcode: BPLEZnapt +/* 210 */ MCD_OPC_FilterValue, 3, 17, 0, // Skip to: 231 +/* 214 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 217 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 224 +/* 221 */ MCD_OPC_Decode, 98, 3, // Opcode: BPLZnapn +/* 224 */ MCD_OPC_FilterValue, 1, 208, 21, // Skip to: 5812 +/* 228 */ MCD_OPC_Decode, 99, 3, // Opcode: BPLZnapt +/* 231 */ MCD_OPC_FilterValue, 5, 17, 0, // Skip to: 252 +/* 235 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 238 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 245 +/* 242 */ MCD_OPC_Decode, 102, 3, // Opcode: BPNZnapn +/* 245 */ MCD_OPC_FilterValue, 1, 187, 21, // Skip to: 5812 +/* 249 */ MCD_OPC_Decode, 103, 3, // Opcode: BPNZnapt +/* 252 */ MCD_OPC_FilterValue, 6, 17, 0, // Skip to: 273 +/* 256 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 259 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 266 +/* 263 */ MCD_OPC_Decode, 86, 3, // Opcode: BPGZnapn +/* 266 */ MCD_OPC_FilterValue, 1, 166, 21, // Skip to: 5812 +/* 270 */ MCD_OPC_Decode, 87, 3, // Opcode: BPGZnapt +/* 273 */ MCD_OPC_FilterValue, 7, 17, 0, // Skip to: 294 +/* 277 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 280 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 287 +/* 284 */ MCD_OPC_Decode, 82, 3, // Opcode: BPGEZnapn +/* 287 */ MCD_OPC_FilterValue, 1, 145, 21, // Skip to: 5812 +/* 291 */ MCD_OPC_Decode, 83, 3, // Opcode: BPGEZnapt +/* 294 */ MCD_OPC_FilterValue, 17, 17, 0, // Skip to: 315 +/* 298 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 301 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 308 +/* 305 */ MCD_OPC_Decode, 108, 3, // Opcode: BPZapn +/* 308 */ MCD_OPC_FilterValue, 1, 124, 21, // Skip to: 5812 +/* 312 */ MCD_OPC_Decode, 109, 3, // Opcode: BPZapt +/* 315 */ MCD_OPC_FilterValue, 18, 17, 0, // Skip to: 336 +/* 319 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 322 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 329 +/* 326 */ MCD_OPC_Decode, 92, 3, // Opcode: BPLEZapn +/* 329 */ MCD_OPC_FilterValue, 1, 103, 21, // Skip to: 5812 +/* 333 */ MCD_OPC_Decode, 93, 3, // Opcode: BPLEZapt +/* 336 */ MCD_OPC_FilterValue, 19, 17, 0, // Skip to: 357 +/* 340 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 343 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 350 +/* 347 */ MCD_OPC_Decode, 96, 3, // Opcode: BPLZapn +/* 350 */ MCD_OPC_FilterValue, 1, 82, 21, // Skip to: 5812 +/* 354 */ MCD_OPC_Decode, 97, 3, // Opcode: BPLZapt +/* 357 */ MCD_OPC_FilterValue, 21, 17, 0, // Skip to: 378 +/* 361 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 364 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 371 +/* 368 */ MCD_OPC_Decode, 100, 3, // Opcode: BPNZapn +/* 371 */ MCD_OPC_FilterValue, 1, 61, 21, // Skip to: 5812 +/* 375 */ MCD_OPC_Decode, 101, 3, // Opcode: BPNZapt +/* 378 */ MCD_OPC_FilterValue, 22, 17, 0, // Skip to: 399 +/* 382 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 385 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 392 +/* 389 */ MCD_OPC_Decode, 84, 3, // Opcode: BPGZapn +/* 392 */ MCD_OPC_FilterValue, 1, 40, 21, // Skip to: 5812 +/* 396 */ MCD_OPC_Decode, 85, 3, // Opcode: BPGZapt +/* 399 */ MCD_OPC_FilterValue, 23, 33, 21, // Skip to: 5812 +/* 403 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 406 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 413 +/* 410 */ MCD_OPC_Decode, 80, 3, // Opcode: BPGEZapn +/* 413 */ MCD_OPC_FilterValue, 1, 19, 21, // Skip to: 5812 +/* 417 */ MCD_OPC_Decode, 81, 3, // Opcode: BPGEZapt +/* 420 */ MCD_OPC_FilterValue, 4, 20, 0, // Skip to: 444 +/* 424 */ MCD_OPC_CheckField, 25, 5, 0, 10, 0, // Skip to: 440 +/* 430 */ MCD_OPC_CheckField, 0, 22, 0, 4, 0, // Skip to: 440 +/* 436 */ MCD_OPC_Decode, 221, 2, 4, // Opcode: NOP +/* 440 */ MCD_OPC_Decode, 132, 3, 5, // Opcode: SETHIi +/* 444 */ MCD_OPC_FilterValue, 5, 61, 0, // Skip to: 509 +/* 448 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 451 */ MCD_OPC_FilterValue, 0, 25, 0, // Skip to: 480 +/* 455 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... +/* 458 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 469 +/* 462 */ MCD_OPC_CheckPredicate, 0, 226, 20, // Skip to: 5812 +/* 466 */ MCD_OPC_Decode, 79, 6, // Opcode: BPFCCNT +/* 469 */ MCD_OPC_FilterValue, 1, 219, 20, // Skip to: 5812 +/* 473 */ MCD_OPC_CheckPredicate, 0, 215, 20, // Skip to: 5812 +/* 477 */ MCD_OPC_Decode, 78, 6, // Opcode: BPFCCANT +/* 480 */ MCD_OPC_FilterValue, 1, 208, 20, // Skip to: 5812 +/* 484 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... +/* 487 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 498 +/* 491 */ MCD_OPC_CheckPredicate, 0, 197, 20, // Skip to: 5812 +/* 495 */ MCD_OPC_Decode, 76, 6, // Opcode: BPFCC +/* 498 */ MCD_OPC_FilterValue, 1, 190, 20, // Skip to: 5812 +/* 502 */ MCD_OPC_CheckPredicate, 0, 186, 20, // Skip to: 5812 +/* 506 */ MCD_OPC_Decode, 77, 6, // Opcode: BPFCCA +/* 509 */ MCD_OPC_FilterValue, 6, 179, 20, // Skip to: 5812 +/* 513 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... +/* 516 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 524 +/* 520 */ MCD_OPC_Decode, 148, 1, 2, // Opcode: FBCOND +/* 524 */ MCD_OPC_FilterValue, 1, 164, 20, // Skip to: 5812 +/* 528 */ MCD_OPC_Decode, 149, 1, 2, // Opcode: FBCONDA +/* 532 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 539 +/* 536 */ MCD_OPC_Decode, 113, 7, // Opcode: CALL +/* 539 */ MCD_OPC_FilterValue, 2, 84, 18, // Skip to: 5235 +/* 543 */ MCD_OPC_ExtractField, 19, 6, // Inst{24-19} ... +/* 546 */ MCD_OPC_FilterValue, 0, 23, 0, // Skip to: 573 +/* 550 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 553 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 566 +/* 557 */ MCD_OPC_CheckField, 5, 8, 0, 129, 20, // Skip to: 5812 +/* 563 */ MCD_OPC_Decode, 30, 8, // Opcode: ADDrr +/* 566 */ MCD_OPC_FilterValue, 1, 122, 20, // Skip to: 5812 +/* 570 */ MCD_OPC_Decode, 29, 9, // Opcode: ADDri +/* 573 */ MCD_OPC_FilterValue, 1, 23, 0, // Skip to: 600 +/* 577 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 580 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 593 +/* 584 */ MCD_OPC_CheckField, 5, 8, 0, 102, 20, // Skip to: 5812 +/* 590 */ MCD_OPC_Decode, 45, 8, // Opcode: ANDrr +/* 593 */ MCD_OPC_FilterValue, 1, 95, 20, // Skip to: 5812 +/* 597 */ MCD_OPC_Decode, 44, 9, // Opcode: ANDri +/* 600 */ MCD_OPC_FilterValue, 2, 25, 0, // Skip to: 629 +/* 604 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 607 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 621 +/* 611 */ MCD_OPC_CheckField, 5, 8, 0, 75, 20, // Skip to: 5812 +/* 617 */ MCD_OPC_Decode, 232, 2, 8, // Opcode: ORrr +/* 621 */ MCD_OPC_FilterValue, 1, 67, 20, // Skip to: 5812 +/* 625 */ MCD_OPC_Decode, 231, 2, 9, // Opcode: ORri +/* 629 */ MCD_OPC_FilterValue, 3, 25, 0, // Skip to: 658 +/* 633 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 636 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 650 +/* 640 */ MCD_OPC_CheckField, 5, 8, 0, 46, 20, // Skip to: 5812 +/* 646 */ MCD_OPC_Decode, 234, 3, 8, // Opcode: XORrr +/* 650 */ MCD_OPC_FilterValue, 1, 38, 20, // Skip to: 5812 +/* 654 */ MCD_OPC_Decode, 233, 3, 9, // Opcode: XORri +/* 658 */ MCD_OPC_FilterValue, 4, 25, 0, // Skip to: 687 +/* 662 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 665 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 679 +/* 669 */ MCD_OPC_CheckField, 5, 8, 0, 17, 20, // Skip to: 5812 +/* 675 */ MCD_OPC_Decode, 175, 3, 8, // Opcode: SUBrr +/* 679 */ MCD_OPC_FilterValue, 1, 9, 20, // Skip to: 5812 +/* 683 */ MCD_OPC_Decode, 174, 3, 9, // Opcode: SUBri +/* 687 */ MCD_OPC_FilterValue, 5, 23, 0, // Skip to: 714 +/* 691 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 694 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 707 +/* 698 */ MCD_OPC_CheckField, 5, 8, 0, 244, 19, // Skip to: 5812 +/* 704 */ MCD_OPC_Decode, 40, 8, // Opcode: ANDNrr +/* 707 */ MCD_OPC_FilterValue, 1, 237, 19, // Skip to: 5812 +/* 711 */ MCD_OPC_Decode, 39, 9, // Opcode: ANDNri +/* 714 */ MCD_OPC_FilterValue, 6, 25, 0, // Skip to: 743 +/* 718 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 721 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 735 +/* 725 */ MCD_OPC_CheckField, 5, 8, 0, 217, 19, // Skip to: 5812 +/* 731 */ MCD_OPC_Decode, 227, 2, 8, // Opcode: ORNrr +/* 735 */ MCD_OPC_FilterValue, 1, 209, 19, // Skip to: 5812 +/* 739 */ MCD_OPC_Decode, 226, 2, 9, // Opcode: ORNri +/* 743 */ MCD_OPC_FilterValue, 7, 25, 0, // Skip to: 772 +/* 747 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 750 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 764 +/* 754 */ MCD_OPC_CheckField, 5, 8, 0, 188, 19, // Skip to: 5812 +/* 760 */ MCD_OPC_Decode, 228, 3, 8, // Opcode: XNORrr +/* 764 */ MCD_OPC_FilterValue, 1, 180, 19, // Skip to: 5812 +/* 768 */ MCD_OPC_Decode, 227, 3, 9, // Opcode: XNORri +/* 772 */ MCD_OPC_FilterValue, 8, 23, 0, // Skip to: 799 +/* 776 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 779 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 792 +/* 783 */ MCD_OPC_CheckField, 5, 8, 0, 159, 19, // Skip to: 5812 +/* 789 */ MCD_OPC_Decode, 22, 8, // Opcode: ADDCrr +/* 792 */ MCD_OPC_FilterValue, 1, 152, 19, // Skip to: 5812 +/* 796 */ MCD_OPC_Decode, 21, 9, // Opcode: ADDCri +/* 799 */ MCD_OPC_FilterValue, 9, 25, 0, // Skip to: 828 +/* 803 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 806 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 820 +/* 810 */ MCD_OPC_CheckField, 5, 8, 0, 132, 19, // Skip to: 5812 +/* 816 */ MCD_OPC_Decode, 220, 2, 10, // Opcode: MULXrr +/* 820 */ MCD_OPC_FilterValue, 1, 124, 19, // Skip to: 5812 +/* 824 */ MCD_OPC_Decode, 219, 2, 11, // Opcode: MULXri +/* 828 */ MCD_OPC_FilterValue, 10, 25, 0, // Skip to: 857 +/* 832 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 835 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 849 +/* 839 */ MCD_OPC_CheckField, 5, 8, 0, 103, 19, // Skip to: 5812 +/* 845 */ MCD_OPC_Decode, 207, 3, 8, // Opcode: UMULrr +/* 849 */ MCD_OPC_FilterValue, 1, 95, 19, // Skip to: 5812 +/* 853 */ MCD_OPC_Decode, 206, 3, 9, // Opcode: UMULri +/* 857 */ MCD_OPC_FilterValue, 11, 25, 0, // Skip to: 886 +/* 861 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 864 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 878 +/* 868 */ MCD_OPC_CheckField, 5, 8, 0, 74, 19, // Skip to: 5812 +/* 874 */ MCD_OPC_Decode, 142, 3, 8, // Opcode: SMULrr +/* 878 */ MCD_OPC_FilterValue, 1, 66, 19, // Skip to: 5812 +/* 882 */ MCD_OPC_Decode, 141, 3, 9, // Opcode: SMULri +/* 886 */ MCD_OPC_FilterValue, 12, 25, 0, // Skip to: 915 +/* 890 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 893 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 907 +/* 897 */ MCD_OPC_CheckField, 5, 8, 0, 45, 19, // Skip to: 5812 +/* 903 */ MCD_OPC_Decode, 169, 3, 8, // Opcode: SUBCrr +/* 907 */ MCD_OPC_FilterValue, 1, 37, 19, // Skip to: 5812 +/* 911 */ MCD_OPC_Decode, 168, 3, 9, // Opcode: SUBCri +/* 915 */ MCD_OPC_FilterValue, 13, 25, 0, // Skip to: 944 +/* 919 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 922 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 936 +/* 926 */ MCD_OPC_CheckField, 5, 8, 0, 16, 19, // Skip to: 5812 +/* 932 */ MCD_OPC_Decode, 200, 3, 10, // Opcode: UDIVXrr +/* 936 */ MCD_OPC_FilterValue, 1, 8, 19, // Skip to: 5812 +/* 940 */ MCD_OPC_Decode, 199, 3, 11, // Opcode: UDIVXri +/* 944 */ MCD_OPC_FilterValue, 14, 25, 0, // Skip to: 973 +/* 948 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 951 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 965 +/* 955 */ MCD_OPC_CheckField, 5, 8, 0, 243, 18, // Skip to: 5812 +/* 961 */ MCD_OPC_Decode, 202, 3, 8, // Opcode: UDIVrr +/* 965 */ MCD_OPC_FilterValue, 1, 235, 18, // Skip to: 5812 +/* 969 */ MCD_OPC_Decode, 201, 3, 9, // Opcode: UDIVri +/* 973 */ MCD_OPC_FilterValue, 15, 25, 0, // Skip to: 1002 +/* 977 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 980 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 994 +/* 984 */ MCD_OPC_CheckField, 5, 8, 0, 214, 18, // Skip to: 5812 +/* 990 */ MCD_OPC_Decode, 250, 2, 8, // Opcode: SDIVrr +/* 994 */ MCD_OPC_FilterValue, 1, 206, 18, // Skip to: 5812 +/* 998 */ MCD_OPC_Decode, 249, 2, 9, // Opcode: SDIVri +/* 1002 */ MCD_OPC_FilterValue, 16, 23, 0, // Skip to: 1029 +/* 1006 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1009 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1022 +/* 1013 */ MCD_OPC_CheckField, 5, 8, 0, 185, 18, // Skip to: 5812 +/* 1019 */ MCD_OPC_Decode, 20, 8, // Opcode: ADDCCrr +/* 1022 */ MCD_OPC_FilterValue, 1, 178, 18, // Skip to: 5812 +/* 1026 */ MCD_OPC_Decode, 19, 9, // Opcode: ADDCCri +/* 1029 */ MCD_OPC_FilterValue, 17, 23, 0, // Skip to: 1056 +/* 1033 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1036 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1049 +/* 1040 */ MCD_OPC_CheckField, 5, 8, 0, 158, 18, // Skip to: 5812 +/* 1046 */ MCD_OPC_Decode, 36, 8, // Opcode: ANDCCrr +/* 1049 */ MCD_OPC_FilterValue, 1, 151, 18, // Skip to: 5812 +/* 1053 */ MCD_OPC_Decode, 35, 9, // Opcode: ANDCCri +/* 1056 */ MCD_OPC_FilterValue, 18, 25, 0, // Skip to: 1085 +/* 1060 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1063 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1077 +/* 1067 */ MCD_OPC_CheckField, 5, 8, 0, 131, 18, // Skip to: 5812 +/* 1073 */ MCD_OPC_Decode, 223, 2, 8, // Opcode: ORCCrr +/* 1077 */ MCD_OPC_FilterValue, 1, 123, 18, // Skip to: 5812 +/* 1081 */ MCD_OPC_Decode, 222, 2, 9, // Opcode: ORCCri +/* 1085 */ MCD_OPC_FilterValue, 19, 25, 0, // Skip to: 1114 +/* 1089 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1092 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1106 +/* 1096 */ MCD_OPC_CheckField, 5, 8, 0, 102, 18, // Skip to: 5812 +/* 1102 */ MCD_OPC_Decode, 230, 3, 8, // Opcode: XORCCrr +/* 1106 */ MCD_OPC_FilterValue, 1, 94, 18, // Skip to: 5812 +/* 1110 */ MCD_OPC_Decode, 229, 3, 9, // Opcode: XORCCri +/* 1114 */ MCD_OPC_FilterValue, 20, 44, 0, // Skip to: 1162 +/* 1118 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1121 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 1145 +/* 1125 */ MCD_OPC_ExtractField, 5, 8, // Inst{12-5} ... +/* 1128 */ MCD_OPC_FilterValue, 0, 72, 18, // Skip to: 5812 +/* 1132 */ MCD_OPC_CheckField, 25, 5, 0, 3, 0, // Skip to: 1141 +/* 1138 */ MCD_OPC_Decode, 122, 12, // Opcode: CMPrr +/* 1141 */ MCD_OPC_Decode, 167, 3, 8, // Opcode: SUBCCrr +/* 1145 */ MCD_OPC_FilterValue, 1, 55, 18, // Skip to: 5812 +/* 1149 */ MCD_OPC_CheckField, 25, 5, 0, 3, 0, // Skip to: 1158 +/* 1155 */ MCD_OPC_Decode, 121, 13, // Opcode: CMPri +/* 1158 */ MCD_OPC_Decode, 166, 3, 9, // Opcode: SUBCCri +/* 1162 */ MCD_OPC_FilterValue, 21, 23, 0, // Skip to: 1189 +/* 1166 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1169 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1182 +/* 1173 */ MCD_OPC_CheckField, 5, 8, 0, 25, 18, // Skip to: 5812 +/* 1179 */ MCD_OPC_Decode, 38, 8, // Opcode: ANDNCCrr +/* 1182 */ MCD_OPC_FilterValue, 1, 18, 18, // Skip to: 5812 +/* 1186 */ MCD_OPC_Decode, 37, 9, // Opcode: ANDNCCri +/* 1189 */ MCD_OPC_FilterValue, 22, 25, 0, // Skip to: 1218 +/* 1193 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1196 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1210 +/* 1200 */ MCD_OPC_CheckField, 5, 8, 0, 254, 17, // Skip to: 5812 +/* 1206 */ MCD_OPC_Decode, 225, 2, 8, // Opcode: ORNCCrr +/* 1210 */ MCD_OPC_FilterValue, 1, 246, 17, // Skip to: 5812 +/* 1214 */ MCD_OPC_Decode, 224, 2, 9, // Opcode: ORNCCri +/* 1218 */ MCD_OPC_FilterValue, 23, 25, 0, // Skip to: 1247 +/* 1222 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1225 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1239 +/* 1229 */ MCD_OPC_CheckField, 5, 8, 0, 225, 17, // Skip to: 5812 +/* 1235 */ MCD_OPC_Decode, 225, 3, 8, // Opcode: XNORCCrr +/* 1239 */ MCD_OPC_FilterValue, 1, 217, 17, // Skip to: 5812 +/* 1243 */ MCD_OPC_Decode, 224, 3, 9, // Opcode: XNORCCri +/* 1247 */ MCD_OPC_FilterValue, 24, 23, 0, // Skip to: 1274 +/* 1251 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1254 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1267 +/* 1258 */ MCD_OPC_CheckField, 5, 8, 0, 196, 17, // Skip to: 5812 +/* 1264 */ MCD_OPC_Decode, 24, 8, // Opcode: ADDErr +/* 1267 */ MCD_OPC_FilterValue, 1, 189, 17, // Skip to: 5812 +/* 1271 */ MCD_OPC_Decode, 23, 9, // Opcode: ADDEri +/* 1274 */ MCD_OPC_FilterValue, 26, 25, 0, // Skip to: 1303 +/* 1278 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1281 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1295 +/* 1285 */ MCD_OPC_CheckField, 5, 8, 0, 169, 17, // Skip to: 5812 +/* 1291 */ MCD_OPC_Decode, 204, 3, 8, // Opcode: UMULCCrr +/* 1295 */ MCD_OPC_FilterValue, 1, 161, 17, // Skip to: 5812 +/* 1299 */ MCD_OPC_Decode, 203, 3, 9, // Opcode: UMULCCri +/* 1303 */ MCD_OPC_FilterValue, 27, 25, 0, // Skip to: 1332 +/* 1307 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1310 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1324 +/* 1314 */ MCD_OPC_CheckField, 5, 8, 0, 140, 17, // Skip to: 5812 +/* 1320 */ MCD_OPC_Decode, 140, 3, 8, // Opcode: SMULCCrr +/* 1324 */ MCD_OPC_FilterValue, 1, 132, 17, // Skip to: 5812 +/* 1328 */ MCD_OPC_Decode, 139, 3, 9, // Opcode: SMULCCri +/* 1332 */ MCD_OPC_FilterValue, 28, 25, 0, // Skip to: 1361 +/* 1336 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1339 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1353 +/* 1343 */ MCD_OPC_CheckField, 5, 8, 0, 111, 17, // Skip to: 5812 +/* 1349 */ MCD_OPC_Decode, 171, 3, 8, // Opcode: SUBErr +/* 1353 */ MCD_OPC_FilterValue, 1, 103, 17, // Skip to: 5812 +/* 1357 */ MCD_OPC_Decode, 170, 3, 9, // Opcode: SUBEri +/* 1361 */ MCD_OPC_FilterValue, 30, 25, 0, // Skip to: 1390 +/* 1365 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1368 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1382 +/* 1372 */ MCD_OPC_CheckField, 5, 8, 0, 82, 17, // Skip to: 5812 +/* 1378 */ MCD_OPC_Decode, 198, 3, 8, // Opcode: UDIVCCrr +/* 1382 */ MCD_OPC_FilterValue, 1, 74, 17, // Skip to: 5812 +/* 1386 */ MCD_OPC_Decode, 197, 3, 9, // Opcode: UDIVCCri +/* 1390 */ MCD_OPC_FilterValue, 31, 25, 0, // Skip to: 1419 +/* 1394 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1397 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1411 +/* 1401 */ MCD_OPC_CheckField, 5, 8, 0, 53, 17, // Skip to: 5812 +/* 1407 */ MCD_OPC_Decode, 246, 2, 8, // Opcode: SDIVCCrr +/* 1411 */ MCD_OPC_FilterValue, 1, 45, 17, // Skip to: 5812 +/* 1415 */ MCD_OPC_Decode, 245, 2, 9, // Opcode: SDIVCCri +/* 1419 */ MCD_OPC_FilterValue, 32, 25, 0, // Skip to: 1448 +/* 1423 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1426 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1440 +/* 1430 */ MCD_OPC_CheckField, 5, 8, 0, 24, 17, // Skip to: 5812 +/* 1436 */ MCD_OPC_Decode, 183, 3, 8, // Opcode: TADDCCrr +/* 1440 */ MCD_OPC_FilterValue, 1, 16, 17, // Skip to: 5812 +/* 1444 */ MCD_OPC_Decode, 182, 3, 9, // Opcode: TADDCCri +/* 1448 */ MCD_OPC_FilterValue, 33, 25, 0, // Skip to: 1477 +/* 1452 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1455 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1469 +/* 1459 */ MCD_OPC_CheckField, 5, 8, 0, 251, 16, // Skip to: 5812 +/* 1465 */ MCD_OPC_Decode, 194, 3, 8, // Opcode: TSUBCCrr +/* 1469 */ MCD_OPC_FilterValue, 1, 243, 16, // Skip to: 5812 +/* 1473 */ MCD_OPC_Decode, 193, 3, 9, // Opcode: TSUBCCri +/* 1477 */ MCD_OPC_FilterValue, 34, 25, 0, // Skip to: 1506 +/* 1481 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1484 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1498 +/* 1488 */ MCD_OPC_CheckField, 5, 8, 0, 222, 16, // Skip to: 5812 +/* 1494 */ MCD_OPC_Decode, 181, 3, 8, // Opcode: TADDCCTVrr +/* 1498 */ MCD_OPC_FilterValue, 1, 214, 16, // Skip to: 5812 +/* 1502 */ MCD_OPC_Decode, 180, 3, 9, // Opcode: TADDCCTVri +/* 1506 */ MCD_OPC_FilterValue, 35, 25, 0, // Skip to: 1535 +/* 1510 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1513 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1527 +/* 1517 */ MCD_OPC_CheckField, 5, 8, 0, 193, 16, // Skip to: 5812 +/* 1523 */ MCD_OPC_Decode, 192, 3, 8, // Opcode: TSUBCCTVrr +/* 1527 */ MCD_OPC_FilterValue, 1, 185, 16, // Skip to: 5812 +/* 1531 */ MCD_OPC_Decode, 191, 3, 9, // Opcode: TSUBCCTVri +/* 1535 */ MCD_OPC_FilterValue, 37, 50, 0, // Skip to: 1589 +/* 1539 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1542 */ MCD_OPC_FilterValue, 0, 25, 0, // Skip to: 1571 +/* 1546 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 1549 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1563 +/* 1553 */ MCD_OPC_CheckField, 5, 7, 0, 157, 16, // Skip to: 5812 +/* 1559 */ MCD_OPC_Decode, 138, 3, 8, // Opcode: SLLrr +/* 1563 */ MCD_OPC_FilterValue, 1, 149, 16, // Skip to: 5812 +/* 1567 */ MCD_OPC_Decode, 136, 3, 14, // Opcode: SLLXrr +/* 1571 */ MCD_OPC_FilterValue, 1, 141, 16, // Skip to: 5812 +/* 1575 */ MCD_OPC_CheckField, 12, 1, 1, 4, 0, // Skip to: 1585 +/* 1581 */ MCD_OPC_Decode, 135, 3, 15, // Opcode: SLLXri +/* 1585 */ MCD_OPC_Decode, 137, 3, 9, // Opcode: SLLri +/* 1589 */ MCD_OPC_FilterValue, 38, 50, 0, // Skip to: 1643 +/* 1593 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1596 */ MCD_OPC_FilterValue, 0, 25, 0, // Skip to: 1625 +/* 1600 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 1603 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1617 +/* 1607 */ MCD_OPC_CheckField, 5, 7, 0, 103, 16, // Skip to: 5812 +/* 1613 */ MCD_OPC_Decode, 150, 3, 8, // Opcode: SRLrr +/* 1617 */ MCD_OPC_FilterValue, 1, 95, 16, // Skip to: 5812 +/* 1621 */ MCD_OPC_Decode, 148, 3, 14, // Opcode: SRLXrr +/* 1625 */ MCD_OPC_FilterValue, 1, 87, 16, // Skip to: 5812 +/* 1629 */ MCD_OPC_CheckField, 12, 1, 1, 4, 0, // Skip to: 1639 +/* 1635 */ MCD_OPC_Decode, 147, 3, 15, // Opcode: SRLXri +/* 1639 */ MCD_OPC_Decode, 149, 3, 9, // Opcode: SRLri +/* 1643 */ MCD_OPC_FilterValue, 39, 50, 0, // Skip to: 1697 +/* 1647 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1650 */ MCD_OPC_FilterValue, 0, 25, 0, // Skip to: 1679 +/* 1654 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 1657 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1671 +/* 1661 */ MCD_OPC_CheckField, 5, 7, 0, 49, 16, // Skip to: 5812 +/* 1667 */ MCD_OPC_Decode, 146, 3, 8, // Opcode: SRArr +/* 1671 */ MCD_OPC_FilterValue, 1, 41, 16, // Skip to: 5812 +/* 1675 */ MCD_OPC_Decode, 144, 3, 14, // Opcode: SRAXrr +/* 1679 */ MCD_OPC_FilterValue, 1, 33, 16, // Skip to: 5812 +/* 1683 */ MCD_OPC_CheckField, 12, 1, 1, 4, 0, // Skip to: 1693 +/* 1689 */ MCD_OPC_Decode, 143, 3, 15, // Opcode: SRAXri +/* 1693 */ MCD_OPC_Decode, 145, 3, 9, // Opcode: SRAri +/* 1697 */ MCD_OPC_FilterValue, 40, 55, 0, // Skip to: 1756 +/* 1701 */ MCD_OPC_ExtractField, 13, 6, // Inst{18-13} ... +/* 1704 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1718 +/* 1708 */ MCD_OPC_CheckField, 0, 13, 0, 2, 16, // Skip to: 5812 +/* 1714 */ MCD_OPC_Decode, 236, 2, 4, // Opcode: RDY +/* 1718 */ MCD_OPC_FilterValue, 30, 16, 0, // Skip to: 1738 +/* 1722 */ MCD_OPC_CheckField, 25, 5, 0, 244, 15, // Skip to: 5812 +/* 1728 */ MCD_OPC_CheckField, 0, 13, 0, 238, 15, // Skip to: 5812 +/* 1734 */ MCD_OPC_Decode, 151, 3, 4, // Opcode: STBAR +/* 1738 */ MCD_OPC_FilterValue, 31, 230, 15, // Skip to: 5812 +/* 1742 */ MCD_OPC_CheckPredicate, 0, 226, 15, // Skip to: 5812 +/* 1746 */ MCD_OPC_CheckField, 25, 5, 0, 220, 15, // Skip to: 5812 +/* 1752 */ MCD_OPC_Decode, 195, 2, 16, // Opcode: MEMBARi +/* 1756 */ MCD_OPC_FilterValue, 43, 20, 0, // Skip to: 1780 +/* 1760 */ MCD_OPC_CheckPredicate, 0, 208, 15, // Skip to: 5812 +/* 1764 */ MCD_OPC_CheckField, 25, 5, 0, 202, 15, // Skip to: 5812 +/* 1770 */ MCD_OPC_CheckField, 0, 19, 0, 196, 15, // Skip to: 5812 +/* 1776 */ MCD_OPC_Decode, 180, 1, 4, // Opcode: FLUSHW +/* 1780 */ MCD_OPC_FilterValue, 44, 123, 0, // Skip to: 1907 +/* 1784 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1787 */ MCD_OPC_FilterValue, 0, 56, 0, // Skip to: 1847 +/* 1791 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... +/* 1794 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 1820 +/* 1798 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 1812 +/* 1802 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 1812 +/* 1808 */ MCD_OPC_Decode, 198, 2, 17, // Opcode: MOVFCCrr +/* 1812 */ MCD_OPC_CheckPredicate, 0, 156, 15, // Skip to: 5812 +/* 1816 */ MCD_OPC_Decode, 219, 3, 18, // Opcode: V9MOVFCCrr +/* 1820 */ MCD_OPC_FilterValue, 1, 148, 15, // Skip to: 5812 +/* 1824 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... +/* 1827 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1839 +/* 1831 */ MCD_OPC_CheckPredicate, 0, 137, 15, // Skip to: 5812 +/* 1835 */ MCD_OPC_Decode, 200, 2, 17, // Opcode: MOVICCrr +/* 1839 */ MCD_OPC_FilterValue, 2, 129, 15, // Skip to: 5812 +/* 1843 */ MCD_OPC_Decode, 217, 2, 17, // Opcode: MOVXCCrr +/* 1847 */ MCD_OPC_FilterValue, 1, 121, 15, // Skip to: 5812 +/* 1851 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... +/* 1854 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 1880 +/* 1858 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 1872 +/* 1862 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 1872 +/* 1868 */ MCD_OPC_Decode, 197, 2, 19, // Opcode: MOVFCCri +/* 1872 */ MCD_OPC_CheckPredicate, 0, 96, 15, // Skip to: 5812 +/* 1876 */ MCD_OPC_Decode, 218, 3, 20, // Opcode: V9MOVFCCri +/* 1880 */ MCD_OPC_FilterValue, 1, 88, 15, // Skip to: 5812 +/* 1884 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... +/* 1887 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1899 +/* 1891 */ MCD_OPC_CheckPredicate, 0, 77, 15, // Skip to: 5812 +/* 1895 */ MCD_OPC_Decode, 199, 2, 19, // Opcode: MOVICCri +/* 1899 */ MCD_OPC_FilterValue, 2, 69, 15, // Skip to: 5812 +/* 1903 */ MCD_OPC_Decode, 216, 2, 19, // Opcode: MOVXCCri +/* 1907 */ MCD_OPC_FilterValue, 45, 25, 0, // Skip to: 1936 +/* 1911 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1914 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1928 +/* 1918 */ MCD_OPC_CheckField, 5, 8, 0, 48, 15, // Skip to: 5812 +/* 1924 */ MCD_OPC_Decode, 248, 2, 10, // Opcode: SDIVXrr +/* 1928 */ MCD_OPC_FilterValue, 1, 40, 15, // Skip to: 5812 +/* 1932 */ MCD_OPC_Decode, 247, 2, 11, // Opcode: SDIVXri +/* 1936 */ MCD_OPC_FilterValue, 46, 14, 0, // Skip to: 1954 +/* 1940 */ MCD_OPC_CheckPredicate, 0, 28, 15, // Skip to: 5812 +/* 1944 */ MCD_OPC_CheckField, 5, 14, 0, 22, 15, // Skip to: 5812 +/* 1950 */ MCD_OPC_Decode, 235, 2, 4, // Opcode: POPCrr +/* 1954 */ MCD_OPC_FilterValue, 47, 135, 0, // Skip to: 2093 +/* 1958 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... +/* 1961 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 1975 +/* 1965 */ MCD_OPC_CheckField, 5, 5, 0, 1, 15, // Skip to: 5812 +/* 1971 */ MCD_OPC_Decode, 212, 2, 14, // Opcode: MOVRRZrr +/* 1975 */ MCD_OPC_FilterValue, 2, 10, 0, // Skip to: 1989 +/* 1979 */ MCD_OPC_CheckField, 5, 5, 0, 243, 14, // Skip to: 5812 +/* 1985 */ MCD_OPC_Decode, 206, 2, 14, // Opcode: MOVRLEZrr +/* 1989 */ MCD_OPC_FilterValue, 3, 10, 0, // Skip to: 2003 +/* 1993 */ MCD_OPC_CheckField, 5, 5, 0, 229, 14, // Skip to: 5812 +/* 1999 */ MCD_OPC_Decode, 208, 2, 14, // Opcode: MOVRLZrr +/* 2003 */ MCD_OPC_FilterValue, 5, 10, 0, // Skip to: 2017 +/* 2007 */ MCD_OPC_CheckField, 5, 5, 0, 215, 14, // Skip to: 5812 +/* 2013 */ MCD_OPC_Decode, 210, 2, 14, // Opcode: MOVRNZrr +/* 2017 */ MCD_OPC_FilterValue, 6, 10, 0, // Skip to: 2031 +/* 2021 */ MCD_OPC_CheckField, 5, 5, 0, 201, 14, // Skip to: 5812 +/* 2027 */ MCD_OPC_Decode, 204, 2, 14, // Opcode: MOVRGZrr +/* 2031 */ MCD_OPC_FilterValue, 7, 10, 0, // Skip to: 2045 +/* 2035 */ MCD_OPC_CheckField, 5, 5, 0, 187, 14, // Skip to: 5812 +/* 2041 */ MCD_OPC_Decode, 202, 2, 14, // Opcode: MOVRGEZrr +/* 2045 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 2053 +/* 2049 */ MCD_OPC_Decode, 211, 2, 21, // Opcode: MOVRRZri +/* 2053 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 2061 +/* 2057 */ MCD_OPC_Decode, 205, 2, 21, // Opcode: MOVRLEZri +/* 2061 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 2069 +/* 2065 */ MCD_OPC_Decode, 207, 2, 21, // Opcode: MOVRLZri +/* 2069 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 2077 +/* 2073 */ MCD_OPC_Decode, 209, 2, 21, // Opcode: MOVRNZri +/* 2077 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 2085 +/* 2081 */ MCD_OPC_Decode, 203, 2, 21, // Opcode: MOVRGZri +/* 2085 */ MCD_OPC_FilterValue, 15, 139, 14, // Skip to: 5812 +/* 2089 */ MCD_OPC_Decode, 201, 2, 21, // Opcode: MOVRGEZri +/* 2093 */ MCD_OPC_FilterValue, 48, 37, 0, // Skip to: 2134 +/* 2097 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 2100 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 2120 +/* 2104 */ MCD_OPC_CheckField, 25, 5, 0, 118, 14, // Skip to: 5812 +/* 2110 */ MCD_OPC_CheckField, 5, 8, 0, 112, 14, // Skip to: 5812 +/* 2116 */ MCD_OPC_Decode, 221, 3, 12, // Opcode: WRYrr +/* 2120 */ MCD_OPC_FilterValue, 1, 104, 14, // Skip to: 5812 +/* 2124 */ MCD_OPC_CheckField, 25, 5, 0, 98, 14, // Skip to: 5812 +/* 2130 */ MCD_OPC_Decode, 220, 3, 13, // Opcode: WRYri +/* 2134 */ MCD_OPC_FilterValue, 52, 197, 2, // Skip to: 2847 +/* 2138 */ MCD_OPC_ExtractField, 5, 9, // Inst{13-5} ... +/* 2141 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 2155 +/* 2145 */ MCD_OPC_CheckField, 14, 5, 0, 77, 14, // Skip to: 5812 +/* 2151 */ MCD_OPC_Decode, 208, 1, 22, // Opcode: FMOVS +/* 2155 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 2173 +/* 2159 */ MCD_OPC_CheckPredicate, 0, 65, 14, // Skip to: 5812 +/* 2163 */ MCD_OPC_CheckField, 14, 5, 0, 59, 14, // Skip to: 5812 +/* 2169 */ MCD_OPC_Decode, 182, 1, 23, // Opcode: FMOVD +/* 2173 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 2191 +/* 2177 */ MCD_OPC_CheckPredicate, 0, 47, 14, // Skip to: 5812 +/* 2181 */ MCD_OPC_CheckField, 14, 5, 0, 41, 14, // Skip to: 5812 +/* 2187 */ MCD_OPC_Decode, 186, 1, 24, // Opcode: FMOVQ +/* 2191 */ MCD_OPC_FilterValue, 5, 10, 0, // Skip to: 2205 +/* 2195 */ MCD_OPC_CheckField, 14, 5, 0, 27, 14, // Skip to: 5812 +/* 2201 */ MCD_OPC_Decode, 228, 1, 22, // Opcode: FNEGS +/* 2205 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 2223 +/* 2209 */ MCD_OPC_CheckPredicate, 0, 15, 14, // Skip to: 5812 +/* 2213 */ MCD_OPC_CheckField, 14, 5, 0, 9, 14, // Skip to: 5812 +/* 2219 */ MCD_OPC_Decode, 226, 1, 23, // Opcode: FNEGD +/* 2223 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 2241 +/* 2227 */ MCD_OPC_CheckPredicate, 0, 253, 13, // Skip to: 5812 +/* 2231 */ MCD_OPC_CheckField, 14, 5, 0, 247, 13, // Skip to: 5812 +/* 2237 */ MCD_OPC_Decode, 227, 1, 24, // Opcode: FNEGQ +/* 2241 */ MCD_OPC_FilterValue, 9, 10, 0, // Skip to: 2255 +/* 2245 */ MCD_OPC_CheckField, 14, 5, 0, 233, 13, // Skip to: 5812 +/* 2251 */ MCD_OPC_Decode, 137, 1, 22, // Opcode: FABSS +/* 2255 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 2273 +/* 2259 */ MCD_OPC_CheckPredicate, 0, 221, 13, // Skip to: 5812 +/* 2263 */ MCD_OPC_CheckField, 14, 5, 0, 215, 13, // Skip to: 5812 +/* 2269 */ MCD_OPC_Decode, 135, 1, 23, // Opcode: FABSD +/* 2273 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 2291 +/* 2277 */ MCD_OPC_CheckPredicate, 0, 203, 13, // Skip to: 5812 +/* 2281 */ MCD_OPC_CheckField, 14, 5, 0, 197, 13, // Skip to: 5812 +/* 2287 */ MCD_OPC_Decode, 136, 1, 24, // Opcode: FABSQ +/* 2291 */ MCD_OPC_FilterValue, 41, 10, 0, // Skip to: 2305 +/* 2295 */ MCD_OPC_CheckField, 14, 5, 0, 183, 13, // Skip to: 5812 +/* 2301 */ MCD_OPC_Decode, 144, 2, 22, // Opcode: FSQRTS +/* 2305 */ MCD_OPC_FilterValue, 42, 10, 0, // Skip to: 2319 +/* 2309 */ MCD_OPC_CheckField, 14, 5, 0, 169, 13, // Skip to: 5812 +/* 2315 */ MCD_OPC_Decode, 142, 2, 23, // Opcode: FSQRTD +/* 2319 */ MCD_OPC_FilterValue, 43, 10, 0, // Skip to: 2333 +/* 2323 */ MCD_OPC_CheckField, 14, 5, 0, 155, 13, // Skip to: 5812 +/* 2329 */ MCD_OPC_Decode, 143, 2, 24, // Opcode: FSQRTQ +/* 2333 */ MCD_OPC_FilterValue, 65, 4, 0, // Skip to: 2341 +/* 2337 */ MCD_OPC_Decode, 140, 1, 25, // Opcode: FADDS +/* 2341 */ MCD_OPC_FilterValue, 66, 4, 0, // Skip to: 2349 +/* 2345 */ MCD_OPC_Decode, 138, 1, 26, // Opcode: FADDD +/* 2349 */ MCD_OPC_FilterValue, 67, 4, 0, // Skip to: 2357 +/* 2353 */ MCD_OPC_Decode, 139, 1, 27, // Opcode: FADDQ +/* 2357 */ MCD_OPC_FilterValue, 69, 4, 0, // Skip to: 2365 +/* 2361 */ MCD_OPC_Decode, 159, 2, 25, // Opcode: FSUBS +/* 2365 */ MCD_OPC_FilterValue, 70, 4, 0, // Skip to: 2373 +/* 2369 */ MCD_OPC_Decode, 157, 2, 26, // Opcode: FSUBD +/* 2373 */ MCD_OPC_FilterValue, 71, 4, 0, // Skip to: 2381 +/* 2377 */ MCD_OPC_Decode, 158, 2, 27, // Opcode: FSUBQ +/* 2381 */ MCD_OPC_FilterValue, 73, 4, 0, // Skip to: 2389 +/* 2385 */ MCD_OPC_Decode, 221, 1, 25, // Opcode: FMULS +/* 2389 */ MCD_OPC_FilterValue, 74, 4, 0, // Skip to: 2397 +/* 2393 */ MCD_OPC_Decode, 217, 1, 26, // Opcode: FMULD +/* 2397 */ MCD_OPC_FilterValue, 75, 4, 0, // Skip to: 2405 +/* 2401 */ MCD_OPC_Decode, 220, 1, 27, // Opcode: FMULQ +/* 2405 */ MCD_OPC_FilterValue, 77, 4, 0, // Skip to: 2413 +/* 2409 */ MCD_OPC_Decode, 164, 1, 25, // Opcode: FDIVS +/* 2413 */ MCD_OPC_FilterValue, 78, 4, 0, // Skip to: 2421 +/* 2417 */ MCD_OPC_Decode, 162, 1, 26, // Opcode: FDIVD +/* 2421 */ MCD_OPC_FilterValue, 79, 4, 0, // Skip to: 2429 +/* 2425 */ MCD_OPC_Decode, 163, 1, 27, // Opcode: FDIVQ +/* 2429 */ MCD_OPC_FilterValue, 81, 8, 0, // Skip to: 2441 +/* 2433 */ MCD_OPC_CheckPredicate, 1, 47, 13, // Skip to: 5812 +/* 2437 */ MCD_OPC_Decode, 223, 1, 26, // Opcode: FNADDS +/* 2441 */ MCD_OPC_FilterValue, 82, 8, 0, // Skip to: 2453 +/* 2445 */ MCD_OPC_CheckPredicate, 1, 35, 13, // Skip to: 5812 +/* 2449 */ MCD_OPC_Decode, 222, 1, 26, // Opcode: FNADDD +/* 2453 */ MCD_OPC_FilterValue, 89, 8, 0, // Skip to: 2465 +/* 2457 */ MCD_OPC_CheckPredicate, 1, 23, 13, // Skip to: 5812 +/* 2461 */ MCD_OPC_Decode, 232, 1, 26, // Opcode: FNMULS +/* 2465 */ MCD_OPC_FilterValue, 90, 8, 0, // Skip to: 2477 +/* 2469 */ MCD_OPC_CheckPredicate, 1, 11, 13, // Skip to: 5812 +/* 2473 */ MCD_OPC_Decode, 231, 1, 26, // Opcode: FNMULD +/* 2477 */ MCD_OPC_FilterValue, 97, 8, 0, // Skip to: 2489 +/* 2481 */ MCD_OPC_CheckPredicate, 1, 255, 12, // Skip to: 5812 +/* 2485 */ MCD_OPC_Decode, 172, 1, 26, // Opcode: FHADDS +/* 2489 */ MCD_OPC_FilterValue, 98, 8, 0, // Skip to: 2501 +/* 2493 */ MCD_OPC_CheckPredicate, 1, 243, 12, // Skip to: 5812 +/* 2497 */ MCD_OPC_Decode, 171, 1, 26, // Opcode: FHADDD +/* 2501 */ MCD_OPC_FilterValue, 101, 8, 0, // Skip to: 2513 +/* 2505 */ MCD_OPC_CheckPredicate, 1, 231, 12, // Skip to: 5812 +/* 2509 */ MCD_OPC_Decode, 174, 1, 26, // Opcode: FHSUBS +/* 2513 */ MCD_OPC_FilterValue, 102, 8, 0, // Skip to: 2525 +/* 2517 */ MCD_OPC_CheckPredicate, 1, 219, 12, // Skip to: 5812 +/* 2521 */ MCD_OPC_Decode, 173, 1, 26, // Opcode: FHSUBD +/* 2525 */ MCD_OPC_FilterValue, 105, 4, 0, // Skip to: 2533 +/* 2529 */ MCD_OPC_Decode, 141, 2, 28, // Opcode: FSMULD +/* 2533 */ MCD_OPC_FilterValue, 110, 4, 0, // Skip to: 2541 +/* 2537 */ MCD_OPC_Decode, 165, 1, 29, // Opcode: FDMULQ +/* 2541 */ MCD_OPC_FilterValue, 113, 8, 0, // Skip to: 2553 +/* 2545 */ MCD_OPC_CheckPredicate, 1, 191, 12, // Skip to: 5812 +/* 2549 */ MCD_OPC_Decode, 230, 1, 26, // Opcode: FNHADDS +/* 2553 */ MCD_OPC_FilterValue, 114, 8, 0, // Skip to: 2565 +/* 2557 */ MCD_OPC_CheckPredicate, 1, 179, 12, // Skip to: 5812 +/* 2561 */ MCD_OPC_Decode, 229, 1, 26, // Opcode: FNHADDD +/* 2565 */ MCD_OPC_FilterValue, 121, 8, 0, // Skip to: 2577 +/* 2569 */ MCD_OPC_CheckPredicate, 1, 167, 12, // Skip to: 5812 +/* 2573 */ MCD_OPC_Decode, 239, 1, 26, // Opcode: FNSMULD +/* 2577 */ MCD_OPC_FilterValue, 129, 1, 10, 0, // Skip to: 2592 +/* 2582 */ MCD_OPC_CheckField, 14, 5, 0, 152, 12, // Skip to: 5812 +/* 2588 */ MCD_OPC_Decode, 156, 2, 30, // Opcode: FSTOX +/* 2592 */ MCD_OPC_FilterValue, 130, 1, 10, 0, // Skip to: 2607 +/* 2597 */ MCD_OPC_CheckField, 14, 5, 0, 137, 12, // Skip to: 5812 +/* 2603 */ MCD_OPC_Decode, 169, 1, 23, // Opcode: FDTOX +/* 2607 */ MCD_OPC_FilterValue, 131, 1, 10, 0, // Skip to: 2622 +/* 2612 */ MCD_OPC_CheckField, 14, 5, 0, 122, 12, // Skip to: 5812 +/* 2618 */ MCD_OPC_Decode, 136, 2, 31, // Opcode: FQTOX +/* 2622 */ MCD_OPC_FilterValue, 132, 1, 10, 0, // Skip to: 2637 +/* 2627 */ MCD_OPC_CheckField, 14, 5, 0, 107, 12, // Skip to: 5812 +/* 2633 */ MCD_OPC_Decode, 166, 2, 32, // Opcode: FXTOS +/* 2637 */ MCD_OPC_FilterValue, 136, 1, 10, 0, // Skip to: 2652 +/* 2642 */ MCD_OPC_CheckField, 14, 5, 0, 92, 12, // Skip to: 5812 +/* 2648 */ MCD_OPC_Decode, 164, 2, 23, // Opcode: FXTOD +/* 2652 */ MCD_OPC_FilterValue, 140, 1, 10, 0, // Skip to: 2667 +/* 2657 */ MCD_OPC_CheckField, 14, 5, 0, 77, 12, // Skip to: 5812 +/* 2663 */ MCD_OPC_Decode, 165, 2, 33, // Opcode: FXTOQ +/* 2667 */ MCD_OPC_FilterValue, 196, 1, 10, 0, // Skip to: 2682 +/* 2672 */ MCD_OPC_CheckField, 14, 5, 0, 62, 12, // Skip to: 5812 +/* 2678 */ MCD_OPC_Decode, 177, 1, 22, // Opcode: FITOS +/* 2682 */ MCD_OPC_FilterValue, 198, 1, 10, 0, // Skip to: 2697 +/* 2687 */ MCD_OPC_CheckField, 14, 5, 0, 47, 12, // Skip to: 5812 +/* 2693 */ MCD_OPC_Decode, 168, 1, 32, // Opcode: FDTOS +/* 2697 */ MCD_OPC_FilterValue, 199, 1, 10, 0, // Skip to: 2712 +/* 2702 */ MCD_OPC_CheckField, 14, 5, 0, 32, 12, // Skip to: 5812 +/* 2708 */ MCD_OPC_Decode, 135, 2, 34, // Opcode: FQTOS +/* 2712 */ MCD_OPC_FilterValue, 200, 1, 10, 0, // Skip to: 2727 +/* 2717 */ MCD_OPC_CheckField, 14, 5, 0, 17, 12, // Skip to: 5812 +/* 2723 */ MCD_OPC_Decode, 175, 1, 30, // Opcode: FITOD +/* 2727 */ MCD_OPC_FilterValue, 201, 1, 10, 0, // Skip to: 2742 +/* 2732 */ MCD_OPC_CheckField, 14, 5, 0, 2, 12, // Skip to: 5812 +/* 2738 */ MCD_OPC_Decode, 153, 2, 30, // Opcode: FSTOD +/* 2742 */ MCD_OPC_FilterValue, 203, 1, 10, 0, // Skip to: 2757 +/* 2747 */ MCD_OPC_CheckField, 14, 5, 0, 243, 11, // Skip to: 5812 +/* 2753 */ MCD_OPC_Decode, 133, 2, 31, // Opcode: FQTOD +/* 2757 */ MCD_OPC_FilterValue, 204, 1, 10, 0, // Skip to: 2772 +/* 2762 */ MCD_OPC_CheckField, 14, 5, 0, 228, 11, // Skip to: 5812 +/* 2768 */ MCD_OPC_Decode, 176, 1, 35, // Opcode: FITOQ +/* 2772 */ MCD_OPC_FilterValue, 205, 1, 10, 0, // Skip to: 2787 +/* 2777 */ MCD_OPC_CheckField, 14, 5, 0, 213, 11, // Skip to: 5812 +/* 2783 */ MCD_OPC_Decode, 155, 2, 35, // Opcode: FSTOQ +/* 2787 */ MCD_OPC_FilterValue, 206, 1, 10, 0, // Skip to: 2802 +/* 2792 */ MCD_OPC_CheckField, 14, 5, 0, 198, 11, // Skip to: 5812 +/* 2798 */ MCD_OPC_Decode, 167, 1, 33, // Opcode: FDTOQ +/* 2802 */ MCD_OPC_FilterValue, 209, 1, 10, 0, // Skip to: 2817 +/* 2807 */ MCD_OPC_CheckField, 14, 5, 0, 183, 11, // Skip to: 5812 +/* 2813 */ MCD_OPC_Decode, 154, 2, 22, // Opcode: FSTOI +/* 2817 */ MCD_OPC_FilterValue, 210, 1, 10, 0, // Skip to: 2832 +/* 2822 */ MCD_OPC_CheckField, 14, 5, 0, 168, 11, // Skip to: 5812 +/* 2828 */ MCD_OPC_Decode, 166, 1, 32, // Opcode: FDTOI +/* 2832 */ MCD_OPC_FilterValue, 211, 1, 159, 11, // Skip to: 5812 +/* 2837 */ MCD_OPC_CheckField, 14, 5, 0, 153, 11, // Skip to: 5812 +/* 2843 */ MCD_OPC_Decode, 134, 2, 34, // Opcode: FQTOI +/* 2847 */ MCD_OPC_FilterValue, 53, 70, 2, // Skip to: 3433 +/* 2851 */ MCD_OPC_ExtractField, 5, 6, // Inst{10-5} ... +/* 2854 */ MCD_OPC_FilterValue, 1, 75, 0, // Skip to: 2933 +/* 2858 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 2861 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 2894 +/* 2865 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... +/* 2868 */ MCD_OPC_FilterValue, 0, 124, 11, // Skip to: 5812 +/* 2872 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 2886 +/* 2876 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 2886 +/* 2882 */ MCD_OPC_Decode, 209, 1, 36, // Opcode: FMOVS_FCC +/* 2886 */ MCD_OPC_CheckPredicate, 0, 106, 11, // Skip to: 5812 +/* 2890 */ MCD_OPC_Decode, 217, 3, 37, // Opcode: V9FMOVS_FCC +/* 2894 */ MCD_OPC_FilterValue, 1, 98, 11, // Skip to: 5812 +/* 2898 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... +/* 2901 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 2919 +/* 2905 */ MCD_OPC_CheckPredicate, 0, 87, 11, // Skip to: 5812 +/* 2909 */ MCD_OPC_CheckField, 18, 1, 0, 81, 11, // Skip to: 5812 +/* 2915 */ MCD_OPC_Decode, 210, 1, 36, // Opcode: FMOVS_ICC +/* 2919 */ MCD_OPC_FilterValue, 2, 73, 11, // Skip to: 5812 +/* 2923 */ MCD_OPC_CheckField, 18, 1, 0, 67, 11, // Skip to: 5812 +/* 2929 */ MCD_OPC_Decode, 211, 1, 36, // Opcode: FMOVS_XCC +/* 2933 */ MCD_OPC_FilterValue, 2, 75, 0, // Skip to: 3012 +/* 2937 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 2940 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 2973 +/* 2944 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... +/* 2947 */ MCD_OPC_FilterValue, 0, 45, 11, // Skip to: 5812 +/* 2951 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 2965 +/* 2955 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 2965 +/* 2961 */ MCD_OPC_Decode, 183, 1, 38, // Opcode: FMOVD_FCC +/* 2965 */ MCD_OPC_CheckPredicate, 0, 27, 11, // Skip to: 5812 +/* 2969 */ MCD_OPC_Decode, 215, 3, 39, // Opcode: V9FMOVD_FCC +/* 2973 */ MCD_OPC_FilterValue, 1, 19, 11, // Skip to: 5812 +/* 2977 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... +/* 2980 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 2998 +/* 2984 */ MCD_OPC_CheckPredicate, 0, 8, 11, // Skip to: 5812 +/* 2988 */ MCD_OPC_CheckField, 18, 1, 0, 2, 11, // Skip to: 5812 +/* 2994 */ MCD_OPC_Decode, 184, 1, 38, // Opcode: FMOVD_ICC +/* 2998 */ MCD_OPC_FilterValue, 2, 250, 10, // Skip to: 5812 +/* 3002 */ MCD_OPC_CheckField, 18, 1, 0, 244, 10, // Skip to: 5812 +/* 3008 */ MCD_OPC_Decode, 185, 1, 38, // Opcode: FMOVD_XCC +/* 3012 */ MCD_OPC_FilterValue, 3, 75, 0, // Skip to: 3091 +/* 3016 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 3019 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 3052 +/* 3023 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... +/* 3026 */ MCD_OPC_FilterValue, 0, 222, 10, // Skip to: 5812 +/* 3030 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 3044 +/* 3034 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3044 +/* 3040 */ MCD_OPC_Decode, 187, 1, 40, // Opcode: FMOVQ_FCC +/* 3044 */ MCD_OPC_CheckPredicate, 0, 204, 10, // Skip to: 5812 +/* 3048 */ MCD_OPC_Decode, 216, 3, 41, // Opcode: V9FMOVQ_FCC +/* 3052 */ MCD_OPC_FilterValue, 1, 196, 10, // Skip to: 5812 +/* 3056 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... +/* 3059 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3077 +/* 3063 */ MCD_OPC_CheckPredicate, 0, 185, 10, // Skip to: 5812 +/* 3067 */ MCD_OPC_CheckField, 18, 1, 0, 179, 10, // Skip to: 5812 +/* 3073 */ MCD_OPC_Decode, 188, 1, 40, // Opcode: FMOVQ_ICC +/* 3077 */ MCD_OPC_FilterValue, 2, 171, 10, // Skip to: 5812 +/* 3081 */ MCD_OPC_CheckField, 18, 1, 0, 165, 10, // Skip to: 5812 +/* 3087 */ MCD_OPC_Decode, 189, 1, 40, // Opcode: FMOVQ_XCC +/* 3091 */ MCD_OPC_FilterValue, 5, 27, 0, // Skip to: 3122 +/* 3095 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 3098 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3110 +/* 3102 */ MCD_OPC_CheckPredicate, 0, 146, 10, // Skip to: 5812 +/* 3106 */ MCD_OPC_Decode, 198, 1, 42, // Opcode: FMOVRLEZS +/* 3110 */ MCD_OPC_FilterValue, 3, 138, 10, // Skip to: 5812 +/* 3114 */ MCD_OPC_CheckPredicate, 0, 134, 10, // Skip to: 5812 +/* 3118 */ MCD_OPC_Decode, 195, 1, 42, // Opcode: FMOVRGZS +/* 3122 */ MCD_OPC_FilterValue, 6, 27, 0, // Skip to: 3153 +/* 3126 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 3129 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3141 +/* 3133 */ MCD_OPC_CheckPredicate, 0, 115, 10, // Skip to: 5812 +/* 3137 */ MCD_OPC_Decode, 196, 1, 42, // Opcode: FMOVRLEZD +/* 3141 */ MCD_OPC_FilterValue, 3, 107, 10, // Skip to: 5812 +/* 3145 */ MCD_OPC_CheckPredicate, 0, 103, 10, // Skip to: 5812 +/* 3149 */ MCD_OPC_Decode, 193, 1, 42, // Opcode: FMOVRGZD +/* 3153 */ MCD_OPC_FilterValue, 7, 27, 0, // Skip to: 3184 +/* 3157 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 3160 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3172 +/* 3164 */ MCD_OPC_CheckPredicate, 0, 84, 10, // Skip to: 5812 +/* 3168 */ MCD_OPC_Decode, 197, 1, 42, // Opcode: FMOVRLEZQ +/* 3172 */ MCD_OPC_FilterValue, 3, 76, 10, // Skip to: 5812 +/* 3176 */ MCD_OPC_CheckPredicate, 0, 72, 10, // Skip to: 5812 +/* 3180 */ MCD_OPC_Decode, 194, 1, 42, // Opcode: FMOVRGZQ +/* 3184 */ MCD_OPC_FilterValue, 17, 10, 0, // Skip to: 3198 +/* 3188 */ MCD_OPC_CheckField, 11, 3, 1, 58, 10, // Skip to: 5812 +/* 3194 */ MCD_OPC_Decode, 214, 3, 43, // Opcode: V9FCMPS +/* 3198 */ MCD_OPC_FilterValue, 18, 10, 0, // Skip to: 3212 +/* 3202 */ MCD_OPC_CheckField, 11, 3, 1, 44, 10, // Skip to: 5812 +/* 3208 */ MCD_OPC_Decode, 209, 3, 44, // Opcode: V9FCMPD +/* 3212 */ MCD_OPC_FilterValue, 19, 10, 0, // Skip to: 3226 +/* 3216 */ MCD_OPC_CheckField, 11, 3, 1, 30, 10, // Skip to: 5812 +/* 3222 */ MCD_OPC_Decode, 213, 3, 45, // Opcode: V9FCMPQ +/* 3226 */ MCD_OPC_FilterValue, 21, 10, 0, // Skip to: 3240 +/* 3230 */ MCD_OPC_CheckField, 11, 3, 1, 16, 10, // Skip to: 5812 +/* 3236 */ MCD_OPC_Decode, 212, 3, 43, // Opcode: V9FCMPES +/* 3240 */ MCD_OPC_FilterValue, 22, 10, 0, // Skip to: 3254 +/* 3244 */ MCD_OPC_CheckField, 11, 3, 1, 2, 10, // Skip to: 5812 +/* 3250 */ MCD_OPC_Decode, 210, 3, 44, // Opcode: V9FCMPED +/* 3254 */ MCD_OPC_FilterValue, 23, 10, 0, // Skip to: 3268 +/* 3258 */ MCD_OPC_CheckField, 11, 3, 1, 244, 9, // Skip to: 5812 +/* 3264 */ MCD_OPC_Decode, 211, 3, 45, // Opcode: V9FCMPEQ +/* 3268 */ MCD_OPC_FilterValue, 37, 51, 0, // Skip to: 3323 +/* 3272 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 3275 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3287 +/* 3279 */ MCD_OPC_CheckPredicate, 0, 225, 9, // Skip to: 5812 +/* 3283 */ MCD_OPC_Decode, 207, 1, 42, // Opcode: FMOVRZS +/* 3287 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3299 +/* 3291 */ MCD_OPC_CheckPredicate, 0, 213, 9, // Skip to: 5812 +/* 3295 */ MCD_OPC_Decode, 201, 1, 42, // Opcode: FMOVRLZS +/* 3299 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3311 +/* 3303 */ MCD_OPC_CheckPredicate, 0, 201, 9, // Skip to: 5812 +/* 3307 */ MCD_OPC_Decode, 204, 1, 42, // Opcode: FMOVRNZS +/* 3311 */ MCD_OPC_FilterValue, 3, 193, 9, // Skip to: 5812 +/* 3315 */ MCD_OPC_CheckPredicate, 0, 189, 9, // Skip to: 5812 +/* 3319 */ MCD_OPC_Decode, 192, 1, 42, // Opcode: FMOVRGEZS +/* 3323 */ MCD_OPC_FilterValue, 38, 51, 0, // Skip to: 3378 +/* 3327 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 3330 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3342 +/* 3334 */ MCD_OPC_CheckPredicate, 0, 170, 9, // Skip to: 5812 +/* 3338 */ MCD_OPC_Decode, 205, 1, 42, // Opcode: FMOVRZD +/* 3342 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3354 +/* 3346 */ MCD_OPC_CheckPredicate, 0, 158, 9, // Skip to: 5812 +/* 3350 */ MCD_OPC_Decode, 199, 1, 42, // Opcode: FMOVRLZD +/* 3354 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3366 +/* 3358 */ MCD_OPC_CheckPredicate, 0, 146, 9, // Skip to: 5812 +/* 3362 */ MCD_OPC_Decode, 202, 1, 42, // Opcode: FMOVRNZD +/* 3366 */ MCD_OPC_FilterValue, 3, 138, 9, // Skip to: 5812 +/* 3370 */ MCD_OPC_CheckPredicate, 0, 134, 9, // Skip to: 5812 +/* 3374 */ MCD_OPC_Decode, 190, 1, 42, // Opcode: FMOVRGEZD +/* 3378 */ MCD_OPC_FilterValue, 39, 126, 9, // Skip to: 5812 +/* 3382 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 3385 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3397 +/* 3389 */ MCD_OPC_CheckPredicate, 0, 115, 9, // Skip to: 5812 +/* 3393 */ MCD_OPC_Decode, 206, 1, 42, // Opcode: FMOVRZQ +/* 3397 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3409 +/* 3401 */ MCD_OPC_CheckPredicate, 0, 103, 9, // Skip to: 5812 +/* 3405 */ MCD_OPC_Decode, 200, 1, 42, // Opcode: FMOVRLZQ +/* 3409 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3421 +/* 3413 */ MCD_OPC_CheckPredicate, 0, 91, 9, // Skip to: 5812 +/* 3417 */ MCD_OPC_Decode, 203, 1, 42, // Opcode: FMOVRNZQ +/* 3421 */ MCD_OPC_FilterValue, 3, 83, 9, // Skip to: 5812 +/* 3425 */ MCD_OPC_CheckPredicate, 0, 79, 9, // Skip to: 5812 +/* 3429 */ MCD_OPC_Decode, 191, 1, 42, // Opcode: FMOVRGEZQ +/* 3433 */ MCD_OPC_FilterValue, 54, 15, 6, // Skip to: 4988 +/* 3437 */ MCD_OPC_ExtractField, 5, 9, // Inst{13-5} ... +/* 3440 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3452 +/* 3444 */ MCD_OPC_CheckPredicate, 2, 60, 9, // Skip to: 5812 +/* 3448 */ MCD_OPC_Decode, 131, 1, 10, // Opcode: EDGE8 +/* 3452 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3464 +/* 3456 */ MCD_OPC_CheckPredicate, 3, 48, 9, // Skip to: 5812 +/* 3460 */ MCD_OPC_Decode, 134, 1, 10, // Opcode: EDGE8N +/* 3464 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3476 +/* 3468 */ MCD_OPC_CheckPredicate, 2, 36, 9, // Skip to: 5812 +/* 3472 */ MCD_OPC_Decode, 132, 1, 10, // Opcode: EDGE8L +/* 3476 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 3488 +/* 3480 */ MCD_OPC_CheckPredicate, 3, 24, 9, // Skip to: 5812 +/* 3484 */ MCD_OPC_Decode, 133, 1, 10, // Opcode: EDGE8LN +/* 3488 */ MCD_OPC_FilterValue, 4, 7, 0, // Skip to: 3499 +/* 3492 */ MCD_OPC_CheckPredicate, 2, 12, 9, // Skip to: 5812 +/* 3496 */ MCD_OPC_Decode, 123, 10, // Opcode: EDGE16 +/* 3499 */ MCD_OPC_FilterValue, 5, 7, 0, // Skip to: 3510 +/* 3503 */ MCD_OPC_CheckPredicate, 3, 1, 9, // Skip to: 5812 +/* 3507 */ MCD_OPC_Decode, 126, 10, // Opcode: EDGE16N +/* 3510 */ MCD_OPC_FilterValue, 6, 7, 0, // Skip to: 3521 +/* 3514 */ MCD_OPC_CheckPredicate, 2, 246, 8, // Skip to: 5812 +/* 3518 */ MCD_OPC_Decode, 124, 10, // Opcode: EDGE16L +/* 3521 */ MCD_OPC_FilterValue, 7, 7, 0, // Skip to: 3532 +/* 3525 */ MCD_OPC_CheckPredicate, 3, 235, 8, // Skip to: 5812 +/* 3529 */ MCD_OPC_Decode, 125, 10, // Opcode: EDGE16LN +/* 3532 */ MCD_OPC_FilterValue, 8, 7, 0, // Skip to: 3543 +/* 3536 */ MCD_OPC_CheckPredicate, 2, 224, 8, // Skip to: 5812 +/* 3540 */ MCD_OPC_Decode, 127, 10, // Opcode: EDGE32 +/* 3543 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 3555 +/* 3547 */ MCD_OPC_CheckPredicate, 3, 213, 8, // Skip to: 5812 +/* 3551 */ MCD_OPC_Decode, 130, 1, 10, // Opcode: EDGE32N +/* 3555 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 3567 +/* 3559 */ MCD_OPC_CheckPredicate, 2, 201, 8, // Skip to: 5812 +/* 3563 */ MCD_OPC_Decode, 128, 1, 10, // Opcode: EDGE32L +/* 3567 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 3579 +/* 3571 */ MCD_OPC_CheckPredicate, 3, 189, 8, // Skip to: 5812 +/* 3575 */ MCD_OPC_Decode, 129, 1, 10, // Opcode: EDGE32LN +/* 3579 */ MCD_OPC_FilterValue, 16, 7, 0, // Skip to: 3590 +/* 3583 */ MCD_OPC_CheckPredicate, 2, 177, 8, // Skip to: 5812 +/* 3587 */ MCD_OPC_Decode, 48, 10, // Opcode: ARRAY8 +/* 3590 */ MCD_OPC_FilterValue, 17, 7, 0, // Skip to: 3601 +/* 3594 */ MCD_OPC_CheckPredicate, 1, 166, 8, // Skip to: 5812 +/* 3598 */ MCD_OPC_Decode, 25, 10, // Opcode: ADDXC +/* 3601 */ MCD_OPC_FilterValue, 18, 7, 0, // Skip to: 3612 +/* 3605 */ MCD_OPC_CheckPredicate, 2, 155, 8, // Skip to: 5812 +/* 3609 */ MCD_OPC_Decode, 46, 10, // Opcode: ARRAY16 +/* 3612 */ MCD_OPC_FilterValue, 19, 7, 0, // Skip to: 3623 +/* 3616 */ MCD_OPC_CheckPredicate, 1, 144, 8, // Skip to: 5812 +/* 3620 */ MCD_OPC_Decode, 26, 10, // Opcode: ADDXCCC +/* 3623 */ MCD_OPC_FilterValue, 20, 7, 0, // Skip to: 3634 +/* 3627 */ MCD_OPC_CheckPredicate, 2, 133, 8, // Skip to: 5812 +/* 3631 */ MCD_OPC_Decode, 47, 10, // Opcode: ARRAY32 +/* 3634 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 3646 +/* 3638 */ MCD_OPC_CheckPredicate, 1, 122, 8, // Skip to: 5812 +/* 3642 */ MCD_OPC_Decode, 205, 3, 10, // Opcode: UMULXHI +/* 3646 */ MCD_OPC_FilterValue, 23, 14, 0, // Skip to: 3664 +/* 3650 */ MCD_OPC_CheckPredicate, 1, 110, 8, // Skip to: 5812 +/* 3654 */ MCD_OPC_CheckField, 14, 5, 0, 104, 8, // Skip to: 5812 +/* 3660 */ MCD_OPC_Decode, 194, 2, 46, // Opcode: LZCNT +/* 3664 */ MCD_OPC_FilterValue, 24, 7, 0, // Skip to: 3675 +/* 3668 */ MCD_OPC_CheckPredicate, 2, 92, 8, // Skip to: 5812 +/* 3672 */ MCD_OPC_Decode, 33, 10, // Opcode: ALIGNADDR +/* 3675 */ MCD_OPC_FilterValue, 25, 7, 0, // Skip to: 3686 +/* 3679 */ MCD_OPC_CheckPredicate, 3, 81, 8, // Skip to: 5812 +/* 3683 */ MCD_OPC_Decode, 75, 10, // Opcode: BMASK +/* 3686 */ MCD_OPC_FilterValue, 26, 7, 0, // Skip to: 3697 +/* 3690 */ MCD_OPC_CheckPredicate, 2, 70, 8, // Skip to: 5812 +/* 3694 */ MCD_OPC_Decode, 34, 10, // Opcode: ALIGNADDRL +/* 3697 */ MCD_OPC_FilterValue, 27, 19, 0, // Skip to: 3720 +/* 3701 */ MCD_OPC_CheckPredicate, 1, 59, 8, // Skip to: 5812 +/* 3705 */ MCD_OPC_CheckField, 25, 5, 0, 53, 8, // Skip to: 5812 +/* 3711 */ MCD_OPC_CheckField, 14, 5, 0, 47, 8, // Skip to: 5812 +/* 3717 */ MCD_OPC_Decode, 120, 47, // Opcode: CMASK8 +/* 3720 */ MCD_OPC_FilterValue, 28, 7, 0, // Skip to: 3731 +/* 3724 */ MCD_OPC_CheckPredicate, 3, 36, 8, // Skip to: 5812 +/* 3728 */ MCD_OPC_Decode, 112, 26, // Opcode: BSHUFFLE +/* 3731 */ MCD_OPC_FilterValue, 29, 19, 0, // Skip to: 3754 +/* 3735 */ MCD_OPC_CheckPredicate, 1, 25, 8, // Skip to: 5812 +/* 3739 */ MCD_OPC_CheckField, 25, 5, 0, 19, 8, // Skip to: 5812 +/* 3745 */ MCD_OPC_CheckField, 14, 5, 0, 13, 8, // Skip to: 5812 +/* 3751 */ MCD_OPC_Decode, 118, 47, // Opcode: CMASK16 +/* 3754 */ MCD_OPC_FilterValue, 31, 19, 0, // Skip to: 3777 +/* 3758 */ MCD_OPC_CheckPredicate, 1, 2, 8, // Skip to: 5812 +/* 3762 */ MCD_OPC_CheckField, 25, 5, 0, 252, 7, // Skip to: 5812 +/* 3768 */ MCD_OPC_CheckField, 14, 5, 0, 246, 7, // Skip to: 5812 +/* 3774 */ MCD_OPC_Decode, 119, 47, // Opcode: CMASK32 +/* 3777 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 3789 +/* 3781 */ MCD_OPC_CheckPredicate, 2, 235, 7, // Skip to: 5812 +/* 3785 */ MCD_OPC_Decode, 156, 1, 48, // Opcode: FCMPLE16 +/* 3789 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 3801 +/* 3793 */ MCD_OPC_CheckPredicate, 1, 223, 7, // Skip to: 5812 +/* 3797 */ MCD_OPC_Decode, 139, 2, 26, // Opcode: FSLL16 +/* 3801 */ MCD_OPC_FilterValue, 34, 8, 0, // Skip to: 3813 +/* 3805 */ MCD_OPC_CheckPredicate, 2, 211, 7, // Skip to: 5812 +/* 3809 */ MCD_OPC_Decode, 158, 1, 48, // Opcode: FCMPNE16 +/* 3813 */ MCD_OPC_FilterValue, 35, 8, 0, // Skip to: 3825 +/* 3817 */ MCD_OPC_CheckPredicate, 1, 199, 7, // Skip to: 5812 +/* 3821 */ MCD_OPC_Decode, 151, 2, 26, // Opcode: FSRL16 +/* 3825 */ MCD_OPC_FilterValue, 36, 8, 0, // Skip to: 3837 +/* 3829 */ MCD_OPC_CheckPredicate, 2, 187, 7, // Skip to: 5812 +/* 3833 */ MCD_OPC_Decode, 157, 1, 48, // Opcode: FCMPLE32 +/* 3837 */ MCD_OPC_FilterValue, 37, 8, 0, // Skip to: 3849 +/* 3841 */ MCD_OPC_CheckPredicate, 1, 175, 7, // Skip to: 5812 +/* 3845 */ MCD_OPC_Decode, 140, 2, 26, // Opcode: FSLL32 +/* 3849 */ MCD_OPC_FilterValue, 38, 8, 0, // Skip to: 3861 +/* 3853 */ MCD_OPC_CheckPredicate, 2, 163, 7, // Skip to: 5812 +/* 3857 */ MCD_OPC_Decode, 159, 1, 48, // Opcode: FCMPNE32 +/* 3861 */ MCD_OPC_FilterValue, 39, 8, 0, // Skip to: 3873 +/* 3865 */ MCD_OPC_CheckPredicate, 1, 151, 7, // Skip to: 5812 +/* 3869 */ MCD_OPC_Decode, 152, 2, 26, // Opcode: FSRL32 +/* 3873 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 3885 +/* 3877 */ MCD_OPC_CheckPredicate, 2, 139, 7, // Skip to: 5812 +/* 3881 */ MCD_OPC_Decode, 154, 1, 48, // Opcode: FCMPGT16 +/* 3885 */ MCD_OPC_FilterValue, 41, 8, 0, // Skip to: 3897 +/* 3889 */ MCD_OPC_CheckPredicate, 1, 127, 7, // Skip to: 5812 +/* 3893 */ MCD_OPC_Decode, 137, 2, 26, // Opcode: FSLAS16 +/* 3897 */ MCD_OPC_FilterValue, 42, 8, 0, // Skip to: 3909 +/* 3901 */ MCD_OPC_CheckPredicate, 2, 115, 7, // Skip to: 5812 +/* 3905 */ MCD_OPC_Decode, 152, 1, 48, // Opcode: FCMPEQ16 +/* 3909 */ MCD_OPC_FilterValue, 43, 8, 0, // Skip to: 3921 +/* 3913 */ MCD_OPC_CheckPredicate, 1, 103, 7, // Skip to: 5812 +/* 3917 */ MCD_OPC_Decode, 145, 2, 26, // Opcode: FSRA16 +/* 3921 */ MCD_OPC_FilterValue, 44, 8, 0, // Skip to: 3933 +/* 3925 */ MCD_OPC_CheckPredicate, 2, 91, 7, // Skip to: 5812 +/* 3929 */ MCD_OPC_Decode, 155, 1, 48, // Opcode: FCMPGT32 +/* 3933 */ MCD_OPC_FilterValue, 45, 8, 0, // Skip to: 3945 +/* 3937 */ MCD_OPC_CheckPredicate, 1, 79, 7, // Skip to: 5812 +/* 3941 */ MCD_OPC_Decode, 138, 2, 26, // Opcode: FSLAS32 +/* 3945 */ MCD_OPC_FilterValue, 46, 8, 0, // Skip to: 3957 +/* 3949 */ MCD_OPC_CheckPredicate, 2, 67, 7, // Skip to: 5812 +/* 3953 */ MCD_OPC_Decode, 153, 1, 48, // Opcode: FCMPEQ32 +/* 3957 */ MCD_OPC_FilterValue, 47, 8, 0, // Skip to: 3969 +/* 3961 */ MCD_OPC_CheckPredicate, 1, 55, 7, // Skip to: 5812 +/* 3965 */ MCD_OPC_Decode, 146, 2, 26, // Opcode: FSRA32 +/* 3969 */ MCD_OPC_FilterValue, 49, 8, 0, // Skip to: 3981 +/* 3973 */ MCD_OPC_CheckPredicate, 2, 43, 7, // Skip to: 5812 +/* 3977 */ MCD_OPC_Decode, 214, 1, 26, // Opcode: FMUL8X16 +/* 3981 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 3993 +/* 3985 */ MCD_OPC_CheckPredicate, 2, 31, 7, // Skip to: 5812 +/* 3989 */ MCD_OPC_Decode, 216, 1, 26, // Opcode: FMUL8X16AU +/* 3993 */ MCD_OPC_FilterValue, 53, 8, 0, // Skip to: 4005 +/* 3997 */ MCD_OPC_CheckPredicate, 2, 19, 7, // Skip to: 5812 +/* 4001 */ MCD_OPC_Decode, 215, 1, 26, // Opcode: FMUL8X16AL +/* 4005 */ MCD_OPC_FilterValue, 54, 8, 0, // Skip to: 4017 +/* 4009 */ MCD_OPC_CheckPredicate, 2, 7, 7, // Skip to: 5812 +/* 4013 */ MCD_OPC_Decode, 212, 1, 26, // Opcode: FMUL8SUX16 +/* 4017 */ MCD_OPC_FilterValue, 55, 8, 0, // Skip to: 4029 +/* 4021 */ MCD_OPC_CheckPredicate, 2, 251, 6, // Skip to: 5812 +/* 4025 */ MCD_OPC_Decode, 213, 1, 26, // Opcode: FMUL8ULX16 +/* 4029 */ MCD_OPC_FilterValue, 56, 8, 0, // Skip to: 4041 +/* 4033 */ MCD_OPC_CheckPredicate, 2, 239, 6, // Skip to: 5812 +/* 4037 */ MCD_OPC_Decode, 218, 1, 26, // Opcode: FMULD8SUX16 +/* 4041 */ MCD_OPC_FilterValue, 57, 8, 0, // Skip to: 4053 +/* 4045 */ MCD_OPC_CheckPredicate, 2, 227, 6, // Skip to: 5812 +/* 4049 */ MCD_OPC_Decode, 219, 1, 26, // Opcode: FMULD8ULX16 +/* 4053 */ MCD_OPC_FilterValue, 58, 8, 0, // Skip to: 4065 +/* 4057 */ MCD_OPC_CheckPredicate, 2, 215, 6, // Skip to: 5812 +/* 4061 */ MCD_OPC_Decode, 249, 1, 26, // Opcode: FPACK32 +/* 4065 */ MCD_OPC_FilterValue, 59, 14, 0, // Skip to: 4083 +/* 4069 */ MCD_OPC_CheckPredicate, 2, 203, 6, // Skip to: 5812 +/* 4073 */ MCD_OPC_CheckField, 14, 5, 0, 197, 6, // Skip to: 5812 +/* 4079 */ MCD_OPC_Decode, 248, 1, 23, // Opcode: FPACK16 +/* 4083 */ MCD_OPC_FilterValue, 61, 14, 0, // Skip to: 4101 +/* 4087 */ MCD_OPC_CheckPredicate, 2, 185, 6, // Skip to: 5812 +/* 4091 */ MCD_OPC_CheckField, 14, 5, 0, 179, 6, // Skip to: 5812 +/* 4097 */ MCD_OPC_Decode, 250, 1, 23, // Opcode: FPACKFIX +/* 4101 */ MCD_OPC_FilterValue, 62, 8, 0, // Skip to: 4113 +/* 4105 */ MCD_OPC_CheckPredicate, 2, 167, 6, // Skip to: 5812 +/* 4109 */ MCD_OPC_Decode, 233, 2, 26, // Opcode: PDIST +/* 4113 */ MCD_OPC_FilterValue, 63, 8, 0, // Skip to: 4125 +/* 4117 */ MCD_OPC_CheckPredicate, 1, 155, 6, // Skip to: 5812 +/* 4121 */ MCD_OPC_Decode, 234, 2, 26, // Opcode: PDISTN +/* 4125 */ MCD_OPC_FilterValue, 64, 8, 0, // Skip to: 4137 +/* 4129 */ MCD_OPC_CheckPredicate, 1, 143, 6, // Skip to: 5812 +/* 4133 */ MCD_OPC_Decode, 181, 1, 26, // Opcode: FMEAN16 +/* 4137 */ MCD_OPC_FilterValue, 66, 8, 0, // Skip to: 4149 +/* 4141 */ MCD_OPC_CheckPredicate, 1, 131, 6, // Skip to: 5812 +/* 4145 */ MCD_OPC_Decode, 255, 1, 26, // Opcode: FPADD64 +/* 4149 */ MCD_OPC_FilterValue, 68, 8, 0, // Skip to: 4161 +/* 4153 */ MCD_OPC_CheckPredicate, 1, 119, 6, // Skip to: 5812 +/* 4157 */ MCD_OPC_Decode, 150, 1, 26, // Opcode: FCHKSM16 +/* 4161 */ MCD_OPC_FilterValue, 72, 8, 0, // Skip to: 4173 +/* 4165 */ MCD_OPC_CheckPredicate, 2, 107, 6, // Skip to: 5812 +/* 4169 */ MCD_OPC_Decode, 141, 1, 26, // Opcode: FALIGNADATA +/* 4173 */ MCD_OPC_FilterValue, 75, 8, 0, // Skip to: 4185 +/* 4177 */ MCD_OPC_CheckPredicate, 2, 95, 6, // Skip to: 5812 +/* 4181 */ MCD_OPC_Decode, 128, 2, 26, // Opcode: FPMERGE +/* 4185 */ MCD_OPC_FilterValue, 77, 14, 0, // Skip to: 4203 +/* 4189 */ MCD_OPC_CheckPredicate, 2, 83, 6, // Skip to: 5812 +/* 4193 */ MCD_OPC_CheckField, 14, 5, 0, 77, 6, // Skip to: 5812 +/* 4199 */ MCD_OPC_Decode, 170, 1, 23, // Opcode: FEXPAND +/* 4203 */ MCD_OPC_FilterValue, 80, 8, 0, // Skip to: 4215 +/* 4207 */ MCD_OPC_CheckPredicate, 2, 65, 6, // Skip to: 5812 +/* 4211 */ MCD_OPC_Decode, 251, 1, 26, // Opcode: FPADD16 +/* 4215 */ MCD_OPC_FilterValue, 81, 8, 0, // Skip to: 4227 +/* 4219 */ MCD_OPC_CheckPredicate, 2, 53, 6, // Skip to: 5812 +/* 4223 */ MCD_OPC_Decode, 252, 1, 26, // Opcode: FPADD16S +/* 4227 */ MCD_OPC_FilterValue, 82, 8, 0, // Skip to: 4239 +/* 4231 */ MCD_OPC_CheckPredicate, 2, 41, 6, // Skip to: 5812 +/* 4235 */ MCD_OPC_Decode, 253, 1, 26, // Opcode: FPADD32 +/* 4239 */ MCD_OPC_FilterValue, 83, 8, 0, // Skip to: 4251 +/* 4243 */ MCD_OPC_CheckPredicate, 2, 29, 6, // Skip to: 5812 +/* 4247 */ MCD_OPC_Decode, 254, 1, 26, // Opcode: FPADD32S +/* 4251 */ MCD_OPC_FilterValue, 84, 8, 0, // Skip to: 4263 +/* 4255 */ MCD_OPC_CheckPredicate, 2, 17, 6, // Skip to: 5812 +/* 4259 */ MCD_OPC_Decode, 129, 2, 26, // Opcode: FPSUB16 +/* 4263 */ MCD_OPC_FilterValue, 85, 8, 0, // Skip to: 4275 +/* 4267 */ MCD_OPC_CheckPredicate, 2, 5, 6, // Skip to: 5812 +/* 4271 */ MCD_OPC_Decode, 130, 2, 26, // Opcode: FPSUB16S +/* 4275 */ MCD_OPC_FilterValue, 86, 8, 0, // Skip to: 4287 +/* 4279 */ MCD_OPC_CheckPredicate, 2, 249, 5, // Skip to: 5812 +/* 4283 */ MCD_OPC_Decode, 131, 2, 26, // Opcode: FPSUB32 +/* 4287 */ MCD_OPC_FilterValue, 87, 8, 0, // Skip to: 4299 +/* 4291 */ MCD_OPC_CheckPredicate, 2, 237, 5, // Skip to: 5812 +/* 4295 */ MCD_OPC_Decode, 132, 2, 26, // Opcode: FPSUB32S +/* 4299 */ MCD_OPC_FilterValue, 96, 20, 0, // Skip to: 4323 +/* 4303 */ MCD_OPC_CheckPredicate, 2, 225, 5, // Skip to: 5812 +/* 4307 */ MCD_OPC_CheckField, 14, 5, 0, 219, 5, // Skip to: 5812 +/* 4313 */ MCD_OPC_CheckField, 0, 5, 0, 213, 5, // Skip to: 5812 +/* 4319 */ MCD_OPC_Decode, 167, 2, 49, // Opcode: FZERO +/* 4323 */ MCD_OPC_FilterValue, 97, 20, 0, // Skip to: 4347 +/* 4327 */ MCD_OPC_CheckPredicate, 2, 201, 5, // Skip to: 5812 +/* 4331 */ MCD_OPC_CheckField, 14, 5, 0, 195, 5, // Skip to: 5812 +/* 4337 */ MCD_OPC_CheckField, 0, 5, 0, 189, 5, // Skip to: 5812 +/* 4343 */ MCD_OPC_Decode, 168, 2, 50, // Opcode: FZEROS +/* 4347 */ MCD_OPC_FilterValue, 98, 8, 0, // Skip to: 4359 +/* 4351 */ MCD_OPC_CheckPredicate, 2, 177, 5, // Skip to: 5812 +/* 4355 */ MCD_OPC_Decode, 233, 1, 26, // Opcode: FNOR +/* 4359 */ MCD_OPC_FilterValue, 99, 8, 0, // Skip to: 4371 +/* 4363 */ MCD_OPC_CheckPredicate, 2, 165, 5, // Skip to: 5812 +/* 4367 */ MCD_OPC_Decode, 234, 1, 25, // Opcode: FNORS +/* 4371 */ MCD_OPC_FilterValue, 100, 8, 0, // Skip to: 4383 +/* 4375 */ MCD_OPC_CheckPredicate, 2, 153, 5, // Skip to: 5812 +/* 4379 */ MCD_OPC_Decode, 145, 1, 26, // Opcode: FANDNOT2 +/* 4383 */ MCD_OPC_FilterValue, 101, 8, 0, // Skip to: 4395 +/* 4387 */ MCD_OPC_CheckPredicate, 2, 141, 5, // Skip to: 5812 +/* 4391 */ MCD_OPC_Decode, 146, 1, 25, // Opcode: FANDNOT2S +/* 4395 */ MCD_OPC_FilterValue, 102, 14, 0, // Skip to: 4413 +/* 4399 */ MCD_OPC_CheckPredicate, 2, 129, 5, // Skip to: 5812 +/* 4403 */ MCD_OPC_CheckField, 14, 5, 0, 123, 5, // Skip to: 5812 +/* 4409 */ MCD_OPC_Decode, 237, 1, 23, // Opcode: FNOT2 +/* 4413 */ MCD_OPC_FilterValue, 103, 14, 0, // Skip to: 4431 +/* 4417 */ MCD_OPC_CheckPredicate, 2, 111, 5, // Skip to: 5812 +/* 4421 */ MCD_OPC_CheckField, 14, 5, 0, 105, 5, // Skip to: 5812 +/* 4427 */ MCD_OPC_Decode, 238, 1, 22, // Opcode: FNOT2S +/* 4431 */ MCD_OPC_FilterValue, 104, 8, 0, // Skip to: 4443 +/* 4435 */ MCD_OPC_CheckPredicate, 2, 93, 5, // Skip to: 5812 +/* 4439 */ MCD_OPC_Decode, 143, 1, 26, // Opcode: FANDNOT1 +/* 4443 */ MCD_OPC_FilterValue, 105, 8, 0, // Skip to: 4455 +/* 4447 */ MCD_OPC_CheckPredicate, 2, 81, 5, // Skip to: 5812 +/* 4451 */ MCD_OPC_Decode, 144, 1, 25, // Opcode: FANDNOT1S +/* 4455 */ MCD_OPC_FilterValue, 106, 14, 0, // Skip to: 4473 +/* 4459 */ MCD_OPC_CheckPredicate, 2, 69, 5, // Skip to: 5812 +/* 4463 */ MCD_OPC_CheckField, 0, 5, 0, 63, 5, // Skip to: 5812 +/* 4469 */ MCD_OPC_Decode, 235, 1, 51, // Opcode: FNOT1 +/* 4473 */ MCD_OPC_FilterValue, 107, 14, 0, // Skip to: 4491 +/* 4477 */ MCD_OPC_CheckPredicate, 2, 51, 5, // Skip to: 5812 +/* 4481 */ MCD_OPC_CheckField, 0, 5, 0, 45, 5, // Skip to: 5812 +/* 4487 */ MCD_OPC_Decode, 236, 1, 52, // Opcode: FNOT1S +/* 4491 */ MCD_OPC_FilterValue, 108, 8, 0, // Skip to: 4503 +/* 4495 */ MCD_OPC_CheckPredicate, 2, 33, 5, // Skip to: 5812 +/* 4499 */ MCD_OPC_Decode, 162, 2, 26, // Opcode: FXOR +/* 4503 */ MCD_OPC_FilterValue, 109, 8, 0, // Skip to: 4515 +/* 4507 */ MCD_OPC_CheckPredicate, 2, 21, 5, // Skip to: 5812 +/* 4511 */ MCD_OPC_Decode, 163, 2, 25, // Opcode: FXORS +/* 4515 */ MCD_OPC_FilterValue, 110, 8, 0, // Skip to: 4527 +/* 4519 */ MCD_OPC_CheckPredicate, 2, 9, 5, // Skip to: 5812 +/* 4523 */ MCD_OPC_Decode, 224, 1, 26, // Opcode: FNAND +/* 4527 */ MCD_OPC_FilterValue, 111, 8, 0, // Skip to: 4539 +/* 4531 */ MCD_OPC_CheckPredicate, 2, 253, 4, // Skip to: 5812 +/* 4535 */ MCD_OPC_Decode, 225, 1, 25, // Opcode: FNANDS +/* 4539 */ MCD_OPC_FilterValue, 112, 8, 0, // Skip to: 4551 +/* 4543 */ MCD_OPC_CheckPredicate, 2, 241, 4, // Skip to: 5812 +/* 4547 */ MCD_OPC_Decode, 142, 1, 26, // Opcode: FAND +/* 4551 */ MCD_OPC_FilterValue, 113, 8, 0, // Skip to: 4563 +/* 4555 */ MCD_OPC_CheckPredicate, 2, 229, 4, // Skip to: 5812 +/* 4559 */ MCD_OPC_Decode, 147, 1, 25, // Opcode: FANDS +/* 4563 */ MCD_OPC_FilterValue, 114, 8, 0, // Skip to: 4575 +/* 4567 */ MCD_OPC_CheckPredicate, 2, 217, 4, // Skip to: 5812 +/* 4571 */ MCD_OPC_Decode, 160, 2, 26, // Opcode: FXNOR +/* 4575 */ MCD_OPC_FilterValue, 115, 8, 0, // Skip to: 4587 +/* 4579 */ MCD_OPC_CheckPredicate, 2, 205, 4, // Skip to: 5812 +/* 4583 */ MCD_OPC_Decode, 161, 2, 25, // Opcode: FXNORS +/* 4587 */ MCD_OPC_FilterValue, 116, 14, 0, // Skip to: 4605 +/* 4591 */ MCD_OPC_CheckPredicate, 2, 193, 4, // Skip to: 5812 +/* 4595 */ MCD_OPC_CheckField, 0, 5, 0, 187, 4, // Skip to: 5812 +/* 4601 */ MCD_OPC_Decode, 147, 2, 51, // Opcode: FSRC1 +/* 4605 */ MCD_OPC_FilterValue, 117, 14, 0, // Skip to: 4623 +/* 4609 */ MCD_OPC_CheckPredicate, 2, 175, 4, // Skip to: 5812 +/* 4613 */ MCD_OPC_CheckField, 0, 5, 0, 169, 4, // Skip to: 5812 +/* 4619 */ MCD_OPC_Decode, 148, 2, 52, // Opcode: FSRC1S +/* 4623 */ MCD_OPC_FilterValue, 118, 8, 0, // Skip to: 4635 +/* 4627 */ MCD_OPC_CheckPredicate, 2, 157, 4, // Skip to: 5812 +/* 4631 */ MCD_OPC_Decode, 245, 1, 26, // Opcode: FORNOT2 +/* 4635 */ MCD_OPC_FilterValue, 119, 8, 0, // Skip to: 4647 +/* 4639 */ MCD_OPC_CheckPredicate, 2, 145, 4, // Skip to: 5812 +/* 4643 */ MCD_OPC_Decode, 246, 1, 25, // Opcode: FORNOT2S +/* 4647 */ MCD_OPC_FilterValue, 120, 14, 0, // Skip to: 4665 +/* 4651 */ MCD_OPC_CheckPredicate, 2, 133, 4, // Skip to: 5812 +/* 4655 */ MCD_OPC_CheckField, 14, 5, 0, 127, 4, // Skip to: 5812 +/* 4661 */ MCD_OPC_Decode, 149, 2, 23, // Opcode: FSRC2 +/* 4665 */ MCD_OPC_FilterValue, 121, 14, 0, // Skip to: 4683 +/* 4669 */ MCD_OPC_CheckPredicate, 2, 115, 4, // Skip to: 5812 +/* 4673 */ MCD_OPC_CheckField, 14, 5, 0, 109, 4, // Skip to: 5812 +/* 4679 */ MCD_OPC_Decode, 150, 2, 22, // Opcode: FSRC2S +/* 4683 */ MCD_OPC_FilterValue, 122, 8, 0, // Skip to: 4695 +/* 4687 */ MCD_OPC_CheckPredicate, 2, 97, 4, // Skip to: 5812 +/* 4691 */ MCD_OPC_Decode, 243, 1, 26, // Opcode: FORNOT1 +/* 4695 */ MCD_OPC_FilterValue, 123, 8, 0, // Skip to: 4707 +/* 4699 */ MCD_OPC_CheckPredicate, 2, 85, 4, // Skip to: 5812 +/* 4703 */ MCD_OPC_Decode, 244, 1, 25, // Opcode: FORNOT1S +/* 4707 */ MCD_OPC_FilterValue, 124, 8, 0, // Skip to: 4719 +/* 4711 */ MCD_OPC_CheckPredicate, 2, 73, 4, // Skip to: 5812 +/* 4715 */ MCD_OPC_Decode, 242, 1, 26, // Opcode: FOR +/* 4719 */ MCD_OPC_FilterValue, 125, 8, 0, // Skip to: 4731 +/* 4723 */ MCD_OPC_CheckPredicate, 2, 61, 4, // Skip to: 5812 +/* 4727 */ MCD_OPC_Decode, 247, 1, 25, // Opcode: FORS +/* 4731 */ MCD_OPC_FilterValue, 126, 20, 0, // Skip to: 4755 +/* 4735 */ MCD_OPC_CheckPredicate, 2, 49, 4, // Skip to: 5812 +/* 4739 */ MCD_OPC_CheckField, 14, 5, 0, 43, 4, // Skip to: 5812 +/* 4745 */ MCD_OPC_CheckField, 0, 5, 0, 37, 4, // Skip to: 5812 +/* 4751 */ MCD_OPC_Decode, 240, 1, 49, // Opcode: FONE +/* 4755 */ MCD_OPC_FilterValue, 127, 20, 0, // Skip to: 4779 +/* 4759 */ MCD_OPC_CheckPredicate, 2, 25, 4, // Skip to: 5812 +/* 4763 */ MCD_OPC_CheckField, 14, 5, 0, 19, 4, // Skip to: 5812 +/* 4769 */ MCD_OPC_CheckField, 0, 5, 0, 13, 4, // Skip to: 5812 +/* 4775 */ MCD_OPC_Decode, 241, 1, 50, // Opcode: FONES +/* 4779 */ MCD_OPC_FilterValue, 128, 1, 26, 0, // Skip to: 4810 +/* 4784 */ MCD_OPC_CheckPredicate, 2, 0, 4, // Skip to: 5812 +/* 4788 */ MCD_OPC_CheckField, 25, 5, 0, 250, 3, // Skip to: 5812 +/* 4794 */ MCD_OPC_CheckField, 14, 5, 0, 244, 3, // Skip to: 5812 +/* 4800 */ MCD_OPC_CheckField, 0, 5, 0, 238, 3, // Skip to: 5812 +/* 4806 */ MCD_OPC_Decode, 133, 3, 4, // Opcode: SHUTDOWN +/* 4810 */ MCD_OPC_FilterValue, 129, 1, 26, 0, // Skip to: 4841 +/* 4815 */ MCD_OPC_CheckPredicate, 3, 225, 3, // Skip to: 5812 +/* 4819 */ MCD_OPC_CheckField, 25, 5, 0, 219, 3, // Skip to: 5812 +/* 4825 */ MCD_OPC_CheckField, 14, 5, 0, 213, 3, // Skip to: 5812 +/* 4831 */ MCD_OPC_CheckField, 0, 5, 0, 207, 3, // Skip to: 5812 +/* 4837 */ MCD_OPC_Decode, 134, 3, 4, // Opcode: SIAM +/* 4841 */ MCD_OPC_FilterValue, 144, 2, 14, 0, // Skip to: 4860 +/* 4846 */ MCD_OPC_CheckPredicate, 1, 194, 3, // Skip to: 5812 +/* 4850 */ MCD_OPC_CheckField, 14, 5, 0, 188, 3, // Skip to: 5812 +/* 4856 */ MCD_OPC_Decode, 196, 2, 53, // Opcode: MOVDTOX +/* 4860 */ MCD_OPC_FilterValue, 145, 2, 14, 0, // Skip to: 4879 +/* 4865 */ MCD_OPC_CheckPredicate, 1, 175, 3, // Skip to: 5812 +/* 4869 */ MCD_OPC_CheckField, 14, 5, 0, 169, 3, // Skip to: 5812 +/* 4875 */ MCD_OPC_Decode, 214, 2, 53, // Opcode: MOVSTOUW +/* 4879 */ MCD_OPC_FilterValue, 147, 2, 14, 0, // Skip to: 4898 +/* 4884 */ MCD_OPC_CheckPredicate, 1, 156, 3, // Skip to: 5812 +/* 4888 */ MCD_OPC_CheckField, 14, 5, 0, 150, 3, // Skip to: 5812 +/* 4894 */ MCD_OPC_Decode, 213, 2, 53, // Opcode: MOVSTOSW +/* 4898 */ MCD_OPC_FilterValue, 149, 2, 8, 0, // Skip to: 4911 +/* 4903 */ MCD_OPC_CheckPredicate, 1, 137, 3, // Skip to: 5812 +/* 4907 */ MCD_OPC_Decode, 222, 3, 10, // Opcode: XMULX +/* 4911 */ MCD_OPC_FilterValue, 151, 2, 8, 0, // Skip to: 4924 +/* 4916 */ MCD_OPC_CheckPredicate, 1, 124, 3, // Skip to: 5812 +/* 4920 */ MCD_OPC_Decode, 223, 3, 10, // Opcode: XMULXHI +/* 4924 */ MCD_OPC_FilterValue, 152, 2, 14, 0, // Skip to: 4943 +/* 4929 */ MCD_OPC_CheckPredicate, 1, 111, 3, // Skip to: 5812 +/* 4933 */ MCD_OPC_CheckField, 14, 5, 0, 105, 3, // Skip to: 5812 +/* 4939 */ MCD_OPC_Decode, 218, 2, 54, // Opcode: MOVXTOD +/* 4943 */ MCD_OPC_FilterValue, 153, 2, 14, 0, // Skip to: 4962 +/* 4948 */ MCD_OPC_CheckPredicate, 1, 92, 3, // Skip to: 5812 +/* 4952 */ MCD_OPC_CheckField, 14, 5, 0, 86, 3, // Skip to: 5812 +/* 4958 */ MCD_OPC_Decode, 215, 2, 54, // Opcode: MOVWTOS +/* 4962 */ MCD_OPC_FilterValue, 209, 2, 8, 0, // Skip to: 4975 +/* 4967 */ MCD_OPC_CheckPredicate, 1, 73, 3, // Skip to: 5812 +/* 4971 */ MCD_OPC_Decode, 179, 1, 44, // Opcode: FLCMPS +/* 4975 */ MCD_OPC_FilterValue, 210, 2, 64, 3, // Skip to: 5812 +/* 4980 */ MCD_OPC_CheckPredicate, 1, 60, 3, // Skip to: 5812 +/* 4984 */ MCD_OPC_Decode, 178, 1, 44, // Opcode: FLCMPD +/* 4988 */ MCD_OPC_FilterValue, 56, 25, 0, // Skip to: 5017 +/* 4992 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 4995 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5009 +/* 4999 */ MCD_OPC_CheckField, 5, 8, 0, 39, 3, // Skip to: 5812 +/* 5005 */ MCD_OPC_Decode, 171, 2, 55, // Opcode: JMPLrr +/* 5009 */ MCD_OPC_FilterValue, 1, 31, 3, // Skip to: 5812 +/* 5013 */ MCD_OPC_Decode, 170, 2, 55, // Opcode: JMPLri +/* 5017 */ MCD_OPC_FilterValue, 57, 37, 0, // Skip to: 5058 +/* 5021 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5024 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 5044 +/* 5028 */ MCD_OPC_CheckField, 25, 5, 0, 10, 3, // Skip to: 5812 +/* 5034 */ MCD_OPC_CheckField, 5, 8, 0, 4, 3, // Skip to: 5812 +/* 5040 */ MCD_OPC_Decode, 242, 2, 56, // Opcode: RETTrr +/* 5044 */ MCD_OPC_FilterValue, 1, 252, 2, // Skip to: 5812 +/* 5048 */ MCD_OPC_CheckField, 25, 5, 0, 246, 2, // Skip to: 5812 +/* 5054 */ MCD_OPC_Decode, 241, 2, 56, // Opcode: RETTri +/* 5058 */ MCD_OPC_FilterValue, 58, 115, 0, // Skip to: 5177 +/* 5062 */ MCD_OPC_ExtractField, 8, 6, // Inst{13-8} ... +/* 5065 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 5085 +/* 5069 */ MCD_OPC_CheckField, 29, 1, 0, 225, 2, // Skip to: 5812 +/* 5075 */ MCD_OPC_CheckField, 5, 3, 0, 219, 2, // Skip to: 5812 +/* 5081 */ MCD_OPC_Decode, 185, 3, 57, // Opcode: TICCrr +/* 5085 */ MCD_OPC_FilterValue, 16, 16, 0, // Skip to: 5105 +/* 5089 */ MCD_OPC_CheckField, 29, 1, 0, 205, 2, // Skip to: 5812 +/* 5095 */ MCD_OPC_CheckField, 5, 3, 0, 199, 2, // Skip to: 5812 +/* 5101 */ MCD_OPC_Decode, 196, 3, 57, // Opcode: TXCCrr +/* 5105 */ MCD_OPC_FilterValue, 32, 54, 0, // Skip to: 5163 +/* 5109 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... +/* 5112 */ MCD_OPC_FilterValue, 0, 184, 2, // Skip to: 5812 +/* 5116 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... +/* 5119 */ MCD_OPC_FilterValue, 3, 16, 0, // Skip to: 5139 +/* 5123 */ MCD_OPC_CheckField, 25, 4, 0, 30, 0, // Skip to: 5159 +/* 5129 */ MCD_OPC_CheckField, 14, 5, 1, 24, 0, // Skip to: 5159 +/* 5135 */ MCD_OPC_Decode, 178, 3, 4, // Opcode: TA3 +/* 5139 */ MCD_OPC_FilterValue, 5, 16, 0, // Skip to: 5159 +/* 5143 */ MCD_OPC_CheckField, 25, 4, 8, 10, 0, // Skip to: 5159 +/* 5149 */ MCD_OPC_CheckField, 14, 5, 0, 4, 0, // Skip to: 5159 +/* 5155 */ MCD_OPC_Decode, 179, 3, 4, // Opcode: TA5 +/* 5159 */ MCD_OPC_Decode, 184, 3, 58, // Opcode: TICCri +/* 5163 */ MCD_OPC_FilterValue, 48, 133, 2, // Skip to: 5812 +/* 5167 */ MCD_OPC_CheckField, 29, 1, 0, 127, 2, // Skip to: 5812 +/* 5173 */ MCD_OPC_Decode, 195, 3, 58, // Opcode: TXCCri +/* 5177 */ MCD_OPC_FilterValue, 60, 25, 0, // Skip to: 5206 +/* 5181 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5184 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5198 +/* 5188 */ MCD_OPC_CheckField, 5, 8, 0, 106, 2, // Skip to: 5812 +/* 5194 */ MCD_OPC_Decode, 244, 2, 8, // Opcode: SAVErr +/* 5198 */ MCD_OPC_FilterValue, 1, 98, 2, // Skip to: 5812 +/* 5202 */ MCD_OPC_Decode, 243, 2, 9, // Opcode: SAVEri +/* 5206 */ MCD_OPC_FilterValue, 61, 90, 2, // Skip to: 5812 +/* 5210 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5213 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5227 +/* 5217 */ MCD_OPC_CheckField, 5, 8, 0, 77, 2, // Skip to: 5812 +/* 5223 */ MCD_OPC_Decode, 238, 2, 8, // Opcode: RESTORErr +/* 5227 */ MCD_OPC_FilterValue, 1, 69, 2, // Skip to: 5812 +/* 5231 */ MCD_OPC_Decode, 237, 2, 9, // Opcode: RESTOREri +/* 5235 */ MCD_OPC_FilterValue, 3, 61, 2, // Skip to: 5812 +/* 5239 */ MCD_OPC_ExtractField, 19, 6, // Inst{24-19} ... +/* 5242 */ MCD_OPC_FilterValue, 0, 25, 0, // Skip to: 5271 +/* 5246 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5249 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5263 +/* 5253 */ MCD_OPC_CheckField, 5, 8, 0, 41, 2, // Skip to: 5812 +/* 5259 */ MCD_OPC_Decode, 191, 2, 59, // Opcode: LDrr +/* 5263 */ MCD_OPC_FilterValue, 1, 33, 2, // Skip to: 5812 +/* 5267 */ MCD_OPC_Decode, 190, 2, 59, // Opcode: LDri +/* 5271 */ MCD_OPC_FilterValue, 1, 25, 0, // Skip to: 5300 +/* 5275 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5278 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5292 +/* 5282 */ MCD_OPC_CheckField, 5, 8, 0, 12, 2, // Skip to: 5812 +/* 5288 */ MCD_OPC_Decode, 185, 2, 59, // Opcode: LDUBrr +/* 5292 */ MCD_OPC_FilterValue, 1, 4, 2, // Skip to: 5812 +/* 5296 */ MCD_OPC_Decode, 184, 2, 59, // Opcode: LDUBri +/* 5300 */ MCD_OPC_FilterValue, 2, 25, 0, // Skip to: 5329 +/* 5304 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5307 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5321 +/* 5311 */ MCD_OPC_CheckField, 5, 8, 0, 239, 1, // Skip to: 5812 +/* 5317 */ MCD_OPC_Decode, 187, 2, 59, // Opcode: LDUHrr +/* 5321 */ MCD_OPC_FilterValue, 1, 231, 1, // Skip to: 5812 +/* 5325 */ MCD_OPC_Decode, 186, 2, 59, // Opcode: LDUHri +/* 5329 */ MCD_OPC_FilterValue, 4, 25, 0, // Skip to: 5358 +/* 5333 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5336 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5350 +/* 5340 */ MCD_OPC_CheckField, 5, 8, 0, 210, 1, // Skip to: 5812 +/* 5346 */ MCD_OPC_Decode, 165, 3, 60, // Opcode: STrr +/* 5350 */ MCD_OPC_FilterValue, 1, 202, 1, // Skip to: 5812 +/* 5354 */ MCD_OPC_Decode, 164, 3, 60, // Opcode: STri +/* 5358 */ MCD_OPC_FilterValue, 5, 25, 0, // Skip to: 5387 +/* 5362 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5365 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5379 +/* 5369 */ MCD_OPC_CheckField, 5, 8, 0, 181, 1, // Skip to: 5812 +/* 5375 */ MCD_OPC_Decode, 153, 3, 60, // Opcode: STBrr +/* 5379 */ MCD_OPC_FilterValue, 1, 173, 1, // Skip to: 5812 +/* 5383 */ MCD_OPC_Decode, 152, 3, 60, // Opcode: STBri +/* 5387 */ MCD_OPC_FilterValue, 6, 25, 0, // Skip to: 5416 +/* 5391 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5394 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5408 +/* 5398 */ MCD_OPC_CheckField, 5, 8, 0, 152, 1, // Skip to: 5812 +/* 5404 */ MCD_OPC_Decode, 159, 3, 60, // Opcode: STHrr +/* 5408 */ MCD_OPC_FilterValue, 1, 144, 1, // Skip to: 5812 +/* 5412 */ MCD_OPC_Decode, 158, 3, 60, // Opcode: STHri +/* 5416 */ MCD_OPC_FilterValue, 8, 25, 0, // Skip to: 5445 +/* 5420 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5423 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5437 +/* 5427 */ MCD_OPC_CheckField, 5, 8, 0, 123, 1, // Skip to: 5812 +/* 5433 */ MCD_OPC_Decode, 183, 2, 59, // Opcode: LDSWrr +/* 5437 */ MCD_OPC_FilterValue, 1, 115, 1, // Skip to: 5812 +/* 5441 */ MCD_OPC_Decode, 182, 2, 59, // Opcode: LDSWri +/* 5445 */ MCD_OPC_FilterValue, 9, 25, 0, // Skip to: 5474 +/* 5449 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5452 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5466 +/* 5456 */ MCD_OPC_CheckField, 5, 8, 0, 94, 1, // Skip to: 5812 +/* 5462 */ MCD_OPC_Decode, 179, 2, 59, // Opcode: LDSBrr +/* 5466 */ MCD_OPC_FilterValue, 1, 86, 1, // Skip to: 5812 +/* 5470 */ MCD_OPC_Decode, 178, 2, 59, // Opcode: LDSBri +/* 5474 */ MCD_OPC_FilterValue, 10, 25, 0, // Skip to: 5503 +/* 5478 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5481 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5495 +/* 5485 */ MCD_OPC_CheckField, 5, 8, 0, 65, 1, // Skip to: 5812 +/* 5491 */ MCD_OPC_Decode, 181, 2, 59, // Opcode: LDSHrr +/* 5495 */ MCD_OPC_FilterValue, 1, 57, 1, // Skip to: 5812 +/* 5499 */ MCD_OPC_Decode, 180, 2, 59, // Opcode: LDSHri +/* 5503 */ MCD_OPC_FilterValue, 11, 25, 0, // Skip to: 5532 +/* 5507 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5510 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5524 +/* 5514 */ MCD_OPC_CheckField, 5, 8, 0, 36, 1, // Skip to: 5812 +/* 5520 */ MCD_OPC_Decode, 189, 2, 59, // Opcode: LDXrr +/* 5524 */ MCD_OPC_FilterValue, 1, 28, 1, // Skip to: 5812 +/* 5528 */ MCD_OPC_Decode, 188, 2, 59, // Opcode: LDXri +/* 5532 */ MCD_OPC_FilterValue, 14, 25, 0, // Skip to: 5561 +/* 5536 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5539 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5553 +/* 5543 */ MCD_OPC_CheckField, 5, 8, 0, 7, 1, // Skip to: 5812 +/* 5549 */ MCD_OPC_Decode, 163, 3, 60, // Opcode: STXrr +/* 5553 */ MCD_OPC_FilterValue, 1, 255, 0, // Skip to: 5812 +/* 5557 */ MCD_OPC_Decode, 162, 3, 60, // Opcode: STXri +/* 5561 */ MCD_OPC_FilterValue, 15, 25, 0, // Skip to: 5590 +/* 5565 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5568 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5582 +/* 5572 */ MCD_OPC_CheckField, 5, 8, 0, 234, 0, // Skip to: 5812 +/* 5578 */ MCD_OPC_Decode, 177, 3, 4, // Opcode: SWAPrr +/* 5582 */ MCD_OPC_FilterValue, 1, 226, 0, // Skip to: 5812 +/* 5586 */ MCD_OPC_Decode, 176, 3, 4, // Opcode: SWAPri +/* 5590 */ MCD_OPC_FilterValue, 32, 25, 0, // Skip to: 5619 +/* 5594 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5597 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5611 +/* 5601 */ MCD_OPC_CheckField, 5, 8, 0, 205, 0, // Skip to: 5812 +/* 5607 */ MCD_OPC_Decode, 175, 2, 61, // Opcode: LDFrr +/* 5611 */ MCD_OPC_FilterValue, 1, 197, 0, // Skip to: 5812 +/* 5615 */ MCD_OPC_Decode, 174, 2, 61, // Opcode: LDFri +/* 5619 */ MCD_OPC_FilterValue, 34, 33, 0, // Skip to: 5656 +/* 5623 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5626 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5644 +/* 5630 */ MCD_OPC_CheckPredicate, 0, 178, 0, // Skip to: 5812 +/* 5634 */ MCD_OPC_CheckField, 5, 8, 0, 172, 0, // Skip to: 5812 +/* 5640 */ MCD_OPC_Decode, 177, 2, 62, // Opcode: LDQFrr +/* 5644 */ MCD_OPC_FilterValue, 1, 164, 0, // Skip to: 5812 +/* 5648 */ MCD_OPC_CheckPredicate, 0, 160, 0, // Skip to: 5812 +/* 5652 */ MCD_OPC_Decode, 176, 2, 62, // Opcode: LDQFri +/* 5656 */ MCD_OPC_FilterValue, 35, 25, 0, // Skip to: 5685 +/* 5660 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5663 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5677 +/* 5667 */ MCD_OPC_CheckField, 5, 8, 0, 139, 0, // Skip to: 5812 +/* 5673 */ MCD_OPC_Decode, 173, 2, 63, // Opcode: LDDFrr +/* 5677 */ MCD_OPC_FilterValue, 1, 131, 0, // Skip to: 5812 +/* 5681 */ MCD_OPC_Decode, 172, 2, 63, // Opcode: LDDFri +/* 5685 */ MCD_OPC_FilterValue, 36, 25, 0, // Skip to: 5714 +/* 5689 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5692 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5706 +/* 5696 */ MCD_OPC_CheckField, 5, 8, 0, 110, 0, // Skip to: 5812 +/* 5702 */ MCD_OPC_Decode, 157, 3, 64, // Opcode: STFrr +/* 5706 */ MCD_OPC_FilterValue, 1, 102, 0, // Skip to: 5812 +/* 5710 */ MCD_OPC_Decode, 156, 3, 64, // Opcode: STFri +/* 5714 */ MCD_OPC_FilterValue, 38, 33, 0, // Skip to: 5751 +/* 5718 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5721 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5739 +/* 5725 */ MCD_OPC_CheckPredicate, 0, 83, 0, // Skip to: 5812 +/* 5729 */ MCD_OPC_CheckField, 5, 8, 0, 77, 0, // Skip to: 5812 +/* 5735 */ MCD_OPC_Decode, 161, 3, 65, // Opcode: STQFrr +/* 5739 */ MCD_OPC_FilterValue, 1, 69, 0, // Skip to: 5812 +/* 5743 */ MCD_OPC_CheckPredicate, 0, 65, 0, // Skip to: 5812 +/* 5747 */ MCD_OPC_Decode, 160, 3, 65, // Opcode: STQFri +/* 5751 */ MCD_OPC_FilterValue, 39, 25, 0, // Skip to: 5780 +/* 5755 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5758 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5772 +/* 5762 */ MCD_OPC_CheckField, 5, 8, 0, 44, 0, // Skip to: 5812 +/* 5768 */ MCD_OPC_Decode, 155, 3, 66, // Opcode: STDFrr +/* 5772 */ MCD_OPC_FilterValue, 1, 36, 0, // Skip to: 5812 +/* 5776 */ MCD_OPC_Decode, 154, 3, 66, // Opcode: STDFri +/* 5780 */ MCD_OPC_FilterValue, 60, 14, 0, // Skip to: 5798 +/* 5784 */ MCD_OPC_CheckPredicate, 0, 24, 0, // Skip to: 5812 +/* 5788 */ MCD_OPC_CheckField, 5, 9, 128, 1, 17, 0, // Skip to: 5812 +/* 5795 */ MCD_OPC_Decode, 117, 67, // Opcode: CASrr +/* 5798 */ MCD_OPC_FilterValue, 62, 10, 0, // Skip to: 5812 +/* 5802 */ MCD_OPC_CheckField, 5, 9, 128, 1, 3, 0, // Skip to: 5812 +/* 5809 */ MCD_OPC_Decode, 116, 68, // Opcode: CASXrr +/* 5812 */ MCD_OPC_Fail, + 0 +}; + +static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) +{ + switch (Idx) { + default: // llvm_unreachable("Invalid index!"); + case 0: + return (bool)((Bits & Sparc_FeatureV9)); + case 1: + return (bool)((Bits & Sparc_FeatureVIS3)); + case 2: + return (bool)((Bits & Sparc_FeatureVIS)); + case 3: + return (bool)((Bits & Sparc_FeatureVIS2)); + } +} + +#define DecodeToMCInst(fname,fieldname, InsnType) \ +static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ + uint64_t Address, void *Decoder) \ +{ \ + InsnType tmp; \ + switch (Idx) { \ + default: \ + case 0: \ + tmp = fieldname(insn, 0, 22); \ + MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \ + return S; \ + case 1: \ + tmp = fieldname(insn, 0, 19); \ + MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \ + tmp = fieldname(insn, 25, 4); \ + MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \ + return S; \ + case 2: \ + tmp = fieldname(insn, 0, 22); \ + MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \ + tmp = fieldname(insn, 25, 4); \ + MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \ + return S; \ + case 3: \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= (fieldname(insn, 0, 14) << 0); \ + tmp |= (fieldname(insn, 20, 2) << 14); \ + MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \ + return S; \ + case 4: \ + return S; \ + case 5: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 22); \ + MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \ + return S; \ + case 6: \ + tmp = fieldname(insn, 0, 19); \ + MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \ + tmp = fieldname(insn, 25, 4); \ + MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \ + tmp = fieldname(insn, 20, 2); \ + if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 7: \ + tmp = fieldname(insn, 0, 30); \ + if (DecodeCall(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 8: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 9: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 13); \ + if (DecodeSIMM13(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 10: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 11: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 13); \ + MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \ + return S; \ + case 12: \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 13: \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 13); \ + if (DecodeSIMM13(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 14: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 15: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 6); \ + MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \ + return S; \ + case 16: \ + tmp = fieldname(insn, 0, 13); \ + if (DecodeSIMM13(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 17: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 4); \ + MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \ + return S; \ + case 18: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 4); \ + MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \ + return S; \ + case 19: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 11); \ + MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 4); \ + MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \ + return S; \ + case 20: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 11); \ + MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 4); \ + MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \ + return S; \ + case 21: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 10); \ + MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \ + return S; \ + case 22: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 23: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 24: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 25: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 26: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 27: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 28: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 29: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 30: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 31: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 32: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 33: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 34: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 35: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 36: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 4); \ + MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \ + return S; \ + case 37: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 4); \ + MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \ + return S; \ + case 38: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 4); \ + MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \ + return S; \ + case 39: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 4); \ + MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \ + return S; \ + case 40: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 4); \ + MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \ + return S; \ + case 41: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 4); \ + MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \ + return S; \ + case 42: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 43: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 44: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 45: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 46: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 47: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 48: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 49: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 50: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 51: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 52: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 53: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 54: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 55: \ + if (DecodeJMPL(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 56: \ + if (DecodeReturn(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 57: \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 25, 4); \ + MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \ + return S; \ + case 58: \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 8); \ + MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \ + tmp = fieldname(insn, 25, 4); \ + MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \ + return S; \ + case 59: \ + if (DecodeLoadInt(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 60: \ + if (DecodeStoreInt(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 61: \ + if (DecodeLoadFP(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 62: \ + if (DecodeLoadQFP(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 63: \ + if (DecodeLoadDFP(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 64: \ + if (DecodeStoreFP(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 65: \ + if (DecodeStoreQFP(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 66: \ + if (DecodeStoreDFP(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 67: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 68: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + } \ +} + +#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ +static DecodeStatus fname(uint8_t DecodeTable[], MCInst *MI, \ + InsnType insn, uint64_t Address, MCRegisterInfo *MRI, int feature) \ +{ \ + uint64_t Bits = getFeatureBits(feature); \ + uint8_t *Ptr = DecodeTable; \ + uint32_t CurFieldValue = 0; \ + DecodeStatus S = MCDisassembler_Success; \ + for (;;) { \ + switch (*Ptr) { \ + default: \ + return MCDisassembler_Fail; \ + case MCD_OPC_ExtractField: { \ + unsigned Start = *++Ptr; \ + unsigned Len = *++Ptr; \ + ++Ptr; \ + CurFieldValue = fieldname(insn, Start, Len); \ + break; \ + } \ + case MCD_OPC_FilterValue: { \ + unsigned Len; \ + InsnType Val = (InsnType)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + unsigned NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + if (Val != CurFieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckField: { \ + unsigned Start = *++Ptr; \ + unsigned Len = *++Ptr; \ + InsnType FieldValue = fieldname(insn, Start, Len); \ + uint32_t ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + unsigned NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + if (ExpectedValue != FieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckPredicate: { \ + unsigned Len; \ + unsigned PIdx = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + unsigned NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + bool Pred; \ + Pred = checkDecoderPredicate(PIdx, Bits); \ + if (!Pred) \ + Ptr += NumToSkip; \ + (void)Pred; \ + break; \ + } \ + case MCD_OPC_Decode: { \ + unsigned Len; \ + unsigned Opc = (unsigned)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + unsigned DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + MCInst_setOpcode(MI, Opc); \ + return decoder(S, DecodeIdx, insn, MI, Address, MRI); \ + } \ + case MCD_OPC_SoftFail: { \ + unsigned Len; \ + InsnType PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + InsnType NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + bool Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ + if (Fail) \ + S = MCDisassembler_SoftFail; \ + break; \ + } \ + case MCD_OPC_Fail: { \ + return MCDisassembler_Fail; \ + } \ + } \ + } \ +} + +FieldFromInstruction(fieldFromInstruction_4, uint32_t) +DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t) +DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t) diff --git a/arch/Sparc/SparcGenInstrInfo.inc b/arch/Sparc/SparcGenInstrInfo.inc new file mode 100644 index 0000000000..063208f481 --- /dev/null +++ b/arch/Sparc/SparcGenInstrInfo.inc @@ -0,0 +1,511 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*Target Instruction Enum Values *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2014 */ + + +#ifdef GET_INSTRINFO_ENUM +#undef GET_INSTRINFO_ENUM + +enum { + SP_PHI = 0, + SP_INLINEASM = 1, + SP_CFI_INSTRUCTION = 2, + SP_EH_LABEL = 3, + SP_GC_LABEL = 4, + SP_KILL = 5, + SP_EXTRACT_SUBREG = 6, + SP_INSERT_SUBREG = 7, + SP_IMPLICIT_DEF = 8, + SP_SUBREG_TO_REG = 9, + SP_COPY_TO_REGCLASS = 10, + SP_DBG_VALUE = 11, + SP_REG_SEQUENCE = 12, + SP_COPY = 13, + SP_BUNDLE = 14, + SP_LIFETIME_START = 15, + SP_LIFETIME_END = 16, + SP_STACKMAP = 17, + SP_PATCHPOINT = 18, + SP_ADDCCri = 19, + SP_ADDCCrr = 20, + SP_ADDCri = 21, + SP_ADDCrr = 22, + SP_ADDEri = 23, + SP_ADDErr = 24, + SP_ADDXC = 25, + SP_ADDXCCC = 26, + SP_ADDXri = 27, + SP_ADDXrr = 28, + SP_ADDri = 29, + SP_ADDrr = 30, + SP_ADJCALLSTACKDOWN = 31, + SP_ADJCALLSTACKUP = 32, + SP_ALIGNADDR = 33, + SP_ALIGNADDRL = 34, + SP_ANDCCri = 35, + SP_ANDCCrr = 36, + SP_ANDNCCri = 37, + SP_ANDNCCrr = 38, + SP_ANDNri = 39, + SP_ANDNrr = 40, + SP_ANDXNrr = 41, + SP_ANDXri = 42, + SP_ANDXrr = 43, + SP_ANDri = 44, + SP_ANDrr = 45, + SP_ARRAY16 = 46, + SP_ARRAY32 = 47, + SP_ARRAY8 = 48, + SP_ATOMIC_LOAD_ADD_32 = 49, + SP_ATOMIC_LOAD_ADD_64 = 50, + SP_ATOMIC_LOAD_AND_32 = 51, + SP_ATOMIC_LOAD_AND_64 = 52, + SP_ATOMIC_LOAD_MAX_32 = 53, + SP_ATOMIC_LOAD_MAX_64 = 54, + SP_ATOMIC_LOAD_MIN_32 = 55, + SP_ATOMIC_LOAD_MIN_64 = 56, + SP_ATOMIC_LOAD_NAND_32 = 57, + SP_ATOMIC_LOAD_NAND_64 = 58, + SP_ATOMIC_LOAD_OR_32 = 59, + SP_ATOMIC_LOAD_OR_64 = 60, + SP_ATOMIC_LOAD_SUB_32 = 61, + SP_ATOMIC_LOAD_SUB_64 = 62, + SP_ATOMIC_LOAD_UMAX_32 = 63, + SP_ATOMIC_LOAD_UMAX_64 = 64, + SP_ATOMIC_LOAD_UMIN_32 = 65, + SP_ATOMIC_LOAD_UMIN_64 = 66, + SP_ATOMIC_LOAD_XOR_32 = 67, + SP_ATOMIC_LOAD_XOR_64 = 68, + SP_ATOMIC_SWAP_64 = 69, + SP_BA = 70, + SP_BCOND = 71, + SP_BCONDA = 72, + SP_BINDri = 73, + SP_BINDrr = 74, + SP_BMASK = 75, + SP_BPFCC = 76, + SP_BPFCCA = 77, + SP_BPFCCANT = 78, + SP_BPFCCNT = 79, + SP_BPGEZapn = 80, + SP_BPGEZapt = 81, + SP_BPGEZnapn = 82, + SP_BPGEZnapt = 83, + SP_BPGZapn = 84, + SP_BPGZapt = 85, + SP_BPGZnapn = 86, + SP_BPGZnapt = 87, + SP_BPICC = 88, + SP_BPICCA = 89, + SP_BPICCANT = 90, + SP_BPICCNT = 91, + SP_BPLEZapn = 92, + SP_BPLEZapt = 93, + SP_BPLEZnapn = 94, + SP_BPLEZnapt = 95, + SP_BPLZapn = 96, + SP_BPLZapt = 97, + SP_BPLZnapn = 98, + SP_BPLZnapt = 99, + SP_BPNZapn = 100, + SP_BPNZapt = 101, + SP_BPNZnapn = 102, + SP_BPNZnapt = 103, + SP_BPXCC = 104, + SP_BPXCCA = 105, + SP_BPXCCANT = 106, + SP_BPXCCNT = 107, + SP_BPZapn = 108, + SP_BPZapt = 109, + SP_BPZnapn = 110, + SP_BPZnapt = 111, + SP_BSHUFFLE = 112, + SP_CALL = 113, + SP_CALLri = 114, + SP_CALLrr = 115, + SP_CASXrr = 116, + SP_CASrr = 117, + SP_CMASK16 = 118, + SP_CMASK32 = 119, + SP_CMASK8 = 120, + SP_CMPri = 121, + SP_CMPrr = 122, + SP_EDGE16 = 123, + SP_EDGE16L = 124, + SP_EDGE16LN = 125, + SP_EDGE16N = 126, + SP_EDGE32 = 127, + SP_EDGE32L = 128, + SP_EDGE32LN = 129, + SP_EDGE32N = 130, + SP_EDGE8 = 131, + SP_EDGE8L = 132, + SP_EDGE8LN = 133, + SP_EDGE8N = 134, + SP_FABSD = 135, + SP_FABSQ = 136, + SP_FABSS = 137, + SP_FADDD = 138, + SP_FADDQ = 139, + SP_FADDS = 140, + SP_FALIGNADATA = 141, + SP_FAND = 142, + SP_FANDNOT1 = 143, + SP_FANDNOT1S = 144, + SP_FANDNOT2 = 145, + SP_FANDNOT2S = 146, + SP_FANDS = 147, + SP_FBCOND = 148, + SP_FBCONDA = 149, + SP_FCHKSM16 = 150, + SP_FCMPD = 151, + SP_FCMPEQ16 = 152, + SP_FCMPEQ32 = 153, + SP_FCMPGT16 = 154, + SP_FCMPGT32 = 155, + SP_FCMPLE16 = 156, + SP_FCMPLE32 = 157, + SP_FCMPNE16 = 158, + SP_FCMPNE32 = 159, + SP_FCMPQ = 160, + SP_FCMPS = 161, + SP_FDIVD = 162, + SP_FDIVQ = 163, + SP_FDIVS = 164, + SP_FDMULQ = 165, + SP_FDTOI = 166, + SP_FDTOQ = 167, + SP_FDTOS = 168, + SP_FDTOX = 169, + SP_FEXPAND = 170, + SP_FHADDD = 171, + SP_FHADDS = 172, + SP_FHSUBD = 173, + SP_FHSUBS = 174, + SP_FITOD = 175, + SP_FITOQ = 176, + SP_FITOS = 177, + SP_FLCMPD = 178, + SP_FLCMPS = 179, + SP_FLUSHW = 180, + SP_FMEAN16 = 181, + SP_FMOVD = 182, + SP_FMOVD_FCC = 183, + SP_FMOVD_ICC = 184, + SP_FMOVD_XCC = 185, + SP_FMOVQ = 186, + SP_FMOVQ_FCC = 187, + SP_FMOVQ_ICC = 188, + SP_FMOVQ_XCC = 189, + SP_FMOVRGEZD = 190, + SP_FMOVRGEZQ = 191, + SP_FMOVRGEZS = 192, + SP_FMOVRGZD = 193, + SP_FMOVRGZQ = 194, + SP_FMOVRGZS = 195, + SP_FMOVRLEZD = 196, + SP_FMOVRLEZQ = 197, + SP_FMOVRLEZS = 198, + SP_FMOVRLZD = 199, + SP_FMOVRLZQ = 200, + SP_FMOVRLZS = 201, + SP_FMOVRNZD = 202, + SP_FMOVRNZQ = 203, + SP_FMOVRNZS = 204, + SP_FMOVRZD = 205, + SP_FMOVRZQ = 206, + SP_FMOVRZS = 207, + SP_FMOVS = 208, + SP_FMOVS_FCC = 209, + SP_FMOVS_ICC = 210, + SP_FMOVS_XCC = 211, + SP_FMUL8SUX16 = 212, + SP_FMUL8ULX16 = 213, + SP_FMUL8X16 = 214, + SP_FMUL8X16AL = 215, + SP_FMUL8X16AU = 216, + SP_FMULD = 217, + SP_FMULD8SUX16 = 218, + SP_FMULD8ULX16 = 219, + SP_FMULQ = 220, + SP_FMULS = 221, + SP_FNADDD = 222, + SP_FNADDS = 223, + SP_FNAND = 224, + SP_FNANDS = 225, + SP_FNEGD = 226, + SP_FNEGQ = 227, + SP_FNEGS = 228, + SP_FNHADDD = 229, + SP_FNHADDS = 230, + SP_FNMULD = 231, + SP_FNMULS = 232, + SP_FNOR = 233, + SP_FNORS = 234, + SP_FNOT1 = 235, + SP_FNOT1S = 236, + SP_FNOT2 = 237, + SP_FNOT2S = 238, + SP_FNSMULD = 239, + SP_FONE = 240, + SP_FONES = 241, + SP_FOR = 242, + SP_FORNOT1 = 243, + SP_FORNOT1S = 244, + SP_FORNOT2 = 245, + SP_FORNOT2S = 246, + SP_FORS = 247, + SP_FPACK16 = 248, + SP_FPACK32 = 249, + SP_FPACKFIX = 250, + SP_FPADD16 = 251, + SP_FPADD16S = 252, + SP_FPADD32 = 253, + SP_FPADD32S = 254, + SP_FPADD64 = 255, + SP_FPMERGE = 256, + SP_FPSUB16 = 257, + SP_FPSUB16S = 258, + SP_FPSUB32 = 259, + SP_FPSUB32S = 260, + SP_FQTOD = 261, + SP_FQTOI = 262, + SP_FQTOS = 263, + SP_FQTOX = 264, + SP_FSLAS16 = 265, + SP_FSLAS32 = 266, + SP_FSLL16 = 267, + SP_FSLL32 = 268, + SP_FSMULD = 269, + SP_FSQRTD = 270, + SP_FSQRTQ = 271, + SP_FSQRTS = 272, + SP_FSRA16 = 273, + SP_FSRA32 = 274, + SP_FSRC1 = 275, + SP_FSRC1S = 276, + SP_FSRC2 = 277, + SP_FSRC2S = 278, + SP_FSRL16 = 279, + SP_FSRL32 = 280, + SP_FSTOD = 281, + SP_FSTOI = 282, + SP_FSTOQ = 283, + SP_FSTOX = 284, + SP_FSUBD = 285, + SP_FSUBQ = 286, + SP_FSUBS = 287, + SP_FXNOR = 288, + SP_FXNORS = 289, + SP_FXOR = 290, + SP_FXORS = 291, + SP_FXTOD = 292, + SP_FXTOQ = 293, + SP_FXTOS = 294, + SP_FZERO = 295, + SP_FZEROS = 296, + SP_GETPCX = 297, + SP_JMPLri = 298, + SP_JMPLrr = 299, + SP_LDDFri = 300, + SP_LDDFrr = 301, + SP_LDFri = 302, + SP_LDFrr = 303, + SP_LDQFri = 304, + SP_LDQFrr = 305, + SP_LDSBri = 306, + SP_LDSBrr = 307, + SP_LDSHri = 308, + SP_LDSHrr = 309, + SP_LDSWri = 310, + SP_LDSWrr = 311, + SP_LDUBri = 312, + SP_LDUBrr = 313, + SP_LDUHri = 314, + SP_LDUHrr = 315, + SP_LDXri = 316, + SP_LDXrr = 317, + SP_LDri = 318, + SP_LDrr = 319, + SP_LEAX_ADDri = 320, + SP_LEA_ADDri = 321, + SP_LZCNT = 322, + SP_MEMBARi = 323, + SP_MOVDTOX = 324, + SP_MOVFCCri = 325, + SP_MOVFCCrr = 326, + SP_MOVICCri = 327, + SP_MOVICCrr = 328, + SP_MOVRGEZri = 329, + SP_MOVRGEZrr = 330, + SP_MOVRGZri = 331, + SP_MOVRGZrr = 332, + SP_MOVRLEZri = 333, + SP_MOVRLEZrr = 334, + SP_MOVRLZri = 335, + SP_MOVRLZrr = 336, + SP_MOVRNZri = 337, + SP_MOVRNZrr = 338, + SP_MOVRRZri = 339, + SP_MOVRRZrr = 340, + SP_MOVSTOSW = 341, + SP_MOVSTOUW = 342, + SP_MOVWTOS = 343, + SP_MOVXCCri = 344, + SP_MOVXCCrr = 345, + SP_MOVXTOD = 346, + SP_MULXri = 347, + SP_MULXrr = 348, + SP_NOP = 349, + SP_ORCCri = 350, + SP_ORCCrr = 351, + SP_ORNCCri = 352, + SP_ORNCCrr = 353, + SP_ORNri = 354, + SP_ORNrr = 355, + SP_ORXNrr = 356, + SP_ORXri = 357, + SP_ORXrr = 358, + SP_ORri = 359, + SP_ORrr = 360, + SP_PDIST = 361, + SP_PDISTN = 362, + SP_POPCrr = 363, + SP_RDY = 364, + SP_RESTOREri = 365, + SP_RESTORErr = 366, + SP_RET = 367, + SP_RETL = 368, + SP_RETTri = 369, + SP_RETTrr = 370, + SP_SAVEri = 371, + SP_SAVErr = 372, + SP_SDIVCCri = 373, + SP_SDIVCCrr = 374, + SP_SDIVXri = 375, + SP_SDIVXrr = 376, + SP_SDIVri = 377, + SP_SDIVrr = 378, + SP_SELECT_CC_DFP_FCC = 379, + SP_SELECT_CC_DFP_ICC = 380, + SP_SELECT_CC_FP_FCC = 381, + SP_SELECT_CC_FP_ICC = 382, + SP_SELECT_CC_Int_FCC = 383, + SP_SELECT_CC_Int_ICC = 384, + SP_SELECT_CC_QFP_FCC = 385, + SP_SELECT_CC_QFP_ICC = 386, + SP_SETHIXi = 387, + SP_SETHIi = 388, + SP_SHUTDOWN = 389, + SP_SIAM = 390, + SP_SLLXri = 391, + SP_SLLXrr = 392, + SP_SLLri = 393, + SP_SLLrr = 394, + SP_SMULCCri = 395, + SP_SMULCCrr = 396, + SP_SMULri = 397, + SP_SMULrr = 398, + SP_SRAXri = 399, + SP_SRAXrr = 400, + SP_SRAri = 401, + SP_SRArr = 402, + SP_SRLXri = 403, + SP_SRLXrr = 404, + SP_SRLri = 405, + SP_SRLrr = 406, + SP_STBAR = 407, + SP_STBri = 408, + SP_STBrr = 409, + SP_STDFri = 410, + SP_STDFrr = 411, + SP_STFri = 412, + SP_STFrr = 413, + SP_STHri = 414, + SP_STHrr = 415, + SP_STQFri = 416, + SP_STQFrr = 417, + SP_STXri = 418, + SP_STXrr = 419, + SP_STri = 420, + SP_STrr = 421, + SP_SUBCCri = 422, + SP_SUBCCrr = 423, + SP_SUBCri = 424, + SP_SUBCrr = 425, + SP_SUBEri = 426, + SP_SUBErr = 427, + SP_SUBXri = 428, + SP_SUBXrr = 429, + SP_SUBri = 430, + SP_SUBrr = 431, + SP_SWAPri = 432, + SP_SWAPrr = 433, + SP_TA3 = 434, + SP_TA5 = 435, + SP_TADDCCTVri = 436, + SP_TADDCCTVrr = 437, + SP_TADDCCri = 438, + SP_TADDCCrr = 439, + SP_TICCri = 440, + SP_TICCrr = 441, + SP_TLS_ADDXrr = 442, + SP_TLS_ADDrr = 443, + SP_TLS_CALL = 444, + SP_TLS_LDXrr = 445, + SP_TLS_LDrr = 446, + SP_TSUBCCTVri = 447, + SP_TSUBCCTVrr = 448, + SP_TSUBCCri = 449, + SP_TSUBCCrr = 450, + SP_TXCCri = 451, + SP_TXCCrr = 452, + SP_UDIVCCri = 453, + SP_UDIVCCrr = 454, + SP_UDIVXri = 455, + SP_UDIVXrr = 456, + SP_UDIVri = 457, + SP_UDIVrr = 458, + SP_UMULCCri = 459, + SP_UMULCCrr = 460, + SP_UMULXHI = 461, + SP_UMULri = 462, + SP_UMULrr = 463, + SP_UNIMP = 464, + SP_V9FCMPD = 465, + SP_V9FCMPED = 466, + SP_V9FCMPEQ = 467, + SP_V9FCMPES = 468, + SP_V9FCMPQ = 469, + SP_V9FCMPS = 470, + SP_V9FMOVD_FCC = 471, + SP_V9FMOVQ_FCC = 472, + SP_V9FMOVS_FCC = 473, + SP_V9MOVFCCri = 474, + SP_V9MOVFCCrr = 475, + SP_WRYri = 476, + SP_WRYrr = 477, + SP_XMULX = 478, + SP_XMULXHI = 479, + SP_XNORCCri = 480, + SP_XNORCCrr = 481, + SP_XNORXrr = 482, + SP_XNORri = 483, + SP_XNORrr = 484, + SP_XORCCri = 485, + SP_XORCCrr = 486, + SP_XORXri = 487, + SP_XORXrr = 488, + SP_XORri = 489, + SP_XORrr = 490, + SP_INSTRUCTION_LIST_END = 491 +}; + +#endif // GET_INSTRINFO_ENUM diff --git a/arch/Sparc/SparcGenRegisterInfo.inc b/arch/Sparc/SparcGenRegisterInfo.inc new file mode 100644 index 0000000000..30bf9e01b6 --- /dev/null +++ b/arch/Sparc/SparcGenRegisterInfo.inc @@ -0,0 +1,462 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*Target Register Enum Values *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2014 */ + + +#ifdef GET_REGINFO_ENUM +#undef GET_REGINFO_ENUM + +enum { + SP_NoRegister, + SP_ICC = 1, + SP_Y = 2, + SP_D0 = 3, + SP_D1 = 4, + SP_D2 = 5, + SP_D3 = 6, + SP_D4 = 7, + SP_D5 = 8, + SP_D6 = 9, + SP_D7 = 10, + SP_D8 = 11, + SP_D9 = 12, + SP_D10 = 13, + SP_D11 = 14, + SP_D12 = 15, + SP_D13 = 16, + SP_D14 = 17, + SP_D15 = 18, + SP_D16 = 19, + SP_D17 = 20, + SP_D18 = 21, + SP_D19 = 22, + SP_D20 = 23, + SP_D21 = 24, + SP_D22 = 25, + SP_D23 = 26, + SP_D24 = 27, + SP_D25 = 28, + SP_D26 = 29, + SP_D27 = 30, + SP_D28 = 31, + SP_D29 = 32, + SP_D30 = 33, + SP_D31 = 34, + SP_F0 = 35, + SP_F1 = 36, + SP_F2 = 37, + SP_F3 = 38, + SP_F4 = 39, + SP_F5 = 40, + SP_F6 = 41, + SP_F7 = 42, + SP_F8 = 43, + SP_F9 = 44, + SP_F10 = 45, + SP_F11 = 46, + SP_F12 = 47, + SP_F13 = 48, + SP_F14 = 49, + SP_F15 = 50, + SP_F16 = 51, + SP_F17 = 52, + SP_F18 = 53, + SP_F19 = 54, + SP_F20 = 55, + SP_F21 = 56, + SP_F22 = 57, + SP_F23 = 58, + SP_F24 = 59, + SP_F25 = 60, + SP_F26 = 61, + SP_F27 = 62, + SP_F28 = 63, + SP_F29 = 64, + SP_F30 = 65, + SP_F31 = 66, + SP_FCC0 = 67, + SP_FCC1 = 68, + SP_FCC2 = 69, + SP_FCC3 = 70, + SP_G0 = 71, + SP_G1 = 72, + SP_G2 = 73, + SP_G3 = 74, + SP_G4 = 75, + SP_G5 = 76, + SP_G6 = 77, + SP_G7 = 78, + SP_I0 = 79, + SP_I1 = 80, + SP_I2 = 81, + SP_I3 = 82, + SP_I4 = 83, + SP_I5 = 84, + SP_I6 = 85, + SP_I7 = 86, + SP_L0 = 87, + SP_L1 = 88, + SP_L2 = 89, + SP_L3 = 90, + SP_L4 = 91, + SP_L5 = 92, + SP_L6 = 93, + SP_L7 = 94, + SP_O0 = 95, + SP_O1 = 96, + SP_O2 = 97, + SP_O3 = 98, + SP_O4 = 99, + SP_O5 = 100, + SP_O6 = 101, + SP_O7 = 102, + SP_Q0 = 103, + SP_Q1 = 104, + SP_Q2 = 105, + SP_Q3 = 106, + SP_Q4 = 107, + SP_Q5 = 108, + SP_Q6 = 109, + SP_Q7 = 110, + SP_Q8 = 111, + SP_Q9 = 112, + SP_Q10 = 113, + SP_Q11 = 114, + SP_Q12 = 115, + SP_Q13 = 116, + SP_Q14 = 117, + SP_Q15 = 118, + SP_NUM_TARGET_REGS // 119 +}; + +// Register classes +enum { + SP_FCCRegsRegClassID = 0, + SP_FPRegsRegClassID = 1, + SP_IntRegsRegClassID = 2, + SP_DFPRegsRegClassID = 3, + SP_I64RegsRegClassID = 4, + SP_DFPRegs_with_sub_evenRegClassID = 5, + SP_QFPRegsRegClassID = 6, + SP_QFPRegs_with_sub_evenRegClassID = 7 +}; + +// Subregister indices +enum { + SP_NoSubRegister, + SP_sub_even, // 1 + SP_sub_even64, // 2 + SP_sub_odd, // 3 + SP_sub_odd64, // 4 + SP_sub_odd64_then_sub_even, // 5 + SP_sub_odd64_then_sub_odd, // 6 + SP_NUM_TARGET_SUBREGS +}; +#endif // GET_REGINFO_ENUM + +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*MC Register Information *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + + +#ifdef GET_REGINFO_MC_DESC +#undef GET_REGINFO_MC_DESC + +static MCPhysReg SparcRegDiffLists[] = { + /* 0 */ 65126, 1, 1, 1, 0, + /* 5 */ 32, 1, 0, + /* 8 */ 65436, 32, 1, 65504, 33, 1, 0, + /* 15 */ 34, 1, 0, + /* 18 */ 65437, 34, 1, 65502, 35, 1, 0, + /* 25 */ 36, 1, 0, + /* 28 */ 65438, 36, 1, 65500, 37, 1, 0, + /* 35 */ 38, 1, 0, + /* 38 */ 65439, 38, 1, 65498, 39, 1, 0, + /* 45 */ 40, 1, 0, + /* 48 */ 65440, 40, 1, 65496, 41, 1, 0, + /* 55 */ 42, 1, 0, + /* 58 */ 65441, 42, 1, 65494, 43, 1, 0, + /* 65 */ 44, 1, 0, + /* 68 */ 65442, 44, 1, 65492, 45, 1, 0, + /* 75 */ 46, 1, 0, + /* 78 */ 65443, 46, 1, 65490, 47, 1, 0, + /* 85 */ 65348, 1, 0, + /* 88 */ 65444, 1, 0, + /* 91 */ 65445, 1, 0, + /* 94 */ 65446, 1, 0, + /* 97 */ 65447, 1, 0, + /* 100 */ 65448, 1, 0, + /* 103 */ 65449, 1, 0, + /* 106 */ 65450, 1, 0, + /* 109 */ 65451, 1, 0, + /* 112 */ 65532, 1, 0, + /* 115 */ 15, 0, + /* 117 */ 84, 0, + /* 119 */ 85, 0, + /* 121 */ 86, 0, + /* 123 */ 87, 0, + /* 125 */ 88, 0, + /* 127 */ 89, 0, + /* 129 */ 90, 0, + /* 131 */ 91, 0, + /* 133 */ 65488, 92, 0, + /* 136 */ 65489, 92, 0, + /* 139 */ 65489, 93, 0, + /* 142 */ 65490, 93, 0, + /* 145 */ 65491, 93, 0, + /* 148 */ 65491, 94, 0, + /* 151 */ 65492, 94, 0, + /* 154 */ 65493, 94, 0, + /* 157 */ 65493, 95, 0, + /* 160 */ 65494, 95, 0, + /* 163 */ 65495, 95, 0, + /* 166 */ 65495, 96, 0, + /* 169 */ 65496, 96, 0, + /* 172 */ 65497, 96, 0, + /* 175 */ 65497, 97, 0, + /* 178 */ 65498, 97, 0, + /* 181 */ 65499, 97, 0, + /* 184 */ 65499, 98, 0, + /* 187 */ 65500, 98, 0, + /* 190 */ 65501, 98, 0, + /* 193 */ 65501, 99, 0, + /* 196 */ 65502, 99, 0, + /* 199 */ 65503, 99, 0, + /* 202 */ 65503, 100, 0, + /* 205 */ 65504, 100, 0, + /* 208 */ 65503, 0, + /* 210 */ 65519, 0, + /* 212 */ 65535, 0, +}; + +static uint16_t SparcSubRegIdxLists[] = { + /* 0 */ 1, 3, 0, + /* 3 */ 2, 4, 0, + /* 6 */ 2, 1, 3, 4, 5, 6, 0, +}; + +static MCRegisterDesc SparcRegDesc[] = { // Descriptors + { 3, 0, 0, 0, 0 }, + { 406, 4, 4, 2, 3393 }, + { 410, 4, 4, 2, 3393 }, + { 33, 5, 203, 0, 1794 }, + { 87, 12, 194, 0, 1794 }, + { 133, 15, 194, 0, 1794 }, + { 179, 22, 185, 0, 1794 }, + { 220, 25, 185, 0, 1794 }, + { 261, 32, 176, 0, 1794 }, + { 298, 35, 176, 0, 1794 }, + { 335, 42, 167, 0, 1794 }, + { 372, 45, 167, 0, 1794 }, + { 397, 52, 158, 0, 1794 }, + { 0, 55, 158, 0, 1794 }, + { 54, 62, 149, 0, 1794 }, + { 108, 65, 149, 0, 1794 }, + { 154, 72, 140, 0, 1794 }, + { 200, 75, 140, 0, 1794 }, + { 241, 82, 134, 0, 1794 }, + { 282, 4, 134, 2, 1841 }, + { 319, 4, 131, 2, 1841 }, + { 356, 4, 131, 2, 1841 }, + { 381, 4, 129, 2, 1841 }, + { 12, 4, 129, 2, 1841 }, + { 66, 4, 127, 2, 1841 }, + { 120, 4, 127, 2, 1841 }, + { 166, 4, 125, 2, 1841 }, + { 212, 4, 125, 2, 1841 }, + { 253, 4, 123, 2, 1841 }, + { 290, 4, 123, 2, 1841 }, + { 327, 4, 121, 2, 1841 }, + { 364, 4, 121, 2, 1841 }, + { 389, 4, 119, 2, 1841 }, + { 20, 4, 119, 2, 1841 }, + { 74, 4, 117, 2, 1841 }, + { 36, 4, 205, 2, 3329 }, + { 90, 4, 202, 2, 3329 }, + { 136, 4, 199, 2, 3329 }, + { 182, 4, 196, 2, 3329 }, + { 223, 4, 196, 2, 3329 }, + { 264, 4, 193, 2, 3329 }, + { 301, 4, 190, 2, 3329 }, + { 338, 4, 187, 2, 3329 }, + { 375, 4, 187, 2, 3329 }, + { 400, 4, 184, 2, 3329 }, + { 4, 4, 181, 2, 3329 }, + { 58, 4, 178, 2, 3329 }, + { 112, 4, 178, 2, 3329 }, + { 158, 4, 175, 2, 3329 }, + { 204, 4, 172, 2, 3329 }, + { 245, 4, 169, 2, 3329 }, + { 286, 4, 169, 2, 3329 }, + { 323, 4, 166, 2, 3329 }, + { 360, 4, 163, 2, 3329 }, + { 385, 4, 160, 2, 3329 }, + { 16, 4, 160, 2, 3329 }, + { 70, 4, 157, 2, 3329 }, + { 124, 4, 154, 2, 3329 }, + { 170, 4, 151, 2, 3329 }, + { 216, 4, 151, 2, 3329 }, + { 257, 4, 148, 2, 3329 }, + { 294, 4, 145, 2, 3329 }, + { 331, 4, 142, 2, 3329 }, + { 368, 4, 142, 2, 3329 }, + { 393, 4, 139, 2, 3329 }, + { 24, 4, 136, 2, 3329 }, + { 78, 4, 133, 2, 3329 }, + { 28, 4, 4, 2, 3361 }, + { 82, 4, 4, 2, 3361 }, + { 128, 4, 4, 2, 3361 }, + { 174, 4, 4, 2, 3361 }, + { 39, 4, 4, 2, 3361 }, + { 93, 4, 4, 2, 3361 }, + { 139, 4, 4, 2, 3361 }, + { 185, 4, 4, 2, 3361 }, + { 226, 4, 4, 2, 3361 }, + { 267, 4, 4, 2, 3361 }, + { 304, 4, 4, 2, 3361 }, + { 341, 4, 4, 2, 3361 }, + { 42, 4, 4, 2, 3361 }, + { 96, 4, 4, 2, 3361 }, + { 142, 4, 4, 2, 3361 }, + { 188, 4, 4, 2, 3361 }, + { 229, 4, 4, 2, 3361 }, + { 270, 4, 4, 2, 3361 }, + { 307, 4, 4, 2, 3361 }, + { 344, 4, 4, 2, 3361 }, + { 45, 4, 4, 2, 3361 }, + { 99, 4, 4, 2, 3361 }, + { 145, 4, 4, 2, 3361 }, + { 191, 4, 4, 2, 3361 }, + { 232, 4, 4, 2, 3361 }, + { 273, 4, 4, 2, 3361 }, + { 310, 4, 4, 2, 3361 }, + { 347, 4, 4, 2, 3361 }, + { 48, 4, 4, 2, 3361 }, + { 102, 4, 4, 2, 3361 }, + { 148, 4, 4, 2, 3361 }, + { 194, 4, 4, 2, 3361 }, + { 235, 4, 4, 2, 3361 }, + { 276, 4, 4, 2, 3361 }, + { 313, 4, 4, 2, 3361 }, + { 350, 4, 4, 2, 3361 }, + { 51, 8, 4, 6, 4 }, + { 105, 18, 4, 6, 4 }, + { 151, 28, 4, 6, 4 }, + { 197, 38, 4, 6, 4 }, + { 238, 48, 4, 6, 4 }, + { 279, 58, 4, 6, 4 }, + { 316, 68, 4, 6, 4 }, + { 353, 78, 4, 6, 4 }, + { 378, 88, 4, 3, 1362 }, + { 403, 91, 4, 3, 1362 }, + { 8, 94, 4, 3, 1362 }, + { 62, 97, 4, 3, 1362 }, + { 116, 100, 4, 3, 1362 }, + { 162, 103, 4, 3, 1362 }, + { 208, 106, 4, 3, 1362 }, + { 249, 109, 4, 3, 1362 }, +}; + + // FCCRegs Register Class... + static uint16_t FCCRegs[] = { + SP_FCC0, SP_FCC1, SP_FCC2, SP_FCC3, + }; + + // FCCRegs Bit set. + static uint8_t FCCRegsBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, + }; + + // FPRegs Register Class... + static uint16_t FPRegs[] = { + SP_F0, SP_F1, SP_F2, SP_F3, SP_F4, SP_F5, SP_F6, SP_F7, SP_F8, SP_F9, SP_F10, SP_F11, SP_F12, SP_F13, SP_F14, SP_F15, SP_F16, SP_F17, SP_F18, SP_F19, SP_F20, SP_F21, SP_F22, SP_F23, SP_F24, SP_F25, SP_F26, SP_F27, SP_F28, SP_F29, SP_F30, SP_F31, + }; + + // FPRegs Bit set. + static uint8_t FPRegsBits[] = { + 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, + }; + + // IntRegs Register Class... + static uint16_t IntRegs[] = { + SP_I0, SP_I1, SP_I2, SP_I3, SP_I4, SP_I5, SP_I6, SP_I7, SP_G0, SP_G1, SP_G2, SP_G3, SP_G4, SP_G5, SP_G6, SP_G7, SP_L0, SP_L1, SP_L2, SP_L3, SP_L4, SP_L5, SP_L6, SP_L7, SP_O0, SP_O1, SP_O2, SP_O3, SP_O4, SP_O5, SP_O6, SP_O7, + }; + + // IntRegs Bit set. + static uint8_t IntRegsBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, + }; + + // DFPRegs Register Class... + static uint16_t DFPRegs[] = { + SP_D0, SP_D1, SP_D2, SP_D3, SP_D4, SP_D5, SP_D6, SP_D7, SP_D8, SP_D9, SP_D10, SP_D11, SP_D12, SP_D13, SP_D14, SP_D15, SP_D16, SP_D17, SP_D18, SP_D19, SP_D20, SP_D21, SP_D22, SP_D23, SP_D24, SP_D25, SP_D26, SP_D27, SP_D28, SP_D29, SP_D30, SP_D31, + }; + + // DFPRegs Bit set. + static uint8_t DFPRegsBits[] = { + 0xf8, 0xff, 0xff, 0xff, 0x07, + }; + + // I64Regs Register Class... + static uint16_t I64Regs[] = { + SP_I0, SP_I1, SP_I2, SP_I3, SP_I4, SP_I5, SP_I6, SP_I7, SP_G0, SP_G1, SP_G2, SP_G3, SP_G4, SP_G5, SP_G6, SP_G7, SP_L0, SP_L1, SP_L2, SP_L3, SP_L4, SP_L5, SP_L6, SP_L7, SP_O0, SP_O1, SP_O2, SP_O3, SP_O4, SP_O5, SP_O6, SP_O7, + }; + + // I64Regs Bit set. + static uint8_t I64RegsBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, + }; + + // DFPRegs_with_sub_even Register Class... + static uint16_t DFPRegs_with_sub_even[] = { + SP_D0, SP_D1, SP_D2, SP_D3, SP_D4, SP_D5, SP_D6, SP_D7, SP_D8, SP_D9, SP_D10, SP_D11, SP_D12, SP_D13, SP_D14, SP_D15, + }; + + // DFPRegs_with_sub_even Bit set. + static uint8_t DFPRegs_with_sub_evenBits[] = { + 0xf8, 0xff, 0x07, + }; + + // QFPRegs Register Class... + static uint16_t QFPRegs[] = { + SP_Q0, SP_Q1, SP_Q2, SP_Q3, SP_Q4, SP_Q5, SP_Q6, SP_Q7, SP_Q8, SP_Q9, SP_Q10, SP_Q11, SP_Q12, SP_Q13, SP_Q14, SP_Q15, + }; + + // QFPRegs Bit set. + static uint8_t QFPRegsBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, + }; + + // QFPRegs_with_sub_even Register Class... + static uint16_t QFPRegs_with_sub_even[] = { + SP_Q0, SP_Q1, SP_Q2, SP_Q3, SP_Q4, SP_Q5, SP_Q6, SP_Q7, + }; + + // QFPRegs_with_sub_even Bit set. + static uint8_t QFPRegs_with_sub_evenBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, + }; + +static MCRegisterClass SparcMCRegisterClasses[] = { + { "FCCRegs", FCCRegs, FCCRegsBits, 4, sizeof(FCCRegsBits), SP_FCCRegsRegClassID, 0, 0, 1, 1 }, + { "FPRegs", FPRegs, FPRegsBits, 32, sizeof(FPRegsBits), SP_FPRegsRegClassID, 4, 4, 1, 1 }, + { "IntRegs", IntRegs, IntRegsBits, 32, sizeof(IntRegsBits), SP_IntRegsRegClassID, 4, 4, 1, 1 }, + { "DFPRegs", DFPRegs, DFPRegsBits, 32, sizeof(DFPRegsBits), SP_DFPRegsRegClassID, 8, 8, 1, 1 }, + { "I64Regs", I64Regs, I64RegsBits, 32, sizeof(I64RegsBits), SP_I64RegsRegClassID, 8, 8, 1, 1 }, + { "DFPRegs_with_sub_even", DFPRegs_with_sub_even, DFPRegs_with_sub_evenBits, 16, sizeof(DFPRegs_with_sub_evenBits), SP_DFPRegs_with_sub_evenRegClassID, 8, 8, 1, 1 }, + { "QFPRegs", QFPRegs, QFPRegsBits, 16, sizeof(QFPRegsBits), SP_QFPRegsRegClassID, 16, 16, 1, 1 }, + { "QFPRegs_with_sub_even", QFPRegs_with_sub_even, QFPRegs_with_sub_evenBits, 8, sizeof(QFPRegs_with_sub_evenBits), SP_QFPRegs_with_sub_evenRegClassID, 16, 16, 1, 1 }, +}; + +#endif // GET_REGINFO_MC_DESC diff --git a/arch/Sparc/SparcGenSubtargetInfo.inc b/arch/Sparc/SparcGenSubtargetInfo.inc new file mode 100644 index 0000000000..afe5108f6e --- /dev/null +++ b/arch/Sparc/SparcGenSubtargetInfo.inc @@ -0,0 +1,27 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*Subtarget Enumeration Source Fragment *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2014 */ + + +#ifdef GET_SUBTARGETINFO_ENUM +#undef GET_SUBTARGETINFO_ENUM + +enum { + Sparc_FeatureHardQuad = 1ULL << 0, + Sparc_FeatureV8Deprecated = 1ULL << 1, + Sparc_FeatureV9 = 1ULL << 2, + Sparc_FeatureVIS = 1ULL << 3, + Sparc_FeatureVIS2 = 1ULL << 4, + Sparc_FeatureVIS3 = 1ULL << 5, + Sparc_UsePopc = 1ULL << 6 +}; + +#endif // GET_SUBTARGETINFO_ENUM + diff --git a/arch/Sparc/SparcInstPrinter.c b/arch/Sparc/SparcInstPrinter.c new file mode 100644 index 0000000000..345d41fe7c --- /dev/null +++ b/arch/Sparc/SparcInstPrinter.c @@ -0,0 +1,266 @@ +//===-- SparcInstPrinter.cpp - Convert Sparc MCInst to assembly syntax --------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This class prints an Sparc MCInst to a .s file. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2014 */ + +#include +#include +#include + +#include "SparcInstPrinter.h" +#include "../../MCInst.h" +#include "../../utils.h" +#include "../../SStream.h" +#include "../../MCRegisterInfo.h" +#include "../../MathExtras.h" +#include "SparcMapping.h" + +#include "Sparc.h" + +static const char *getRegisterName(unsigned RegNo); +static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI); +static void printMemOperand(MCInst *MI, int opNum, SStream *O, const char *Modifier); +static void printOperand(MCInst *MI, int opNum, SStream *O); + +static void set_mem_access(MCInst *MI, bool status) +{ + if (MI->csh->detail != CS_OPT_ON) + return; + + MI->csh->doing_mem = status; + + if (status) { + MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].type = SPARC_OP_MEM; + MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].mem.base = SPARC_REG_INVALID; + MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].mem.disp = 0; + } else { + // done, create the next operand slot + MI->flat_insn.sparc.op_count++; + } +} + +void Sparc_post_printer(csh ud, cs_insn *insn, char *insn_asm) +{ + if (((cs_struct *)ud)->detail != CS_OPT_ON) + return; + + // fix up some instructions + if (insn->id == SPARC_INS_CASX) { + // first op is actually a memop, not regop + insn->detail->sparc.operands[0].type = SPARC_OP_MEM; + insn->detail->sparc.operands[0].mem.base = insn->detail->sparc.operands[0].reg; + insn->detail->sparc.operands[0].mem.disp = 0; + } +} + +static void printRegName(SStream *OS, unsigned RegNo) +{ + SStream_concat(OS, "%%%s", getRegisterName(RegNo)); +} + +#define GET_INSTRINFO_ENUM +#include "SparcGenInstrInfo.inc" + +#define GET_REGINFO_ENUM +#include "SparcGenRegisterInfo.inc" + +static bool printSparcAliasInstr(MCInst *MI, SStream *O) +{ + switch (MCInst_getOpcode(MI)) { + default: return false; + case SP_JMPLrr: + case SP_JMPLri: + if (MCInst_getNumOperands(MI) != 3) + return false; + if (!MCOperand_isReg(MCInst_getOperand(MI, 0))) + return false; + + switch (MCOperand_getReg(MCInst_getOperand(MI, 0))) { + default: return false; + case SP_G0: // jmp $addr | ret | retl + if (MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { + switch(MCOperand_getReg(MCInst_getOperand(MI, 1))) { + default: break; + case SP_I7: SStream_concat(O, "\tret"); return true; + case SP_O7: SStream_concat(O, "\tretl"); return true; + } + } + + SStream_concat(O, "\tjmp "); + printMemOperand(MI, 1, O, NULL); + return true; + case SP_O7: // call $addr + SStream_concat(O, "\tcall "); + printMemOperand(MI, 1, O, NULL); + return true; + } + case SP_V9FCMPS: + case SP_V9FCMPD: + case SP_V9FCMPQ: + case SP_V9FCMPES: + case SP_V9FCMPED: + case SP_V9FCMPEQ: + if (MI->csh->mode & CS_MODE_V9 || (MCInst_getNumOperands(MI) != 3) || + (!MCOperand_isReg(MCInst_getOperand(MI, 0))) || + (MCOperand_getReg(MCInst_getOperand(MI, 0)) != SP_FCC0)) + return false; + // if V8, skip printing %fcc0. + switch(MCInst_getOpcode(MI)) { + default: + case SP_V9FCMPS: SStream_concat(O, "\tfcmps "); break; + case SP_V9FCMPD: SStream_concat(O, "\tfcmpd "); break; + case SP_V9FCMPQ: SStream_concat(O, "\tfcmpq "); break; + case SP_V9FCMPES: SStream_concat(O, "\tfcmpes "); break; + case SP_V9FCMPED: SStream_concat(O, "\tfcmped "); break; + case SP_V9FCMPEQ: SStream_concat(O, "\tfcmpeq "); break; + } + printOperand(MI, 1, O); + SStream_concat(O, ", "); + printOperand(MI, 2, O); + return true; + } +} + +static void printOperand(MCInst *MI, int opNum, SStream *O) +{ + int Imm; + unsigned reg; + MCOperand *MO = MCInst_getOperand(MI, opNum); + + if (MCOperand_isReg(MO)) { + reg = MCOperand_getReg(MO); + printRegName(O, reg); + reg = Sparc_map_register(reg); + + if (MI->csh->detail) { + if (MI->csh->doing_mem) { + if (MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].mem.base) + MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].mem.index = reg; + else + MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].mem.base = reg; + } else { + MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].type = SPARC_OP_REG; + MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].reg = reg; + MI->flat_insn.sparc.op_count++; + } + } + + return; + } + + if (MCOperand_isImm(MO)) { + Imm = (int)MCOperand_getImm(MO); + if (Imm > HEX_THRESHOLD) + SStream_concat(O, "0x%x", Imm); + else + SStream_concat(O, "%u", Imm); + + if (MI->csh->detail) { + if (MI->csh->doing_mem) { + MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].mem.disp = Imm; + } else { + MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].type = SPARC_OP_IMM; + MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].imm = Imm; + MI->flat_insn.sparc.op_count++; + } + } + } + + return; +} + +static void printMemOperand(MCInst *MI, int opNum, SStream *O, const char *Modifier) +{ + MCOperand *MO; + + set_mem_access(MI, true); + printOperand(MI, opNum, O); + + // If this is an ADD operand, emit it like normal operands. + if (Modifier && !strcmp(Modifier, "arith")) { + SStream_concat(O, ", "); + printOperand(MI, opNum + 1, O); + set_mem_access(MI, false); + return; + } + + MO = MCInst_getOperand(MI, opNum + 1); + + if (MCOperand_isReg(MO) && (MCOperand_getReg(MO) == SP_G0)) { + set_mem_access(MI, false); + return; // don't print "+%g0" + } + + if (MCOperand_isImm(MO) && (MCOperand_getImm(MO) == 0)) { + set_mem_access(MI, false); + return; // don't print "+0" + } + + SStream_concat(O, "+"); + + printOperand(MI, opNum + 1, O); + set_mem_access(MI, false); +} + +static void printCCOperand(MCInst *MI, int opNum, SStream *O) +{ + int CC = (int)MCOperand_getImm(MCInst_getOperand(MI, opNum)); + + switch (MCInst_getOpcode(MI)) { + default: break; + case SP_FBCOND: + case SP_FBCONDA: + case SP_BPFCC: + case SP_BPFCCA: + case SP_BPFCCNT: + case SP_BPFCCANT: + case SP_MOVFCCrr: case SP_V9MOVFCCrr: + case SP_MOVFCCri: case SP_V9MOVFCCri: + case SP_FMOVS_FCC: case SP_V9FMOVS_FCC: + case SP_FMOVD_FCC: case SP_V9FMOVD_FCC: + case SP_FMOVQ_FCC: case SP_V9FMOVQ_FCC: + // Make sure CC is a fp conditional flag. + CC = (CC < 16) ? (CC + 16) : CC; + break; + } + + SStream_concat(O, "%s", SPARCCondCodeToString((sparc_cc)CC)); + + if (MI->csh->detail) + MI->flat_insn.sparc.cc = (sparc_cc)CC; +} + + +static bool printGetPCX(MCInst *MI, unsigned opNum, SStream *O) +{ + return true; +} + + +#define PRINT_ALIAS_INSTR +#include "SparcGenAsmWriter.inc" + +void Sparc_printInst(MCInst *MI, SStream *O, void *Info) +{ + char *mnem; + + mnem = printAliasInstr(MI, O, Info); + if (mnem) + cs_mem_free(mnem); + else { + if (!printSparcAliasInstr(MI, O)) + printInstruction(MI, O, NULL); + } +} diff --git a/arch/Sparc/SparcInstPrinter.h b/arch/Sparc/SparcInstPrinter.h new file mode 100644 index 0000000000..4e6a5cef37 --- /dev/null +++ b/arch/Sparc/SparcInstPrinter.h @@ -0,0 +1,15 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2014 */ + +#ifndef CS_SPARCINSTPRINTER_H +#define CS_SPARCINSTPRINTER_H + +#include "../../MCInst.h" +#include "../../MCRegisterInfo.h" +#include "../../SStream.h" + +void Sparc_printInst(MCInst *MI, SStream *O, void *Info); + +void Sparc_post_printer(csh ud, cs_insn *insn, char *insn_asm); + +#endif diff --git a/arch/Sparc/SparcMapping.c b/arch/Sparc/SparcMapping.c new file mode 100644 index 0000000000..3efbf4b223 --- /dev/null +++ b/arch/Sparc/SparcMapping.c @@ -0,0 +1,3179 @@ +/* Capstone Unified Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2014 */ + +#include // debug +#include + +#include "../../include/sparc.h" +#include "../../utils.h" + +#include "SparcMapping.h" + +#define GET_INSTRINFO_ENUM +#include "SparcGenInstrInfo.inc" + +#ifndef CAPSTONE_DIET +static name_map reg_name_maps[] = { + { SPARC_REG_INVALID, NULL }, + + { SPARC_REG_F0, "f0"}, + { SPARC_REG_F1, "f1"}, + { SPARC_REG_F2, "f2"}, + { SPARC_REG_F3, "f3"}, + { SPARC_REG_F4, "f4"}, + { SPARC_REG_F5, "f5"}, + { SPARC_REG_F6, "f6"}, + { SPARC_REG_F7, "f7"}, + { SPARC_REG_F8, "f8"}, + { SPARC_REG_F9, "f9"}, + { SPARC_REG_F10, "f10"}, + { SPARC_REG_F11, "f11"}, + { SPARC_REG_F12, "f12"}, + { SPARC_REG_F13, "f13"}, + { SPARC_REG_F14, "f14"}, + { SPARC_REG_F15, "f15"}, + { SPARC_REG_F16, "f16"}, + { SPARC_REG_F17, "f17"}, + { SPARC_REG_F18, "f18"}, + { SPARC_REG_F19, "f19"}, + { SPARC_REG_F20, "f20"}, + { SPARC_REG_F21, "f21"}, + { SPARC_REG_F22, "f22"}, + { SPARC_REG_F23, "f23"}, + { SPARC_REG_F24, "f24"}, + { SPARC_REG_F25, "f25"}, + { SPARC_REG_F26, "f26"}, + { SPARC_REG_F27, "f27"}, + { SPARC_REG_F28, "f28"}, + { SPARC_REG_F29, "f29"}, + { SPARC_REG_F30, "f30"}, + { SPARC_REG_F31, "f31"}, + { SPARC_REG_F32, "f32"}, + { SPARC_REG_F34, "f34"}, + { SPARC_REG_F36, "f36"}, + { SPARC_REG_F38, "f38"}, + { SPARC_REG_F40, "f40"}, + { SPARC_REG_F42, "f42"}, + { SPARC_REG_F44, "f44"}, + { SPARC_REG_F46, "f46"}, + { SPARC_REG_F48, "f48"}, + { SPARC_REG_F50, "f50"}, + { SPARC_REG_F52, "f52"}, + { SPARC_REG_F54, "f54"}, + { SPARC_REG_F56, "f56"}, + { SPARC_REG_F58, "f58"}, + { SPARC_REG_F60, "f60"}, + { SPARC_REG_F62, "f62"}, + { SPARC_REG_FCC0, "fcc0"}, + { SPARC_REG_FCC1, "fcc1"}, + { SPARC_REG_FCC2, "fcc2"}, + { SPARC_REG_FCC3, "fcc3"}, + { SPARC_REG_FP, "fp"}, + { SPARC_REG_G0, "g0"}, + { SPARC_REG_G1, "g1"}, + { SPARC_REG_G2, "g2"}, + { SPARC_REG_G3, "g3"}, + { SPARC_REG_G4, "g4"}, + { SPARC_REG_G5, "g5"}, + { SPARC_REG_G6, "g6"}, + { SPARC_REG_G7, "g7"}, + { SPARC_REG_I0, "i0"}, + { SPARC_REG_I1, "i1"}, + { SPARC_REG_I2, "i2"}, + { SPARC_REG_I3, "i3"}, + { SPARC_REG_I4, "i4"}, + { SPARC_REG_I5, "i5"}, + { SPARC_REG_I7, "i7"}, + { SPARC_REG_ICC, "icc"}, + { SPARC_REG_L0, "l0"}, + { SPARC_REG_L1, "l1"}, + { SPARC_REG_L2, "l2"}, + { SPARC_REG_L3, "l3"}, + { SPARC_REG_L4, "l4"}, + { SPARC_REG_L5, "l5"}, + { SPARC_REG_L6, "l6"}, + { SPARC_REG_L7, "l7"}, + { SPARC_REG_O0, "o0"}, + { SPARC_REG_O1, "o1"}, + { SPARC_REG_O2, "o2"}, + { SPARC_REG_O3, "o3"}, + { SPARC_REG_O4, "o4"}, + { SPARC_REG_O5, "o5"}, + { SPARC_REG_O7, "o7"}, + { SPARC_REG_SP, "sp"}, + { SPARC_REG_Y, "y"}, +}; +#endif + +const char *Sparc_reg_name(csh handle, unsigned int reg) +{ +#ifndef CAPSTONE_DIET + if (reg >= SPARC_REG_MAX) + return NULL; + + return reg_name_maps[reg].name; +#else + return NULL; +#endif +} + +static insn_map insns[] = { + // dummy item + { + 0, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { + SP_ADDCCri, SPARC_INS_ADDCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_ADDCCrr, SPARC_INS_ADDCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_ADDCri, SPARC_INS_ADDX, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_ADDCrr, SPARC_INS_ADDX, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_ADDEri, SPARC_INS_ADDXCC, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_ADDErr, SPARC_INS_ADDXCC, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_ADDXC, SPARC_INS_ADDXC, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_ADDXCCC, SPARC_INS_ADDXCCC, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { SPARC_REG_ICC, 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_ADDXri, SPARC_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_ADDXrr, SPARC_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_ADDri, SPARC_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_ADDrr, SPARC_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_ALIGNADDR, SPARC_INS_ALIGNADDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_ALIGNADDRL, SPARC_INS_ALIGNADDRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_ANDCCri, SPARC_INS_ANDCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_ANDCCrr, SPARC_INS_ANDCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_ANDNCCri, SPARC_INS_ANDNCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_ANDNCCrr, SPARC_INS_ANDNCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_ANDNri, SPARC_INS_ANDN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_ANDNrr, SPARC_INS_ANDN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_ANDXNrr, SPARC_INS_ANDN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_ANDXri, SPARC_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_ANDXrr, SPARC_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_ANDri, SPARC_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_ANDrr, SPARC_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_ARRAY16, SPARC_INS_ARRAY16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_ARRAY32, SPARC_INS_ARRAY32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_ARRAY8, SPARC_INS_ARRAY8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_BA, SPARC_INS_BA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif + }, + { + SP_BCOND, SPARC_INS_B, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 1, 0 +#endif + }, + { + SP_BCONDA, SPARC_INS_B, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 1, 0 +#endif + }, + { + SP_BINDri, SPARC_INS_JMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif + }, + { + SP_BINDrr, SPARC_INS_JMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif + }, + { + SP_BMASK, SPARC_INS_BMASK, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 +#endif + }, + { + SP_BPFCC, SPARC_INS_FB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0 +#endif + }, + { + SP_BPFCCA, SPARC_INS_FB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0 +#endif + }, + { + SP_BPFCCANT, SPARC_INS_FB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0 +#endif + }, + { + SP_BPFCCNT, SPARC_INS_FB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0 +#endif + }, + { + SP_BPGEZapn, SPARC_INS_BRGEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif + }, + { + SP_BPGEZapt, SPARC_INS_BRGEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif + }, + { + SP_BPGEZnapn, SPARC_INS_BRGEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif + }, + { + SP_BPGEZnapt, SPARC_INS_BRGEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif + }, + { + SP_BPGZapn, SPARC_INS_BRGZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif + }, + { + SP_BPGZapt, SPARC_INS_BRGZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif + }, + { + SP_BPGZnapn, SPARC_INS_BRGZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif + }, + { + SP_BPGZnapt, SPARC_INS_BRGZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif + }, + { + SP_BPICC, SPARC_INS_B, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0 +#endif + }, + { + SP_BPICCA, SPARC_INS_B, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0 +#endif + }, + { + SP_BPICCANT, SPARC_INS_B, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0 +#endif + }, + { + SP_BPICCNT, SPARC_INS_B, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0 +#endif + }, + { + SP_BPLEZapn, SPARC_INS_BRLEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif + }, + { + SP_BPLEZapt, SPARC_INS_BRLEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif + }, + { + SP_BPLEZnapn, SPARC_INS_BRLEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif + }, + { + SP_BPLEZnapt, SPARC_INS_BRLEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif + }, + { + SP_BPLZapn, SPARC_INS_BRLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif + }, + { + SP_BPLZapt, SPARC_INS_BRLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif + }, + { + SP_BPLZnapn, SPARC_INS_BRLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif + }, + { + SP_BPLZnapt, SPARC_INS_BRLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif + }, + { + SP_BPNZapn, SPARC_INS_BRNZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif + }, + { + SP_BPNZapt, SPARC_INS_BRNZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif + }, + { + SP_BPNZnapn, SPARC_INS_BRNZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif + }, + { + SP_BPNZnapt, SPARC_INS_BRNZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif + }, + { + SP_BPXCC, SPARC_INS_B, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif + }, + { + SP_BPXCCA, SPARC_INS_B, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif + }, + { + SP_BPXCCANT, SPARC_INS_B, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif + }, + { + SP_BPXCCNT, SPARC_INS_B, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif + }, + { + SP_BPZapn, SPARC_INS_BRZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif + }, + { + SP_BPZapt, SPARC_INS_BRZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif + }, + { + SP_BPZnapn, SPARC_INS_BRZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif + }, + { + SP_BPZnapt, SPARC_INS_BRZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif + }, + { + SP_BSHUFFLE, SPARC_INS_BSHUFFLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 +#endif + }, + { + SP_CALL, SPARC_INS_CALL, +#ifndef CAPSTONE_DIET + { SPARC_REG_O6, 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_CALLri, SPARC_INS_CALL, +#ifndef CAPSTONE_DIET + { SPARC_REG_O6, 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_CALLrr, SPARC_INS_CALL, +#ifndef CAPSTONE_DIET + { SPARC_REG_O6, 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_CASXrr, SPARC_INS_CASX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_CASrr, SPARC_INS_CAS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_CMASK16, SPARC_INS_CMASK16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_CMASK32, SPARC_INS_CMASK32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_CMASK8, SPARC_INS_CMASK8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_CMPri, SPARC_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_CMPrr, SPARC_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_EDGE16, SPARC_INS_EDGE16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_EDGE16L, SPARC_INS_EDGE16L, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_EDGE16LN, SPARC_INS_EDGE16LN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 +#endif + }, + { + SP_EDGE16N, SPARC_INS_EDGE16N, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 +#endif + }, + { + SP_EDGE32, SPARC_INS_EDGE32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_EDGE32L, SPARC_INS_EDGE32L, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_EDGE32LN, SPARC_INS_EDGE32LN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 +#endif + }, + { + SP_EDGE32N, SPARC_INS_EDGE32N, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 +#endif + }, + { + SP_EDGE8, SPARC_INS_EDGE8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_EDGE8L, SPARC_INS_EDGE8L, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_EDGE8LN, SPARC_INS_EDGE8LN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 +#endif + }, + { + SP_EDGE8N, SPARC_INS_EDGE8N, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 +#endif + }, + { + SP_FABSD, SPARC_INS_FABSD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_FABSQ, SPARC_INS_FABSQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_FABSS, SPARC_INS_FABSS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_FADDD, SPARC_INS_FADDD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_FADDQ, SPARC_INS_FADDQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif + }, + { + SP_FADDS, SPARC_INS_FADDS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_FALIGNADATA, SPARC_INS_FALIGNDATA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FAND, SPARC_INS_FAND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FANDNOT1, SPARC_INS_FANDNOT1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FANDNOT1S, SPARC_INS_FANDNOT1S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FANDNOT2, SPARC_INS_FANDNOT2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FANDNOT2S, SPARC_INS_FANDNOT2S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FANDS, SPARC_INS_FANDS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FBCOND, SPARC_INS_FB, +#ifndef CAPSTONE_DIET + { SPARC_REG_FCC0, 0 }, { 0 }, { 0 }, 1, 0 +#endif + }, + { + SP_FBCONDA, SPARC_INS_FB, +#ifndef CAPSTONE_DIET + { SPARC_REG_FCC0, 0 }, { 0 }, { 0 }, 1, 0 +#endif + }, + { + SP_FCHKSM16, SPARC_INS_FCHKSM16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_FCMPD, SPARC_INS_FCMPD, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_FCC0, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_FCMPEQ16, SPARC_INS_FCMPEQ16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FCMPEQ32, SPARC_INS_FCMPEQ32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FCMPGT16, SPARC_INS_FCMPGT16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FCMPGT32, SPARC_INS_FCMPGT32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FCMPLE16, SPARC_INS_FCMPLE16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FCMPLE32, SPARC_INS_FCMPLE32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FCMPNE16, SPARC_INS_FCMPNE16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FCMPNE32, SPARC_INS_FCMPNE32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FCMPQ, SPARC_INS_FCMPQ, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_FCC0, 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif + }, + { + SP_FCMPS, SPARC_INS_FCMPS, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_FCC0, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_FDIVD, SPARC_INS_FDIVD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_FDIVQ, SPARC_INS_FDIVQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif + }, + { + SP_FDIVS, SPARC_INS_FDIVS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_FDMULQ, SPARC_INS_FDMULQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif + }, + { + SP_FDTOI, SPARC_INS_FDTOI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_FDTOQ, SPARC_INS_FDTOQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif + }, + { + SP_FDTOS, SPARC_INS_FDTOS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_FDTOX, SPARC_INS_FDTOX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_FEXPAND, SPARC_INS_FEXPAND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FHADDD, SPARC_INS_FHADDD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_FHADDS, SPARC_INS_FHADDS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_FHSUBD, SPARC_INS_FHSUBD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_FHSUBS, SPARC_INS_FHSUBS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_FITOD, SPARC_INS_FITOD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_FITOQ, SPARC_INS_FITOQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif + }, + { + SP_FITOS, SPARC_INS_FITOS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_FLCMPD, SPARC_INS_FLCMPD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_FLCMPS, SPARC_INS_FLCMPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_FLUSHW, SPARC_INS_FLUSHW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_FMEAN16, SPARC_INS_FMEAN16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_FMOVD, SPARC_INS_FMOVD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_FMOVD_FCC, SPARC_INS_FMOVD, +#ifndef CAPSTONE_DIET + { SPARC_REG_FCC0, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_FMOVD_ICC, SPARC_INS_FMOVD, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_FMOVD_XCC, SPARC_INS_FMOVD, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_FMOVQ, SPARC_INS_FMOVQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_FMOVQ_FCC, SPARC_INS_FMOVQ, +#ifndef CAPSTONE_DIET + { SPARC_REG_FCC0, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_FMOVQ_ICC, SPARC_INS_FMOVQ, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_FMOVQ_XCC, SPARC_INS_FMOVQ, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_FMOVRGEZD, SPARC_INS_FMOVRDGEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_FMOVRGEZQ, SPARC_INS_FMOVRQGEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_FMOVRGEZS, SPARC_INS_FMOVRSGEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_FMOVRGZD, SPARC_INS_FMOVRDGZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_FMOVRGZQ, SPARC_INS_FMOVRQGZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_FMOVRGZS, SPARC_INS_FMOVRSGZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_FMOVRLEZD, SPARC_INS_FMOVRDLEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_FMOVRLEZQ, SPARC_INS_FMOVRQLEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_FMOVRLEZS, SPARC_INS_FMOVRSLEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_FMOVRLZD, SPARC_INS_FMOVRDLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_FMOVRLZQ, SPARC_INS_FMOVRQLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_FMOVRLZS, SPARC_INS_FMOVRSLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_FMOVRNZD, SPARC_INS_FMOVRDNZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_FMOVRNZQ, SPARC_INS_FMOVRQNZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_FMOVRNZS, SPARC_INS_FMOVRSNZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_FMOVRZD, SPARC_INS_FMOVRDZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_FMOVRZQ, SPARC_INS_FMOVRQZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_FMOVRZS, SPARC_INS_FMOVRSZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_FMOVS, SPARC_INS_FMOVS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_FMOVS_FCC, SPARC_INS_FMOVS, +#ifndef CAPSTONE_DIET + { SPARC_REG_FCC0, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_FMOVS_ICC, SPARC_INS_FMOVS, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_FMOVS_XCC, SPARC_INS_FMOVS, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_FMUL8SUX16, SPARC_INS_FMUL8SUX16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FMUL8ULX16, SPARC_INS_FMUL8ULX16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FMUL8X16, SPARC_INS_FMUL8X16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FMUL8X16AL, SPARC_INS_FMUL8X16AL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FMUL8X16AU, SPARC_INS_FMUL8X16AU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FMULD, SPARC_INS_FMULD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_FMULD8SUX16, SPARC_INS_FMULD8SUX16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FMULD8ULX16, SPARC_INS_FMULD8ULX16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FMULQ, SPARC_INS_FMULQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif + }, + { + SP_FMULS, SPARC_INS_FMULS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_FNADDD, SPARC_INS_FNADDD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_FNADDS, SPARC_INS_FNADDS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_FNAND, SPARC_INS_FNAND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FNANDS, SPARC_INS_FNANDS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FNEGD, SPARC_INS_FNEGD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_FNEGQ, SPARC_INS_FNEGQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_FNEGS, SPARC_INS_FNEGS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_FNHADDD, SPARC_INS_FNHADDD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_FNHADDS, SPARC_INS_FNHADDS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_FNMULD, SPARC_INS_FNHADDD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_FNMULS, SPARC_INS_FNHADDS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_FNOR, SPARC_INS_FNOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FNORS, SPARC_INS_FNORS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FNOT1, SPARC_INS_FNOT1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FNOT1S, SPARC_INS_FNOT1S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FNOT2, SPARC_INS_FNOT2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FNOT2S, SPARC_INS_FNOT2S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FNSMULD, SPARC_INS_FNHADDS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_FONE, SPARC_INS_FONE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FONES, SPARC_INS_FONES, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FOR, SPARC_INS_FOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FORNOT1, SPARC_INS_FORNOT1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FORNOT1S, SPARC_INS_FORNOT1S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FORNOT2, SPARC_INS_FORNOT2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FORNOT2S, SPARC_INS_FORNOT2S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FORS, SPARC_INS_FORS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FPACK16, SPARC_INS_FPACK16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FPACK32, SPARC_INS_FPACK32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FPACKFIX, SPARC_INS_FPACKFIX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FPADD16, SPARC_INS_FPADD16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FPADD16S, SPARC_INS_FPADD16S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FPADD32, SPARC_INS_FPADD32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FPADD32S, SPARC_INS_FPADD32S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FPADD64, SPARC_INS_FPADD64, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_FPMERGE, SPARC_INS_FPMERGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FPSUB16, SPARC_INS_FPSUB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FPSUB16S, SPARC_INS_FPSUB16S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FPSUB32, SPARC_INS_FPSUB32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FPSUB32S, SPARC_INS_FPSUB32S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FQTOD, SPARC_INS_FQTOD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif + }, + { + SP_FQTOI, SPARC_INS_FQTOI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif + }, + { + SP_FQTOS, SPARC_INS_FQTOS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif + }, + { + SP_FQTOX, SPARC_INS_FQTOX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_FSLAS16, SPARC_INS_FSLAS16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_FSLAS32, SPARC_INS_FSLAS32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_FSLL16, SPARC_INS_FSLL16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_FSLL32, SPARC_INS_FSLL32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_FSMULD, SPARC_INS_FSMULD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_FSQRTD, SPARC_INS_FSQRTD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_FSQRTQ, SPARC_INS_FSQRTQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif + }, + { + SP_FSQRTS, SPARC_INS_FSQRTS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_FSRA16, SPARC_INS_FSRA16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_FSRA32, SPARC_INS_FSRA32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_FSRC1, SPARC_INS_FSRC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FSRC1S, SPARC_INS_FSRC1S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FSRC2, SPARC_INS_FSRC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FSRC2S, SPARC_INS_FSRC2S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FSRL16, SPARC_INS_FSRL16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_FSRL32, SPARC_INS_FSRL32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_FSTOD, SPARC_INS_FSTOD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_FSTOI, SPARC_INS_FSTOI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_FSTOQ, SPARC_INS_FSTOQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif + }, + { + SP_FSTOX, SPARC_INS_FSTOX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_FSUBD, SPARC_INS_FSUBD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_FSUBQ, SPARC_INS_FSUBQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif + }, + { + SP_FSUBS, SPARC_INS_FSUBS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_FXNOR, SPARC_INS_FXNOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FXNORS, SPARC_INS_FXNORS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FXOR, SPARC_INS_FXOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FXORS, SPARC_INS_FXORS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FXTOD, SPARC_INS_FXTOD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_FXTOQ, SPARC_INS_FXTOQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_FXTOS, SPARC_INS_FXTOS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_FZERO, SPARC_INS_FZERO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_FZEROS, SPARC_INS_FZEROS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_JMPLri, SPARC_INS_JMPL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_JMPLrr, SPARC_INS_JMPL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_LDDFri, SPARC_INS_LDD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_LDDFrr, SPARC_INS_LDD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_LDFri, SPARC_INS_LD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_LDFrr, SPARC_INS_LD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_LDQFri, SPARC_INS_LDQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif + }, + { + SP_LDQFrr, SPARC_INS_LDQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif + }, + { + SP_LDSBri, SPARC_INS_LDSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_LDSBrr, SPARC_INS_LDSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_LDSHri, SPARC_INS_LDSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_LDSHrr, SPARC_INS_LDSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_LDSWri, SPARC_INS_LDSW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_LDSWrr, SPARC_INS_LDSW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_LDUBri, SPARC_INS_LDUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_LDUBrr, SPARC_INS_LDUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_LDUHri, SPARC_INS_LDUH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_LDUHrr, SPARC_INS_LDUH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_LDXri, SPARC_INS_LDX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_LDXrr, SPARC_INS_LDX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_LDri, SPARC_INS_LD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_LDrr, SPARC_INS_LD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_LEAX_ADDri, SPARC_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_LEA_ADDri, SPARC_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_32BIT, 0 }, 0, 0 +#endif + }, + { + SP_LZCNT, SPARC_INS_LZCNT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_MEMBARi, SPARC_INS_MEMBAR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_MOVDTOX, SPARC_INS_MOVDTOX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_MOVFCCri, SPARC_INS_MOV, +#ifndef CAPSTONE_DIET + { SPARC_REG_FCC0, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_MOVFCCrr, SPARC_INS_MOV, +#ifndef CAPSTONE_DIET + { SPARC_REG_FCC0, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_MOVICCri, SPARC_INS_MOV, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_MOVICCrr, SPARC_INS_MOV, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_MOVRGEZri, SPARC_INS_MOVRGEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_MOVRGEZrr, SPARC_INS_MOVRGEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_MOVRGZri, SPARC_INS_MOVRGZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_MOVRGZrr, SPARC_INS_MOVRGZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_MOVRLEZri, SPARC_INS_MOVRLEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_MOVRLEZrr, SPARC_INS_MOVRLEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_MOVRLZri, SPARC_INS_MOVRLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_MOVRLZrr, SPARC_INS_MOVRLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_MOVRNZri, SPARC_INS_MOVRNZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_MOVRNZrr, SPARC_INS_MOVRNZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_MOVRRZri, SPARC_INS_MOVRZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_MOVRRZrr, SPARC_INS_MOVRZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_MOVSTOSW, SPARC_INS_MOVSTOSW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_MOVSTOUW, SPARC_INS_MOVSTOUW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_MOVWTOS, SPARC_INS_MOVDTOX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_MOVXCCri, SPARC_INS_MOV, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_MOVXCCrr, SPARC_INS_MOV, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_MOVXTOD, SPARC_INS_MOVDTOX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_MULXri, SPARC_INS_MULX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_MULXrr, SPARC_INS_MULX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_NOP, SPARC_INS_NOP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_ORCCri, SPARC_INS_ORCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_ORCCrr, SPARC_INS_ORCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_ORNCCri, SPARC_INS_ORNCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_ORNCCrr, SPARC_INS_ORNCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_ORNri, SPARC_INS_ORN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_ORNrr, SPARC_INS_ORN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_ORXNrr, SPARC_INS_ORN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_ORXri, SPARC_INS_OR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_ORXrr, SPARC_INS_OR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_ORri, SPARC_INS_OR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_ORrr, SPARC_INS_OR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_PDIST, SPARC_INS_PDIST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_PDISTN, SPARC_INS_PDISTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_POPCrr, SPARC_INS_POPC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_RDY, SPARC_INS_RD, +#ifndef CAPSTONE_DIET + { SPARC_REG_Y, 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_RESTOREri, SPARC_INS_RESTORE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_RESTORErr, SPARC_INS_RESTORE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_RET, SPARC_INS_JMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_RETL, SPARC_INS_JMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_RETTri, SPARC_INS_RETT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_RETTrr, SPARC_INS_RETT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_SAVEri, SPARC_INS_SAVE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_SAVErr, SPARC_INS_SAVE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_SDIVCCri, SPARC_INS_SDIVCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_SDIVCCrr, SPARC_INS_SDIVCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_SDIVXri, SPARC_INS_SDIVX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_SDIVXrr, SPARC_INS_SDIVX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_SDIVri, SPARC_INS_SDIV, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_SDIVrr, SPARC_INS_SDIV, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_SETHIXi, SPARC_INS_SETHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_SETHIi, SPARC_INS_SETHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_SHUTDOWN, SPARC_INS_SHUTDOWN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif + }, + { + SP_SIAM, SPARC_INS_SIAM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 +#endif + }, + { + SP_SLLXri, SPARC_INS_SLLX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_SLLXrr, SPARC_INS_SLLX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_SLLri, SPARC_INS_SLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_SLLrr, SPARC_INS_SLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_SMULCCri, SPARC_INS_SMULCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_SMULCCrr, SPARC_INS_SMULCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_SMULri, SPARC_INS_SMUL, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_SMULrr, SPARC_INS_SMUL, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_SRAXri, SPARC_INS_SRAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_SRAXrr, SPARC_INS_SRAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_SRAri, SPARC_INS_SRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_SRArr, SPARC_INS_SRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_SRLXri, SPARC_INS_SRLX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_SRLXrr, SPARC_INS_SRLX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_SRLri, SPARC_INS_SRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_SRLrr, SPARC_INS_SRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_STBAR, SPARC_INS_STBAR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_STBri, SPARC_INS_STB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_STBrr, SPARC_INS_STB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_STDFri, SPARC_INS_STD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_STDFrr, SPARC_INS_STD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_STFri, SPARC_INS_ST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_STFrr, SPARC_INS_ST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_STHri, SPARC_INS_STH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_STHrr, SPARC_INS_STH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_STQFri, SPARC_INS_STQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif + }, + { + SP_STQFrr, SPARC_INS_STQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif + }, + { + SP_STXri, SPARC_INS_STX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_STXrr, SPARC_INS_STX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_STri, SPARC_INS_ST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_STrr, SPARC_INS_ST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_SUBCCri, SPARC_INS_SUBCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_SUBCCrr, SPARC_INS_SUBCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_SUBCri, SPARC_INS_SUBX, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_SUBCrr, SPARC_INS_SUBX, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_SUBEri, SPARC_INS_SUBXCC, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_SUBErr, SPARC_INS_SUBXCC, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_SUBXri, SPARC_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_SUBXrr, SPARC_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_SUBri, SPARC_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_SUBrr, SPARC_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_SWAPri, SPARC_INS_SWAP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_SWAPrr, SPARC_INS_SWAP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_TA3, SPARC_INS_TA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_TA5, SPARC_INS_TA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_TADDCCTVri, SPARC_INS_TADDCCTV, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_TADDCCTVrr, SPARC_INS_TADDCCTV, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_TADDCCri, SPARC_INS_TADDCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_TADDCCrr, SPARC_INS_TADDCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_TICCri, SPARC_INS_T, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_TICCrr, SPARC_INS_T, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_TLS_ADDXrr, SPARC_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_TLS_ADDrr, SPARC_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_TLS_CALL, SPARC_INS_CALL, +#ifndef CAPSTONE_DIET + { SPARC_REG_O6, 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_TLS_LDXrr, SPARC_INS_LDX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_TLS_LDrr, SPARC_INS_LD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_TSUBCCTVri, SPARC_INS_TSUBCCTV, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_TSUBCCTVrr, SPARC_INS_TSUBCCTV, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_TSUBCCri, SPARC_INS_TSUBCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_TSUBCCrr, SPARC_INS_TSUBCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_TXCCri, SPARC_INS_T, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_TXCCrr, SPARC_INS_T, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_UDIVCCri, SPARC_INS_UDIVCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_UDIVCCrr, SPARC_INS_UDIVCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_UDIVXri, SPARC_INS_UDIVX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_UDIVXrr, SPARC_INS_UDIVX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_UDIVri, SPARC_INS_UDIV, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_UDIVrr, SPARC_INS_UDIV, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_UMULCCri, SPARC_INS_UMULCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_UMULCCrr, SPARC_INS_UMULCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_UMULXHI, SPARC_INS_UMULXHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_UMULri, SPARC_INS_UMUL, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_UMULrr, SPARC_INS_UMUL, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_UNIMP, SPARC_INS_UNIMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_V9FCMPD, SPARC_INS_FCMPD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_V9FCMPED, SPARC_INS_FCMPED, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_V9FCMPEQ, SPARC_INS_FCMPEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif + }, + { + SP_V9FCMPES, SPARC_INS_FCMPES, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_V9FCMPQ, SPARC_INS_FCMPQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif + }, + { + SP_V9FCMPS, SPARC_INS_FCMPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_V9FMOVD_FCC, SPARC_INS_FMOVD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_V9FMOVQ_FCC, SPARC_INS_FMOVQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_V9FMOVS_FCC, SPARC_INS_FMOVS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_V9MOVFCCri, SPARC_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_V9MOVFCCrr, SPARC_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif + }, + { + SP_WRYri, SPARC_INS_WR, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_WRYrr, SPARC_INS_WR, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_XMULX, SPARC_INS_XMULX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_XMULXHI, SPARC_INS_XMULXHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif + }, + { + SP_XNORCCri, SPARC_INS_XNORCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_XNORCCrr, SPARC_INS_XNORCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_XNORXrr, SPARC_INS_XNOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_XNORri, SPARC_INS_XNOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_XNORrr, SPARC_INS_XNOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_XORCCri, SPARC_INS_XORCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_XORCCrr, SPARC_INS_XORCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_XORXri, SPARC_INS_XOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_XORXrr, SPARC_INS_XOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif + }, + { + SP_XORri, SPARC_INS_XOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + { + SP_XORrr, SPARC_INS_XOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, +}; + +static struct hint_map { + unsigned int id; + uint8_t hints; +} insn_hints[] = { + { SP_BPGEZapn, SPARC_HINT_A | SPARC_HINT_PN }, + { SP_BPGEZapt, SPARC_HINT_A | SPARC_HINT_PT }, + { SP_BPGEZnapn, SPARC_HINT_PN }, + { SP_BPGZapn, SPARC_HINT_A | SPARC_HINT_PN }, + { SP_BPGZapt, SPARC_HINT_A | SPARC_HINT_PT }, + { SP_BPGZnapn, SPARC_HINT_PN }, + { SP_BPLEZapn, SPARC_HINT_A | SPARC_HINT_PN }, + { SP_BPLEZapt, SPARC_HINT_A | SPARC_HINT_PT }, + { SP_BPLEZnapn, SPARC_HINT_PN }, + { SP_BPLZapn, SPARC_HINT_A | SPARC_HINT_PN }, + { SP_BPLZapt, SPARC_HINT_A | SPARC_HINT_PT }, + { SP_BPLZnapn, SPARC_HINT_PN }, + { SP_BPNZapn, SPARC_HINT_A | SPARC_HINT_PN }, + { SP_BPNZapt, SPARC_HINT_A | SPARC_HINT_PT }, + { SP_BPNZnapn, SPARC_HINT_PN }, + { SP_BPZapn, SPARC_HINT_A | SPARC_HINT_PN }, + { SP_BPZapt, SPARC_HINT_A | SPARC_HINT_PT }, + { SP_BPZnapn, SPARC_HINT_PN }, +}; + +// given internal insn id, return public instruction info +void Sparc_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) +{ + unsigned short i; + + i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); + if (i != 0) { + insn->id = insns[i].mapid; + + if (h->detail) { +#ifndef CAPSTONE_DIET + cs_struct handle; + handle.detail = h->detail; + + memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); + insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); + + memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); + insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); + + memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); + insn->detail->groups_count = (uint8_t)count_positive(insns[i].groups); + + if (insns[i].branch || insns[i].indirect_branch) { + // this insn also belongs to JUMP group. add JUMP group + insn->detail->groups[insn->detail->groups_count] = SPARC_GRP_JUMP; + insn->detail->groups_count++; + } +#endif + // hint code + for (i = 0; i < ARR_SIZE(insn_hints); i++) { + if (id == insn_hints[i].id) { + insn->detail->sparc.hint = insn_hints[i].hints; + break; + } + } + } + } +} + +#ifndef CAPSTONE_DIET +static name_map insn_name_maps[] = { + { SPARC_INS_INVALID, NULL }, + + { SPARC_INS_ADDCC, "addcc" }, + { SPARC_INS_ADDX, "addx" }, + { SPARC_INS_ADDXCC, "addxcc" }, + { SPARC_INS_ADDXC, "addxc" }, + { SPARC_INS_ADDXCCC, "addxccc" }, + { SPARC_INS_ADD, "add" }, + { SPARC_INS_ALIGNADDR, "alignaddr" }, + { SPARC_INS_ALIGNADDRL, "alignaddrl" }, + { SPARC_INS_ANDCC, "andcc" }, + { SPARC_INS_ANDNCC, "andncc" }, + { SPARC_INS_ANDN, "andn" }, + { SPARC_INS_AND, "and" }, + { SPARC_INS_ARRAY16, "array16" }, + { SPARC_INS_ARRAY32, "array32" }, + { SPARC_INS_ARRAY8, "array8" }, + { SPARC_INS_BA, "ba" }, + { SPARC_INS_B, "b" }, + { SPARC_INS_JMP, "jmp" }, + { SPARC_INS_BMASK, "bmask" }, + { SPARC_INS_FB, "fb" }, + { SPARC_INS_BRGEZ, "brgez" }, + { SPARC_INS_BRGZ, "brgz" }, + { SPARC_INS_BRLEZ, "brlez" }, + { SPARC_INS_BRLZ, "brlz" }, + { SPARC_INS_BRNZ, "brnz" }, + { SPARC_INS_BRZ, "brz" }, + { SPARC_INS_BSHUFFLE, "bshuffle" }, + { SPARC_INS_CALL, "call" }, + { SPARC_INS_CASX, "casx" }, + { SPARC_INS_CAS, "cas" }, + { SPARC_INS_CMASK16, "cmask16" }, + { SPARC_INS_CMASK32, "cmask32" }, + { SPARC_INS_CMASK8, "cmask8" }, + { SPARC_INS_CMP, "cmp" }, + { SPARC_INS_EDGE16, "edge16" }, + { SPARC_INS_EDGE16L, "edge16l" }, + { SPARC_INS_EDGE16LN, "edge16ln" }, + { SPARC_INS_EDGE16N, "edge16n" }, + { SPARC_INS_EDGE32, "edge32" }, + { SPARC_INS_EDGE32L, "edge32l" }, + { SPARC_INS_EDGE32LN, "edge32ln" }, + { SPARC_INS_EDGE32N, "edge32n" }, + { SPARC_INS_EDGE8, "edge8" }, + { SPARC_INS_EDGE8L, "edge8l" }, + { SPARC_INS_EDGE8LN, "edge8ln" }, + { SPARC_INS_EDGE8N, "edge8n" }, + { SPARC_INS_FABSD, "fabsd" }, + { SPARC_INS_FABSQ, "fabsq" }, + { SPARC_INS_FABSS, "fabss" }, + { SPARC_INS_FADDD, "faddd" }, + { SPARC_INS_FADDQ, "faddq" }, + { SPARC_INS_FADDS, "fadds" }, + { SPARC_INS_FALIGNDATA, "faligndata" }, + { SPARC_INS_FAND, "fand" }, + { SPARC_INS_FANDNOT1, "fandnot1" }, + { SPARC_INS_FANDNOT1S, "fandnot1s" }, + { SPARC_INS_FANDNOT2, "fandnot2" }, + { SPARC_INS_FANDNOT2S, "fandnot2s" }, + { SPARC_INS_FANDS, "fands" }, + { SPARC_INS_FCHKSM16, "fchksm16" }, + { SPARC_INS_FCMPD, "fcmpd" }, + { SPARC_INS_FCMPEQ16, "fcmpeq16" }, + { SPARC_INS_FCMPEQ32, "fcmpeq32" }, + { SPARC_INS_FCMPGT16, "fcmpgt16" }, + { SPARC_INS_FCMPGT32, "fcmpgt32" }, + { SPARC_INS_FCMPLE16, "fcmple16" }, + { SPARC_INS_FCMPLE32, "fcmple32" }, + { SPARC_INS_FCMPNE16, "fcmpne16" }, + { SPARC_INS_FCMPNE32, "fcmpne32" }, + { SPARC_INS_FCMPQ, "fcmpq" }, + { SPARC_INS_FCMPS, "fcmps" }, + { SPARC_INS_FDIVD, "fdivd" }, + { SPARC_INS_FDIVQ, "fdivq" }, + { SPARC_INS_FDIVS, "fdivs" }, + { SPARC_INS_FDMULQ, "fdmulq" }, + { SPARC_INS_FDTOI, "fdtoi" }, + { SPARC_INS_FDTOQ, "fdtoq" }, + { SPARC_INS_FDTOS, "fdtos" }, + { SPARC_INS_FDTOX, "fdtox" }, + { SPARC_INS_FEXPAND, "fexpand" }, + { SPARC_INS_FHADDD, "fhaddd" }, + { SPARC_INS_FHADDS, "fhadds" }, + { SPARC_INS_FHSUBD, "fhsubd" }, + { SPARC_INS_FHSUBS, "fhsubs" }, + { SPARC_INS_FITOD, "fitod" }, + { SPARC_INS_FITOQ, "fitoq" }, + { SPARC_INS_FITOS, "fitos" }, + { SPARC_INS_FLCMPD, "flcmpd" }, + { SPARC_INS_FLCMPS, "flcmps" }, + { SPARC_INS_FLUSHW, "flushw" }, + { SPARC_INS_FMEAN16, "fmean16" }, + { SPARC_INS_FMOVD, "fmovd" }, + { SPARC_INS_FMOVQ, "fmovq" }, + { SPARC_INS_FMOVRDGEZ, "fmovrdgez" }, + { SPARC_INS_FMOVRQGEZ, "fmovrqgez" }, + { SPARC_INS_FMOVRSGEZ, "fmovrsgez" }, + { SPARC_INS_FMOVRDGZ, "fmovrdgz" }, + { SPARC_INS_FMOVRQGZ, "fmovrqgz" }, + { SPARC_INS_FMOVRSGZ, "fmovrsgz" }, + { SPARC_INS_FMOVRDLEZ, "fmovrdlez" }, + { SPARC_INS_FMOVRQLEZ, "fmovrqlez" }, + { SPARC_INS_FMOVRSLEZ, "fmovrslez" }, + { SPARC_INS_FMOVRDLZ, "fmovrdlz" }, + { SPARC_INS_FMOVRQLZ, "fmovrqlz" }, + { SPARC_INS_FMOVRSLZ, "fmovrslz" }, + { SPARC_INS_FMOVRDNZ, "fmovrdnz" }, + { SPARC_INS_FMOVRQNZ, "fmovrqnz" }, + { SPARC_INS_FMOVRSNZ, "fmovrsnz" }, + { SPARC_INS_FMOVRDZ, "fmovrdz" }, + { SPARC_INS_FMOVRQZ, "fmovrqz" }, + { SPARC_INS_FMOVRSZ, "fmovrsz" }, + { SPARC_INS_FMOVS, "fmovs" }, + { SPARC_INS_FMUL8SUX16, "fmul8sux16" }, + { SPARC_INS_FMUL8ULX16, "fmul8ulx16" }, + { SPARC_INS_FMUL8X16, "fmul8x16" }, + { SPARC_INS_FMUL8X16AL, "fmul8x16al" }, + { SPARC_INS_FMUL8X16AU, "fmul8x16au" }, + { SPARC_INS_FMULD, "fmuld" }, + { SPARC_INS_FMULD8SUX16, "fmuld8sux16" }, + { SPARC_INS_FMULD8ULX16, "fmuld8ulx16" }, + { SPARC_INS_FMULQ, "fmulq" }, + { SPARC_INS_FMULS, "fmuls" }, + { SPARC_INS_FNADDD, "fnaddd" }, + { SPARC_INS_FNADDS, "fnadds" }, + { SPARC_INS_FNAND, "fnand" }, + { SPARC_INS_FNANDS, "fnands" }, + { SPARC_INS_FNEGD, "fnegd" }, + { SPARC_INS_FNEGQ, "fnegq" }, + { SPARC_INS_FNEGS, "fnegs" }, + { SPARC_INS_FNHADDD, "fnhaddd" }, + { SPARC_INS_FNHADDS, "fnhadds" }, + { SPARC_INS_FNOR, "fnor" }, + { SPARC_INS_FNORS, "fnors" }, + { SPARC_INS_FNOT1, "fnot1" }, + { SPARC_INS_FNOT1S, "fnot1s" }, + { SPARC_INS_FNOT2, "fnot2" }, + { SPARC_INS_FNOT2S, "fnot2s" }, + { SPARC_INS_FONE, "fone" }, + { SPARC_INS_FONES, "fones" }, + { SPARC_INS_FOR, "for" }, + { SPARC_INS_FORNOT1, "fornot1" }, + { SPARC_INS_FORNOT1S, "fornot1s" }, + { SPARC_INS_FORNOT2, "fornot2" }, + { SPARC_INS_FORNOT2S, "fornot2s" }, + { SPARC_INS_FORS, "fors" }, + { SPARC_INS_FPACK16, "fpack16" }, + { SPARC_INS_FPACK32, "fpack32" }, + { SPARC_INS_FPACKFIX, "fpackfix" }, + { SPARC_INS_FPADD16, "fpadd16" }, + { SPARC_INS_FPADD16S, "fpadd16s" }, + { SPARC_INS_FPADD32, "fpadd32" }, + { SPARC_INS_FPADD32S, "fpadd32s" }, + { SPARC_INS_FPADD64, "fpadd64" }, + { SPARC_INS_FPMERGE, "fpmerge" }, + { SPARC_INS_FPSUB16, "fpsub16" }, + { SPARC_INS_FPSUB16S, "fpsub16s" }, + { SPARC_INS_FPSUB32, "fpsub32" }, + { SPARC_INS_FPSUB32S, "fpsub32s" }, + { SPARC_INS_FQTOD, "fqtod" }, + { SPARC_INS_FQTOI, "fqtoi" }, + { SPARC_INS_FQTOS, "fqtos" }, + { SPARC_INS_FQTOX, "fqtox" }, + { SPARC_INS_FSLAS16, "fslas16" }, + { SPARC_INS_FSLAS32, "fslas32" }, + { SPARC_INS_FSLL16, "fsll16" }, + { SPARC_INS_FSLL32, "fsll32" }, + { SPARC_INS_FSMULD, "fsmuld" }, + { SPARC_INS_FSQRTD, "fsqrtd" }, + { SPARC_INS_FSQRTQ, "fsqrtq" }, + { SPARC_INS_FSQRTS, "fsqrts" }, + { SPARC_INS_FSRA16, "fsra16" }, + { SPARC_INS_FSRA32, "fsra32" }, + { SPARC_INS_FSRC1, "fsrc1" }, + { SPARC_INS_FSRC1S, "fsrc1s" }, + { SPARC_INS_FSRC2, "fsrc2" }, + { SPARC_INS_FSRC2S, "fsrc2s" }, + { SPARC_INS_FSRL16, "fsrl16" }, + { SPARC_INS_FSRL32, "fsrl32" }, + { SPARC_INS_FSTOD, "fstod" }, + { SPARC_INS_FSTOI, "fstoi" }, + { SPARC_INS_FSTOQ, "fstoq" }, + { SPARC_INS_FSTOX, "fstox" }, + { SPARC_INS_FSUBD, "fsubd" }, + { SPARC_INS_FSUBQ, "fsubq" }, + { SPARC_INS_FSUBS, "fsubs" }, + { SPARC_INS_FXNOR, "fxnor" }, + { SPARC_INS_FXNORS, "fxnors" }, + { SPARC_INS_FXOR, "fxor" }, + { SPARC_INS_FXORS, "fxors" }, + { SPARC_INS_FXTOD, "fxtod" }, + { SPARC_INS_FXTOQ, "fxtoq" }, + { SPARC_INS_FXTOS, "fxtos" }, + { SPARC_INS_FZERO, "fzero" }, + { SPARC_INS_FZEROS, "fzeros" }, + { SPARC_INS_JMPL, "jmpl" }, + { SPARC_INS_LDD, "ldd" }, + { SPARC_INS_LD, "ld" }, + { SPARC_INS_LDQ, "ldq" }, + { SPARC_INS_LDSB, "ldsb" }, + { SPARC_INS_LDSH, "ldsh" }, + { SPARC_INS_LDSW, "ldsw" }, + { SPARC_INS_LDUB, "ldub" }, + { SPARC_INS_LDUH, "lduh" }, + { SPARC_INS_LDX, "ldx" }, + { SPARC_INS_LZCNT, "lzcnt" }, + { SPARC_INS_MEMBAR, "membar" }, + { SPARC_INS_MOVDTOX, "movdtox" }, + { SPARC_INS_MOV, "mov" }, + { SPARC_INS_MOVRGEZ, "movrgez" }, + { SPARC_INS_MOVRGZ, "movrgz" }, + { SPARC_INS_MOVRLEZ, "movrlez" }, + { SPARC_INS_MOVRLZ, "movrlz" }, + { SPARC_INS_MOVRNZ, "movrnz" }, + { SPARC_INS_MOVRZ, "movrz" }, + { SPARC_INS_MOVSTOSW, "movstosw" }, + { SPARC_INS_MOVSTOUW, "movstouw" }, + { SPARC_INS_MULX, "mulx" }, + { SPARC_INS_NOP, "nop" }, + { SPARC_INS_ORCC, "orcc" }, + { SPARC_INS_ORNCC, "orncc" }, + { SPARC_INS_ORN, "orn" }, + { SPARC_INS_OR, "or" }, + { SPARC_INS_PDIST, "pdist" }, + { SPARC_INS_PDISTN, "pdistn" }, + { SPARC_INS_POPC, "popc" }, + { SPARC_INS_RD, "rd" }, + { SPARC_INS_RESTORE, "restore" }, + { SPARC_INS_RETT, "rett" }, + { SPARC_INS_SAVE, "save" }, + { SPARC_INS_SDIVCC, "sdivcc" }, + { SPARC_INS_SDIVX, "sdivx" }, + { SPARC_INS_SDIV, "sdiv" }, + { SPARC_INS_SETHI, "sethi" }, + { SPARC_INS_SHUTDOWN, "shutdown" }, + { SPARC_INS_SIAM, "siam" }, + { SPARC_INS_SLLX, "sllx" }, + { SPARC_INS_SLL, "sll" }, + { SPARC_INS_SMULCC, "smulcc" }, + { SPARC_INS_SMUL, "smul" }, + { SPARC_INS_SRAX, "srax" }, + { SPARC_INS_SRA, "sra" }, + { SPARC_INS_SRLX, "srlx" }, + { SPARC_INS_SRL, "srl" }, + { SPARC_INS_STBAR, "stbar" }, + { SPARC_INS_STB, "stb" }, + { SPARC_INS_STD, "std" }, + { SPARC_INS_ST, "st" }, + { SPARC_INS_STH, "sth" }, + { SPARC_INS_STQ, "stq" }, + { SPARC_INS_STX, "stx" }, + { SPARC_INS_SUBCC, "subcc" }, + { SPARC_INS_SUBX, "subx" }, + { SPARC_INS_SUBXCC, "subxcc" }, + { SPARC_INS_SUB, "sub" }, + { SPARC_INS_SWAP, "swap" }, + { SPARC_INS_TA, "ta" }, + { SPARC_INS_TADDCCTV, "taddcctv" }, + { SPARC_INS_TADDCC, "taddcc" }, + { SPARC_INS_T, "t" }, + { SPARC_INS_TSUBCCTV, "tsubcctv" }, + { SPARC_INS_TSUBCC, "tsubcc" }, + { SPARC_INS_UDIVCC, "udivcc" }, + { SPARC_INS_UDIVX, "udivx" }, + { SPARC_INS_UDIV, "udiv" }, + { SPARC_INS_UMULCC, "umulcc" }, + { SPARC_INS_UMULXHI, "umulxhi" }, + { SPARC_INS_UMUL, "umul" }, + { SPARC_INS_UNIMP, "unimp" }, + { SPARC_INS_FCMPED, "fcmped" }, + { SPARC_INS_FCMPEQ, "fcmpeq" }, + { SPARC_INS_FCMPES, "fcmpes" }, + { SPARC_INS_WR, "wr" }, + { SPARC_INS_XMULX, "xmulx" }, + { SPARC_INS_XMULXHI, "xmulxhi" }, + { SPARC_INS_XNORCC, "xnorcc" }, + { SPARC_INS_XNOR, "xnor" }, + { SPARC_INS_XORCC, "xorcc" }, + { SPARC_INS_XOR, "xor" }, +}; + +// special alias insn +static name_map alias_insn_names[] = { + { 0, NULL } +}; +#endif + +const char *Sparc_insn_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + if (id >= SPARC_INS_MAX) + return NULL; + + // handle special alias first + int i; + for (i = 0; i < ARR_SIZE(alias_insn_names); i++) { + if (alias_insn_names[i].id == id) + return alias_insn_names[i].name; + } + + return insn_name_maps[id].name; +#else + return NULL; +#endif +} + +// map internal raw register to 'public' register +sparc_reg Sparc_map_register(unsigned int r) +{ + static unsigned int map[] = { 0, + SPARC_REG_ICC, SPARC_REG_Y, SPARC_REG_F0, SPARC_REG_F2, SPARC_REG_F4, + SPARC_REG_F6, SPARC_REG_F8, SPARC_REG_F10, SPARC_REG_F12, SPARC_REG_F14, + SPARC_REG_F16, SPARC_REG_F18, SPARC_REG_F20, SPARC_REG_F22, SPARC_REG_F24, + SPARC_REG_F26, SPARC_REG_F28, SPARC_REG_F30, SPARC_REG_F32, SPARC_REG_F34, + SPARC_REG_F36, SPARC_REG_F38, SPARC_REG_F40, SPARC_REG_F42, SPARC_REG_F44, + SPARC_REG_F46, SPARC_REG_F48, SPARC_REG_F50, SPARC_REG_F52, SPARC_REG_F54, + SPARC_REG_F56, SPARC_REG_F58, SPARC_REG_F60, SPARC_REG_F62, SPARC_REG_F0, + SPARC_REG_F1, SPARC_REG_F2, SPARC_REG_F3, SPARC_REG_F4, SPARC_REG_F5, + SPARC_REG_F6, SPARC_REG_F7, SPARC_REG_F8, SPARC_REG_F9, SPARC_REG_F10, + SPARC_REG_F11, SPARC_REG_F12, SPARC_REG_F13, SPARC_REG_F14, SPARC_REG_F15, + SPARC_REG_F16, SPARC_REG_F17, SPARC_REG_F18, SPARC_REG_F19, SPARC_REG_F20, + SPARC_REG_F21, SPARC_REG_F22, SPARC_REG_F23, SPARC_REG_F24, SPARC_REG_F25, + SPARC_REG_F26, SPARC_REG_F27, SPARC_REG_F28, SPARC_REG_F29, SPARC_REG_F30, + SPARC_REG_F31, SPARC_REG_FCC0, SPARC_REG_FCC1, SPARC_REG_FCC2, SPARC_REG_FCC3, + SPARC_REG_G0, SPARC_REG_G1, SPARC_REG_G2, SPARC_REG_G3, SPARC_REG_G4, + SPARC_REG_G5, SPARC_REG_G6, SPARC_REG_G7, SPARC_REG_I0, SPARC_REG_I1, + SPARC_REG_I2, SPARC_REG_I3, SPARC_REG_I4, SPARC_REG_I5, SPARC_REG_FP, + SPARC_REG_I7, SPARC_REG_L0, SPARC_REG_L1, SPARC_REG_L2, SPARC_REG_L3, + SPARC_REG_L4, SPARC_REG_L5, SPARC_REG_L6, SPARC_REG_L7, SPARC_REG_O0, + SPARC_REG_O1, SPARC_REG_O2, SPARC_REG_O3, SPARC_REG_O4, SPARC_REG_O5, + SPARC_REG_SP, SPARC_REG_O7, SPARC_REG_F0, SPARC_REG_F4, SPARC_REG_F8, + SPARC_REG_F12, SPARC_REG_F16, SPARC_REG_F20, SPARC_REG_F24, SPARC_REG_F28, + SPARC_REG_F32, SPARC_REG_F36, SPARC_REG_F40, SPARC_REG_F44, SPARC_REG_F48, + SPARC_REG_F52, SPARC_REG_F56, SPARC_REG_F60, + }; + + if (r < ARR_SIZE(map)) + return map[r]; + + // cannot find this register + return 0; +} diff --git a/arch/Sparc/SparcMapping.h b/arch/Sparc/SparcMapping.h new file mode 100644 index 0000000000..3de9335cfc --- /dev/null +++ b/arch/Sparc/SparcMapping.h @@ -0,0 +1,22 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2014 */ + +#ifndef CS_SPARC_MAP_H +#define CS_SPARC_MAP_H + +#include "../../include/capstone.h" +#include "../../include/sparc.h" + +// return name of regiser in friendly string +const char *Sparc_reg_name(csh handle, unsigned int reg); + +// given internal insn id, return public instruction info +void Sparc_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); + +const char *Sparc_insn_name(csh handle, unsigned int id); + +// map internal raw register to 'public' register +sparc_reg Sparc_map_register(unsigned int r); + +#endif + diff --git a/arch/Sparc/SparcModule.c b/arch/Sparc/SparcModule.c new file mode 100644 index 0000000000..e9cae3c08a --- /dev/null +++ b/arch/Sparc/SparcModule.c @@ -0,0 +1,54 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2014 */ + +#include "../../utils.h" +#include "../../MCRegisterInfo.h" +#include "SparcDisassembler.h" +#include "SparcInstPrinter.h" +#include "SparcMapping.h" + +static cs_err init(cs_struct *ud) +{ + MCRegisterInfo *mri; + + // verify if requested mode is valid + if (ud->mode & ~(CS_MODE_BIG_ENDIAN | CS_MODE_V9)) + return CS_ERR_MODE; + + mri = cs_mem_malloc(sizeof(*mri)); + + Sparc_init(mri); + ud->printer = Sparc_printInst; + ud->printer_info = mri; + ud->getinsn_info = mri; + ud->disasm = Sparc_getInstruction; + ud->post_printer = Sparc_post_printer; + + ud->reg_name = Sparc_reg_name; + ud->insn_id = Sparc_get_insn_id; + ud->insn_name = Sparc_insn_name; + + return CS_ERR_OK; +} + +static cs_err option(cs_struct *handle, cs_opt_type type, size_t value) +{ + if (type == CS_OPT_SYNTAX) + handle->syntax = value; + + return CS_ERR_OK; +} + +static void destroy(cs_struct *handle) +{ +} + +void Sparc_enable(void) +{ + arch_init[CS_ARCH_SPARC] = init; + arch_option[CS_ARCH_SPARC] = option; + arch_destroy[CS_ARCH_SPARC] = destroy; + + // support this arch + all_arch |= (1 << CS_ARCH_SPARC); +} diff --git a/config.mk b/config.mk index 437c148b77..e99a3370c3 100644 --- a/config.mk +++ b/config.mk @@ -18,6 +18,9 @@ CAPSTONE_ARCHS += mips # Comment out the line below if you don't want to support PowerPC CAPSTONE_ARCHS += powerpc +# Comment out the line below if you don't want to support Sparc +CAPSTONE_ARCHS += sparc + # Comment out the line below if you don't want to support Intel (16/32/64-bit) CAPSTONE_ARCHS += x86 diff --git a/cs.c b/cs.c index bdacee8570..6eac9330e9 100644 --- a/cs.c +++ b/cs.c @@ -26,6 +26,7 @@ extern void AArch64_enable(void); extern void Mips_enable(void); extern void X86_enable(void); extern void PPC_enable(void); +extern void Sparc_enable(void); static void archs_enable(void) { @@ -43,12 +44,15 @@ static void archs_enable(void) #ifdef CAPSTONE_HAS_MIPS Mips_enable(); #endif -#ifdef CAPSTONE_HAS_X86 - X86_enable(); -#endif #ifdef CAPSTONE_HAS_POWERPC PPC_enable(); #endif +#ifdef CAPSTONE_HAS_SPARC + Sparc_enable(); +#endif +#ifdef CAPSTONE_HAS_X86 + X86_enable(); +#endif initialized = true; } @@ -88,7 +92,7 @@ bool cs_support(int query) if (query == CS_ARCH_ALL) return all_arch == ((1 << CS_ARCH_ARM) | (1 << CS_ARCH_ARM64) | (1 << CS_ARCH_MIPS) | (1 << CS_ARCH_X86) | - (1 << CS_ARCH_PPC)); + (1 << CS_ARCH_PPC) | (1 << CS_ARCH_SPARC)); if ((unsigned int)query < CS_ARCH_MAX) return all_arch & (1 << query); @@ -576,6 +580,11 @@ int cs_op_count(csh ud, cs_insn *insn, unsigned int op_type) if (insn->detail->ppc.operands[i].type == (ppc_op_type)op_type) count++; break; + case CS_ARCH_SPARC: + for (i = 0; i < insn->detail->sparc.op_count; i++) + if (insn->detail->sparc.operands[i].type == (sparc_op_type)op_type) + count++; + break; } return count; @@ -641,6 +650,14 @@ int cs_op_index(csh ud, cs_insn *insn, unsigned int op_type, return i; } break; + case CS_ARCH_SPARC: + for (i = 0; i < insn->detail->sparc.op_count; i++) { + if (insn->detail->sparc.operands[i].type == (sparc_op_type)op_type) + count++; + if (count == post) + return i; + } + break; } return -1; diff --git a/include/capstone.h b/include/capstone.h index c926e4fb6b..206c980f60 100644 --- a/include/capstone.h +++ b/include/capstone.h @@ -39,6 +39,7 @@ typedef enum cs_arch { CS_ARCH_MIPS, // Mips architecture CS_ARCH_X86, // X86 architecture (including x86 & x86-64) CS_ARCH_PPC, // PowerPC architecture + CS_ARCH_SPARC, // Sparc architecture CS_ARCH_MAX, CS_ARCH_ALL = 0xFFFF, } cs_arch; @@ -56,6 +57,8 @@ typedef enum cs_mode { CS_MODE_MICRO = 1 << 4, // MicroMips mode (MIPS architecture) CS_MODE_N64 = 1 << 5, // Nintendo-64 mode (MIPS architecture) + CS_MODE_V9 = 1 << 4, // SparcV9 mode (Sparc architecture) + CS_MODE_BIG_ENDIAN = 1 << 31 // big endian mode } cs_mode; @@ -100,6 +103,7 @@ typedef enum cs_opt_value { #include "mips.h" #include "x86.h" #include "ppc.h" +#include "sparc.h" // NOTE: All information in cs_detail is only available when CS_OPT_DETAIL = CS_OPT_ON typedef struct cs_detail { @@ -119,6 +123,7 @@ typedef struct cs_detail { cs_arm arm; // ARM architecture (including Thumb/Thumb2) cs_mips mips; // MIPS architecture cs_ppc ppc; // PowerPC architecture + cs_sparc sparc; // Sparc architecture }; } cs_detail; diff --git a/tests/Makefile b/tests/Makefile index 5b6950f5fe..49d79db30c 100644 --- a/tests/Makefile +++ b/tests/Makefile @@ -1,5 +1,5 @@ # Capstone Disassembler Engine -# By Nguyen Anh Quynh , 2013> +# By Nguyen Anh Quynh , 2013-2014 include ../config.mk @@ -51,6 +51,9 @@ endif ifneq (,$(findstring powerpc,$(CAPSTONE_ARCHS))) SOURCES += test_ppc.c endif +ifneq (,$(findstring sparc,$(CAPSTONE_ARCHS))) +SOURCES += test_sparc.c +endif ifneq (,$(findstring x86,$(CAPSTONE_ARCHS))) SOURCES += test_x86.c endif diff --git a/tests/test.c b/tests/test.c index 9f32e08827..c9cfe0744a 100644 --- a/tests/test.c +++ b/tests/test.c @@ -48,6 +48,8 @@ static void test() #define ARM64_CODE "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9" #define PPC_CODE "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21" +#define SPARC_CODE "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03" + struct platform platforms[] = { { .arch = CS_ARCH_X86, @@ -144,6 +146,13 @@ static void test() .opt_value = CS_OPT_SYNTAX_NOREGNAME, .comment = "PPC-64, print register with number only" }, + { + .arch = CS_ARCH_SPARC, + .mode = CS_MODE_BIG_ENDIAN, + .code = (unsigned char*)SPARC_CODE, + .size = sizeof(SPARC_CODE) - 1, + .comment = "Sparc" + }, }; csh handle; diff --git a/tests/test_detail.c b/tests/test_detail.c index a320ba1afa..ebe0835f85 100644 --- a/tests/test_detail.c +++ b/tests/test_detail.c @@ -53,6 +53,8 @@ static void test() //#define THUMB_CODE "\x0a\xbf" // itet eq //#define X86_CODE32 "\x77\x04" // ja +6 #define PPC_CODE "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21" +#define SPARC_CODE "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03" + struct platform platforms[] = { { @@ -141,6 +143,13 @@ static void test() .size = sizeof(PPC_CODE) - 1, .comment = "PPC-64" }, + { + .arch = CS_ARCH_SPARC, + .mode = CS_MODE_BIG_ENDIAN, + .code = (unsigned char*)SPARC_CODE, + .size = sizeof(SPARC_CODE) - 1, + .comment = "Sparc" + }, }; csh handle; diff --git a/tests/test_sparc.c b/tests/test_sparc.c new file mode 100644 index 0000000000..41c2bf8f66 --- /dev/null +++ b/tests/test_sparc.c @@ -0,0 +1,135 @@ +/* Capstone Disassembler Engine */ +/* By Nguyen Anh Quynh , 2013-2014 */ + +#include +#include + +#include + +struct platform { + cs_arch arch; + cs_mode mode; + unsigned char *code; + size_t size; + char *comment; +}; + +static csh handle; + +static void print_string_hex(char *comment, unsigned char *str, int len) +{ + unsigned char *c; + + printf("%s", comment); + for (c = str; c < str + len; c++) { + printf("0x%02x ", *c & 0xff); + } + + printf("\n"); +} + +static void print_insn_detail(cs_insn *ins) +{ + cs_sparc *sparc = &(ins->detail->sparc); + + if (sparc->op_count) + printf("\top_count: %u\n", sparc->op_count); + + int i; + for (i = 0; i < sparc->op_count; i++) { + cs_sparc_op *op = &(sparc->operands[i]); + switch((int)op->type) { + default: + break; + case SPARC_OP_REG: + printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); + break; + case SPARC_OP_IMM: + printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm); + break; + case SPARC_OP_MEM: + printf("\t\toperands[%u].type: MEM\n", i); + if (op->mem.base != X86_REG_INVALID) + printf("\t\t\toperands[%u].mem.base: REG = %s\n", + i, cs_reg_name(handle, op->mem.base)); + if (op->mem.index != X86_REG_INVALID) + printf("\t\t\toperands[%u].mem.index: REG = %s\n", + i, cs_reg_name(handle, op->mem.index)); + if (op->mem.disp != 0) + printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); + + break; + } + } + + if (sparc->cc != 0) + printf("\tCode condition: %u\n", sparc->cc); + + if (sparc->hint != 0) + printf("\tHint code: %u\n", sparc->hint); + + printf("\n"); +} + +static void test() +{ +#define SPARC_CODE "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03" + + struct platform platforms[] = { + { + .arch = CS_ARCH_SPARC, + .mode = CS_MODE_BIG_ENDIAN, + .code = (unsigned char*)SPARC_CODE, + .size = sizeof(SPARC_CODE) - 1, + .comment = "Sparc", + } + }; + + uint64_t address = 0x1000; + cs_insn *insn; + int i; + + for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { + cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle); + if (err) { + printf("Failed on cs_open() with error returned: %u\n", err); + continue; + } + + cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); + + size_t count = cs_disasm_ex(handle, platforms[i].code, platforms[i].size, address, 0, &insn); + if (count) { + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code:", platforms[i].code, platforms[i].size); + printf("Disasm:\n"); + + size_t j; + for (j = 0; j < count; j++) { + printf("0x%"PRIx64":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str); + print_insn_detail(&insn[j]); + } + printf("0x%"PRIx64":\n", insn[j-1].address + insn[j-1].size); + + // free memory allocated by cs_disasm_ex() + cs_free(insn, count); + } else { + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code:", platforms[i].code, platforms[i].size); + printf("ERROR: Failed to disasm given code!\n"); + } + + printf("\n"); + + cs_close(&handle); + } +} + +int main() +{ + test(); + + return 0; +}