From 10b6d2f5bc50f965d6aee213415b60f1f9af58e5 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sun, 28 Jan 2024 16:38:38 -0800 Subject: [PATCH] Force AXIS RAM switch output FIFO into distributed RAM Signed-off-by: Alex Forencich --- rtl/axis_ram_switch.v | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/rtl/axis_ram_switch.v b/rtl/axis_ram_switch.v index 6e08a921a..56dc66a51 100644 --- a/rtl/axis_ram_switch.v +++ b/rtl/axis_ram_switch.v @@ -912,11 +912,17 @@ generate assign port_cmd_status_ready[m] = int_cmd_status_ready[m*M_COUNT+n]; end + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [DATA_WIDTH-1:0] out_fifo_tdata[31:0]; + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [KEEP_WIDTH-1:0] out_fifo_tkeep[31:0]; + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg out_fifo_tlast[31:0]; + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [M_ID_WIDTH-1:0] out_fifo_tid[31:0]; + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [M_DEST_WIDTH-1:0] out_fifo_tdest[31:0]; + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [USER_WIDTH-1:0] out_fifo_tuser[31:0]; reg [5:0] out_fifo_data_wr_ptr_reg = 0;