diff --git a/example/VCU108/fpga_10g/rtl/fpga_core.v b/example/VCU108/fpga_10g/rtl/fpga_core.v
index 740b86fc1..aab66c1ad 100644
--- a/example/VCU108/fpga_10g/rtl/fpga_core.v
+++ b/example/VCU108/fpga_10g/rtl/fpga_core.v
@@ -604,8 +604,8 @@ axis_switch #(
     .M_CONNECT({3{3'b111}}),
     .S_REG_TYPE(0),
     .M_REG_TYPE(2),
-    .ARB_TYPE("PRIORITY"),
-    .LSB_PRIORITY("HIGH")
+    .ARB_TYPE_ROUND_ROBIN(0),
+    .ARB_LSB_HIGH_PRIORITY(1)
 )
 axis_switch_inst (
     .clk(clk),
diff --git a/example/VCU118/fpga_10g/rtl/fpga_core.v b/example/VCU118/fpga_10g/rtl/fpga_core.v
index 827fc7fbf..02a7e6794 100644
--- a/example/VCU118/fpga_10g/rtl/fpga_core.v
+++ b/example/VCU118/fpga_10g/rtl/fpga_core.v
@@ -645,8 +645,8 @@ axis_switch #(
     .M_CONNECT({3{3'b111}}),
     .S_REG_TYPE(0),
     .M_REG_TYPE(2),
-    .ARB_TYPE("PRIORITY"),
-    .LSB_PRIORITY("HIGH")
+    .ARB_TYPE_ROUND_ROBIN(0),
+    .ARB_LSB_HIGH_PRIORITY(1)
 )
 axis_switch_inst (
     .clk(clk),
diff --git a/example/VCU118/fpga_25g/rtl/fpga_core.v b/example/VCU118/fpga_25g/rtl/fpga_core.v
index f095b92ac..c6b57cbdf 100644
--- a/example/VCU118/fpga_25g/rtl/fpga_core.v
+++ b/example/VCU118/fpga_25g/rtl/fpga_core.v
@@ -645,8 +645,8 @@ axis_switch #(
     .M_CONNECT({3{3'b111}}),
     .S_REG_TYPE(0),
     .M_REG_TYPE(2),
-    .ARB_TYPE("PRIORITY"),
-    .LSB_PRIORITY("HIGH")
+    .ARB_TYPE_ROUND_ROBIN(0),
+    .ARB_LSB_HIGH_PRIORITY(1)
 )
 axis_switch_inst (
     .clk(clk),
diff --git a/rtl/eth_arb_mux.v b/rtl/eth_arb_mux.v
index 8aa662646..c4b0d0faf 100644
--- a/rtl/eth_arb_mux.v
+++ b/rtl/eth_arb_mux.v
@@ -41,10 +41,10 @@ module eth_arb_mux #
     parameter DEST_WIDTH = 8,
     parameter USER_ENABLE = 1,
     parameter USER_WIDTH = 1,
-    // arbitration type: "PRIORITY" or "ROUND_ROBIN"
-    parameter ARB_TYPE = "PRIORITY",
-    // LSB priority: "LOW", "HIGH"
-    parameter LSB_PRIORITY = "HIGH"
+    // select round robin arbitration
+    parameter ARB_TYPE_ROUND_ROBIN = 0,
+    // LSB priority selection
+    parameter ARB_LSB_HIGH_PRIORITY = 1
 )
 (
     input  wire                          clk,
@@ -135,9 +135,10 @@ wire [USER_WIDTH-1:0] current_s_tuser  = s_eth_payload_axis_tuser[grant_encoded*
 // arbiter instance
 arbiter #(
     .PORTS(S_COUNT),
-    .TYPE(ARB_TYPE),
-    .BLOCK("ACKNOWLEDGE"),
-    .LSB_PRIORITY(LSB_PRIORITY)
+    .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
+    .ARB_BLOCK(1),
+    .ARB_BLOCK_ACK(1),
+    .ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
 )
 arb_inst (
     .clk(clk),
diff --git a/rtl/ip_arb_mux.v b/rtl/ip_arb_mux.v
index ec88c5262..68cfbf3ae 100644
--- a/rtl/ip_arb_mux.v
+++ b/rtl/ip_arb_mux.v
@@ -41,10 +41,10 @@ module ip_arb_mux #
     parameter DEST_WIDTH = 8,
     parameter USER_ENABLE = 1,
     parameter USER_WIDTH = 1,
-    // arbitration type: "PRIORITY" or "ROUND_ROBIN"
-    parameter ARB_TYPE = "PRIORITY",
-    // LSB priority: "LOW", "HIGH"
-    parameter LSB_PRIORITY = "HIGH"
+    // select round robin arbitration
+    parameter ARB_TYPE_ROUND_ROBIN = 0,
+    // LSB priority selection
+    parameter ARB_LSB_HIGH_PRIORITY = 1
 )
 (
     input  wire                          clk,
@@ -187,9 +187,10 @@ wire [USER_WIDTH-1:0] current_s_tuser  = s_ip_payload_axis_tuser[grant_encoded*U
 // arbiter instance
 arbiter #(
     .PORTS(S_COUNT),
-    .TYPE(ARB_TYPE),
-    .BLOCK("ACKNOWLEDGE"),
-    .LSB_PRIORITY(LSB_PRIORITY)
+    .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
+    .ARB_BLOCK(1),
+    .ARB_BLOCK_ACK(1),
+    .ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
 )
 arb_inst (
     .clk(clk),
diff --git a/rtl/ip_complete.v b/rtl/ip_complete.v
index f16d697b3..a878b71a5 100644
--- a/rtl/ip_complete.v
+++ b/rtl/ip_complete.v
@@ -261,8 +261,8 @@ eth_arb_mux #(
     .DEST_ENABLE(0),
     .USER_ENABLE(1),
     .USER_WIDTH(1),
-    .ARB_TYPE("PRIORITY"),
-    .LSB_PRIORITY("HIGH")
+    .ARB_TYPE_ROUND_ROBIN(0),
+    .ARB_LSB_HIGH_PRIORITY(1)
 )
 eth_arb_mux_inst (
     .clk(clk),
diff --git a/rtl/ip_complete_64.v b/rtl/ip_complete_64.v
index 3dc4f03a4..6e0d4df84 100644
--- a/rtl/ip_complete_64.v
+++ b/rtl/ip_complete_64.v
@@ -271,8 +271,8 @@ eth_arb_mux #(
     .DEST_ENABLE(0),
     .USER_ENABLE(1),
     .USER_WIDTH(1),
-    .ARB_TYPE("PRIORITY"),
-    .LSB_PRIORITY("HIGH")
+    .ARB_TYPE_ROUND_ROBIN(0),
+    .ARB_LSB_HIGH_PRIORITY(1)
 )
 eth_arb_mux_inst (
     .clk(clk),
diff --git a/rtl/udp_arb_mux.v b/rtl/udp_arb_mux.v
index 9b285ee97..a76218cb2 100644
--- a/rtl/udp_arb_mux.v
+++ b/rtl/udp_arb_mux.v
@@ -41,10 +41,10 @@ module udp_arb_mux #
     parameter DEST_WIDTH = 8,
     parameter USER_ENABLE = 1,
     parameter USER_WIDTH = 1,
-    // arbitration type: "PRIORITY" or "ROUND_ROBIN"
-    parameter ARB_TYPE = "PRIORITY",
-    // LSB priority: "LOW", "HIGH"
-    parameter LSB_PRIORITY = "HIGH"
+    // select round robin arbitration
+    parameter ARB_TYPE_ROUND_ROBIN = 0,
+    // LSB priority selection
+    parameter ARB_LSB_HIGH_PRIORITY = 1
 )
 (
     input  wire                          clk,
@@ -203,9 +203,10 @@ wire [USER_WIDTH-1:0] current_s_tuser  = s_udp_payload_axis_tuser[grant_encoded*
 // arbiter instance
 arbiter #(
     .PORTS(S_COUNT),
-    .TYPE(ARB_TYPE),
-    .BLOCK("ACKNOWLEDGE"),
-    .LSB_PRIORITY(LSB_PRIORITY)
+    .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
+    .ARB_BLOCK(1),
+    .ARB_BLOCK_ACK(1),
+    .ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
 )
 arb_inst (
     .clk(clk),
diff --git a/rtl/udp_complete.v b/rtl/udp_complete.v
index 4432c9091..389c00fce 100644
--- a/rtl/udp_complete.v
+++ b/rtl/udp_complete.v
@@ -361,8 +361,8 @@ ip_arb_mux #(
     .DEST_ENABLE(0),
     .USER_ENABLE(1),
     .USER_WIDTH(1),
-    .ARB_TYPE("PRIORITY"),
-    .LSB_PRIORITY("HIGH")
+    .ARB_TYPE_ROUND_ROBIN(0),
+    .ARB_LSB_HIGH_PRIORITY(1)
 )
 ip_arb_mux_inst (
     .clk(clk),
diff --git a/rtl/udp_complete_64.v b/rtl/udp_complete_64.v
index 2ab69c91b..3a1d4d5a9 100644
--- a/rtl/udp_complete_64.v
+++ b/rtl/udp_complete_64.v
@@ -373,8 +373,8 @@ ip_arb_mux #(
     .DEST_ENABLE(0),
     .USER_ENABLE(1),
     .USER_WIDTH(1),
-    .ARB_TYPE("PRIORITY"),
-    .LSB_PRIORITY("HIGH")
+    .ARB_TYPE_ROUND_ROBIN(0),
+    .ARB_LSB_HIGH_PRIORITY(1)
 )
 ip_arb_mux_inst (
     .clk(clk),
diff --git a/tb/test_eth_arb_mux_4.py b/tb/test_eth_arb_mux_4.py
index f96e9b710..7b8cf79f7 100755
--- a/tb/test_eth_arb_mux_4.py
+++ b/tb/test_eth_arb_mux_4.py
@@ -55,8 +55,8 @@ def bench():
     DEST_WIDTH = 8
     USER_ENABLE = 1
     USER_WIDTH = 1
-    ARB_TYPE = "PRIORITY"
-    LSB_PRIORITY = "HIGH"
+    ARB_TYPE_ROUND_ROBIN = 0
+    ARB_LSB_HIGH_PRIORITY = 1
 
     # Inputs
     clk = Signal(bool(0))
diff --git a/tb/test_eth_arb_mux_4.v b/tb/test_eth_arb_mux_4.v
index 6c98fb762..84102682d 100644
--- a/tb/test_eth_arb_mux_4.v
+++ b/tb/test_eth_arb_mux_4.v
@@ -42,8 +42,8 @@ parameter DEST_ENABLE = 1;
 parameter DEST_WIDTH = 8;
 parameter USER_ENABLE = 1;
 parameter USER_WIDTH = 1;
-parameter ARB_TYPE = "PRIORITY";
-parameter LSB_PRIORITY = "HIGH";
+parameter ARB_TYPE_ROUND_ROBIN = 0;
+parameter ARB_LSB_HIGH_PRIORITY = 1;
 
 // Inputs
 reg clk = 0;
@@ -133,8 +133,8 @@ eth_arb_mux #(
     .DEST_WIDTH(DEST_WIDTH),
     .USER_ENABLE(USER_ENABLE),
     .USER_WIDTH(USER_WIDTH),
-    .ARB_TYPE(ARB_TYPE),
-    .LSB_PRIORITY(LSB_PRIORITY)
+    .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
+    .ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
 )
 UUT (
     .clk(clk),
diff --git a/tb/test_eth_arb_mux_64_4.py b/tb/test_eth_arb_mux_64_4.py
index 75d321252..52b574f04 100755
--- a/tb/test_eth_arb_mux_64_4.py
+++ b/tb/test_eth_arb_mux_64_4.py
@@ -55,8 +55,8 @@ def bench():
     DEST_WIDTH = 8
     USER_ENABLE = 1
     USER_WIDTH = 1
-    ARB_TYPE = "PRIORITY"
-    LSB_PRIORITY = "HIGH"
+    ARB_TYPE_ROUND_ROBIN = 0
+    ARB_LSB_HIGH_PRIORITY = 1
 
     # Inputs
     clk = Signal(bool(0))
diff --git a/tb/test_eth_arb_mux_64_4.v b/tb/test_eth_arb_mux_64_4.v
index ed74367ab..382f2f2d8 100644
--- a/tb/test_eth_arb_mux_64_4.v
+++ b/tb/test_eth_arb_mux_64_4.v
@@ -42,8 +42,8 @@ parameter DEST_ENABLE = 1;
 parameter DEST_WIDTH = 8;
 parameter USER_ENABLE = 1;
 parameter USER_WIDTH = 1;
-parameter ARB_TYPE = "PRIORITY";
-parameter LSB_PRIORITY = "HIGH";
+parameter ARB_TYPE_ROUND_ROBIN = 0;
+parameter ARB_LSB_HIGH_PRIORITY = 1;
 
 // Inputs
 reg clk = 0;
@@ -133,8 +133,8 @@ eth_arb_mux #(
     .DEST_WIDTH(DEST_WIDTH),
     .USER_ENABLE(USER_ENABLE),
     .USER_WIDTH(USER_WIDTH),
-    .ARB_TYPE(ARB_TYPE),
-    .LSB_PRIORITY(LSB_PRIORITY)
+    .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
+    .ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
 )
 UUT (
     .clk(clk),
diff --git a/tb/test_ip_arb_mux_4.py b/tb/test_ip_arb_mux_4.py
index 2127c395c..065cba94a 100755
--- a/tb/test_ip_arb_mux_4.py
+++ b/tb/test_ip_arb_mux_4.py
@@ -55,8 +55,8 @@ def bench():
     DEST_WIDTH = 8
     USER_ENABLE = 1
     USER_WIDTH = 1
-    ARB_TYPE = "PRIORITY"
-    LSB_PRIORITY = "HIGH"
+    ARB_TYPE_ROUND_ROBIN = 0
+    ARB_LSB_HIGH_PRIORITY = 1
 
     # Inputs
     clk = Signal(bool(0))
diff --git a/tb/test_ip_arb_mux_4.v b/tb/test_ip_arb_mux_4.v
index 400c0bb1c..a75bd62e1 100644
--- a/tb/test_ip_arb_mux_4.v
+++ b/tb/test_ip_arb_mux_4.v
@@ -42,8 +42,8 @@ parameter DEST_ENABLE = 1;
 parameter DEST_WIDTH = 8;
 parameter USER_ENABLE = 1;
 parameter USER_WIDTH = 1;
-parameter ARB_TYPE = "PRIORITY";
-parameter LSB_PRIORITY = "HIGH";
+parameter ARB_TYPE_ROUND_ROBIN = 0;
+parameter ARB_LSB_HIGH_PRIORITY = 1;
 
 // Inputs
 reg clk = 0;
@@ -185,8 +185,8 @@ ip_arb_mux #(
     .DEST_WIDTH(DEST_WIDTH),
     .USER_ENABLE(USER_ENABLE),
     .USER_WIDTH(USER_WIDTH),
-    .ARB_TYPE(ARB_TYPE),
-    .LSB_PRIORITY(LSB_PRIORITY)
+    .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
+    .ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
 )
 UUT (
     .clk(clk),
diff --git a/tb/test_ip_arb_mux_64_4.py b/tb/test_ip_arb_mux_64_4.py
index ee633c952..3e58b3b8f 100755
--- a/tb/test_ip_arb_mux_64_4.py
+++ b/tb/test_ip_arb_mux_64_4.py
@@ -55,8 +55,8 @@ def bench():
     DEST_WIDTH = 8
     USER_ENABLE = 1
     USER_WIDTH = 1
-    ARB_TYPE = "PRIORITY"
-    LSB_PRIORITY = "HIGH"
+    ARB_TYPE_ROUND_ROBIN = 0
+    ARB_LSB_HIGH_PRIORITY = 1
 
     # Inputs
     clk = Signal(bool(0))
diff --git a/tb/test_ip_arb_mux_64_4.v b/tb/test_ip_arb_mux_64_4.v
index 5559ebb12..4b140236d 100644
--- a/tb/test_ip_arb_mux_64_4.v
+++ b/tb/test_ip_arb_mux_64_4.v
@@ -42,8 +42,8 @@ parameter DEST_ENABLE = 1;
 parameter DEST_WIDTH = 8;
 parameter USER_ENABLE = 1;
 parameter USER_WIDTH = 1;
-parameter ARB_TYPE = "PRIORITY";
-parameter LSB_PRIORITY = "HIGH";
+parameter ARB_TYPE_ROUND_ROBIN = 0;
+parameter ARB_LSB_HIGH_PRIORITY = 1;
 
 // Inputs
 reg clk = 0;
@@ -185,8 +185,8 @@ ip_arb_mux #(
     .DEST_WIDTH(DEST_WIDTH),
     .USER_ENABLE(USER_ENABLE),
     .USER_WIDTH(USER_WIDTH),
-    .ARB_TYPE(ARB_TYPE),
-    .LSB_PRIORITY(LSB_PRIORITY)
+    .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
+    .ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
 )
 UUT (
     .clk(clk),
diff --git a/tb/test_udp_arb_mux_4.py b/tb/test_udp_arb_mux_4.py
index 69c07767e..8b3d7bf75 100755
--- a/tb/test_udp_arb_mux_4.py
+++ b/tb/test_udp_arb_mux_4.py
@@ -55,8 +55,8 @@ def bench():
     DEST_WIDTH = 8
     USER_ENABLE = 1
     USER_WIDTH = 1
-    ARB_TYPE = "PRIORITY"
-    LSB_PRIORITY = "HIGH"
+    ARB_TYPE_ROUND_ROBIN = 0
+    ARB_LSB_HIGH_PRIORITY = 1
 
     # Inputs
     clk = Signal(bool(0))
diff --git a/tb/test_udp_arb_mux_4.v b/tb/test_udp_arb_mux_4.v
index 4072e624e..bdc127ac0 100644
--- a/tb/test_udp_arb_mux_4.v
+++ b/tb/test_udp_arb_mux_4.v
@@ -42,8 +42,8 @@ parameter DEST_ENABLE = 1;
 parameter DEST_WIDTH = 8;
 parameter USER_ENABLE = 1;
 parameter USER_WIDTH = 1;
-parameter ARB_TYPE = "PRIORITY";
-parameter LSB_PRIORITY = "HIGH";
+parameter ARB_TYPE_ROUND_ROBIN = 0;
+parameter ARB_LSB_HIGH_PRIORITY = 1;
 
 // Inputs
 reg clk = 0;
@@ -201,8 +201,8 @@ udp_arb_mux #(
     .DEST_WIDTH(DEST_WIDTH),
     .USER_ENABLE(USER_ENABLE),
     .USER_WIDTH(USER_WIDTH),
-    .ARB_TYPE(ARB_TYPE),
-    .LSB_PRIORITY(LSB_PRIORITY)
+    .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
+    .ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
 )
 UUT (
     .clk(clk),
diff --git a/tb/test_udp_arb_mux_64_4.py b/tb/test_udp_arb_mux_64_4.py
index a4d0b3de8..afb9261cc 100755
--- a/tb/test_udp_arb_mux_64_4.py
+++ b/tb/test_udp_arb_mux_64_4.py
@@ -55,9 +55,8 @@ def bench():
     DEST_WIDTH = 8
     USER_ENABLE = 1
     USER_WIDTH = 1
-    ARB_TYPE = "PRIORITY"
-    LSB_PRIORITY = "HIGH"
-
+    ARB_TYPE_ROUND_ROBIN = 0
+    ARB_LSB_HIGH_PRIORITY = 1
     # Inputs
     clk = Signal(bool(0))
     rst = Signal(bool(0))
diff --git a/tb/test_udp_arb_mux_64_4.v b/tb/test_udp_arb_mux_64_4.v
index db33c2352..8f3122172 100644
--- a/tb/test_udp_arb_mux_64_4.v
+++ b/tb/test_udp_arb_mux_64_4.v
@@ -42,8 +42,8 @@ parameter DEST_ENABLE = 1;
 parameter DEST_WIDTH = 8;
 parameter USER_ENABLE = 1;
 parameter USER_WIDTH = 1;
-parameter ARB_TYPE = "PRIORITY";
-parameter LSB_PRIORITY = "HIGH";
+parameter ARB_TYPE_ROUND_ROBIN = 0;
+parameter ARB_LSB_HIGH_PRIORITY = 1;
 
 // Inputs
 reg clk = 0;
@@ -201,8 +201,8 @@ udp_arb_mux #(
     .DEST_WIDTH(DEST_WIDTH),
     .USER_ENABLE(USER_ENABLE),
     .USER_WIDTH(USER_WIDTH),
-    .ARB_TYPE(ARB_TYPE),
-    .LSB_PRIORITY(LSB_PRIORITY)
+    .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
+    .ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
 )
 UUT (
     .clk(clk),