diff --git a/rtl/arp_eth_tx.v b/rtl/arp_eth_tx.v
index 727ea3b05..cd5400505 100644
--- a/rtl/arp_eth_tx.v
+++ b/rtl/arp_eth_tx.v
@@ -296,8 +296,8 @@ assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg;
 assign m_eth_payload_axis_tlast = m_eth_payload_axis_tlast_reg;
 assign m_eth_payload_axis_tuser = m_eth_payload_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || !m_eth_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && !m_eth_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/axis_eth_fcs_check.v b/rtl/axis_eth_fcs_check.v
index e9da7df9a..08233f0fc 100644
--- a/rtl/axis_eth_fcs_check.v
+++ b/rtl/axis_eth_fcs_check.v
@@ -280,8 +280,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
 assign m_axis_tlast = m_axis_tlast_reg;
 assign m_axis_tuser = m_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/axis_eth_fcs_check_64.v b/rtl/axis_eth_fcs_check_64.v
index 0ddd5b7f1..d0f407128 100644
--- a/rtl/axis_eth_fcs_check_64.v
+++ b/rtl/axis_eth_fcs_check_64.v
@@ -414,8 +414,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
 assign m_axis_tlast = m_axis_tlast_reg;
 assign m_axis_tuser = m_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/axis_eth_fcs_insert.v b/rtl/axis_eth_fcs_insert.v
index 46735aec8..98feed791 100644
--- a/rtl/axis_eth_fcs_insert.v
+++ b/rtl/axis_eth_fcs_insert.v
@@ -307,8 +307,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
 assign m_axis_tlast = m_axis_tlast_reg;
 assign m_axis_tuser = m_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/axis_eth_fcs_insert_64.v b/rtl/axis_eth_fcs_insert_64.v
index 1ee919375..f83f89efc 100644
--- a/rtl/axis_eth_fcs_insert_64.v
+++ b/rtl/axis_eth_fcs_insert_64.v
@@ -653,8 +653,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
 assign m_axis_tlast = m_axis_tlast_reg;
 assign m_axis_tuser = m_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/eth_arb_mux.v b/rtl/eth_arb_mux.v
index 7f5180864..7c604226f 100644
--- a/rtl/eth_arb_mux.v
+++ b/rtl/eth_arb_mux.v
@@ -241,8 +241,8 @@ assign m_eth_payload_axis_tid    = ID_ENABLE   ? m_eth_payload_axis_tid_reg   :
 assign m_eth_payload_axis_tdest  = DEST_ENABLE ? m_eth_payload_axis_tdest_reg : {DEST_WIDTH{1'b0}};
 assign m_eth_payload_axis_tuser  = USER_ENABLE ? m_eth_payload_axis_tuser_reg : {USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || !m_eth_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && !m_eth_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/eth_axis_rx.v b/rtl/eth_axis_rx.v
index c427ac29a..3501841d1 100644
--- a/rtl/eth_axis_rx.v
+++ b/rtl/eth_axis_rx.v
@@ -333,8 +333,8 @@ assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg;
 assign m_eth_payload_axis_tlast = m_eth_payload_axis_tlast_reg;
 assign m_eth_payload_axis_tuser = m_eth_payload_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || !m_eth_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && !m_eth_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/eth_axis_tx.v b/rtl/eth_axis_tx.v
index 93d131a59..fa742a62b 100644
--- a/rtl/eth_axis_tx.v
+++ b/rtl/eth_axis_tx.v
@@ -337,8 +337,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
 assign m_axis_tlast = m_axis_tlast_reg;
 assign m_axis_tuser = m_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/eth_demux.v b/rtl/eth_demux.v
index 64b4c2fe3..c1db47726 100644
--- a/rtl/eth_demux.v
+++ b/rtl/eth_demux.v
@@ -235,8 +235,8 @@ assign m_eth_payload_axis_tid    = ID_ENABLE   ? {M_COUNT{m_eth_payload_axis_tid
 assign m_eth_payload_axis_tdest  = DEST_ENABLE ? {M_COUNT{m_eth_payload_axis_tdest_reg}} : {M_COUNT*DEST_WIDTH{1'b0}};
 assign m_eth_payload_axis_tuser  = USER_ENABLE ? {M_COUNT{m_eth_payload_axis_tuser_reg}} : {M_COUNT*USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_eth_payload_axis_tready_int_early = (m_eth_payload_axis_tready & m_eth_payload_axis_tvalid) || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid || !m_eth_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_eth_payload_axis_tready_int_early = (m_eth_payload_axis_tready & m_eth_payload_axis_tvalid) || (!temp_m_eth_payload_axis_tvalid_reg && !m_eth_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/eth_mux.v b/rtl/eth_mux.v
index 0a69adcbd..a54ed04b0 100644
--- a/rtl/eth_mux.v
+++ b/rtl/eth_mux.v
@@ -229,8 +229,8 @@ assign m_eth_payload_axis_tid    = ID_ENABLE   ? m_eth_payload_axis_tid_reg   :
 assign m_eth_payload_axis_tdest  = DEST_ENABLE ? m_eth_payload_axis_tdest_reg : {DEST_WIDTH{1'b0}};
 assign m_eth_payload_axis_tuser  = USER_ENABLE ? m_eth_payload_axis_tuser_reg : {USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || !m_eth_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && !m_eth_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/ip_arb_mux.v b/rtl/ip_arb_mux.v
index 91de3cfd3..fbda910b7 100644
--- a/rtl/ip_arb_mux.v
+++ b/rtl/ip_arb_mux.v
@@ -332,8 +332,8 @@ assign m_ip_payload_axis_tid    = ID_ENABLE   ? m_ip_payload_axis_tid_reg   : {I
 assign m_ip_payload_axis_tdest  = DEST_ENABLE ? m_ip_payload_axis_tdest_reg : {DEST_WIDTH{1'b0}};
 assign m_ip_payload_axis_tuser  = USER_ENABLE ? m_ip_payload_axis_tuser_reg : {USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid_reg || !m_ip_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && !m_ip_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/ip_demux.v b/rtl/ip_demux.v
index c7bea23fa..1897d0da8 100644
--- a/rtl/ip_demux.v
+++ b/rtl/ip_demux.v
@@ -326,8 +326,8 @@ assign m_ip_payload_axis_tid    = ID_ENABLE   ? {M_COUNT{m_ip_payload_axis_tid_r
 assign m_ip_payload_axis_tdest  = DEST_ENABLE ? {M_COUNT{m_ip_payload_axis_tdest_reg}} : {M_COUNT*DEST_WIDTH{1'b0}};
 assign m_ip_payload_axis_tuser  = USER_ENABLE ? {M_COUNT{m_ip_payload_axis_tuser_reg}} : {M_COUNT*USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_ip_payload_axis_tready_int_early = (m_ip_payload_axis_tready & m_ip_payload_axis_tvalid) || (!temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid || !m_ip_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_ip_payload_axis_tready_int_early = (m_ip_payload_axis_tready & m_ip_payload_axis_tvalid) || (!temp_m_ip_payload_axis_tvalid_reg && !m_ip_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/ip_eth_rx.v b/rtl/ip_eth_rx.v
index 3f5b9e071..d23844bb0 100644
--- a/rtl/ip_eth_rx.v
+++ b/rtl/ip_eth_rx.v
@@ -516,8 +516,8 @@ assign m_ip_payload_axis_tvalid = m_ip_payload_axis_tvalid_reg;
 assign m_ip_payload_axis_tlast = m_ip_payload_axis_tlast_reg;
 assign m_ip_payload_axis_tuser = m_ip_payload_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid_reg || !m_ip_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && !m_ip_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/ip_eth_rx_64.v b/rtl/ip_eth_rx_64.v
index a77def5c8..46429cc7c 100644
--- a/rtl/ip_eth_rx_64.v
+++ b/rtl/ip_eth_rx_64.v
@@ -622,8 +622,8 @@ assign m_ip_payload_axis_tvalid = m_ip_payload_axis_tvalid_reg;
 assign m_ip_payload_axis_tlast = m_ip_payload_axis_tlast_reg;
 assign m_ip_payload_axis_tuser = m_ip_payload_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid_reg || !m_ip_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && !m_ip_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/ip_eth_tx.v b/rtl/ip_eth_tx.v
index 60ac39a7c..558be2b7d 100644
--- a/rtl/ip_eth_tx.v
+++ b/rtl/ip_eth_tx.v
@@ -436,8 +436,8 @@ assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg;
 assign m_eth_payload_axis_tlast = m_eth_payload_axis_tlast_reg;
 assign m_eth_payload_axis_tuser = m_eth_payload_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || !m_eth_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && !m_eth_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/ip_eth_tx_64.v b/rtl/ip_eth_tx_64.v
index 4677de98c..652519765 100644
--- a/rtl/ip_eth_tx_64.v
+++ b/rtl/ip_eth_tx_64.v
@@ -584,8 +584,8 @@ assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg;
 assign m_eth_payload_axis_tlast = m_eth_payload_axis_tlast_reg;
 assign m_eth_payload_axis_tuser = m_eth_payload_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready | (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg | !m_eth_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && !m_eth_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/ip_mux.v b/rtl/ip_mux.v
index 189692a8f..70e64af9b 100644
--- a/rtl/ip_mux.v
+++ b/rtl/ip_mux.v
@@ -320,8 +320,8 @@ assign m_ip_payload_axis_tid    = ID_ENABLE   ? m_ip_payload_axis_tid_reg   : {I
 assign m_ip_payload_axis_tdest  = DEST_ENABLE ? m_ip_payload_axis_tdest_reg : {DEST_WIDTH{1'b0}};
 assign m_ip_payload_axis_tuser  = USER_ENABLE ? m_ip_payload_axis_tuser_reg : {USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid_reg || !m_ip_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && !m_ip_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/udp_arb_mux.v b/rtl/udp_arb_mux.v
index 49bc25efe..29a39e8e4 100644
--- a/rtl/udp_arb_mux.v
+++ b/rtl/udp_arb_mux.v
@@ -360,8 +360,8 @@ assign m_udp_payload_axis_tid    = ID_ENABLE   ? m_udp_payload_axis_tid_reg   :
 assign m_udp_payload_axis_tdest  = DEST_ENABLE ? m_udp_payload_axis_tdest_reg : {DEST_WIDTH{1'b0}};
 assign m_udp_payload_axis_tuser  = USER_ENABLE ? m_udp_payload_axis_tuser_reg : {USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_udp_payload_axis_tready_int_early = m_udp_payload_axis_tready || (!temp_m_udp_payload_axis_tvalid_reg && (!m_udp_payload_axis_tvalid_reg || !m_udp_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_udp_payload_axis_tready_int_early = m_udp_payload_axis_tready || (!temp_m_udp_payload_axis_tvalid_reg && !m_udp_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/udp_demux.v b/rtl/udp_demux.v
index 17e3d00cf..3605052c9 100644
--- a/rtl/udp_demux.v
+++ b/rtl/udp_demux.v
@@ -354,8 +354,8 @@ assign m_udp_payload_axis_tid    = ID_ENABLE   ? {M_COUNT{m_udp_payload_axis_tid
 assign m_udp_payload_axis_tdest  = DEST_ENABLE ? {M_COUNT{m_udp_payload_axis_tdest_reg}} : {M_COUNT*DEST_WIDTH{1'b0}};
 assign m_udp_payload_axis_tuser  = USER_ENABLE ? {M_COUNT{m_udp_payload_axis_tuser_reg}} : {M_COUNT*USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_udp_payload_axis_tready_int_early = (m_udp_payload_axis_tready & m_udp_payload_axis_tvalid) || (!temp_m_udp_payload_axis_tvalid_reg && (!m_udp_payload_axis_tvalid || !m_udp_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_udp_payload_axis_tready_int_early = (m_udp_payload_axis_tready & m_udp_payload_axis_tvalid) || (!temp_m_udp_payload_axis_tvalid_reg && !m_udp_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/udp_ip_rx.v b/rtl/udp_ip_rx.v
index 5212711d7..2463a8113 100644
--- a/rtl/udp_ip_rx.v
+++ b/rtl/udp_ip_rx.v
@@ -471,8 +471,8 @@ assign m_udp_payload_axis_tvalid = m_udp_payload_axis_tvalid_reg;
 assign m_udp_payload_axis_tlast = m_udp_payload_axis_tlast_reg;
 assign m_udp_payload_axis_tuser = m_udp_payload_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_udp_payload_axis_tready_int_early = m_udp_payload_axis_tready || (!temp_m_udp_payload_axis_tvalid_reg && (!m_udp_payload_axis_tvalid_reg || !m_udp_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_udp_payload_axis_tready_int_early = m_udp_payload_axis_tready || (!temp_m_udp_payload_axis_tvalid_reg && !m_udp_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/udp_ip_rx_64.v b/rtl/udp_ip_rx_64.v
index 37fb3a56c..5c583d9e9 100644
--- a/rtl/udp_ip_rx_64.v
+++ b/rtl/udp_ip_rx_64.v
@@ -496,8 +496,8 @@ assign m_udp_payload_axis_tvalid = m_udp_payload_axis_tvalid_reg;
 assign m_udp_payload_axis_tlast = m_udp_payload_axis_tlast_reg;
 assign m_udp_payload_axis_tuser = m_udp_payload_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_udp_payload_axis_tready_int_early = m_udp_payload_axis_tready || (!temp_m_udp_payload_axis_tvalid_reg && (!m_udp_payload_axis_tvalid_reg || !m_udp_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_udp_payload_axis_tready_int_early = m_udp_payload_axis_tready || (!temp_m_udp_payload_axis_tvalid_reg && !m_udp_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/udp_ip_tx.v b/rtl/udp_ip_tx.v
index ebf1a3b14..7e316365e 100644
--- a/rtl/udp_ip_tx.v
+++ b/rtl/udp_ip_tx.v
@@ -432,8 +432,8 @@ assign m_ip_payload_axis_tvalid = m_ip_payload_axis_tvalid_reg;
 assign m_ip_payload_axis_tlast = m_ip_payload_axis_tlast_reg;
 assign m_ip_payload_axis_tuser = m_ip_payload_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid_reg || !m_ip_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && !m_ip_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/udp_ip_tx_64.v b/rtl/udp_ip_tx_64.v
index a209c17f6..5a77e9492 100644
--- a/rtl/udp_ip_tx_64.v
+++ b/rtl/udp_ip_tx_64.v
@@ -485,8 +485,8 @@ assign m_ip_payload_axis_tvalid = m_ip_payload_axis_tvalid_reg;
 assign m_ip_payload_axis_tlast = m_ip_payload_axis_tlast_reg;
 assign m_ip_payload_axis_tuser = m_ip_payload_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid_reg || !m_ip_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && !m_ip_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/udp_mux.v b/rtl/udp_mux.v
index 5b74cd9b2..eaa76dcce 100644
--- a/rtl/udp_mux.v
+++ b/rtl/udp_mux.v
@@ -348,8 +348,8 @@ assign m_udp_payload_axis_tid    = ID_ENABLE   ? m_udp_payload_axis_tid_reg   :
 assign m_udp_payload_axis_tdest  = DEST_ENABLE ? m_udp_payload_axis_tdest_reg : {DEST_WIDTH{1'b0}};
 assign m_udp_payload_axis_tuser  = USER_ENABLE ? m_udp_payload_axis_tuser_reg : {USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_udp_payload_axis_tready_int_early = m_udp_payload_axis_tready || (!temp_m_udp_payload_axis_tvalid_reg && (!m_udp_payload_axis_tvalid_reg || !m_udp_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_udp_payload_axis_tready_int_early = m_udp_payload_axis_tready || (!temp_m_udp_payload_axis_tvalid_reg && !m_udp_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source