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Commits on Feb 13, 2024

• Reorganize PTP timestamp capture logic; determine PTP clock step size from PTP time instead of parameters

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Commits on Feb 11, 2024

• Add ptp_td_rel2tod module for timestamp reconstruction

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• Move alternate offset switch near the end of the current second to extend reconstruction range for timestamps in the past

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• Clean up PTP parameters on MACs

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Commits on Feb 9, 2024

• Remove extraneous scaleb(-9) in set_ts_tod_ns in ptp_td so that the seconds field can be set correctly

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Commits on Feb 6, 2024

• merged changes in axis

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• Split out and pipeline relative timestamp LSB increment in PTP TD leaf clock

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Commits on Jan 30, 2024

• Rework MAC TX error handling to streamline logic; pad errored frames to avoid generating runt frames

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• Add TX underrun and error tests

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• Cleanup RGMII PHY IF, fix TX error indication

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Commits on Jan 29, 2024

• Fix wait end state in GMII TX

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• Clean up XGMII symbol generation

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• Force AXIS RAM switch output FIFO into distributed RAM

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Commits on Jan 28, 2024

• Handle framing errors in payload state in XGMII RX module

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• Unconditionally transfer out XGMII data in XGMII RX modules

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• Move timestamp capture into payload state in XGMII RX module

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Commits on Jan 27, 2024

• Rework termination character handling in XGMII RX modules

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Commits on Jan 26, 2024

• Fix spurious multi-driven net issue in axis_ram_switch when S_ID_WIDTH = 0

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Commits on Jan 17, 2024

• merged changes in axis

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• Remove stall cycle in axis_arb_mux

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• Fix FIFO output pause logic

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• More extensive overhaul of the PTP period output module to improve resource consumption and parallelize computation

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Commits on Jan 16, 2024

• Separate locked status from fast-forward mode in PTP period output module

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Commits on Jan 15, 2024

• Add missing assign to frame_min_count_reg in axis_xgmii_tx_32 module

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• Add CRC state registers where possible to 10G/25G MAC modules

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• Optimize block type decoding in 10G PHY RX to reduce fanin

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• Add register on PRBS checker output in 10G PHY RX to improve timing performance

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Commits on Jan 14, 2024

• Rename Arista_7132LB to DCS7132LB

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Commits on Dec 2, 2023

• Rework PHC to register shared adder outputs for improved timing performance

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• Prevent stale data frim being used to sync leaf clock

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• Improve tolerance of sample point synchronization

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• Rewrite gain scheduling

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• Add test for PCIe spread spectrum clocking

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Commits on Dec 1, 2023

• Remove unnecessary shadow valid registers

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• Improve handling of instance name mangling

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