How and where are the inputs given?

[sametzeybek]

Hi Alex,
I want to export data to test_eth_mac_10g_fifo_64.v module myself. Where exactly are you giving transmitter inputs like tx_axis_tdata? As far as I can see from Vivado, it pulls the inputs from the testbench module where it says "$from_myhdl", where can I find this part? I can run Testbench on Ubuntu, but I couldn't understand how the inputs are given, I would be very happy if you could help.
In addition, how do these modules work integrated with cocotb testbench? I would appreciate it if you could make a YouTube video where you can explain this through code.

[alexforencich]

The MyHDL testbenches are old; the current cocotb testbench for the 10G MAC is here: https://github.com/alexforencich/verilog-ethernet/tree/master/tb/eth_mac_10g_fifo. Unfortunately, Vivado's simulator PLI is incomplete and hence cannot be used with cocotb.

Data is driven through the HDL using simulation models from cocotbext-axi and cocotbext-eth, which are instantiated here:

https://github.com/alexforencich/verilog-ethernet/blob/master/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py#L66-L70

These act as streaming sources and sinks, so data can be sent into the MAC like so:

https://github.com/alexforencich/verilog-ethernet/blob/master/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py#L114

And then the response can be retrieved later on: https://github.com/alexforencich/verilog-ethernet/blob/master/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py#L117