Logic clock (MAC)

[MarcoPanconesi]

Hi,
I'm Marco and I have a question: I saw the logic_clk of the eth_MAC_10g_fifo connected to ground in the Synthesis schematic. Is it normal?

[alexforencich]

Doesn't sound right to me, but logic_clk should be supplied by your application logic at an appropriate frequency (doesn't have to match the MAC clocks due to the async FIFOs)

[MarcoPanconesi]

Thank you for your answer but I still don't understand.
The logic_clk port of eth_MAC_10G_fifo receives the same clock of the tx_clk port of the same module, correct?
This clock is the tx_userclk2 generated by the transceiver.
However in the sythesis schematic the logic_clk port seems connected to ground.

[MarcoPanconesi]

Thank you very much.

[alexforencich]

Odd, in my case the synthesized design doesn't even show a pin called "logic_clk". Possibly there is some optimization/renaming/etc. taking place here. How exactly did you get to that schematic? Just "open synthesized design?" What version of Vivado are you using?

[MarcoPanconesi]

I'm using Vivado 2023.1.
Probably the difference is caused by a different Sythesis settings. In order to have a better view for debug I set flatten_hierarchy to none. This should keep the synthesis design as close to the RTL design as possible instead of rearrange it, and it shouldn't interest the logic.

[alexforencich]

Well, the only explanation that I can think of is that the logic_clk was merged into tx_clk since they are driven from the same source, but for whatever reason the now-unused logic_clk pin is still shown in the schematic.

[MarcoPanconesi]

I understand, thanks a lot again for the help.