Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Example for Digilent Genesys2 board (XC7K325T) #93

Open
wants to merge 10 commits into
base: master
Choose a base branch
from

Conversation

unbtorsten
Copy link

Porting KC705 example to Genesys2, the implementation has been inspired by pull request #6 and is compatible with the latest commits.

unbtorsten and others added 7 commits September 16, 2021 08:26
derive example for Genesys2 board from Xilinx evaluation board KC705 which has the same FPGA
…ntation verified on hardware, but not by test bench
align FPGA part name with requirements of Xilinx Vivado
@unbtorsten unbtorsten mentioned this pull request Oct 5, 2021
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

1 participant