diff --git a/openfasoc/generators/glayout/glayout/flow/routing/smart_route.py b/openfasoc/generators/glayout/glayout/flow/routing/smart_route.py index 0443f89f9..e47c64b9f 100644 --- a/openfasoc/generators/glayout/glayout/flow/routing/smart_route.py +++ b/openfasoc/generators/glayout/glayout/flow/routing/smart_route.py @@ -264,48 +264,54 @@ def generic_route_ab_ba_common_centroid( # TODO: implement name1, name2 = parse_port_name(edge1.name), parse_port_name(edge2.name) width1 = edge1.width + # grab basename for reading ports + basename = edge1.name.rstrip("NESW").rstrip("_") + basename = basename.removesuffix("source").removesuffix("drain").removesuffix("gate").rstrip("_") + basename = basename.removesuffix("A").removesuffix("B") + def get_top_port(prtname): + return top_comp.ports[basename + prtname] # order names so that A is first (if only one A) if "A" in name2 and not("A" in name1): name1, name2 = name2, name1 # same device routes (A->A or B->B) (6/15) if check_route(name1,name2,"A_source","A_gate"): - return straight_route(pdk, top_comp.ports["A_source_E_private"],top_comp.ports["A_gate_route_con_N"],via2_alignment=("right","bottom")) + return straight_route(pdk, get_top_port("A_source_E_private"),get_top_port("A_gate_route_con_N"),via2_alignment=("right","bottom")) if check_route(name1,name2,"A_drain","A_gate"): - return straight_route(pdk, top_comp.ports["A_drain_E_private"],top_comp.ports["A_gate_route_con_N"],via2_alignment=("right","top")) + return straight_route(pdk, get_top_port("A_drain_E_private"),get_top_port("A_gate_route_con_N"),via2_alignment=("right","top")) if check_route(name1,name2,"A_source","A_drain"): - straight_route(pdk, top_comp.ports["br_multiplier_0_source_N"],top_comp.ports["br_multiplier_0_drain_S"],width=min(width1,1)) - return straight_route(pdk, top_comp.ports["tl_multiplier_0_source_S"],top_comp.ports["tl_multiplier_0_drain_N"],width=min(width1,1)) + straight_route(pdk, get_top_port("br_multiplier_0_source_N"),get_top_port("br_multiplier_0_drain_S"),width=min(width1,1)) + return straight_route(pdk, get_top_port("tl_multiplier_0_source_S"),get_top_port("tl_multiplier_0_drain_N"),width=min(width1,1)) if check_route(name1,name2,"B_source","B_gate"): - return straight_route(pdk, top_comp.ports["B_source_W_private"],top_comp.ports["B_gate_route_con_N"],via2_alignment=("left","bottom")) + return straight_route(pdk, get_top_port("B_source_W_private"),get_top_port("B_gate_route_con_N"),via2_alignment=("left","bottom")) if check_route(name1,name2,"B_drain","B_gate"): - return straight_route(pdk, top_comp.ports["B_drain_W_private"],top_comp.ports["B_gate_route_con_N"],via2_alignment=("left","top")) + return straight_route(pdk, get_top_port("B_drain_W_private"),get_top_port("B_gate_route_con_N"),via2_alignment=("left","top")) if check_route(name1,name2,"B_source","B_drain"): - top_comp << straight_route(pdk, top_comp.ports["tr_multiplier_0_source_S"],top_comp.ports["tr_multiplier_0_drain_N"],width=min(width1,1)) - return straight_route(pdk, top_comp.ports["bl_multiplier_0_source_N"],top_comp.ports["bl_multiplier_0_drain_S"],width=min(width1,1)) + top_comp << straight_route(pdk, get_top_port("tr_multiplier_0_source_S"),get_top_port("tr_multiplier_0_drain_N"),width=min(width1,1)) + return straight_route(pdk, get_top_port("bl_multiplier_0_source_N"),get_top_port("bl_multiplier_0_drain_S"),width=min(width1,1)) # A_src/drain->B_gate or B_src/drain->A_gate (4/15) if check_route(name1,name2,"A_source","B_gate"): - return straight_route(pdk, top_comp.ports["A_source_W_private"],top_comp.ports["B_gate_route_con_N"],via2_alignment=("left","top")) + return straight_route(pdk, get_top_port("A_source_W_private"),get_top_port("B_gate_route_con_N"),via2_alignment=("left","top")) if check_route(name1,name2,"A_drain","B_gate"): - return straight_route(pdk, top_comp.ports["A_drain_W_private"],top_comp.ports["B_gate_route_con_N"],via2_alignment=("left","bottom")) + return straight_route(pdk, get_top_port("A_drain_W_private"),get_top_port("B_gate_route_con_N"),via2_alignment=("left","bottom")) if check_route(name1,name2,"B_source","A_gate"): - return straight_route(pdk, top_comp.ports["B_source_E_private"],top_comp.ports["A_gate_route_con_N"],via2_alignment=("right","top")) + return straight_route(pdk, get_top_port("B_source_E_private"),get_top_port("A_gate_route_con_N"),via2_alignment=("right","top")) if check_route(name1,name2,"B_drain","A_gate"): - return straight_route(pdk, top_comp.ports["B_drain_E_private"],top_comp.ports["A_gate_route_con_N"],via2_alignment=("right","bottom")) + return straight_route(pdk, get_top_port("B_drain_E_private"),get_top_port("A_gate_route_con_N"),via2_alignment=("right","bottom")) # A_src/drain->B_src or A_src/drain->B_drain (4/15) if check_route(name1,name2,"A_source","B_source"): - return straight_route(pdk, top_comp.ports["tl_multiplier_0_source_E"],top_comp.ports["tr_multiplier_0_source_W"]) + return straight_route(pdk, get_top_port("tl_multiplier_0_source_E"),get_top_port("tr_multiplier_0_source_W")) if check_route(name1,name2,"A_drain","B_source"): - portmv1 = top_comp.ports["tl_multiplier_0_drain_E"].copy() - return straight_route(pdk, top_comp.ports["tl_multiplier_0_drain_E"],movex(portmv1,2*pdk.get_grule(pdk.layer_to_glayer(portmv1.layer))["min_separation"])) + portmv1 = get_top_port("tl_multiplier_0_drain_E").copy() + return straight_route(pdk, get_top_port("tl_multiplier_0_drain_E"),movex(portmv1,2*pdk.get_grule(pdk.layer_to_glayer(portmv1.layer))["min_separation"])) if check_route(name1,name2,"A_source","B_drain"): - portmv1 = top_comp.ports["tr_multiplier_0_drain_W"].copy() - return straight_route(pdk, top_comp.ports["tr_multiplier_0_drain_W"],movex(portmv1,-2*pdk.get_grule(pdk.layer_to_glayer(portmv1.layer))["min_separation"])) + portmv1 = get_top_port("tr_multiplier_0_drain_W").copy() + return straight_route(pdk, get_top_port("tr_multiplier_0_drain_W"),movex(portmv1,-2*pdk.get_grule(pdk.layer_to_glayer(portmv1.layer))["min_separation"])) if check_route(name1,name2,"A_drain","B_drain"): - portmv1 = top_comp.ports["bl_mutliplier_0_drain_N"].copy() - portmv2 = top_comp.ports["br_multiplier_0_drain_N"].copy() - top_comp << straight_route(pdk, movex(portmv1,-portmv1.width/2), top_comp.ports["tl_multiplier_0_drain_S"],width=width1) - return straight_route(pdk, movex(portmv2,portmv2.width/2),top_comp.ports["tr_multiplier_0_drain_S"]) + portmv1 = get_top_port("bl_mutliplier_0_drain_N").copy() + portmv2 = get_top_port("br_multiplier_0_drain_N").copy() + top_comp << straight_route(pdk, movex(portmv1,-portmv1.width/2), get_top_port("tl_multiplier_0_drain_S"),width=width1) + return straight_route(pdk, movex(portmv2,portmv2.width/2),get_top_port("tr_multiplier_0_drain_S")) # A_gate -> B_gate (1/15) if check_route(name1,name2,"A_gate","B_gate"): - return straight_route(pdk,top_comp.ports["br_multiplier_0_gate_W"],top_comp.ports["bl_multiplier_0_gate_E"]) + return straight_route(pdk,get_top_port("br_multiplier_0_gate_W"),get_top_port("bl_multiplier_0_gate_E")) raise ValueError("You picked a port that smart_route with ab_ba_common_centroid does not support") diff --git a/openfasoc/generators/glayout/glayout/llm/manage_data.py b/openfasoc/generators/glayout/glayout/llm/manage_data.py index 9c8e40c0d..a8bcfe5f3 100644 --- a/openfasoc/generators/glayout/glayout/llm/manage_data.py +++ b/openfasoc/generators/glayout/glayout/llm/manage_data.py @@ -217,9 +217,9 @@ def get_prompt_from_template( inst_prompt += f"Below is some context on Glayout strictsyntax:\n{glayout_nlp_context}\n\n" #inst_prompt += "Below is context on the circuit" #inst_prompt += "convert an example prompt to Glayout strictsyntax\n" - #inst_prompt += f"{ragcontext}\n\n----\nTRANSLATION TASK\n" + inst_prompt += f"\n{ragcontext}\n" #inst_prompt += f"Do NOT include the context in your response. Convert the following prompt to Glayout strictsyntax:\n{prompt}" - inst_prompt += f"Glayout strictsyntax is a electronic circuit layout command language. Convert the following prompt to Glayout strictsyntax:\n{prompt}" + inst_prompt += f"Convert the following prompt to Glayout strictsyntax:\n{prompt}" # unify prompt and return messages = [{"role": "user", "content": inst_prompt}] # conditionally add label (expected strict syntax output) @@ -268,12 +268,14 @@ def load_preprocessed_data_in_messages_format(): # train train_messages = list() for prompt, result in train_examples: - train_messages.append(get_prompt_from_template(None,None,prompt,result,True)) + ragcontext = RAGvecdb.query(prompt, 1) + train_messages.append(get_prompt_from_template(None,ragcontext,prompt,result,True)) train_data = Dataset.from_dict({"messages":train_messages}) # eval eval_messages = list() for prompt, result in eval_examples: - eval_messages.append(get_prompt_from_template(None,None,prompt,result,True)) + ragcontext = RAGvecdb.query(prompt, 1) + eval_messages.append(get_prompt_from_template(None,ragcontext,prompt,result,True)) eval_data = Dataset.from_dict({"messages":eval_messages}) return {"train": train_data, "evaluation": eval_data} diff --git a/openfasoc/generators/glayout/glayout/llm/rag_data/CommonSource.md b/openfasoc/generators/glayout/glayout/llm/rag_data/CommonSource.md index 4d12fe1fd..a0a354842 100644 --- a/openfasoc/generators/glayout/glayout/llm/rag_data/CommonSource.md +++ b/openfasoc/generators/glayout/glayout/llm/rag_data/CommonSource.md @@ -1,15 +1,2 @@ -# Common Source Amplifier -The common source amplifier, serves as an amplifier with voltage gain and phase inversion. -The main amplifying transistor is in a common-source configuration. Its source is connected to a common reference (often ground), its gate receives the input signal, and the drain is connected to the active load. +# Common Source Amplifier There are two MOSFETs. One acts as the amplifying stage and we will call this M1, and the other is the active load which we will call M2. Depending on the type of active load, the port of the active load corresponding to the direction of current is connected to the drain of M1. The source of M1 is connected to a lower voltage level than the supply. -Pseudo Netlist: -an nmos is has the following subckt definition: -NMOS drain gate source body -a pmos is has the following subckt definition: -PMOS drain gate source body - -a common source amplifier with a biased pfet transistor has the following subckt definition: -.subckt commonsourceamp vin vbias vdd vss vout -m1 vout vin vss vss NMOS -m2 vout vbias vdd vdd PMOS -.endsubckt diff --git a/openfasoc/generators/glayout/glayout/llm/rag_data/CurrentMirror.md b/openfasoc/generators/glayout/glayout/llm/rag_data/CurrentMirror.md index 785621f87..f9336a517 100644 --- a/openfasoc/generators/glayout/glayout/llm/rag_data/CurrentMirror.md +++ b/openfasoc/generators/glayout/glayout/llm/rag_data/CurrentMirror.md @@ -1,12 +1,4 @@ # Current Mirror A current mirror is a circuit designed to copy a current The ratio is the width ratio between mirror and reference, used to tune the relative current between mirror transistor drain and reference transistor drain. -two transistors (either nfet or pfet) one labeled as the reference which accepts an input current at the drain, and one labeled as mirror which has the output current at the drain. The sources of reference and mirror are connected and the gates of reference and mirror are also connected. The drain of the reference is connected to gate of reference. -Pseudo Netlist: -an nmos is has the following subckt definition: -NMOS drain gate source body -the nfet current mirror has the following subckt definition: -.subckt currentmirror inputcurrent outputcurrent -reference inputcurrent inputcurrent gnd gnd NMOS -mirror outputcurrent inputcurrent gnd gnd NMOS -.endsubckt \ No newline at end of file +two transistors (either nfet or pfet) one labeled as the reference which accepts an input current at the drain, and one labeled as mirror which has the output current at the drain. The sources of reference and mirror are connected and the gates of reference and mirror are also connected. The drain of the reference is connected to gate of reference. \ No newline at end of file diff --git a/openfasoc/generators/glayout/glayout/llm/rag_data/DeltaSigmaModulator.md b/openfasoc/generators/glayout/glayout/llm/rag_data/DeltaSigmaModulator.md new file mode 100644 index 000000000..4d8a45aa1 --- /dev/null +++ b/openfasoc/generators/glayout/glayout/llm/rag_data/DeltaSigmaModulator.md @@ -0,0 +1,2 @@ +# Delta Sigma Modulator ADC +A delta sigma modulator is a circuit consisting of several existing components including an opamp and a latched comparator. The latched compartor includes a d flip flop and a strong arm latch. All these components can be directly imported. The outputs of the opamp should be connected to the inputs of the latched comparator. \ No newline at end of file diff --git a/openfasoc/generators/glayout/glayout/llm/rag_data/StrongArmLatch.md b/openfasoc/generators/glayout/glayout/llm/rag_data/StrongArmLatch.md index 366dc1703..b1ed63e08 100644 --- a/openfasoc/generators/glayout/glayout/llm/rag_data/StrongArmLatch.md +++ b/openfasoc/generators/glayout/glayout/llm/rag_data/StrongArmLatch.md @@ -1,3 +1,2 @@ # Strong Arm Latch -A strong arm latch is a comparator (which means it compares two input voltages). If one voltage is higher it outputs a high voltage and if one of them is lower then it output a low voltage. -A strong arm latch consists of a diffpair. The inputs of the diffpair are the inputs of the strong arm latch. The diff pair outputs are connected to a cross coupled inverter..... drain. There are 2 pfets for... \ No newline at end of file +A strong arm latch consists of a diffpair, a CrossCoupleInverters, a bridge nfet, a clkgnd nfet, and two pfets clkpwrL (west) and clkpwrR (east). The cross coupled inverters should be at the top. The bridge should be above the diffpair but below the cross coupled inverters. The clkgnd should be at the bottom, and both clkpwr transistors should be left and right of the cross coupled inverters. You must route the drain of transistor A of the diffpair with the drain of the bridge, the drain of transistor B of the diffpair with the source of the bridge, the source of transistor A in the diffpair with the source of clkgnd. \ No newline at end of file diff --git a/openfasoc/generators/glayout/glayout/llm/rag_data/diffpair.md b/openfasoc/generators/glayout/glayout/llm/rag_data/diffpair.md index ffe2c3cfa..5036571d6 100644 --- a/openfasoc/generators/glayout/glayout/llm/rag_data/diffpair.md +++ b/openfasoc/generators/glayout/glayout/llm/rag_data/diffpair.md @@ -8,9 +8,6 @@ width: a float parameter specifying the width of all transistor Components part fingers: an integer parameter which modifies the number of fingers in all transistor Components which are part of the diff pair. ## Ports The following are just some examples of the valid ports for diff_pair: -ComponentRef_A_source_S -ComponentRef_A_drain_N -ComponentRef_B_source_S -ComponentRef_A_gate_E +ComponentRef_A_source_E ComponentRef_B_drain_W -ComponentRef_B_gate_E +ComponentRef_A_gate_E diff --git a/openfasoc/generators/glayout/glayout/llm/rag_data/opamp.md b/openfasoc/generators/glayout/glayout/llm/rag_data/opamp.md index 9b64abcda..1cd554fb6 100644 --- a/openfasoc/generators/glayout/glayout/llm/rag_data/opamp.md +++ b/openfasoc/generators/glayout/glayout/llm/rag_data/opamp.md @@ -1,13 +1,2 @@ # Opamp -An operational amplifier or opamp is a voltage amplifying device. -## Terms Defined -Inverting Input (IN-): The input terminal where the signal is inversely amplified.
-Non-inverting Input (IN+): The input terminal where the signal is amplified retaining its original phase.
-Output Terminal: Where the amplified signal is provided.
-Power Supply Ports: Two ports, one for the positive power supply voltage (V+), and one for the negative (V-).
-Bias Current: The current that flows into the input terminals due to internal transistor biasing.
-Open-Loop Gain: The amplification factor of the operational amplifier without any feedback.
-Slew Rate: The maximum rate at which the output voltage can change, often specified in V/µs.
-Offset Voltage: A small voltage that must be applied between the input terminals to ensure a zero volt output without any signal. -### In Words -The op amp symbol consists of a triangle pointing to the right with five terminals: two input terminals on the left side, one output terminal on the triangle's right tip, and two power supply terminals (-V and +V) at the top and bottom respectively. The non-inverting input (IN+) is usually shown at the top left of the triangle, and the inverting input (IN-) is depicted below it. \ No newline at end of file +An operational amplifier or opamp is a voltage amplifying device. A 4 stage opamp consists of several integrator stages. \ No newline at end of file diff --git a/openfasoc/generators/glayout/glayout/llm/rag_data/pushpullamp.md b/openfasoc/generators/glayout/glayout/llm/rag_data/pushpullamp.md index 208f25f65..9af29f92d 100644 --- a/openfasoc/generators/glayout/glayout/llm/rag_data/pushpullamp.md +++ b/openfasoc/generators/glayout/glayout/llm/rag_data/pushpullamp.md @@ -1,23 +1,2 @@ # Push Pull Amp (Class B Amplifier) -A push-pull amplifier is a type of amplifier which is able to - -## Terms Defined - -Class: The amplifier class, such as Class A, B, AB, or C, indicating the portion of the input signal cycle during which each transistor conducts. -Active Device: The amplifying element, often a transistor, that can control a large current flow with a smaller input signal. -Biasing: The process of setting the initial operating point of an active device. -Crossover Distortion: A form of distortion that occurs in Class B and AB push-pull amplifiers due to the transition between the "push" and "pull" transistors. - -## Schematic - -### In Words - -A push-pull amplifier typically consists of two transistors, an NPN (or N-channel MOSFET) and a PNP (or P-channel MOSFET) transistor. The emitters (or sources) of the two transistors are connected together and to the output load. The bases (or gates) receive the input signal through a phase splitter, which creates two signals that are 180 degrees out of phase with each other. The collectors (or drains) of each transistor are connected to the supply voltages. - -### Pseudo Netlist - -A push pull amp has the following subckt definition: .subckt pushpullamp input output vcc vee -Q1 NPN_collector input common vcc NPN -Q2 PNP_collector input common vee PNP -.endsubckt - +A push-pull amplifier typically consists of two transistors, a nmos and pmos. The sources of the two transistors are connected together and to the output load. The drains of each transistor are connected to the supply voltages. \ No newline at end of file diff --git a/openfasoc/generators/glayout/glayout/llm/rag_data/resistor.md b/openfasoc/generators/glayout/glayout/llm/rag_data/resistor.md deleted file mode 100644 index 93fd47720..000000000 --- a/openfasoc/generators/glayout/glayout/llm/rag_data/resistor.md +++ /dev/null @@ -1,28 +0,0 @@ -# Resistor - -## Purpose - -A resistor is a passive electrical component that provides electrical resistance in an electronic circuit. The main purpose of a resistor is to limit electrical current, divide voltages, and dissipate power as heat. They are essential in creating specific voltage or current relationships in circuits, adjusting signal levels, biasing active elements, and terminating transmission lines, among many other applications. - -## Ohm's Law - -The fundamental characteristic of a resistor is described by Ohm's Law, which states that the current (I) through a conductor between two points is directly proportional to the voltage (V) across the two points and inversely proportional to the resistance (R) of the conductor: - -$[ V = I \times R ]$ - -## Construction and Characteristics - -Resistors can be constructed from various materials, such as carbon, metal film, or wires wound around a core. They are specified by resistance value, power rating, tolerance, temperature coefficient, and stability. The resistance value determines how much it will oppose current flow, while the power rating specifies the maximum power it can dissipate without damage. -Schematic Symbol - -The schematic symbol for a resistor is typically a zigzag line with two protruding terminals representing the points of electrical connection. European schematics sometimes use a simple rectangle instead of the zigzag symbol. - - -## Performance Specifications - -Resistance: The main parameter of a resistor, typically measured in ohms (Ω).
-Tolerance: Indicates how much the actual resistance can vary from the specified value, often given as a percentage (e.g., ±1%, ±5%).
-Power Rating: The maximum power, usually in watts (W), that a resistor can safely dissipate as heat.
-Temperature Coefficient: Describes how the resistance changes with temperature, important for precision applications. - -Resistors are reliable, economical, and widely available components that remain integral to nearly every electronic circuit. Whether used singly or in networks, resistors shape the behavior of circuits in predictable and controllable ways. diff --git a/openfasoc/generators/glayout/glayout/llm/rag_data/ringoscillator.md b/openfasoc/generators/glayout/glayout/llm/rag_data/ringoscillator.md deleted file mode 100644 index 4159db158..000000000 --- a/openfasoc/generators/glayout/glayout/llm/rag_data/ringoscillator.md +++ /dev/null @@ -1,41 +0,0 @@ -# Ring Oscillator - -## Purpose - -A ring oscillator is a type of electronic oscillator that produces a periodic oscillating electronic signal (often a square wave). It consists of an odd number of NOT gates or inverters whose output is connected back to the input, forming a closed loop. The main purpose of the ring oscillator is to generate a high-frequency clock signal and for use in integrated circuits as a timing element. It's also frequently used in characterizing and testing the properties of semiconductor technologies, such as propagation delay and signal integrity. - -## Terms Defined - -Inverter: A logic gate that outputs the complement (opposite) of its input signal.
-Propagation Delay (t_pd): The time delay it takes for a signal to pass through one stage of the circuit, such as an inverter.
-Frequency (f): The frequency of oscillation, determined by the number of inverters and the propagation delay. - -## Theory - -The operation of a ring oscillator is based on the propagation delay inherent in the inverters. When the loop is closed, an initial change in voltage at the first inverter's input propagates through each inverter in the chain. Since an odd number of inverters are used, the output of the last inverter is an inverted version of the original signal, which becomes the input to the first inverter, perpetuating the oscillation. The frequency of oscillation is inversely proportional to the total propagation delay through the loop (the sum of the delay through each inverter and any delay from wiring) and can be estimated by: - -$[ f = \frac{1}{t_{pd} \times N} ]$ - -where $( t_{pd} )$ is the individual delay for one inverter and ( N ) is the number of inverters. - -## Schematic - -### Described in Words - -A ring oscillator circuit uses an odd number of inverters connected in series. The output of the last inverter is fed back to the input of the first, creating a feedback loop. - -### Pseudo Netlist - -A pseudo netlist of a ring oscillator can be written as:.subckt ringoscillator out X1 out net1 INV X2 net1 net2 INV ... XN net(N-1) out INV .endsubckt - -In this netlist, X1...XN denote individual inverters, net1...net(N-1) represent internal connections between inverters, and INV stands for the inverter model. - -## Performance Specifications - -Performance characteristics of a ring oscillator include: - -Frequency Stability: Often limited due to sensitivity to supply voltage variations and temperature changes.
-Power Consumption: Related to the number of stages and the frequency of operation, with higher frequencies generally leading to higher power usage.
-Phase Noise: The short-term frequency stability of the oscillator, affected by the quality of the inverters and the supply noise. - - diff --git a/openfasoc/generators/glayout/glayout/llm/rag_data/tia.md b/openfasoc/generators/glayout/glayout/llm/rag_data/tia.md deleted file mode 100644 index bea41570b..000000000 --- a/openfasoc/generators/glayout/glayout/llm/rag_data/tia.md +++ /dev/null @@ -1,40 +0,0 @@ -# Transimpedance Amplifier (TIA) - -## Purpose - -A Transimpedance Amplifier (TIA) is an amplifier that converts an input current to a proportional output voltage. The primary role of a TIA is in applications where current signals need to be detected or measured, and amplified into a more usable voltage level. Commonly, TIAs are used with photodiodes, photomultiplier tubes, or other sensors that produce a current proportional to the intensity of light they receive. - -## Terms Defined - -Photodiode: A semiconductor device that generates a current when exposed to light.
-Feedback Resistor $(R_f)$: The resistor in the feedback loop of the TIA that sets the gain of the amplifier.
-Transimpedance Gain: The ratio of the output voltage to the input current, given in ohms, which is numerically equal to the value of the feedback resistor (R_f). - -## Theory - -The TIA uses a feedback resistor to set the gain of the amplifier and convert a small input current (I_in) from a sensor or photodiode to a larger output voltage (V_out). Ohm’s law describes the relationship between the input current and the output voltage of a TIA: $V_out = I_in * R_f$. Because the input is current and the output is voltage, the transimpedance gain has units of resistance, which is what gives the TIA its name. In an ideal TIA, the input impedance is close to zero, which ensures that the current flows through the amplifier, and the output impedance is low. - -## Schematic - -### Described in Words - -In the schematic of a TIA, an op-amp is configured with the photodiode connected between its inverting input and the ground, effectively reverse-biasing the photodiode when the op-amp output swings positive. The non-inverting input is connected to a reference voltage, often ground. A feedback resistor is connected between the op-amp's output and its inverting input. - -### Pseudo Netlist - -An operational amplifier has the following subckt definition: .subckt opamp inverting_input non_inverting_input output v_positive v_negative - -A pseudo netlist of a tia can be written as: -.subckt tia pd_in v_out v_ref XU1 op_out pd_in v_ref opamp Rf op_out pd_in .endsubckt - -In this netlist, XU1 represents the operational amplifier, pd_in is the input from the photodiode, v_out is the output voltage of the TIA, and v_ref is the reference voltage for the non-inverting input. Rf is the feedback resistor which sets the gain of the TIA. - -## Performance Specifications - -Important specifications for a TIA include: - -Bandwidth: The range of frequencies over which the TIA will have a consistent gain. This is often affected by the feedback resistor and any parasitic capacitance at the input.
-Noise Performance: Critical for the sensitivity of the TIA as it amplifies the signal from the photodiode. Includes contributions from the feedback resistor, the op-amp, and the diode itself.
-Dynamic Range: The range of input currents over which the TIA can provide a linear output voltage response.
-Stability: Factors such as the capacitance of the photodiode and the value of Rf can affect the stability and may lead to oscillations if not properly compensated. - diff --git a/openfasoc/generators/glayout/glayout/llm/rag_data/voltagefollower.md b/openfasoc/generators/glayout/glayout/llm/rag_data/voltagefollower.md deleted file mode 100644 index 91ac5efe5..000000000 --- a/openfasoc/generators/glayout/glayout/llm/rag_data/voltagefollower.md +++ /dev/null @@ -1,50 +0,0 @@ -# Voltage Follower - -## Purpose - -A voltage follower, also known as a buffer amplifier, is a circuit configuration where the output voltage directly follows the input voltage. This means the output voltage is the same as the input voltage. The primary purpose of a voltage follower is to increase the input impedance (ideally to infinity) and decrease the output impedance (ideally to zero), thus providing no voltage gain but significant current gain. This allows the voltage follower to serve as a buffer, isolating the source from the load while preventing signal attenuation that would occur if the load were directly connected to the source. - -## Terms Defined - -Anode: The terminal through which conventional current flows into the diode, typically marked with a plus sign. -Cathode: The terminal through which conventional current flows out of the diode, often denoted with a line or band on the diode body. -Forward Bias: A condition where the anode is more positive relative to the cathode, allowing current flow. -Reverse Bias: A condition where the cathode is more positive in relation to the anode, restricting current flow. -Forward Voltage Drop (Vf): The potential difference across the diode terminals when current is conducted in the forward direction, typically 0.7V for silicon diodes and 0.3V for germanium diodes. -Reverse Breakdown Voltage (V_br): The voltage at which the diode will conduct a significant reverse current, potentially leading to device damage if sustained. - -## Theory - -The voltage follower is realized using an operational amplifier (op-amp) with 100% negative feedback provided by a direct connection from the output terminal back to the inverting input. There is no external feedback network of resistors or capacitors, simplifying the configuration. - -## Schematic - -### In Words - -In the schematic for a voltage follower: - -The positive (+) terminal of the op-amp is the non-inverting input. -The negative (−) terminal of the op-amp, the inverting input, is connected directly to the output terminal of the op-amp. -The input voltage is applied to the non-inverting input (+). -The output is taken from the output terminal of the op-amp. - - -### Pseudo Netlist - -An operational amplifier has the following subckt definition: .subckt opamp inverting_input non_inverting_input output v_positive v_negative - -A voltage follower has the following subckt definition: .subckt voltagefollower in out opamp_model X1 in out out opamp_model .endsubckt - -X1 represents the operational amplifier with the in net connected to the non-inverting input, the out net connected to both the inverting input and the output, with opamp_model defining the operational amplifier’s characteristics. - -## Performance Specifications - -Key specifications for a voltage follower include: - -Input Impedance (Z_in): Ideally infinite, which means no current is drawn from the input source.
-Output Impedance (Z_out): Ideally zero, which allows the circuit to drive heavy loads without significant voltage drop.
-Voltage Gain (A_v): Unity (1), meaning the output voltage equals the input voltage without amplification.
-Bandwidth: Broad, often limited only by the op-amp’s characteristics since no reactive components are introduced.
-Slew Rate: This defines the maximum rate at which the output can change and can be a limiting factor in high-frequency applications. - -Voltage followers are widely used in circuits where signal isolation is needed without altering the signal voltage, such as interfacing between high and low impedance circuit blocks or driving capacitive loads without stability issues. \ No newline at end of file diff --git a/openfasoc/generators/glayout/glayout/llm/syntax_data/GlayoutStrictSyntax.md b/openfasoc/generators/glayout/glayout/llm/syntax_data/GlayoutStrictSyntax.md index ecc70ceed..84faf17b8 100644 --- a/openfasoc/generators/glayout/glayout/llm/syntax_data/GlayoutStrictSyntax.md +++ b/openfasoc/generators/glayout/glayout/llm/syntax_data/GlayoutStrictSyntax.md @@ -131,3 +131,4 @@ Where top refers to the inverter’s pmos Component and bottom refers to the inv ## StrictSyntax Style Guide You should always follow this order of commands when creating a Component with strictsyntax: Start by importing any required Components, then create any required parameters, then place all required ComponentRefs with their respective parameters, then move all ComponentRefs to their final positions relative to one another, and lastly route between ComponentRefs. +Do not place components overlapping (always move components if more than one is placed) \ No newline at end of file diff --git a/openfasoc/generators/glayout/glayout/llm/syntax_data/convos/CasecodeCommonGateCommonCentroid.convo b/openfasoc/generators/glayout/glayout/llm/syntax_data/convos/CasecodeCommonGateCommonCentroid.convo new file mode 100644 index 000000000..00425523d --- /dev/null +++ b/openfasoc/generators/glayout/glayout/llm/syntax_data/convos/CasecodeCommonGateCommonCentroid.convo @@ -0,0 +1,6 @@ +CascodeCommonGateCommonCentroid +create a float parameter called width +create a float parameter called length +create a int parameter called fingers +place a common centroid pair called ccg with width=width, length=length, fingers=fingers +route between ccg_A_source_W and ccg_B_drain_W using smart_route diff --git a/openfasoc/generators/glayout/glayout/llm/syntax_data/convos/CurrentMirrorNtypeCommonCentroid.convo b/openfasoc/generators/glayout/glayout/llm/syntax_data/convos/CurrentMirrorNtypeCommonCentroid.convo new file mode 100644 index 000000000..02f609106 --- /dev/null +++ b/openfasoc/generators/glayout/glayout/llm/syntax_data/convos/CurrentMirrorNtypeCommonCentroid.convo @@ -0,0 +1,8 @@ +CurrentMirrorNtypeCommonCentroid +create a float parameter called width +create a float parameter called length +create a int parameter called fingers +place a common centroid pair called cmirror with width=width, length=length, fingers=fingers +route between cmirror_A_source_E and cmirror_B_source_E +route between cmirror_A_drain_E and cmirror_B_gate_E +route between cmirror_A_gate_E and cmirror_B_gate_E \ No newline at end of file diff --git a/openfasoc/generators/glayout/glayout/llm/syntax_data/convos/PTypeDiffPair.convo b/openfasoc/generators/glayout/glayout/llm/syntax_data/convos/PTypeDiffPair.convo index c4e17de0b..c007a4349 100644 --- a/openfasoc/generators/glayout/glayout/llm/syntax_data/convos/PTypeDiffPair.convo +++ b/openfasoc/generators/glayout/glayout/llm/syntax_data/convos/PTypeDiffPair.convo @@ -10,4 +10,4 @@ create a int parameter called vin2_fingers place a pmos called vin1 with width=vin1_width, length=vin1_length, fingers=vin1_fingers, rmult=1, multipliers=vin1_multiplier, with_substrate_tap=False, with_tie=True, with_dummy=True place a pmos called vin2 with width=vin2_width, length=vin2_length, fingers=vin2_fingers, rmult=1, multipliers=vin2_multiplier, with_substrate_tap=False, with_tie=True, with_dummy=True move vin1 to the left of vin2 -route between vin1_source_N and vin2_source_N using smart_route \ No newline at end of file +route between vin1_source_E and vin2_source_W using smart_route \ No newline at end of file diff --git a/openfasoc/generators/glayout/glayout/llm/syntax_data/eval.json b/openfasoc/generators/glayout/glayout/llm/syntax_data/eval.json index 93dcba856..a9915e62b 100644 --- a/openfasoc/generators/glayout/glayout/llm/syntax_data/eval.json +++ b/openfasoc/generators/glayout/glayout/llm/syntax_data/eval.json @@ -18,7 +18,7 @@ }, { "NLPfilename": "IntegratorStage.convo", - "LLMprompt": "Create an integrator stage. This can be made with two pairs of pfets and a pair of nfets. The first pair of pfets is a current mirror that is connected to a pfet diff pair. This is then connected to an active load. These components are arranged top to bottom respectively. Parametrize everything" + "LLMprompt": "Create an integrator stage. This can be made with two pairs of pfets and a pair of nfets. The first pair of pfets is a current mirror that is connected to a pfet diff pair. This is then connected to an active load. Parametrize everything" }, { "NLPfilename": "DeltaSigmaModulator", @@ -28,6 +28,5 @@ "NLPfilename": "NtypeCurrentMirror", "LLMprompt": "Make a current mirror using common centroid technique." } - ] } \ No newline at end of file diff --git a/openfasoc/generators/glayout/glayout/llm/syntax_data/rephrase_train.json b/openfasoc/generators/glayout/glayout/llm/syntax_data/rephrase_train.json index 17d59a2f6..0f7343043 100644 --- a/openfasoc/generators/glayout/glayout/llm/syntax_data/rephrase_train.json +++ b/openfasoc/generators/glayout/glayout/llm/syntax_data/rephrase_train.json @@ -2,103 +2,143 @@ "data": [ { "NLPfilename": "BiasVoltageGenerator", - "LLMprompt": "A generic BiasVoltageGenerator includes a source pmos and a load nmos. Position the load below the source. Connect the drains of both transistors and the load gate. Link the source gate to the load source." + "LLMprompt": "Design a BiasVoltageGenerator with a source PMOS and a load NMOS. Position the load below the source. Short the drains of both transistors and the load gate. Connect the source gate and load source." }, { "NLPfilename": "CrossCoupledInverters", - "LLMprompt": "Cross-coupled inverters consist of two inverters where the output of one serves as the input for the other. Use the interdigitated placement macro to match the pfet and nfet of both inverters." + "LLMprompt": "Cross-coupled inverters consist of two inverters, where the output of one is the input of the other. Use interdigitated placement to match the PFET and NFET of both inverters." }, { "NLPfilename": "DiffPair", - "LLMprompt": "Design an nfet differential pair by placing two nfets side by side and routing their sources, without employing any matching techniques." + "LLMprompt": "Create an NFET differential pair without using any matching techniques. Place two NFETs side by side and connect their sources." }, { "NLPfilename": "SourceFollow", - "LLMprompt": "Create an n-type source follower with the amplifier named srcfoll and the load named isrc. Position the load below the amplifier and route the load source to the amplifier drain. Avoid using any matching techniques." + "LLMprompt": "Design an N-type source follower with the amplifier named 'srcfoll' and the load named 'isrc'. Place the load below the amplifier and route the load source to the amplifier drain without using any matching techniques." }, { "NLPfilename": "CascodeCommonGate", - "LLMprompt": "A cascode common gate stage involves two nfets: an input nfet and an output nfet. Connect the source of the input to the drain of the output. Position the output above the input without using any matching techniques." + "LLMprompt": "Design a cascode common gate stage with two NFETs: an input NFET and an output NFET. Connect the source of the input to the drain of the output. Place the output above the input and parametrize everything without using any matching techniques." }, { "NLPfilename": "CTATVGen", - "LLMprompt": "A CTAT (complementary to absolute temperature) voltage generator includes a pair of nmos transistors: a source and a load. Connect the drain of the source to the load's source. Avoid matching techniques and place the source above the load." + "LLMprompt": "Design a CTAT voltage generator with a pair of NMOS transistors: one source and one load. Connect the drain of the source to the source of the load. Place the source above the load and parametrize everything without using any matching techniques." }, { "NLPfilename": "Inverter", - "LLMprompt": "An inverter comprises a pmos for pull-up and an nmos for pull-down, with their drains forming the output node and their gates forming the input node. Typically, the pfet is placed above the nfet." + "LLMprompt": "Design an inverter with a PMOS for pull-up and an NMOS for pull-down. Connect their drains to form the output node and their gates to form the input node. Place the PFET above the NFET and parametrize everything." }, { "NLPfilename": "CascodeCommonSource", - "LLMprompt": "A cascode common source configuration includes an input nmos and a bias nfet stacked above each other, with the input at the bottom. Connect the bias source to the input drain." + "LLMprompt": "Design a cascode common source stage with an input NMOS and a bias NFET stacked above each other, with the input at the bottom. Connect the bias source to the input drain and parametrize everything." }, { "NLPfilename": "CurrentMirrorNtype", - "LLMprompt": "An n-type current mirror consists of two nmos transistors: a reference and a mirror. Place them side by side, connecting their gates and sources together. Connect the drain and gate of the mirror transistor. Do not use special placement techniques." + "LLMprompt": "Design an N-type current mirror with two NMOS transistors: a reference and a mirror. Place them side by side, connecting the gates and sources together. Connect the drain and gate of the mirror transistor. Parametrize everything without using special placement techniques." }, { "NLPfilename": "LowNoiseAmp", - "LLMprompt": "A low noise amplifier configuration includes two nfets: one for input and one for gain. The gain source and input gate form the input node, while the input source and gain drain form the output node." + "LLMprompt": "Design a low noise amplifier with two NFETs: one for input and one for gain. Connect the gain source and input gate to form the input node, and the input source and gain drain to form the output node without using any special placement strategies." }, { "NLPfilename": "ULPD", - "LLMprompt": "An ultra low power diode is constructed using two nfet transistors: one named forward and the other named leakagered. Place the forward transistor on top. Connect the gate to the source for both transistors without any matching." + "LLMprompt": "Design an ultra low power diode with two NFET transistors: one named 'forward' and the other 'leakagered'. Place 'forward' on top and route the gate to the source of both transistors without using any matching techniques." }, { "NLPfilename": "ClassBPushPull", - "LLMprompt": "Design a class B push-pull amplifier with an nfet named supply and a pfet named absorb. Connect the sources together and the gates together, without using matching techniques." + "LLMprompt": "Design a class B push-pull amplifier with an NFET named 'supply' and a PFET named 'absorb'. Parametrize everything, route the sources together, and route the gates together without using any matching techniques." }, { "NLPfilename": "CurrentMirrorNtypeInterdigitated", - "LLMprompt": "Use interdigitated matching to create an n-type current mirror. Parametrize the width, length, and number of fingers." + "LLMprompt": "Design an N-type current mirror using interdigitated placement. Parametrize width, length, and fingers." }, { "NLPfilename": "NAND", - "LLMprompt": "A NAND gate is a digital circuit with two pull-up and two pull-down transistors. The pull-up transistors are in parallel, and the pull-down transistors are in series. Place the pull-up network above the pull-down network without using matching techniques." + "LLMprompt": "Design a NAND gate with two pull-up and two pull-down transistors. Place the pull-up transistors in parallel and the pull-down transistors in series. Place the pull-up network above the pull-down network without using any matching techniques." }, { "NLPfilename": "Varactor", - "LLMprompt": "Varactors are variable capacitors. To create one, place two nmos transistors named control and accumulation. Connect their sources together and their drains together. Connect the control source to the accumulation drain." + "LLMprompt": "Design a varactor with two NMOS transistors named 'control' and 'accumulation'. Short the sources and drains, and connect the control source to the accumulation drain." }, { "NLPfilename": "CommonSourceAmplifier", - "LLMprompt": "A common source amplifier includes an input nmos and a bias pmos, with the input at the bottom. Route the input drain to the bias source." + "LLMprompt": "Design a common source amplifier with an input NMOS and a bias PMOS. Place the input at the bottom and route the input drain to the bias source." }, { "NLPfilename": "CurrentMirrorPtype", - "LLMprompt": "Create a current mirror using pmos transistors. Avoid matching techniques. Parametrize all components." + "LLMprompt": "Design a current mirror using PMOS transistors. Parametrize everything without using any matching techniques." }, { "NLPfilename": "NoiseXDiffConv", - "LLMprompt": "A NoiseXDiffConv circuit consists of two nfet transistors placed one above the other, with the gate of one connected to the drain of the other." + "LLMprompt": "Design a NoiseXDiffConv circuit with two NFET transistors, one below the other, with the gate of one connected to the drain of the other." }, { "NLPfilename": "VoltageFollower", - "LLMprompt": "A voltage follower includes a transconductance enhancement nfet (tet) and a gate-source capacitance nfet (gsc). Connect the source of tet to the drain of gsc and the drain of tet to the gate of gsc without using special placement strategies." + "LLMprompt": "Design a voltage follower with a transconductance enhancement NFET (tet) and a gate-source capacitance NFET (gsc). Route the source of tet to the drain of gsc and the drain of tet to the gate of gsc without using special placement strategies." }, { "NLPfilename": "CommonSourceAmplifierFoldedDiodeLoad", - "LLMprompt": "A common source amplifier with a folded diode load uses nfet transistors, where the bias transistor is replaced with a diode-connected transistor. Route the gate and drain of the diode and short the drains and sources without special placement techniques." + "LLMprompt": "Design a common source amplifier with a folded diode load using NFET transistors. Replace the bias transistor with a diode-connected transistor. Route the gate and drain of the diode and short the drains and sources without using special placement techniques." }, { "NLPfilename": "CurrentMirrorPtypeInterdigitated", - "LLMprompt": "Use interdigitated matching to create a p-type current mirror. Parametrize the width, length, and number of fingers." + "LLMprompt": "Design a P-type current mirror using interdigitated matching. Parametrize width, length, and fingers." }, { "NLPfilename": "NOR", - "LLMprompt": "A NOR gate is a digital circuit with two pull-up and two pull-down transistors. The pull-up transistors are in series, and the pull-down transistors are in parallel. Place the pull-up network above the pull-down network without using matching techniques." + "LLMprompt": "Design a NOR gate with two pull-up and two pull-down transistors. Place the pull-up transistors in series and the pull-down transistors in parallel. Place the pull-up network above the pull-down network without using any matching techniques." }, { "NLPfilename": "CommonSourceAmplifierWDiodeLoad", - "LLMprompt": "A high-speed common source amplifier with a diode load is called a wideband amplifier. Short the source of the input transistor and the diode drain, as well as the diode gate and diode drain." + "LLMprompt": "Design a high-speed common source amplifier with a diode load using NFET transistors. Short the source of the input transistor and the diode drain, and also short the diode gate and drain." }, { "NLPfilename": "DegenCommonGate", - "LLMprompt": "Create a degen common gate using two nfets: one named isrc and the other named load. Short the load drain and isrc source." + "LLMprompt": "Design a degenerated common gate stage with two NFETs named 'isrc' and 'load'. Short the load drain and isrc source." }, { "NLPfilename": "PTATVoltageGen", - "LLMprompt": "A PTAT (proportional to absolute temperature) voltage generator includes a mirror nmos and a bias nmos. Place the bias below the mirror, short the gates, and route the mirror gate to its drain and the source of the mirror to the bias drain." + "LLMprompt": "Design a PTAT voltage generator with a mirror NMOS and a bias NMOS. Place the bias below the mirror and short the gates. Route the gate of the mirror to its drain and the source of the mirror to the drain of the bias." + }, + { + "NLPfilename": "ConstBiasVoltageGen", + "LLMprompt": "Design a bias voltage generator using two N-type transistors with different threshold voltages. Connect the source of the first transistor (source) to the drain of the second transistor (load), and connect the load gate to its drain. Connect the gate of the source to the source of the load. Parametrize everything without using any matching techniques." + }, + { + "NLPfilename": "DegenCommonSource", + "LLMprompt": "Design a degenerated common source stage with two NFETs named 'isrc' and 'degen'. Connect the source of 'isrc' to the drain of 'degen' and short the gates of both transistors. Parametrize everything without using any matching techniques." + }, + { + "NLPfilename": "RegulatedCascode", + "LLMprompt": "Design a regulated cascode with two NMOS transistors named 'cascode' and 'feedback'. Connect the gate of 'cascode' to the drain of 'feedback' and the gate of 'feedback' to the source of 'cascode'. Parametrize everything without using any matching techniques." + }, + { + "NLPfilename": "ClassBPushPullInterdigitated", + "LLMprompt": "Design an interdigitated class B push-pull amplifier. Parametrize the width, length, and fingers." + }, + { + "NLPfilename": "CascodeCommonGateInterdigitated", + "LLMprompt": "Design an interdigitated cascode common gate stage. Parametrize the width, length, and fingers." + }, + { + "NLPfilename": "CascodeCommonSourceInterdigitated", + "LLMprompt": "Design an interdigitated cascode common source stage with an input NMOS and a bias NFET. Connect the bias source to the input drain and parametrize everything." + }, + { + "NLPfilename": "ClassBPushPullInterdigitated", + "LLMprompt": "Design an interdigitated class B push-pull amplifier. Place an NFET named 'supply' and a PFET named 'absorb'. Parametrize everything, route the sources together, and route the gates together." + }, + { + "NLPfilename": "CascodeCommonGateInterdigitated", + "LLMprompt": "Design an interdigitated cascode common gate stage with two NFETs: an input NFET and an output NFET. Connect the source of the input to the drain of the output. Parametrize everything and match the transistors through interdigitation." + }, + { + "NLPfilename": "CascodeCommonSourceInterdigitated", + "LLMprompt": "Design an interdigitated cascode common source stage with an input NMOS and a bias NFET. Connect the bias source to the input drain and parametrize everything." + }, + { + "NLPfilename": "CascodeCommonGateCommonCentroid", + "LLMprompt": "Design a cascode common gate stage with two NFETs: an input NFET and an output NFET. Connect the source of the input to the drain of the output. Parametrize everything and match the transistors using common centroid placement." } ] } diff --git a/openfasoc/generators/glayout/glayout/llm/syntax_data/train.json b/openfasoc/generators/glayout/glayout/llm/syntax_data/train.json index e6595714c..bc2b9602c 100644 --- a/openfasoc/generators/glayout/glayout/llm/syntax_data/train.json +++ b/openfasoc/generators/glayout/glayout/llm/syntax_data/train.json @@ -2,7 +2,7 @@ "data": [ { "NLPfilename": "BiasVoltageGenerator", - "LLMprompt": "A generic BiasVoltageGenerator contains a src pmos and a load nmos. The load should be below the src. The drains of both transistors and load gate should be shorted. Connect the src gate and load source. " + "LLMprompt": "A generic BiasVoltageGenerator contains a src pmos and a load nmos. The load should be below the src. The drains of both transistors and load gate should be shorted. Connect the src gate and load source." }, { "NLPfilename": "CrossCoupledInverters", @@ -50,7 +50,7 @@ }, { "NLPfilename": "CurrentMirrorNtypeInterdigitated", - "LLMprompt": "Use interdigitized matching to create an n-type current mirror. Parametrize width, length, and fingers." + "LLMprompt": "Use interdigitized placement matching to create an n-type current mirror. Parametrize width, length, and fingers." }, { "NLPfilename": "NAND", @@ -130,11 +130,15 @@ }, { "NLPfilename": "CascodeCommonGateInterdigitated", - "LLMprompt": "A cascode common gate stage consists of 2 nfets, an input nfet and output nfet. The source of the input and drain of the output are connected. Do not use any matching techniques, just place the output above the input. Parametrize everything. The transistors should be matched through interdigitation." + "LLMprompt": "A cascode common gate stage consists of 2 nfets, an input nfet and output nfet. The source of the input and drain of the output are connected. Parametrize everything. The transistors should be matched through interdigitation." }, { "NLPfilename": "CascodeCommonSourceInterdigitated", - "LLMprompt": "A cascode common source consists of an input nmos and bias nfet, both of which are interdigitated. The bias source is connected to the input drain. parametrize everything." + "LLMprompt": "A cascode common source consists of an input nmos and bias nfet. both of which are interdigitated. The bias source is connected to the input drain. parametrize everything." + }, + { + "NLPfilename": "CascodeCommonGateCommonCentroid", + "LLMprompt": "A cascode common gate stage consists of 2 nfets, an input nfet and output nfet. The source of the input and drain of the output are connected. Parametrize everything. The transistors should be matched using common centroid placement." } ] } diff --git a/openfasoc/generators/glayout/glayout/llm/train_and_run.py b/openfasoc/generators/glayout/glayout/llm/train_and_run.py index f2ac20c69..9da7b736b 100644 --- a/openfasoc/generators/glayout/glayout/llm/train_and_run.py +++ b/openfasoc/generators/glayout/glayout/llm/train_and_run.py @@ -85,8 +85,11 @@ def load_model_and_tokenizer(device: str, lora: bool = True) -> tuple: """ qlora = True # load model - modelname = "microsoft/Phi-3-mini-128k-instruct" - #modelname = "mistralai/Codestral-22B-v0.1" + # when use codestral on 80GB GPU, you may need to set the following in your env + # PYTORCH_CUDA_ALLOC_CONF=garbage_collection_threshold:0.6,max_split_size_mb:128 + # reduce epochs to 2 + #modelname = "microsoft/Phi-3-mini-128k-instruct" + modelname = "mistralai/Codestral-22B-v0.1" #modelname = "mistralai/Mistral-7B-Instruct-v0.3" global microsoft_model global mistral_model @@ -117,7 +120,7 @@ def load_model_and_tokenizer(device: str, lora: bool = True) -> tuple: lora_alpha=16, lora_dropout=0.05, bias="none", - target_modules=["q_proj", "k_proj", "v_proj", "o_proj"], + target_modules=["q_proj", "k_proj", "v_proj"], ) model = get_peft_model(model, peft_config) model.print_trainable_parameters() @@ -227,9 +230,9 @@ def run_full_SFT_training() -> tuple: # hyperparameters lr = 5e-5 batch_size = 1 # 2 #4 - num_epochs = 4 + num_epochs = 2 # define training arguments - output_dir = Path(__file__).resolve().parent / "glayout_llm_checkpoints" + output_dir = Path(__file__).resolve().parent / ("glayout_llm_checkpoints" + ("phi" if microsoft_model else "mstrl")) training_args = TrainingArguments( output_dir=str(output_dir), learning_rate=lr, @@ -247,7 +250,7 @@ def run_full_SFT_training() -> tuple: gradient_accumulation_steps=1, warmup_steps=1, bf16=True, - optim="paged_adamw_8bit", + optim="paged_adamw_8bit" ) #training_args = TrainingArguments(output_dir=str(output_dir)) if microsoft_model: diff --git a/openfasoc/generators/glayout/glayout/syntaxer/relational.py b/openfasoc/generators/glayout/glayout/syntaxer/relational.py index 35e190163..e31e6265e 100644 --- a/openfasoc/generators/glayout/glayout/syntaxer/relational.py +++ b/openfasoc/generators/glayout/glayout/syntaxer/relational.py @@ -715,6 +715,7 @@ def __init__(self, toplvl_name: str): self.update_import_table(generic_4T_interdigitzed_aliases, "generic_4T_interdigitzed", "glayout.flow.placement.four_transistor_interdigitized") two_pfet_interdigitized_aliases = list_cartesian_product(["interdigitized","interdigitated"],["pmos","pfet"],True) self.update_import_table(two_pfet_interdigitized_aliases,"two_pfet_interdigitized","glayout.flow.placement.two_transistor_interdigitized") + self.update_import_table(["common centroid"],"common_centroid_ab_ba","glayout.flow.placement.common_centroid_ab_ba") self.update_import_table(["diff pair","diff_pair","differential pair","differential pairs","differential transistor"],"diff_pair_generic","glayout.flow.blocks.diff_pair") # import routing funcs self.update_import_table(["smart route","smart","smart_route"],"smart_route","glayout.flow.routing.smart_route")