From 00b9cb2507059b4eabed60b72dc88172ea1acc3a Mon Sep 17 00:00:00 2001 From: Andrew Tridgell Date: Thu, 25 Jul 2024 20:36:42 +1000 Subject: [PATCH 01/11] build: reduce the number of places we list the MCU types this is a step towards removing the recursive make, and making it easier to add new MCUs --- Makefile | 94 +++++++++++++++++++++----------------------------------- 1 file changed, 35 insertions(+), 59 deletions(-) diff --git a/Makefile b/Makefile index b85da3563..4f7308634 100644 --- a/Makefile +++ b/Makefile @@ -22,17 +22,15 @@ ROOT := $(patsubst %/,%,$(dir $(lastword $(MAKEFILE_LIST)))) # include the rules for OS independence include $(ROOT)/make/tools.mk -# Include processor specific makefiles -include f051makefile.mk -include g071makefile.mk -include f031makefile.mk -include f421makefile.mk -include e230makefile.mk -include f415makefile.mk -include gd32makefile.mk - -# Default MCU type to F051 -MCU_TYPE ?= F051 +# supported MCU types +MCU_TYPES := E230 F031 F051 F415 F421 G071 +MCU_TYPE := NONE + +# Function to include makefile for each MCU type +define INCLUDE_MCU_MAKEFILES +$(foreach MCU_TYPE,$(MCU_TYPES),$(eval include $(call lc,$(MCU_TYPE))makefile.mk)) +endef +$(call INCLUDE_MCU_MAKEFILES) # additional libs LIBS := -lnosys @@ -44,9 +42,11 @@ VERSION_MINOR := $(shell $(FGREP) "define VERSION_MINOR" $(MAIN_INC_DIR)/version FIRMWARE_VERSION := $(VERSION_MAJOR).$(VERSION_MINOR) # Compiler options -CFLAGS_COMMON := -DUSE_MAKE -fsingle-precision-constant -fomit-frame-pointer -ffast-math -CFLAGS_COMMON += -I$(MAIN_INC_DIR) -g -O3 -Wall -ffunction-sections -CFLAGS_COMMON += -D$(TARGET) + +CFLAGS_BASE := -DUSE_MAKE -fsingle-precision-constant -fomit-frame-pointer -ffast-math +CFLAGS_BASE += -I$(MAIN_INC_DIR) -g -O3 -Wall -ffunction-sections + +CFLAGS_COMMON := $(CFLAGS_BASE) -D$(TARGET) # Linker options LDFLAGS_COMMON := -specs=nano.specs $(LIBS) -Wl,--gc-sections -Wl,--print-memory-usage @@ -61,25 +61,20 @@ TARGET_BASENAME = $(BIN_DIR)/$(TARGET_FNAME) OBJ := obj BIN_DIR := $(ROOT)/$(OBJ) -TOOLS_DIR ?= $(ROOT)/tools -DL_DIR := $(ROOT)/downloads - -.PHONY : clean all binary f051 g071 f031 e230 f421 f415 -ALL_TARGETS := $(TARGETS_F051) $(TARGETS_G071) $(TARGETS_F031) $(TARGETS_E230) $(TARGETS_F421) $(TARGETS_F415) +.PHONY : clean all binary $(foreach MCU,$(MCU_TYPES),$(call lc,$(MCU))) +ALL_TARGETS := $(foreach MCU,$(MCU_TYPES),$(TARGETS_$(MCU))) all : $(ALL_TARGETS) -f051 : $(TARGETS_F051) -g071 : $(TARGETS_G071) -f031 : $(TARGETS_F031) -e230 : $(TARGETS_E230) -f421 : $(TARGETS_F421) -f415 : $(TARGETS_F415) + +# create targets for compiling one mcu type, eg "make f421" +define CREATE_TARGET +$(call lc,$(1)) : $$(TARGETS_$(1)) +endef +$(foreach MCU,$(MCU_TYPES),$(eval $(call CREATE_TARGET,$(MCU)))) clean : @echo Removing $(OBJ) directory @$(RM) -rf $(OBJ) -# lowercase version of MCU_TYPE -MCU_LOWER = $(call lc,$(MCU_TYPE)) binary : $(TARGET_BASENAME).bin # we copy debug.elf to give us a constant debug target for vscode @@ -87,26 +82,16 @@ binary : $(TARGET_BASENAME).bin @$(CP) -f $(OBJ)$(DSEP)$(TARGET_FNAME).elf $(OBJ)$(DSEP)debug.elf > $(NUL) # also copy the openocd.cfg from the MCU directory to obj/openocd.cfg for auto config of Cortex-Debug # in vscode - @$(CP) -f Mcu$(DSEP)$(MCU_LOWER)$(DSEP)openocd.cfg $(OBJ)$(DSEP)openocd.cfg > $(NUL) + @$(CP) -f Mcu$(DSEP)$(call lc,$(MCU_TYPE))$(DSEP)openocd.cfg $(OBJ)$(DSEP)openocd.cfg > $(NUL) @$(ECHO) done $(TARGET) -$(TARGETS_F051) : - @$(MAKE) -s MCU_TYPE=F051 TARGET=$@ binary - -$(TARGETS_G071) : - @$(MAKE) -s MCU_TYPE=G071 TARGET=$@ binary +# create targets compiling each MCU types targets +define CREATE_MCU_TARGETS +$$(TARGETS_$(1)) : + @$$(MAKE) -s MCU_TYPE=$(1) TARGET=$$@ binary +endef +$(foreach MCU,$(MCU_TYPES),$(eval $(call CREATE_MCU_TARGETS,$(MCU)))) -$(TARGETS_F031) : - @$(MAKE) -s MCU_TYPE=F031 TARGET=$@ binary - -$(TARGETS_E230) : - @$(MAKE) -s MCU_TYPE=E230 TARGET=$@ binary - -$(TARGETS_F421) : - @$(MAKE) -s MCU_TYPE=F421 TARGET=$@ binary - -$(TARGETS_F415) : - @$(MAKE) -s MCU_TYPE=F415 TARGET=$@ binary # Compile target $(TARGET_BASENAME).elf: CFLAGS := $(MCU_$(MCU_TYPE)) $(CFLAGS_$(MCU_TYPE)) $(CFLAGS_COMMON) @@ -122,22 +107,13 @@ $(TARGET_BASENAME).bin: $(TARGET_BASENAME).elf $(QUIET)$(OBJCOPY) -O binary $(<) $@ $(QUIET)$(OBJCOPY) $(<) -O ihex $(@:.bin=.hex) -# mkdirs -$(DL_DIR): - $(QUIET)$(MKDIR) -p $@ - -$(TOOLS_DIR): - $(QUIET)$(MKDIR) -p $@ - # include the targets for installing tools include $(ROOT)/make/tools_install.mk +define SHOW_MCU_TARGETS +$(1) Targets $(TARGETS_$(1))\n +endef + targets: - $(QUIET)echo Targets for each MCU. To build a target use 'make TARGETNAME' - $(QUIET)echo F051 Targets: $(TARGETS_F051) - $(QUIET)echo G071 Targets: $(TARGETS_G071) - $(QUIET)echo F031 Targets: $(TARGETS_F031) - $(QUIET)echo E230 Targets: $(TARGETS_E230) - $(QUIET)echo F421 Targets: $(TARGETS_F421) - $(QUIET)echo F415 Targets: $(TARGETS_F415) - $(QUIET)echo GD32 Targets: $(TARGETS_GD32) + $(QUIET)echo List of targets. To build a target use 'make TARGETNAME' + $(QUIET)echo $(ALL_TARGETS) From b567f2887ce7a7655f71e2ceee4d74bdc4890c1d Mon Sep 17 00:00:00 2001 From: Andrew Tridgell Date: Fri, 26 Jul 2024 15:24:27 +1000 Subject: [PATCH 02/11] remove stray file --- f051_ll_bi_dir Debug.launch | 73 ------------------------------------- 1 file changed, 73 deletions(-) delete mode 100644 f051_ll_bi_dir Debug.launch diff --git a/f051_ll_bi_dir Debug.launch b/f051_ll_bi_dir Debug.launch deleted file mode 100644 index df14d08fb..000000000 --- a/f051_ll_bi_dir Debug.launch +++ /dev/null @@ -1,73 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - From 9e4c92512dc335b19ba76625e0456e8d5c39e3bb Mon Sep 17 00:00:00 2001 From: Andrew Tridgell Date: Fri, 26 Jul 2024 15:24:44 +1000 Subject: [PATCH 03/11] remove stray linker file --- STM32F051K6TX_FLASH.ld | 187 ----------------------------------------- 1 file changed, 187 deletions(-) delete mode 100644 STM32F051K6TX_FLASH.ld diff --git a/STM32F051K6TX_FLASH.ld b/STM32F051K6TX_FLASH.ld deleted file mode 100644 index 15d654b01..000000000 --- a/STM32F051K6TX_FLASH.ld +++ /dev/null @@ -1,187 +0,0 @@ -/** - ****************************************************************************** - * @file LinkerScript.ld - * @author Auto-generated by STM32CubeIDE - * @brief Linker script for STM32F051K6Tx Device from STM32F0 series - * 32Kbytes FLASH - * 8Kbytes RAM - * - * Set heap size, stack size and stack location according - * to application requirements. - * - * Set memory bank area and size if external memory is used - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ - -_Min_Heap_Size = 0x200 ; /* required amount of heap */ -_Min_Stack_Size = 0x400 ; /* required amount of stack */ - -/* Memories definition */ - -MEMORY -{ - SRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 192 - RAM (xrw) : ORIGIN = 0x200000C0, LENGTH = 8K - 192 - FLASH_VECTAB (rx) : ORIGIN = 0x08001000, LENGTH = 192 - FLASH_VERSION (rx) : ORIGIN = 0x080010C0, LENGTH = 14 - FLASH (rx) : ORIGIN = ORIGIN(FLASH_VERSION) + LENGTH(FLASH_VERSION), LENGTH = 27K - (LENGTH(FLASH_VECTAB) + LENGTH(FLASH_VERSION)) - EEPROM (rx) : ORIGIN = 0x080007C00, LENGTH = 1K -} - -/* Sections */ -SECTIONS -{ - /* The startup code into "FLASH" Rom type memory */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >FLASH_VECTAB - - /* The firmware version and name - at a fixed address to make it possible to read it from firmware files. */ - .firmware_version : - { - . = ALIGN(4); - KEEP (*(.firmware_info)) - } >FLASH_VERSION - - /* The program code and other data into "FLASH" Rom type memory */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - /* Constant data into "FLASH" Rom type memory */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >FLASH - - .ARM.extab : { - . = ALIGN(4); - *(.ARM.extab* .gnu.linkonce.armextab.*) - . = ALIGN(4); - } >FLASH - - .ARM : { - . = ALIGN(4); - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - . = ALIGN(4); - } >FLASH - - .preinit_array : - { - . = ALIGN(4); - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - . = ALIGN(4); - } >FLASH - - .init_array : - { - . = ALIGN(4); - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(4); - } >FLASH - - .fini_array : - { - . = ALIGN(4); - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - . = ALIGN(4); - } >FLASH - - /* Used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections into "RAM" Ram type memory */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - - } >RAM AT> FLASH - - /* Uninitialized data section into "RAM" Ram type memory */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ - ._user_heap_stack : - { - . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(8); - } >RAM - - /* Remove information from the compiler libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} From 47a79f8861d588e9c0df8ec5eaa72468b770d74b Mon Sep 17 00:00:00 2001 From: Andrew Tridgell Date: Fri, 26 Jul 2024 18:33:54 +1000 Subject: [PATCH 04/11] build: use -g3 so we can debug macros makes no difference to the binary --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 4f7308634..e921b0b7c 100644 --- a/Makefile +++ b/Makefile @@ -44,7 +44,7 @@ FIRMWARE_VERSION := $(VERSION_MAJOR).$(VERSION_MINOR) # Compiler options CFLAGS_BASE := -DUSE_MAKE -fsingle-precision-constant -fomit-frame-pointer -ffast-math -CFLAGS_BASE += -I$(MAIN_INC_DIR) -g -O3 -Wall -ffunction-sections +CFLAGS_BASE += -I$(MAIN_INC_DIR) -g3 -O3 -Wall -ffunction-sections CFLAGS_COMMON := $(CFLAGS_BASE) -D$(TARGET) From 1be526c37edc322b96ea5d21fc2a7e7adccdfbf0 Mon Sep 17 00:00:00 2001 From: Andrew Tridgell Date: Sat, 27 Jul 2024 08:11:48 +1000 Subject: [PATCH 05/11] linker: ensure all sections align to 4 bytes --- Mcu/e230/GD32E230K8_FLASH.ld | 4 +++- Mcu/f031/STM32F031C6TX_FLASH.ld | 4 +++- Mcu/f051/STM32F051K6TX_FLASH.ld | 4 +++- Mcu/f415/AT32F415x8_FLASH.ld | 4 +++- Mcu/f421/AT32F421x6_FLASH.ld | 4 +++- Mcu/g071/STM32G071GBUX_FLASH.ld | 4 +++- 6 files changed, 18 insertions(+), 6 deletions(-) diff --git a/Mcu/e230/GD32E230K8_FLASH.ld b/Mcu/e230/GD32E230K8_FLASH.ld index 6ec5ad32f..dbc25809c 100644 --- a/Mcu/e230/GD32E230K8_FLASH.ld +++ b/Mcu/e230/GD32E230K8_FLASH.ld @@ -12,7 +12,7 @@ _Min_Stack_Size = 0x400; /* required amount of stack */ MEMORY { FLASH (rx) : ORIGIN = 0x08001000, LENGTH = 27K -FLASH_VERSION (rx) : ORIGIN = 0x08007C00 - 48, LENGTH = 14 +FLASH_VERSION (rx) : ORIGIN = 0x08007C00 - 48, LENGTH = 16 FILE_NAME (rx) : ORIGIN = 0x08007C00 - 32, LENGTH = 32 EEPROM (rx) : ORIGIN = 0x08007C00, LENGTH = 1K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 16K @@ -88,6 +88,7 @@ SECTIONS { . = ALIGN(4); KEEP (*(.firmware_info)) + . = ALIGN(4); } >FLASH_VERSION /* The file name */ @@ -95,6 +96,7 @@ SECTIONS { . = ALIGN(4); KEEP (*(.file_name)) + . = ALIGN(4); } >FILE_NAME diff --git a/Mcu/f031/STM32F031C6TX_FLASH.ld b/Mcu/f031/STM32F031C6TX_FLASH.ld index 6031fc975..340cc4472 100644 --- a/Mcu/f031/STM32F031C6TX_FLASH.ld +++ b/Mcu/f031/STM32F031C6TX_FLASH.ld @@ -39,7 +39,7 @@ MEMORY SRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 192 RAM (xrw) : ORIGIN = 0x200000C0, LENGTH = 4K - 192 FLASH_VECTAB (rx) : ORIGIN = 0x08001000, LENGTH = 192 - FLASH_VERSION (rx) : ORIGIN = 0x080010C0, LENGTH = 14 + FLASH_VERSION (rx) : ORIGIN = 0x080010C0, LENGTH = 16 FLASH (rx) : ORIGIN = ORIGIN(FLASH_VERSION) + LENGTH(FLASH_VERSION), LENGTH = 27K - 32 -(LENGTH(FLASH_VECTAB) + LENGTH(FLASH_VERSION)) FILE_NAME (rx) : ORIGIN = 0x08007C00 - 32, LENGTH = 32 EEPROM (rx) : ORIGIN = 0x080007C00, LENGTH = 1K @@ -62,6 +62,7 @@ SECTIONS { . = ALIGN(4); KEEP (*(.firmware_info)) + . = ALIGN(4); } >FLASH_VERSION @@ -140,6 +141,7 @@ SECTIONS { . = ALIGN(4); KEEP (*(.file_name)) + . = ALIGN(4); } >FILE_NAME /* Used by the startup to initialize data */ diff --git a/Mcu/f051/STM32F051K6TX_FLASH.ld b/Mcu/f051/STM32F051K6TX_FLASH.ld index 7f6900380..fb4daf342 100644 --- a/Mcu/f051/STM32F051K6TX_FLASH.ld +++ b/Mcu/f051/STM32F051K6TX_FLASH.ld @@ -40,7 +40,7 @@ MEMORY SRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 192 RAM (xrw) : ORIGIN = 0x200000C0, LENGTH = 8K - 192 FLASH_VECTAB (rx) : ORIGIN = 0x08001000, LENGTH = 192 - FLASH_VERSION (rx) : ORIGIN = 0x080010C0, LENGTH = 14 + FLASH_VERSION (rx) : ORIGIN = 0x080010C0, LENGTH = 16 FLASH (rx) : ORIGIN = ORIGIN(FLASH_VERSION) + LENGTH(FLASH_VERSION), LENGTH = 27K - 32 - (LENGTH(FLASH_VECTAB) + LENGTH(FLASH_VERSION)) FILE_NAME (rx) : ORIGIN = 0x08007C00 - 32, LENGTH = 32 EEPROM (rx) : ORIGIN = 0x08007C00, LENGTH = 1K @@ -62,6 +62,7 @@ SECTIONS { . = ALIGN(4); KEEP (*(.firmware_info)) + . = ALIGN(4); } >FLASH_VERSION /* The program code and other data into "FLASH" Rom type memory */ @@ -136,6 +137,7 @@ SECTIONS { . = ALIGN(4); KEEP (*(.file_name)) + . = ALIGN(4); } >FILE_NAME diff --git a/Mcu/f415/AT32F415x8_FLASH.ld b/Mcu/f415/AT32F415x8_FLASH.ld index c2cb55c4f..6dabc92e4 100644 --- a/Mcu/f415/AT32F415x8_FLASH.ld +++ b/Mcu/f415/AT32F415x8_FLASH.ld @@ -32,7 +32,7 @@ _Min_Stack_Size = 0x400; /* required amount of stack */ MEMORY { FLASH (rx) : ORIGIN = 0x08001000, LENGTH = 27K -FLASH_VERSION (rx) : ORIGIN = 0x08007C00 - 48, LENGTH = 14 +FLASH_VERSION (rx) : ORIGIN = 0x08007C00 - 48, LENGTH = 16 FILE_NAME (rx) : ORIGIN = 0x08007C00 - 32, LENGTH = 32 EEPROM (rx) : ORIGIN = 0x08007C00, LENGTH = 1K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K @@ -107,6 +107,7 @@ SECTIONS { . = ALIGN(4); KEEP (*(.firmware_info)) + . = ALIGN(4); } >FLASH_VERSION @@ -115,6 +116,7 @@ SECTIONS { . = ALIGN(4); KEEP (*(.file_name)) + . = ALIGN(4); } >FILE_NAME /* used by the startup to initialize data */ diff --git a/Mcu/f421/AT32F421x6_FLASH.ld b/Mcu/f421/AT32F421x6_FLASH.ld index f8c07c8d6..cd4f2433b 100644 --- a/Mcu/f421/AT32F421x6_FLASH.ld +++ b/Mcu/f421/AT32F421x6_FLASH.ld @@ -31,7 +31,7 @@ _Min_Stack_Size = 0x400; /* required amount of stack */ MEMORY { FLASH (rx) : ORIGIN = 0x08001000, LENGTH = 27K -FLASH_VERSION (rx) : ORIGIN = 0x08007C00 - 48, LENGTH = 14 +FLASH_VERSION (rx) : ORIGIN = 0x08007C00 - 48, LENGTH = 16 FILE_NAME (rx) : ORIGIN = 0x08007C00 - 32, LENGTH = 32 EEPROM (rx) : ORIGIN = 0x08007C00, LENGTH = 1K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 16K @@ -107,6 +107,7 @@ SECTIONS { . = ALIGN(4); KEEP (*(.firmware_info)) + . = ALIGN(4); } >FLASH_VERSION /* The file name */ @@ -114,6 +115,7 @@ SECTIONS { . = ALIGN(4); KEEP (*(.file_name)) + . = ALIGN(4); } >FILE_NAME diff --git a/Mcu/g071/STM32G071GBUX_FLASH.ld b/Mcu/g071/STM32G071GBUX_FLASH.ld index a995fdf23..e4ab7737b 100644 --- a/Mcu/g071/STM32G071GBUX_FLASH.ld +++ b/Mcu/g071/STM32G071GBUX_FLASH.ld @@ -41,7 +41,7 @@ MEMORY { RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 36K FLASH_VECTAB (rx) : ORIGIN = 0x08001000, LENGTH = 192 - FLASH_VERSION (rx) : ORIGIN = 0x080010C0, LENGTH = 14 + FLASH_VERSION (rx) : ORIGIN = 0x080010C0, LENGTH = 16 FLASH (rx) : ORIGIN = ORIGIN(FLASH_VERSION) + LENGTH(FLASH_VERSION), LENGTH = 62K - 32 - (LENGTH(FLASH_VECTAB) + LENGTH(FLASH_VERSION)) FILE_NAME (rx) : ORIGIN = 0x0800F800 - 32, LENGTH = 32 EEPROM (rx) : ORIGIN = 0x0800F800, LENGTH = 2K @@ -63,6 +63,7 @@ SECTIONS { . = ALIGN(4); KEEP (*(.firmware_info)) + . = ALIGN(4); } >FLASH_VERSION /* The program code and other data into "FLASH" Rom type memory */ @@ -139,6 +140,7 @@ SECTIONS { . = ALIGN(4); KEEP (*(.file_name)) + . = ALIGN(4); } >FILE_NAME /* Used by the startup to initialize data */ From a473b63f4e7cdd56ef94f88037517437175d2539 Mon Sep 17 00:00:00 2001 From: Andrew Tridgell Date: Fri, 26 Jul 2024 15:25:05 +1000 Subject: [PATCH 06/11] moved to common bootloader in bootloader/*.c all bootloaders built from common source, using blutil.h for MCU specific functions and macros --- Inc/version.h | 3 + Makefile | 52 +++ Mcu/e230/Inc/blutil.h | 91 ++++++ Mcu/f031/Inc/blutil.h | 152 +++++++++ Mcu/f051/Inc/blutil.h | 152 +++++++++ Mcu/f051/Inc/flash.h | 2 + Mcu/f415/Inc/blutil.h | 191 +++++++++++ Mcu/f415/Src/eeprom.c | 2 +- Mcu/f421/Inc/blutil.h | 124 ++++++++ Mcu/f421/Src/at32f421_it.c | 10 + Mcu/g071/Inc/blutil.h | 153 +++++++++ bootloader/ldscript_bl.ld | 135 ++++++++ bootloader/main.c | 628 +++++++++++++++++++++++++++++++++++++ e230makefile.mk | 44 +-- f031makefile.mk | 42 ++- f051makefile.mk | 42 ++- f415makefile.mk | 42 ++- f421makefile.mk | 42 ++- g071makefile.mk | 42 ++- 19 files changed, 1848 insertions(+), 101 deletions(-) create mode 100644 Mcu/e230/Inc/blutil.h create mode 100644 Mcu/f031/Inc/blutil.h create mode 100644 Mcu/f051/Inc/blutil.h create mode 100644 Mcu/f051/Inc/flash.h create mode 100644 Mcu/f415/Inc/blutil.h create mode 100644 Mcu/f421/Inc/blutil.h create mode 100644 Mcu/g071/Inc/blutil.h create mode 100644 bootloader/ldscript_bl.ld create mode 100644 bootloader/main.c diff --git a/Inc/version.h b/Inc/version.h index 19554e016..d18ce9bef 100644 --- a/Inc/version.h +++ b/Inc/version.h @@ -3,3 +3,6 @@ */ #define VERSION_MAJOR 2 #define VERSION_MINOR 16 + +// update this when bootloader build changes +#define BOOTLOADER_VERSION 12 diff --git a/Makefile b/Makefile index e921b0b7c..6ac31e8eb 100644 --- a/Makefile +++ b/Makefile @@ -26,6 +26,10 @@ include $(ROOT)/make/tools.mk MCU_TYPES := E230 F031 F051 F415 F421 G071 MCU_TYPE := NONE +# MCU types that we build a bootloader for - this should be $(MCU_TYPES) in the future +# when all bootloader porting is completed +BL_MCU_TYPES := E230 F031 F051 F415 F421 G071 + # Function to include makefile for each MCU type define INCLUDE_MCU_MAKEFILES $(foreach MCU_TYPE,$(MCU_TYPES),$(eval include $(call lc,$(MCU_TYPE))makefile.mk)) @@ -114,6 +118,54 @@ define SHOW_MCU_TARGETS $(1) Targets $(TARGETS_$(1))\n endef +# bootloader build +BOOTLOADER_VERSION := $(shell $(FGREP) "define BOOTLOADER_VERSION" $(MAIN_INC_DIR)/version.h | $(CUT) -d" " -f3 ) + +# we support bootloader comms on either PB4 or PA2 +BOOTLOADER_PINS = PB4 PA2 + +SRC_BL := $(foreach dir,bootloader,$(wildcard $(dir)/*.[cs])) +LDSCRIPT_BL := bootloader/ldscript_bl.ld + +# bootloader target names for example "make AM32_F421_BOOTLOADER" +define BOOTLOADER_BASENAME +$(IDENTIFIER)_$(1)_BOOTLOADER_$(2) +endef + +# bootloader target names with version for filename +define BOOTLOADER_BASENAME_VER +$(call BOOTLOADER_BASENAME,$(1),$(2)_V$(BOOTLOADER_VERSION)) +endef + +define CREATE_BOOTLOADER_TARGET +$(BIN_DIR)/$(call BOOTLOADER_BASENAME_VER,$(1),$(2)).elf: CFLAGS_BL := $$(MCU_$(1)) $$(CFLAGS_$(1)) $$(CFLAGS_BASE) -DBOOTLOADER -DUSE_$(2) +$(BIN_DIR)/$(call BOOTLOADER_BASENAME_VER,$(1),$(2)).elf: LDFLAGS_BL := $$(LDFLAGS_COMMON) $$(LDFLAGS_$(1)) -T$$(LDSCRIPT_BL) +$(BIN_DIR)/$(call BOOTLOADER_BASENAME_VER,$(1),$(2)).elf: $$(SRC_BL) + $$(QUIET)echo building bootloader for $(1) with pin $(2) + $$(QUIET)$$(MKDIR) -p $(OBJ) + $$(QUIET)echo BUILT $(1) pin $(2) > $$@ + $$(QUIET)echo Compiling $(notdir $$@) + $$(QUIET)$$(CC) $$(CFLAGS_BL) $$(LDFLAGS_BL) -o $$(@) $$(SRC_BL) $$(SRC_$(1)_BL) -Os + $$(QUIET)$$(CP) -f $$@ $$(OBJ)$$(DSEP)debug.elf + $$(QUIET)$$(CP) -f Mcu$(DSEP)$(call lc,$(1))$(DSEP)openocd.cfg $$(OBJ)$$(DSEP)openocd.cfg > $$(NUL) + +# Generate bin and hex files +$(BIN_DIR)/$(call BOOTLOADER_BASENAME_VER,$(1),$(2)).hex: $(BIN_DIR)/$(call BOOTLOADER_BASENAME_VER,$(1),$(2)).elf + $$(QUIET)echo Generating $(notdir $$@) + $$(QUIET)$$(OBJCOPY) -O binary $$(<) $$(@:.hex=.bin) + $$(QUIET)$$(OBJCOPY) $$(<) -O ihex $$(@:.bin=.hex) + +$(call BOOTLOADER_BASENAME,$(1),$(2)): $(BIN_DIR)/$(call BOOTLOADER_BASENAME_VER,$(1),$(2)).hex +endef +$(foreach MCU,$(MCU_TYPES),$(foreach PIN,$(BOOTLOADER_PINS),$(eval $(call CREATE_BOOTLOADER_TARGET,$(MCU),$(PIN))))) + +ALL_BOOTLOADERS := $(foreach MCU,$(BL_MCU_TYPES),$(foreach PIN,$(BOOTLOADER_PINS),$(call BOOTLOADER_BASENAME,$(MCU),$(PIN)))) + +bootloaders: $(ALL_BOOTLOADERS) + +# useful target to list all of the board targets so you can see what +# make target to use for your board targets: $(QUIET)echo List of targets. To build a target use 'make TARGETNAME' $(QUIET)echo $(ALL_TARGETS) + $(QUIET)echo Bootloaders: $(ALL_BOOTLOADERS) diff --git a/Mcu/e230/Inc/blutil.h b/Mcu/e230/Inc/blutil.h new file mode 100644 index 000000000..4dc94b6a2 --- /dev/null +++ b/Mcu/e230/Inc/blutil.h @@ -0,0 +1,91 @@ +/* + MCU specific utility functions for the bootloader + */ +#pragma once + +#define GPIO_PINS_2 GPIO_PIN_2 +#define GPIO_PINS_4 GPIO_PIN_4 + +#define GPIO_PULL_NONE GPIO_PUPD_NONE +#define GPIO_PULL_UP GPIO_PUPD_PULLUP +#define GPIO_PULL_DOWN GPIO_PUPD_PULLDOWN + +#define GPIO_OUTPUT_PUSH_PULL GPIO_OTYPE_PP + +static inline void gpio_mode_set_input(uint32_t pin, uint32_t pull_up_down) +{ + gpio_mode_set(input_port, GPIO_MODE_INPUT, pull_up_down, pin); +} + +static inline void gpio_mode_set_output(uint32_t pin, uint32_t output_mode) +{ + gpio_mode_set(input_port, GPIO_MODE_OUTPUT, output_mode, pin); +} + +static inline void gpio_set(uint32_t pin) +{ + gpio_bit_set(input_port, pin); +} + +static inline void gpio_clear(uint32_t pin) +{ + gpio_bit_reset(input_port, pin); +} + +static inline bool gpio_read(uint32_t pin) +{ + return (gpio_input_port_get(input_port) & pin) != 0; +} + +#define BL_TIMER TIMER16 + +/* + initialise timer for 1us per tick + */ +static inline void bl_timer_init(void) +{ + rcu_periph_clock_enable(RCU_TIMER16); + TIMER_CAR(BL_TIMER) = 0xFFFF; + TIMER_PSC(BL_TIMER) = 35; + timer_auto_reload_shadow_enable(BL_TIMER); + timer_enable(BL_TIMER); +} + +/* + disable timer ready for app start + */ +static inline void bl_timer_disable(void) +{ + timer_disable(BL_TIMER); +} + +static inline uint32_t bl_timer_us(void) +{ + return timer_counter_read(BL_TIMER); +} + +static inline void bl_timer_reset(void) +{ + timer_counter_value_config(BL_TIMER, 0); +} + +/* + initialise clocks + */ +static inline void bl_clock_config(void) +{ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_GPIOB); +} + +static inline void bl_gpio_init(void) +{ +} + +/* + return true if the MCU booted under a software reset + */ +static inline bool bl_was_software_reset(void) +{ + return (RCU_RSTSCK & RCU_RSTSCK_SWRSTF) != 0; +} diff --git a/Mcu/f031/Inc/blutil.h b/Mcu/f031/Inc/blutil.h new file mode 100644 index 000000000..e9d5dca49 --- /dev/null +++ b/Mcu/f031/Inc/blutil.h @@ -0,0 +1,152 @@ +/* + MCU specific utility functions for the bootloader + */ +/* + based on https://github.com/AlkaMotors/AM32_Bootloader_F051/blob/main/Core/ + */ +#pragma once + +#define GPIO_PINS_2 (1U<<2) +#define GPIO_PINS_4 (1U<<4) + +#define GPIO_PULL_NONE LL_GPIO_PULL_NO +#define GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */ +#define GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */ + +#define GPIO_OUTPUT_PUSH_PULL LL_GPIO_OUTPUT_PUSHPULL + +// assume 8MHz crystal +uint32_t SystemCoreClock = 8000000U; + +static inline void gpio_mode_set_input(uint32_t pin, uint32_t pull_up_down) +{ + LL_GPIO_SetPinPull(input_port, pin, pull_up_down); +} + +static inline void gpio_mode_set_output(uint32_t pin, uint32_t output_mode) +{ + LL_GPIO_SetPinMode(input_port, pin, LL_GPIO_MODE_OUTPUT); +} + +static inline void gpio_set(uint32_t pin) +{ + input_port->BSRR = pin; +} + +static inline void gpio_clear(uint32_t pin) +{ + input_port->BRR = pin; +} + +static inline bool gpio_read(uint32_t pin) +{ + return (input_port->IDR & pin) != 0; +} + +#define BL_TIMER TIM2 + +/* + initialise timer for 1us per tick + */ +static inline void bl_timer_init(void) +{ + LL_TIM_InitTypeDef TIM_InitStruct = {0}; + + /* Peripheral clock enable */ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2); + + TIM_InitStruct.Prescaler = 47; + TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; + TIM_InitStruct.Autoreload = 0xFFFFFFFF; + TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; + LL_TIM_Init(BL_TIMER, &TIM_InitStruct); + LL_TIM_DisableARRPreload(BL_TIMER); + LL_TIM_SetClockSource(BL_TIMER, LL_TIM_CLOCKSOURCE_INTERNAL); + LL_TIM_SetTriggerOutput(BL_TIMER, LL_TIM_TRGO_RESET); + LL_TIM_DisableMasterSlaveMode(BL_TIMER); +} + +/* + disable timer ready for app start + */ +static inline void bl_timer_disable(void) +{ + LL_TIM_DeInit(BL_TIMER); +} + +static inline uint32_t bl_timer_us(void) +{ + return BL_TIMER->CNT; +} + +static inline void bl_timer_reset(void) +{ + BL_TIMER->CNT = 0; +} + +/* + initialise clocks + */ +static inline void bl_clock_config(void) +{ + LL_FLASH_SetLatency(LL_FLASH_LATENCY_1); + + LL_RCC_HSI_Enable(); + + /* Wait till HSI is ready */ + while(LL_RCC_HSI_IsReady() != 1) + { + } + LL_RCC_HSI_SetCalibTrimming(16); + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, LL_RCC_PLL_MUL_12); + LL_RCC_PLL_Enable(); + + /* Wait till PLL is ready */ + while(LL_RCC_PLL_IsReady() != 1) + { + } + LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); + LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1); + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); + + /* Wait till System clock is ready */ + while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) + { + } + LL_Init1msTick(48000000); + LL_SetSystemCoreClock(48000000); +} + +static inline void bl_gpio_init(void) +{ + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; +#ifdef USE_PB4 + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOB); +#endif +#ifdef USE_PA2 + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA); +#endif + + + /**/ + GPIO_InitStruct.Pin = input_pin; + GPIO_InitStruct.Mode = LL_GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = LL_GPIO_PULL_UP; + LL_GPIO_Init(input_port, &GPIO_InitStruct); +} + +/* + return true if the MCU booted under a software reset + */ +static inline bool bl_was_software_reset(void) +{ + return (RCC->CSR & RCC_CSR_SFTRSTF) != 0; +} + +/* + no need for any action in SystemInit + */ +void SystemInit() +{ +} + diff --git a/Mcu/f051/Inc/blutil.h b/Mcu/f051/Inc/blutil.h new file mode 100644 index 000000000..e9d5dca49 --- /dev/null +++ b/Mcu/f051/Inc/blutil.h @@ -0,0 +1,152 @@ +/* + MCU specific utility functions for the bootloader + */ +/* + based on https://github.com/AlkaMotors/AM32_Bootloader_F051/blob/main/Core/ + */ +#pragma once + +#define GPIO_PINS_2 (1U<<2) +#define GPIO_PINS_4 (1U<<4) + +#define GPIO_PULL_NONE LL_GPIO_PULL_NO +#define GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */ +#define GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */ + +#define GPIO_OUTPUT_PUSH_PULL LL_GPIO_OUTPUT_PUSHPULL + +// assume 8MHz crystal +uint32_t SystemCoreClock = 8000000U; + +static inline void gpio_mode_set_input(uint32_t pin, uint32_t pull_up_down) +{ + LL_GPIO_SetPinPull(input_port, pin, pull_up_down); +} + +static inline void gpio_mode_set_output(uint32_t pin, uint32_t output_mode) +{ + LL_GPIO_SetPinMode(input_port, pin, LL_GPIO_MODE_OUTPUT); +} + +static inline void gpio_set(uint32_t pin) +{ + input_port->BSRR = pin; +} + +static inline void gpio_clear(uint32_t pin) +{ + input_port->BRR = pin; +} + +static inline bool gpio_read(uint32_t pin) +{ + return (input_port->IDR & pin) != 0; +} + +#define BL_TIMER TIM2 + +/* + initialise timer for 1us per tick + */ +static inline void bl_timer_init(void) +{ + LL_TIM_InitTypeDef TIM_InitStruct = {0}; + + /* Peripheral clock enable */ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2); + + TIM_InitStruct.Prescaler = 47; + TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; + TIM_InitStruct.Autoreload = 0xFFFFFFFF; + TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; + LL_TIM_Init(BL_TIMER, &TIM_InitStruct); + LL_TIM_DisableARRPreload(BL_TIMER); + LL_TIM_SetClockSource(BL_TIMER, LL_TIM_CLOCKSOURCE_INTERNAL); + LL_TIM_SetTriggerOutput(BL_TIMER, LL_TIM_TRGO_RESET); + LL_TIM_DisableMasterSlaveMode(BL_TIMER); +} + +/* + disable timer ready for app start + */ +static inline void bl_timer_disable(void) +{ + LL_TIM_DeInit(BL_TIMER); +} + +static inline uint32_t bl_timer_us(void) +{ + return BL_TIMER->CNT; +} + +static inline void bl_timer_reset(void) +{ + BL_TIMER->CNT = 0; +} + +/* + initialise clocks + */ +static inline void bl_clock_config(void) +{ + LL_FLASH_SetLatency(LL_FLASH_LATENCY_1); + + LL_RCC_HSI_Enable(); + + /* Wait till HSI is ready */ + while(LL_RCC_HSI_IsReady() != 1) + { + } + LL_RCC_HSI_SetCalibTrimming(16); + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, LL_RCC_PLL_MUL_12); + LL_RCC_PLL_Enable(); + + /* Wait till PLL is ready */ + while(LL_RCC_PLL_IsReady() != 1) + { + } + LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); + LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1); + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); + + /* Wait till System clock is ready */ + while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) + { + } + LL_Init1msTick(48000000); + LL_SetSystemCoreClock(48000000); +} + +static inline void bl_gpio_init(void) +{ + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; +#ifdef USE_PB4 + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOB); +#endif +#ifdef USE_PA2 + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA); +#endif + + + /**/ + GPIO_InitStruct.Pin = input_pin; + GPIO_InitStruct.Mode = LL_GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = LL_GPIO_PULL_UP; + LL_GPIO_Init(input_port, &GPIO_InitStruct); +} + +/* + return true if the MCU booted under a software reset + */ +static inline bool bl_was_software_reset(void) +{ + return (RCC->CSR & RCC_CSR_SFTRSTF) != 0; +} + +/* + no need for any action in SystemInit + */ +void SystemInit() +{ +} + diff --git a/Mcu/f051/Inc/flash.h b/Mcu/f051/Inc/flash.h new file mode 100644 index 000000000..ace641aff --- /dev/null +++ b/Mcu/f051/Inc/flash.h @@ -0,0 +1,2 @@ +void save_flash_nolib(uint8_t *data, int length, uint32_t add); +void read_flash_bin(uint8_t* data, uint32_t add, int out_buff_len); diff --git a/Mcu/f415/Inc/blutil.h b/Mcu/f415/Inc/blutil.h new file mode 100644 index 000000000..f31c79d12 --- /dev/null +++ b/Mcu/f415/Inc/blutil.h @@ -0,0 +1,191 @@ +/* + MCU specific utility functions for the bootloader + */ +#pragma once + +static inline void gpio_mode_set_input(uint32_t pin, uint32_t pull_up_down) +{ + if (pin < 8) { + const uint32_t pin4 = (pin*pin*pin*pin); + input_port->cfglr = (input_port->cfglr & ~(pin4*0xfU)) | (pin4*(GPIO_MODE_INPUT | pull_up_down)); + } else { + pin = (pin-8); + const uint32_t pin4 = (pin*pin*pin*pin); + input_port->cfghr = (input_port->cfglr & ~(pin4*0xfU)) | (pin4*(GPIO_MODE_INPUT | pull_up_down)); + } +} + +static inline void gpio_mode_set_output(uint32_t pin, uint32_t output_mode) +{ + if (pin < 8) { + const uint32_t pin4 = (pin*pin*pin*pin); + input_port->cfglr = (input_port->cfglr & ~(pin4*0xfU)) | (pin4*(GPIO_MODE_OUTPUT | output_mode)); + } else { + pin = (pin-8); + const uint32_t pin4 = (pin*pin*pin*pin); + input_port->cfghr = (input_port->cfghr & ~(pin4*0xfU)) | (pin4*(GPIO_MODE_OUTPUT | output_mode)); + } +} + +static inline void gpio_set(uint32_t pin) +{ + input_port->scr = pin; +} + +static inline void gpio_clear(uint32_t pin) +{ + input_port->clr = pin; +} + +static inline bool gpio_read(uint32_t pin) +{ + return (input_port->idt & pin) != 0; +} + +#define BL_TIMER TMR3 + +/* + initialise timer for 1us per tick + */ +static inline void bl_timer_init(void) +{ + crm_periph_clock_enable(CRM_TMR3_PERIPH_CLOCK, TRUE); + + BL_TIMER->div = 143; + BL_TIMER->pr = 0xFFFF; + BL_TIMER->swevt_bit.ovfswtr = TRUE; + + BL_TIMER->ctrl1_bit.tmren = TRUE; +} + +unsigned int system_core_clock = HICK_VALUE; /*!< system clock frequency (core clock) */ + +/* + cut down version of system_core_clock_update for HICK source only + */ +void system_core_clock_update(void) +{ + uint32_t temp = 0, div_value = 0; + + static const uint8_t sys_ahb_div_table[16] = { 0, 0, 0, 0, 0, 0, 0, 0, + 1, 2, 3, 4, 6, 7, 8, 9 }; + + if (((CRM->misc2_bit.hick_to_sclk) != RESET) && ((CRM->misc1_bit.hickdiv) != RESET)) + system_core_clock = HICK_VALUE * 6; + else + system_core_clock = HICK_VALUE; + + /* compute sclk, ahbclk frequency */ + /* get ahb division */ + temp = CRM->cfg_bit.ahbdiv; + div_value = sys_ahb_div_table[temp]; + /* ahbclk frequency */ + system_core_clock = system_core_clock >> div_value; +} + +/* + initialise clocks + */ +static inline void bl_clock_config(void) +{ + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_4); + + /* reset crm */ + crm_reset(); + + crm_clock_source_enable(CRM_CLOCK_SOURCE_HICK, TRUE); + + /* wait till hick is ready */ + while(crm_flag_get(CRM_HICK_STABLE_FLAG) != SET) + { + } + + /* config pll clock resource */ + crm_pll_config(CRM_PLL_SOURCE_HICK, CRM_PLL_MULT_36); + + /* enable pll */ + crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE); + + /* wait till pll is ready */ + while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET) + { + } + + /* config ahbclk */ + crm_ahb_div_set(CRM_AHB_DIV_1); + + /* config apb2clk */ + crm_apb2_div_set(CRM_APB2_DIV_2); + + /* config apb1clk */ + crm_apb1_div_set(CRM_APB1_DIV_2); + + /* enable auto step mode */ + crm_auto_step_mode_enable(TRUE); + + /* select pll as system clock source */ + crm_sysclk_switch(CRM_SCLK_PLL); + + /* wait till pll is used as system clock source */ + while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL) + { + } + + /* disable auto step mode */ + crm_auto_step_mode_enable(FALSE); + + /* update system_core_clock global variable */ + system_core_clock_update(); +} + +static inline void bl_gpio_init(void) +{ + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_IOMUX_PERIPH_CLOCK , TRUE); + gpio_pin_remap_config(SWJTAG_GMUX_010, TRUE); // pb4 GPIO + + gpio_init_type gpio_init_struct; + gpio_default_para_init(&gpio_init_struct); + + gpio_init_struct.gpio_pins = input_pin; + gpio_init_struct.gpio_mode = GPIO_MODE_INPUT; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + + gpio_init(input_port, &gpio_init_struct); +} + +/* + disable timer ready for app start + */ +static inline void bl_timer_disable(void) +{ + BL_TIMER->ctrl1_bit.tmren = FALSE; +} + +static inline uint32_t bl_timer_us(void) +{ + return BL_TIMER->cval; +} + +static inline void bl_timer_reset(void) +{ + BL_TIMER->cval = 0; +} + +/* + return true if the MCU booted under a software reset + */ +static inline bool bl_was_software_reset(void) +{ + return crm_flag_get(CRM_SW_RESET_FLAG) == SET; +} + +/* + no need for any action in SystemInit + */ +void SystemInit() +{ +} diff --git a/Mcu/f415/Src/eeprom.c b/Mcu/f415/Src/eeprom.c index d06e31f86..32743304e 100644 --- a/Mcu/f415/Src/eeprom.c +++ b/Mcu/f415/Src/eeprom.c @@ -52,4 +52,4 @@ void read_flash_bin(uint8_t* data, uint32_t add, int out_buff_len) for (int i = 0; i < out_buff_len; i++) { data[i] = *(uint8_t*)(add + i); } -} \ No newline at end of file +} diff --git a/Mcu/f421/Inc/blutil.h b/Mcu/f421/Inc/blutil.h new file mode 100644 index 000000000..ee890ffa4 --- /dev/null +++ b/Mcu/f421/Inc/blutil.h @@ -0,0 +1,124 @@ +/* + MCU specific utility functions for the bootloader + */ +#pragma once + +static inline void gpio_mode_set_input(uint32_t pin, uint32_t pull_up_down) +{ + const uint32_t pinsq = (pin*pin); + input_port->cfgr = (input_port->cfgr & ~(pinsq * 0x3U)) | (pinsq * GPIO_MODE_INPUT); + input_port->pull = (input_port->pull & ~(pinsq * 0x3U)) | (pinsq * pull_up_down); +} + +static inline void gpio_mode_set_output(uint32_t pin, uint32_t output_mode) +{ + const uint32_t pinsq = (pin*pin); + input_port->cfgr = (input_port->cfgr & ~(pinsq * 0x3U)) | (pinsq * GPIO_MODE_OUTPUT); + input_port->omode = (input_port->omode & ~pin) | (output_mode << pin); +} + +static inline void gpio_set(uint32_t pin) +{ + input_port->scr = pin; +} + +static inline void gpio_clear(uint32_t pin) +{ + input_port->clr = pin; +} + +static inline bool gpio_read(uint32_t pin) +{ + return (input_port->idt & pin) != 0; +} + +#define BL_TIMER TMR3 + +/* + initialise timer for 1us per tick + */ +static inline void bl_timer_init(void) +{ + crm_periph_clock_enable(CRM_TMR3_PERIPH_CLOCK, TRUE); + + BL_TIMER->div = 119; + BL_TIMER->pr = 0xFFFF; + BL_TIMER->ctrl1_bit.tmren = TRUE; +} + +/* + disable timer ready for app start + */ +static inline void bl_timer_disable(void) +{ + BL_TIMER->ctrl1_bit.tmren = FALSE; +} + +static inline uint32_t bl_timer_us(void) +{ + return BL_TIMER->cval; +} + +static inline void bl_timer_reset(void) +{ + BL_TIMER->cval = 0; +} + +/* + initialise clocks + */ +static inline void bl_clock_config(void) +{ + flash_psr_set(FLASH_WAIT_CYCLE_3); + crm_reset(); + crm_clock_source_enable(CRM_CLOCK_SOURCE_HICK, TRUE); + while(crm_flag_get(CRM_HICK_STABLE_FLAG) != SET) + { + } + crm_pll_config(CRM_PLL_SOURCE_HICK, CRM_PLL_MULT_30); + crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE); + while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET) + { + } + crm_ahb_div_set(CRM_AHB_DIV_1); + crm_apb2_div_set(CRM_APB2_DIV_1); + crm_apb1_div_set(CRM_APB1_DIV_1); + crm_auto_step_mode_enable(TRUE); + crm_sysclk_switch(CRM_SCLK_PLL); + while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL) + { + } + crm_auto_step_mode_enable(FALSE); +} + +static inline void bl_gpio_init(void) +{ + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE); + + gpio_init_type gpio_init_struct; + gpio_default_para_init(&gpio_init_struct); + + gpio_init_struct.gpio_pins = input_pin; + gpio_init_struct.gpio_mode = GPIO_MODE_INPUT; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + + gpio_init(input_port, &gpio_init_struct); +} + +/* + return true if the MCU booted under a software reset + */ +static inline bool bl_was_software_reset(void) +{ + return crm_flag_get(CRM_SW_RESET_FLAG) == SET; +} + +/* + no need for any action in SystemInit + */ +void SystemInit() +{ +} diff --git a/Mcu/f421/Src/at32f421_it.c b/Mcu/f421/Src/at32f421_it.c index c9268d65f..115b85d8f 100644 --- a/Mcu/f421/Src/at32f421_it.c +++ b/Mcu/f421/Src/at32f421_it.c @@ -2,9 +2,13 @@ * ------------------------------------------------------------------*/ #include "at32f421_it.h" +#ifndef BOOTLOADER #include "ADC.h" +#endif #include "main.h" +#ifndef BOOTLOADER #include "targets.h" +#endif extern void transfercomplete(); extern void PeriodElapsedCallback(); extern void interruptRoutine(); @@ -171,6 +175,7 @@ void DMA1_Channel5_4_IRQHandler(void) #endif } +#ifndef BOOTLOADER /** * @brief This function handles ADC and COMP interrupts (COMP interrupts * through EXTI lines 21 and 22). @@ -202,6 +207,8 @@ void TMR16_GLOBAL_IRQHandler(void) TMR16->ists = 0x00; PeriodElapsedCallback(); } +#endif // BOOTLOADER + void TMR15_GLOBAL_IRQHandler(void) { @@ -254,6 +261,7 @@ void TMR3_GLOBAL_IRQHandler(void) // } //} +#ifndef BOOTLOADER void EXINT15_4_IRQHandler(void) { exti_int++; @@ -262,6 +270,8 @@ void EXINT15_4_IRQHandler(void) processDshot(); } } +#endif + /******************************************************************************/ /* AT32F4xx Peripherals Interrupt Handlers */ diff --git a/Mcu/g071/Inc/blutil.h b/Mcu/g071/Inc/blutil.h new file mode 100644 index 000000000..81153c6ac --- /dev/null +++ b/Mcu/g071/Inc/blutil.h @@ -0,0 +1,153 @@ +/* + MCU specific utility functions for the bootloader + */ +/* + based on https://github.com/AlkaMotors/g071Bootloader + */ +#pragma once + +#define GPIO_PINS_2 (1U<<2) +#define GPIO_PINS_4 (1U<<4) + +#define GPIO_PULL_NONE LL_GPIO_PULL_NO +#define GPIO_PULL_UP LL_GPIO_PULL_UP +#define GPIO_PULL_DOWN LL_GPIO_PULL_DOWN + +#define GPIO_OUTPUT_PUSH_PULL LL_GPIO_OUTPUT_PUSHPULL + +// assume 8MHz crystal +uint32_t SystemCoreClock = 8000000U; + +static inline void gpio_mode_set_input(uint32_t pin, uint32_t pull_up_down) +{ + LL_GPIO_SetPinPull(input_port, pin, pull_up_down); +} + +static inline void gpio_mode_set_output(uint32_t pin, uint32_t output_mode) +{ + LL_GPIO_SetPinMode(input_port, pin, LL_GPIO_MODE_OUTPUT); +} + +static inline void gpio_set(uint32_t pin) +{ + input_port->BSRR = pin; +} + +static inline void gpio_clear(uint32_t pin) +{ + input_port->BRR = pin; +} + +static inline bool gpio_read(uint32_t pin) +{ + return (input_port->IDR & pin) != 0; +} + +#define BL_TIMER TIM2 + +/* + initialise timer for 1us per tick + */ +static inline void bl_timer_init(void) +{ + LL_TIM_InitTypeDef TIM_InitStruct = {0}; + + /* Peripheral clock enable */ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2); + + TIM_InitStruct.Prescaler = 47; + TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; + TIM_InitStruct.Autoreload = 0xFFFFFFFF; + TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; + LL_TIM_Init(BL_TIMER, &TIM_InitStruct); + LL_TIM_DisableARRPreload(BL_TIMER); + LL_TIM_SetClockSource(BL_TIMER, LL_TIM_CLOCKSOURCE_INTERNAL); + LL_TIM_SetTriggerOutput(BL_TIMER, LL_TIM_TRGO_RESET); + LL_TIM_DisableMasterSlaveMode(BL_TIMER); +} + +/* + disable timer ready for app start + */ +static inline void bl_timer_disable(void) +{ + LL_TIM_DeInit(BL_TIMER); +} + +static inline uint32_t bl_timer_us(void) +{ + return BL_TIMER->CNT; +} + +static inline void bl_timer_reset(void) +{ + BL_TIMER->CNT = 0; +} + +/* + initialise clocks + */ +static inline void bl_clock_config(void) +{ + LL_FLASH_SetLatency(LL_FLASH_LATENCY_2); + + /* HSI configuration and activation */ + LL_RCC_HSI_Enable(); + while(LL_RCC_HSI_IsReady() != 1) + { + } + + /* Main PLL configuration and activation */ + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, LL_RCC_PLLM_DIV_1, 8, LL_RCC_PLLR_DIV_2); + LL_RCC_PLL_Enable(); + LL_RCC_PLL_EnableDomain_SYS(); + while(LL_RCC_PLL_IsReady() != 1) + { + } + + /* Set AHB prescaler*/ + LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); + + /* Sysclk activation on the main PLL */ + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); + while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) + { + } + + /* Set APB1 prescaler*/ + LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1); + LL_Init1msTick(64000000); + LL_SetSystemCoreClock(64000000); + /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */ + LL_SetSystemCoreClock(64000000); +} + +static inline void bl_gpio_init(void) +{ + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA); + LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOB); + + /**/ + GPIO_InitStruct.Pin = input_pin; + GPIO_InitStruct.Mode = LL_GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(input_port, &GPIO_InitStruct); +} + +/* + return true if the MCU booted under a software reset + */ +static inline bool bl_was_software_reset(void) +{ + return (RCC->CSR & RCC_CSR_SFTRSTF) != 0; +} + +/* + no need for any action in SystemInit + */ +void SystemInit() +{ +} diff --git a/bootloader/ldscript_bl.ld b/bootloader/ldscript_bl.ld new file mode 100644 index 000000000..aa0e7428b --- /dev/null +++ b/bootloader/ldscript_bl.ld @@ -0,0 +1,135 @@ +/* + linker file for AM32 bootloader +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +_estack = 0x20002000; /* end of RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 4K +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 16K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bootloader/main.c b/bootloader/main.c new file mode 100644 index 000000000..656853f4f --- /dev/null +++ b/bootloader/main.c @@ -0,0 +1,628 @@ +/* + bootloader for AM32 ESC firmware + + based on https://github.com/AlkaMotors/AT32F421_AM32_Bootloader + */ +#include +#include + +#include + +#if !defined(USE_PA2) && !defined(USE_PB4) +//#define USE_PB4 +#define USE_PA2 +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include + +#include "main.h" +#include + +//#define USE_ADC_INPUT // will go right to application and ignore eeprom +//#define UPDATE_EEPROM_ENABLE + +#include + +#define STM32_FLASH_START 0x08000000 +#define FIRMWARE_RELATIVE_START 0x1000 + +#ifdef SIXTY_FOUR_KB_MEMORY +#define EEPROM_RELATIVE_START 0xf800 +#else +#define EEPROM_RELATIVE_START 0x7c00 +#endif + + +typedef void (*pFunction)(void); + +#define APPLICATION_ADDRESS (uint32_t)(STM32_FLASH_START + FIRMWARE_RELATIVE_START) // 4k + +#define EEPROM_START_ADD (uint32_t)(STM32_FLASH_START + EEPROM_RELATIVE_START) +#define FLASH_END_ADD (uint32_t)(STM32_FLASH_START + 0x7FFF) // 32 k + + +#define CMD_RUN 0x00 +#define CMD_PROG_FLASH 0x01 +#define CMD_ERASE_FLASH 0x02 +#define CMD_READ_FLASH_SIL 0x03 +#define CMD_VERIFY_FLASH 0x03 +#define CMD_VERIFY_FLASH_ARM 0x04 +#define CMD_READ_EEPROM 0x04 +#define CMD_PROG_EEPROM 0x05 +#define CMD_READ_SRAM 0x06 +#define CMD_READ_FLASH_ATM 0x07 +#define CMD_KEEP_ALIVE 0xFD +#define CMD_SET_ADDRESS 0xFF +#define CMD_SET_BUFFER 0xFE + + +#ifdef USE_PA2 +#define input_pin GPIO_PINS_2 +#define input_port GPIOA +#define PIN_NUMBER 2 +#define PORT_LETTER 0 +#endif + +#ifdef USE_PB4 +#define input_pin GPIO_PINS_4 +#define input_port GPIOB +#define PIN_NUMBER 4 +#define PORT_LETTER 1 +#endif + +#include + +static uint16_t low_pin_count; +static char receviedByte; +static int count; +static char messagereceived; +static uint16_t invalid_command; +static uint16_t address_expected_increment; +static int cmd; +static char eeprom_req; +static int received; + + +static uint8_t pin_code = PORT_LETTER << 4 | PIN_NUMBER; +#ifdef SIXTY_FOUR_KB_MEMORY +static uint8_t deviceInfo[9] = {0x34,0x37,0x31,0x64,0x35,0x06,0x06,0x01,0x30}; +#else +static uint8_t deviceInfo[9] = {0x34,0x37,0x31,0x00,0x1f,0x06,0x06,0x01,0x30}; // stm32 device info +#endif + + +static uint8_t rxBuffer[258]; +static uint8_t payLoadBuffer[256]; +static char rxbyte; +static uint32_t address; + +typedef union __attribute__ ((packed)) { + uint8_t bytes[2]; + uint16_t word; +} uint8_16_u; + +static uint16_t len; +static uint8_t calculated_crc_low_byte; +static uint8_t calculated_crc_high_byte; +static uint16_t payload_buffer_size; +static char incoming_payload_no_command; + +static uint32_t JumpAddress; +static pFunction JumpToApplication; + +/* USER CODE BEGIN PFP */ +static void serialwriteChar(char data); +static void sendString(uint8_t data[], int len); +static void recieveBuffer(); + +#define BAUDRATE 19200 +#define BITTIME 1000000/BAUDRATE +#define HALFBITTIME 500000/BAUDRATE + +static void delayMicroseconds(uint32_t micros) +{ + bl_timer_reset(); + while (bl_timer_us() < micros) { + } +} + +/* + jump to the application firmware + */ +static void jump() +{ + __disable_irq(); + JumpAddress = *(__IO uint32_t*) (APPLICATION_ADDRESS + 4); + uint8_t value = *(uint8_t*)(EEPROM_START_ADD); + if (value != 0x01) { // check first byte of eeprom to see if its programmed, if not do not jump + invalid_command = 0; + return; + } + bl_timer_disable(); + JumpToApplication = (pFunction) JumpAddress; + + __set_MSP(*(__IO uint32_t*) APPLICATION_ADDRESS); + JumpToApplication(); +} + + + +static void makeCrc(uint8_t* pBuff, uint16_t length) +{ + static uint8_16_u CRC_16; + CRC_16.word=0; + + for(int i = 0; i < length; i++) { + + + uint8_t xb = pBuff[i]; + for (uint8_t j = 0; j < 8; j++) + { + if (((xb & 0x01) ^ (CRC_16.word & 0x0001)) !=0 ) { + CRC_16.word = CRC_16.word >> 1; + CRC_16.word = CRC_16.word ^ 0xA001; + } else { + CRC_16.word = CRC_16.word >> 1; + } + xb = xb >> 1; + } + } + calculated_crc_low_byte = CRC_16.bytes[0]; + calculated_crc_high_byte = CRC_16.bytes[1]; +} + +static char checkCrc(uint8_t* pBuff, uint16_t length) +{ + + char received_crc_low_byte2 = pBuff[length]; // one higher than len in buffer + char received_crc_high_byte2 = pBuff[length+1]; + makeCrc(pBuff,length); + + if((calculated_crc_low_byte==received_crc_low_byte2) && (calculated_crc_high_byte==received_crc_high_byte2)){ + return 1; + }else{ + return 0; + } +} + + +static void setReceive() +{ + gpio_mode_set_input(input_pin, GPIO_PULL_NONE); + received = 0; +} + +static void setTransmit() +{ + gpio_set(input_pin); + gpio_mode_set_output(input_pin, GPIO_OUTPUT_PUSH_PULL); +} + + +static void send_ACK() +{ + setTransmit(); + serialwriteChar(0x30); // good ack! + setReceive(); +} + +static void send_BAD_ACK() +{ + setTransmit(); + serialwriteChar(0xC1); // bad command message. + setReceive(); +} + +static void send_BAD_CRC_ACK() +{ + setTransmit(); + serialwriteChar(0xC2); // bad command message. + setReceive(); +} + +static void sendDeviceInfo() +{ + setTransmit(); + sendString(deviceInfo,9); + setReceive(); +} + +static bool checkAddressWritable(uint32_t address) +{ + return address >= APPLICATION_ADDRESS; +} + +static void decodeInput() +{ + if (incoming_payload_no_command) { + len = payload_buffer_size; + if (checkCrc(rxBuffer,len)) { + memset(payLoadBuffer, 0, sizeof(payLoadBuffer)); // reset buffer + + for(int i = 0; i < len; i++){ + payLoadBuffer[i]= rxBuffer[i]; + } + send_ACK(); + incoming_payload_no_command = 0; + return; + }else{ + send_BAD_CRC_ACK(); + return; + } + } + + cmd = rxBuffer[0]; + + if (rxBuffer[16] == 0x7d) { + if(rxBuffer[8] == 13 && rxBuffer[9] == 66) { + sendDeviceInfo(); + rxBuffer[20]= 0; + + } + return; + } + + if (rxBuffer[20] == 0x7d) { + if(rxBuffer[12] == 13 && rxBuffer[13] == 66) { + sendDeviceInfo(); + rxBuffer[20]= 0; + return; + } + + } + if (rxBuffer[40] == 0x7d) { + if (rxBuffer[32] == 13 && rxBuffer[33] == 66) { + sendDeviceInfo(); + rxBuffer[20]= 0; + return; + } + } + + if (cmd == CMD_RUN) { + // starts the main app + if((rxBuffer[1] == 0) && (rxBuffer[2] == 0) && (rxBuffer[3] == 0)) { + invalid_command = 101; + } + } + + if (cmd == CMD_PROG_FLASH) { + len = 2; + if (!checkCrc((uint8_t*)rxBuffer, len)) { + send_BAD_CRC_ACK(); + + return; + } + + if (!checkAddressWritable(address)) { + send_BAD_ACK(); + + return; + } + + save_flash_nolib((uint8_t*)payLoadBuffer, payload_buffer_size,address); + send_ACK(); + + return; + } + + if (cmd == CMD_SET_ADDRESS) { + // command set addressinput format is: CMD, 00 , High byte + // address, Low byte address, crclb ,crchb + len = 4; // package without 2 byte crc + if (!checkCrc((uint8_t*)rxBuffer, len)) { + send_BAD_CRC_ACK(); + + return; + } + + + // will send Ack 0x30 and read input after transfer out callback + invalid_command = 0; + address = STM32_FLASH_START + (rxBuffer[2] << 8 | rxBuffer[3]); + send_ACK(); + + return; + } + + if (cmd == CMD_SET_BUFFER) { + // for writing buffer rx buffer 0 = command byte. command set + // address, input , format is CMD, 00 , 00 or 01 (if buffer is 256), + // buffer_size, + len = 4; // package without 2 byte crc + if (!checkCrc((uint8_t*)rxBuffer, len)) { + send_BAD_CRC_ACK(); + + return; + } + + // no ack with command set buffer; + if(rxBuffer[2] == 0x01){ + payload_buffer_size = 256; // if nothing in this buffer + }else{ + payload_buffer_size = rxBuffer[3]; + } + incoming_payload_no_command = 1; + address_expected_increment = 256; + setReceive(); + + return; + } + + if (cmd == CMD_KEEP_ALIVE) { + len = 2; + if (!checkCrc((uint8_t*)rxBuffer, len)) { + send_BAD_CRC_ACK(); + + return; + } + + setTransmit(); + serialwriteChar(0xC1); // bad command message. + setReceive(); + + return; + } + + if (cmd == CMD_ERASE_FLASH) { + len = 2; + if (!checkCrc((uint8_t*)rxBuffer, len)) { + send_BAD_CRC_ACK(); + + return; + } + + if (!checkAddressWritable(address)) { + send_BAD_ACK(); + + return; + } + + send_ACK(); + return; + } + + if (cmd == CMD_READ_EEPROM) { + eeprom_req = 1; + } + + if (cmd == CMD_READ_FLASH_SIL) { + // for sending contents of flash memory at the memory location set in + // bootloader.c need to still set memory with data from set mem + // command + len = 2; + if (!checkCrc((uint8_t*)rxBuffer, len)) { + send_BAD_CRC_ACK(); + + return; + } + + count++; + uint16_t out_buffer_size = rxBuffer[1];// + if(out_buffer_size == 0){ + out_buffer_size = 256; + } + address_expected_increment = 128; + + setTransmit(); + uint8_t read_data[out_buffer_size + 3]; // make buffer 3 larger to fit CRC and ACK + memset(read_data, 0, sizeof(read_data)); + // read_flash((uint8_t*)read_data , address); // make sure read_flash reads two less than buffer. + read_flash_bin((uint8_t*)read_data , address, out_buffer_size); + + makeCrc(read_data,out_buffer_size); + read_data[out_buffer_size] = calculated_crc_low_byte; + read_data[out_buffer_size + 1] = calculated_crc_high_byte; + read_data[out_buffer_size + 2] = 0x30; + sendString(read_data, out_buffer_size+3); + + setReceive(); + + return; + } + + setTransmit(); + + serialwriteChar(0xC1); // bad command message. + invalid_command++; + setReceive(); +} + + +static void serialreadChar() +{ + rxbyte=0; + while (!gpio_read(input_pin)) { // wait for rx to go high + if(bl_timer_us() > 20000){ + invalid_command = 101; + return; + } + } + + + while (gpio_read(input_pin)) { // wait for it go go low + if(bl_timer_us() > 250 && messagereceived){ + return; + } + } + + delayMicroseconds(HALFBITTIME);//wait to get the center of bit time + + int bits_to_read = 0; + while (bits_to_read < 8) { + delayMicroseconds(BITTIME); + rxbyte = rxbyte | gpio_read(input_pin) << bits_to_read; + bits_to_read++; + } + + delayMicroseconds(HALFBITTIME); //wait till the stop bit time begins + messagereceived = 1; + receviedByte = rxbyte; +} + + +void serialwriteChar(char data) +{ + gpio_clear(input_pin); + char bits_to_read = 0; + while (bits_to_read < 8) { + delayMicroseconds(BITTIME); + if (data & 0x01) { + //GPIO_BOP(input_port) = input_pin; + gpio_set(input_pin); + } else { + // GPIO_BC(input_port) = input_pin; + gpio_clear(input_pin); + } + bits_to_read++; + data = data >> 1; + } + + delayMicroseconds(BITTIME); + gpio_set(input_pin); +} + + +static void sendString(uint8_t *data, int len) +{ + for(int i = 0; i < len; i++){ + serialwriteChar(data[i]); + delayMicroseconds(BITTIME); + } +} + +static void recieveBuffer() +{ + count = 0; + messagereceived = 0; + memset(rxBuffer, 0, sizeof(rxBuffer)); + + for(int i = 0; i < sizeof(rxBuffer); i++){ + serialreadChar(); + + if(incoming_payload_no_command) { + if(count == payload_buffer_size+2){ + break; + } + rxBuffer[i] = rxbyte; + count++; + } else { + if(bl_timer_us() > 250){ + + count = 0; + + break; + } else { + rxBuffer[i] = rxbyte; + if(i == 257){ + invalid_command+=20; // needs one hundred to trigger a jump but will be reset on next set address commmand + + } + } + } + } + decodeInput(); + +} + +#ifdef UPDATE_EEPROM_ENABLE +static void update_EEPROM() +{ + read_flash_bin(rxBuffer , EEPROM_START_ADD , 48); + if(BOOTLOADER_VERSION != rxBuffer[2]) { + if (rxBuffer[2] == 0xFF || rxBuffer[2] == 0x00){ + return; + } + rxBuffer[2] = BOOTLOADER_VERSION; + save_flash_nolib(rxBuffer, 48, EEPROM_START_ADD); + } +} +#endif // UPDATE_EEPROM_ENABLE + +static void checkForSignal() +{ + gpio_mode_set_input(input_pin, GPIO_PULL_DOWN); + + delayMicroseconds(500); + + for(int i = 0 ; i < 500; i ++){ + if(!gpio_read(input_pin)){ + low_pin_count++; + }else{ + + } + + delayMicroseconds(10); + } + if (low_pin_count > 450) { + if (!bl_was_software_reset()) { + jump(); + } + } + + gpio_mode_set_input(input_pin, GPIO_PULL_UP); + + delayMicroseconds(500); + + for (int i = 0 ; i < 500; i++) { + if( !(gpio_read(input_pin))){ + low_pin_count++; + }else{ + + } + delayMicroseconds(10); + } + if (low_pin_count == 0) { + return; // all high while pin is pulled low, bootloader signal + } + + low_pin_count = 0; + + gpio_mode_set_input(input_pin, GPIO_PULL_NONE); + + delayMicroseconds(500); + + for (int i = 0 ; i < 500; i ++) { + if( !(gpio_read(input_pin))){ + low_pin_count++; + } + + delayMicroseconds(10); + } + if (low_pin_count == 0) { + return; // when floated all + } + + if (low_pin_count > 0) { + jump(); + } +} + +int main(void) +{ + bl_clock_config(); + bl_timer_init(); + bl_gpio_init(); + + checkForSignal(); + + gpio_mode_set_input(input_pin, GPIO_PULL_NONE); + +#ifdef USE_ADC_INPUT // go right to application + jump(); +#endif + + deviceInfo[3] = pin_code; + +#ifdef UPDATE_EEPROM_ENABLE + update_EEPROM(); +#endif + + while (1) { + recieveBuffer(); + if (invalid_command > 100) { + jump(); + } + } +} diff --git a/e230makefile.mk b/e230makefile.mk index 87aa3b081..6a267eee5 100644 --- a/e230makefile.mk +++ b/e230makefile.mk @@ -1,27 +1,35 @@ +MCU := E230 +PART := GD32E230 -TARGETS_E230 := $(call get_targets,E230) +TARGETS_$(MCU) := $(call get_targets,$(MCU)) -HAL_FOLDER_E230 := $(HAL_FOLDER)/e230 +HAL_FOLDER_$(MCU) := $(HAL_FOLDER)/$(call lc,$(MCU)) -MCU_E230 := -mfloat-abi=soft -mthumb -march=armv8-m.main -LDSCRIPT_E230 := $(HAL_FOLDER_E230)/GD32E230K8_FLASH.ld +MCU_$(MCU) := -mfloat-abi=soft -mthumb -march=armv8-m.main +LDSCRIPT_$(MCU) := $(wildcard $(HAL_FOLDER_$(MCU))/*.ld) -SRC_DIR_E230 := \ - $(HAL_FOLDER_E230)/Src \ - $(HAL_FOLDER_E230)/Drivers/CMSIS/Source\ - $(HAL_FOLDER_E230)/Drivers/GD32E23x_standard_peripheral/Source \ - $(HAL_FOLDER_E230)/Startup +SRC_BASE_DIR_$(MCU) := \ + $(HAL_FOLDER_$(MCU))/Drivers/CMSIS/Source \ + $(HAL_FOLDER_$(MCU))/Drivers/GD32E23x_standard_peripheral/Source \ + $(HAL_FOLDER_$(MCU))/Startup -CFLAGS_E230 += \ - -I$(HAL_FOLDER_E230)/Inc \ - -I$(HAL_FOLDER_E230)/Drivers/CMSIS/Include \ - -I$(HAL_FOLDER_E230)/Drivers/CMSIS/Core/Include \ - -I$(HAL_FOLDER_E230)/Drivers/GD32E23x_standard_peripheral/Include +SRC_DIR_$(MCU) := $(SRC_BASE_DIR_$(MCU)) \ + $(HAL_FOLDER_$(MCU))/Src -CFLAGS_E230 += \ - -DGD32E230 \ - -DGD32E23x \ +CFLAGS_$(MCU) += \ + -I$(HAL_FOLDER_$(MCU))/Inc \ + -I$(HAL_FOLDER_$(MCU))/Drivers/CMSIS/Include \ + -I$(HAL_FOLDER_$(MCU))/Drivers/CMSIS/Core/Include \ + -I$(HAL_FOLDER_$(MCU))/Drivers/GD32E23x_standard_peripheral/Include + +CFLAGS_$(MCU) += \ + -DGD32$(MCU) \ + -D$(PART) \ -DUSE_STDPERIPH_DRIVER -SRC_E230 := $(foreach dir,$(SRC_DIR_E230),$(wildcard $(dir)/*.[cs])) +SRC_$(MCU) := $(foreach dir,$(SRC_DIR_$(MCU)),$(wildcard $(dir)/*.[cs])) +SRC_$(MCU)_BL := $(foreach dir,$(SRC_BASE_DIR_$(MCU)),$(wildcard $(dir)/*.[cs])) \ + $(HAL_FOLDER_$(MCU))/Src/eeprom.c \ + $(HAL_FOLDER_$(MCU))/Src/system_gd32e23x.c \ + $(wildcard $(HAL_FOLDER_$(MCU))/*_it.c) diff --git a/f031makefile.mk b/f031makefile.mk index 3d0733403..3aa1b78e4 100644 --- a/f031makefile.mk +++ b/f031makefile.mk @@ -1,25 +1,31 @@ +MCU := F031 +PART := STM32F031x6 -TARGETS_F031 := $(call get_targets,F031) +MCU_LC := $(call lc,$(MCU)) -HAL_FOLDER_F031 := $(HAL_FOLDER)/f031 +TARGETS_$(MCU) := $(call get_targets,$(MCU)) -MCU_F031 := -mcpu=cortex-m0 -mthumb -LDSCRIPT_F031 := $(HAL_FOLDER_F031)/STM32F031C6TX_FLASH.ld +HAL_FOLDER_$(MCU) := $(HAL_FOLDER)/$(MCU_LC) -SRC_DIR_F031 += \ - $(HAL_FOLDER_F031)/Startup \ - $(HAL_FOLDER_F031)/Src \ - $(HAL_FOLDER_F031)/Drivers/STM32F0xx_HAL_Driver/Src +MCU_$(MCU) := -mcpu=cortex-m0 -mthumb +LDSCRIPT_$(MCU) := $(wildcard $(HAL_FOLDER_$(MCU))/*.ld) -CFLAGS_F031 := \ - -I$(HAL_FOLDER_F031)/Inc \ - -I$(HAL_FOLDER_F031)/Drivers/STM32F0xx_HAL_Driver/Inc \ - -I$(HAL_FOLDER_F031)/Drivers/CMSIS/Include \ - -I$(HAL_FOLDER_F031)/Drivers/CMSIS/Device/ST/STM32F0xx/Include +SRC_BASE_DIR_$(MCU) := \ + $(HAL_FOLDER_$(MCU))/Startup \ + $(HAL_FOLDER_$(MCU))/Drivers/STM32F0xx_HAL_Driver/Src -CFLAGS_F031 += \ +SRC_DIR_$(MCU) := $(SRC_BASE_DIR_$(MCU)) \ + $(HAL_FOLDER_$(MCU))/Src + +CFLAGS_$(MCU) := \ + -I$(HAL_FOLDER_$(MCU))/Inc \ + -I$(HAL_FOLDER_$(MCU))/Drivers/STM32F0xx_HAL_Driver/Inc \ + -I$(HAL_FOLDER_$(MCU))/Drivers/CMSIS/Include \ + -I$(HAL_FOLDER_$(MCU))/Drivers/CMSIS/Device/ST/STM32F0xx/Include + +CFLAGS_$(MCU) += \ -DHSE_VALUE=8000000 \ - -DSTM32F031x6 \ + -D$(PART) \ -DHSE_STARTUP_TIMEOUT=100 \ -DLSE_STARTUP_TIMEOUT=5000 \ -DLSE_VALUE=32768 \ @@ -31,4 +37,8 @@ CFLAGS_F031 += \ -DUSE_FULL_LL_DRIVER \ -DPREFETCH_ENABLE=1 -SRC_F031 := $(foreach dir,$(SRC_DIR_F031),$(wildcard $(dir)/*.[cs])) +SRC_$(MCU) := $(foreach dir,$(SRC_DIR_$(MCU)),$(wildcard $(dir)/*.[cs])) + +SRC_$(MCU)_BL := $(foreach dir,$(SRC_BASE_DIR_$(MCU)),$(wildcard $(dir)/*.[cs])) \ + $(HAL_FOLDER_$(MCU))/Src/eeprom.c \ + $(wildcard $(HAL_FOLDER_$(MCU))/*_it.c) diff --git a/f051makefile.mk b/f051makefile.mk index 2b15fda3f..9cf8c452c 100644 --- a/f051makefile.mk +++ b/f051makefile.mk @@ -1,25 +1,31 @@ +MCU := F051 +PART := STM32F051x8 -TARGETS_F051 := $(call get_targets,F051) +MCU_LC := $(call lc,$(MCU)) -HAL_FOLDER_F051 := $(HAL_FOLDER)/f051 +TARGETS_$(MCU) := $(call get_targets,$(MCU)) -MCU_F051 := -mcpu=cortex-m0 -mthumb -LDSCRIPT_F051 := $(HAL_FOLDER_F051)/STM32F051K6TX_FLASH.ld +HAL_FOLDER_$(MCU) := $(HAL_FOLDER)/$(MCU_LC) -SRC_DIR_F051 += \ - $(HAL_FOLDER_F051)/Startup \ - $(HAL_FOLDER_F051)/Src \ - $(HAL_FOLDER_F051)/Drivers/STM32F0xx_HAL_Driver/Src +MCU_$(MCU) := -mcpu=cortex-m0 -mthumb +LDSCRIPT_$(MCU) := $(wildcard $(HAL_FOLDER_$(MCU))/*.ld) -CFLAGS_F051 := \ - -I$(HAL_FOLDER_F051)/Inc \ - -I$(HAL_FOLDER_F051)/Drivers/STM32F0xx_HAL_Driver/Inc \ - -I$(HAL_FOLDER_F051)/Drivers/CMSIS/Include \ - -I$(HAL_FOLDER_F051)/Drivers/CMSIS/Device/ST/STM32F0xx/Include +SRC_BASE_DIR_$(MCU) := \ + $(HAL_FOLDER_$(MCU))/Startup \ + $(HAL_FOLDER_$(MCU))/Drivers/STM32F0xx_HAL_Driver/Src -CFLAGS_F051 += \ +SRC_DIR_$(MCU) := $(SRC_BASE_DIR_$(MCU)) \ + $(HAL_FOLDER_$(MCU))/Src + +CFLAGS_$(MCU) := \ + -I$(HAL_FOLDER_$(MCU))/Inc \ + -I$(HAL_FOLDER_$(MCU))/Drivers/STM32F0xx_HAL_Driver/Inc \ + -I$(HAL_FOLDER_$(MCU))/Drivers/CMSIS/Include \ + -I$(HAL_FOLDER_$(MCU))/Drivers/CMSIS/Device/ST/STM32F0xx/Include + +CFLAGS_$(MCU) += \ -DHSE_VALUE=8000000 \ - -DSTM32F051x8 \ + -D$(PART) \ -DHSE_STARTUP_TIMEOUT=100 \ -DLSE_STARTUP_TIMEOUT=5000 \ -DLSE_VALUE=32768 \ @@ -31,4 +37,8 @@ CFLAGS_F051 += \ -DUSE_FULL_LL_DRIVER \ -DPREFETCH_ENABLE=1 -SRC_F051 := $(foreach dir,$(SRC_DIR_F051),$(wildcard $(dir)/*.[cs])) +SRC_$(MCU) := $(foreach dir,$(SRC_DIR_$(MCU)),$(wildcard $(dir)/*.[cs])) + +SRC_$(MCU)_BL := $(foreach dir,$(SRC_BASE_DIR_$(MCU)),$(wildcard $(dir)/*.[cs])) \ + $(HAL_FOLDER_$(MCU))/Src/eeprom.c \ + $(wildcard $(HAL_FOLDER_$(MCU))/*_it.c) diff --git a/f415makefile.mk b/f415makefile.mk index c3ae98c2b..995742e67 100644 --- a/f415makefile.mk +++ b/f415makefile.mk @@ -1,25 +1,33 @@ +MCU := F415 +PART := AT32F415K8U7_4 -TARGETS_F415 := $(call get_targets,F415) +MCU_LC := $(call lc,$(MCU)) -HAL_FOLDER_F415 := $(HAL_FOLDER)/f415 +TARGETS_$(MCU) := $(call get_targets,$(MCU)) -MCU_F415 := -mcpu=cortex-m4 -mthumb -LDSCRIPT_F415 := $(HAL_FOLDER_F415)/AT32F415x8_FLASH.ld +HAL_FOLDER_$(MCU) := $(HAL_FOLDER)/$(MCU_LC) -SRC_DIR_F415 := \ - $(HAL_FOLDER_F415)/Startup \ - $(HAL_FOLDER_F415)/Src \ - $(HAL_FOLDER_F415)/Drivers/drivers/src +MCU_$(MCU) := -mcpu=cortex-m4 -mthumb +LDSCRIPT_$(MCU) := $(wildcard $(HAL_FOLDER_$(MCU))/*.ld) -CFLAGS_F415 := \ - -I$(HAL_FOLDER_F415)/Inc \ - -I$(HAL_FOLDER_F415)/Drivers/drivers/inc \ - -I$(HAL_FOLDER_F415)/Drivers/CMSIS/cm4/core_support \ - -I$(HAL_FOLDER_F415)/Drivers/CMSIS/cm4/device_support +SRC_BASE_DIR_$(MCU) := \ + $(HAL_FOLDER_$(MCU))/Startup \ + $(HAL_FOLDER_$(MCU))/Drivers/drivers/src -CFLAGS_F415 += \ - -DAT32F415K8U7_4 \ - -DUSE_STDPERIPH_DRIVER +SRC_DIR_$(MCU) := $(SRC_BASE_DIR_$(MCU)) \ + $(HAL_FOLDER_$(MCU))/Src + +CFLAGS_$(MCU) := \ + -I$(HAL_FOLDER_$(MCU))/Inc \ + -I$(HAL_FOLDER_$(MCU))/Drivers/drivers/inc \ + -I$(HAL_FOLDER_$(MCU))/Drivers/CMSIS/cm4/core_support \ + -I$(HAL_FOLDER_$(MCU))/Drivers/CMSIS/cm4/device_support +CFLAGS_$(MCU) += \ + -D$(PART) \ + -DUSE_STDPERIPH_DRIVER -SRC_F415 := $(foreach dir,$(SRC_DIR_F415),$(wildcard $(dir)/*.[cs])) +SRC_$(MCU) := $(foreach dir,$(SRC_DIR_$(MCU)),$(wildcard $(dir)/*.[cs])) +SRC_$(MCU)_BL := $(foreach dir,$(SRC_BASE_DIR_$(MCU)),$(wildcard $(dir)/*.[cs])) \ + $(HAL_FOLDER_$(MCU))/Src/eeprom.c \ + $(wildcard $(HAL_FOLDER_$(MCU))/*_it.c) diff --git a/f421makefile.mk b/f421makefile.mk index 26c2f8e94..04612642f 100644 --- a/f421makefile.mk +++ b/f421makefile.mk @@ -1,25 +1,33 @@ +MCU := F421 +PART := AT32F421K8U7 -TARGETS_F421 := $(call get_targets,F421) +MCU_LC := $(call lc,$(MCU)) -HAL_FOLDER_F421 := $(HAL_FOLDER)/f421 +TARGETS_$(MCU) := $(call get_targets,$(MCU)) -MCU_F421 := -mcpu=cortex-m4 -mthumb -LDSCRIPT_F421 := $(HAL_FOLDER_F421)/AT32F421x6_FLASH.ld +HAL_FOLDER_$(MCU) := $(HAL_FOLDER)/$(MCU_LC) -SRC_DIR_F421 := \ - $(HAL_FOLDER_F421)/Startup \ - $(HAL_FOLDER_F421)/Src \ - $(HAL_FOLDER_F421)/Drivers/drivers/src +MCU_$(MCU) := -mcpu=cortex-m4 -mthumb +LDSCRIPT_$(MCU) := $(wildcard $(HAL_FOLDER_$(MCU))/*.ld) -CFLAGS_F421 := \ - -I$(HAL_FOLDER_F421)/Inc \ - -I$(HAL_FOLDER_F421)/Drivers/drivers/inc \ - -I$(HAL_FOLDER_F421)/Drivers/CMSIS/cm4/core_support \ - -I$(HAL_FOLDER_F421)/Drivers/CMSIS/cm4/device_support +SRC_BASE_DIR_$(MCU) := \ + $(HAL_FOLDER_$(MCU))/Startup \ + $(HAL_FOLDER_$(MCU))/Drivers/drivers/src -CFLAGS_F421 += \ - -DAT32F421K8U7 \ - -DUSE_STDPERIPH_DRIVER +SRC_DIR_$(MCU) := $(SRC_BASE_DIR_$(MCU)) \ + $(HAL_FOLDER_$(MCU))/Src + +CFLAGS_$(MCU) := \ + -I$(HAL_FOLDER_$(MCU))/Inc \ + -I$(HAL_FOLDER_$(MCU))/Drivers/drivers/inc \ + -I$(HAL_FOLDER_$(MCU))/Drivers/CMSIS/cm4/core_support \ + -I$(HAL_FOLDER_$(MCU))/Drivers/CMSIS/cm4/device_support +CFLAGS_$(MCU) += \ + -D$(PART) \ + -DUSE_STDPERIPH_DRIVER -SRC_F421 := $(foreach dir,$(SRC_DIR_F421),$(wildcard $(dir)/*.[cs])) +SRC_$(MCU) := $(foreach dir,$(SRC_DIR_$(MCU)),$(wildcard $(dir)/*.[cs])) +SRC_$(MCU)_BL := $(foreach dir,$(SRC_BASE_DIR_$(MCU)),$(wildcard $(dir)/*.[cs])) \ + $(HAL_FOLDER_$(MCU))/Src/eeprom.c \ + $(wildcard $(HAL_FOLDER_$(MCU))/*_it.c) diff --git a/g071makefile.mk b/g071makefile.mk index c4b64e4a7..1509f8e66 100644 --- a/g071makefile.mk +++ b/g071makefile.mk @@ -1,25 +1,31 @@ +MCU := G071 +PART := STM32G071xx -TARGETS_F071 := $(call get_targets,G071) +MCU_LC := $(call lc,$(MCU)) -HAL_FOLDER_G071 := $(HAL_FOLDER)/g071 +TARGETS_$(MCU) := $(call get_targets,$(MCU)) -MCU_G071 := -mcpu=cortex-m0 -mthumb -LDSCRIPT_G071 := $(HAL_FOLDER_G071)/STM32G071GBUX_FLASH.ld +HAL_FOLDER_$(MCU) := $(HAL_FOLDER)/$(MCU_LC) -SRC_DIR_G071 := \ - $(HAL_FOLDER_G071)/Startup \ - $(HAL_FOLDER_G071)/Src \ - $(HAL_FOLDER_G071)/Drivers/STM32G0xx_HAL_Driver/Src +MCU_$(MCU) := -mcpu=cortex-m0 -mthumb +LDSCRIPT_$(MCU) := $(wildcard $(HAL_FOLDER_$(MCU))/*.ld) -CFLAGS_G071 := \ - -I$(HAL_FOLDER_G071)/Inc \ - -I$(HAL_FOLDER_G071)/Drivers/STM32G0xx_HAL_Driver/Inc \ - -I$(HAL_FOLDER_G071)/Drivers/CMSIS/Include \ - -I$(HAL_FOLDER_G071)/Drivers/CMSIS/Device/ST/STM32G0xx/Include +SRC_BASE_DIR_$(MCU) := \ + $(HAL_FOLDER_$(MCU))/Startup \ + $(HAL_FOLDER_$(MCU))/Drivers/STM32G0xx_HAL_Driver/Src -CFLAGS_G071 += \ +SRC_DIR_$(MCU) := $(SRC_BASE_DIR_$(MCU)) \ + $(HAL_FOLDER_$(MCU))/Src + +CFLAGS_$(MCU) := \ + -I$(HAL_FOLDER_$(MCU))/Inc \ + -I$(HAL_FOLDER_$(MCU))/Drivers/STM32G0xx_HAL_Driver/Inc \ + -I$(HAL_FOLDER_$(MCU))/Drivers/CMSIS/Include \ + -I$(HAL_FOLDER_$(MCU))/Drivers/CMSIS/Device/ST/STM32G0xx/Include + +CFLAGS_$(MCU) += \ -DHSE_VALUE=8000000 \ - -DSTM32G071xx \ + -D$(PART) \ -DHSE_STARTUP_TIMEOUT=100 \ -DLSE_STARTUP_TIMEOUT=5000 \ -DLSE_VALUE=32768 \ @@ -31,4 +37,8 @@ CFLAGS_G071 += \ -DUSE_FULL_LL_DRIVER \ -DPREFETCH_ENABLE=1 -SRC_G071 := $(foreach dir,$(SRC_DIR_G071),$(wildcard $(dir)/*.[cs])) +SRC_$(MCU) := $(foreach dir,$(SRC_DIR_$(MCU)),$(wildcard $(dir)/*.[cs])) + +SRC_$(MCU)_BL := $(foreach dir,$(SRC_BASE_DIR_$(MCU)),$(wildcard $(dir)/*.[cs])) \ + $(HAL_FOLDER_$(MCU))/Src/eeprom.c \ + $(wildcard $(HAL_FOLDER_$(MCU))/*_it.c) From 7c64e5c1851e164797be8629db4949ff03588bb4 Mon Sep 17 00:00:00 2001 From: Andrew Tridgell Date: Sat, 27 Jul 2024 19:38:15 +1000 Subject: [PATCH 07/11] CI: build bootloaders in CI --- .github/workflows/CI_build.yml | 1 + .github/workflows/CI_build_windows.yml | 1 + 2 files changed, 2 insertions(+) diff --git a/.github/workflows/CI_build.yml b/.github/workflows/CI_build.yml index 7b11d8880..81fa3eec1 100644 --- a/.github/workflows/CI_build.yml +++ b/.github/workflows/CI_build.yml @@ -15,6 +15,7 @@ jobs: run: | make arm_sdk_install make -j8 + make bootloaders -j8 - name: Archive build uses: actions/upload-artifact@v3 diff --git a/.github/workflows/CI_build_windows.yml b/.github/workflows/CI_build_windows.yml index ecfd63dec..e3b40bb8e 100644 --- a/.github/workflows/CI_build_windows.yml +++ b/.github/workflows/CI_build_windows.yml @@ -15,6 +15,7 @@ jobs: run: | make arm_sdk_install tools/windows/make/bin/make + tools/windows/make/bin/make bootloaders - name: Archive build uses: actions/upload-artifact@v3 From 366481a996437a9f2473cd7140226d99a3d2f0ab Mon Sep 17 00:00:00 2001 From: Andrew Tridgell Date: Sun, 28 Jul 2024 11:04:49 +1000 Subject: [PATCH 08/11] build: removed recursive make generate targets separately, avoiding the need to recursively call make This also fixes disabling quiet, like this: make FOXEER_F421 QUIET= also see "Recursive Make Considered Harmful" paper by Peter Miller --- Makefile | 64 +++++++++++++++++++++++++------------------------------- 1 file changed, 28 insertions(+), 36 deletions(-) diff --git a/Makefile b/Makefile index 6ac31e8eb..41efdc1b5 100644 --- a/Makefile +++ b/Makefile @@ -50,7 +50,7 @@ FIRMWARE_VERSION := $(VERSION_MAJOR).$(VERSION_MINOR) CFLAGS_BASE := -DUSE_MAKE -fsingle-precision-constant -fomit-frame-pointer -ffast-math CFLAGS_BASE += -I$(MAIN_INC_DIR) -g3 -O3 -Wall -ffunction-sections -CFLAGS_COMMON := $(CFLAGS_BASE) -D$(TARGET) +CFLAGS_COMMON := $(CFLAGS_BASE) # Linker options LDFLAGS_COMMON := -specs=nano.specs $(LIBS) -Wl,--gc-sections -Wl,--print-memory-usage @@ -58,9 +58,6 @@ LDFLAGS_COMMON := -specs=nano.specs $(LIBS) -Wl,--gc-sections -Wl,--print-memory # Search source files SRC_COMMON := $(foreach dir,$(SRC_DIRS_COMMON),$(wildcard $(dir)/*.[cs])) -TARGET_FNAME = $(IDENTIFIER)_$(TARGET)_$(FIRMWARE_VERSION) -TARGET_BASENAME = $(BIN_DIR)/$(TARGET_FNAME) - # configure some directories that are relative to wherever ROOT_DIR is located OBJ := obj BIN_DIR := $(ROOT)/$(OBJ) @@ -79,45 +76,37 @@ clean : @echo Removing $(OBJ) directory @$(RM) -rf $(OBJ) +##################### +# main firmware build +define CREATE_BUILD_TARGET +$(2)_BASENAME = $(BIN_DIR)/$(IDENTIFIER)_$(2)_$(FIRMWARE_VERSION) + +$(2) : $$($(2)_BASENAME).bin + +# Generate bin and hex files from elf +$$($(2)_BASENAME).bin: $$($(2)_BASENAME).elf + echo building BIN $$@ + @$(ECHO) Generating $$(notdir $$@) + $(QUIET)$(OBJCOPY) -O binary $$(<) $$@ + $(QUIET)$(OBJCOPY) $$(<) -O ihex $$(@:.bin=.hex) -binary : $(TARGET_BASENAME).bin +CFLAGS_$(2) = $(MCU_$(1)) -D$(2) $(CFLAGS_$(1)) $(CFLAGS_COMMON) +LDFLAGS_$(2) = $(LDFLAGS_COMMON) $(LDFLAGS_$(1)) -T$(LDSCRIPT_$(1)) + +$$($(2)_BASENAME).elf: $(SRC_COMMON) $$(SRC_$(1)) + @$(ECHO) Compiling $$(notdir $$@) + $(QUIET)$(MKDIR) -p $(OBJ) + $(QUIET)$(CC) $$(CFLAGS_$(2)) $$(LDFLAGS_$(2)) -MMD -MP -MF $$(@:.elf=.d) -o $$(@) $(SRC_COMMON) $$(SRC_$(1)) # we copy debug.elf to give us a constant debug target for vscode # this means the debug button will always debug the last target built - @$(CP) -f $(OBJ)$(DSEP)$(TARGET_FNAME).elf $(OBJ)$(DSEP)debug.elf > $(NUL) + @$(CP) -f $$(@) $(OBJ)$(DSEP)debug.elf > $(NUL) # also copy the openocd.cfg from the MCU directory to obj/openocd.cfg for auto config of Cortex-Debug # in vscode - @$(CP) -f Mcu$(DSEP)$(call lc,$(MCU_TYPE))$(DSEP)openocd.cfg $(OBJ)$(DSEP)openocd.cfg > $(NUL) - @$(ECHO) done $(TARGET) - -# create targets compiling each MCU types targets -define CREATE_MCU_TARGETS -$$(TARGETS_$(1)) : - @$$(MAKE) -s MCU_TYPE=$(1) TARGET=$$@ binary -endef -$(foreach MCU,$(MCU_TYPES),$(eval $(call CREATE_MCU_TARGETS,$(MCU)))) - - -# Compile target -$(TARGET_BASENAME).elf: CFLAGS := $(MCU_$(MCU_TYPE)) $(CFLAGS_$(MCU_TYPE)) $(CFLAGS_COMMON) -$(TARGET_BASENAME).elf: LDFLAGS := $(LDFLAGS_COMMON) $(LDFLAGS_$(MCU_TYPE)) -T$(LDSCRIPT_$(MCU_TYPE)) -$(TARGET_BASENAME).elf: $(SRC_COMMON) $(SRC_$(MCU_TYPE)) - @$(ECHO) Compiling $(notdir $@) - $(QUIRT)$(MKDIR) -p $(OBJ) - $(QUIET)$(CC) $(CFLAGS) $(LDFLAGS) -MMD -MP -MF $(@:.elf=.d) -o $(@) $(SRC_COMMON) $(SRC_$(MCU_TYPE)) - -# Generate bin and hex files -$(TARGET_BASENAME).bin: $(TARGET_BASENAME).elf - @$(ECHO) Generating $(notdir $@) - $(QUIET)$(OBJCOPY) -O binary $(<) $@ - $(QUIET)$(OBJCOPY) $(<) -O ihex $(@:.bin=.hex) - -# include the targets for installing tools -include $(ROOT)/make/tools_install.mk - -define SHOW_MCU_TARGETS -$(1) Targets $(TARGETS_$(1))\n + @$(CP) -f Mcu$(DSEP)$(call lc,$(1))$(DSEP)openocd.cfg $(OBJ)$(DSEP)openocd.cfg > $(NUL) endef +$(foreach MCU,$(MCU_TYPES),$(foreach TARGET,$(TARGETS_$(MCU)), $(eval $(call CREATE_BUILD_TARGET,$(MCU),$(TARGET))))) +################## # bootloader build BOOTLOADER_VERSION := $(shell $(FGREP) "define BOOTLOADER_VERSION" $(MAIN_INC_DIR)/version.h | $(CUT) -d" " -f3 ) @@ -163,6 +152,9 @@ ALL_BOOTLOADERS := $(foreach MCU,$(BL_MCU_TYPES),$(foreach PIN,$(BOOTLOADER_PINS bootloaders: $(ALL_BOOTLOADERS) +# include the targets for installing tools +include $(ROOT)/make/tools_install.mk + # useful target to list all of the board targets so you can see what # make target to use for your board targets: From 5a13d38ed1d2225a4152fb5540f4a819adf5ab4f Mon Sep 17 00:00:00 2001 From: Ian Murphy Date: Sat, 27 Jul 2024 11:34:14 +0100 Subject: [PATCH 09/11] Builds G431 in Keil & make. B-G431-ESC1 target added. Compiles with warnings & notes. Not tested on hardware. --- Inc/targets.h | 10 + Keil_Projects/Am32G431.uvoptx | 274 +++++- Keil_Projects/Am32G431.uvprojx | 613 +++++++++++- Makefile | 2 +- .../Src/stm32g4xx_ll_fmc.c | 806 --------------- .../Src/stm32g4xx_ll_usb.c | 915 ------------------ Mcu/g431/STM32G431CBUX_FLASH.ld | 209 ++++ .../Startup/{ => mdk}/startup_stm32g431xx.s | 0 g431makefile.mk | 34 + 9 files changed, 1135 insertions(+), 1728 deletions(-) delete mode 100644 Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_fmc.c delete mode 100644 Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c create mode 100644 Mcu/g431/STM32G431CBUX_FLASH.ld rename Mcu/g431/Startup/{ => mdk}/startup_stm32g431xx.s (100%) create mode 100644 g431makefile.mk diff --git a/Inc/targets.h b/Inc/targets.h index 8ee6f1fdd..efca20831 100644 --- a/Inc/targets.h +++ b/Inc/targets.h @@ -106,6 +106,16 @@ // #define USE_SERIAL_TELEMETRY #endif +#ifdef B_G431_ESC1 +#define FIRMWARE_NAME "B-G431-ESC1 " +#define FILE_NAME "B_G431_ESC1" +#define DEAD_TIME 80 +#define HARDWARE_GROUP_G4_A +#define TARGET_STALL_PROTECTION_INTERVAL 20000 +// #define PA6_VOLTAGE +// #define USE_SERIAL_TELEMETRY +#endif + #ifdef GD32DEV_A_E230 #define FIRMWARE_NAME "GD32 Dev A " #define FILE_NAME "GD32DEV_A_E230" diff --git a/Keil_Projects/Am32G431.uvoptx b/Keil_Projects/Am32G431.uvoptx index 4fdb786a9..e464c3a0c 100644 --- a/Keil_Projects/Am32G431.uvoptx +++ b/Keil_Projects/Am32G431.uvoptx @@ -73,7 +73,277 @@ 0 - 1 + 0 + 0 + 0 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=157,189,753,874,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC8000 -FN1 -FF0STM32G43x-4x_128 -FS08000000 -FL020000 -FP0($$Device:STM32G431KBUx$CMSIS\Flash\STM32G43x-4x_128.FLM)) + + + 0 + ST-LINKIII-KEIL_SWO + -U-O142 -O2254 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(2BA01477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32G43x-4x_128.FLM -FS08000000 -FL020000 -FP0($$Device:STM32G431KBUx$CMSIS\Flash\STM32G43x-4x_128.FLM) -WA0 -WE0 -WVCE4 -WS2710 -WM0 -WP2 + + + + + + 0 + 1 + signaltimeout + + + 1 + 1 + armed + + + 2 + 1 + smallestnumber,0x0A + + + 3 + 1 + dshot + + + 4 + 1 + input + + + 5 + 1 + newinput,0x0A + + + 6 + 1 + stepper_sine + + + 7 + 1 + use_sin_start + + + 8 + 1 + eepromBuffer + + + 9 + 1 + stall_protection,0x0A + + + 10 + 1 + commutation_interval,0x0A + + + 11 + 1 + interrupt + + + 12 + 1 + dma_buffer + + + 13 + 1 + ADCDataDMA,0x0A + + + 14 + 1 + degrees_celsius,0x0A + + + 15 + 1 + ADC_raw_temp + + + + + 1 + 0 + 40015804 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 10000000 + + + + + + B_G431_ESC1 + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 0 1 @@ -304,7 +574,7 @@ 0 0 0 - ..\Mcu\g431\Startup\startup_stm32g431xx.s + ..\Mcu\g431\Startup\mdk\startup_stm32g431xx.s startup_stm32g431xx.s 0 0 diff --git a/Keil_Projects/Am32G431.uvprojx b/Keil_Projects/Am32G431.uvprojx index 9a90e578e..afdf91837 100644 --- a/Keil_Projects/Am32G431.uvprojx +++ b/Keil_Projects/Am32G431.uvprojx @@ -10,14 +10,618 @@ G431_test 0x4 ARM-ADS - 6190000::V6.19::ARMCLANG - 6190000::V6.19::ARMCLANG + 6220000::V6.22::ARMCLANG 1 STM32G431KBUx STMicroelectronics - Keil.STM32G4xx_DFP.1.5.0 + Keil.STM32G4xx_DFP.1.6.0 + https://www.keil.com/pack/ + IRAM(0x20000000-0x20007FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4") TZ + + + + 0 + + + + + + + + + + + $$Device:STM32G431KBUx$CMSIS\SVD\STM32G431xx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + B_G431_ESC1 + 1 + 0 + 1 + 1 + 1 + + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4101 + + 1 + BIN\UL2V8M.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 3 + 5 + 1 + 1 + 0 + 0 + 0 + + + B_G431_ESC1, USE_FULL_LL_DRIVER,HSE_VALUE=8000000,HSE_STARTUP_TIMEOUT=100,LSE_STARTUP_TIMEOUT=5000,LSE_VALUE=32768,EXTERNAL_CLOCK_VALUE=12288000,HSI_VALUE=16000000,LSI_VALUE=32000,VDD_VALUE=3300,PREFETCH_ENABLE=0,INSTRUCTION_CACHE_ENABLE=1,DATA_CACHE_ENABLE=1,STM32G431xx + + ..\Mcu\g431\Drivers\STM32G4xx_HAL_Driver\Inc;..\Mcu\g431\Drivers\CMSIS\Device\ST\STM32G4xx\Include;..\Inc;..\Mcu\g431\Inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + + + + ..\Mcu\g431\Am32_64kb_g431.sct + + + + + + + + + + + startup + + + startup_stm32g431xx.s + 2 + ..\Mcu\g431\Startup\mdk\startup_stm32g431xx.s + + + + + Drivers + + + stm32g4xx_ll_adc.c + 1 + ..\Mcu\g431\Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_adc.c + + + stm32g4xx_ll_comp.c + 1 + ..\Mcu\g431\Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_comp.c + + + stm32g4xx_ll_cordic.c + 1 + ..\Mcu\g431\Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_cordic.c + + + stm32g4xx_ll_crc.c + 1 + ..\Mcu\g431\Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_crc.c + + + stm32g4xx_ll_crs.c + 1 + ..\Mcu\g431\Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_crs.c + + + stm32g4xx_ll_dac.c + 1 + ..\Mcu\g431\Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_dac.c + + + stm32g4xx_ll_dma.c + 1 + ..\Mcu\g431\Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_dma.c + + + stm32g4xx_ll_exti.c + 1 + ..\Mcu\g431\Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_exti.c + + + stm32g4xx_ll_fmac.c + 1 + ..\Mcu\g431\Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_fmac.c + + + stm32g4xx_ll_gpio.c + 1 + ..\Mcu\g431\Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_gpio.c + + + stm32g4xx_ll_hrtim.c + 1 + ..\Mcu\g431\Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_hrtim.c + + + stm32g4xx_ll_i2c.c + 1 + ..\Mcu\g431\Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_i2c.c + + + stm32g4xx_ll_lptim.c + 1 + ..\Mcu\g431\Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_lptim.c + + + stm32g4xx_ll_lpuart.c + 1 + ..\Mcu\g431\Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_lpuart.c + + + stm32g4xx_ll_opamp.c + 1 + ..\Mcu\g431\Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_opamp.c + + + stm32g4xx_ll_pwr.c + 1 + ..\Mcu\g431\Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_pwr.c + + + stm32g4xx_ll_rcc.c + 1 + ..\Mcu\g431\Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_rcc.c + + + stm32g4xx_ll_rng.c + 1 + ..\Mcu\g431\Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_rng.c + + + stm32g4xx_ll_rtc.c + 1 + ..\Mcu\g431\Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_rtc.c + + + stm32g4xx_ll_spi.c + 1 + ..\Mcu\g431\Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_spi.c + + + stm32g4xx_ll_tim.c + 1 + ..\Mcu\g431\Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_tim.c + + + stm32g4xx_ll_ucpd.c + 1 + ..\Mcu\g431\Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_ucpd.c + + + stm32g4xx_ll_usart.c + 1 + ..\Mcu\g431\Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_usart.c + + + stm32g4xx_ll_utils.c + 1 + ..\Mcu\g431\Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_utils.c + + + + + Src + + + dshot.c + 1 + ..\Src\dshot.c + + + firmwareversion.c + 1 + ..\Src\firmwareversion.c + + + functions.c + 1 + ..\Src\functions.c + + + main.c + 1 + ..\Src\main.c + + + signal.c + 1 + ..\Src\signal.c + + + sounds.c + 1 + ..\Src\sounds.c + + + + + Mcu + + + ADC.c + 1 + ..\Mcu\g431\Src\ADC.c + + + comparator.c + 1 + ..\Mcu\g431\Src\comparator.c + + + eeprom.c + 1 + ..\Mcu\g431\Src\eeprom.c + + + IO.c + 1 + ..\Mcu\g431\Src\IO.c + + + peripherals.c + 1 + ..\Mcu\g431\Src\peripherals.c + + + phaseouts.c + 1 + ..\Mcu\g431\Src\phaseouts.c + + + serial_telemetry.c + 1 + ..\Mcu\g431\Src\serial_telemetry.c + + + stm32g4xx_it.c + 1 + ..\Mcu\g431\Src\stm32g4xx_it.c + + + system_stm32g4xx.c + 1 + ..\Mcu\g431\Src\system_stm32g4xx.c + + + WS2812.c + 1 + ..\Mcu\g431\Src\WS2812.c + + + + + ::CMSIS + + + + + B_G431_ESC1 + 0x4 + ARM-ADS + 6220000::V6.22::ARMCLANG + 1 + + + STM32G431KBUx + STMicroelectronics + Keil.STM32G4xx_DFP.1.6.0 https://www.keil.com/pack/ IRAM(0x20000000-0x20007FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4") TZ @@ -388,7 +992,7 @@ startup_stm32g431xx.s 2 - ..\Mcu\g431\Startup\startup_stm32g431xx.s + ..\Mcu\g431\Startup\mdk\startup_stm32g431xx.s @@ -620,6 +1224,7 @@ + diff --git a/Makefile b/Makefile index 41efdc1b5..6976fa0e4 100644 --- a/Makefile +++ b/Makefile @@ -23,7 +23,7 @@ ROOT := $(patsubst %/,%,$(dir $(lastword $(MAKEFILE_LIST)))) include $(ROOT)/make/tools.mk # supported MCU types -MCU_TYPES := E230 F031 F051 F415 F421 G071 +MCU_TYPES := E230 F031 F051 F415 F421 G071 G431 MCU_TYPE := NONE # MCU types that we build a bootloader for - this should be $(MCU_TYPES) in the future diff --git a/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_fmc.c b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_fmc.c deleted file mode 100644 index 2a6a2f601..000000000 --- a/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_fmc.c +++ /dev/null @@ -1,806 +0,0 @@ -/** - ****************************************************************************** - * @file stm32g4xx_ll_fmc.c - * @author MCD Application Team - * @brief FMC Low Layer HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the Flexible Memory Controller (FMC) peripheral memories: - * + Initialization/de-initialization functions - * + Peripheral Control functions - * + Peripheral State functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2019 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### FMC peripheral features ##### - ============================================================================== - [..] The Flexible memory controller (FMC) includes following memory controllers: - (+) The NOR/PSRAM memory controller - (+) The NAND memory controller - - [..] The FMC functional block makes the interface with synchronous and asynchronous static - memories. Its main purposes are: - (+) to translate AHB transactions into the appropriate external device protocol - (+) to meet the access time requirements of the external memory devices - - [..] All external memories share the addresses, data and control signals with the controller. - Each external device is accessed by means of a unique Chip Select. The FMC performs - only one access at a time to an external device. - The main features of the FMC controller are the following: - (+) Interface with static-memory mapped devices including: - (++) Static random access memory (SRAM) - (++) Read-only memory (ROM) - (++) NOR Flash memory/OneNAND Flash memory - (++) PSRAM (4 memory banks) - (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of - data - (+) Independent Chip Select control for each memory bank - (+) Independent configuration for each memory bank - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32g4xx_hal.h" - -/** @addtogroup STM32G4xx_HAL_Driver - * @{ - */ -#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) \ - || defined(HAL_SRAM_MODULE_ENABLED) - -/** @defgroup FMC_LL FMC Low Layer - * @brief FMC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants - * @{ - */ - -/* ----------------------- FMC registers bit mask --------------------------- */ - -#if defined(FMC_BANK1) -/* --- BCR Register ---*/ -/* BCR register clear mask */ - -/* --- BTR Register ---*/ -/* BTR register clear mask */ -#define BTR_CLEAR_MASK ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD |\ - FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\ - FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT |\ - FMC_BTRx_ACCMOD | FMC_BTRx_DATAHLD)) - -/* --- BWTR Register ---*/ -/* BWTR register clear mask */ -#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\ - FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\ - FMC_BWTRx_ACCMOD | FMC_BWTRx_DATAHLD)) -#endif /* FMC_BANK1 */ -#if defined(FMC_BANK3) - -/* --- PCR Register ---*/ -/* PCR register clear mask */ -#define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | \ - FMC_PCR_PTYP | FMC_PCR_PWID | \ - FMC_PCR_ECCEN | FMC_PCR_TCLR | \ - FMC_PCR_TAR | FMC_PCR_ECCPS)) -/* --- PMEM Register ---*/ -/* PMEM register clear mask */ -#define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM_MEMSET | FMC_PMEM_MEMWAIT |\ - FMC_PMEM_MEMHOLD | FMC_PMEM_MEMHIZ)) - -/* --- PATT Register ---*/ -/* PATT register clear mask */ -#define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT_ATTSET | FMC_PATT_ATTWAIT |\ - FMC_PATT_ATTHOLD | FMC_PATT_ATTHIZ)) - -#endif /* FMC_BANK3 */ - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions - * @{ - */ - -#if defined(FMC_BANK1) - -/** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions - * @brief NORSRAM Controller functions - * - @verbatim - ============================================================================== - ##### How to use NORSRAM device driver ##### - ============================================================================== - - [..] - This driver contains a set of APIs to interface with the FMC NORSRAM banks in order - to run the NORSRAM external devices. - - (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit() - (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init() - (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init() - (+) FMC NORSRAM bank extended timing configuration using the function - FMC_NORSRAM_Extended_Timing_Init() - (+) FMC NORSRAM bank enable/disable write operation using the functions - FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable() - -@endverbatim - * @{ - */ - -/** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * - @verbatim - ============================================================================== - ##### Initialization and de_initialization functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the FMC NORSRAM interface - (+) De-initialize the FMC NORSRAM interface - (+) Configure the FMC clock and associated GPIOs - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the FMC_NORSRAM device according to the specified - * control parameters in the FMC_NORSRAM_InitTypeDef - * @param Device Pointer to NORSRAM device instance - * @param Init Pointer to NORSRAM Initialization structure - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_InitTypeDef *Init) -{ - uint32_t flashaccess; - uint32_t btcr_reg; - uint32_t mask; - - /* Check the parameters */ - assert_param(IS_FMC_NORSRAM_DEVICE(Device)); - assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); - assert_param(IS_FMC_MUX(Init->DataAddressMux)); - assert_param(IS_FMC_MEMORY(Init->MemoryType)); - assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); - assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); - assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); - assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); - assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); - assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); - assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode)); - assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait)); - assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst)); - assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); - assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo)); - assert_param(IS_FMC_PAGESIZE(Init->PageSize)); - assert_param(IS_FMC_NBL_SETUPTIME(Init->NBLSetupTime)); - assert_param(IS_FUNCTIONAL_STATE(Init->MaxChipSelectPulse)); - - /* Disable NORSRAM Device */ - __FMC_NORSRAM_DISABLE(Device, Init->NSBank); - - /* Set NORSRAM device control parameters */ - if (Init->MemoryType == FMC_MEMORY_TYPE_NOR) - { - flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE; - } - else - { - flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE; - } - - btcr_reg = (flashaccess | \ - Init->DataAddressMux | \ - Init->MemoryType | \ - Init->MemoryDataWidth | \ - Init->BurstAccessMode | \ - Init->WaitSignalPolarity | \ - Init->WaitSignalActive | \ - Init->WriteOperation | \ - Init->WaitSignal | \ - Init->ExtendedMode | \ - Init->AsynchronousWait | \ - Init->WriteBurst); - - btcr_reg |= Init->ContinuousClock; - btcr_reg |= Init->WriteFifo; - btcr_reg |= Init->NBLSetupTime; - btcr_reg |= Init->PageSize; - - mask = (FMC_BCRx_MBKEN | - FMC_BCRx_MUXEN | - FMC_BCRx_MTYP | - FMC_BCRx_MWID | - FMC_BCRx_FACCEN | - FMC_BCRx_BURSTEN | - FMC_BCRx_WAITPOL | - FMC_BCRx_WAITCFG | - FMC_BCRx_WREN | - FMC_BCRx_WAITEN | - FMC_BCRx_EXTMOD | - FMC_BCRx_ASYNCWAIT | - FMC_BCRx_CBURSTRW); - - mask |= FMC_BCR1_CCLKEN; - mask |= FMC_BCR1_WFDIS; - mask |= FMC_BCRx_NBLSET; - mask |= FMC_BCRx_CPSIZE; - - MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); - - /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */ - if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) - { - MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); - } - - if (Init->NSBank != FMC_NORSRAM_BANK1) - { - /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */ - SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); - } - - /* Check PSRAM chip select counter state */ - if (Init->MaxChipSelectPulse == ENABLE) - { - /* Check the parameters */ - assert_param(IS_FMC_MAX_CHIP_SELECT_PULSE_TIME(Init->MaxChipSelectPulseTime)); - - /* Configure PSRAM chip select counter value */ - MODIFY_REG(Device->PCSCNTR, FMC_PCSCNTR_CSCOUNT, (uint32_t)(Init->MaxChipSelectPulseTime)); - - /* Enable PSRAM chip select counter for the bank */ - switch (Init->NSBank) - { - case FMC_NORSRAM_BANK1 : - SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN); - break; - - case FMC_NORSRAM_BANK2 : - SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN); - break; - - case FMC_NORSRAM_BANK3 : - SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN); - break; - - default : - SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN); - break; - } - } - - return HAL_OK; -} - -/** - * @brief DeInitialize the FMC_NORSRAM peripheral - * @param Device Pointer to NORSRAM device instance - * @param ExDevice Pointer to NORSRAM extended mode device instance - * @param Bank NORSRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NORSRAM_DEVICE(Device)); - assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); - assert_param(IS_FMC_NORSRAM_BANK(Bank)); - - /* Disable the FMC_NORSRAM device */ - __FMC_NORSRAM_DISABLE(Device, Bank); - - /* De-initialize the FMC_NORSRAM device */ - /* FMC_NORSRAM_BANK1 */ - if (Bank == FMC_NORSRAM_BANK1) - { - Device->BTCR[Bank] = 0x000030DBU; - } - /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */ - else - { - Device->BTCR[Bank] = 0x000030D2U; - } - - Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; - ExDevice->BWTR[Bank] = 0x0FFFFFFFU; - - /* De-initialize PSRAM chip select counter */ - switch (Bank) - { - case FMC_NORSRAM_BANK1 : - CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN); - break; - - case FMC_NORSRAM_BANK2 : - CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN); - break; - - case FMC_NORSRAM_BANK3 : - CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN); - break; - - default : - CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN); - break; - } - - return HAL_OK; -} - -/** - * @brief Initialize the FMC_NORSRAM Timing according to the specified - * parameters in the FMC_NORSRAM_TimingTypeDef - * @param Device Pointer to NORSRAM device instance - * @param Timing Pointer to NORSRAM Timing structure - * @param Bank NORSRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) -{ - uint32_t tmpr; - - /* Check the parameters */ - assert_param(IS_FMC_NORSRAM_DEVICE(Device)); - assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); - assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); - assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime)); - assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); - assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); - assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); - assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); - assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); - assert_param(IS_FMC_NORSRAM_BANK(Bank)); - - /* Set FMC_NORSRAM device timing parameters */ - MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime | - ((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) | - ((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) | - ((Timing->DataHoldTime) << FMC_BTRx_DATAHLD_Pos) | - ((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) | - (((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos) | - (((Timing->DataLatency) - 2U) << FMC_BTRx_DATLAT_Pos) | - (Timing->AccessMode))); - - /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ - if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) - { - tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); - tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos); - MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); - } - - return HAL_OK; -} - -/** - * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified - * parameters in the FMC_NORSRAM_TimingTypeDef - * @param Device Pointer to NORSRAM device instance - * @param Timing Pointer to NORSRAM Timing structure - * @param Bank NORSRAM bank number - * @param ExtendedMode FMC Extended Mode - * This parameter can be one of the following values: - * @arg FMC_EXTENDED_MODE_DISABLE - * @arg FMC_EXTENDED_MODE_ENABLE - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, - uint32_t ExtendedMode) -{ - /* Check the parameters */ - assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode)); - - /* Set NORSRAM device timing register for write configuration, if extended mode is used */ - if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE) - { - /* Check the parameters */ - assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); - assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); - assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); - assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); - assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime)); - assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); - assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); - assert_param(IS_FMC_NORSRAM_BANK(Bank)); - - /* Set NORSRAM device timing register for write configuration, if extended mode is used */ - MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime | - ((Timing->AddressHoldTime) << FMC_BWTRx_ADDHLD_Pos) | - ((Timing->DataSetupTime) << FMC_BWTRx_DATAST_Pos) | - ((Timing->DataHoldTime) << FMC_BWTRx_DATAHLD_Pos) | - Timing->AccessMode | - ((Timing->BusTurnAroundDuration) << FMC_BWTRx_BUSTURN_Pos))); - } - else - { - Device->BWTR[Bank] = 0x0FFFFFFFU; - } - - return HAL_OK; -} -/** - * @} - */ - -/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2 - * @brief management functions - * -@verbatim - ============================================================================== - ##### FMC_NORSRAM Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control dynamically - the FMC NORSRAM interface. - -@endverbatim - * @{ - */ - -/** - * @brief Enables dynamically FMC_NORSRAM write operation. - * @param Device Pointer to NORSRAM device instance - * @param Bank NORSRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NORSRAM_DEVICE(Device)); - assert_param(IS_FMC_NORSRAM_BANK(Bank)); - - /* Enable write operation */ - SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); - - return HAL_OK; -} - -/** - * @brief Disables dynamically FMC_NORSRAM write operation. - * @param Device Pointer to NORSRAM device instance - * @param Bank NORSRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NORSRAM_DEVICE(Device)); - assert_param(IS_FMC_NORSRAM_BANK(Bank)); - - /* Disable write operation */ - CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); - - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ -#endif /* FMC_BANK1 */ - -#if defined(FMC_BANK3) - -/** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions - * @brief NAND Controller functions - * - @verbatim - ============================================================================== - ##### How to use NAND device driver ##### - ============================================================================== - [..] - This driver contains a set of APIs to interface with the FMC NAND banks in order - to run the NAND external devices. - - (+) FMC NAND bank reset using the function FMC_NAND_DeInit() - (+) FMC NAND bank control configuration using the function FMC_NAND_Init() - (+) FMC NAND bank common space timing configuration using the function - FMC_NAND_CommonSpace_Timing_Init() - (+) FMC NAND bank attribute space timing configuration using the function - FMC_NAND_AttributeSpace_Timing_Init() - (+) FMC NAND bank enable/disable ECC correction feature using the functions - FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable() - (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC() - -@endverbatim - * @{ - */ - -/** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and de_initialization functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the FMC NAND interface - (+) De-initialize the FMC NAND interface - (+) Configure the FMC clock and associated GPIOs - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the FMC_NAND device according to the specified - * control parameters in the FMC_NAND_HandleTypeDef - * @param Device Pointer to NAND device instance - * @param Init Pointer to NAND Initialization structure - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) -{ - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Init->NandBank)); - assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); - assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); - assert_param(IS_FMC_ECC_STATE(Init->EccComputation)); - assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize)); - assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); - assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); - - /* NAND bank 3 registers configuration */ - MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature | - FMC_PCR_MEMORY_TYPE_NAND | - Init->MemoryDataWidth | - Init->EccComputation | - Init->ECCPageSize | - ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos) | - ((Init->TARSetupTime) << FMC_PCR_TAR_Pos))); - - return HAL_OK; -} - -/** - * @brief Initializes the FMC_NAND Common space Timing according to the specified - * parameters in the FMC_NAND_PCC_TimingTypeDef - * @param Device Pointer to NAND device instance - * @param Timing Pointer to NAND timing structure - * @param Bank NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); - assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); - assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); - assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Prevent unused argument(s) compilation warning if no assert_param check */ - UNUSED(Bank); - - /* NAND bank 3 registers configuration */ - MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime | - ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) | - ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) | - ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos))); - - return HAL_OK; -} - -/** - * @brief Initializes the FMC_NAND Attribute space Timing according to the specified - * parameters in the FMC_NAND_PCC_TimingTypeDef - * @param Device Pointer to NAND device instance - * @param Timing Pointer to NAND timing structure - * @param Bank NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); - assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); - assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); - assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Prevent unused argument(s) compilation warning if no assert_param check */ - UNUSED(Bank); - - /* NAND bank 3 registers configuration */ - MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime | - ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) | - ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) | - ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos))); - - return HAL_OK; -} - -/** - * @brief DeInitializes the FMC_NAND device - * @param Device Pointer to NAND device instance - * @param Bank NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Disable the NAND Bank */ - __FMC_NAND_DISABLE(Device, Bank); - - /* De-initialize the NAND Bank */ - /* Prevent unused argument(s) compilation warning if no assert_param check */ - UNUSED(Bank); - - /* Set the FMC_NAND_BANK3 registers to their reset values */ - WRITE_REG(Device->PCR, 0x00000018U); - WRITE_REG(Device->SR, 0x00000040U); - WRITE_REG(Device->PMEM, 0xFCFCFCFCU); - WRITE_REG(Device->PATT, 0xFCFCFCFCU); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup HAL_FMC_NAND_Group2 Peripheral Control functions - * @brief management functions - * -@verbatim - ============================================================================== - ##### FMC_NAND Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control dynamically - the FMC NAND interface. - -@endverbatim - * @{ - */ - - -/** - * @brief Enables dynamically FMC_NAND ECC feature. - * @param Device Pointer to NAND device instance - * @param Bank NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Enable ECC feature */ - /* Prevent unused argument(s) compilation warning if no assert_param check */ - UNUSED(Bank); - - SET_BIT(Device->PCR, FMC_PCR_ECCEN); - - return HAL_OK; -} - - -/** - * @brief Disables dynamically FMC_NAND ECC feature. - * @param Device Pointer to NAND device instance - * @param Bank NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Disable ECC feature */ - /* Prevent unused argument(s) compilation warning if no assert_param check */ - UNUSED(Bank); - - CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN); - - return HAL_OK; -} - -/** - * @brief Disables dynamically FMC_NAND ECC feature. - * @param Device Pointer to NAND device instance - * @param ECCval Pointer to ECC value - * @param Bank NAND bank number - * @param Timeout Timeout wait value - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, - uint32_t Timeout) -{ - uint32_t tickstart; - - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until FIFO is empty */ - while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - return HAL_TIMEOUT; - } - } - } - - /* Prevent unused argument(s) compilation warning if no assert_param check */ - UNUSED(Bank); - - /* Get the ECCR register value */ - *ECCval = (uint32_t)Device->ECCR; - - return HAL_OK; -} - -/** - * @} - */ -#endif /* FMC_BANK3 */ - - - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_NOR_MODULE_ENABLED */ -/** - * @} - */ -/** - * @} - */ diff --git a/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c deleted file mode 100644 index 61a3edb09..000000000 --- a/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c +++ /dev/null @@ -1,915 +0,0 @@ -/** - ****************************************************************************** - * @file stm32g4xx_ll_usb.c - * @author MCD Application Team - * @brief USB Low Layer HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the USB Peripheral Controller: - * + Initialization/de-initialization functions - * + I/O operation functions - * + Peripheral Control functions - * + Peripheral State functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2019 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Fill parameters of Init structure in USB_CfgTypeDef structure. - - (#) Call USB_CoreInit() API to initialize the USB Core peripheral. - - (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes. - - @endverbatim - - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32g4xx_hal.h" - -/** @addtogroup STM32G4xx_LL_USB_DRIVER - * @{ - */ - -#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) -#if defined (USB) -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** - * @brief Initializes the USB Core - * @param USBx USB Instance - * @param cfg pointer to a USB_CfgTypeDef structure that contains - * the configuration information for the specified USBx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(cfg); - - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - return HAL_OK; -} - -/** - * @brief USB_EnableGlobalInt - * Enables the controller's Global Int in the AHB Config reg - * @param USBx Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) -{ - uint32_t winterruptmask; - - /* Clear pending interrupts */ - USBx->ISTR = 0U; - - /* Set winterruptmask variable */ - winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | - USB_CNTR_SUSPM | USB_CNTR_ERRM | - USB_CNTR_SOFM | USB_CNTR_ESOFM | - USB_CNTR_RESETM | USB_CNTR_L1REQM; - - /* Set interrupt mask */ - USBx->CNTR = (uint16_t)winterruptmask; - - return HAL_OK; -} - -/** - * @brief USB_DisableGlobalInt - * Disable the controller's Global Int in the AHB Config reg - * @param USBx Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) -{ - uint32_t winterruptmask; - - /* Set winterruptmask variable */ - winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | - USB_CNTR_SUSPM | USB_CNTR_ERRM | - USB_CNTR_SOFM | USB_CNTR_ESOFM | - USB_CNTR_RESETM | USB_CNTR_L1REQM; - - /* Clear interrupt mask */ - USBx->CNTR &= (uint16_t)(~winterruptmask); - - return HAL_OK; -} - -/** - * @brief USB_SetCurrentMode Set functional mode - * @param USBx Selected device - * @param mode current core mode - * This parameter can be one of the these values: - * @arg USB_DEVICE_MODE Peripheral mode - * @retval HAL status - */ -HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(mode); - - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - return HAL_OK; -} - -/** - * @brief USB_DevInit Initializes the USB controller registers - * for device mode - * @param USBx Selected device - * @param cfg pointer to a USB_CfgTypeDef structure that contains - * the configuration information for the specified USBx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(cfg); - - /* Init Device */ - /* CNTR_FRES = 1 */ - USBx->CNTR = (uint16_t)USB_CNTR_FRES; - - /* CNTR_FRES = 0 */ - USBx->CNTR = 0U; - - /* Clear pending interrupts */ - USBx->ISTR = 0U; - - /*Set Btable Address*/ - USBx->BTABLE = BTABLE_ADDRESS; - - return HAL_OK; -} - -/** - * @brief USB_FlushTxFifo : Flush a Tx FIFO - * @param USBx : Selected device - * @param num : FIFO number - * This parameter can be a value from 1 to 15 - 15 means Flush all Tx FIFOs - * @retval HAL status - */ -HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef const *USBx, uint32_t num) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(num); - - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - return HAL_OK; -} - -/** - * @brief USB_FlushRxFifo : Flush Rx FIFO - * @param USBx : Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef const *USBx) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - return HAL_OK; -} - - -#if defined (HAL_PCD_MODULE_ENABLED) -/** - * @brief Activate and configure an endpoint - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) -{ - HAL_StatusTypeDef ret = HAL_OK; - uint16_t wEpRegVal; - - wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK; - - /* initialize Endpoint */ - switch (ep->type) - { - case EP_TYPE_CTRL: - wEpRegVal |= USB_EP_CONTROL; - break; - - case EP_TYPE_BULK: - wEpRegVal |= USB_EP_BULK; - break; - - case EP_TYPE_INTR: - wEpRegVal |= USB_EP_INTERRUPT; - break; - - case EP_TYPE_ISOC: - wEpRegVal |= USB_EP_ISOCHRONOUS; - break; - - default: - ret = HAL_ERROR; - break; - } - - PCD_SET_ENDPOINT(USBx, ep->num, (wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); - - PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num); - - if (ep->doublebuffer == 0U) - { - if (ep->is_in != 0U) - { - /*Set the endpoint Transmit buffer address */ - PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress); - PCD_CLEAR_TX_DTOG(USBx, ep->num); - - if (ep->type != EP_TYPE_ISOC) - { - /* Configure NAK status for the Endpoint */ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); - } - else - { - /* Configure TX Endpoint to disabled state */ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); - } - } - else - { - /* Set the endpoint Receive buffer address */ - PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress); - - /* Set the endpoint Receive buffer counter */ - PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket); - PCD_CLEAR_RX_DTOG(USBx, ep->num); - - if (ep->num == 0U) - { - /* Configure VALID status for EP0 */ - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); - } - else - { - /* Configure NAK status for OUT Endpoint */ - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK); - } - } - } -#if (USE_USB_DOUBLE_BUFFER == 1U) - /* Double Buffer */ - else - { - if (ep->type == EP_TYPE_BULK) - { - /* Set bulk endpoint as double buffered */ - PCD_SET_BULK_EP_DBUF(USBx, ep->num); - } - else - { - /* Set the ISOC endpoint in double buffer mode */ - PCD_CLEAR_EP_KIND(USBx, ep->num); - } - - /* Set buffer address for double buffered mode */ - PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1); - - if (ep->is_in == 0U) - { - /* Clear the data toggle bits for the endpoint IN/OUT */ - PCD_CLEAR_RX_DTOG(USBx, ep->num); - PCD_CLEAR_TX_DTOG(USBx, ep->num); - - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); - } - else - { - /* Clear the data toggle bits for the endpoint IN/OUT */ - PCD_CLEAR_RX_DTOG(USBx, ep->num); - PCD_CLEAR_TX_DTOG(USBx, ep->num); - - if (ep->type != EP_TYPE_ISOC) - { - /* Configure NAK status for the Endpoint */ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); - } - else - { - /* Configure TX Endpoint to disabled state */ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); - } - - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); - } - } -#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - - return ret; -} - -/** - * @brief De-activate and de-initialize an endpoint - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) -{ - if (ep->doublebuffer == 0U) - { - if (ep->is_in != 0U) - { - PCD_CLEAR_TX_DTOG(USBx, ep->num); - - /* Configure DISABLE status for the Endpoint */ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); - } - - else - { - PCD_CLEAR_RX_DTOG(USBx, ep->num); - - /* Configure DISABLE status for the Endpoint */ - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); - } - } -#if (USE_USB_DOUBLE_BUFFER == 1U) - /* Double Buffer */ - else - { - if (ep->is_in == 0U) - { - /* Clear the data toggle bits for the endpoint IN/OUT*/ - PCD_CLEAR_RX_DTOG(USBx, ep->num); - PCD_CLEAR_TX_DTOG(USBx, ep->num); - - /* Reset value of the data toggle bits for the endpoint out*/ - PCD_TX_DTOG(USBx, ep->num); - - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); - } - else - { - /* Clear the data toggle bits for the endpoint IN/OUT*/ - PCD_CLEAR_RX_DTOG(USBx, ep->num); - PCD_CLEAR_TX_DTOG(USBx, ep->num); - PCD_RX_DTOG(USBx, ep->num); - - /* Configure DISABLE status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); - } - } -#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - - return HAL_OK; -} - -/** - * @brief USB_EPStartXfer setup and starts a transfer over an EP - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) -{ - uint32_t len; -#if (USE_USB_DOUBLE_BUFFER == 1U) - uint16_t pmabuffer; - uint16_t wEPVal; -#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - - /* IN endpoint */ - if (ep->is_in == 1U) - { - /*Multi packet transfer*/ - if (ep->xfer_len > ep->maxpacket) - { - len = ep->maxpacket; - } - else - { - len = ep->xfer_len; - } - - /* configure and validate Tx endpoint */ - if (ep->doublebuffer == 0U) - { - USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len); - PCD_SET_EP_TX_CNT(USBx, ep->num, len); - } -#if (USE_USB_DOUBLE_BUFFER == 1U) - else - { - /* double buffer bulk management */ - if (ep->type == EP_TYPE_BULK) - { - if (ep->xfer_len_db > ep->maxpacket) - { - /* enable double buffer */ - PCD_SET_BULK_EP_DBUF(USBx, ep->num); - - /* each Time to write in PMA xfer_len_db will */ - ep->xfer_len_db -= len; - - /* Fill the two first buffer in the Buffer0 & Buffer1 */ - if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) - { - /* Set the Double buffer counter for pmabuffer1 */ - PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); - pmabuffer = ep->pmaaddr1; - - /* Write the user buffer to USB PMA */ - USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); - ep->xfer_buff += len; - - if (ep->xfer_len_db > ep->maxpacket) - { - ep->xfer_len_db -= len; - } - else - { - len = ep->xfer_len_db; - ep->xfer_len_db = 0U; - } - - /* Set the Double buffer counter for pmabuffer0 */ - PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); - pmabuffer = ep->pmaaddr0; - - /* Write the user buffer to USB PMA */ - USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); - } - else - { - /* Set the Double buffer counter for pmabuffer0 */ - PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); - pmabuffer = ep->pmaaddr0; - - /* Write the user buffer to USB PMA */ - USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); - ep->xfer_buff += len; - - if (ep->xfer_len_db > ep->maxpacket) - { - ep->xfer_len_db -= len; - } - else - { - len = ep->xfer_len_db; - ep->xfer_len_db = 0U; - } - - /* Set the Double buffer counter for pmabuffer1 */ - PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); - pmabuffer = ep->pmaaddr1; - - /* Write the user buffer to USB PMA */ - USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); - } - } - /* auto Switch to single buffer mode when transfer xfer_len_db; - - /* disable double buffer mode for Bulk endpoint */ - PCD_CLEAR_BULK_EP_DBUF(USBx, ep->num); - - /* Set Tx count with nbre of byte to be transmitted */ - PCD_SET_EP_TX_CNT(USBx, ep->num, len); - pmabuffer = ep->pmaaddr0; - - /* Write the user buffer to USB PMA */ - USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); - } - } - else /* manage isochronous double buffer IN mode */ - { - /* each Time to write in PMA xfer_len_db will */ - ep->xfer_len_db -= len; - - /* Fill the data buffer */ - if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) - { - /* Set the Double buffer counter for pmabuffer1 */ - PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); - pmabuffer = ep->pmaaddr1; - - /* Write the user buffer to USB PMA */ - USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); - } - else - { - /* Set the Double buffer counter for pmabuffer0 */ - PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); - pmabuffer = ep->pmaaddr0; - - /* Write the user buffer to USB PMA */ - USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); - } - } - } -#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID); - } - else /* OUT endpoint */ - { - if (ep->doublebuffer == 0U) - { - /* Multi packet transfer */ - if (ep->xfer_len > ep->maxpacket) - { - len = ep->maxpacket; - ep->xfer_len -= len; - } - else - { - len = ep->xfer_len; - ep->xfer_len = 0U; - } - /* configure and validate Rx endpoint */ - PCD_SET_EP_RX_CNT(USBx, ep->num, len); - } -#if (USE_USB_DOUBLE_BUFFER == 1U) - else - { - /* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */ - /* Set the Double buffer counter */ - if (ep->type == EP_TYPE_BULK) - { - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); - - /* Coming from ISR */ - if (ep->xfer_count != 0U) - { - /* update last value to check if there is blocking state */ - wEPVal = PCD_GET_ENDPOINT(USBx, ep->num); - - /*Blocking State */ - if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || - (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) - { - PCD_FREE_USER_BUFFER(USBx, ep->num, 0U); - } - } - } - /* iso out double */ - else if (ep->type == EP_TYPE_ISOC) - { - /* Multi packet transfer */ - if (ep->xfer_len > ep->maxpacket) - { - len = ep->maxpacket; - ep->xfer_len -= len; - } - else - { - len = ep->xfer_len; - ep->xfer_len = 0U; - } - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len); - } - else - { - return HAL_ERROR; - } - } -#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); - } - - return HAL_OK; -} - - -/** - * @brief USB_EPSetStall set a stall condition over an EP - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) -{ - if (ep->is_in != 0U) - { - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL); - } - else - { - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL); - } - - return HAL_OK; -} - -/** - * @brief USB_EPClearStall Clear a stall condition over an EP - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) -{ - if (ep->doublebuffer == 0U) - { - if (ep->is_in != 0U) - { - PCD_CLEAR_TX_DTOG(USBx, ep->num); - - if (ep->type != EP_TYPE_ISOC) - { - /* Configure NAK status for the Endpoint */ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); - } - } - else - { - PCD_CLEAR_RX_DTOG(USBx, ep->num); - - /* Configure VALID status for the Endpoint */ - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); - } - } - - return HAL_OK; -} - -/** - * @brief USB_EPStoptXfer Stop transfer on an EP - * @param USBx usb device instance - * @param ep pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPStopXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) -{ - /* IN endpoint */ - if (ep->is_in == 1U) - { - if (ep->doublebuffer == 0U) - { - if (ep->type != EP_TYPE_ISOC) - { - /* Configure NAK status for the Endpoint */ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); - } - else - { - /* Configure TX Endpoint to disabled state */ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); - } - } - } - else /* OUT endpoint */ - { - if (ep->doublebuffer == 0U) - { - if (ep->type != EP_TYPE_ISOC) - { - /* Configure NAK status for the Endpoint */ - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK); - } - else - { - /* Configure RX Endpoint to disabled state */ - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); - } - } - } - - return HAL_OK; -} -#endif /* defined (HAL_PCD_MODULE_ENABLED) */ - -/** - * @brief USB_StopDevice Stop the usb device mode - * @param USBx Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx) -{ - /* disable all interrupts and force USB reset */ - USBx->CNTR = (uint16_t)USB_CNTR_FRES; - - /* clear interrupt status register */ - USBx->ISTR = 0U; - - /* switch-off device */ - USBx->CNTR = (uint16_t)(USB_CNTR_FRES | USB_CNTR_PDWN); - - return HAL_OK; -} - -/** - * @brief USB_SetDevAddress Stop the usb device mode - * @param USBx Selected device - * @param address new device address to be assigned - * This parameter can be a value from 0 to 255 - * @retval HAL status - */ -HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address) -{ - if (address == 0U) - { - /* set device address and enable function */ - USBx->DADDR = (uint16_t)USB_DADDR_EF; - } - - return HAL_OK; -} - -/** - * @brief USB_DevConnect Connect the USB device by enabling the pull-up/pull-down - * @param USBx Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx) -{ - /* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */ - USBx->BCDR |= (uint16_t)USB_BCDR_DPPU; - - return HAL_OK; -} - -/** - * @brief USB_DevDisconnect Disconnect the USB device by disabling the pull-up/pull-down - * @param USBx Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx) -{ - /* Disable DP Pull-Up bit to disconnect the Internal PU resistor on USB DP line */ - USBx->BCDR &= (uint16_t)(~(USB_BCDR_DPPU)); - - return HAL_OK; -} - -/** - * @brief USB_ReadInterrupts return the global USB interrupt status - * @param USBx Selected device - * @retval USB Global Interrupt status - */ -uint32_t USB_ReadInterrupts(USB_TypeDef const *USBx) -{ - uint32_t tmpreg; - - tmpreg = USBx->ISTR; - return tmpreg; -} - -/** - * @brief USB_ActivateRemoteWakeup : active remote wakeup signalling - * @param USBx Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx) -{ - USBx->CNTR |= (uint16_t)USB_CNTR_RESUME; - - return HAL_OK; -} - -/** - * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling - * @param USBx Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx) -{ - USBx->CNTR &= (uint16_t)(~USB_CNTR_RESUME); - - return HAL_OK; -} - -/** - * @brief Copy a buffer from user memory area to packet memory area (PMA) - * @param USBx USB peripheral instance register address. - * @param pbUsrBuf pointer to user memory area. - * @param wPMABufAddr address into PMA. - * @param wNBytes no. of bytes to be copied. - * @retval None - */ -void USB_WritePMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) -{ - uint32_t n = ((uint32_t)wNBytes + 1U) >> 1; - uint32_t BaseAddr = (uint32_t)USBx; - uint32_t count; - uint16_t WrVal; - __IO uint16_t *pdwVal; - uint8_t *pBuf = pbUsrBuf; - - pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); - - for (count = n; count != 0U; count--) - { - WrVal = pBuf[0]; - WrVal |= (uint16_t)pBuf[1] << 8; - *pdwVal = (WrVal & 0xFFFFU); - pdwVal++; - -#if PMA_ACCESS > 1U - pdwVal++; -#endif /* PMA_ACCESS */ - - pBuf++; - pBuf++; - } -} - -/** - * @brief Copy data from packet memory area (PMA) to user memory buffer - * @param USBx USB peripheral instance register address. - * @param pbUsrBuf pointer to user memory area. - * @param wPMABufAddr address into PMA. - * @param wNBytes no. of bytes to be copied. - * @retval None - */ -void USB_ReadPMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) -{ - uint32_t n = (uint32_t)wNBytes >> 1; - uint32_t BaseAddr = (uint32_t)USBx; - uint32_t count; - uint32_t RdVal; - __IO uint16_t *pdwVal; - uint8_t *pBuf = pbUsrBuf; - - pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); - - for (count = n; count != 0U; count--) - { - RdVal = *(__IO uint16_t *)pdwVal; - pdwVal++; - *pBuf = (uint8_t)((RdVal >> 0) & 0xFFU); - pBuf++; - *pBuf = (uint8_t)((RdVal >> 8) & 0xFFU); - pBuf++; - -#if PMA_ACCESS > 1U - pdwVal++; -#endif /* PMA_ACCESS */ - } - - if ((wNBytes % 2U) != 0U) - { - RdVal = *pdwVal; - *pBuf = (uint8_t)((RdVal >> 0) & 0xFFU); - } -} - - -/** - * @} - */ - -/** - * @} - */ -#endif /* defined (USB) */ -#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */ - -/** - * @} - */ diff --git a/Mcu/g431/STM32G431CBUX_FLASH.ld b/Mcu/g431/STM32G431CBUX_FLASH.ld new file mode 100644 index 000000000..02a370c4f --- /dev/null +++ b/Mcu/g431/STM32G431CBUX_FLASH.ld @@ -0,0 +1,209 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32G431CBUx Device from STM32G4 series +** 112KBytes FLASH +** 32KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2024 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 112K + FLASH (rx) :ORIGIN = 0x08001000, LENGTH = 64K - 52 + FLASH_VERSION (rx) : ORIGIN = 0x0800F800 - 52, LENGTH = 18 + FILE_NAME (rx) : ORIGIN = 0x0800F800 - 32, LENGTH = 32 + EEPROM (rx) : ORIGIN = 0x0800F800, LENGTH = 2K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The firmware version and name - at a fixed address to make it possible to read it from firmware files. */ + .firmware_version : + { + . = ALIGN(4); + KEEP (*(.firmware_info)) + } >FLASH_VERSION + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + .firmware_version : + { + . = ALIGN(4); + KEEP (*(.firmware_info)) + } >FLASH_VERSION + + .file_name : + { + . = ALIGN(4); + KEEP (*(.file_name)) + } >FILE_NAME + + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/Mcu/g431/Startup/startup_stm32g431xx.s b/Mcu/g431/Startup/mdk/startup_stm32g431xx.s similarity index 100% rename from Mcu/g431/Startup/startup_stm32g431xx.s rename to Mcu/g431/Startup/mdk/startup_stm32g431xx.s diff --git a/g431makefile.mk b/g431makefile.mk new file mode 100644 index 000000000..2d5be0682 --- /dev/null +++ b/g431makefile.mk @@ -0,0 +1,34 @@ + +TARGETS_G431 := $(call get_targets,G431) + +HAL_FOLDER_G431 := $(HAL_FOLDER)/g431 + +MCU_G431 := -mcpu=cortex-m0 -mthumb +LDSCRIPT_G431 := $(HAL_FOLDER_G431)/STM32G431CBUX_FLASH.ld + +SRC_DIR_G431 := \ + $(HAL_FOLDER_G431)/Startup \ + $(HAL_FOLDER_G431)/Src \ + $(HAL_FOLDER_G431)/Drivers/STM32G4xx_HAL_Driver/Src + +CFLAGS_G431 := \ + -I$(HAL_FOLDER_G431)/Inc \ + -I$(HAL_FOLDER_G431)/Drivers/STM32G4xx_HAL_Driver/Inc \ + -I$(HAL_FOLDER_G431)/Drivers/CMSIS/Include \ + -I$(HAL_FOLDER_G431)/Drivers/CMSIS/Device/ST/STM32G4xx/Include + +CFLAGS_G431 += \ + -DHSE_VALUE=8000000 \ + -DSTM32G431xx \ + -DHSE_STARTUP_TIMEOUT=100 \ + -DLSE_STARTUP_TIMEOUT=5000 \ + -DLSE_VALUE=32768 \ + -DDATA_CACHE_ENABLE=1 \ + -DINSTRUCTION_CACHE_ENABLE=0 \ + -DVDD_VALUE=3300 \ + -DLSI_VALUE=32000 \ + -DHSI_VALUE=16000000 \ + -DUSE_FULL_LL_DRIVER \ + -DPREFETCH_ENABLE=1 + +SRC_G431 := $(foreach dir,$(SRC_DIR_G431),$(wildcard $(dir)/*.[cs])) From c5738761af0107ecf359b94ef2b7c67923d5d7a2 Mon Sep 17 00:00:00 2001 From: Andrew Tridgell Date: Sun, 28 Jul 2024 14:25:56 +1000 Subject: [PATCH 10/11] g431: added bootloader targetting PA15 for ST G431 discovery ESC --- Makefile | 7 +- Mcu/e230/Inc/blutil.h | 3 +- Mcu/f031/Inc/blutil.h | 3 +- Mcu/f051/Inc/blutil.h | 3 +- Mcu/f415/Inc/blutil.h | 2 + Mcu/f421/Inc/blutil.h | 2 + Mcu/g071/Inc/blutil.h | 3 +- .../STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h | 627 +++ .../Inc/stm32g4xx_hal_cortex.h | 419 ++ .../Inc/stm32g4xx_hal_def.h | 211 + .../Inc/stm32g4xx_hal_dma.h | 852 +++++ .../Inc/stm32g4xx_hal_dma_ex.h | 264 ++ .../Inc/stm32g4xx_hal_exti.h | 315 ++ .../Inc/stm32g4xx_hal_flash.h | 1018 +++++ .../Inc/stm32g4xx_hal_flash_ex.h | 89 + ...mplate.h => stm32g4xx_hal_flash_ramfunc.h} | 73 +- .../Inc/stm32g4xx_hal_gpio.h | 326 ++ .../Inc/stm32g4xx_hal_gpio_ex.h | 340 ++ .../Inc/stm32g4xx_hal_pwr.h | 411 ++ .../Inc/stm32g4xx_hal_pwr_ex.h | 817 ++++ .../Inc/stm32g4xx_hal_rcc.h | 3406 +++++++++++++++++ .../Inc/stm32g4xx_hal_rcc_ex.h | 1606 ++++++++ .../STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c | 800 ++++ .../Src/stm32g4xx_hal_cortex.c | 517 +++ .../Src/stm32g4xx_hal_gpio.c | 532 +++ .../Src/stm32g4xx_hal_pwr_ex.c | 1182 ++++++ .../Src/stm32g4xx_hal_rcc.c | 1400 +++++++ Mcu/g431/Inc/blutil.h | 145 + Mcu/g431/Inc/main.h | 17 - Mcu/g431/Inc/stm32g4xx_hal_conf.h | 382 ++ Mcu/g431/Src/eeprom.c | 2 +- Mcu/g431/Src/stm32g4xx_it.c | 264 +- Mcu/g431/Src/system_stm32g4xx.c | 46 +- Mcu/g431/Startup/startup_stm32g431xx.s | 515 +++ bootloader/main.c | 67 +- g431makefile.mk | 52 +- 36 files changed, 16477 insertions(+), 241 deletions(-) create mode 100644 Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h create mode 100644 Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h create mode 100644 Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h create mode 100644 Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h create mode 100644 Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h create mode 100644 Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h create mode 100644 Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h create mode 100644 Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h rename Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/{stm32_assert_template.h => stm32g4xx_hal_flash_ramfunc.h} (50%) create mode 100644 Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h create mode 100644 Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h create mode 100644 Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h create mode 100644 Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h create mode 100644 Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h create mode 100644 Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h create mode 100644 Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c create mode 100644 Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c create mode 100644 Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c create mode 100644 Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c create mode 100644 Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c create mode 100644 Mcu/g431/Inc/blutil.h create mode 100644 Mcu/g431/Inc/stm32g4xx_hal_conf.h create mode 100644 Mcu/g431/Startup/startup_stm32g431xx.s diff --git a/Makefile b/Makefile index 6976fa0e4..9d60bb085 100644 --- a/Makefile +++ b/Makefile @@ -28,7 +28,7 @@ MCU_TYPE := NONE # MCU types that we build a bootloader for - this should be $(MCU_TYPES) in the future # when all bootloader porting is completed -BL_MCU_TYPES := E230 F031 F051 F415 F421 G071 +BL_MCU_TYPES := E230 F031 F051 F415 F421 G071 G431 # Function to include makefile for each MCU type define INCLUDE_MCU_MAKEFILES @@ -110,8 +110,8 @@ $(foreach MCU,$(MCU_TYPES),$(foreach TARGET,$(TARGETS_$(MCU)), $(eval $(call CRE # bootloader build BOOTLOADER_VERSION := $(shell $(FGREP) "define BOOTLOADER_VERSION" $(MAIN_INC_DIR)/version.h | $(CUT) -d" " -f3 ) -# we support bootloader comms on either PB4 or PA2 -BOOTLOADER_PINS = PB4 PA2 +# we support bootloader comms on a list of possible pins +BOOTLOADER_PINS = PB4 PA2 PA15 SRC_BL := $(foreach dir,bootloader,$(wildcard $(dir)/*.[cs])) LDSCRIPT_BL := bootloader/ldscript_bl.ld @@ -132,7 +132,6 @@ $(BIN_DIR)/$(call BOOTLOADER_BASENAME_VER,$(1),$(2)).elf: LDFLAGS_BL := $$(LDFLA $(BIN_DIR)/$(call BOOTLOADER_BASENAME_VER,$(1),$(2)).elf: $$(SRC_BL) $$(QUIET)echo building bootloader for $(1) with pin $(2) $$(QUIET)$$(MKDIR) -p $(OBJ) - $$(QUIET)echo BUILT $(1) pin $(2) > $$@ $$(QUIET)echo Compiling $(notdir $$@) $$(QUIET)$$(CC) $$(CFLAGS_BL) $$(LDFLAGS_BL) -o $$(@) $$(SRC_BL) $$(SRC_$(1)_BL) -Os $$(QUIET)$$(CP) -f $$@ $$(OBJ)$$(DSEP)debug.elf diff --git a/Mcu/e230/Inc/blutil.h b/Mcu/e230/Inc/blutil.h index 4dc94b6a2..11a5277ba 100644 --- a/Mcu/e230/Inc/blutil.h +++ b/Mcu/e230/Inc/blutil.h @@ -3,8 +3,7 @@ */ #pragma once -#define GPIO_PINS_2 GPIO_PIN_2 -#define GPIO_PINS_4 GPIO_PIN_4 +#define GPIO_PIN(n) (1U<<(n)) #define GPIO_PULL_NONE GPIO_PUPD_NONE #define GPIO_PULL_UP GPIO_PUPD_PULLUP diff --git a/Mcu/f031/Inc/blutil.h b/Mcu/f031/Inc/blutil.h index e9d5dca49..6db298996 100644 --- a/Mcu/f031/Inc/blutil.h +++ b/Mcu/f031/Inc/blutil.h @@ -6,8 +6,7 @@ */ #pragma once -#define GPIO_PINS_2 (1U<<2) -#define GPIO_PINS_4 (1U<<4) +#define GPIO_PIN(n) (1U<<(n)) #define GPIO_PULL_NONE LL_GPIO_PULL_NO #define GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */ diff --git a/Mcu/f051/Inc/blutil.h b/Mcu/f051/Inc/blutil.h index e9d5dca49..6db298996 100644 --- a/Mcu/f051/Inc/blutil.h +++ b/Mcu/f051/Inc/blutil.h @@ -6,8 +6,7 @@ */ #pragma once -#define GPIO_PINS_2 (1U<<2) -#define GPIO_PINS_4 (1U<<4) +#define GPIO_PIN(n) (1U<<(n)) #define GPIO_PULL_NONE LL_GPIO_PULL_NO #define GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */ diff --git a/Mcu/f415/Inc/blutil.h b/Mcu/f415/Inc/blutil.h index f31c79d12..4184960df 100644 --- a/Mcu/f415/Inc/blutil.h +++ b/Mcu/f415/Inc/blutil.h @@ -3,6 +3,8 @@ */ #pragma once +#define GPIO_PIN(n) (1U<<(n)) + static inline void gpio_mode_set_input(uint32_t pin, uint32_t pull_up_down) { if (pin < 8) { diff --git a/Mcu/f421/Inc/blutil.h b/Mcu/f421/Inc/blutil.h index ee890ffa4..2a6b3b612 100644 --- a/Mcu/f421/Inc/blutil.h +++ b/Mcu/f421/Inc/blutil.h @@ -3,6 +3,8 @@ */ #pragma once +#define GPIO_PIN(n) (1U<<(n)) + static inline void gpio_mode_set_input(uint32_t pin, uint32_t pull_up_down) { const uint32_t pinsq = (pin*pin); diff --git a/Mcu/g071/Inc/blutil.h b/Mcu/g071/Inc/blutil.h index 81153c6ac..7aa642e01 100644 --- a/Mcu/g071/Inc/blutil.h +++ b/Mcu/g071/Inc/blutil.h @@ -6,8 +6,7 @@ */ #pragma once -#define GPIO_PINS_2 (1U<<2) -#define GPIO_PINS_4 (1U<<4) +#define GPIO_PIN(n) (1U<<(n)) #define GPIO_PULL_NONE LL_GPIO_PULL_NO #define GPIO_PULL_UP LL_GPIO_PULL_UP diff --git a/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h new file mode 100644 index 000000000..5786f8a42 --- /dev/null +++ b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h @@ -0,0 +1,627 @@ +/** + ****************************************************************************** + * @file stm32g4xx_hal.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the HAL + * module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G4xx_HAL_H +#define STM32G4xx_HAL_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_hal_conf.h" + +/** @addtogroup STM32G4xx_HAL_Driver + * @{ + */ + +/** @addtogroup HAL HAL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ + +/** @defgroup HAL_TICK_FREQ Tick Frequency + * @{ + */ +#define HAL_TICK_FREQ_10HZ 100U +#define HAL_TICK_FREQ_100HZ 10U +#define HAL_TICK_FREQ_1KHZ 1U +#define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ + +/** + * @} + */ + +/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants + * @{ + */ + +/** @defgroup SYSCFG_BootMode Boot Mode + * @{ + */ +#define SYSCFG_BOOT_MAINFLASH 0x00000000U +#define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMMEMRMP_MODE_0 + +#if defined (FMC_BANK1) +#define SYSCFG_BOOT_FMC SYSCFG_MEMMEMRMP_MODE_1 +#endif /* FMC_BANK1 */ + +#define SYSCFG_BOOT_SRAM (SYSCFG_MEMMEMRMP_MODE_1 | SYSCFG_MEMMEMRMP_MODE_0) + +#if defined (QUADSPI) +#define SYSCFG_BOOT_QUADSPI (SYSCFG_MEMMEMRMP_MODE_2 | SYSCFG_MEMMEMRMP_MODE_1) +#endif /* QUADSPI */ + +/** + * @} + */ + +/** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts + * @{ + */ +#define SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ +#define SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ +#define SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ +#define SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ +#define SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ +#define SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ + +/** + * @} + */ + +/** @defgroup SYSCFG_CCMSRAMWRP CCM Write protection + * @{ + */ +#define SYSCFG_CCMSRAMWRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< CCMSRAM Write protection page 0 */ +#define SYSCFG_CCMSRAMWRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< CCMSRAM Write protection page 1 */ +#define SYSCFG_CCMSRAMWRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< CCMSRAM Write protection page 2 */ +#define SYSCFG_CCMSRAMWRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< CCMSRAM Write protection page 3 */ +#define SYSCFG_CCMSRAMWRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< CCMSRAM Write protection page 4 */ +#define SYSCFG_CCMSRAMWRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< CCMSRAM Write protection page 5 */ +#define SYSCFG_CCMSRAMWRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< CCMSRAM Write protection page 6 */ +#define SYSCFG_CCMSRAMWRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< CCMSRAM Write protection page 7 */ +#define SYSCFG_CCMSRAMWRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< CCMSRAM Write protection page 8 */ +#define SYSCFG_CCMSRAMWRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< CCMSRAM Write protection page 9 */ +#define SYSCFG_CCMSRAMWRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< CCMSRAM Write protection page 10 */ +#define SYSCFG_CCMSRAMWRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< CCMSRAM Write protection page 11 */ +#define SYSCFG_CCMSRAMWRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< CCMSRAM Write protection page 12 */ +#define SYSCFG_CCMSRAMWRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< CCMSRAM Write protection page 13 */ +#define SYSCFG_CCMSRAMWRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< CCMSRAM Write protection page 14 */ +#define SYSCFG_CCMSRAMWRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< CCMSRAM Write protection page 15 */ +#define SYSCFG_CCMSRAMWRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< CCMSRAM Write protection page 16 */ +#define SYSCFG_CCMSRAMWRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< CCMSRAM Write protection page 17 */ +#define SYSCFG_CCMSRAMWRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< CCMSRAM Write protection page 18 */ +#define SYSCFG_CCMSRAMWRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< CCMSRAM Write protection page 19 */ +#define SYSCFG_CCMSRAMWRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< CCMSRAM Write protection page 20 */ +#define SYSCFG_CCMSRAMWRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< CCMSRAM Write protection page 21 */ +#define SYSCFG_CCMSRAMWRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< CCMSRAM Write protection page 22 */ +#define SYSCFG_CCMSRAMWRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< CCMSRAM Write protection page 23 */ +#define SYSCFG_CCMSRAMWRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< CCMSRAM Write protection page 24 */ +#define SYSCFG_CCMSRAMWRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< CCMSRAM Write protection page 25 */ +#define SYSCFG_CCMSRAMWRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< CCMSRAM Write protection page 26 */ +#define SYSCFG_CCMSRAMWRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< CCMSRAM Write protection page 27 */ +#define SYSCFG_CCMSRAMWRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< CCMSRAM Write protection page 28 */ +#define SYSCFG_CCMSRAMWRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< CCMSRAM Write protection page 29 */ +#define SYSCFG_CCMSRAMWRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< CCMSRAM Write protection page 30 */ +#define SYSCFG_CCMSRAMWRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< CCMSRAM Write protection page 31 */ + +/** + * @} + */ + +#if defined(VREFBUF) +/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale + * @{ + */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 0x00000000U /*!< Voltage reference scale 0 (VREFBUF_OUT = 2.048V) */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREFBUF_OUT = 2.5V) */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREFBUF_OUT = 2.9V) */ + +/** + * @} + */ + +/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance + * @{ + */ +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0x00000000U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ + +/** + * @} + */ +#endif /* VREFBUF */ + +/** @defgroup SYSCFG_flags_definition Flags + * @{ + */ + +#define SYSCFG_FLAG_SRAM_PE SYSCFG_CFGR2_SPF /*!< SRAM parity error (first 32kB of SRAM1 + CCM SRAM) */ +#define SYSCFG_FLAG_CCMSRAM_BUSY SYSCFG_SCSR_CCMBSY /*!< CCMSRAM busy by erase operation */ + +/** + * @} + */ + +/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO + * @{ + */ + +/** @brief Fast-mode Plus driving capability on a specific GPIO + */ +#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ +#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ +#if defined(SYSCFG_CFGR1_I2C_PB8_FMP) +#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ +#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */ +#if defined(SYSCFG_CFGR1_I2C_PB9_FMP) +#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ +#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros + * @{ + */ + +/** @brief Freeze/Unfreeze Peripherals in Debug mode + */ +#if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP) +#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_TIM2_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP) +#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_TIM3_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP) +#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP) +#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_TIM5_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP) +#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_TIM6_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP) +#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_TIM7_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP) +#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) +#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_RTC_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP) +#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) +#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_WWDG_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP) +#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) +#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_IWDG_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP) +#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_I2C1_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP) +#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_I2C2_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP) +#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_I2C3_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) +#define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) +#define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_LPTIM1_STOP */ + +#if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP) +#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) +#endif /* DBGMCU_APB1FZR2_DBG_I2C4_STOP */ + +#if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP) +#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP) +#endif /* DBGMCU_APB2FZ_DBG_TIM1_STOP */ + +#if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP) +#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP) +#endif /* DBGMCU_APB2FZ_DBG_TIM8_STOP */ + +#if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP) +#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP) +#endif /* DBGMCU_APB2FZ_DBG_TIM15_STOP */ + +#if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP) +#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP) +#endif /* DBGMCU_APB2FZ_DBG_TIM16_STOP */ + +#if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP) +#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP) +#endif /* DBGMCU_APB2FZ_DBG_TIM17_STOP */ + +#if defined(DBGMCU_APB2FZ_DBG_TIM20_STOP) +#define __HAL_DBGMCU_FREEZE_TIM20() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM20_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM20() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM20_STOP) +#endif /* DBGMCU_APB2FZ_DBG_TIM20_STOP */ + +#if defined(DBGMCU_APB2FZ_DBG_HRTIM1_STOP) +#define __HAL_DBGMCU_FREEZE_HRTIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_HRTIM1_STOP) +#define __HAL_DBGMCU_UNFREEZE_HRTIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_HRTIM1_STOP) +#endif /* DBGMCU_APB2FZ_DBG_HRTIM1_STOP */ + +/** + * @} + */ + +/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros + * @{ + */ + +/** @brief Main Flash memory mapped at 0x00000000. + */ +#define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) + +/** @brief System Flash memory mapped at 0x00000000. + */ +#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0) + +/** @brief Embedded SRAM mapped at 0x00000000. + */ +#define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0)) + +#if defined (FMC_BANK1) +/** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000. + */ +#define __HAL_SYSCFG_REMAPMEMORY_FMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1) +#endif /* FMC_BANK1 */ + +#if defined (QUADSPI) +/** @brief QUADSPI mapped at 0x00000000. + */ +#define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1)) +#endif /* QUADSPI */ + +/** + * @brief Return the boot mode as configured by user. + * @retval The boot mode as configured by user. The returned value can be one + * of the following values: + * @arg @ref SYSCFG_BOOT_MAINFLASH + * @arg @ref SYSCFG_BOOT_SYSTEMFLASH + * @arg @ref SYSCFG_BOOT_FMC (*) + * @arg @ref SYSCFG_BOOT_QUADSPI (*) + * @arg @ref SYSCFG_BOOT_SRAM + * @note (*) availability depends on devices + */ +#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) + +/** @brief CCMSRAM page write protection enable macro + * @param __CCMSRAMWRP__: This parameter can be a value of @ref SYSCFG_CCMSRAMWRP + * @note write protection can only be disabled by a system reset + * @retval None + */ +/* Legacy define */ +#define __HAL_SYSCFG_CCMSRAM_WRP_1_31_ENABLE __HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE +#define __HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE(__CCMSRAMWRP__) do {assert_param(IS_SYSCFG_CCMSRAMWRP_PAGE((__CCMSRAMWRP__)));\ + SET_BIT(SYSCFG->SWPR,(__CCMSRAMWRP__));\ + }while(0) + +/** @brief CCMSRAM page write protection unlock prior to erase + * @note Writing a wrong key reactivates the write protection + */ +#define __HAL_SYSCFG_CCMSRAM_WRP_UNLOCK() do {SYSCFG->SKR = 0xCA;\ + SYSCFG->SKR = 0x53;\ + }while(0) + +/** @brief CCMSRAM erase + * @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_CCMSRAM_BUSY) may be used to check end of erase + */ +#define __HAL_SYSCFG_CCMSRAM_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER) + +/** @brief Floating Point Unit interrupt enable/disable macros + * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts + */ +#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ + SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ + }while(0) + +#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ + CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ + }while(0) + +/** @brief SYSCFG Break ECC lock. + * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + */ +#define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL) + +/** @brief SYSCFG Break Cortex-M4 Lockup lock. + * Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + */ +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL) + +/** @brief SYSCFG Break PVD lock. + * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register. + * @note The selected configuration is locked and can be unlocked only by system reset. + */ +#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL) + +/** @brief SYSCFG Break SRAM parity lock. + * Enable and lock the SRAM parity error (first 32kB of SRAM1 + CCM SRAM) signal connection to TIM1/8/15/16/17 Break input. + * @note The selected configuration is locked and can be unlocked by system reset. + */ +#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL) + +/** @brief Check SYSCFG flag is set or not. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref SYSCFG_FLAG_SRAM_PE SRAM Parity Error Flag + * @arg @ref SYSCFG_FLAG_CCMSRAM_BUSY CCMSRAM Erase Ongoing + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_CCMBSY)? SYSCFG->SCSR : SYSCFG->CFGR2)\ + & (__FLAG__))!= 0U) ? 1U : 0U) + +/** @brief Set the SPF bit to clear the SRAM Parity Error Flag. + */ +#define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) + +/** @brief Fast-mode Plus driving capability enable/disable macros + * @param __FASTMODEPLUS__: This parameter can be a value of : + * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 + * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 + * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 + * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9 + */ +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ + SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ + }while(0) + +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ + CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ + }while(0) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros + * @{ + */ + +#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \ + (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \ + (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \ + (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \ + (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \ + (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC)) + +#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \ + ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ + ((__CONFIG__) == SYSCFG_BREAK_SRAMPARITY) || \ + ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) + +#if (CCMSRAM_SIZE == 0x00008000UL) || (CCMSRAM_SIZE == 0x00004000UL) +#define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__) ((__PAGE__) > 0U) +#elif (CCMSRAM_SIZE == 0x00002800UL) +#define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000003FFU)) +#endif /* CCMSRAM_SIZE */ + +#if defined(VREFBUF) +#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ + ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \ + ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2)) + +#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ + ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) + +#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) +#endif /* VREFBUF */ + +#if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9) +#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) +#elif defined(SYSCFG_FASTMODEPLUS_PB8) +#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8)) +#elif defined(SYSCFG_FASTMODEPLUS_PB9) +#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) +#else +#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7)) +#endif /* SYSCFG_FASTMODEPLUS_PB */ +/** + * @} + */ + +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ +#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ + ((FREQ) == HAL_TICK_FREQ_100HZ) || \ + ((FREQ) == HAL_TICK_FREQ_1KHZ)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup HAL_Exported_Functions + * @{ + */ + +/** @addtogroup HAL_Exported_Functions_Group1 + * @{ + */ +/* Initialization and Configuration functions ******************************/ +HAL_StatusTypeDef HAL_Init(void); +HAL_StatusTypeDef HAL_DeInit(void); +void HAL_MspInit(void); +void HAL_MspDeInit(void); +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_IncTick(void); +void HAL_Delay(uint32_t Delay); +uint32_t HAL_GetTick(void); +uint32_t HAL_GetTickPrio(void); +HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq); +uint32_t HAL_GetTickFreq(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +uint32_t HAL_GetHalVersion(void); +uint32_t HAL_GetREVID(void); +uint32_t HAL_GetDEVID(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group3 + * @{ + */ + +/* DBGMCU Peripheral Control functions *****************************************/ +void HAL_DBGMCU_EnableDBGSleepMode(void); +void HAL_DBGMCU_DisableDBGSleepMode(void); +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); + +/** + * @} + */ + +/* Exported variables ---------------------------------------------------------*/ +/** @addtogroup HAL_Exported_Variables + * @{ + */ +extern __IO uint32_t uwTick; +extern uint32_t uwTickPrio; +extern uint32_t uwTickFreq; +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group4 + * @{ + */ + +/* SYSCFG Control functions ****************************************************/ +void HAL_SYSCFG_CCMSRAMErase(void); +void HAL_SYSCFG_EnableMemorySwappingBank(void); +void HAL_SYSCFG_DisableMemorySwappingBank(void); + +#if defined(VREFBUF) +void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); +void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); +void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); +HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); +void HAL_SYSCFG_DisableVREFBUF(void); +#endif /* VREFBUF */ + +void HAL_SYSCFG_EnableIOSwitchBooster(void); +void HAL_SYSCFG_DisableIOSwitchBooster(void); +void HAL_SYSCFG_EnableIOSwitchVDD(void); +void HAL_SYSCFG_DisableIOSwitchVDD(void); + +void HAL_SYSCFG_CCMSRAM_WriteProtectionEnable(uint32_t Page); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G4xx_HAL_H */ + diff --git a/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h new file mode 100644 index 000000000..0fd9deec3 --- /dev/null +++ b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h @@ -0,0 +1,419 @@ +/** + ****************************************************************************** + * @file stm32g4xx_hal_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32G4xx_HAL_CORTEX_H +#define __STM32G4xx_HAL_CORTEX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_hal_def.h" + +/** @addtogroup STM32G4xx_HAL_Driver + * @{ + */ + +/** @defgroup CORTEX CORTEX + * @brief CORTEX HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Types CORTEX Exported Types + * @{ + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition + * @brief MPU Region initialization structure + * @{ + */ +typedef struct +{ + uint8_t Enable; /*!< Specifies the status of the region. + This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ + uint8_t Number; /*!< Specifies the number of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Number */ + uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ + uint8_t Size; /*!< Specifies the size of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Size */ + uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint8_t TypeExtField; /*!< Specifies the TEX field level. + This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ + uint8_t AccessPermission; /*!< Specifies the region access permission type. + This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ + uint8_t DisableExec; /*!< Specifies the instruction access status. + This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ + uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ + uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. + This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ + uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ +}MPU_Region_InitTypeDef; +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group + * @{ + */ +#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bit for pre-emption priority, + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bit for pre-emption priority, + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority, + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority, + 1 bit for subpriority */ +#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority, + 0 bit for subpriority */ +/** + * @} + */ + +/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source + * @{ + */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U +#define SYSTICK_CLKSOURCE_HCLK 0x00000004U + +/** + * @} + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control + * @{ + */ +#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U +#define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk) +#define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk) +#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable + * @{ + */ +#define MPU_REGION_ENABLE ((uint8_t)0x01) +#define MPU_REGION_DISABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access + * @{ + */ +#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) +#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable + * @{ + */ +#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable + * @{ + */ +#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable + * @{ + */ +#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels + * @{ + */ +#define MPU_TEX_LEVEL0 ((uint8_t)0x00) +#define MPU_TEX_LEVEL1 ((uint8_t)0x01) +#define MPU_TEX_LEVEL2 ((uint8_t)0x02) +#define MPU_TEX_LEVEL4 ((uint8_t)0x04) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size + * @{ + */ +#define MPU_REGION_SIZE_32B ((uint8_t)0x04) +#define MPU_REGION_SIZE_64B ((uint8_t)0x05) +#define MPU_REGION_SIZE_128B ((uint8_t)0x06) +#define MPU_REGION_SIZE_256B ((uint8_t)0x07) +#define MPU_REGION_SIZE_512B ((uint8_t)0x08) +#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) +#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) +#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) +#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) +#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) +#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) +#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) +#define MPU_REGION_SIZE_128KB ((uint8_t)0x10) +#define MPU_REGION_SIZE_256KB ((uint8_t)0x11) +#define MPU_REGION_SIZE_512KB ((uint8_t)0x12) +#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) +#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) +#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) +#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) +#define MPU_REGION_SIZE_16MB ((uint8_t)0x17) +#define MPU_REGION_SIZE_32MB ((uint8_t)0x18) +#define MPU_REGION_SIZE_64MB ((uint8_t)0x19) +#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) +#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) +#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) +#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) +#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) +#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes + * @{ + */ +#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) +#define MPU_REGION_PRIV_RW ((uint8_t)0x01) +#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) +#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) +#define MPU_REGION_PRIV_RO ((uint8_t)0x05) +#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number + * @{ + */ +#define MPU_REGION_NUMBER0 ((uint8_t)0x00) +#define MPU_REGION_NUMBER1 ((uint8_t)0x01) +#define MPU_REGION_NUMBER2 ((uint8_t)0x02) +#define MPU_REGION_NUMBER3 ((uint8_t)0x03) +#define MPU_REGION_NUMBER4 ((uint8_t)0x04) +#define MPU_REGION_NUMBER5 ((uint8_t)0x05) +#define MPU_REGION_NUMBER6 ((uint8_t)0x06) +#define MPU_REGION_NUMBER7 ((uint8_t)0x07) +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ + +/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * @{ + */ +/* Initialization and Configuration functions *****************************/ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); +void HAL_NVIC_SystemReset(void); +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); + +/** + * @} + */ + +/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * @{ + */ +/* Peripheral Control functions ***********************************************/ +uint32_t HAL_NVIC_GetPriorityGrouping(void); +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +void HAL_SYSTICK_IRQHandler(void); +void HAL_SYSTICK_Callback(void); + +#if (__MPU_PRESENT == 1) +void HAL_MPU_Enable(uint32_t MPU_Control); +void HAL_MPU_Disable(void); +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Macros CORTEX Private Macros + * @{ + */ +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ + ((GROUP) == NVIC_PRIORITYGROUP_1) || \ + ((GROUP) == NVIC_PRIORITYGROUP_2) || \ + ((GROUP) == NVIC_PRIORITYGROUP_3) || \ + ((GROUP) == NVIC_PRIORITYGROUP_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) + +#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn) + +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) + +#if (__MPU_PRESENT == 1) +#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ + ((STATE) == MPU_REGION_DISABLE)) + +#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ + ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) + +#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ + ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) + +#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ + ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) + +#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ + ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) + +#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ + ((TYPE) == MPU_TEX_LEVEL1) || \ + ((TYPE) == MPU_TEX_LEVEL2) || \ + ((TYPE) == MPU_TEX_LEVEL4)) + +#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RW) || \ + ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ + ((TYPE) == MPU_REGION_FULL_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RO) || \ + ((TYPE) == MPU_REGION_PRIV_RO_URO)) + +#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ + ((NUMBER) == MPU_REGION_NUMBER1) || \ + ((NUMBER) == MPU_REGION_NUMBER2) || \ + ((NUMBER) == MPU_REGION_NUMBER3) || \ + ((NUMBER) == MPU_REGION_NUMBER4) || \ + ((NUMBER) == MPU_REGION_NUMBER5) || \ + ((NUMBER) == MPU_REGION_NUMBER6) || \ + ((NUMBER) == MPU_REGION_NUMBER7)) + +#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ + ((SIZE) == MPU_REGION_SIZE_64B) || \ + ((SIZE) == MPU_REGION_SIZE_128B) || \ + ((SIZE) == MPU_REGION_SIZE_256B) || \ + ((SIZE) == MPU_REGION_SIZE_512B) || \ + ((SIZE) == MPU_REGION_SIZE_1KB) || \ + ((SIZE) == MPU_REGION_SIZE_2KB) || \ + ((SIZE) == MPU_REGION_SIZE_4KB) || \ + ((SIZE) == MPU_REGION_SIZE_8KB) || \ + ((SIZE) == MPU_REGION_SIZE_16KB) || \ + ((SIZE) == MPU_REGION_SIZE_32KB) || \ + ((SIZE) == MPU_REGION_SIZE_64KB) || \ + ((SIZE) == MPU_REGION_SIZE_128KB) || \ + ((SIZE) == MPU_REGION_SIZE_256KB) || \ + ((SIZE) == MPU_REGION_SIZE_512KB) || \ + ((SIZE) == MPU_REGION_SIZE_1MB) || \ + ((SIZE) == MPU_REGION_SIZE_2MB) || \ + ((SIZE) == MPU_REGION_SIZE_4MB) || \ + ((SIZE) == MPU_REGION_SIZE_8MB) || \ + ((SIZE) == MPU_REGION_SIZE_16MB) || \ + ((SIZE) == MPU_REGION_SIZE_32MB) || \ + ((SIZE) == MPU_REGION_SIZE_64MB) || \ + ((SIZE) == MPU_REGION_SIZE_128MB) || \ + ((SIZE) == MPU_REGION_SIZE_256MB) || \ + ((SIZE) == MPU_REGION_SIZE_512MB) || \ + ((SIZE) == MPU_REGION_SIZE_1GB) || \ + ((SIZE) == MPU_REGION_SIZE_2GB) || \ + ((SIZE) == MPU_REGION_SIZE_4GB)) + +#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32G4xx_HAL_CORTEX_H */ + + diff --git a/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h new file mode 100644 index 000000000..dcb73f677 --- /dev/null +++ b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h @@ -0,0 +1,211 @@ +/** + ****************************************************************************** + * @file stm32g4xx_hal_def.h + * @author MCD Application Team + * @brief This file contains HAL common defines, enumeration, macros and + * structures definitions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32G4xx_HAL_DEF +#define __STM32G4xx_HAL_DEF + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx.h" +#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */ +#include + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HAL Status structures definition + */ +typedef enum +{ + HAL_OK = 0x00U, + HAL_ERROR = 0x01U, + HAL_BUSY = 0x02U, + HAL_TIMEOUT = 0x03U +} HAL_StatusTypeDef; + +/** + * @brief HAL Lock structures definition + */ +typedef enum +{ + HAL_UNLOCKED = 0x00U, + HAL_LOCKED = 0x01U +} HAL_LockTypeDef; + +/* Exported macros -----------------------------------------------------------*/ + +#define HAL_MAX_DELAY 0xFFFFFFFFU + +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) +#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) + +#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ + (__DMA_HANDLE__).Parent = (__HANDLE__); \ + } while(0) + +#if !defined(UNUSED) +#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ +#endif /* UNUSED */ + +/** @brief Reset the Handle's State field. + * @param __HANDLE__: specifies the Peripheral Handle. + * @note This macro can be used for the following purpose: + * - When the Handle is declared as local variable; before passing it as parameter + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to set to 0 the Handle's "State" field. + * Otherwise, "State" field may have any random value and the first time the function + * HAL_PPP_Init() is called, the low level hardware initialization will be missed + * (i.e. HAL_PPP_MspInit() will not be executed). + * - When there is a need to reconfigure the low level hardware: instead of calling + * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). + * In this later function, when the Handle's "State" field is set to 0, it will execute the function + * HAL_PPP_MspInit() which will reconfigure the low level hardware. + * @retval None + */ +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) + +#if (USE_RTOS == 1U) +/* Reserved for future use */ +#error " USE_RTOS should be 0 in the current HAL release " +#else +#define __HAL_LOCK(__HANDLE__) \ + do{ \ + if((__HANDLE__)->Lock == HAL_LOCKED) \ + { \ + return HAL_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = HAL_LOCKED; \ + } \ + }while (0U) + +#define __HAL_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0U) +#endif /* USE_RTOS */ + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif +#ifndef __packed +#define __packed __attribute__((packed)) +#endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ +#ifndef __packed +#define __packed __attribute__((__packed__)) +#endif /* __packed */ +#endif /* __GNUC__ */ + + +/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif +#ifndef __ALIGN_END +#define __ALIGN_END __attribute__ ((aligned (4))) +#endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ +#ifndef __ALIGN_END +#define __ALIGN_END __attribute__ ((aligned (4U))) +#endif /* __ALIGN_END */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif /* __ALIGN_BEGIN */ +#else +#ifndef __ALIGN_END +#define __ALIGN_END +#endif /* __ALIGN_END */ +#ifndef __ALIGN_BEGIN +#if defined (__CC_ARM) /* ARM Compiler V5*/ +#define __ALIGN_BEGIN __align(4U) +#elif defined (__ICCARM__) /* IAR Compiler */ +#define __ALIGN_BEGIN +#endif /* __CC_ARM */ +#endif /* __ALIGN_BEGIN */ +#endif /* __GNUC__ */ + +/** + * @brief __RAM_FUNC definition + */ +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +/* ARM Compiler V4/V5 and V6 + -------------------------- + RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the 'Options for Target' + dialog. +*/ +#define __RAM_FUNC + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ +#define __RAM_FUNC __ramfunc + +#elif defined ( __GNUC__ ) +/* GNU Compiler + ------------ + RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". +*/ +#define __RAM_FUNC __attribute__((section(".RamFunc"))) + +#endif /* __CC_ARM */ + +/** + * @brief __NOINLINE definition + */ +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) +/* ARM V4/V5 and V6 & GNU Compiler + ------------------------------- +*/ +#define __NOINLINE __attribute__ ( (noinline) ) + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- +*/ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif /* __CC_ARM || __GNUC__ */ + + +#ifdef __cplusplus +} +#endif + +#endif /* ___STM32G4xx_HAL_DEF */ + diff --git a/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h new file mode 100644 index 000000000..8ba1b6130 --- /dev/null +++ b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h @@ -0,0 +1,852 @@ +/** + ****************************************************************************** + * @file stm32g4xx_hal_dma.h + * @author MCD Application Team + * @brief Header file of DMA HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32G4xx_HAL_DMA_H +#define __STM32G4xx_HAL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_hal_def.h" + +/** @addtogroup STM32G4xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Types DMA Exported Types + * @{ + */ + +/** + * @brief DMA Configuration Structure definition + */ +typedef struct +{ + uint32_t Request; /*!< Specifies the request selected for the specified channel. + This parameter can be a value of @ref DMA_request */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_Data_transfer_direction */ + + uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. + This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ + + uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. + This parameter can be a value of @ref DMA_Memory_incremented_mode */ + + uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_Peripheral_data_size */ + + uint32_t MemDataAlignment; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_Memory_data_size */ + + uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_mode + @note The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_Priority_level */ +} DMA_InitTypeDef; + +/** + * @brief HAL DMA State structures definition + */ +typedef enum +{ + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ +} HAL_DMA_StateTypeDef; + +/** + * @brief HAL DMA Error Code structure definition + */ +typedef enum +{ + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ + HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ +} HAL_DMA_LevelCompleteTypeDef; + + +/** + * @brief HAL DMA Callback ID structure definition + */ +typedef enum +{ + HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ + HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ + HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ + HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ + HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ + +} HAL_DMA_CallbackIDTypeDef; + +/** + * @brief DMA handle Structure definition + */ +typedef struct __DMA_HandleTypeDef +{ + DMA_Channel_TypeDef *Instance; /*!< Register base address */ + + DMA_InitTypeDef Init; /*!< DMA communication parameters */ + + HAL_LockTypeDef Lock; /*!< DMA locking object */ + + __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ + + void *Parent; /*!< Parent object state */ + + void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ + + void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */ + + void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ + + void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */ + + __IO uint32_t ErrorCode; /*!< DMA Error code */ + + DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ + + uint32_t ChannelIndex; /*!< DMA Channel Index */ + + DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */ + + DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ + + uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ + + DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ + + DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */ + + uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ + +} DMA_HandleTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @{ + */ + +/** @defgroup DMA_Error_Code DMA Error Code + * @{ + */ +#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ +#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */ +#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ +#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ +#define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */ +#define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */ +/** + * @} + */ + +/** @defgroup DMA_request DMA request + * @{ + */ +#define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */ + +#define DMA_REQUEST_GENERATOR0 1U +#define DMA_REQUEST_GENERATOR1 2U +#define DMA_REQUEST_GENERATOR2 3U +#define DMA_REQUEST_GENERATOR3 4U + +#define DMA_REQUEST_ADC1 5U + +#define DMA_REQUEST_DAC1_CHANNEL1 6U +#define DMA_REQUEST_DAC1_CHANNEL2 7U + +#define DMA_REQUEST_TIM6_UP 8U +#define DMA_REQUEST_TIM7_UP 9U + +#define DMA_REQUEST_SPI1_RX 10U +#define DMA_REQUEST_SPI1_TX 11U +#define DMA_REQUEST_SPI2_RX 12U +#define DMA_REQUEST_SPI2_TX 13U +#define DMA_REQUEST_SPI3_RX 14U +#define DMA_REQUEST_SPI3_TX 15U + +#define DMA_REQUEST_I2C1_RX 16U +#define DMA_REQUEST_I2C1_TX 17U +#define DMA_REQUEST_I2C2_RX 18U +#define DMA_REQUEST_I2C2_TX 19U +#define DMA_REQUEST_I2C3_RX 20U +#define DMA_REQUEST_I2C3_TX 21U +#if defined (I2C4) +#define DMA_REQUEST_I2C4_RX 22U +#define DMA_REQUEST_I2C4_TX 23U +#endif /* I2C4 */ + +#define DMA_REQUEST_USART1_RX 24U +#define DMA_REQUEST_USART1_TX 25U +#define DMA_REQUEST_USART2_RX 26U +#define DMA_REQUEST_USART2_TX 27U +#define DMA_REQUEST_USART3_RX 28U +#define DMA_REQUEST_USART3_TX 29U + +#define DMA_REQUEST_UART4_RX 30U +#define DMA_REQUEST_UART4_TX 31U +#if defined (UART5) +#define DMA_REQUEST_UART5_RX 32U +#define DMA_REQUEST_UART5_TX 33U +#endif /* UART5 */ + +#define DMA_REQUEST_LPUART1_RX 34U +#define DMA_REQUEST_LPUART1_TX 35U + +#define DMA_REQUEST_ADC2 36U +#if defined (ADC3) +#define DMA_REQUEST_ADC3 37U +#endif /* ADC3 */ +#if defined (ADC4) +#define DMA_REQUEST_ADC4 38U +#endif /* ADC4 */ +#if defined (ADC5) +#define DMA_REQUEST_ADC5 39U +#endif /* ADC5 */ + +#if defined (QUADSPI) +#define DMA_REQUEST_QUADSPI 40U +#endif /* QUADSPI */ + +#if defined (DAC2) +#define DMA_REQUEST_DAC2_CHANNEL1 41U +#endif /* DAC2 */ + +#define DMA_REQUEST_TIM1_CH1 42U +#define DMA_REQUEST_TIM1_CH2 43U +#define DMA_REQUEST_TIM1_CH3 44U +#define DMA_REQUEST_TIM1_CH4 45U +#define DMA_REQUEST_TIM1_UP 46U +#define DMA_REQUEST_TIM1_TRIG 47U +#define DMA_REQUEST_TIM1_COM 48U + +#define DMA_REQUEST_TIM8_CH1 49U +#define DMA_REQUEST_TIM8_CH2 50U +#define DMA_REQUEST_TIM8_CH3 51U +#define DMA_REQUEST_TIM8_CH4 52U +#define DMA_REQUEST_TIM8_UP 53U +#define DMA_REQUEST_TIM8_TRIG 54U +#define DMA_REQUEST_TIM8_COM 55U + +#define DMA_REQUEST_TIM2_CH1 56U +#define DMA_REQUEST_TIM2_CH2 57U +#define DMA_REQUEST_TIM2_CH3 58U +#define DMA_REQUEST_TIM2_CH4 59U +#define DMA_REQUEST_TIM2_UP 60U + +#define DMA_REQUEST_TIM3_CH1 61U +#define DMA_REQUEST_TIM3_CH2 62U +#define DMA_REQUEST_TIM3_CH3 63U +#define DMA_REQUEST_TIM3_CH4 64U +#define DMA_REQUEST_TIM3_UP 65U +#define DMA_REQUEST_TIM3_TRIG 66U + +#define DMA_REQUEST_TIM4_CH1 67U +#define DMA_REQUEST_TIM4_CH2 68U +#define DMA_REQUEST_TIM4_CH3 69U +#define DMA_REQUEST_TIM4_CH4 70U +#define DMA_REQUEST_TIM4_UP 71U + +#if defined (TIM5) +#define DMA_REQUEST_TIM5_CH1 72U +#define DMA_REQUEST_TIM5_CH2 73U +#define DMA_REQUEST_TIM5_CH3 74U +#define DMA_REQUEST_TIM5_CH4 75U +#define DMA_REQUEST_TIM5_UP 76U +#define DMA_REQUEST_TIM5_TRIG 77U +#endif /* TIM5 */ + +#define DMA_REQUEST_TIM15_CH1 78U +#define DMA_REQUEST_TIM15_UP 79U +#define DMA_REQUEST_TIM15_TRIG 80U +#define DMA_REQUEST_TIM15_COM 81U + +#define DMA_REQUEST_TIM16_CH1 82U +#define DMA_REQUEST_TIM16_UP 83U +#define DMA_REQUEST_TIM17_CH1 84U +#define DMA_REQUEST_TIM17_UP 85U + +#if defined (TIM20) +#define DMA_REQUEST_TIM20_CH1 86U +#define DMA_REQUEST_TIM20_CH2 87U +#define DMA_REQUEST_TIM20_CH3 88U +#define DMA_REQUEST_TIM20_CH4 89U +#define DMA_REQUEST_TIM20_UP 90U +#endif /* TIM20 */ + +#define DMA_REQUEST_AES_IN 91U +#define DMA_REQUEST_AES_OUT 92U + +#if defined (TIM20) +#define DMA_REQUEST_TIM20_TRIG 93U +#define DMA_REQUEST_TIM20_COM 94U +#endif /* TIM20 */ + +#if defined (HRTIM1) +#define DMA_REQUEST_HRTIM1_M 95U +#define DMA_REQUEST_HRTIM1_A 96U +#define DMA_REQUEST_HRTIM1_B 97U +#define DMA_REQUEST_HRTIM1_C 98U +#define DMA_REQUEST_HRTIM1_D 99U +#define DMA_REQUEST_HRTIM1_E 100U +#define DMA_REQUEST_HRTIM1_F 101U +#endif /* HRTIM1 */ + +#define DMA_REQUEST_DAC3_CHANNEL1 102U +#define DMA_REQUEST_DAC3_CHANNEL2 103U +#if defined (DAC4) +#define DMA_REQUEST_DAC4_CHANNEL1 104U +#define DMA_REQUEST_DAC4_CHANNEL2 105U +#endif /* DAC4 */ + +#if defined (SPI4) +#define DMA_REQUEST_SPI4_RX 106U +#define DMA_REQUEST_SPI4_TX 107U +#endif /* SPI4 */ + +#define DMA_REQUEST_SAI1_A 108U +#define DMA_REQUEST_SAI1_B 109U + +#define DMA_REQUEST_FMAC_READ 110U +#define DMA_REQUEST_FMAC_WRITE 111U + +#define DMA_REQUEST_CORDIC_READ 112U +#define DMA_REQUEST_CORDIC_WRITE 113U + +#define DMA_REQUEST_UCPD1_RX 114U +#define DMA_REQUEST_UCPD1_TX 115U + +/** + * @} + */ + +/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction + * @{ + */ +#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ +#define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode + * @{ + */ +#define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */ +#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode + * @{ + */ +#define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */ +#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size + * @{ + */ +#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ +#define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ +#define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_Memory_data_size DMA Memory data size + * @{ + */ +#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ +#define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ +#define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_mode DMA mode + * @{ + */ +#define DMA_NORMAL 0x00000000U /*!< Normal mode */ +#define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */ +/** + * @} + */ + +/** @defgroup DMA_Priority_level DMA Priority level + * @{ + */ +#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ +#define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ +#define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ +#define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */ +/** + * @} + */ + + +/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions + * @{ + */ +#define DMA_IT_TC DMA_CCR_TCIE +#define DMA_IT_HT DMA_CCR_HTIE +#define DMA_IT_TE DMA_CCR_TEIE +/** + * @} + */ + +/** @defgroup DMA_flag_definitions DMA flag definitions + * @{ + */ +#define DMA_FLAG_GL1 0x00000001U +#define DMA_FLAG_TC1 0x00000002U +#define DMA_FLAG_HT1 0x00000004U +#define DMA_FLAG_TE1 0x00000008U +#define DMA_FLAG_GL2 0x00000010U +#define DMA_FLAG_TC2 0x00000020U +#define DMA_FLAG_HT2 0x00000040U +#define DMA_FLAG_TE2 0x00000080U +#define DMA_FLAG_GL3 0x00000100U +#define DMA_FLAG_TC3 0x00000200U +#define DMA_FLAG_HT3 0x00000400U +#define DMA_FLAG_TE3 0x00000800U +#define DMA_FLAG_GL4 0x00001000U +#define DMA_FLAG_TC4 0x00002000U +#define DMA_FLAG_HT4 0x00004000U +#define DMA_FLAG_TE4 0x00008000U +#define DMA_FLAG_GL5 0x00010000U +#define DMA_FLAG_TC5 0x00020000U +#define DMA_FLAG_HT5 0x00040000U +#define DMA_FLAG_TE5 0x00080000U +#define DMA_FLAG_GL6 0x00100000U +#define DMA_FLAG_TC6 0x00200000U +#define DMA_FLAG_HT6 0x00400000U +#define DMA_FLAG_TE6 0x00800000U +#if defined (DMA1_Channel7) +#define DMA_FLAG_GL7 0x01000000U +#define DMA_FLAG_TC7 0x02000000U +#define DMA_FLAG_HT7 0x04000000U +#define DMA_FLAG_TE7 0x08000000U +#endif /* DMA1_Channel7 */ +#if defined (DMA1_Channel8) +#define DMA_FLAG_GL8 0x10000000U +#define DMA_FLAG_TC8 0x20000000U +#define DMA_FLAG_HT8 0x40000000U +#define DMA_FLAG_TE8 0x80000000U +#endif /* DMA1_Channel8 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup DMA_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @brief Reset DMA handle state. + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) + +/** + * @brief Enable the specified DMA Channel. + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) + +/** + * @brief Disable the specified DMA Channel. + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) + + +/* Interrupt & Flag management */ + +/** + * @brief Return the current DMA Channel transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer complete flag index. + */ + +#if defined (DMA1_Channel8) +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ + (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_TC7 :\ + DMA_FLAG_TC8) +#elif defined (DMA1_Channel6) +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ + (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\ + DMA_FLAG_TC6) +#endif /* DMA1_Channel8 */ + +/** + * @brief Return the current DMA Channel half transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified half transfer complete flag index. + */ +#if defined (DMA1_Channel8) +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ + (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_HT7 :\ + DMA_FLAG_HT8) +#elif defined (DMA1_Channel6) +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ + (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\ + DMA_FLAG_HT6) +#endif /* DMA1_Channel8 */ + +/** + * @brief Return the current DMA Channel transfer error flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#if defined (DMA1_Channel8) +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ + (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_TE7 :\ + DMA_FLAG_TE8) +#elif defined (DMA1_Channel6) +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ + (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\ + DMA_FLAG_TE6) +#endif /* DMA1_Channel8 */ + +/** + * @brief Return the current DMA Channel Global interrupt flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#if defined (DMA1_Channel8) +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ + (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_ISR_GIF7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_ISR_GIF7 :\ + DMA_ISR_GIF8) +#elif defined (DMA1_Channel6) +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ + (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\ + DMA_ISR_GIF6) +#endif /* DMA1_Channel8 */ + +/** + * @brief Get the DMA Channel pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx Transfer complete flag + * @arg DMA_FLAG_HTx Half transfer complete flag + * @arg DMA_FLAG_TEx Transfer error flag + * @arg DMA_FLAG_GLx Global interrupt flag + * Where x can be from 1 to 8 to select the DMA Channel x flag. + * @retval The state of FLAG (SET or RESET). + */ +#if defined (DMA1_Channel8) +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel8))? \ + (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) +#elif defined (DMA1_Channel6) +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel6))? \ + (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) +#endif /* DMA1_Channel8 */ + +/** + * @brief Clear the DMA Channel pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx Transfer complete flag + * @arg DMA_FLAG_HTx Half transfer complete flag + * @arg DMA_FLAG_TEx Transfer error flag + * @arg DMA_FLAG_GLx Global interrupt flag + * Where x can be from 1 to 8 to select the DMA Channel x flag. + * @retval None + */ +#if defined (DMA1_Channel8) +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel8))? \ + (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) +#else +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel6))? \ + (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) +#endif /* DMA1_Channel8 */ + +/** + * @brief Enable the specified DMA Channel interrupts. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC Transfer complete interrupt mask + * @arg DMA_IT_HT Half transfer complete interrupt mask + * @arg DMA_IT_TE Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) + +/** + * @brief Disable the specified DMA Channel interrupts. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC Transfer complete interrupt mask + * @arg DMA_IT_HT Half transfer complete interrupt mask + * @arg DMA_IT_TE Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) + +/** + * @brief Check whether the specified DMA Channel interrupt is enabled or not. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA_IT_TC Transfer complete interrupt mask + * @arg DMA_IT_HT Half transfer complete interrupt mask + * @arg DMA_IT_TE Transfer error interrupt mask + * @retval The state of DMA_IT (SET or RESET). + */ +#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) + +/** + * @brief Return the number of remaining data units in the current DMA Channel transfer. + * @param __HANDLE__ DMA handle + * @retval The number of remaining data units in the current DMA Channel transfer. + */ +#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) + +/** + * @} + */ + +/* Include DMA HAL Extension module */ +#include "stm32g4xx_hal_dma_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup DMA_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, + uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, + uint32_t Timeout); +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMA_Private_Macros DMA Private Macros + * @{ + */ + +#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ + ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) + +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x40000U)) + +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ + ((STATE) == DMA_PINC_DISABLE)) + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ + ((STATE) == DMA_MINC_DISABLE)) + +#define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_UCPD1_TX) + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ + ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_PDATAALIGN_WORD)) + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ + ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_MDATAALIGN_WORD )) + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ + ((MODE) == DMA_CIRCULAR)) + +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ + ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ + ((PRIORITY) == DMA_PRIORITY_HIGH) || \ + ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32G4xx_HAL_DMA_H */ + diff --git a/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h new file mode 100644 index 000000000..606db3bc4 --- /dev/null +++ b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h @@ -0,0 +1,264 @@ +/** + ****************************************************************************** + * @file stm32g4xx_hal_dma_ex.h + * @author MCD Application Team + * @brief Header file of DMA HAL extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32G4xx_HAL_DMA_EX_H +#define __STM32G4xx_HAL_DMA_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_hal_def.h" + +/** @addtogroup STM32G4xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMAEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Types DMAEx Exported Types + * @{ + */ + +/** + * @brief HAL DMA Synchro definition + */ + + +/** + * @brief HAL DMAMUX Synchronization configuration structure definition + */ +typedef struct +{ + uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode. + This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */ + + uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized. + This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */ + + FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled + This parameter can take the value ENABLE or DISABLE*/ + + + FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached. + This parameter can take the value ENABLE or DISABLE */ + + uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event + This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ + + +} HAL_DMA_MuxSyncConfigTypeDef; + + +/** + * @brief HAL DMAMUX request generator parameters structure definition + */ +typedef struct +{ + uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator + This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */ + + uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated. + This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */ + + uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event + This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ + +} HAL_DMA_MuxRequestGeneratorConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants + * @{ + */ + +/** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection + * @{ + */ +#define HAL_DMAMUX1_SYNC_EXTI0 0U /*!< Synchronization Signal is EXTI0 IT */ +#define HAL_DMAMUX1_SYNC_EXTI1 1U /*!< Synchronization Signal is EXTI1 IT */ +#define HAL_DMAMUX1_SYNC_EXTI2 2U /*!< Synchronization Signal is EXTI2 IT */ +#define HAL_DMAMUX1_SYNC_EXTI3 3U /*!< Synchronization Signal is EXTI3 IT */ +#define HAL_DMAMUX1_SYNC_EXTI4 4U /*!< Synchronization Signal is EXTI4 IT */ +#define HAL_DMAMUX1_SYNC_EXTI5 5U /*!< Synchronization Signal is EXTI5 IT */ +#define HAL_DMAMUX1_SYNC_EXTI6 6U /*!< Synchronization Signal is EXTI6 IT */ +#define HAL_DMAMUX1_SYNC_EXTI7 7U /*!< Synchronization Signal is EXTI7 IT */ +#define HAL_DMAMUX1_SYNC_EXTI8 8U /*!< Synchronization Signal is EXTI8 IT */ +#define HAL_DMAMUX1_SYNC_EXTI9 9U /*!< Synchronization Signal is EXTI9 IT */ +#define HAL_DMAMUX1_SYNC_EXTI10 10U /*!< Synchronization Signal is EXTI10 IT */ +#define HAL_DMAMUX1_SYNC_EXTI11 11U /*!< Synchronization Signal is EXTI11 IT */ +#define HAL_DMAMUX1_SYNC_EXTI12 12U /*!< Synchronization Signal is EXTI12 IT */ +#define HAL_DMAMUX1_SYNC_EXTI13 13U /*!< Synchronization Signal is EXTI13 IT */ +#define HAL_DMAMUX1_SYNC_EXTI14 14U /*!< Synchronization Signal is EXTI14 IT */ +#define HAL_DMAMUX1_SYNC_EXTI15 15U /*!< Synchronization Signal is EXTI15 IT */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 16U /*!< Synchronization Signal is DMAMUX1 Channel0 Event */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 17U /*!< Synchronization Signal is DMAMUX1 Channel1 Event */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 18U /*!< Synchronization Signal is DMAMUX1 Channel2 Event */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT 19U /*!< Synchronization Signal is DMAMUX1 Channel3 Event */ +#define HAL_DMAMUX1_SYNC_LPTIM1_OUT 20U /*!< Synchronization Signal is LPTIM1 OUT */ + +/** + * @} + */ + +/** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection + * @{ + */ +#define HAL_DMAMUX_SYNC_NO_EVENT 0U /*!< block synchronization events */ +#define HAL_DMAMUX_SYNC_RISING ((uint32_t)DMAMUX_CxCR_SPOL_0) /*!< synchronize with rising edge events */ +#define HAL_DMAMUX_SYNC_FALLING ((uint32_t)DMAMUX_CxCR_SPOL_1) /*!< synchronize with falling edge events */ +#define HAL_DMAMUX_SYNC_RISING_FALLING ((uint32_t)DMAMUX_CxCR_SPOL) /*!< synchronize with rising and falling edge events */ + +/** + * @} + */ + +/** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection + * @{ + */ +#define HAL_DMAMUX1_REQ_GEN_EXTI0 0U /*!< Request generator Signal is EXTI0 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI1 1U /*!< Request generator Signal is EXTI1 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI2 2U /*!< Request generator Signal is EXTI2 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI3 3U /*!< Request generator Signal is EXTI3 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI4 4U /*!< Request generator Signal is EXTI4 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI5 5U /*!< Request generator Signal is EXTI5 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI6 6U /*!< Request generator Signal is EXTI6 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI7 7U /*!< Request generator Signal is EXTI7 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI8 8U /*!< Request generator Signal is EXTI8 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI9 9U /*!< Request generator Signal is EXTI9 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI10 10U /*!< Request generator Signal is EXTI10 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI11 11U /*!< Request generator Signal is EXTI11 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI12 12U /*!< Request generator Signal is EXTI12 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI13 13U /*!< Request generator Signal is EXTI13 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI14 14U /*!< Request generator Signal is EXTI14 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI15 15U /*!< Request generator Signal is EXTI15 IT */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 16U /*!< Request generator Signal is DMAMUX1 Channel0 Event */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 17U /*!< Request generator Signal is DMAMUX1 Channel1 Event */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 18U /*!< Request generator Signal is DMAMUX1 Channel2 Event */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT 19U /*!< Request generator Signal is DMAMUX1 Channel3 Event */ +#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 20U /*!< Request generator Signal is LPTIM1 OUT */ + +/** + * @} + */ + +/** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection + * @{ + */ +#define HAL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< block request generator events */ +#define HAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */ +#define HAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */ +#define HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DMAEx_Exported_Functions + * @{ + */ + +/* IO operation functions *****************************************************/ +/** @addtogroup DMAEx_Exported_Functions_Group1 + * @{ + */ + +/* ------------------------- REQUEST -----------------------------------------*/ +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, + HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig); +HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma); +/* -------------------------------------------------------------------------- */ + +/* ------------------------- SYNCHRO -----------------------------------------*/ +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig); +/* -------------------------------------------------------------------------- */ + +void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma); + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Macros DMAEx Private Macros + * @brief DMAEx private macros + * @{ + */ + +#define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LPTIM1_OUT) + +#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) + +#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \ + ((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \ + ((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \ + ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING)) + +#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE)) + +#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \ + ((EVENT) == ENABLE)) + +#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT) + +#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) + +#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \ + ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \ + ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \ + ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING)) + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32G4xx_HAL_DMA_EX_H */ + diff --git a/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h new file mode 100644 index 000000000..4908976ad --- /dev/null +++ b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h @@ -0,0 +1,315 @@ +/** + ****************************************************************************** + * @file stm32g4xx_hal_exti.h + * @author MCD Application Team + * @brief Header file of EXTI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G4xx_HAL_EXTI_H +#define STM32G4xx_HAL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_hal_def.h" + +/** @addtogroup STM32G4xx_HAL_Driver + * @{ + */ + +/** @defgroup EXTI EXTI + * @brief EXTI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup EXTI_Exported_Types EXTI Exported Types + * @{ + */ +typedef enum +{ + HAL_EXTI_COMMON_CB_ID = 0x00UL +} EXTI_CallbackIDTypeDef; + + +/** + * @brief EXTI Handle structure definition + */ +typedef struct +{ + uint32_t Line; /*!< Exti line number */ + void (* PendingCallback)(void); /*!< Exti pending callback */ +} EXTI_HandleTypeDef; + +/** + * @brief EXTI Configuration structure definition + */ +typedef struct +{ + uint32_t Line; /*!< The Exti line to be configured. This parameter + can be a value of @ref EXTI_Line */ + uint32_t Mode; /*!< The Exit Mode to be configured for a core. + This parameter can be a combination of @ref EXTI_Mode */ + uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter + can be a value of @ref EXTI_Trigger */ + uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. + This parameter is only possible for line 0 to 15. It + can be a value of @ref EXTI_GPIOSel */ +} EXTI_ConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_Line EXTI Line + * @{ + */ +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | 0x00u) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | 0x01u) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | 0x02u) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | 0x03u) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | 0x04u) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | 0x05u) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | 0x06u) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | 0x07u) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | 0x08u) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | 0x09u) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | 0x0Au) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | 0x0Bu) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | 0x0Cu) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | 0x0Du) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | 0x0Eu) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0Fu) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10u) +#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_REG1 | 0x11u) +#define EXTI_LINE_18 (EXTI_DIRECT | EXTI_REG1 | 0x12u) +#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | 0x13u) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | 0x14u) +#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | 0x15u) +#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | 0x16u) +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u) +#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u) +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u) +#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | 0x1Au) +#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | 0x1Bu) +#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu) +#define EXTI_LINE_29 (EXTI_CONFIG | EXTI_REG1 | 0x1Du) +#define EXTI_LINE_30 (EXTI_CONFIG | EXTI_REG1 | 0x1Eu) +#define EXTI_LINE_31 (EXTI_CONFIG | EXTI_REG1 | 0x1Fu) +#define EXTI_LINE_32 (EXTI_CONFIG | EXTI_REG2 | 0x00u) +#define EXTI_LINE_33 (EXTI_CONFIG | EXTI_REG2 | 0x01u) +#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | 0x02u) +#define EXTI_LINE_35 (EXTI_DIRECT | EXTI_REG2 | 0x03u) +#define EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04u) +#define EXTI_LINE_37 (EXTI_DIRECT | EXTI_REG2 | 0x05u) +#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | 0x06u) +#define EXTI_LINE_39 (EXTI_CONFIG | EXTI_REG2 | 0x07u) +#define EXTI_LINE_40 (EXTI_CONFIG | EXTI_REG2 | 0x08u) +#define EXTI_LINE_41 (EXTI_CONFIG | EXTI_REG2 | 0x09u) +#define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0Au) +#define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0Bu) +/** + * @} + */ + +/** @defgroup EXTI_Mode EXTI Mode + * @{ + */ +#define EXTI_MODE_NONE 0x00000000U +#define EXTI_MODE_INTERRUPT 0x00000001U +#define EXTI_MODE_EVENT 0x00000002U +/** + * @} + */ + +/** @defgroup EXTI_Trigger EXTI Trigger + * @{ + */ +#define EXTI_TRIGGER_NONE 0x00000000U +#define EXTI_TRIGGER_RISING 0x00000001U +#define EXTI_TRIGGER_FALLING 0x00000002U +#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) +/** + * @} + */ + +/** @defgroup EXTI_GPIOSel EXTI GPIOSel + * @brief + * @{ + */ +#define EXTI_GPIOA 0x00000000U +#define EXTI_GPIOB 0x00000001U +#define EXTI_GPIOC 0x00000002U +#define EXTI_GPIOD 0x00000003U +#define EXTI_GPIOE 0x00000004U +#define EXTI_GPIOF 0x00000005U +#define EXTI_GPIOG 0x00000006U +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Private constants --------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +/** + * @brief EXTI Line property definition + */ +#define EXTI_PROPERTY_SHIFT 24U +#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT) +#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) +#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) +#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT) +#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO) + +/** + * @brief EXTI Register and bit usage + */ +#define EXTI_REG_SHIFT 16U +#define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT) +#define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT) +#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2) +#define EXTI_PIN_MASK 0x0000001FU + +/** + * @brief EXTI Mask for interrupt & event mode + */ +#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) + +/** + * @brief EXTI Mask for trigger possibilities + */ +#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) + +/** + * @brief EXTI Line number + */ +#define EXTI_LINE_NB 44UL + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Macros EXTI Private Macros + * @{ + */ +#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) && \ + ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ + (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \ + (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u)))) + +#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00U) && \ + (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00U)) + +#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U) + +#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00U) + +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG)) + +#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u) + +#define IS_EXTI_PENDING_EDGE(__EDGE__) (((__EDGE__) == EXTI_TRIGGER_RISING) || \ + ((__EDGE__) == EXTI_TRIGGER_FALLING)|| \ + ((__EDGE__) == EXTI_TRIGGER_RISING_FALLING)) + +#define IS_EXTI_CB(__CB__) ((__CB__) == HAL_EXTI_COMMON_CB_ID) +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI Exported Functions + * @brief EXTI Exported Functions + * @{ + */ + +/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions + * @brief Configuration functions + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G4xx_HAL_EXTI_H */ + diff --git a/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h new file mode 100644 index 000000000..98f78f015 --- /dev/null +++ b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h @@ -0,0 +1,1018 @@ +/** + ****************************************************************************** + * @file stm32g4xx_hal_flash.h + * @author MCD Application Team + * @brief Header file of FLASH HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G4xx_HAL_FLASH_H +#define STM32G4xx_HAL_FLASH_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_hal_def.h" + +/** @addtogroup STM32G4xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t TypeErase; /*!< Mass erase or page erase. + This parameter can be a value of @ref FLASH_Type_Erase */ + uint32_t Banks; /*!< Select bank to erase. + This parameter must be a value of @ref FLASH_Banks + (FLASH_BANK_BOTH should be used only for mass erase) */ + uint32_t Page; /*!< Initial Flash page to erase when page erase is disabled. + This parameter must be a value between 0 and (max number of pages in the bank - 1) + (eg : 127 for 512KB dual bank) */ + uint32_t NbPages; /*!< Number of pages to be erased. + This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/ +} FLASH_EraseInitTypeDef; + +/** + * @brief FLASH Option Bytes Program structure definition + */ +typedef struct +{ + uint32_t OptionType; /*!< Option byte to be configured. + This parameter can be a combination of the values of @ref FLASH_OB_Type */ + uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP). + Only one WRP area could be programmed at the same time. + This parameter can be value of @ref FLASH_OB_WRP_Area */ + uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP). + This parameter must be a value between 0 and (max number of pages in the bank - 1) */ + uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP). + This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1) */ + uint32_t RDPLevel; /*!< Set the read protection level.. (used for OPTIONBYTE_RDP). + This parameter can be a value of @ref FLASH_OB_Read_Protection */ + uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). + This parameter can be a combination of @ref FLASH_OB_USER_Type */ + uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). + This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, + @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, + @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, + @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, + @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2 (*), + @ref FLASH_OB_USER_nBOOT1, @ref FLASH_OB_USER_SRAM_PE, + @ref FLASH_OB_USER_CCMSRAM_RST + @note (*) availability depends on devices */ + uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP). + This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH) + and @ref FLASH_OB_PCROP_RDP */ + uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). + This parameter must be a value between begin and end of bank + => Be careful of the bank swapping for the address */ + uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). + This parameter must be a value between PCROP Start address and end of bank */ + uint32_t BootEntryPoint; /*!< Set the Boot Lock (used for OPTIONBYTE_BOOT_LOCK). + This parameter can be a value of @ref FLASH_OB_Boot_Lock */ + uint32_t SecBank; /*!< Bank of securable memory area to be programmed (used for OPTIONBYTE_SEC). + Only one securable memory area could be programmed at the same time. + This parameter can be one of the following values: + FLASH_BANK_1: Securable memory area to be programmed in bank 1 + FLASH_BANK_2: Securable memory area to be programmed in bank 2 (*) + @note (*) availability depends on devices */ + uint32_t SecSize; /*!< Size of securable memory area to be programmed (used for OPTIONBYTE_SEC), + in number of pages. Securable memory area is starting from first page of the bank. + Only one securable memory could be programmed at the same time. + This parameter must be a value between 0 and (max number of pages in the bank - 1) */ +} FLASH_OBProgramInitTypeDef; + +/** + * @brief FLASH Procedure structure definition + */ +typedef enum +{ + FLASH_PROC_NONE = 0, + FLASH_PROC_PAGE_ERASE, + FLASH_PROC_MASS_ERASE, + FLASH_PROC_PROGRAM, + FLASH_PROC_PROGRAM_LAST +} FLASH_ProcedureTypeDef; + +/** + * @brief FLASH Cache structure definition + */ +typedef enum +{ + FLASH_CACHE_DISABLED = 0, + FLASH_CACHE_ICACHE_ENABLED, + FLASH_CACHE_DCACHE_ENABLED, + FLASH_CACHE_ICACHE_DCACHE_ENABLED +} FLASH_CacheTypeDef; + +/** + * @brief FLASH handle Structure definition + */ +typedef struct +{ + HAL_LockTypeDef Lock; /* FLASH locking object */ + __IO uint32_t ErrorCode; /* FLASH error code */ + __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */ + __IO uint32_t Address; /* Internal variable to save address selected for program in IT context */ + __IO uint32_t Bank; /* Internal variable to save current bank selected during erase in IT context */ + __IO uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */ + __IO uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */ + __IO FLASH_CacheTypeDef CacheToReactivate; /* Internal variable to indicate which caches should be reactivated */ +} FLASH_ProcessTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Constants FLASH Exported Constants + * @{ + */ + +/** @defgroup FLASH_Error FLASH Error + * @{ + */ +#define HAL_FLASH_ERROR_NONE 0x00000000U +#define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR +#define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR +#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR +#define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR +#define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR +#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR +#define HAL_FLASH_ERROR_MIS FLASH_FLAG_MISERR +#define HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR +#define HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR +#define HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR +#define HAL_FLASH_ERROR_ECCC FLASH_FLAG_ECCC +#define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD +#if defined (FLASH_OPTR_DBANK) +#define HAL_FLASH_ERROR_ECCC2 FLASH_FLAG_ECCC2 +#define HAL_FLASH_ERROR_ECCD2 FLASH_FLAG_ECCD2 +#endif +/** + * @} + */ + +/** @defgroup FLASH_Type_Erase FLASH Erase Type + * @{ + */ +#define FLASH_TYPEERASE_PAGES 0x00U /*!> 24U) /*!< ECC Correction Interrupt source */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Macros FLASH Exported Macros + * @brief macros to control FLASH features + * @{ + */ + +/** + * @brief Set the FLASH Latency. + * @param __LATENCY__ FLASH Latency. + * This parameter can be one of the following values : + * @arg FLASH_LATENCY_0: FLASH Zero wait state + * @arg FLASH_LATENCY_1: FLASH One wait state + * @arg FLASH_LATENCY_2: FLASH Two wait states + * @arg FLASH_LATENCY_3: FLASH Three wait states + * @arg FLASH_LATENCY_4: FLASH Four wait states + * @arg FLASH_LATENCY_5: FLASH Five wait states + * @arg FLASH_LATENCY_6: FLASH Six wait states + * @arg FLASH_LATENCY_7: FLASH Seven wait states + * @arg FLASH_LATENCY_8: FLASH Eight wait states + * @arg FLASH_LATENCY_9: FLASH Nine wait states + * @arg FLASH_LATENCY_10: FLASH Ten wait state + * @arg FLASH_LATENCY_11: FLASH Eleven wait state + * @arg FLASH_LATENCY_12: FLASH Twelve wait states + * @arg FLASH_LATENCY_13: FLASH Thirteen wait states + * @arg FLASH_LATENCY_14: FLASH Fourteen wait states + * @arg FLASH_LATENCY_15: FLASH Fifteen wait states + * @retval None + */ +#define __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)) + +/** + * @brief Get the FLASH Latency. + * @retval FLASH_Latency. + * This parameter can be one of the following values : + * @arg FLASH_LATENCY_0: FLASH Zero wait state + * @arg FLASH_LATENCY_1: FLASH One wait state + * @arg FLASH_LATENCY_2: FLASH Two wait states + * @arg FLASH_LATENCY_3: FLASH Three wait states + * @arg FLASH_LATENCY_4: FLASH Four wait states + * @arg FLASH_LATENCY_5: FLASH Five wait states + * @arg FLASH_LATENCY_6: FLASH Six wait states + * @arg FLASH_LATENCY_7: FLASH Seven wait states + * @arg FLASH_LATENCY_8: FLASH Eight wait states + * @arg FLASH_LATENCY_9: FLASH Nine wait states + * @arg FLASH_LATENCY_10: FLASH Ten wait state + * @arg FLASH_LATENCY_11: FLASH Eleven wait state + * @arg FLASH_LATENCY_12: FLASH Twelve wait states + * @arg FLASH_LATENCY_13: FLASH Thirteen wait states + * @arg FLASH_LATENCY_14: FLASH Fourteen wait states + * @arg FLASH_LATENCY_15: FLASH Fifteen wait states + */ +#define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) + +/** + * @brief Enable the FLASH prefetch buffer. + * @retval None + */ +#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) + +/** + * @brief Disable the FLASH prefetch buffer. + * @retval None + */ +#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) + +/** + * @brief Enable the FLASH instruction cache. + * @retval none + */ +#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN) + +/** + * @brief Disable the FLASH instruction cache. + * @retval none + */ +#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN) + +/** + * @brief Enable the FLASH data cache. + * @retval none + */ +#define __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN) + +/** + * @brief Disable the FLASH data cache. + * @retval none + */ +#define __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN) + +/** + * @brief Reset the FLASH instruction Cache. + * @note This function must be used only when the Instruction Cache is disabled. + * @retval None + */ +#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ + } while (0) + +/** + * @brief Reset the FLASH data Cache. + * @note This function must be used only when the data Cache is disabled. + * @retval None + */ +#define __HAL_FLASH_DATA_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ + } while (0) + +/** + * @brief Enable the FLASH power down during Low-power run mode. + * @note Writing this bit to 1, automatically the keys are + * lost and a new unlock sequence is necessary to re-write it to 0. + */ +#define __HAL_FLASH_POWER_DOWN_ENABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \ + WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \ + SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \ + } while (0) + +/** + * @brief Disable the FLASH power down during Low-power run mode. + * @note Writing this bit to 0, automatically the keys are + * lost and a new unlock sequence is necessary to re-write it to 1. + */ +#define __HAL_FLASH_POWER_DOWN_DISABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \ + WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \ + } while (0) + +/** + * @brief Enable the FLASH power down during Low-Power sleep mode + * @retval none + */ +#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) + +/** + * @brief Disable the FLASH power down during Low-Power sleep mode + * @retval none + */ +#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) + +/** + * @} + */ + +/** @defgroup FLASH_Interrupt FLASH Interrupts Macros + * @brief macros to handle FLASH interrupts + * @{ + */ + +/** + * @brief Enable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt + * @arg FLASH_IT_OPERR: Error Interrupt + * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt + * @arg FLASH_IT_ECCC: ECC Correction Interrupt + * @retval none + */ +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ + if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ + } while (0) + +/** + * @brief Disable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt + * @arg FLASH_IT_OPERR: Error Interrupt + * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt + * @arg FLASH_IT_ECCC: ECC Correction Interrupt + * @retval none + */ +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ + if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ + } while (0) + +/** + * @brief Check whether the specified FLASH flag is set or not. + * @param __FLAG__ specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg FLASH_FLAG_EOP: FLASH End of Operation flag + * @arg FLASH_FLAG_OPERR: FLASH Operation error flag + * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag + * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag + * @arg FLASH_FLAG_SIZERR: FLASH Size error flag + * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag + * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag + * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag + * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag + * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag + * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag + * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected in 64 LSB bits + * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected in 64 LSB bits + * @arg FLASH_FLAG_ECCC2(*): FLASH one ECC error has been detected and corrected in 64 MSB bits (mode 128 bits only) + * @arg FLASH_FLAG_ECCD2(*): FLASH two ECC errors have been detected in 64 MSB bits (mode 128 bits only) + * @note (*) availability depends on devices + * @retval The new state of FLASH_FLAG (SET or RESET). + */ +#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) ? \ + (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ + (READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__))) + +/** + * @brief Clear the FLASH's pending flags. + * @param __FLAG__ specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg FLASH_FLAG_EOP: FLASH End of Operation flag + * @arg FLASH_FLAG_OPERR: FLASH Operation error flag + * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag + * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag + * @arg FLASH_FLAG_SIZERR: FLASH Size error flag + * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag + * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag + * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag + * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag + * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag + * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected in 64 LSB bits + * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected in 64 LSB bits + * @arg FLASH_FLAG_ECCC2(*): FLASH one ECC error has been detected and corrected in 64 MSB bits (mode 128 bits only) + * @arg FLASH_FLAG_ECCD2(*): FLASH two ECC errors have been detected in 64 MSB bits (mode 128 bits only) + * @arg FLASH_FLAG_SR_ERRORS: FLASH All SR errors flags + * @arg FLASH_FLAG_ECCR_ERRORS: FLASH All ECCR errors flags + * @note (*) availability depends on devices + * @retval None + */ +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\ + if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\ + } while (0) +/** + * @} + */ + +/* Include FLASH HAL Extended module */ +#include "stm32g4xx_hal_flash_ex.h" +#include "stm32g4xx_hal_flash_ramfunc.h" + +/* Exported variables --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Variables FLASH Exported Variables + * @{ + */ +extern FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASH_Exported_Functions + * @{ + */ + +/* Program operation functions ***********************************************/ +/** @addtogroup FLASH_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +/* FLASH IRQ handler method */ +void HAL_FLASH_IRQHandler(void); +/* Callbacks in non blocking modes */ +void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); +void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); +/** + * @} + */ + +/* Peripheral Control functions **********************************************/ +/** @addtogroup FLASH_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_Lock(void); +/* Option bytes control */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); +/** + * @} + */ + +/* Peripheral State functions ************************************************/ +/** @addtogroup FLASH_Exported_Functions_Group3 + * @{ + */ +uint32_t HAL_FLASH_GetError(void); +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +/** + * @} + */ + +/* Private constants --------------------------------------------------------*/ +/** @defgroup FLASH_Private_Constants FLASH Private Constants + * @{ + */ +#define FLASH_SIZE_DATA_REGISTER FLASHSIZE_BASE + +#if defined (FLASH_OPTR_DBANK) +#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x200UL << 10U) : \ + (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & 0xFFFFUL) << 10U)) +#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) +#define FLASH_PAGE_NB ((FLASH_SIZE == 0x00080000U) ? 128U : \ + ((FLASH_SIZE == 0x00040000U) ? 64U : 32U)) +#define FLASH_PAGE_SIZE_128_BITS 0x1000U /* 4 KB */ +#else +#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x80UL << 10U) : \ + (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & 0xFFFFUL) << 10U)) +#define FLASH_BANK_SIZE (FLASH_SIZE) +#define FLASH_PAGE_NB ((FLASH_SIZE == 0x00080000U) ? 256U : \ + ((FLASH_SIZE == 0x00040000U) ? 128U : 64U)) +#endif + +#define FLASH_PAGE_SIZE 0x800U /* 2 KB */ + +#define FLASH_TIMEOUT_VALUE 1000U /* 1 s */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ + +#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ + ((VALUE) == FLASH_TYPEERASE_MASSERASE)) + +#if defined (FLASH_OPTR_DBANK) +#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ + ((BANK) == FLASH_BANK_2) || \ + ((BANK) == FLASH_BANK_BOTH)) + +#define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \ + ((BANK) == FLASH_BANK_2)) +#else +#define IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1) + +#define IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1) +#endif + +#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \ + ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST)) + +#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE))) + +#define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000U) && ((ADDRESS) <= 0x1FFF73FFU)) + +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS)) + +#define IS_FLASH_PAGE(PAGE) ((PAGE) < FLASH_PAGE_NB) + +#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP | \ + OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_SEC))) + +#if defined (FLASH_OPTR_DBANK) +#define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \ + ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB)) +#else +#define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB)) +#endif + +#define IS_OB_BOOT_LOCK(VALUE) (((VALUE) == OB_BOOT_LOCK_ENABLE) || ((VALUE) == OB_BOOT_LOCK_DISABLE)) + +#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ + ((LEVEL) == OB_RDP_LEVEL_1) ||\ + ((LEVEL) == OB_RDP_LEVEL_2)) + +#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= 0x1FFFFU) && ((TYPE) != 0U)) + +#define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \ + ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \ + ((LEVEL) == OB_BOR_LEVEL_4)) + +#define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST)) + +#define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST)) + +#define IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST)) + +#define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW)) + +#define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN)) + +#define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN)) + +#define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW)) + +#if defined (FLASH_OPTR_DBANK) +#define IS_OB_USER_BFB2(VALUE) (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE)) + +#define IS_OB_USER_DBANK(VALUE) (((VALUE) == OB_DBANK_128_BITS) || ((VALUE) == OB_DBANK_64_BITS)) +#endif + +#if defined (FLASH_OPTR_PB4_PUPEN) +#define IS_OB_USER_PB4_PUPEN(VALUE) (((VALUE) == OB_PB4_PUPEN_DISABLE) || ((VALUE) == OB_PB4_PUPEN_ENABLE)) +#endif + +#define IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM)) + +#define IS_OB_USER_SRAM_PARITY(VALUE) (((VALUE) == OB_SRAM_PARITY_ENABLE) || ((VALUE) == OB_SRAM_PARITY_DISABLE)) + +#define IS_OB_USER_CCMSRAM_RST(VALUE) (((VALUE) == OB_CCMSRAM_RST_ERASE) || ((VALUE) == OB_CCMSRAM_RST_NOT_ERASE)) + +#define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN)) + +#define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_nBOOT0_RESET) || ((VALUE) == OB_nBOOT0_SET)) + +#define IS_OB_USER_NRST_MODE(VALUE) (((VALUE) == OB_NRST_MODE_GPIO) || ((VALUE) == OB_NRST_MODE_INPUT_ONLY) || \ + ((VALUE) == OB_NRST_MODE_INPUT_OUTPUT)) + +#define IS_OB_USER_IRHEN(VALUE) (((VALUE) == OB_IRH_ENABLE) || ((VALUE) == OB_IRH_DISABLE)) + +#define IS_OB_PCROP_RDP(VALUE) (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE)) + +#define IS_OB_SECMEM_SIZE(VALUE) ((VALUE) <= FLASH_PAGE_NB) + +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \ + ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \ + ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \ + ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \ + ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \ + ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \ + ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \ + ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G4xx_HAL_FLASH_H */ + diff --git a/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h new file mode 100644 index 000000000..f32e8102e --- /dev/null +++ b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h @@ -0,0 +1,89 @@ +/** + ****************************************************************************** + * @file stm32g4xx_hal_flash_ex.h + * @author MCD Application Team + * @brief Header file of FLASH HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G4xx_HAL_FLASH_EX_H +#define STM32G4xx_HAL_FLASH_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_hal_def.h" + +/** @addtogroup STM32G4xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASHEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASHEx_Exported_Functions + * @{ + */ + +/* Extended Program operation functions *************************************/ +/** @addtogroup FLASHEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); +HAL_StatusTypeDef HAL_FLASHEx_EnableSecMemProtection(uint32_t Bank); +void HAL_FLASHEx_EnableDebugger(void); +void HAL_FLASHEx_DisableDebugger(void); +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASHEx_Private_Functions + * @{ + */ +void FLASH_PageErase(uint32_t Page, uint32_t Banks); +void FLASH_FlushCaches(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G4xx_HAL_FLASH_EX_H */ + diff --git a/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32_assert_template.h b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h similarity index 50% rename from Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32_assert_template.h rename to Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h index ef5d596b8..753bb3387 100644 --- a/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32_assert_template.h +++ b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h @@ -1,55 +1,74 @@ /** ****************************************************************************** - * @file stm32_assert.h + * @file stm32g4xx_hal_flash_ramfunc.h * @author MCD Application Team - * @brief STM32 assert template file. - * This file should be copied to the application folder and renamed - * to stm32_assert.h. + * @brief Header file of FLASH RAMFUNC driver. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. - * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32_ASSERT_H -#define STM32_ASSERT_H +#ifndef STM32G4xx_FLASH_RAMFUNC_H +#define STM32G4xx_FLASH_RAMFUNC_H #ifdef __cplusplus extern "C" { #endif -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_hal_def.h" + +/** @addtogroup STM32G4xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH_RAMFUNC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASH_RAMFUNC_Exported_Functions + * @{ + */ + +/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1 + * @{ + */ +/* Peripheral Control functions ************************************************/ +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void); +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void); +#if defined (FLASH_OPTR_DBANK) +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig); +#endif /** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ -#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ -void assert_failed(uint8_t *file, uint32_t line); -#else -#define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ #ifdef __cplusplus } #endif -#endif /* STM32_ASSERT_H */ - +#endif /* STM32G4xx_FLASH_RAMFUNC_H */ diff --git a/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h new file mode 100644 index 000000000..d0954d040 --- /dev/null +++ b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h @@ -0,0 +1,326 @@ +/** + ****************************************************************************** + * @file stm32g4xx_hal_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G4xx_HAL_GPIO_H +#define STM32G4xx_HAL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_hal_def.h" + +/** @addtogroup STM32G4xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Types GPIO Exported Types + * @{ + */ +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode */ + + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull */ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_speed */ + + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins + This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ +} GPIO_InitTypeDef; + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + GPIO_PIN_RESET = 0U, + GPIO_PIN_SET +} GPIO_PinState; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Constants GPIO Exported Constants + * @{ + */ +/** @defgroup GPIO_pins GPIO pins + * @{ + */ +#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ + +#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */ +/** + * @} + */ + +/** @defgroup GPIO_mode GPIO mode + * @brief GPIO Configuration Mode + * Elements values convention: 0x00WX00YZ + * - W : EXTI trigger detection on 3 bits + * - X : EXTI mode (IT or Event) on 2 bits + * - Y : Output type (Push Pull or Open Drain) on 1 bit + * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits + * @{ + */ +#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */ + +#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */ + +#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ + +#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup GPIO_speed GPIO speed + * @brief GPIO Output Maximum frequency + * @{ + */ +#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< range up to 5 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< range 5 MHz to 25 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_HIGH (0x00000002U) /*!< range 25 MHz to 50 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U) /*!< range 50 MHz to 120 MHz, please refer to the product datasheet */ +/** + * @} + */ + +/** @defgroup GPIO_pull GPIO pull + * @brief GPIO Pull-Up or Pull-Down Activation + * @{ + */ +#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */ +#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** + * @brief Check whether the specified EXTI line flag is set or not. + * @param __EXTI_LINE__ specifies the EXTI line flag to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__)) + +/** + * @brief Clear the EXTI's line pending flags. + * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__)) + +/** + * @brief Check whether the specified EXTI line is asserted or not. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__)) + +/** + * @brief Clear the EXTI's line pending bits. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__)) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__)) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ +#define GPIO_MODE_Pos 0U +#define GPIO_MODE (0x3UL << GPIO_MODE_Pos) +#define MODE_INPUT (0x0UL << GPIO_MODE_Pos) +#define MODE_OUTPUT (0x1UL << GPIO_MODE_Pos) +#define MODE_AF (0x2UL << GPIO_MODE_Pos) +#define MODE_ANALOG (0x3UL << GPIO_MODE_Pos) +#define OUTPUT_TYPE_Pos 4U +#define OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos) +#define OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos) +#define OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos) +#define EXTI_MODE_Pos 16U +#define EXTI_MODE (0x3UL << EXTI_MODE_Pos) +#define EXTI_IT (0x1UL << EXTI_MODE_Pos) +#define EXTI_EVT (0x2UL << EXTI_MODE_Pos) +#define TRIGGER_MODE_Pos 20U +#define TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos) +#define TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos) +#define TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos) +/** + * @} + */ + +/** @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) + +#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ + (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) + +#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\ + ((__MODE__) == GPIO_MODE_AF_PP) ||\ + ((__MODE__) == GPIO_MODE_AF_OD) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING) ||\ + ((__MODE__) == GPIO_MODE_IT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING) ||\ + ((__MODE__) == GPIO_MODE_EVT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_ANALOG)) + +#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_HIGH) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH)) + +#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\ + ((__PULL__) == GPIO_PULLUP) || \ + ((__PULL__) == GPIO_PULLDOWN)) +/** + * @} + */ + +/* Include GPIO HAL Extended module */ +#include "stm32g4xx_hal_gpio_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Functions GPIO Exported Functions + * @brief GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G4xx_HAL_GPIO_H */ + diff --git a/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h new file mode 100644 index 000000000..e1513a213 --- /dev/null +++ b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h @@ -0,0 +1,340 @@ +/** + ****************************************************************************** + * @file stm32g4xx_hal_gpio_ex.h + * @author MCD Application Team + * @brief Header file of GPIO HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G4xx_HAL_GPIO_EX_H +#define STM32G4xx_HAL_GPIO_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_hal_def.h" + +/** @addtogroup STM32G4xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIOEx GPIOEx + * @brief GPIO Extended HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants + * @{ + */ + +/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection + * @{ + */ + +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ +#if defined(TIM5) +#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */ +#endif /* TIM5 */ +#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */ +#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */ +#define GPIO_AF1_TIM17_COMP1 ((uint8_t)0x01) /* TIM17/COMP1 Break in Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */ +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#if defined(TIM5) +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ +#endif /* TIM5 */ +#define GPIO_AF2_TIM8 ((uint8_t)0x02) /* TIM8 Alternate Function mapping */ +#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02) /* TIM16 Alternate Function mapping */ +#if defined(TIM20) +#define GPIO_AF2_TIM20 ((uint8_t)0x02) /* TIM20 Alternate Function mapping */ +#endif /* TIM20 */ +#define GPIO_AF2_TIM1_COMP1 ((uint8_t)0x02) /* TIM1/COMP1 Break in Alternate Function mapping */ +#define GPIO_AF2_TIM15_COMP1 ((uint8_t)0x02) /* TIM15/COMP1 Break in Alternate Function mapping */ +#define GPIO_AF2_TIM16_COMP1 ((uint8_t)0x02) /* TIM16/COMP1 Break in Alternate Function mapping */ +#if defined(TIM20) +#define GPIO_AF2_TIM20_COMP1 ((uint8_t)0x02) /* TIM20/COMP1 Break in Alternate Function mapping */ +#define GPIO_AF2_TIM20_COMP2 ((uint8_t)0x02) /* TIM20/COMP2 Break in Alternate Function mapping */ +#endif /* TIM20 */ +#define GPIO_AF2_I2C3 ((uint8_t)0x02) /* I2C3 Alternate Function mapping */ +#define GPIO_AF2_COMP1 ((uint8_t)0x02) /* COMP1 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */ +#if defined(TIM20) +#define GPIO_AF3_TIM20 ((uint8_t)0x03) /* TIM20 Alternate Function mapping */ +#endif /* TIM20 */ +#define GPIO_AF3_UCPD1 ((uint8_t)0x03) /* UCPD1 Alternate Function mapping */ +#define GPIO_AF3_I2C3 ((uint8_t)0x03) /* I2C3 Alternate Function mapping */ +#if defined(I2C4) +#define GPIO_AF3_I2C4 ((uint8_t)0x03) /* I2C4 Alternate Function mapping */ +#endif /* I2C4 */ +#if defined(HRTIM1) +#define GPIO_AF3_HRTIM1 ((uint8_t)0x03) /* HRTIM1 Alternate Function mapping */ +#endif /* HRTIM1 */ +#if defined(QUADSPI) +#define GPIO_AF3_QUADSPI ((uint8_t)0x03) /* QUADSPI Alternate Function mapping */ +#endif /* QUADSPI */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_SAI1 ((uint8_t)0x03) /* SAI1 Alternate Function mapping */ +#define GPIO_AF3_COMP3 ((uint8_t)0x03) /* COMP3 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */ +#define GPIO_AF4_TIM8 ((uint8_t)0x04) /* TIM8 Alternate Function mapping */ +#define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */ +#define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */ +#define GPIO_AF4_TIM8_COMP1 ((uint8_t)0x04) /* TIM8/COMP1 Break in Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ +#if defined(I2C4) +#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */ +#endif /* I2C4 */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ +#if defined(SPI4) +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ +#endif /* SPI4 */ +#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */ +#define GPIO_AF5_TIM8 ((uint8_t)0x05) /* TIM8 Alternate Function mapping */ +#define GPIO_AF5_TIM8_COMP1 ((uint8_t)0x05) /* TIM8/COMP1 Break in Alternate Function mapping */ +#define GPIO_AF5_UART4 ((uint8_t)0x05) /* UART4 Alternate Function mapping */ +#if defined(UART5) +#define GPIO_AF5_UART5 ((uint8_t)0x05) /* UART5 Alternate Function mapping */ +#endif /* UART5 */ +#define GPIO_AF5_I2S2ext ((uint8_t)0x05) /* I2S2ext_SD Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */ +#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */ +#if defined(TIM5) +#define GPIO_AF6_TIM5 ((uint8_t)0x06) /* TIM5 Alternate Function mapping */ +#endif /* TIM5 */ +#define GPIO_AF6_TIM8 ((uint8_t)0x06) /* TIM8 Alternate Function mapping */ +#if defined(TIM20) +#define GPIO_AF6_TIM20 ((uint8_t)0x06) /* TIM20 Alternate Function mapping */ +#endif /* TIM20 */ +#define GPIO_AF6_TIM1_COMP1 ((uint8_t)0x06) /* TIM1/COMP1 Break in Alternate Function mapping */ +#define GPIO_AF6_TIM1_COMP2 ((uint8_t)0x06) /* TIM1/COMP2 Break in Alternate Function mapping */ +#define GPIO_AF6_TIM8_COMP2 ((uint8_t)0x06) /* TIM8/COMP2 Break in Alternate Function mapping */ +#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */ +#define GPIO_AF6_I2S3ext ((uint8_t)0x06) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#if defined(COMP5) +#define GPIO_AF7_COMP5 ((uint8_t)0x07) /* COMP5 Alternate Function mapping */ +#endif /* COMP5 */ +#if defined(COMP6) +#define GPIO_AF7_COMP6 ((uint8_t)0x07) /* COMP6 Alternate Function mapping */ +#endif /* COMP6 */ +#if defined(COMP7) +#define GPIO_AF7_COMP7 ((uint8_t)0x07) /* COMP7 Alternate Function mapping */ +#endif /* COMP7 */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */ +#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */ +#define GPIO_AF8_COMP3 ((uint8_t)0x08) /* COMP3 Alternate Function mapping */ +#define GPIO_AF8_COMP4 ((uint8_t)0x08) /* COMP4 Alternate Function mapping */ +#if defined(COMP5) +#define GPIO_AF8_COMP5 ((uint8_t)0x08) /* COMP5 Alternate Function mapping */ +#endif /* COMP5 */ +#if defined(COMP6) +#define GPIO_AF8_COMP6 ((uint8_t)0x08) /* COMP6 Alternate Function mapping */ +#endif /* COMP6 */ +#if defined(COMP7) +#define GPIO_AF8_COMP7 ((uint8_t)0x08) /* COMP7 Alternate Function mapping */ +#endif /* COMP7 */ +#define GPIO_AF8_I2C3 ((uint8_t)0x08) /* I2C3 Alternate Function mapping */ +#if defined(I2C4) +#define GPIO_AF8_I2C4 ((uint8_t)0x08) /* I2C4 Alternate Function mapping */ +#endif /* I2C4 */ +#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#if defined(UART5) +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#endif /* UART5 */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */ +#define GPIO_AF9_TIM8 ((uint8_t)0x09) /* TIM8 Alternate Function mapping */ +#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */ +#define GPIO_AF9_TIM1_COMP1 ((uint8_t)0x09) /* TIM1/COMP1 Break in Alternate Function mapping */ +#define GPIO_AF9_TIM8_COMP1 ((uint8_t)0x09) /* TIM8/COMP1 Break in Alternate Function mapping */ +#define GPIO_AF9_TIM15_COMP1 ((uint8_t)0x09) /* TIM15/COMP1 Break in Alternate Function mapping */ +#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */ +#if defined(FDCAN2) +#define GPIO_AF9_FDCAN2 ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping */ +#endif /* FDCAN2 */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_TIM2 ((uint8_t)0x0A) /* TIM2 Alternate Function mapping */ +#define GPIO_AF10_TIM3 ((uint8_t)0x0A) /* TIM3 Alternate Function mapping */ +#define GPIO_AF10_TIM4 ((uint8_t)0x0A) /* TIM4 Alternate Function mapping */ +#define GPIO_AF10_TIM8 ((uint8_t)0x0A) /* TIM8 Alternate Function mapping */ +#define GPIO_AF10_TIM17 ((uint8_t)0x0A) /* TIM17 Alternate Function mapping */ +#define GPIO_AF10_TIM8_COMP2 ((uint8_t)0x0A) /* TIM8/COMP2 Break in Alternate Function mapping */ +#define GPIO_AF10_TIM17_COMP1 ((uint8_t)0x0A) /* TIM17/COMP1 Break in Alternate Function mapping */ +#if defined(QUADSPI) +#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* OctoSPI Manager Port 1 Alternate Function mapping */ +#endif /* QUADSPI */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_FDCAN1 ((uint8_t)0x0B) /* FDCAN1 Alternate Function mapping */ +#if defined(FDCAN3) +#define GPIO_AF11_FDCAN3 ((uint8_t)0x0B) /* FDCAN3 Alternate Function mapping */ +#endif /* FDCAN3 */ +#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */ +#define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */ +#define GPIO_AF11_TIM8_COMP1 ((uint8_t)0x0B) /* TIM8/COMP1 Break in Alternate Function mapping */ +#define GPIO_AF11_LPTIM1 ((uint8_t)0x0B) /* LPTIM1 Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_LPUART1 ((uint8_t)0x0C) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */ +#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */ +#define GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */ +#if defined(HRTIM1) +#define GPIO_AF12_HRTIM1 ((uint8_t)0x0C) /* HRTIM1 Alternate Function mapping */ +#endif /* HRTIM1 */ +#if defined(FMC_BANK1) +#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ +#endif /* FMC_BANK1 */ +#define GPIO_AF12_SAI1 ((uint8_t)0x0C) /* SAI1 Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#if defined(HRTIM1) +#define GPIO_AF13_HRTIM1 ((uint8_t)0x0D) /* HRTIM1 Alternate Function mapping */ +#endif /* HRTIM1 */ +#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */ +#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */ +#define GPIO_AF14_UCPD1 ((uint8_t)0x0E) /* UCPD1 Alternate Function mapping */ +#define GPIO_AF14_SAI1 ((uint8_t)0x0E) /* SAI1 Alternate Function mapping */ +#define GPIO_AF14_UART4 ((uint8_t)0x0E) /* UART4 Alternate Function mapping */ +#if defined(UART5) +#define GPIO_AF14_UART5 ((uint8_t)0x0E) /* UART5 Alternate Function mapping */ +#endif /* UART5 */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros + * @{ + */ + +/** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index + * @{ + */ +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\ + ((__GPIOx__) == (GPIOB))? 1UL :\ + ((__GPIOx__) == (GPIOC))? 2UL :\ + ((__GPIOx__) == (GPIOD))? 3UL :\ + ((__GPIOx__) == (GPIOE))? 4UL :\ + ((__GPIOx__) == (GPIOF))? 5UL : 6UL) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G4xx_HAL_GPIO_EX_H */ + diff --git a/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h new file mode 100644 index 000000000..57422ee35 --- /dev/null +++ b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h @@ -0,0 +1,411 @@ +/** + ****************************************************************************** + * @file stm32g4xx_hal_pwr.h + * @author MCD Application Team + * @brief Header file of PWR HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G4xx_HAL_PWR_H +#define STM32G4xx_HAL_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_hal_def.h" + +/** @addtogroup STM32G4xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Types PWR Exported Types + * @{ + */ + +/** + * @brief PWR PVD configuration structure definition + */ +typedef struct +{ + uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. + This parameter can be a value of @ref PWR_PVD_detection_level. */ + + uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. + This parameter can be a value of @ref PWR_PVD_Mode. */ +}PWR_PVDTypeDef; + + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Constants PWR Exported Constants + * @{ + */ + + +/** @defgroup PWR_PVD_detection_level Programmable Voltage Detection levels + * @{ + */ +#define PWR_PVDLEVEL_0 PWR_CR2_PLS_LEV0 /*!< PVD threshold around 2.0 V */ +#define PWR_PVDLEVEL_1 PWR_CR2_PLS_LEV1 /*!< PVD threshold around 2.2 V */ +#define PWR_PVDLEVEL_2 PWR_CR2_PLS_LEV2 /*!< PVD threshold around 2.4 V */ +#define PWR_PVDLEVEL_3 PWR_CR2_PLS_LEV3 /*!< PVD threshold around 2.5 V */ +#define PWR_PVDLEVEL_4 PWR_CR2_PLS_LEV4 /*!< PVD threshold around 2.6 V */ +#define PWR_PVDLEVEL_5 PWR_CR2_PLS_LEV5 /*!< PVD threshold around 2.8 V */ +#define PWR_PVDLEVEL_6 PWR_CR2_PLS_LEV6 /*!< PVD threshold around 2.9 V */ +#define PWR_PVDLEVEL_7 PWR_CR2_PLS_LEV7 /*!< External input analog voltage (compared internally to VREFINT) */ +/** + * @} + */ + +/** @defgroup PWR_PVD_Mode PWR PVD interrupt and event mode + * @{ + */ +#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< Basic mode is used */ +#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + + + + +/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR regulator mode + * @{ + */ +#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) /*!< Regulator in main mode */ +#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPR /*!< Regulator in low-power mode */ +/** + * @} + */ + +/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry + * @{ + */ +#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Sleep mode */ +#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Sleep mode */ +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry + * @{ + */ +#define PWR_STOPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Stop mode */ +#define PWR_STOPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Stop mode */ +/** + * @} + */ + + +/** @defgroup PWR_PVD_EXTI_LINE PWR PVD external interrupt line + * @{ + */ +#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ +/** + * @} + */ + +/** @defgroup PWR_PVD_EVENT_LINE PWR PVD event line + * @{ + */ +#define PWR_EVENT_LINE_PVD ((uint32_t)0x00010000) /*!< Event line 16 Connected to the PVD Event Line */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup PWR_Exported_Macros PWR Exported Macros + * @{ + */ + +/** @brief Check whether or not a specific PWR flag is set. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event + * was received from the WKUP pin 1. + * @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event + * was received from the WKUP pin 2. + * @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event + * was received from the WKUP pin 3. + * @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event + * was received from the WKUP pin 4. + * @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event + * was received from the WKUP pin 5. + * @arg @ref PWR_FLAG_SB StandBy Flag. Indicates that the system + * entered StandBy mode. + * @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on + * the internal wakeup line. + * @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the + * low-power regulator is ready. + * @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the + * regulator is ready in main mode or is in low-power mode. + * @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready + * in the selected voltage range or is still changing to the required voltage level. + * @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is + * below or above the selected PVD threshold. +@if PWR_CR2_PVME1 + * @arg @ref PWR_FLAG_PVMO1 Peripheral Voltage Monitoring Output 1. Indicates whether VDDUSB voltage is + * is below or above PVM1 threshold (applicable when USB feature is supported). +@endif +@if PWR_CR2_PVME2 + * @arg @ref PWR_FLAG_PVMO2 Peripheral Voltage Monitoring Output 2. Indicates whether VDDIO2 voltage is + * is below or above PVM2 threshold (applicable when VDDIO2 is present on device). +@endif + * @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is + * is below or above PVM3 threshold. + * @arg @ref PWR_FLAG_PVMO4 Peripheral Voltage Monitoring Output 4. Indicates whether VDDA voltage is + * is below or above PVM4 threshold. + * + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_PWR_GET_FLAG(__FLAG__) ( ((((uint8_t)(__FLAG__)) >> 5U) == 1) ?\ + (PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\ + (PWR->SR2 & (1U << ((__FLAG__) & 31U))) ) + +/** @brief Clear a specific PWR flag. + * @param __FLAG__: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event + * was received from the WKUP pin 1. + * @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event + * was received from the WKUP pin 2. + * @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event + * was received from the WKUP pin 3. + * @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event + * was received from the WKUP pin 4. + * @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event + * was received from the WKUP pin 5. + * @arg @ref PWR_FLAG_WU Encompasses all five Wake Up Flags. + * @arg @ref PWR_FLAG_SB Standby Flag. Indicates that the system + * entered Standby mode. + * @retval None + */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\ + (PWR->SCR = (__FLAG__)) :\ + (PWR->SCR = (1U << ((__FLAG__) & 31U))) ) +/** + * @brief Enable the PVD Extended Interrupt Line. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Line. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Event Line. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD) + +/** + * @brief Disable the PVD Event Line. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Rising Trigger. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Rising Trigger. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) + + +/** + * @brief Disable the PVD Extended Interrupt Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) + + +/** + * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD) + +/** + * @brief Check whether or not the PVD EXTI interrupt flag is set. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR1 & PWR_EXTI_LINE_PVD) + +/** + * @brief Clear the PVD EXTI interrupt flag. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD) + +/** + * @} + */ + + +/* Private macros --------------------------------------------------------*/ +/** @addtogroup PWR_Private_Macros PWR Private Macros + * @{ + */ + +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ + ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ + ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ + ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) + +#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_NORMAL) ||\ + ((MODE) == PWR_PVD_MODE_IT_RISING) ||\ + ((MODE) == PWR_PVD_MODE_IT_FALLING) ||\ + ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\ + ((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\ + ((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\ + ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING)) + +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ + ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) + +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) + +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) ) + +/** + * @} + */ + +/* Include PWR HAL Extended module */ +#include "stm32g4xx_hal_pwr_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions *******************************/ +void HAL_PWR_DeInit(void); +void HAL_PWR_EnableBkUpAccess(void); +void HAL_PWR_DisableBkUpAccess(void); + +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); +void HAL_PWR_EnablePVD(void); +void HAL_PWR_DisablePVD(void); + + +/* WakeUp pins configuration functions ****************************************/ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity); +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); + +/* Low Power modes configuration functions ************************************/ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); +void HAL_PWR_EnterSTANDBYMode(void); + +void HAL_PWR_EnableSleepOnExit(void); +void HAL_PWR_DisableSleepOnExit(void); +void HAL_PWR_EnableSEVOnPend(void); +void HAL_PWR_DisableSEVOnPend(void); + +void HAL_PWR_PVDCallback(void); + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32G4xx_HAL_PWR_H */ + diff --git a/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h new file mode 100644 index 000000000..79fc57f50 --- /dev/null +++ b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h @@ -0,0 +1,817 @@ +/** + ****************************************************************************** + * @file stm32g4xx_hal_pwr_ex.h + * @author MCD Application Team + * @brief Header file of PWR HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G4xx_HAL_PWR_EX_H +#define STM32G4xx_HAL_PWR_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_hal_def.h" + +/** @addtogroup STM32G4xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWREx + * @{ + */ + + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Types PWR Extended Exported Types + * @{ + */ + + +/** + * @brief PWR PVM configuration structure definition + */ +typedef struct +{ + uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold. + This parameter can be a value of @ref PWREx_PVM_Type. */ + uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. + This parameter can be a value of @ref PWREx_PVM_Mode. */ +}PWR_PVMTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants + * @{ + */ + +/** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants + * @{ + */ +#define PWR_WUP_POLARITY_SHIFT 0x05U /*!< Internal constant used to retrieve wakeup pin polariry */ +/** + * @} + */ + + +/** @defgroup PWREx_WakeUp_Pins PWR wake-up pins + * @{ + */ +#define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ +#define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ +#define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ +#define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ +#define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ +#define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ +#define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ +#define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ +#define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ +#define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ +#define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR4_WP1<IMR2, PWR_EXTI_LINE_PVM1) + +/** + * @brief Disable the PVM1 Extended Interrupt Line. + * @retval None + */ +#define __HAL_PWR_PVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1) + +/** + * @brief Enable the PVM1 Event Line. + * @retval None + */ +#define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1) + +/** + * @brief Disable the PVM1 Event Line. + * @retval None + */ +#define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1) + +/** + * @brief Enable the PVM1 Extended Interrupt Rising Trigger. + * @retval None + */ +#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1) + +/** + * @brief Disable the PVM1 Extended Interrupt Rising Trigger. + * @retval None + */ +#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1) + +/** + * @brief Enable the PVM1 Extended Interrupt Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1) + + +/** + * @brief Disable the PVM1 Extended Interrupt Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1) + + +/** + * @brief PVM1 EXTI line configuration: set rising & falling edge trigger. + * @retval None + */ +#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None + */ +#define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1) + +/** + * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not. + * @retval EXTI PVM1 Line Status. + */ +#define __HAL_PWR_PVM1_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM1) + +/** + * @brief Clear the PVM1 EXTI flag. + * @retval None + */ +#define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1) + +#endif /* PWR_CR2_PVME1 */ + + +#if defined(PWR_CR2_PVME2) +/** + * @brief Enable the PVM2 Extended Interrupt Line. + * @retval None + */ +#define __HAL_PWR_PVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2) + +/** + * @brief Disable the PVM2 Extended Interrupt Line. + * @retval None + */ +#define __HAL_PWR_PVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2) + +/** + * @brief Enable the PVM2 Event Line. + * @retval None + */ +#define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2) + +/** + * @brief Disable the PVM2 Event Line. + * @retval None + */ +#define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2) + +/** + * @brief Enable the PVM2 Extended Interrupt Rising Trigger. + * @retval None + */ +#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2) + +/** + * @brief Disable the PVM2 Extended Interrupt Rising Trigger. + * @retval None + */ +#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2) + +/** + * @brief Enable the PVM2 Extended Interrupt Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2) + + +/** + * @brief Disable the PVM2 Extended Interrupt Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2) + + +/** + * @brief PVM2 EXTI line configuration: set rising & falling edge trigger. + * @retval None + */ +#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None + */ +#define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2) + +/** + * @brief Check whether the specified PVM2 EXTI interrupt flag is set or not. + * @retval EXTI PVM2 Line Status. + */ +#define __HAL_PWR_PVM2_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM2) + +/** + * @brief Clear the PVM2 EXTI flag. + * @retval None + */ +#define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2) + +#endif /* PWR_CR2_PVME2 */ + + +/** + * @brief Enable the PVM3 Extended Interrupt Line. + * @retval None + */ +#define __HAL_PWR_PVM3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3) + +/** + * @brief Disable the PVM3 Extended Interrupt Line. + * @retval None + */ +#define __HAL_PWR_PVM3_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3) + +/** + * @brief Enable the PVM3 Event Line. + * @retval None + */ +#define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3) + +/** + * @brief Disable the PVM3 Event Line. + * @retval None + */ +#define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3) + +/** + * @brief Enable the PVM3 Extended Interrupt Rising Trigger. + * @retval None + */ +#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3) + +/** + * @brief Disable the PVM3 Extended Interrupt Rising Trigger. + * @retval None + */ +#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3) + +/** + * @brief Enable the PVM3 Extended Interrupt Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3) + + +/** + * @brief Disable the PVM3 Extended Interrupt Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3) + + +/** + * @brief PVM3 EXTI line configuration: set rising & falling edge trigger. + * @retval None + */ +#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None + */ +#define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3) + +/** + * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not. + * @retval EXTI PVM3 Line Status. + */ +#define __HAL_PWR_PVM3_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM3) + +/** + * @brief Clear the PVM3 EXTI flag. + * @retval None + */ +#define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3) + + + + +/** + * @brief Enable the PVM4 Extended Interrupt Line. + * @retval None + */ +#define __HAL_PWR_PVM4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4) + +/** + * @brief Disable the PVM4 Extended Interrupt Line. + * @retval None + */ +#define __HAL_PWR_PVM4_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4) + +/** + * @brief Enable the PVM4 Event Line. + * @retval None + */ +#define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4) + +/** + * @brief Disable the PVM4 Event Line. + * @retval None + */ +#define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4) + +/** + * @brief Enable the PVM4 Extended Interrupt Rising Trigger. + * @retval None + */ +#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4) + +/** + * @brief Disable the PVM4 Extended Interrupt Rising Trigger. + * @retval None + */ +#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4) + +/** + * @brief Enable the PVM4 Extended Interrupt Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4) + + +/** + * @brief Disable the PVM4 Extended Interrupt Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4) + + +/** + * @brief PVM4 EXTI line configuration: set rising & falling edge trigger. + * @retval None + */ +#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None + */ +#define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4) + +/** + * @brief Check whether or not the specified PVM4 EXTI interrupt flag is set. + * @retval EXTI PVM4 Line Status. + */ +#define __HAL_PWR_PVM4_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM4) + +/** + * @brief Clear the PVM4 EXTI flag. + * @retval None + */ +#define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4) + + +/** + * @brief Configure the main internal regulator output voltage. + * @param __REGULATOR__: specifies the regulator output voltage to achieve + * a tradeoff between performance and power consumption. + * This parameter can be one of the following values: + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1_BOOST Regulator voltage output range 1 mode, + * typical output voltage at 1.28 V, + * system frequency up to 170 MHz. + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, + * typical output voltage at 1.2 V, + * system frequency up to 150 MHz. + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, + * typical output voltage at 1.0 V, + * system frequency up to 26 MHz. + * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check + * whether or not VOSF flag is cleared when moving from range 2 to range 1. User + * may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting. + * @retval None + */ +#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ + __IO uint32_t tmpreg; \ + MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \ + UNUSED(tmpreg); \ + } while(0) + +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @addtogroup PWREx_Private_Macros PWR Extended Private Macros + * @{ + */ + +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ + ((PIN) == PWR_WAKEUP_PIN2) || \ + ((PIN) == PWR_WAKEUP_PIN3) || \ + ((PIN) == PWR_WAKEUP_PIN4) || \ + ((PIN) == PWR_WAKEUP_PIN5) || \ + ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \ + ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \ + ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \ + ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \ + ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \ + ((PIN) == PWR_WAKEUP_PIN1_LOW) || \ + ((PIN) == PWR_WAKEUP_PIN2_LOW) || \ + ((PIN) == PWR_WAKEUP_PIN3_LOW) || \ + ((PIN) == PWR_WAKEUP_PIN4_LOW) || \ + ((PIN) == PWR_WAKEUP_PIN5_LOW)) + +#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\ + ((TYPE) == PWR_PVM_2) ||\ + ((TYPE) == PWR_PVM_3) ||\ + ((TYPE) == PWR_PVM_4)) + +#define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\ + ((MODE) == PWR_PVM_MODE_IT_RISING) ||\ + ((MODE) == PWR_PVM_MODE_IT_FALLING) ||\ + ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\ + ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\ + ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\ + ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) + +#if defined(PWR_CR5_R1MODE) +#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) || \ + ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ + ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) +#else +#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ + ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) +#endif + + +#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ + ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) + +#define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\ + ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE)) + +#define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00U) +#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ + ((GPIO) == PWR_GPIO_B) ||\ + ((GPIO) == PWR_GPIO_C) ||\ + ((GPIO) == PWR_GPIO_D) ||\ + ((GPIO) == PWR_GPIO_E) ||\ + ((GPIO) == PWR_GPIO_F) ||\ + ((GPIO) == PWR_GPIO_G)) + + +/** + * @} + */ + + +/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions + * @{ + */ + +/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions + * @{ + */ + + +/* Peripheral Control functions **********************************************/ +uint32_t HAL_PWREx_GetVoltageRange(void); +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); +void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection); +void HAL_PWREx_DisableBatteryCharging(void); +void HAL_PWREx_EnableInternalWakeUpLine(void); +void HAL_PWREx_DisableInternalWakeUpLine(void); +HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); +HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); +HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); +HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); +void HAL_PWREx_EnablePullUpPullDownConfig(void); +void HAL_PWREx_DisablePullUpPullDownConfig(void); +void HAL_PWREx_EnableSRAM2ContentRetention(void); +void HAL_PWREx_DisableSRAM2ContentRetention(void); +#if defined(PWR_CR2_PVME1) +void HAL_PWREx_EnablePVM1(void); +void HAL_PWREx_DisablePVM1(void); +#endif /* PWR_CR2_PVME1 */ +#if defined(PWR_CR2_PVME2) +void HAL_PWREx_EnablePVM2(void); +void HAL_PWREx_DisablePVM2(void); +#endif /* PWR_CR2_PVME2 */ +void HAL_PWREx_EnablePVM3(void); +void HAL_PWREx_DisablePVM3(void); +void HAL_PWREx_EnablePVM4(void); +void HAL_PWREx_DisablePVM4(void); +HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM); + +/* Low Power modes configuration functions ************************************/ +void HAL_PWREx_EnableLowPowerRunMode(void); +HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void); +void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry); +void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry); +void HAL_PWREx_EnterSHUTDOWNMode(void); + +void HAL_PWREx_PVD_PVM_IRQHandler(void); +#if defined(PWR_CR2_PVME1) +void HAL_PWREx_PVM1Callback(void); +#endif /* PWR_CR2_PVME1 */ +#if defined(PWR_CR2_PVME2) +void HAL_PWREx_PVM2Callback(void); +#endif /* PWR_CR2_PVME2 */ +void HAL_PWREx_PVM3Callback(void); +void HAL_PWREx_PVM4Callback(void); + +#if defined(PWR_CR3_UCPD_STDBY) +void HAL_PWREx_EnableUCPDStandbyMode(void); +void HAL_PWREx_DisableUCPDStandbyMode(void); +#endif /* PWR_CR3_UCPD_STDBY */ +#if defined(PWR_CR3_UCPD_DBDIS) +void HAL_PWREx_EnableUCPDDeadBattery(void); +void HAL_PWREx_DisableUCPDDeadBattery(void); +#endif /* PWR_CR3_UCPD_DBDIS */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32G4xx_HAL_PWR_EX_H */ + diff --git a/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h new file mode 100644 index 000000000..c8f077352 --- /dev/null +++ b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h @@ -0,0 +1,3406 @@ +/** + ****************************************************************************** + * @file stm32g4xx_hal_rcc.h + * @author MCD Application Team + * @brief Header file of RCC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G4xx_HAL_RCC_H +#define STM32G4xx_HAL_RCC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_hal_def.h" + +/** @addtogroup STM32G4xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RCC_Exported_Types RCC Exported Types + * @{ + */ + +/** + * @brief RCC PLL configuration structure definition + */ +typedef struct +{ + uint32_t PLLState; /*!< The new state of the PLL. + This parameter can be a value of @ref RCC_PLL_Config */ + + uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ + + uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. + This parameter must be a value of @ref RCC_PLLM_Clock_Divider */ + + uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. + This parameter must be a number between Min_Data = 8 and Max_Data = 127 */ + + uint32_t PLLP; /*!< PLLP: Division factor for ADC clock. + This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ + + uint32_t PLLQ; /*!< PLLQ: Division factor for SAI, I2S, USB, FDCAN and QUADSPI clocks. + This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ + + uint32_t PLLR; /*!< PLLR: Division for the main system clock. + User have to set the PLLR parameter correctly to not exceed max frequency 170MHZ. + This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ + +}RCC_PLLInitTypeDef; + +/** + * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition + */ +typedef struct +{ + uint32_t OscillatorType; /*!< The oscillators to be configured. + This parameter can be a value of @ref RCC_Oscillator_Type */ + + uint32_t HSEState; /*!< The new state of the HSE. + This parameter can be a value of @ref RCC_HSE_Config */ + + uint32_t LSEState; /*!< The new state of the LSE. + This parameter can be a value of @ref RCC_LSE_Config */ + + uint32_t HSIState; /*!< The new state of the HSI. + This parameter can be a value of @ref RCC_HSI_Config */ + + uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + + uint32_t LSIState; /*!< The new state of the LSI. + This parameter can be a value of @ref RCC_LSI_Config */ + + uint32_t HSI48State; /*!< The new state of the HSI48. + This parameter can be a value of @ref RCC_HSI48_Config */ + + RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ + +}RCC_OscInitTypeDef; + +/** + * @brief RCC System, AHB and APB busses clock configuration structure definition + */ +typedef struct +{ + uint32_t ClockType; /*!< The clock to be configured. + This parameter can be a value of @ref RCC_System_Clock_Type */ + + uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). + This parameter can be a value of @ref RCC_System_Clock_Source */ + + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_AHB_Clock_Source */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ + +}RCC_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_Timeout_Value Timeout Values + * @{ + */ +#define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT +/** + * @} + */ + +/** @defgroup RCC_Oscillator_Type Oscillator Type + * @{ + */ +#define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */ +#define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */ +#define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */ +#define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */ +#define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */ +#define RCC_OSCILLATORTYPE_HSI48 0x00000020U /*!< HSI48 to configure */ +/** + * @} + */ + +/** @defgroup RCC_HSE_Config HSE Config + * @{ + */ +#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ +#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ +#define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */ +/** + * @} + */ + +/** @defgroup RCC_LSE_Config LSE Config + * @{ + */ +#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ +#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ +#define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ +/** + * @} + */ + +/** @defgroup RCC_HSI_Config HSI Config + * @{ + */ +#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ +#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ +#define RCC_HSICALIBRATION_DEFAULT 0x40U /* Default HSI calibration trimming value */ +/** + * @} + */ + +/** @defgroup RCC_LSI_Config LSI Config + * @{ + */ +#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ +#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ +/** + * @} + */ + +/** @defgroup RCC_HSI48_Config HSI48 Config + * @{ + */ +#define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ +#define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */ +/** + * @} + */ + +/** @defgroup RCC_PLL_Config PLL Config + * @{ + */ +#define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */ +#define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ +#define RCC_PLL_ON 0x00000002U /*!< PLL activation */ +/** + * @} + */ + +/** @defgroup RCC_PLLM_Clock_Divider PLLM Clock Divider + * @{ + */ +#define RCC_PLLM_DIV1 0x00000001U /*!< PLLM division factor = 1 */ +#define RCC_PLLM_DIV2 0x00000002U /*!< PLLM division factor = 2 */ +#define RCC_PLLM_DIV3 0x00000003U /*!< PLLM division factor = 3 */ +#define RCC_PLLM_DIV4 0x00000004U /*!< PLLM division factor = 4 */ +#define RCC_PLLM_DIV5 0x00000005U /*!< PLLM division factor = 5 */ +#define RCC_PLLM_DIV6 0x00000006U /*!< PLLM division factor = 6 */ +#define RCC_PLLM_DIV7 0x00000007U /*!< PLLM division factor = 7 */ +#define RCC_PLLM_DIV8 0x00000008U /*!< PLLM division factor = 8 */ +#define RCC_PLLM_DIV9 0x00000009U /*!< PLLM division factor = 9 */ +#define RCC_PLLM_DIV10 0x0000000AU /*!< PLLM division factor = 10 */ +#define RCC_PLLM_DIV11 0x0000000BU /*!< PLLM division factor = 11 */ +#define RCC_PLLM_DIV12 0x0000000CU /*!< PLLM division factor = 12 */ +#define RCC_PLLM_DIV13 0x0000000DU /*!< PLLM division factor = 13 */ +#define RCC_PLLM_DIV14 0x0000000EU /*!< PLLM division factor = 14 */ +#define RCC_PLLM_DIV15 0x0000000FU /*!< PLLM division factor = 15 */ +#define RCC_PLLM_DIV16 0x00000010U /*!< PLLM division factor = 16 */ +/** + * @} + */ + +/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider + * @{ + */ +#define RCC_PLLP_DIV2 0x00000002U /*!< PLLP division factor = 2 */ +#define RCC_PLLP_DIV3 0x00000003U /*!< PLLP division factor = 3 */ +#define RCC_PLLP_DIV4 0x00000004U /*!< PLLP division factor = 4 */ +#define RCC_PLLP_DIV5 0x00000005U /*!< PLLP division factor = 5 */ +#define RCC_PLLP_DIV6 0x00000006U /*!< PLLP division factor = 6 */ +#define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */ +#define RCC_PLLP_DIV8 0x00000008U /*!< PLLP division factor = 8 */ +#define RCC_PLLP_DIV9 0x00000009U /*!< PLLP division factor = 9 */ +#define RCC_PLLP_DIV10 0x0000000AU /*!< PLLP division factor = 10 */ +#define RCC_PLLP_DIV11 0x0000000BU /*!< PLLP division factor = 11 */ +#define RCC_PLLP_DIV12 0x0000000CU /*!< PLLP division factor = 12 */ +#define RCC_PLLP_DIV13 0x0000000DU /*!< PLLP division factor = 13 */ +#define RCC_PLLP_DIV14 0x0000000EU /*!< PLLP division factor = 14 */ +#define RCC_PLLP_DIV15 0x0000000FU /*!< PLLP division factor = 15 */ +#define RCC_PLLP_DIV16 0x00000010U /*!< PLLP division factor = 16 */ +#define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */ +#define RCC_PLLP_DIV18 0x00000012U /*!< PLLP division factor = 18 */ +#define RCC_PLLP_DIV19 0x00000013U /*!< PLLP division factor = 19 */ +#define RCC_PLLP_DIV20 0x00000014U /*!< PLLP division factor = 20 */ +#define RCC_PLLP_DIV21 0x00000015U /*!< PLLP division factor = 21 */ +#define RCC_PLLP_DIV22 0x00000016U /*!< PLLP division factor = 22 */ +#define RCC_PLLP_DIV23 0x00000017U /*!< PLLP division factor = 23 */ +#define RCC_PLLP_DIV24 0x00000018U /*!< PLLP division factor = 24 */ +#define RCC_PLLP_DIV25 0x00000019U /*!< PLLP division factor = 25 */ +#define RCC_PLLP_DIV26 0x0000001AU /*!< PLLP division factor = 26 */ +#define RCC_PLLP_DIV27 0x0000001BU /*!< PLLP division factor = 27 */ +#define RCC_PLLP_DIV28 0x0000001CU /*!< PLLP division factor = 28 */ +#define RCC_PLLP_DIV29 0x0000001DU /*!< PLLP division factor = 29 */ +#define RCC_PLLP_DIV30 0x0000001EU /*!< PLLP division factor = 30 */ +#define RCC_PLLP_DIV31 0x0000001FU /*!< PLLP division factor = 31 */ +/** + * @} + */ + +/** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider + * @{ + */ +#define RCC_PLLQ_DIV2 0x00000002U /*!< PLLQ division factor = 2 */ +#define RCC_PLLQ_DIV4 0x00000004U /*!< PLLQ division factor = 4 */ +#define RCC_PLLQ_DIV6 0x00000006U /*!< PLLQ division factor = 6 */ +#define RCC_PLLQ_DIV8 0x00000008U /*!< PLLQ division factor = 8 */ +/** + * @} + */ + +/** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider + * @{ + */ +#define RCC_PLLR_DIV2 0x00000002U /*!< PLLR division factor = 2 */ +#define RCC_PLLR_DIV4 0x00000004U /*!< PLLR division factor = 4 */ +#define RCC_PLLR_DIV6 0x00000006U /*!< PLLR division factor = 6 */ +#define RCC_PLLR_DIV8 0x00000008U /*!< PLLR division factor = 8 */ +/** + * @} + */ + +/** @defgroup RCC_PLL_Clock_Source PLL Clock Source + * @{ + */ +#define RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as PLL entry clock source */ +#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */ +#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ +/** + * @} + */ + +/** @defgroup RCC_PLL_Clock_Output PLL Clock Output + * @{ + */ +#define RCC_PLL_ADCCLK RCC_PLLCFGR_PLLPEN /*!< PLLADCCLK selection from main PLL */ +#define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /*!< PLL48M1CLK selection from main PLL */ +#define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /*!< PLLCLK selection from main PLL */ +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Type System Clock Type + * @{ + */ +#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ +#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ +#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ +#define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source System Clock Source + * @{ + */ +#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ +#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ +#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status + * @{ + */ +#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Source AHB Clock Source + * @{ + */ +#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ +#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ +#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ +#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ +#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ +#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ +#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ +#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ +#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ +/** + * @} + */ + +/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source + * @{ + */ +#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ +#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ +#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ +#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ +#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Source RTC Clock Source + * @{ + */ +#define RCC_RTCCLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ +/** + * @} + */ + +/** @defgroup RCC_MCO_Index MCO Index + * @{ + */ +/* 32 28 20 16 0 + -------------------------------- + | MCO | GPIO | GPIO | GPIO | + | Index | AF | Port | Pin | + -------------------------------*/ + +#define RCC_MCO_GPIOPORT_POS 16U +#define RCC_MCO_GPIOPORT_MASK (0xFUL << RCC_MCO_GPIOPORT_POS) +#define RCC_MCO_GPIOAF_POS 20U +#define RCC_MCO_GPIOAF_MASK (0xFFUL << RCC_MCO_GPIOAF_POS) +#define RCC_MCO_INDEX_POS 28U +#define RCC_MCO_INDEX_MASK (0x1UL << RCC_MCO_INDEX_POS) +#define RCC_MCO1_INDEX (0x0UL << RCC_MCO_INDEX_POS) /*!< MCO1 index */ +#define RCC_MCO_PA8 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8) +#define RCC_MCO_PG10 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOG) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_10) + +/* Legacy Defines*/ +#define RCC_MCO1 RCC_MCO_PA8 +#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ +/** + * @} + */ + +/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source + * @{ + */ +#define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */ +#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ +#define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */ +#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */ +#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< PLLCLK selection as MCO1 source */ +#define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */ +#define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */ +#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source */ +/** + * @} + */ + +/** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler + * @{ + */ +#define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */ +#define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */ +#define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */ +#define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */ +#define RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_Interrupt Interrupts + * @{ + */ +#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ +#define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ +#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */ +#define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ +#define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ +#define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ +#define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ +#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ +/** + * @} + */ + +/** @defgroup RCC_Flag Flags + * Elements values convention: XXXYYYYYb + * - YYYYY : Flag position in the register + * - XXX : Register index + * - 001: CR register + * - 010: BDCR register + * - 011: CSR register + * - 100: CRRCR register + * @{ + */ +/* Flags in the CR register */ +#define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ +#define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ +#define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */ + +/* Flags in the BDCR register */ +#define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */ +#define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */ + +/* Flags in the CSR register */ +#define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */ +#define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */ +#define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */ +#define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */ +#define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */ +#define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */ +#define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ +#define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ + +/* Flags in the CRRCR register */ +#define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */ +/** + * @} + */ + +/** @defgroup RCC_LSEDrive_Config LSE Drive Config + * @{ + */ +#define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */ +#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ +#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ +#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DMAMUX1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_CORDIC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_FMAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_FLASH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) + +#define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) + +#define __HAL_RCC_DMAMUX1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) + +#define __HAL_RCC_CORDIC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) + +#define __HAL_RCC_FMAC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) + +#define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) + +#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) + +/** + * @} + */ + +/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ADC12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(ADC345_COMMON) +#define __HAL_RCC_ADC345_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* ADC345_COMMON */ + +#define __HAL_RCC_DAC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(DAC2) +#define __HAL_RCC_DAC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* DAC2 */ + +#define __HAL_RCC_DAC3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(DAC4) +#define __HAL_RCC_DAC4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* DAC4 */ + +#if defined(AES) +#define __HAL_RCC_AES_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* AES */ + +#define __HAL_RCC_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) + +#define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) + +#define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) + +#define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) + +#define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) + +#define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) + +#define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) + +#define __HAL_RCC_ADC12_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) + +#if defined(ADC345_COMMON) +#define __HAL_RCC_ADC345_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN) +#endif /* ADC345_COMMON */ + +#define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) + +#if defined(DAC2) +#define __HAL_RCC_DAC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN) +#endif /* DAC2 */ + +#define __HAL_RCC_DAC3_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN) + +#if defined(DAC4) +#define __HAL_RCC_DAC4_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN) +#endif /* DAC4 */ + +#if defined(AES) +#define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); +#endif /* AES */ + +#define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) + +/** + * @} + */ + +/** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#if defined(FMC_BANK1) +#define __HAL_RCC_FMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* FMC_BANK1 */ + +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* QUADSPI */ + +#if defined(FMC_BANK1) +#define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) +#endif /* FMC_BANK1 */ + +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) +#endif /* QUADSPI */ + +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(TIM5) +#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* TIM5 */ + +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_CRS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(UART4) +#define __HAL_RCC_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* UART4 */ + +#if defined(UART5) +#define __HAL_RCC_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* UART5 */ + +#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(FDCAN1) +#define __HAL_RCC_FDCAN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* FDCAN1 */ + +#define __HAL_RCC_PWR_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(I2C4) +#define __HAL_RCC_I2C4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* I2C4 */ + +#define __HAL_RCC_UCPD1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) + +#define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) + +#define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) + +#if defined(TIM5) +#define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) +#endif /* TIM5 */ + +#define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) + +#define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) + +#define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); + +#define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); + +#define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) + +#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) + +#define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) + +#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) + +#define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) + +#if defined(UART4) +#define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) +#endif /* UART4 */ + +#if defined(UART5) +#define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) +#endif /* UART5 */ + +#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) + +#define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) + +#define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN) + +#if defined(FDCAN1) +#define __HAL_RCC_FDCAN_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN) +#endif /* FDCAN1 */ + +#define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) + +#define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) + +#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) + +#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) + +#if defined(I2C4) +#define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) +#endif /* I2C4 */ + +#define __HAL_RCC_UCPD1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(SPI4) +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* SPI4 */ + +#define __HAL_RCC_TIM15_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM16_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM17_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(TIM20) +#define __HAL_RCC_TIM20_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* TIM20 */ + +#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* HRTIM1 */ + +#define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) + +#define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) + +#define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) + +#define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) + +#define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) + +#if defined(SPI4) +#define __HAL_RCC_SPI4_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) +#endif /* SPI4 */ + +#define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) + +#define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) + +#define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) + +#if defined(TIM20) +#define __HAL_RCC_TIM20_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN) +#endif /* TIM20 */ + +#define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) + +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN) +#endif /* HRTIM1 */ + +/** + * @} + */ + +/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the AHB1 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != 0U) + +#define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != 0U) + +#define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != 0U) + +#define __HAL_RCC_CORDIC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) != 0U) + +#define __HAL_RCC_FMAC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) != 0U) + +#define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U) + +#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U) + +#define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == 0U) + +#define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == 0U) + +#define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == 0U) + +#define __HAL_RCC_CORDIC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) == 0U) + +#define __HAL_RCC_FMAC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) == 0U) + +#define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U) + +#define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U) + +/** + * @} + */ + +/** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the AHB2 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U) + +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U) + +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U) + +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U) + +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U) + +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U) + +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U) + +#define __HAL_RCC_ADC12_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) != 0U) + +#if defined(ADC345_COMMON) +#define __HAL_RCC_ADC345_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN) != 0U) +#endif /* ADC345_COMMON */ + +#define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) != 0U) + +#if defined(DAC2) +#define __HAL_RCC_DAC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN) != 0U) +#endif /* DAC2 */ + +#define __HAL_RCC_DAC3_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN) != 0U) + +#if defined(DAC4) +#define __HAL_RCC_DAC4_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN) != 0U) +#endif /* DAC4 */ + +#if defined(AES) +#define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U) +#endif /* AES */ + +#define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U) + + +#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U) + +#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U) + +#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U) + +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U) + +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U) + +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U) + +#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U) + +#define __HAL_RCC_ADC12_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) == 0U) + +#if defined(ADC345_COMMON) +#define __HAL_RCC_ADC345_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN) == 0U) +#endif /* ADC345_COMMON */ + +#define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) == 0U) + +#if defined(DAC2) +#define __HAL_RCC_DAC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN) == 0U) +#endif /* DAC2 */ + +#define __HAL_RCC_DAC3_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN) == 0U) + +#if defined(DAC4) +#define __HAL_RCC_DAC4_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN) == 0U) +#endif /* DAC4 */ + +#if defined(AES) +#define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U) +#endif /* AES */ + +#define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U) + +/** + * @} + */ + +/** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the AHB3 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#if defined(FMC_BANK1) +#define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != 0U) +#endif /* FMC_BANK1 */ + +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != 0U) +#endif /* QUADSPI */ + +#if defined(FMC_BANK1) +#define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) +#endif /* FMC_BANK1 */ + +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == 0U) +#endif /* QUADSPI */ + +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the APB1 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U) + +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U) + +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U) + +#if defined(TIM5) +#define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U) +#endif /* TIM5 */ + +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U) + +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U) + +#define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U) + +#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != 0U) + +#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U) + +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U) + +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != 0U) + +#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U) + +#define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U) + +#if defined(UART4) +#define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U) +#endif /* UART4 */ + +#if defined(UART5) +#define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U) +#endif /* UART5 */ + +#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U) + +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U) + +#define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN) != 0U) + +#if defined(FDCAN1) +#define __HAL_RCC_FDCAN_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN) != 0U) +#endif /* FDCAN1 */ + +#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != 0U) + +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != 0U) + +#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != 0U) + +#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != 0U) + +#if defined(I2C4) +#define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U) +#endif /* I2C4 */ + +#define __HAL_RCC_UCPD1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) != 0U) + +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U) + +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U) + +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U) + +#if defined(TIM5) +#define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U) +#endif /* TIM5 */ + +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U) + +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U) + +#define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U) + +#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == 0U) + +#define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == 0U) + +#define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U) + +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == 0U) + +#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U) + +#define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U) + +#if defined(UART4) +#define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U) +#endif /* UART4 */ + +#if defined(UART5) +#define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == 0U) +#endif /* UART5 */ + +#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U) + +#define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U) + +#if defined(USB) +#define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN) == 0U) +#endif /* USB */ + +#if defined(FDCAN1) +#define __HAL_RCC_FDCAN_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN) == 0U) +#endif /* FDCAN1 */ + +#define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == 0U) + +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == 0U) + +#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == 0U) + +#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == 0U) + +#if defined(I2C4) +#define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U) +#endif /* I2C4 */ + +#define __HAL_RCC_UCPD1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) == 0U) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the APB2 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U) + +#define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U) + +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U) + +#define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U) + +#define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U) + +#if defined(SPI4) +#define __HAL_RCC_SPI4_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) != 0U) +#endif /* SPI4 */ + +#define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U) + +#define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U) + +#define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U) + +#if defined(TIM20) +#define __HAL_RCC_TIM20_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN) != 0U) +#endif /* TIM20 */ + +#define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U) + +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN) != 0U) +#endif /* HRTIM1 */ + + +#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U) + +#define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U) + +#define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U) + +#define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U) + +#define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U) + +#if defined(SPI4) +#define __HAL_RCC_SPI4_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) == 0U) +#endif /* SPI4 */ + +#define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U) + +#define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U) + +#define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U) + +#if defined(TIM20) +#define __HAL_RCC_TIM20_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN) == 0U) +#endif /* TIM20 */ + +#define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U) + +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN) == 0U) +#endif /* HRTIM1 */ + +/** + * @} + */ + +/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU) + +#define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST) + +#define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) + +#define __HAL_RCC_DMAMUX1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST) + +#define __HAL_RCC_CORDIC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) + +#define __HAL_RCC_FMAC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST) + +#define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) + +#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) + + +#define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U) + +#define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST) + +#define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) + +#define __HAL_RCC_DMAMUX1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST) + +#define __HAL_RCC_CORDIC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) + +#define __HAL_RCC_FMAC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST) + +#define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) + +#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) + +/** + * @} + */ + +/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU) + +#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) + +#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) + +#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) + +#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) + +#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) + +#define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) + +#define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) + +#define __HAL_RCC_ADC12_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC12RST) + +#if defined(ADC345_COMMON) +#define __HAL_RCC_ADC345_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC345RST) +#endif /* ADC345_COMMON */ + +#define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST) + +#if defined(DAC2) +#define __HAL_RCC_DAC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC2RST) +#endif /* DAC2 */ + +#define __HAL_RCC_DAC3_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC3RST) + +#if defined(DAC4) +#define __HAL_RCC_DAC4_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC4RST) +#endif /* DAC4 */ + +#if defined(AES) +#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) +#endif /* AES */ + +#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) + + +#define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U) + +#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) + +#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) + +#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) + +#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) + +#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) + +#define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) + +#define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) + +#define __HAL_RCC_ADC12_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC12RST) + +#if defined(ADC345_COMMON) +#define __HAL_RCC_ADC345_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC345RST) +#endif /* ADC345_COMMON */ + +#define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST) + +#if defined(DAC2) +#define __HAL_RCC_DAC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC2RST) +#endif /* DAC2 */ + +#define __HAL_RCC_DAC3_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC3RST) + +#if defined(DAC4) +#define __HAL_RCC_DAC4_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC4RST) +#endif /* DAC4 */ + +#if defined(AES) +#define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) +#endif /* AES */ + +#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) + +/** + * @} + */ + +/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset + * @brief Force or release AHB3 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU) + +#if defined(FMC_BANK1) +#define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST) +#endif /* FMC_BANK1 */ + +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST) +#endif /* QUADSPI */ + +#define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U) + +#if defined(FMC_BANK1) +#define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST) +#endif /* FMC_BANK1 */ + +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST) +#endif /* QUADSPI */ + +/** + * @} + */ + +/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU) + +#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) + +#define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) + +#define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) + +#if defined(TIM5) +#define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) +#endif /* TIM5 */ + +#define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) + +#define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) + +#define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) + +#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) + +#define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) + +#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) + +#define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) + +#if defined(UART4) +#define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) +#endif /* UART4 */ + +#if defined(UART5) +#define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) +#endif /* UART5 */ + +#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) + +#define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) + +#define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBRST) + +#if defined(FDCAN1) +#define __HAL_RCC_FDCAN_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_FDCANRST) +#endif /* FDCAN1 */ + +#define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) + +#define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) + +#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) + +#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST) + +#if defined(I2C4) +#define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) +#endif /* I2C4 */ + +#define __HAL_RCC_UCPD1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST) + +#define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000U) + +#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) + +#define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) + +#define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) + +#if defined(TIM5) +#define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) +#endif /* TIM5 */ + +#define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) + +#define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) + +#define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) + +#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) + +#define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) + +#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) + +#define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) + +#if defined(UART4) +#define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) +#endif /* UART4 */ + +#if defined(UART5) +#define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) +#endif /* UART5 */ + +#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) + +#define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) + +#define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBRST) + +#if defined(FDCAN1) +#define __HAL_RCC_FDCAN_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_FDCANRST) +#endif /* FDCAN1 */ + +#define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) + +#define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) + +#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) + +#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST) + +#if defined(I2C4) +#define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) +#endif /* I2C4 */ + +#define __HAL_RCC_UCPD1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU) + +#define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) + +#define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) + +#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) + +#define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) + +#define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) + +#if defined(SPI4) +#define __HAL_RCC_SPI4_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST) +#endif /* SPI4 */ + +#define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) + +#define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) + +#define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) + +#if defined(TIM20) +#define __HAL_RCC_TIM20_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM20RST) +#endif /* TIM20 */ + +#define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) + +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_HRTIM1RST) +#endif /* HRTIM1 */ + + +#define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U) + +#define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) + +#define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) + +#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) + +#define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) + +#define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) + +#if defined(SPI4) +#define __HAL_RCC_SPI4_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST) +#endif /* SPI4 */ + +#define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) + +#define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) + +#define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) + +#if defined(TIM20) +#define __HAL_RCC_TIM20_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM20RST) +#endif /* TIM20 */ + +#define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) + +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_HRTIM1RST) +#endif /* HRTIM1 */ + +/** + * @} + */ + +/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) + +#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) + +#define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) + +#define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) + +#define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) + +#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) + +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) + +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) + + +#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) + +#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) + +#define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) + +#define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) + +#define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) + +#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) + +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) + +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) + +/** + * @} + */ + +/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) + +#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) + +#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) + +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) + +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) + +#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) + +#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) + +#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) + +#define __HAL_RCC_CCM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) + +#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) + +#if defined(ADC345_COMMON) +#define __HAL_RCC_ADC345_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN) +#endif /* ADC345_COMMON */ + +#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) + +#if defined(DAC2) +#define __HAL_RCC_DAC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN) +#endif /* DAC2 */ + +#define __HAL_RCC_DAC3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) + +#if defined(DAC4) +#define __HAL_RCC_DAC4_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN) +#endif /* DAC4 */ + +#if defined(AES) +#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) +#endif /* AES */ + +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) + + +#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) + +#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) + +#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) + +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) + +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) + +#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) + +#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) + +#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) + +#define __HAL_RCC_CCM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) + +#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) + +#if defined(ADC345_COMMON) +#define __HAL_RCC_ADC345_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN) +#endif /* ADC345_COMMON */ + +#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) + +#if defined(DAC2) +#define __HAL_RCC_DAC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN) +#endif /* DAC2 */ + +#define __HAL_RCC_DAC3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) + +#if defined(DAC4) +#define __HAL_RCC_DAC4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN) +#endif /* DAC4 */ + +#if defined(AES) +#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) +#endif /* AES */ + +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) + +/** + * @} + */ + +/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#if defined(FMC_BANK1) +#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) +#endif /* FMC_BANK1 */ + +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) +#endif /* QUADSPI */ + +#if defined(FMC_BANK1) +#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) +#endif /* FMC_BANK1 */ + +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) +#endif /* QUADSPI */ + +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) + +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) + +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) + +#if defined(TIM5) +#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) +#endif /* TIM5 */ + +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) + +#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) + +#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) + +#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) + +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) + +#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) + +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) + +#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) + +#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) + +#if defined(UART4) +#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) +#endif /* UART4 */ + +#if defined(UART5) +#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) +#endif /* UART5 */ + +#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) + +#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) + +#if defined(USB) +#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) +#endif /* USB */ + +#if defined(FDCAN1) +#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) +#endif /* FDCAN1 */ + +#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) + +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) + +#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) + +#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) + +#if defined(I2C4) +#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) +#endif /* I2C4 */ + +#define __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) + + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) + +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) + +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) + +#if defined(TIM5) +#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) +#endif /* TIM5 */ + +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) + +#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) + +#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) + +#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) + +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) + +#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) + +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) + +#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) + +#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) + +#if defined(UART4) +#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) +#endif /* UART4 */ + +#if defined(UART5) +#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) +#endif /* UART5 */ + +#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) + +#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) + +#if defined(USB) +#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) +#endif /* USB */ + +#if defined(FDCAN1) +#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) +#endif /* FDCAN1 */ + +#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) + +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) + +#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) + +#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) + +#if defined(I2C4) +#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) +#endif /* I2C4 */ + +#define __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) + +#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) + +#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) + +#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) + +#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) + +#if defined(SPI4) +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN) +#endif /* SPI4 */ + +#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) + +#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) + +#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) + +#if defined(TIM20) +#define __HAL_RCC_TIM20_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN) +#endif /* TIM20 */ + +#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) + +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN) +#endif /* HRTIM1 */ + + +#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) + +#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) + +#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) + +#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) + +#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) + +#if defined(SPI4) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN) +#endif /* SPI4 */ + +#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) + +#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) + +#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) + +#if defined(TIM20) +#define __HAL_RCC_TIM20_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN) +#endif /* TIM20 */ + +#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) + +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN) +#endif /* HRTIM1 */ + +/** + * @} + */ + +/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status + * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != 0U) + +#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != 0U) + +#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != 0U) + +#define __HAL_RCC_CORDIC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) != 0U) + +#define __HAL_RCC_FMAC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) != 0U) + +#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U) + +#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != 0U) + +#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U) + + +#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == 0U) + +#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == 0U) + +#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == 0U) + +#define __HAL_RCC_CORDIC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) == 0U) + +#define __HAL_RCC_FMAC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) == 0U) + +#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == 0U) + +#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == 0U) + +#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == 0U) + +/** + * @} + */ + +/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status + * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != 0U) + +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != 0U) + +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != 0U) + +#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != 0U) + +#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != 0U) + +#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != 0U) + +#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != 0U) + +#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U) + +#define __HAL_RCC_CCM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) != 0U) + +#define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) != 0U) + +#if defined(ADC345_COMMON) +#define __HAL_RCC_ADC345_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN) != 0U) +#endif /* ADC345_COMMON */ + +#define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) != 0U) + +#if defined(DAC2) +#define __HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN) != 0U) +#endif /* DAC2 */ + +#define __HAL_RCC_DAC3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) != 0U) + +#if defined(DAC4) +#define __HAL_RCC_DAC4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN) != 0U) +#endif /* DAC4 */ + +#if defined(AES) +#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != 0U) +#endif /* AES */ + +#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U) + + +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == 0U) + +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == 0U) + +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == 0U) + +#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == 0U) + +#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == 0U) + +#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == 0U) + +#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == 0U) + +#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == 0U) + +#define __HAL_RCC_CCM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) == 0U) + +#define __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) == 0U) + +#if defined(ADC345_COMMON) +#define __HAL_RCC_ADC345_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN) == 0U) +#endif /* ADC345_COMMON */ + +#define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) == 0U) + +#if defined(DAC2) +#define __HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN) == 0U) +#endif /* DAC2 */ + +#define __HAL_RCC_DAC3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) == 0U) + +#if defined(DAC4) +#define __HAL_RCC_DAC4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN) == 0U) +#endif /* DAC4 */ + +#if defined(AES) +#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == 0U) +#endif /* AES */ + +#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == 0U) + +/** + * @} + */ + +/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status + * @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#if defined(FMC_BANK1) +#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != 0U) +#endif /* FMC_BANK1 */ + +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != 0U) +#endif /* QUADSPI */ + +#if defined(FMC_BANK1) +#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == 0U) +#endif /* FMC_BANK1 */ + +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == 0U) +#endif /* QUADSPI */ + +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status + * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != 0U) + +#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U) + +#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != 0U) + +#if defined(TIM5) +#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != 0U) +#endif /* TIM5 */ + +#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != 0U) + +#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != 0U) + +#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != 0U) + +#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != 0U) + +#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U) + +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != 0U) + +#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != 0U) + +#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U) + +#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != 0U) + +#if defined(UART4) +#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != 0U) +#endif /* UART4 */ + +#if defined(UART5) +#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != 0U) +#endif /* UART5 */ + +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U) + +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != 0U) + +#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) != 0U) + +#if defined(FDCAN1) +#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) != 0U) +#endif /* FDCAN1 */ + +#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != 0U) + +#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != 0U) + +#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != 0U) + +#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != 0U) + +#if defined(I2C4) +#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != 0U) +#endif /* I2C4 */ + +#define __HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) != 0U) + + +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == 0U) + +#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == 0U) + +#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == 0U) + +#if defined(TIM5) +#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == 0U) +#endif /* TIM5 */ + +#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == 0U) + +#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == 0U) + +#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == 0U) + +#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == 0U) + +#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == 0U) + +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == 0U) + +#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == 0U) + +#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == 0U) + +#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == 0U) + +#if defined(UART4) +#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == 0U) +#endif /* UART4 */ + +#if defined(UART5) +#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == 0U) +#endif /* UART5 */ + +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == 0U) + +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == 0U) + +#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) == 0U) + +#if defined(FDCAN1) +#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) == 0U) +#endif /* FDCAN1 */ + +#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == 0U) + +#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == 0U) + +#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == 0U) + +#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == 0U) + +#if defined(I2C4) +#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == 0U) +#endif /* I2C4 */ + +#define __HAL_RCC_UCPD1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) == 0U) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status + * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U) + +#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != 0U) + +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U) + +#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != 0U) + +#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U) + +#if defined(SPI4) +#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN) != 0U) +#endif /* SPI4 */ + +#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != 0U) + +#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != 0U) + +#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != 0U) + +#if defined(TIM20) +#define __HAL_RCC_TIM20_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN) != 0U) +#endif /* TIM20 */ + +#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U) + +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN) != 0U) +#endif /* HRTIM1 */ + + +#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U) + +#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == 0U) + +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == 0U) + +#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == 0U) + +#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == 0U) + +#if defined(SPI4) +#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN) == 0U) +#endif /* SPI4 */ + +#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == 0U) + +#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == 0U) + +#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == 0U) + +#if defined(TIM20) +#define __HAL_RCC_TIM20_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN) == 0U) +#endif /* TIM20 */ + +#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == 0U) + +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN) == 0U) +#endif /* HRTIM1 */ + + +/** + * @} + */ + +/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset + * @{ + */ + +/** @brief Macros to force or release the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_CSR register. + * @note The BKPSRAM is not affected by this reset. + * @retval None + */ +#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) + +#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) + +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration + * @{ + */ + +/** @brief Macros to enable or disable the RTC clock. + * @note As the RTC is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the RTC + * (to be done once after reset). + * @note These macros must be used after the RTC clock source was selected. + * @retval None + */ +#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) + +#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) + +/** + * @} + */ + +/** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after startup + * from Reset, wakeup from STOP and STANDBY mode, or in case of failure + * of the HSE used directly or indirectly as system clock (if the Clock + * Security System CSS is enabled). + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * This parameter can be: ENABLE or DISABLE. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + * @retval None + */ +#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) + +#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) + +/** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value + * (default is RCC_HSICALIBRATION_DEFAULT). + * This parameter must be a number between 0 and 0x7F. + * @retval None + */ +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos) + +/** + * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) + * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. + * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication + * speed because of the HSI startup time. + * @note The enable of this function has not effect on the HSION bit. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) + +#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) + +/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + * @note LSI can not be disabled if the IWDG is running. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + * @retval None + */ +#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) + +#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) + +/** + * @brief Macro to configure the External High Speed oscillator (HSE). + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application + * software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note This function reset the CSSON bit, so if the clock security system(CSS) + * was previously enabled you have to enable it again after calling this + * function. + * @param __STATE__ specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. + * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. + * @retval None + */ +#define __HAL_RCC_HSE_CONFIG(__STATE__) \ + do { \ + if((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + } while(0) + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE). + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this macro. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @param __STATE__ specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. + * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. + * @retval None + */ +#define __HAL_RCC_LSE_CONFIG(__STATE__) \ + do { \ + if((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + } while(0) + +/** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). + * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. + * @note After enabling the HSI48, the application software should wait on HSI48RDY + * flag to be set indicating that HSI48 clock is stable. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) + +#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) + +/** @brief Macros to configure the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using the Power Backup Access macro before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it cannot be changed unless the + * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by + * a Power On Reset (POR). + * + * @param __RTC_CLKSOURCE__ specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected + * + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the HSE clock is used as RTC clock source, the RTC + * cannot be used in STOP and STANDBY modes. + * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as + * RTC clock source). + * @retval None + */ +#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ + MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) + + +/** @brief Macro to get the RTC clock source. + * @retval The returned value can be one of the following: + * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected + */ +#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) + +/** @brief Macros to enable or disable the main PLL. + * @note After enabling the main PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The main PLL can not be disabled if it is used as system clock source + * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. + * @retval None + */ +#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) + +#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) + +/** @brief Macro to configure the PLL clock source. + * @note This function must be used only when the main PLL is disabled. + * @param __PLLSOURCE__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry + * @retval None + * + */ +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) + +/** @brief Macro to configure the PLL source division factor M. + * @note This function must be used only when the main PLL is disabled. + * @param __PLLM__ specifies the division factor for PLL VCO input clock + * This parameter must be a value of @ref RCC_PLLM_Clock_Divider. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 2.66 to 8 MHz. It is recommended to select a frequency + * of 8 MHz to limit PLL jitter. + * @retval None + * + */ +#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << RCC_PLLCFGR_PLLM_Pos) + +/** + * @brief Macro to configure the main PLL clock source, multiplication and division factors. + * @note This macro must be used only when the main PLL is disabled. + * @note This macro preserves the PLL's output clocks enable state. + * + * @param __PLLSOURCE__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry + * + * @param __PLLM__ specifies the division factor for PLL VCO input clock. + * This parameter must be a value of @ref RCC_PLLM_Clock_Divider + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 2.66 to 8 MHz. It is recommended to select a frequency + * of 8 MHz to limit PLL jitter. + * + * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock. + * This parameter must be a number between 8 and 127. + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 64 and 344 MHz. + * + * @param __PLLP__ specifies the division factor for SAI clock. + * This parameter must be a number in the range (2 to 31). + * + * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC1 and RNG clocks. + * This parameter must be in the range (2, 4, 6 or 8). + * @note If the USB OTG FS is used in your application, you have to set the + * PLLQ parameter correctly to have 48 MHz clock for the USB. However, + * the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work + * correctly. + * @param __PLLR__ specifies the division factor for the main system clock. + * @note You have to set the PLLR parameter correctly to not exceed 170MHZ. + * This parameter must be in the range (2, 4, 6 or 8). + * @retval None + */ +#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ + MODIFY_REG(RCC->PLLCFGR, \ + (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \ + RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLPDIV), \ + ((__PLLSOURCE__) | \ + (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \ + ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ + ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \ + ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \ + ((__PLLP__) << RCC_PLLCFGR_PLLPDIV_Pos))) + +/** @brief Macro to get the oscillator used as PLL clock source. + * @retval The oscillator used as PLL clock source. The returned value can be one + * of the following: + * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. + * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. + * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. + */ +#define __HAL_RCC_GET_PLL_OSCSOURCE() (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)) + +/** + * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_ADCCLK) + * @note Enabling/disabling clock outputs RCC_PLL_ADCCLK and RCC_PLL_48M1CLK can be done at anytime + * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot + * be stopped if used as System Clock. + * @param __PLLCLOCKOUT__ specifies the PLL clock to be output. + * This parameter can be one or a combination of the following values: + * @arg @ref RCC_PLL_ADCCLK This clock is used to generate a clock on ADC. + * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB (48 MHz), + * FDCAN (<=48 MHz) and QSPI (<=48 MHz). + * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 170MHz) + * @retval None + */ +#define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) + +#define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) + +/** + * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) + * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked. + * This parameter can be one of the following values: + * @arg @ref RCC_PLL_ADCCLK This clock is used to generate a clock on ADC. + * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB (48 MHz), + * FDCAN (<=48 MHz) and QSPI (<=48 MHz). + * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 170MHz) + * @retval SET / RESET + */ +#define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) + +/** + * @brief Macro to configure the system clock source. + * @param __SYSCLKSOURCE__ specifies the system clock source. + * This parameter can be one of the following values: + * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. + * @retval None + */ +#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) + +/** @brief Macro to get the clock source used as system clock. + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. + * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. + * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS)) + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. + * This parameter can be one of the following values: + * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. + * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. + * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. + * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. + * @retval None + */ +#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__)) + +/** @brief Macro to configure the MCO clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled + * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 + * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 + * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 + * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 + * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 + */ +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) + +/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management + * @brief macros to manage the specified RCC Flags and interrupts. + * @{ + */ + +/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable + * the selected interrupts). + * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt + * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 + * @retval None + */ +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) + +/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable + * the selected interrupts). + * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt + * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 + * @retval None + */ +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) + +/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] + * bits to clear the selected interrupt pending bits. + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt + * @arg @ref RCC_IT_CSS HSE Clock security system interrupt + * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 + * @retval None + */ +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__)) + +/** @brief Check whether the RCC interrupt has occurred or not. + * @param __INTERRUPT__ specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt + * @arg @ref RCC_IT_CSS HSE Clock security system interrupt + * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Set RMVF bit to clear the reset flags. + * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, + * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. + * @retval None + */ +#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) + +/** @brief Check whether the selected RCC flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready + * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready + * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready + * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 + * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready + * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection + * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready + * @arg @ref RCC_FLAG_BORRST BOR reset + * @arg @ref RCC_FLAG_OBLRST OBLRST reset + * @arg @ref RCC_FLAG_PINRST Pin reset + * @arg @ref RCC_FLAG_SFTRST Software reset + * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset + * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset + * @arg @ref RCC_FLAG_LPWRRST Low Power reset + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ + ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \ + ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ + ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ + ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) \ + ? 1U : 0U) + +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup RCC_Private_Constants + * @{ + */ +/* Defines used for Flags */ +#define CR_REG_INDEX 1U +#define BDCR_REG_INDEX 2U +#define CSR_REG_INDEX 3U +#define CRRCR_REG_INDEX 4U + +#define RCC_FLAG_MASK 0x1FU + +/* Define used for IS_RCC_CLOCKTYPE() */ +#define RCC_CLOCKTYPE_ALL (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2) /*!< All clcoktype to configure */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCC_Private_Macros + * @{ + */ + +#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) + +#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ + ((__HSE__) == RCC_HSE_BYPASS)) + +#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ + ((__LSE__) == RCC_LSE_BYPASS)) + +#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) + +#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos)) + +#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) + +#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) + +#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \ + ((__PLL__) == RCC_PLL_ON)) + +#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \ + ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ + ((__SOURCE__) == RCC_PLLSOURCE_HSE)) + +#define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) + +#define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 127U)) + +#define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) + +#define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ + ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) + +#define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ + ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) + +#define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_ALL) != 0x00UL) && (((__CLK__) & ~RCC_CLOCKTYPE_ALL) == 0x00UL)) + +#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) + +#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ + ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ + ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ + ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ + ((__HCLK__) == RCC_SYSCLK_DIV512)) + +#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ + ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ + ((__PCLK__) == RCC_HCLK_DIV16)) + +#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) + +#define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO_PA8) || \ + ((__MCOX__) == RCC_MCO_PG10)) + +#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSI48)) + +#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ + ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ + ((__DIV__) == RCC_MCODIV_16)) + +#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ + ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ + ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ + ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) + +/** + * @} + */ + +/* Include RCC HAL Extended module */ +#include "stm32g4xx_hal_rcc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_Exported_Functions + * @{ + */ + + +/** @addtogroup RCC_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group2 + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); +void HAL_RCC_EnableCSS(void); +void HAL_RCC_EnableLSECSS(void); +void HAL_RCC_DisableLSECSS(void); +uint32_t HAL_RCC_GetSysClockFreq(void); +uint32_t HAL_RCC_GetHCLKFreq(void); +uint32_t HAL_RCC_GetPCLK1Freq(void); +uint32_t HAL_RCC_GetPCLK2Freq(void); +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); +/* CSS NMI IRQ handler */ +void HAL_RCC_NMI_IRQHandler(void); +/* User Callbacks in non blocking mode (IT mode) */ +void HAL_RCC_CSSCallback(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G4xx_HAL_RCC_H */ + diff --git a/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h new file mode 100644 index 000000000..6cebf2779 --- /dev/null +++ b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h @@ -0,0 +1,1606 @@ +/** + ****************************************************************************** + * @file stm32g4xx_hal_rcc_ex.h + * @author MCD Application Team + * @brief Header file of RCC HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G4xx_HAL_RCC_EX_H +#define STM32G4xx_HAL_RCC_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_hal_def.h" + +/** @addtogroup STM32G4xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Types RCCEx Exported Types + * @{ + */ + +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. + This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ + + uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. + This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ + + uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source. + This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ + +#if defined(UART4) + uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source. + This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ +#endif /* UART4 */ + +#if defined(UART5) + uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source. + This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ + +#endif /* UART5 */ + + uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. + This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. + This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ + + uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source. + This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ + + uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. + This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ + +#if defined(I2C4) + + uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source. + This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ +#endif /* I2C4 */ + + uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. + This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ + + uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. + This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ + + uint32_t I2sClockSelection; /*!< Specifies I2S clock source. + This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ +#if defined(FDCAN1) + + uint32_t FdcanClockSelection; /*!< Specifies FDCAN clock source. + This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source */ +#endif /* FDCAN1 */ +#if defined(USB) + + uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for RNG). + This parameter can be a value of @ref RCCEx_USB_Clock_Source */ +#endif /* USB */ + + uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB). + This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ + + uint32_t Adc12ClockSelection; /*!< Specifies ADC12 interface clock source. + This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ + +#if defined(ADC345_COMMON) + uint32_t Adc345ClockSelection; /*!< Specifies ADC345 interface clock source. + This parameter can be a value of @ref RCCEx_ADC345_Clock_Source */ +#endif /* ADC345_COMMON */ + +#if defined(QUADSPI) + uint32_t QspiClockSelection; /*!< Specifies QuadSPI clock source. + This parameter can be a value of @ref RCCEx_QSPI_Clock_Source */ +#endif + + uint32_t RTCClockSelection; /*!< Specifies RTC clock source. + This parameter can be a value of @ref RCC_RTC_Clock_Source */ +}RCC_PeriphCLKInitTypeDef; + +/** + * @brief RCC_CRS Init structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. + This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ + + uint32_t Source; /*!< Specifies the SYNC signal source. + This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ + + uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. + This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ + + uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. + It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) + This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ + + uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. + This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ + + uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. + This parameter must be a number between 0 and 0x7F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ + +}RCC_CRSInitTypeDef; + +/** + * @brief RCC_CRS Synchronization structure definition + */ +typedef struct +{ + uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. + This parameter must be a number between 0 and 0xFFFF */ + + uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. + This parameter must be a number between 0 and 0x7F */ + + uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter + value latched in the time of the last SYNC event. + This parameter must be a number between 0 and 0xFFFF */ + + uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the + frequency error counter latched in the time of the last SYNC event. + It shows whether the actual frequency is below or above the target. + This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ + +}RCC_CRSSynchroInfoTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants + * @{ + */ + +/** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source + * @{ + */ +#define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */ +#define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */ +/** + * @} + */ + +/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection + * @{ + */ +#define RCC_PERIPHCLK_USART1 0x00000001U +#define RCC_PERIPHCLK_USART2 0x00000002U +#define RCC_PERIPHCLK_USART3 0x00000004U +#if defined(UART4) +#define RCC_PERIPHCLK_UART4 0x00000008U +#endif /* UART4 */ +#if defined(UART5) +#define RCC_PERIPHCLK_UART5 0x00000010U +#endif /* UART5 */ +#define RCC_PERIPHCLK_LPUART1 0x00000020U +#define RCC_PERIPHCLK_I2C1 0x00000040U +#define RCC_PERIPHCLK_I2C2 0x00000080U +#define RCC_PERIPHCLK_I2C3 0x00000100U +#define RCC_PERIPHCLK_LPTIM1 0x00000200U +#define RCC_PERIPHCLK_SAI1 0x00000400U +#define RCC_PERIPHCLK_I2S 0x00000800U +#if defined(FDCAN1) +#define RCC_PERIPHCLK_FDCAN 0x00001000U +#endif /* FDCAN1 */ +#define RCC_PERIPHCLK_USB 0x00002000U +#define RCC_PERIPHCLK_RNG 0x00004000U +#define RCC_PERIPHCLK_ADC12 0x00008000U +#if defined(ADC345_COMMON) +#define RCC_PERIPHCLK_ADC345 0x00010000U +#endif /* ADC345_COMMON */ +#if defined(I2C4) +#define RCC_PERIPHCLK_I2C4 0x00020000U +#endif /* I2C4 */ +#if defined(QUADSPI) +#define RCC_PERIPHCLK_QSPI 0x00040000U +#endif /* QUADSPI */ +#define RCC_PERIPHCLK_RTC 0x00080000U +/** + * @} + */ + + +/** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source + * @{ + */ +#define RCC_USART1CLKSOURCE_PCLK2 0x00000000U +#define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 +#define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 +#define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1) +/** + * @} + */ + +/** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source + * @{ + */ +#define RCC_USART2CLKSOURCE_PCLK1 0x00000000U +#define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0 +#define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1 +#define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1) +/** + * @} + */ + +/** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source + * @{ + */ +#define RCC_USART3CLKSOURCE_PCLK1 0x00000000U +#define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0 +#define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1 +#define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1) +/** + * @} + */ + +#if defined(UART4) +/** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source + * @{ + */ +#define RCC_UART4CLKSOURCE_PCLK1 0x00000000U +#define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0 +#define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1 +#define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1) +/** + * @} + */ +#endif /* UART4 */ + +#if defined(UART5) +/** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source + * @{ + */ +#define RCC_UART5CLKSOURCE_PCLK1 0x00000000U +#define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0 +#define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1 +#define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1) +/** + * @} + */ +#endif /* UART5 */ + +/** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source + * @{ + */ +#define RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U +#define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 +#define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 +#define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1) +/** + * @} + */ + +/** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source + * @{ + */ +#define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U +#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 +#define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1 +/** + * @} + */ + +/** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source + * @{ + */ +#define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U +#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0 +#define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1 +/** + * @} + */ + +/** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source + * @{ + */ +#define RCC_I2C3CLKSOURCE_PCLK1 0x00000000U +#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0 +#define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1 +/** + * @} + */ + +/** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source + * @{ + */ +#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U +#define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 +#define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 +#define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL +/** + * @} + */ + +/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source + * @{ + */ +#define RCC_SAI1CLKSOURCE_SYSCLK 0x00000000U +#define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_0 +#define RCC_SAI1CLKSOURCE_EXT RCC_CCIPR_SAI1SEL_1 +#define RCC_SAI1CLKSOURCE_HSI (RCC_CCIPR_SAI1SEL_1 | RCC_CCIPR_SAI1SEL_0) +/** + * @} + */ + +/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source + * @{ + */ +#define RCC_I2SCLKSOURCE_SYSCLK 0x00000000U +#define RCC_I2SCLKSOURCE_PLL RCC_CCIPR_I2S23SEL_0 +#define RCC_I2SCLKSOURCE_EXT RCC_CCIPR_I2S23SEL_1 +#define RCC_I2SCLKSOURCE_HSI (RCC_CCIPR_I2S23SEL_1 | RCC_CCIPR_I2S23SEL_0) +/** + * @} + */ +#if defined(FDCAN1) +/** @defgroup RCCEx_FDCAN_Clock_Source FDCAN Clock Source + * @{ + */ +#define RCC_FDCANCLKSOURCE_HSE 0x00000000U +#define RCC_FDCANCLKSOURCE_PLL RCC_CCIPR_FDCANSEL_0 +#define RCC_FDCANCLKSOURCE_PCLK1 RCC_CCIPR_FDCANSEL_1 +/** + * @} + */ +#endif /* FDCAN1 */ + +/** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source + * @{ + */ +#define RCC_RNGCLKSOURCE_HSI48 0x00000000U +#define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 +/** + * @} + */ + +/** @defgroup RCCEx_USB_Clock_Source USB Clock Source + * @{ + */ +#define RCC_USBCLKSOURCE_HSI48 0x00000000U +#define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 +/** + * @} + */ + +/** @defgroup RCCEx_ADC12_Clock_Source ADC12 Clock Source + * @{ + */ +#define RCC_ADC12CLKSOURCE_NONE 0x00000000U +#define RCC_ADC12CLKSOURCE_PLL RCC_CCIPR_ADC12SEL_0 +#define RCC_ADC12CLKSOURCE_SYSCLK RCC_CCIPR_ADC12SEL_1 +/** + * @} + */ + +#if defined(ADC345_COMMON) +/** @defgroup RCCEx_ADC345_Clock_Source ADC345 Clock Source + * @{ + */ +#define RCC_ADC345CLKSOURCE_NONE 0x00000000U +#define RCC_ADC345CLKSOURCE_PLL RCC_CCIPR_ADC345SEL_0 +#define RCC_ADC345CLKSOURCE_SYSCLK RCC_CCIPR_ADC345SEL_1 +/** + * @} + */ +#endif /* ADC345_COMMON */ + +#if defined(I2C4) +/** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source + * @{ + */ +#define RCC_I2C4CLKSOURCE_PCLK1 0x00000000U +#define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR2_I2C4SEL_0 +#define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR2_I2C4SEL_1 +/** + * @} + */ +#endif /* I2C4 */ + +#if defined(QUADSPI) +/** @defgroup RCCEx_QSPI_Clock_Source QuadSPI Clock Source + * @{ + */ +#define RCC_QSPICLKSOURCE_SYSCLK 0x00000000U +#define RCC_QSPICLKSOURCE_HSI RCC_CCIPR2_QSPISEL_0 +#define RCC_QSPICLKSOURCE_PLL RCC_CCIPR2_QSPISEL_1 +/** + * @} + */ +#endif /* QUADSPI */ + +/** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line + * @{ + */ +#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19 /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_Status RCCEx CRS Status + * @{ + */ +#define RCC_CRS_NONE 0x00000000U +#define RCC_CRS_TIMEOUT 0x00000001U +#define RCC_CRS_SYNCOK 0x00000002U +#define RCC_CRS_SYNCWARN 0x00000004U +#define RCC_CRS_SYNCERR 0x00000008U +#define RCC_CRS_SYNCMISS 0x00000010U +#define RCC_CRS_TRIMOVF 0x00000020U +/** + * @} + */ + +/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource + * @{ + */ +#define RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ +#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ +#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider + * @{ + */ +#define RCC_CRS_SYNC_DIV1 0x00000000U /*!< Synchro Signal not divided (default) */ +#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ +#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ +#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ +#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ +#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ +#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ +#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity + * @{ + */ +#define RCC_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */ +#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault + * @{ + */ +#define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds + to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault + * @{ + */ +#define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /*!< Default Frequency error limit */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault + * @{ + */ +#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U /*!< The default value is 64, which corresponds to the middle of the trimming interval. + The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value + corresponds to a higher output frequency */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection + * @{ + */ +#define RCC_CRS_FREQERRORDIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */ +#define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources + * @{ + */ +#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ +#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ +#define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ +#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ +#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ +#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ +#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ + +/** + * @} + */ + +/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags + * @{ + */ +#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ +#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ +#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ +#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ +#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ +#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ +#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros + * @{ + */ + +/** @brief Macro to configure the USART1 clock (USART1CLK). + * + * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock + * @retval None + */ +#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__)) + +/** @brief Macro to get the USART1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock + */ +#define __HAL_RCC_GET_USART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)) + +/** @brief Macro to configure the USART2 clock (USART2CLK). + * + * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock + * @retval None + */ +#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__)) + +/** @brief Macro to get the USART2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock + */ +#define __HAL_RCC_GET_USART2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)) + +/** @brief Macro to configure the USART3 clock (USART3CLK). + * + * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock + * @retval None + */ +#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__)) + +/** @brief Macro to get the USART3 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock + */ +#define __HAL_RCC_GET_USART3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)) + +#if defined(UART4) +/** @brief Macro to configure the UART4 clock (UART4CLK). + * + * @param __UART4_CLKSOURCE__ specifies the UART4 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock + * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock + * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock + * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock + * @retval None + */ +#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__)) + +/** @brief Macro to get the UART4 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock + * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock + * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock + * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock + */ +#define __HAL_RCC_GET_UART4_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL)) +#endif /* UART4 */ + +#if defined(UART5) + +/** @brief Macro to configure the UART5 clock (UART5CLK). + * + * @param __UART5_CLKSOURCE__ specifies the UART5 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock + * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock + * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock + * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock + * @retval None + */ +#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (__UART5_CLKSOURCE__)) + +/** @brief Macro to get the UART5 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock + * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock + * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock + * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock + */ +#define __HAL_RCC_GET_UART5_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL)) + +#endif /* UART5 */ + +/** @brief Macro to configure the LPUART1 clock (LPUART1CLK). + * + * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock + * @retval None + */ +#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__)) + +/** @brief Macro to get the LPUART1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock + */ +#define __HAL_RCC_GET_LPUART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)) + +/** @brief Macro to configure the I2C1 clock (I2C1CLK). + * + * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock + * @retval None + */ +#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__)) + +/** @brief Macro to get the I2C1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock + */ +#define __HAL_RCC_GET_I2C1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)) + + +/** @brief Macro to configure the I2C2 clock (I2C2CLK). + * + * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock + * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock + * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock + * @retval None + */ +#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__)) + +/** @brief Macro to get the I2C2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock + * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock + * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock + */ +#define __HAL_RCC_GET_I2C2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)) + +/** @brief Macro to configure the I2C3 clock (I2C3CLK). + * + * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock + * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock + * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock + * @retval None + */ +#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__)) + +/** @brief Macro to get the I2C3 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock + * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock + * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock + */ +#define __HAL_RCC_GET_I2C3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)) + +#if defined(I2C4) + +/** @brief Macro to configure the I2C4 clock (I2C4CLK). + * + * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock + * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock + * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock + * @retval None + */ +#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (__I2C4_CLKSOURCE__)) + +/** @brief Macro to get the I2C4 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock + * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock + * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock + */ +#define __HAL_RCC_GET_I2C4_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL)) + +#endif /* I2C4 */ + +/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). + * + * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock + * @retval None + */ +#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__)) + +/** @brief Macro to get the LPTIM1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock + */ +#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)) + +/** + * @brief Macro to configure the SAI1 clock source. + * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived + * from the HSI, system PLL, System Clock or external clock. + * This parameter can be one of the following values: + * @arg @ref RCC_SAI1CLKSOURCE_SYSCLK SAI1 clock = System Clock + * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "Q" clock + * @arg @ref RCC_SAI1CLKSOURCE_EXT SAI1 clock = EXT + * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI + * + * @retval None + */ +#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__)) + +/** @brief Macro to get the SAI1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_SAI1CLKSOURCE_SYSCLK SAI1 clock = System Clock + * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "Q" clock + * @arg @ref RCC_SAI1CLKSOURCE_EXT SAI1 clock = EXT + * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI + * + */ +#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)) + +/** + * @brief Macro to configure the I2S clock source. + * @param __I2S_CLKSOURCE__ defines the I2S clock source. This clock is derived + * from the HSI, system PLL, System Clock or external clock. + * This parameter can be one of the following values: + * @arg @ref RCC_I2SCLKSOURCE_SYSCLK I2S clock = System Clock + * @arg @ref RCC_I2SCLKSOURCE_PLL I2S clock = PLL "Q" clock + * @arg @ref RCC_I2SCLKSOURCE_EXT I2S clock = EXT + * @arg @ref RCC_I2SCLKSOURCE_HSI I2S clock = HSI + * + * @retval None + */ +#define __HAL_RCC_I2S_CONFIG(__I2S_CLKSOURCE__)\ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S23SEL, (__I2S_CLKSOURCE__)) + +/** @brief Macro to get the I2S clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2SCLKSOURCE_SYSCLK I2S clock = System Clock + * @arg @ref RCC_I2SCLKSOURCE_PLL I2S clock = PLL "Q" clock + * @arg @ref RCC_I2SCLKSOURCE_EXT I2S clock = EXT + * @arg @ref RCC_I2SCLKSOURCE_HSI I2S clock = HSI + * + */ +#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2S23SEL))) + +#if defined(FDCAN1) +/** + * @brief Macro to configure the FDCAN clock source. + * @param __FDCAN_CLKSOURCE__ defines the FDCAN clock source. This clock is derived + * from the HSE, system PLL or PCLK1. + * This parameter can be one of the following values: + * @arg @ref RCC_FDCANCLKSOURCE_HSE FDCAN clock = HSE + * @arg @ref RCC_FDCANCLKSOURCE_PLL FDCAN clock = PLL "Q" clock + * @arg @ref RCC_FDCANCLKSOURCE_PCLK1 FDCAN clock = PCLK1 + * + * @retval None + */ +#define __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__)\ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__)) + +/** @brief Macro to get the FDCAN clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_FDCANCLKSOURCE_HSE FDCAN clock = HSE + * @arg @ref RCC_FDCANCLKSOURCE_PLL FDCAN clock = PLL "Q" clock + * @arg @ref RCC_FDCANCLKSOURCE_PCLK1 FDCAN clock = PCLK1 + * + */ +#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_FDCANSEL))) +#endif /* FDCAN1 */ + +/** @brief Macro to configure the RNG clock. + * + * @note USB and RNG peripherals share the same 48MHz clock source. + * + * @param __RNG_CLKSOURCE__ specifies the RNG clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock for devices with HSI48 + * @arg @ref RCC_RNGCLKSOURCE_PLL PLL Clock selected as RNG clock + * @retval None + */ +#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__)) + +/** @brief Macro to get the RNG clock. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock for devices with HSI48 + * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock selected as RNG clock + */ +#define __HAL_RCC_GET_RNG_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) + +#if defined(USB) + +/** @brief Macro to configure the USB clock (USBCLK). + * + * @note USB, RNG peripherals share the same 48MHz clock source. + * + * @param __USB_CLKSOURCE__ specifies the USB clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 + * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock + * @retval None + */ +#define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__)) + +/** @brief Macro to get the USB clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 + * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock + */ +#define __HAL_RCC_GET_USB_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) + +#endif /* USB */ + +/** @brief Macro to configure the ADC12 interface clock. + * @param __ADC12_CLKSOURCE__ specifies the ADC12 digital interface clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_ADC12CLKSOURCE_NONE No clock selected as ADC12 clock + * @arg @ref RCC_ADC12CLKSOURCE_PLL PLL Clock selected as ADC12 clock + * @arg @ref RCC_ADC12CLKSOURCE_SYSCLK System Clock selected as ADC12 clock + * @retval None + */ +#define __HAL_RCC_ADC12_CONFIG(__ADC12_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADC12SEL, (__ADC12_CLKSOURCE__)) + +/** @brief Macro to get the ADC12 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_ADC12CLKSOURCE_NONE No clock selected as ADC12 clock + * @arg @ref RCC_ADC12CLKSOURCE_PLL PLL Clock selected as ADC12 clock + * @arg @ref RCC_ADC12CLKSOURCE_SYSCLK System Clock selected as ADC12 clock + */ +#define __HAL_RCC_GET_ADC12_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADC12SEL)) + +#if defined(ADC345_COMMON) +/** @brief Macro to configure the ADC345 interface clock. + * @param __ADC345_CLKSOURCE__ specifies the ADC345 digital interface clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_ADC345CLKSOURCE_NONE No clock selected as ADC345 clock + * @arg @ref RCC_ADC345CLKSOURCE_PLL PLL Clock selected as ADC345 clock + * @arg @ref RCC_ADC345CLKSOURCE_SYSCLK System Clock selected as ADC345 clock + * @retval None + */ +#define __HAL_RCC_ADC345_CONFIG(__ADC345_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADC345SEL, __ADC345_CLKSOURCE__) + +/** @brief Macro to get the ADC345 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_ADC345CLKSOURCE_NONE No clock selected as ADC345 clock + * @arg @ref RCC_ADC345CLKSOURCE_PLL PLL Clock selected as ADC345 clock + * @arg @ref RCC_ADC345CLKSOURCE_SYSCLK System Clock selected as ADC345 clock + */ +#define __HAL_RCC_GET_ADC345_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADC345SEL)) +#endif /* ADC345_COMMON */ + +#if defined(QUADSPI) + +/** @brief Macro to configure the QuadSPI clock. + * @param __QSPI_CLKSOURCE__ specifies the QuadSPI clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_QSPICLKSOURCE_SYSCLK System Clock selected as QuadSPI clock + * @arg @ref RCC_QSPICLKSOURCE_HSI HSI clock selected as QuadSPI clock + * @arg @ref RCC_QSPICLKSOURCE_PLL PLL Q divider clock selected as QuadSPI clock + * @retval None + */ +#define __HAL_RCC_QSPI_CONFIG(__QSPI_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_QSPISEL, __QSPI_CLKSOURCE__) + +/** @brief Macro to get the QuadSPI clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_QSPICLKSOURCE_SYSCLK System Clock selected as QuadSPI clock + * @arg @ref RCC_QSPICLKSOURCE_HSI HSI clock selected as QuadSPI clock + * @arg @ref RCC_QSPICLKSOURCE_PLL PLL Q divider clock selected as QuadSPI clock + */ +#define __HAL_RCC_GET_QSPI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_QSPISEL)) + +#endif /* QUADSPI */ + +/** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management + * @brief macros to manage the specified RCC Flags and interrupts. + * @{ + */ + +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Line. + * @retval None + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Line. + * @retval None + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Enable the RCC LSE CSS Event Line. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Event Line. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) + + +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) + + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) + + +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. + * @retval EXTI RCC LSE CSS Line Status. + */ +#define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) + +/** + * @brief Clear the RCC LSE CSS EXTI flag. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS) + + +/** + * @brief Enable the specified CRS interrupts. + * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval None + */ +#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) + +/** + * @brief Disable the specified CRS interrupts. + * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval None + */ +#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) + +/** @brief Check whether the CRS interrupt has occurred or not. + * @param __INTERRUPT__ specifies the CRS interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET) + +/** @brief Clear the CRS interrupt pending bits + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt + * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt + * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt + */ +/* CRS IT Error Mask */ +#define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS) + +#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ + if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ + { \ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ + } \ + else \ + { \ + WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ + } \ + } while(0) + +/** + * @brief Check whether the specified CRS flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK + * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning + * @arg @ref RCC_CRS_FLAG_ERR Error + * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC + * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow + * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error + * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed + * @retval The new state of _FLAG_ (TRUE or FALSE). + */ +#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the CRS specified FLAG. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK + * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning + * @arg @ref RCC_CRS_FLAG_ERR Error + * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC + * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow + * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error + * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed + * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR + * @retval None + */ + +/* CRS Flag Error Mask */ +#define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS) + +#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ + if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ + { \ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ + } \ + else \ + { \ + WRITE_REG(CRS->ICR, (__FLAG__)); \ + } \ + } while(0) + + +/** + * @} + */ + +/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features + * @{ + */ +/** + * @brief Enable the oscillator clock for frequency error counter. + * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. + * @retval None + */ +#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) + +/** + * @brief Disable the oscillator clock for frequency error counter. + * @retval None + */ +#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) + +/** + * @brief Enable the automatic hardware adjustment of TRIM bits. + * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. + * @retval None + */ +#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) + +/** + * @brief Enable or disable the automatic hardware adjustment of TRIM bits. + * @retval None + */ +#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) + +/** + * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies + * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency + * of the synchronization source after prescaling. It is then decreased by one in order to + * reach the expected synchronization on the zero value. The formula is the following: + * RELOAD = (fTARGET / fSYNC) -1 + * @param __FTARGET__ Target frequency (value in Hz) + * @param __FSYNC__ Synchronization signal frequency (value in Hz) + * @retval None + */ +#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCCEx_Exported_Functions + * @{ + */ + +/** @addtogroup RCCEx_Exported_Functions_Group1 + * @{ + */ + +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); + +/** + * @} + */ + +/** @addtogroup RCCEx_Exported_Functions_Group2 + * @{ + */ + +void HAL_RCCEx_EnableLSECSS(void); +void HAL_RCCEx_DisableLSECSS(void); +void HAL_RCCEx_EnableLSECSS_IT(void); +void HAL_RCCEx_LSECSS_IRQHandler(void); +void HAL_RCCEx_LSECSS_Callback(void); +void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); +void HAL_RCCEx_DisableLSCO(void); + +/** + * @} + */ + +/** @addtogroup RCCEx_Exported_Functions_Group3 + * @{ + */ + +void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); +void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); +void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); +uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); +void HAL_RCCEx_CRS_IRQHandler(void); +void HAL_RCCEx_CRS_SyncOkCallback(void); +void HAL_RCCEx_CRS_SyncWarnCallback(void); +void HAL_RCCEx_CRS_ExpectedSyncCallback(void); +void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCCEx_Private_Macros + * @{ + */ + +#define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) + +#if defined(STM32G474xx) || defined(STM32G484xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \ + (((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#elif defined(STM32G491xx) || defined(STM32G4A1xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \ + (((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#elif defined(STM32G473xx) || defined(STM32G483xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \ + (((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) + +#elif defined(STM32G471xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) + +#elif defined(STM32G431xx) || defined(STM32G441xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) + +#elif defined(STM32GBK1CB) +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) + +#endif /* STM32G474xx || STM32G484xx */ + +#define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) + +#define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) + +#define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI)) + +#if defined(UART4) +#define IS_RCC_UART4CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI)) +#endif /* UART4 */ + +#if defined(UART5) +#define IS_RCC_UART5CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI)) + +#endif /* UART5 */ + +#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) + +#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) + +#define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \ + ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)) + +#define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ + ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) + +#if defined(I2C4) + +#define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \ + ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI)) + +#endif /* I2C4 */ + +#define IS_RCC_LPTIM1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) + +#define IS_RCC_SAI1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI1CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_EXT) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI)) + +#define IS_RCC_I2SCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2SCLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_I2SCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_I2SCLKSOURCE_EXT) || \ + ((__SOURCE__) == RCC_I2SCLKSOURCE_HSI)) + +#if defined(FDCAN1) +#define IS_RCC_FDCANCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_FDCANCLKSOURCE_PCLK1)) + +#endif /* FDCAN1 */ +#define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL)) + +#if defined(USB) +#define IS_RCC_USBCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ + ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)) + +#endif /* USB */ + +#define IS_RCC_ADC12CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_ADC12CLKSOURCE_NONE) || \ + ((__SOURCE__) == RCC_ADC12CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_ADC12CLKSOURCE_SYSCLK)) + +#if defined(ADC345_COMMON) +#define IS_RCC_ADC345CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_ADC345CLKSOURCE_NONE) || \ + ((__SOURCE__) == RCC_ADC345CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_ADC345CLKSOURCE_SYSCLK)) +#endif /* ADC345_COMMON */ + +#if defined(QUADSPI) + +#define IS_RCC_QSPICLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_QSPICLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_QSPICLKSOURCE_SYSCLK)|| \ + ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL)) + +#endif /* QUADSPI */ + +#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ + ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ + ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) + +#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ + ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ + ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ + ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) + +#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ + ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) + +#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) + +#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) + +#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU)) + +#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ + ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G4xx_HAL_RCC_EX_H */ + diff --git a/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c new file mode 100644 index 000000000..ebe1bdf5e --- /dev/null +++ b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c @@ -0,0 +1,800 @@ +/** + ****************************************************************************** + * @file stm32g4xx_hal.c + * @author MCD Application Team + * @brief HAL module driver. + * This is the common part of the HAL initialization + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The common HAL driver contains a set of generic and common APIs that can be + used by the PPP peripheral drivers and the user to start using the HAL. + [..] + The HAL contains two APIs' categories: + (+) Common HAL APIs + (+) Services HAL APIs + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_hal.h" + +/** @addtogroup STM32G4xx_HAL_Driver + * @{ + */ + +/** @defgroup HAL HAL + * @brief HAL module driver + * @{ + */ + +#ifdef HAL_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** + * @brief STM32G4xx HAL Driver version number V1.2.3 + */ +#define __STM32G4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define __STM32G4xx_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ +#define __STM32G4xx_HAL_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */ +#define __STM32G4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32G4xx_HAL_VERSION ((__STM32G4xx_HAL_VERSION_MAIN << 24U)\ + |(__STM32G4xx_HAL_VERSION_SUB1 << 16U)\ + |(__STM32G4xx_HAL_VERSION_SUB2 << 8U )\ + |(__STM32G4xx_HAL_VERSION_RC)) + +#if defined(VREFBUF) +#define VREFBUF_TIMEOUT_VALUE 10U /* 10 ms */ +#endif /* VREFBUF */ + +/* ------------ SYSCFG registers bit address in the alias region ------------ */ +#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) +/* --- MEMRMP Register ---*/ +/* Alias word address of FB_MODE bit */ +#define MEMRMP_OFFSET SYSCFG_OFFSET +#define FB_MODE_BitNumber ((uint8_t)0x8) +#define FB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (FB_MODE_BitNumber * 4)) + +/* --- GPC Register ---*/ +/* Alias word address of CCMER bit */ +#define SCSR_OFFSET (SYSCFG_OFFSET + 0x18) +#define CCMER_BitNumber ((uint8_t)0x0) +#define SCSR_CCMER_BB (PERIPH_BB_BASE + (SCSR_OFFSET * 32) + (CCMER_BitNumber * 4)) + +/* Private macro -------------------------------------------------------------*/ +/* Exported variables ---------------------------------------------------------*/ +/** @defgroup HAL_Exported_Variables HAL Exported Variables + * @{ + */ +__IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +uint32_t uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ + +/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions + * @brief HAL Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the Flash interface the NVIC allocation and initial time base + clock configuration. + (+) De-Initialize common part of the HAL. + (+) Configure the time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) SysTick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + handled in milliseconds basis. + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __weak + to make override possible in case of other implementations in user file. +@endverbatim + * @{ + */ + +/** + * @brief This function is used to configure the Flash prefetch, the Instruction and Data caches, + * the time base source, NVIC and any required global low level hardware + * by calling the HAL_MspInit() callback function to be optionally defined in user file + * stm32g4xx_hal_msp.c. + * + * @note HAL_Init() function is called at the beginning of program after reset and before + * the clock configuration. + * + * @note In the default implementation the System Timer (Systick) is used as source of time base. + * The Systick configuration is based on HSI clock, as HSI is the clock + * used after a system Reset and the NVIC configuration is set to Priority group 4. + * Once done, time base tick starts incrementing: the tick variable counter is incremented + * each 1ms in the SysTick_Handler() interrupt handler. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + HAL_StatusTypeDef status = HAL_OK; + /* Configure Flash prefetch, Instruction cache, Data cache */ + /* Default configuration at reset is: */ + /* - Prefetch disabled */ + /* - Instruction cache enabled */ + /* - Data cache enabled */ +#if (INSTRUCTION_CACHE_ENABLE == 0U) + __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); +#endif /* INSTRUCTION_CACHE_ENABLE */ + +#if (DATA_CACHE_ENABLE == 0U) + __HAL_FLASH_DATA_CACHE_DISABLE(); +#endif /* DATA_CACHE_ENABLE */ + +#if (PREFETCH_ENABLE != 0U) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + + /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + { + status = HAL_ERROR; + } + else + { + /* Init the low level hardware */ + HAL_MspInit(); + } + + /* Return function status */ + return status; + +} + +/** + * @brief This function de-initializes common part of the HAL and stops the source of time base. + * @note This function is optional. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DeInit(void) +{ + /* Reset of all peripherals */ + __HAL_RCC_APB1_FORCE_RESET(); + __HAL_RCC_APB1_RELEASE_RESET(); + + __HAL_RCC_APB2_FORCE_RESET(); + __HAL_RCC_APB2_RELEASE_RESET(); + + __HAL_RCC_AHB1_FORCE_RESET(); + __HAL_RCC_AHB1_RELEASE_RESET(); + + __HAL_RCC_AHB2_FORCE_RESET(); + __HAL_RCC_AHB2_RELEASE_RESET(); + + __HAL_RCC_AHB3_FORCE_RESET(); + __HAL_RCC_AHB3_RELEASE_RESET(); + + /* De-Init the low level hardware */ + HAL_MspDeInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initialize the MSP. + * @retval None + */ +__weak void HAL_MspInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the MSP. + * @retval None + */ +__weak void HAL_MspDeInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function configures the source of the time base: + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * The SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __weak to be overwritten in case of other + * implementation in user file. + * @param TickPriority: Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (uwTickFreq != 0U) + { + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U) + { + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + status = HAL_ERROR; + } + } + else + { + status = HAL_ERROR; + } + } + else + { + status = HAL_ERROR; + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions + * @brief HAL Control functions + * +@verbatim + =============================================================================== + ##### HAL Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the HAL API driver version + (+) Get the device identifier + (+) Get the device revision identifier + +@endverbatim + * @{ + */ + +/** + * @brief This function is called to increment a global variable "uwTick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in SysTick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + uwTick += uwTickFreq; +} + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + return uwTick; +} + +/** + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + return uwTickPrio; +} + +/** + * @brief Set new tick Freq. + * @retval status + */ +HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t prevTickFreq; + + assert_param(IS_TICKFREQ(Freq)); + + if (uwTickFreq != Freq) + { + /* Back up uwTickFreq frequency */ + prevTickFreq = uwTickFreq; + + /* Update uwTickFreq global variable used by HAL_InitTick() */ + uwTickFreq = Freq; + + /* Apply the new tick Freq */ + status = HAL_InitTick(uwTickPrio); + + if (status != HAL_OK) + { + /* Restore previous tick frequency */ + uwTickFreq = prevTickFreq; + } + } + + return status; +} + +/** + * @brief Returns tick frequency. + * @retval Tick frequency. + * Value of @ref HAL_TickFreqTypeDef. + */ +uint32_t HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + +/** + * @brief This function provides minimum delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = Delay; + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + { + wait += (uint32_t)(uwTickFreq); + } + + while ((HAL_GetTick() - tickstart) < wait) + { + } +} + +/** + * @brief Suspends Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) +{ + /* Disable SysTick Interrupt */ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Returns the HAL revision. + * @retval version : 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t HAL_GetHalVersion(void) +{ + return __STM32G4xx_HAL_VERSION; +} + +/** + * @brief Returns the device revision identifier. + * @retval Device revision identifier + */ +uint32_t HAL_GetREVID(void) +{ + return ((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16U); +} + +/** + * @brief Returns the device identifier. + * @retval Device identifier + */ +uint32_t HAL_GetDEVID(void) +{ + return (DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID); +} + +/** + * @brief Return the first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return (READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Return the second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return (READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Return the third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return (READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions + * @brief HAL Debug functions + * +@verbatim + =============================================================================== + ##### HAL Debug functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Enable/Disable Debug module during SLEEP mode + (+) Enable/Disable Debug module during STOP0/STOP1/STOP2 modes + (+) Enable/Disable Debug module during STANDBY mode + +@endverbatim + * @{ + */ + +/** + * @brief Enable the Debug Module during SLEEP mode. + * @retval None + */ +void HAL_DBGMCU_EnableDBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Disable the Debug Module during SLEEP mode. + * @retval None + */ +void HAL_DBGMCU_DisableDBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Enable the Debug Module during STOP0/STOP1/STOP2 modes. + * @retval None + */ +void HAL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP0/STOP1/STOP2 modes. + * @retval None + */ +void HAL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode. + * @retval None + */ +void HAL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode. + * @retval None + */ +void HAL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions + * @brief HAL SYSCFG configuration functions + * +@verbatim + =============================================================================== + ##### HAL SYSCFG configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Start a hardware CCMSRAM erase operation + (+) Enable/Disable the Internal FLASH Bank Swapping + (+) Configure the Voltage reference buffer + (+) Enable/Disable the Voltage reference buffer + (+) Enable/Disable the I/O analog switch voltage booster + +@endverbatim + * @{ + */ + +/** + * @brief Start a hardware CCMSRAM erase operation. + * @note As long as CCMSRAM is not erased the CCMER bit will be set. + * This bit is automatically reset at the end of the CCMSRAM erase operation. + * @retval None + */ +void HAL_SYSCFG_CCMSRAMErase(void) +{ + /* unlock the write protection of the CCMER bit */ + SYSCFG->SKR = 0xCA; + SYSCFG->SKR = 0x53; + /* Starts a hardware CCMSRAM erase operation*/ + SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER); +} + +/** + * @brief Enable the Internal FLASH Bank Swapping. + * + * @note This function can be used only for STM32G4xx devices. + * + * @note Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) + * and Flash Bank1 mapped at 0x08040000 (and aliased at 0x00040000) + * + * @retval None + */ +void HAL_SYSCFG_EnableMemorySwappingBank(void) +{ + SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE); +} + +/** + * @brief Disable the Internal FLASH Bank Swapping. + * + * @note This function can be used only for STM32G4xx devices. + * + * @note The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000) + * and Flash Bank2 mapped at 0x08040000 (and aliased at 0x00040000) + * + * @retval None + */ +void HAL_SYSCFG_DisableMemorySwappingBank(void) +{ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE); +} + +#if defined(VREFBUF) +/** + * @brief Configure the internal voltage reference buffer voltage scale. + * @param VoltageScaling: specifies the output voltage to achieve + * This parameter can be one of the following values: + * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREFBUF_OUT around 2.048 V. + * This requires VDDA equal to or higher than 2.4 V. + * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREFBUF_OUT around 2.5 V. + * This requires VDDA equal to or higher than 2.8 V. + * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREFBUF_OUT around 2.9 V. + * This requires VDDA equal to or higher than 3.15 V. + * @retval None + */ +void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling)); + + MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling); +} + +/** + * @brief Configure the internal voltage reference buffer high impedance mode. + * @param Mode: specifies the high impedance mode + * This parameter can be one of the following values: + * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output. + * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance. + * @retval None + */ +void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode)); + + MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode); +} + +/** + * @brief Tune the Internal Voltage Reference buffer (VREFBUF). + * @param TrimmingValue specifies trimming code for VREFBUF calibration + * This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x3F + * @retval None + */ +void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue)); + + MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue); +} + +/** + * @brief Enable the Internal Voltage Reference buffer (VREFBUF). + * @retval HAL_OK/HAL_TIMEOUT + */ +HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void) +{ + uint32_t tickstart; + + SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait for VRR bit */ + while (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0x00U) + { + if ((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Disable the Internal Voltage Reference buffer (VREFBUF). + * + * @retval None + */ +void HAL_SYSCFG_DisableVREFBUF(void) +{ + CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); +} +#endif /* VREFBUF */ + +/** + * @brief Enable the I/O analog switch voltage booster + * + * @retval None + */ +void HAL_SYSCFG_EnableIOSwitchBooster(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); +} + +/** + * @brief Disable the I/O analog switch voltage booster + * + * @retval None + */ +void HAL_SYSCFG_DisableIOSwitchBooster(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); +} + +/** + * @brief Enable the I/O analog switch voltage by VDD + * + * @retval None + */ +void HAL_SYSCFG_EnableIOSwitchVDD(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD); +} + +/** + * @brief Disable the I/O analog switch voltage by VDD + * + * @retval None + */ +void HAL_SYSCFG_DisableIOSwitchVDD(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD); +} + + +/** @brief CCMSRAM page write protection enable + * @param Page: This parameter is a long 32bit value and can be a value of @ref SYSCFG_CCMSRAMWRP + * @note write protection can only be disabled by a system reset + * @retval None + */ +void HAL_SYSCFG_CCMSRAM_WriteProtectionEnable(uint32_t Page) +{ + assert_param(IS_SYSCFG_CCMSRAMWRP_PAGE(Page)); + + SET_BIT(SYSCFG->SWPR, (uint32_t)(Page)); +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c new file mode 100644 index 000000000..5bb9c5758 --- /dev/null +++ b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c @@ -0,0 +1,517 @@ +/** + ****************************************************************************** + * @file stm32g4xx_hal_cortex.c + * @author MCD Application Team + * @brief CORTEX HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the CORTEX: + * + Initialization and Configuration functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + + [..] + *** How to configure Interrupts using CORTEX HAL driver *** + =========================================================== + [..] + This section provides functions allowing to configure the NVIC interrupts (IRQ). + The Cortex-M4 exceptions are managed by CMSIS functions. + + (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function. + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). + + -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. + The pending IRQ priority will be managed only by the sub priority. + + -@- IRQ priority order (sorted by highest to lowest priority): + (+@) Lowest pre-emption priority + (+@) Lowest sub priority + (+@) Lowest hardware priority (IRQ number) + + [..] + *** How to configure SysTick using CORTEX HAL driver *** + ======================================================== + [..] + Setup SysTick Timer for time base. + + (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which + is a CMSIS function that: + (++) Configures the SysTick Reload register with value passed as function parameter. + (++) Configures the SysTick IRQ priority to the lowest value (0x0F). + (++) Resets the SysTick Counter register. + (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + (++) Enables the SysTick Interrupt. + (++) Starts the SysTick Counter. + + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined + inside the stm32g4xx_hal_cortex.h file. + + (+) You can change the SysTick IRQ priority by calling the + HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. + + (+) To adjust the SysTick time base, use the following formula: + + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + (++) Reload Value should not exceed 0xFFFFFF + + @endverbatim + ****************************************************************************** + + The table below gives the allowed values of the pre-emption priority and subpriority according + to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function. + + ========================================================================================================================== + NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description + ========================================================================================================================== + NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bit for pre-emption priority + | | | 4 bits for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority + | | | 3 bits for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority + | | | 2 bits for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority + | | | 1 bit for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority + | | | 0 bit for subpriority + ========================================================================================================================== + + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_hal.h" + +/** @addtogroup STM32G4xx_HAL_Driver + * @{ + */ + +/** @addtogroup CORTEX + * @{ + */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup CORTEX_Exported_Functions + * @{ + */ + + +/** @addtogroup CORTEX_Exported_Functions_Group1 + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and Configuration functions ##### + ============================================================================== + [..] + This section provides the CORTEX HAL driver functions allowing to configure Interrupts + SysTick functionalities + +@endverbatim + * @{ + */ + + +/** + * @brief Set the priority grouping field (pre-emption priority and subpriority) + * using the required unlock sequence. + * @param PriorityGroup: The priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, + * 1 bit for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, + * 0 bit for subpriority + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); +} + +/** + * @brief Set the priority of an interrupt. + * @param IRQn: External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h)) + * @param PreemptPriority: The pre-emption priority for the IRQn channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority + * @param SubPriority: the subpriority level for the IRQ channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t prioritygroup; + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); +} + +/** + * @brief Enable a device specific interrupt in the NVIC interrupt controller. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disable a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Initiate a system reset request to reset the MCU. + * @retval None + */ +void HAL_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/** + * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): + * Counter is in free running mode to generate periodic interrupts. + * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + return SysTick_Config(TicksNumb); +} +/** + * @} + */ + +/** @addtogroup CORTEX_Exported_Functions_Group2 + * @brief Cortex control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the CORTEX + (NVIC, SYSTICK, MPU) functionalities. + + +@endverbatim + * @{ + */ + +/** + * @brief Get the priority grouping field from the NVIC Interrupt Controller. + * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) + */ +uint32_t HAL_NVIC_GetPriorityGrouping(void) +{ + /* Get the PRIGROUP[10:8] field value */ + return NVIC_GetPriorityGrouping(); +} + +/** + * @brief Get the priority of an interrupt. + * @param IRQn: External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h)) + * @param PriorityGroup: the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, + * 1 bit for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, + * 0 bit for subpriority + * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). + * @param pSubPriority: Pointer on the Subpriority value (starting from 0). + * @retval None + */ +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + /* Get priority for Cortex-M system or device specific interrupts */ + NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); +} + +/** + * @brief Set Pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h)) + * @retval None + */ +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Get Pending Interrupt (read the pending register in the NVIC + * and return the pending bit for the specified interrupt). + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if pending else 0 */ + return NVIC_GetPendingIRQ(IRQn); +} + +/** + * @brief Clear the pending bit of an external interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h)) + * @retval None + */ +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Clear pending interrupt */ + NVIC_ClearPendingIRQ(IRQn); +} + +/** + * @brief Get active interrupt (read the active register in NVIC and return the active bit). + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) +{ + /* Return 1 if active else 0 */ + return NVIC_GetActive(IRQn); +} + +/** + * @brief Configure the SysTick clock source. + * @param CLKSource: specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + { + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + } + else + { + SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; + } +} + +/** + * @brief Handle SYSTICK interrupt request. + * @retval None + */ +void HAL_SYSTICK_IRQHandler(void) +{ + HAL_SYSTICK_Callback(); +} + +/** + * @brief SYSTICK callback. + * @retval None + */ +__weak void HAL_SYSTICK_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SYSTICK_Callback could be implemented in the user file + */ +} + +#if (__MPU_PRESENT == 1) +/** + * @brief Enable the MPU. + * @param MPU_Control: Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged accessto the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + /* Enable the MPU */ + MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk); + + /* Ensure MPU setting take effects */ + __DSB(); + __ISB(); +} + + +/** + * @brief Disable the MPU. + * @retval None + */ +void HAL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + + /* Disable the MPU and clear the control register*/ + MPU->CTRL = 0; +} + + +/** + * @brief Initialize and configure the Region and the memory to be protected. + * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); + assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); + + /* Set the Region number */ + MPU->RNR = MPU_Init->Number; + + if ((MPU_Init->Enable) != 0U) + { + /* Check the parameters */ + assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); + assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); + assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); + assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); + assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); + assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); + assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); + + MPU->RBAR = MPU_Init->BaseAddress; + MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); + } + else + { + MPU->RBAR = 0x00; + MPU->RASR = 0x00; + } +} +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CORTEX_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c new file mode 100644 index 000000000..a802626cf --- /dev/null +++ b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c @@ -0,0 +1,532 @@ +/** + ****************************************************************************** + * @file stm32g4xx_hal_gpio.c + * @author MCD Application Team + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually + configured by software in several modes: + (++) Input mode + (++) Analog mode + (++) Output mode + (++) Alternate function mode + (++) External interrupt/event lines + + (+) During and just after reset, the alternate functions and external interrupt + lines are not active and the I/O ports are configured in input floating mode. + + (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull + type and the IO speed can be selected depending on the VDD value. + + (+) The microcontroller IO pins are connected to onboard peripherals/modules through a + multiplexer that allows only one peripheral alternate function (AF) connected + to an IO pin at a time. In this way, there can be no conflict between peripherals + sharing the same IO pin. + + (+) All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + (+) The external interrupt/event controller consists of up to 44 edge detectors + (16 lines are connected to GPIO) for generating event/interrupt requests (each + input line can be independently configured to select the type (interrupt or event) + and the corresponding trigger event (rising or falling or both). Each line can + also be masked independently. + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). + + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + structure. + (++) In case of Output or alternate function mode selection: the speed is + configured through "Speed" member from GPIO_InitTypeDef structure. + (++) In alternate mode is selection, the alternate function connected to the IO + is configured through "Alternate" member from GPIO_InitTypeDef structure. + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + (++) In case of external interrupt/event selection the "Mode" member from + GPIO_InitTypeDef structure select the type (interrupt or event) and + the corresponding trigger event (rising or falling or both). + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + HAL_NVIC_EnableIRQ(). + + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + + (#) To set/reset the level of a pin configured in output mode use + HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + + (#) During and just after reset, the alternate functions are not + active and the GPIO pins are configured in input floating mode (except JTAG + pins). + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + priority over the GPIO function. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PF0 and PF1, respectively, when the HSE oscillator is off. + The HSE has priority over the GPIO function. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_hal.h" + +/** @addtogroup STM32G4xx_HAL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rules: + * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of + * range of the shift operator in following API : + * HAL_GPIO_Init + * HAL_GPIO_DeInit + */ + +#ifdef HAL_GPIO_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @addtogroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ +#define GPIO_NUMBER (16U) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup GPIO_Exported_Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init. + * @param GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + uint32_t position = 0x00U; + uint32_t iocurrent; + uint32_t temp; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0U) + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1UL << position); + + if (iocurrent != 0x00u) + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || + ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); + temp |= (GPIO_Init->Speed << (position * 2U)); + GPIOx->OSPEEDR = temp; + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + temp &= ~(GPIO_OTYPER_OT0 << position) ; + temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + GPIOx->OTYPER = temp; + } + + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + { + /* Check the Pull parameter */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + temp |= ((GPIO_Init->Pull) << (position * 2U)); + GPIOx->PUPDR = temp; + } + + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + { + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3U]; + temp &= ~(0xFU << ((position & 0x07U) * 4U)); + temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); + GPIOx->AFR[position >> 3U] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); + GPIOx->MODER = temp; + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + temp = SYSCFG->EXTICR[position >> 2U]; + temp &= ~(0x0FUL << (4U * (position & 0x03U))); + temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); + SYSCFG->EXTICR[position >> 2U] = temp; + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) + { + temp |= iocurrent; + } + EXTI->RTSR1 = temp; + + temp = EXTI->FTSR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) + { + temp |= iocurrent; + } + EXTI->FTSR1 = temp; + + temp = EXTI->EMR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) + { + temp |= iocurrent; + } + EXTI->EMR1 = temp; + + /* Clear EXTI line configuration */ + temp = EXTI->IMR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) + { + temp |= iocurrent; + } + EXTI->IMR1 = temp; + } + } + + position++; + } +} + +/** + * @brief De-initialize the GPIOx peripheral registers to their default reset values. + * @param GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint32_t position = 0x00U; + uint32_t iocurrent; + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0U) + { + /* Get current io position */ + iocurrent = (GPIO_Pin) & (1UL << position); + + if (iocurrent != 0x00u) + { + /*------------------------- EXTI Mode Configuration --------------------*/ + /* Clear the External Interrupt or Event for the current IO */ + + tmp = SYSCFG->EXTICR[position >> 2U]; + tmp &= (0x0FUL << (4U * (position & 0x03U))); + if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) + { + /* Clear EXTI line configuration */ + EXTI->IMR1 &= ~(iocurrent); + EXTI->EMR1 &= ~(iocurrent); + + /* Clear Rising Falling edge configuration */ + EXTI->FTSR1 &= ~(iocurrent); + EXTI->RTSR1 &= ~(iocurrent); + + tmp = 0x0FUL << (4U * (position & 0x03U)); + SYSCFG->EXTICR[position >> 2U] &= ~tmp; + } + + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO in Analog Mode */ + GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u)); + + /* Configure the default Alternate Function in current IO */ + GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)); + + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); + + /* Configure the default value IO Output Type */ + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position); + + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); + } + + position++; + } +} + +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Functions_Group2 + * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Read the specified input port pin. + * @param GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family + * @param GPIO_Pin specifies the port bit to read. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != 0x00U) + { + bitstatus = GPIO_PIN_SET; + } + else + { + bitstatus = GPIO_PIN_RESET; + } + return bitstatus; +} + +/** + * @brief Set or clear the selected data port bit. + * + * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * + * @param GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). + * @param PinState specifies the value to be written to the selected bit. + * This parameter can be one of the GPIO_PinState enum values: + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + } + else + { + GPIOx->BRR = (uint32_t)GPIO_Pin; + } +} + +/** + * @brief Toggle the specified GPIO pin. + * @param GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family + * @param GPIO_Pin specifies the pin to be toggled. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t odr; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* get current Output Data Register value */ + odr = GPIOx->ODR; + + /* Set selected pins that were at low level, and reset ones that were high */ + GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); +} + +/** + * @brief Lock GPIO Pins configuration registers. + * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + * @note The configuration of the locked GPIO pins can no longer be modified + * until the next reset. + * @param GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family + * @param GPIO_Pin specifies the port bits to be locked. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = GPIO_LCKR_LCKK; + + /* Check the parameters */ + assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Apply lock key write sequence */ + tmp |= GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Read LCKK register. This read is mandatory to complete key lock sequence */ + tmp = GPIOx->LCKR; + + /* read again in order to confirm lock is active */ + if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u) + { + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Handle EXTI interrupt request. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + /* EXTI line interrupt detected */ + if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + HAL_GPIO_EXTI_Callback(GPIO_Pin); + } +} + +/** + * @brief EXTI line detection callback. + * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + + +/** + * @} + */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c new file mode 100644 index 000000000..5ec00b2e9 --- /dev/null +++ b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c @@ -0,0 +1,1182 @@ +/** + ****************************************************************************** + * @file stm32g4xx_hal_pwr_ex.c + * @author MCD Application Team + * @brief Extended PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Extended Initialization and de-initialization functions + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_hal.h" + +/** @addtogroup STM32G4xx_HAL_Driver + * @{ + */ + +/** @defgroup PWREx PWREx + * @brief PWR Extended HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + + +#if defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G474xx) || defined (STM32G483xx) || defined (STM32G484xx) +#define PWR_PORTF_AVAILABLE_PINS 0x0000FFFFU /* PF0..PF15 */ +#define PWR_PORTG_AVAILABLE_PINS 0x000007FFU /* PG0..PG10 */ +#elif defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32GBK1CB) || defined (STM32G491xx) || defined (STM32G4A1xx) +#define PWR_PORTF_AVAILABLE_PINS 0x00000607U /* PF0..PF2 and PF9 and PF10 */ +#define PWR_PORTG_AVAILABLE_PINS 0x00000400U /* PG10 */ +#endif + +/** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines + * @{ + */ + +/** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask + * @{ + */ +#define PVM_MODE_IT 0x00010000U /*!< Mask for interruption yielded by PVM threshold crossing */ +#define PVM_MODE_EVT 0x00020000U /*!< Mask for event yielded by PVM threshold crossing */ +#define PVM_RISING_EDGE 0x00000001U /*!< Mask for rising edge set as PVM trigger */ +#define PVM_FALLING_EDGE 0x00000002U /*!< Mask for falling edge set as PVM trigger */ +/** + * @} + */ + +/** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value + * @{ + */ +#define PWR_FLAG_SETTING_DELAY_US 50UL /*!< Time out value for REGLPF and VOSF flags setting */ +/** + * @} + */ + + + +/** + * @} + */ + + + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions + * @{ + */ + +/** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Initialization and de-initialization functions ##### + =============================================================================== + [..] + +@endverbatim + * @{ + */ + + +/** + * @brief Return Voltage Scaling Range. + * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2 + * or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable) + */ +uint32_t HAL_PWREx_GetVoltageRange(void) +{ + if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) + { + return PWR_REGULATOR_VOLTAGE_SCALE2; + } + else if (READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == PWR_CR5_R1MODE) + { + /* PWR_CR5_R1MODE bit set means that Range 1 Boost is disabled */ + return PWR_REGULATOR_VOLTAGE_SCALE1; + } + else + { + return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST; + } +} + + + +/** + * @brief Configure the main internal regulator output voltage. + * @param VoltageScaling: specifies the regulator output voltage to achieve + * a tradeoff between performance and power consumption. + * This parameter can be one of the following values: + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when available, Regulator voltage output range 1 boost mode, + * typical output voltage at 1.28 V, + * system frequency up to 170 MHz. + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, + * typical output voltage at 1.2 V, + * system frequency up to 150 MHz. + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, + * typical output voltage at 1.0 V, + * system frequency up to 26 MHz. + * @note When moving from Range 1 to Range 2, the system frequency must be decreased to + * a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API. + * When moving from Range 2 to Range 1, the system frequency can be increased to + * a value up to 150 MHz after calling HAL_PWREx_ControlVoltageScaling() API. + * When moving from Range 1 to Boost Mode Range 1, the system frequency can be increased to + * a value up to 170 MHz after calling HAL_PWREx_ControlVoltageScaling() API. + * @note When moving from Range 2 to Range 1, the API waits for VOSF flag to be + * cleared before returning the status. If the flag is not cleared within + * 50 microseconds, HAL_TIMEOUT status is reported. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) +{ + uint32_t wait_loop_index; + + assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); + + if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) + { + /* If current range is range 2 */ + if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) + { + /* Make sure Range 1 Boost is enabled */ + CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); + + /* Set Range 1 */ + MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Wait until VOSF is cleared */ + wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; + while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) + { + wait_loop_index--; + } + if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) + { + return HAL_TIMEOUT; + } + } + /* If current range is range 1 normal or boost mode */ + else + { + /* Enable Range 1 Boost (no issue if bit already reset) */ + CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); + } + } + else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) + { + /* If current range is range 2 */ + if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) + { + /* Make sure Range 1 Boost is disabled */ + SET_BIT(PWR->CR5, PWR_CR5_R1MODE); + + /* Set Range 1 */ + MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Wait until VOSF is cleared */ + wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; + while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) + { + wait_loop_index--; + } + if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) + { + return HAL_TIMEOUT; + } + } + /* If current range is range 1 normal or boost mode */ + else + { + /* Disable Range 1 Boost (no issue if bit already set) */ + SET_BIT(PWR->CR5, PWR_CR5_R1MODE); + } + } + else + { + /* Set Range 2 */ + MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2); + /* No need to wait for VOSF to be cleared for this transition */ + /* PWR_CR5_R1MODE bit setting has no effect in Range 2 */ + } + + return HAL_OK; +} + + +/** + * @brief Enable battery charging. + * When VDD is present, charge the external battery on VBAT through an internal resistor. + * @param ResistorSelection: specifies the resistor impedance. + * This parameter can be one of the following values: + * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor + * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor + * @retval None + */ +void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection) +{ + assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection)); + + /* Specify resistor selection */ + MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection); + + /* Enable battery charging */ + SET_BIT(PWR->CR4, PWR_CR4_VBE); +} + + +/** + * @brief Disable battery charging. + * @retval None + */ +void HAL_PWREx_DisableBatteryCharging(void) +{ + CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); +} + + +/** + * @brief Enable Internal Wake-up Line. + * @retval None + */ +void HAL_PWREx_EnableInternalWakeUpLine(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_EIWF); +} + + +/** + * @brief Disable Internal Wake-up Line. + * @retval None + */ +void HAL_PWREx_DisableInternalWakeUpLine(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF); +} + + + +/** + * @brief Enable GPIO pull-up state in Standby and Shutdown modes. + * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in + * pull-up state in Standby and Shutdown modes. + * @note This state is effective in Standby and Shutdown modes only if APC bit + * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. + * @note The configuration is lost when exiting the Shutdown mode due to the + * power-on reset, maintained when exiting the Standby mode. + * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding + * PDy bit of PWR_PDCRx register is cleared unless it is reserved. + * @note Even if a PUy bit to set is reserved, the other PUy bits entered as input + * parameter at the same time are set. + * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_G + * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral. + * @param GPIONumber: Specify the I/O pins numbers. + * This parameter can be one of the following values: + * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less + * I/O pins are available) or the logical OR of several of them to set + * several bits for a given port in a single API call. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_PWR_GPIO(GPIO)); + assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); + + switch (GPIO) + { + case PWR_GPIO_A: + SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14)))); + CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15)))); + break; + case PWR_GPIO_B: + SET_BIT(PWR->PUCRB, GPIONumber); + CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4)))); + break; + case PWR_GPIO_C: + SET_BIT(PWR->PUCRC, GPIONumber); + CLEAR_BIT(PWR->PDCRC, GPIONumber); + break; + case PWR_GPIO_D: + SET_BIT(PWR->PUCRD, GPIONumber); + CLEAR_BIT(PWR->PDCRD, GPIONumber); + break; + case PWR_GPIO_E: + SET_BIT(PWR->PUCRE, GPIONumber); + CLEAR_BIT(PWR->PDCRE, GPIONumber); + break; + case PWR_GPIO_F: + SET_BIT(PWR->PUCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS)); + CLEAR_BIT(PWR->PDCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS)); + break; + case PWR_GPIO_G: + SET_BIT(PWR->PUCRG, (GPIONumber & PWR_PORTG_AVAILABLE_PINS)); + CLEAR_BIT(PWR->PDCRG, ((GPIONumber & PWR_PORTG_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_10)))); + break; + default: + status = HAL_ERROR; + break; + } + + return status; +} + + +/** + * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes. + * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O + * in pull-up state in Standby and Shutdown modes. + * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as input + * parameter at the same time are reset. + * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_G + * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral. + * @param GPIONumber: Specify the I/O pins numbers. + * This parameter can be one of the following values: + * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less + * I/O pins are available) or the logical OR of several of them to reset + * several bits for a given port in a single API call. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_PWR_GPIO(GPIO)); + assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); + + switch (GPIO) + { + case PWR_GPIO_A: + CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14)))); + break; + case PWR_GPIO_B: + CLEAR_BIT(PWR->PUCRB, GPIONumber); + break; + case PWR_GPIO_C: + CLEAR_BIT(PWR->PUCRC, GPIONumber); + break; + case PWR_GPIO_D: + CLEAR_BIT(PWR->PUCRD, GPIONumber); + break; + case PWR_GPIO_E: + CLEAR_BIT(PWR->PUCRE, GPIONumber); + break; + case PWR_GPIO_F: + CLEAR_BIT(PWR->PUCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS)); + break; + case PWR_GPIO_G: + CLEAR_BIT(PWR->PUCRG, (GPIONumber & PWR_PORTG_AVAILABLE_PINS)); + break; + default: + status = HAL_ERROR; + break; + } + + return status; +} + + + +/** + * @brief Enable GPIO pull-down state in Standby and Shutdown modes. + * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in + * pull-down state in Standby and Shutdown modes. + * @note This state is effective in Standby and Shutdown modes only if APC bit + * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. + * @note The configuration is lost when exiting the Shutdown mode due to the + * power-on reset, maintained when exiting the Standby mode. + * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding + * PUy bit of PWR_PUCRx register is cleared unless it is reserved. + * @note Even if a PDy bit to set is reserved, the other PDy bits entered as input + * parameter at the same time are set. + * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_G + * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral. + * @param GPIONumber: Specify the I/O pins numbers. + * This parameter can be one of the following values: + * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less + * I/O pins are available) or the logical OR of several of them to set + * several bits for a given port in a single API call. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_PWR_GPIO(GPIO)); + assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); + + switch (GPIO) + { + case PWR_GPIO_A: + SET_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15)))); + CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14)))); + break; + case PWR_GPIO_B: + SET_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4)))); + CLEAR_BIT(PWR->PUCRB, GPIONumber); + break; + case PWR_GPIO_C: + SET_BIT(PWR->PDCRC, GPIONumber); + CLEAR_BIT(PWR->PUCRC, GPIONumber); + break; + case PWR_GPIO_D: + SET_BIT(PWR->PDCRD, GPIONumber); + CLEAR_BIT(PWR->PUCRD, GPIONumber); + break; + case PWR_GPIO_E: + SET_BIT(PWR->PDCRE, GPIONumber); + CLEAR_BIT(PWR->PUCRE, GPIONumber); + break; + case PWR_GPIO_F: + SET_BIT(PWR->PDCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS)); + CLEAR_BIT(PWR->PUCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS)); + break; + case PWR_GPIO_G: + SET_BIT(PWR->PDCRG, ((GPIONumber & PWR_PORTG_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_10)))); + CLEAR_BIT(PWR->PUCRG, (GPIONumber & PWR_PORTG_AVAILABLE_PINS)); + break; + default: + status = HAL_ERROR; + break; + } + + return status; +} + + +/** + * @brief Disable GPIO pull-down state in Standby and Shutdown modes. + * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O + * in pull-down state in Standby and Shutdown modes. + * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input + * parameter at the same time are reset. + * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_G + * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral. + * @param GPIONumber: Specify the I/O pins numbers. + * This parameter can be one of the following values: + * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less + * I/O pins are available) or the logical OR of several of them to reset + * several bits for a given port in a single API call. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_PWR_GPIO(GPIO)); + assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); + + switch (GPIO) + { + case PWR_GPIO_A: + CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15)))); + break; + case PWR_GPIO_B: + CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4)))); + break; + case PWR_GPIO_C: + CLEAR_BIT(PWR->PDCRC, GPIONumber); + break; + case PWR_GPIO_D: + CLEAR_BIT(PWR->PDCRD, GPIONumber); + break; + case PWR_GPIO_E: + CLEAR_BIT(PWR->PDCRE, GPIONumber); + break; + case PWR_GPIO_F: + CLEAR_BIT(PWR->PDCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS)); + break; + case PWR_GPIO_G: + CLEAR_BIT(PWR->PDCRG, ((GPIONumber & PWR_PORTG_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_10)))); + break; + default: + status = HAL_ERROR; + break; + } + + return status; +} + + + +/** + * @brief Enable pull-up and pull-down configuration. + * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in + * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes. + * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding + * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher). + * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there + * is no conflict when setting PUy or PDy bit. + * @retval None + */ +void HAL_PWREx_EnablePullUpPullDownConfig(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_APC); +} + + +/** + * @brief Disable pull-up and pull-down configuration. + * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in + * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes. + * @retval None + */ +void HAL_PWREx_DisablePullUpPullDownConfig(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_APC); +} + + + +/** + * @brief Enable SRAM2 content retention in Standby mode. + * @note When RRS bit is set, SRAM2 is powered by the low-power regulator in + * Standby mode and its content is kept. + * @retval None + */ +void HAL_PWREx_EnableSRAM2ContentRetention(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_RRS); +} + + +/** + * @brief Disable SRAM2 content retention in Standby mode. + * @note When RRS bit is reset, SRAM2 is powered off in Standby mode + * and its content is lost. + * @retval None + */ +void HAL_PWREx_DisableSRAM2ContentRetention(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); +} + + + + +#if defined(PWR_CR2_PVME1) +/** + * @brief Enable the Power Voltage Monitoring 1: VDDA versus FASTCOMP minimum voltage. + * @retval None + */ +void HAL_PWREx_EnablePVM1(void) +{ + SET_BIT(PWR->CR2, PWR_PVM_1); +} + +/** + * @brief Disable the Power Voltage Monitoring 1: VDDA versus FASTCOMP minimum voltage. + * @retval None + */ +void HAL_PWREx_DisablePVM1(void) +{ + CLEAR_BIT(PWR->CR2, PWR_PVM_1); +} +#endif /* PWR_CR2_PVME1 */ + + +#if defined(PWR_CR2_PVME2) +/** + * @brief Enable the Power Voltage Monitoring 2: VDDA versus FASTDAC minimum voltage. + * @retval None + */ +void HAL_PWREx_EnablePVM2(void) +{ + SET_BIT(PWR->CR2, PWR_PVM_2); +} + +/** + * @brief Disable the Power Voltage Monitoring 2: VDDA versus FASTDAC minimum voltage. + * @retval None + */ +void HAL_PWREx_DisablePVM2(void) +{ + CLEAR_BIT(PWR->CR2, PWR_PVM_2); +} +#endif /* PWR_CR2_PVME2 */ + + +/** + * @brief Enable the Power Voltage Monitoring 3: VDDA versus ADC minimum voltage 1.62V. + * @retval None + */ +void HAL_PWREx_EnablePVM3(void) +{ + SET_BIT(PWR->CR2, PWR_PVM_3); +} + +/** + * @brief Disable the Power Voltage Monitoring 3: VDDA versus ADC minimum voltage 1.62V. + * @retval None + */ +void HAL_PWREx_DisablePVM3(void) +{ + CLEAR_BIT(PWR->CR2, PWR_PVM_3); +} + + +/** + * @brief Enable the Power Voltage Monitoring 4: VDDA versus OPAMP/DAC minimum voltage 1.8V. + * @retval None + */ +void HAL_PWREx_EnablePVM4(void) +{ + SET_BIT(PWR->CR2, PWR_PVM_4); +} + +/** + * @brief Disable the Power Voltage Monitoring 4: VDDA versus OPAMP/DAC minimum voltage 1.8V. + * @retval None + */ +void HAL_PWREx_DisablePVM4(void) +{ + CLEAR_BIT(PWR->CR2, PWR_PVM_4); +} + + + + +/** + * @brief Configure the Peripheral Voltage Monitoring (PVM). + * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the + * PVM configuration information. + * @note The API configures a single PVM according to the information contained + * in the input structure. To configure several PVMs, the API must be singly + * called for each PVM used. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage thresholds corresponding to each + * detection level and to each monitored supply. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType)); + assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode)); + + + /* Configure EXTI 35 to 38 interrupts if so required: + scan through PVMType to detect which PVMx is set and + configure the corresponding EXTI line accordingly. */ + switch (sConfigPVM->PVMType) + { +#if defined(PWR_CR2_PVME1) + case PWR_PVM_1: + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ + __HAL_PWR_PVM1_EXTI_DISABLE_EVENT(); + __HAL_PWR_PVM1_EXTI_DISABLE_IT(); + __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); + __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); + + /* Configure interrupt mode */ + if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) + { + __HAL_PWR_PVM1_EXTI_ENABLE_IT(); + } + + /* Configure event mode */ + if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) + { + __HAL_PWR_PVM1_EXTI_ENABLE_EVENT(); + } + + /* Configure the edge */ + if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) + { + __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); + } + + if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) + { + __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); + } + break; +#endif /* PWR_CR2_PVME1 */ + +#if defined(PWR_CR2_PVME2) + case PWR_PVM_2: + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ + __HAL_PWR_PVM2_EXTI_DISABLE_EVENT(); + __HAL_PWR_PVM2_EXTI_DISABLE_IT(); + __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); + __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); + + /* Configure interrupt mode */ + if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) + { + __HAL_PWR_PVM2_EXTI_ENABLE_IT(); + } + + /* Configure event mode */ + if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) + { + __HAL_PWR_PVM2_EXTI_ENABLE_EVENT(); + } + + /* Configure the edge */ + if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) + { + __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); + } + + if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) + { + __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); + } + break; +#endif /* PWR_CR2_PVME2 */ + + case PWR_PVM_3: + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ + __HAL_PWR_PVM3_EXTI_DISABLE_EVENT(); + __HAL_PWR_PVM3_EXTI_DISABLE_IT(); + __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); + __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); + + /* Configure interrupt mode */ + if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) + { + __HAL_PWR_PVM3_EXTI_ENABLE_IT(); + } + + /* Configure event mode */ + if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) + { + __HAL_PWR_PVM3_EXTI_ENABLE_EVENT(); + } + + /* Configure the edge */ + if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) + { + __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); + } + + if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) + { + __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); + } + break; + + case PWR_PVM_4: + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ + __HAL_PWR_PVM4_EXTI_DISABLE_EVENT(); + __HAL_PWR_PVM4_EXTI_DISABLE_IT(); + __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); + __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); + + /* Configure interrupt mode */ + if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) + { + __HAL_PWR_PVM4_EXTI_ENABLE_IT(); + } + + /* Configure event mode */ + if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) + { + __HAL_PWR_PVM4_EXTI_ENABLE_EVENT(); + } + + /* Configure the edge */ + if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) + { + __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); + } + + if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) + { + __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); + } + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + + +/** + * @brief Enter Low-power Run mode + * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode. + * @note When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the + * Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register. + * Additionally, the clock frequency must be reduced below 2 MHz. + * Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must + * be done before calling HAL_PWREx_EnableLowPowerRunMode() API. + * @retval None + */ +void HAL_PWREx_EnableLowPowerRunMode(void) +{ + /* Set Regulator parameter */ + SET_BIT(PWR->CR1, PWR_CR1_LPR); +} + + +/** + * @brief Exit Low-power Run mode. + * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that + * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode + * returns HAL_TIMEOUT status). The system clock frequency can then be + * increased above 2 MHz. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) +{ + uint32_t wait_loop_index; + + /* Clear LPR bit */ + CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); + + /* Wait until REGLPF is reset */ + wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000U)); + while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U)) + { + wait_loop_index--; + } + if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) + { + return HAL_TIMEOUT; + } + + return HAL_OK; +} + + +/** + * @brief Enter Stop 0 mode. + * @note In Stop 0 mode, main and low voltage regulators are ON. + * @note In Stop 0 mode, all I/O pins keep the same state as in Run mode. + * @note All clocks in the VCORE domain are stopped; the PLL, the HSI + * and the HSE oscillators are disabled. Some peripherals with the wakeup capability + * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI + * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated + * only to the peripheral requesting it. + * SRAM1, SRAM2 and register contents are preserved. + * The BOR is available. + * @note When exiting Stop 0 mode by issuing an interrupt or a wakeup event, + * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register + * is set; the HSI oscillator is selected if STOPWUCK is cleared. + * @note By keeping the internal regulator ON during Stop 0 mode, the consumption + * is higher although the startup time is reduced. + * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction + * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction + * @retval None + */ +void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Stop 0 mode with Main Regulator */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP0); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select Stop mode entry --------------------------------------------------*/ + if(STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + + +/** + * @brief Enter Stop 1 mode. + * @note In Stop 1 mode, only low power voltage regulator is ON. + * @note In Stop 1 mode, all I/O pins keep the same state as in Run mode. + * @note All clocks in the VCORE domain are stopped; the PLL, the HSI + * and the HSE oscillators are disabled. Some peripherals with the wakeup capability + * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI + * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated + * only to the peripheral requesting it. + * SRAM1, SRAM2 and register contents are preserved. + * The BOR is available. + * @note When exiting Stop 1 mode by issuing an interrupt or a wakeup event, + * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register + * is set. + * @note Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode. + * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction + * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction + * @retval None + */ +void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Stop 1 mode with Low-Power Regulator */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select Stop mode entry --------------------------------------------------*/ + if(STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + + + + +/** + * @brief Enter Shutdown mode. + * @note In Shutdown mode, the PLL, the HSI, the LSI and the HSE oscillators are switched + * off. The voltage regulator is disabled and Vcore domain is powered off. + * SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain. + * The BOR is not available. + * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state. + * @retval None + */ +void HAL_PWREx_EnterSHUTDOWNMode(void) +{ + + /* Set Shutdown mode */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + +/* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); +} + + + + +/** + * @brief This function handles the PWR PVD/PVMx interrupt request. + * @note This API should be called under the PVD_PVM_IRQHandler(). + * @retval None + */ +void HAL_PWREx_PVD_PVM_IRQHandler(void) +{ + /* Check PWR exti flag */ + if(__HAL_PWR_PVD_EXTI_GET_FLAG() != 0U) + { + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback(); + + /* Clear PVD exti pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); + } + /* Next, successively check PVMx exti flags */ +#if defined(PWR_CR2_PVME1) + if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != 0U) + { + /* PWR PVM1 interrupt user callback */ + HAL_PWREx_PVM1Callback(); + + /* Clear PVM1 exti pending bit */ + __HAL_PWR_PVM1_EXTI_CLEAR_FLAG(); + } +#endif /* PWR_CR2_PVME1 */ +#if defined(PWR_CR2_PVME2) + if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != 0U) + { + /* PWR PVM2 interrupt user callback */ + HAL_PWREx_PVM2Callback(); + + /* Clear PVM2 exti pending bit */ + __HAL_PWR_PVM2_EXTI_CLEAR_FLAG(); + } +#endif /* PWR_CR2_PVME2 */ + if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != 0U) + { + /* PWR PVM3 interrupt user callback */ + HAL_PWREx_PVM3Callback(); + + /* Clear PVM3 exti pending bit */ + __HAL_PWR_PVM3_EXTI_CLEAR_FLAG(); + } + if(__HAL_PWR_PVM4_EXTI_GET_FLAG() != 0U) + { + /* PWR PVM4 interrupt user callback */ + HAL_PWREx_PVM4Callback(); + + /* Clear PVM4 exti pending bit */ + __HAL_PWR_PVM4_EXTI_CLEAR_FLAG(); + } +} + + +#if defined(PWR_CR2_PVME1) +/** + * @brief PWR PVM1 interrupt callback + * @retval None + */ +__weak void HAL_PWREx_PVM1Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + HAL_PWREx_PVM1Callback() API can be implemented in the user file + */ +} +#endif /* PWR_CR2_PVME1 */ + +#if defined(PWR_CR2_PVME2) +/** + * @brief PWR PVM2 interrupt callback + * @retval None + */ +__weak void HAL_PWREx_PVM2Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + HAL_PWREx_PVM2Callback() API can be implemented in the user file + */ +} +#endif /* PWR_CR2_PVME2 */ + +/** + * @brief PWR PVM3 interrupt callback + * @retval None + */ +__weak void HAL_PWREx_PVM3Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + HAL_PWREx_PVM3Callback() API can be implemented in the user file + */ +} + +/** + * @brief PWR PVM4 interrupt callback + * @retval None + */ +__weak void HAL_PWREx_PVM4Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + HAL_PWREx_PVM4Callback() API can be implemented in the user file + */ +} + +#if defined(PWR_CR3_UCPD_STDBY) +/** + * @brief Enable UCPD configuration memorization in Standby. + * @retval None + */ +void HAL_PWREx_EnableUCPDStandbyMode(void) +{ + /* Memorize UCPD configuration when entering standby mode */ + SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY); +} + +/** + * @brief Disable UCPD configuration memorization in Standby. + * @note This function must be called on exiting the Standby mode and before any UCPD + * configuration update. + * @retval None + */ +void HAL_PWREx_DisableUCPDStandbyMode(void) +{ + /* Write 0 immediately after Standby exit when using UCPD, + and before writing any UCPD registers */ + CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY); +} +#endif /* PWR_CR3_UCPD_STDBY */ + +#if defined(PWR_CR3_UCPD_DBDIS) +/** + * @brief Enable the USB Type-C dead battery pull-down behavior + * on UCPDx_CC1 and UCPDx_CC2 pins + * @retval None + */ +void HAL_PWREx_EnableUCPDDeadBattery(void) +{ + /* Write 0 to enable the USB Type-C dead battery pull-down behavior */ + CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); +} + +/** + * @brief Disable the USB Type-C dead battery pull-down behavior + * on UCPDx_CC1 and UCPDx_CC2 pins + * @note After exiting reset, the USB Type-C dead battery behavior will be enabled, + * which may have a pull-down effect on CC1 and CC2 pins. + * It is recommended to disable it in all cases, either to stop this pull-down + * or to hand over control to the UCPD (which should therefore be + * initialized before doing the disable). + * @retval None + */ +void HAL_PWREx_DisableUCPDDeadBattery(void) +{ + /* Write 1 to disable the USB Type-C dead battery pull-down behavior */ + SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); +} +#endif /* PWR_CR3_UCPD_DBDIS */ + + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c new file mode 100644 index 000000000..884a75ca3 --- /dev/null +++ b/Mcu/g431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c @@ -0,0 +1,1400 @@ +/** + ****************************************************************************** + * @file stm32g4xx_hal_rcc.c + * @author MCD Application Team + * @brief RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Reset and Clock Control (RCC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### RCC specific features ##### + ============================================================================== + [..] + After reset the device is running from High Speed Internal oscillator + (16 MHz) with Flash 0 wait state. Flash prefetch buffer, D-Cache + and I-Cache are disabled, and all peripherals are off except internal + SRAM, Flash and JTAG. + + (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) buses: + all peripherals mapped on these buses are running at HSI speed. + (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + (+) All GPIOs are in analog mode, except the JTAG pins which + are assigned to be used for debug purpose. + + [..] + Once the device started from reset, the user application has to: + (+) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (+) Configure the System clock frequency and Flash settings + (+) Configure the AHB and APB buses prescalers + (+) Enable the clock for the peripheral(s) to be used + (+) Configure the clock source(s) for peripherals which clocks are not + derived from the System clock (USB, RNG, USART, LPUART, FDCAN, some TIMERs, + UCPD, I2S, I2C, LPTIM, ADC, QSPI) + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_hal.h" + +/** @addtogroup STM32G4xx_HAL_Driver + * @{ + */ + +/** @defgroup RCC RCC + * @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ +#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define HSI48_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */ +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCC_Private_Macros RCC Private Macros + * @{ + */ +#define RCC_GET_MCO_GPIO_PIN(__RCC_MCOx__) ((__RCC_MCOx__) & GPIO_PIN_MASK) + +#define RCC_GET_MCO_GPIO_AF(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOAF_MASK) >> RCC_MCO_GPIOAF_POS) + +#define RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOPORT_MASK) >> RCC_MCO_GPIOPORT_POS) + +#define RCC_GET_MCO_GPIO_PORT(__RCC_MCOx__) (AHB2PERIPH_BASE + ((0x00000400UL) * RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__))) + +#define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \ + (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__HAL_RCC_PLLSOURCE__))) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup RCC_Private_Functions RCC Private Functions + * @{ + */ +static uint32_t RCC_GetSysClockFreqFromPLLSource(void); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to configure the internal and external oscillators + (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 + and APB2). + + [..] Internal/external clock and PLL configuration + (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through + the PLL as System clock source. + + (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC + clock source. + + (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also optionally as RTC clock source. + + (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source. + + (+) PLL (clocked by HSI, HSE) providing up to three independent output clocks: + (++) The first output is used to generate the high speed system clock (up to 170 MHz). + (++) The second output is used to generate the clock for the USB (48 MHz), + the QSPI (<= 48 MHz), the FDCAN, the SAI and the I2S. + (++) The third output is used to generate a clock for ADC + + (+) CSS (Clock security system): once enabled, if a HSE clock failure occurs + (HSE used directly or through PLL as System clock source), the System clock + is automatically switched to HSI and an interrupt is generated if enabled. + The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) + exception vector. + + (+) MCO (microcontroller clock output): used to output LSI, HSI, LSE, HSE, + main PLL clock, system clock or RC48 clock (through a configurable prescaler) on PA8 pin. + + [..] System, AHB and APB buses clocks configuration + (+) Several clock sources can be used to drive the System clock (SYSCLK): HSI, + HSE and main PLL. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these buses. You can use + "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + + -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: + + (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock + divided by 2 to 31. + You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function + to configure this clock. + (+@) USB FS and RNG: USB FS requires a frequency equal to 48 MHz + to work correctly, while the RNG peripheral requires a frequency + equal or lower than to 48 MHz. This clock is derived of the main PLL + through PLLQ divider. You have to enable the peripheral clock and use + HAL_RCCEx_PeriphCLKConfig() function to configure this clock. + (+@) IWDG clock which is always the LSI clock. + + + (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 170 MHz. + The clock source frequency should be adapted depending on the device voltage range + as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter. + + @endverbatim + + Table 1. HCLK clock frequency for STM32G4xx devices + +----------------------------------------------------------------------------+ + | Latency | HCLK clock frequency (MHz) | + | |----------------------------------------------------------| + | | voltage range 1 | voltage range 1 | voltage range 2 | + | | boost mode 1.28 V | normal mode 1.2 V | 1.0 V | + |-----------------|-------------------|-------------------|------------------| + |0WS(1 CPU cycles)| HCLK <= 34 | HCLK <= 30 | HCLK <= 13 | + |-----------------|-------------------|-------------------|------------------| + |1WS(2 CPU cycles)| HCLK <= 68 | HCLK <= 60 | HCLK <= 26 | + |-----------------|-------------------|-------------------|------------------| + |2WS(3 CPU cycles)| HCLK <= 102 | HCLK <= 90 | - | + |-----------------|-------------------|-------------------|------------------| + |3WS(4 CPU cycles)| HCLK <= 136 | HCLK <= 120 | - | + |-----------------|-------------------|-------------------|------------------| + |4WS(5 CPU cycles)| HCLK <= 170 | HCLK <= 150 | - | + +----------------------------------------------------------------------------+ + + * @{ + */ + +/** + * @brief Reset the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE, PLL OFF + * - AHB, APB1 and APB2 prescaler set to 1. + * - CSS, MCO1 OFF + * - All interrupts disabled + * - All interrupt and reset flags cleared + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_DeInit(void) +{ + uint32_t tickstart; + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Set HSION bit to the reset value */ + SET_BIT(RCC->CR, RCC_CR_HSION); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set HSITRIM[6:0] bits to the reset value */ + SET_BIT(RCC->ICSCR, RCC_HSICALIBRATION_DEFAULT << RCC_ICSCR_HSITRIM_Pos); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Reset CFGR register (HSI is selected as system clock source) */ + RCC->CFGR = 0x00000001u; + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HSI_VALUE; + + /* Adapt Systick interrupt period */ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear CR register in 2 steps: first to clear HSEON in case bypass was enabled */ + RCC->CR = RCC_CR_HSION; + + /* Then again to HSEBYP in case bypass was enabled */ + RCC->CR = RCC_CR_HSION; + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is OFF */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* once PLL is OFF, reset PLLCFGR register to default value */ + RCC->PLLCFGR = RCC_PLLCFGR_PLLN_4; + + /* Disable all interrupts */ + CLEAR_REG(RCC->CIER); + + /* Clear all interrupt flags */ + WRITE_REG(RCC->CICR, 0xFFFFFFFFU); + + /* Clear all reset flags */ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); + + return HAL_OK; +} + +/** + * @brief Initialize the RCC Oscillators according to the specified parameters in the + * RCC_OscInitTypeDef. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this macro. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t tickstart; + uint32_t temp_sysclksrc; + uint32_t temp_pllckcfg; + + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) || (temp_sysclksrc == RCC_CFGR_SWS_HSE)) + { + if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + { + return HAL_ERROR; + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + + /* Check the HSE State */ + if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); + if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) || (temp_sysclksrc == RCC_CFGR_SWS_HSI)) + { + /* When HSI is used as system clock it will not be disabled */ + if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + + /* Adapt Systick interrupt period */ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + { + return HAL_ERROR; + } + } + } + else + { + /* Check the HSI State */ + if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is disabled */ + while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) + { + if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + FlagStatus pwrclkchanged = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain if necessary */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR1, PWR_CR1_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + + /* Check the LSE State */ + if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) + { + if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is disabled */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) + { + if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Restore clock configuration if changed */ + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + + /*------------------------------ HSI48 Configuration -----------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); + + /* Check the HSI48 State */ + if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) + { + /* Enable the Internal Low Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI48 is ready */ + while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U) + { + if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI48 is disabled */ + while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U) + { + if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + + if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) + { + /* Check if the PLL is used as system clock or not */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) + { + if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); + assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); + assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); + assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + RCC_OscInitStruct->PLL.PLLM, + RCC_OscInitStruct->PLL.PLLN, + RCC_OscInitStruct->PLL.PLLP, + RCC_OscInitStruct->PLL.PLLQ, + RCC_OscInitStruct->PLL.PLLR); + + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + + /* Enable PLL System Clock output. */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Unselect PLL clock source and disable outputs to save power */ + RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_ADCCLK); + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + { + return HAL_ERROR; + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + temp_pllckcfg = RCC->PLLCFGR; + if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) || + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) || + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) || + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) || + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos))) + { + return HAL_ERROR; + } + } + } + } + + return HAL_OK; +} + +/** + * @brief Initialize the CPU, AHB and APB buses clocks according to the specified + * parameters in the RCC_ClkInitStruct. + * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC peripheral. + * @param FLatency FLASH Latency + * This parameter can be one of the following values: + * @arg FLASH_LATENCY_0 FLASH 0 Latency cycle + * @arg FLASH_LATENCY_1 FLASH 1 Latency cycle + * @arg FLASH_LATENCY_2 FLASH 2 Latency cycles + * @arg FLASH_LATENCY_3 FLASH 3 Latency cycles + * @arg FLASH_LATENCY_4 FLASH 4 Latency cycles + * @arg FLASH_LATENCY_5 FLASH 5 Latency cycles + * @arg FLASH_LATENCY_6 FLASH 6 Latency cycles + * @arg FLASH_LATENCY_7 FLASH 7 Latency cycles + * @arg FLASH_LATENCY_8 FLASH 8 Latency cycles + * @arg FLASH_LATENCY_9 FLASH 9 Latency cycles + * @arg FLASH_LATENCY_10 FLASH 10 Latency cycles + * @arg FLASH_LATENCY_11 FLASH 11 Latency cycles + * @arg FLASH_LATENCY_12 FLASH 12 Latency cycles + * @arg FLASH_LATENCY_13 FLASH 13 Latency cycles + * @arg FLASH_LATENCY_14 FLASH 14 Latency cycles + * @arg FLASH_LATENCY_15 FLASH 15 Latency cycles + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated by HAL_RCC_GetHCLKFreq() function called within this function + * + * @note The HSI is used by default as system clock source after + * startup from Reset, wake-up from STANDBY mode. After restart from Reset, + * the HSI frequency is set to its default value 16 MHz. + * + * @note The HSI can be selected as system clock source after + * from STOP modes or in case of failure of the HSE used directly or indirectly + * as system clock (if the Clock Security System CSS is enabled). + * + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after startup delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source is ready. + * + * @note You can use HAL_RCC_GetClockConfig() function to know which clock is + * currently used as system clock source. + * + * @note Depending on the device voltage range, the software has to set correctly + * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + uint32_t tickstart; + uint32_t pllfreq; + uint32_t hpre = RCC_SYSCLK_DIV1; + + /* Check Null pointer */ + if (RCC_ClkInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + assert_param(IS_FLASH_LATENCY(FLatency)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if (FLatency > __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* PLL is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + /* Check the PLL ready flag */ + if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + { + return HAL_ERROR; + } + /* Undershoot management when selection PLL as SYSCLK source and frequency above 80Mhz */ + /* Compute target PLL output frequency */ + pllfreq = RCC_GetSysClockFreqFromPLLSource(); + + /* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */ + if(pllfreq > 80000000U) + { + if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) || + (((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) && + (RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1)))) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); + hpre = RCC_SYSCLK_DIV2; + } + } + } + else + { + /* HSE is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) + { + return HAL_ERROR; + } + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + { + return HAL_ERROR; + } + } + /* Overshoot management when going down from PLL as SYSCLK source and frequency above 80Mhz */ + pllfreq = HAL_RCC_GetSysClockFreq(); + + /* Intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */ + if(pllfreq > 80000000U) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); + hpre = RCC_SYSCLK_DIV2; + } + + } + + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + /* Set the highest APB divider in order to ensure that we do not go through + a non-spec phase whatever we decrease or increase HCLK. */ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); + } + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, RCC_HCLK_DIV16); + } + + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } + else + { + /* Is intermediate HCLK prescaler 2 applied internally, complete with HCLK prescaler 1 */ + if(hpre == RCC_SYSCLK_DIV2) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1); + } + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by polling the FLASH_ACR register */ + tickstart = HAL_GetTick(); + + while (__HAL_FLASH_GET_LATENCY() != FLatency) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU); + + /* Configure the source of time base considering new system clocks settings*/ + return HAL_InitTick(uwTickPrio); +} + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + * @brief RCC clocks control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to: + + (+) Output clock to MCO pin. + (+) Retrieve current clock frequencies. + (+) Enable the Clock Security System. + +@endverbatim + * @{ + */ + +/** + * @brief Select the clock source to output on MCO pin(PA8/PG10). + * @note PA8/PG10 should be configured in alternate function mode. + * @note The default configuration of the GPIOG pin 10 (PG10) is set to reset mode (NRST pin) + * and user shall set the NRST_MODE Bit in the FLASH OPTR register to be able to use it + * as an MCO pin. + * The @ref HAL_FLASHEx_OBProgram() API can be used to configure the NRST_MODE Bit value. + * @param RCC_MCOx specifies the output direction for the clock source. + * For STM32G4xx family this parameter can have only one value: + * @arg @ref RCC_MCO_PA8 Clock source to output on MCO1 pin(PA8). + * @arg @ref RCC_MCO_PG10 Clock source to output on MCO1 pin(PG10). + * @param RCC_MCOSource specifies the clock source to output. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled, no clock on MCO + * @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLLCLK main PLL clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 + * @param RCC_MCODiv specifies the MCO prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 no division applied to MCO clock + * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock + * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock + * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock + * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock + * @retval None + */ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) +{ + GPIO_InitTypeDef gpio_initstruct; + uint32_t mcoindex; + uint32_t mco_gpio_index; + GPIO_TypeDef * mco_gpio_port; + + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCOx)); + + /* Common GPIO init parameters */ + gpio_initstruct.Mode = GPIO_MODE_AF_PP; + gpio_initstruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + gpio_initstruct.Pull = GPIO_NOPULL; + + /* Get MCOx selection */ + mcoindex = RCC_MCOx & RCC_MCO_INDEX_MASK; + + /* Get MCOx GPIO Port */ + mco_gpio_port = (GPIO_TypeDef *) RCC_GET_MCO_GPIO_PORT(RCC_MCOx); + + /* MCOx Clock Enable */ + mco_gpio_index = RCC_GET_MCO_GPIO_INDEX(RCC_MCOx); + SET_BIT(RCC->AHB2ENR, (1UL << mco_gpio_index )); + + /* Configure the MCOx pin in alternate function mode */ + gpio_initstruct.Pin = RCC_GET_MCO_GPIO_PIN(RCC_MCOx); + gpio_initstruct.Alternate = RCC_GET_MCO_GPIO_AF(RCC_MCOx); + HAL_GPIO_Init(mco_gpio_port, &gpio_initstruct); + + if (mcoindex == RCC_MCO1_INDEX) + { + assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), (RCC_MCOSource | RCC_MCODiv)); + } +} + +/** + * @brief Return the SYSCLK frequency. + * + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) + * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**), + * HSI_VALUE(*) Value multiplied/divided by the PLL factors. + * @note (*) HSI_VALUE is a constant defined in stm32g4xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSE_VALUE is a constant defined in stm32g4xx_hal_conf.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baudrate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + uint32_t pllvco, pllsource, pllr, pllm; + uint32_t sysclockfreq; + + if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) + { + /* HSI used as system clock source */ + sysclockfreq = HSI_VALUE; + } + else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) + { + /* HSE used as system clock source */ + sysclockfreq = HSE_VALUE; + } + else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) + { + /* PLL used as system clock source */ + + /* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); + pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; + + switch (pllsource) + { + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + break; + + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + default: + pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + break; + } + pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; + sysclockfreq = pllvco/pllr; + } + else + { + sysclockfreq = 0U; + } + + return sysclockfreq; +} + +/** + * @brief Return the HCLK frequency. + * @note Each time HCLK changes, this function must be called to update the + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. + * @retval HCLK frequency in Hz + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + return SystemCoreClock; +} + +/** + * @brief Return the PCLK1 frequency. + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU)); +} + +/** + * @brief Return the PCLK2 frequency. + * @note Each time PCLK2 changes, this function must be called to update the + * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK2 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU)); +} + +/** + * @brief Configure the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + /* Check the parameters */ + assert_param(RCC_OscInitStruct != (void *)NULL); + + /* Set all possible values for the Oscillator type parameter ---------------*/ + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | \ + RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48; + + /* Get the HSE configuration -----------------------------------------------*/ + if(READ_BIT(RCC->CR, RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + } + else if(READ_BIT(RCC->CR, RCC_CR_HSEON) == RCC_CR_HSEON) + { + RCC_OscInitStruct->HSEState = RCC_HSE_ON; + } + else + { + RCC_OscInitStruct->HSEState = RCC_HSE_OFF; + } + + /* Get the HSI configuration -----------------------------------------------*/ + if(READ_BIT(RCC->CR, RCC_CR_HSION) == RCC_CR_HSION) + { + RCC_OscInitStruct->HSIState = RCC_HSI_ON; + } + else + { + RCC_OscInitStruct->HSIState = RCC_HSI_OFF; + } + + RCC_OscInitStruct->HSICalibrationValue = READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos; + + /* Get the LSE configuration -----------------------------------------------*/ + if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + } + else if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON; + } + else + { + RCC_OscInitStruct->LSEState = RCC_LSE_OFF; + } + + /* Get the LSI configuration -----------------------------------------------*/ + if(READ_BIT(RCC->CSR, RCC_CSR_LSION) == RCC_CSR_LSION) + { + RCC_OscInitStruct->LSIState = RCC_LSI_ON; + } + else + { + RCC_OscInitStruct->LSIState = RCC_LSI_OFF; + } + + /* Get the HSI48 configuration ---------------------------------------------*/ + if(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON) + { + RCC_OscInitStruct->HSI48State = RCC_HSI48_ON; + } + else + { + RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF; + } + + /* Get the PLL configuration -----------------------------------------------*/ + if(READ_BIT(RCC->CR, RCC_CR_PLLON) == RCC_CR_PLLON) + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; + } + else + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; + } + RCC_OscInitStruct->PLL.PLLSource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); + RCC_OscInitStruct->PLL.PLLM = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U; + RCC_OscInitStruct->PLL.PLLN = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + RCC_OscInitStruct->PLL.PLLQ = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); + RCC_OscInitStruct->PLL.PLLR = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U) << 1U); + RCC_OscInitStruct->PLL.PLLP = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; +} + +/** + * @brief Configure the RCC_ClkInitStruct according to the internal + * RCC configuration registers. + * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that + * will be configured. + * @param pFLatency Pointer on the Flash Latency. + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +{ + /* Check the parameters */ + assert_param(RCC_ClkInitStruct != (void *)NULL); + assert_param(pFLatency != (void *)NULL); + + /* Set all possible values for the Clock type parameter --------------------*/ + RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + + /* Get the SYSCLK configuration --------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKSource = READ_BIT(RCC->CFGR, RCC_CFGR_SW); + + /* Get the HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_HPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1); + + /* Get the APB2 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB2CLKDivider = (READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> 3U); + + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = __HAL_FLASH_GET_LATENCY(); +} + +/** + * @brief Enable the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. + * @note The Clock Security System can only be cleared by reset. + * @retval None + */ +void HAL_RCC_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSON) ; +} + +/** + * @brief Enable the LSE Clock Security System. + * @note If a failure is detected on the external 32 kHz oscillator, + * the LSE clock is no longer supplied to the RTC but no hardware action + * is made to the registers. If enabled, an interrupt will be generated + * and handle through @ref RCCEx_EXTI_LINE_LSECSS + * @note The Clock Security System can only be cleared by reset or after a LSE failure detection. + * @retval None + */ +void HAL_RCC_EnableLSECSS(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; +} + +/** + * @brief Disable the LSE Clock Security System. + * @note After LSE failure detection, the software must disable LSECSSON + * @note The Clock Security System can only be cleared by reset otherwise. + * @retval None + */ +void HAL_RCC_DisableLSECSS(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; +} + +/** + * @brief Handle the RCC Clock Security System interrupt request. + * @note This API should be called under the NMI_Handler(). + * @retval None + */ +void HAL_RCC_NMI_IRQHandler(void) +{ + /* Check RCC CSSF interrupt flag */ + if(__HAL_RCC_GET_IT(RCC_IT_CSS)) + { + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_CSSCallback(); + + /* Clear RCC CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_CSS); + } +} + +/** + * @brief RCC Clock Security System interrupt callback. + * @retval none + */ +__weak void HAL_RCC_CSSCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RCC_CSSCallback should be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup RCC_Private_Functions + * @{ + */ + +/** + * @brief Compute SYSCLK frequency based on PLL SYSCLK source. + * @retval SYSCLK frequency + */ +static uint32_t RCC_GetSysClockFreqFromPLLSource(void) +{ + uint32_t pllvco, pllsource, pllr, pllm; + uint32_t sysclockfreq; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); + pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; + + switch (pllsource) + { + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + break; + + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + default: + pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + break; + } + + pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; + sysclockfreq = pllvco/pllr; + + return sysclockfreq; +} + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Mcu/g431/Inc/blutil.h b/Mcu/g431/Inc/blutil.h new file mode 100644 index 000000000..5ff1331aa --- /dev/null +++ b/Mcu/g431/Inc/blutil.h @@ -0,0 +1,145 @@ +/* + MCU specific utility functions for the bootloader + */ +/* + based on https://github.com/AlkaMotors/AM32_Bootloader_F051/blob/main/Core/ + */ +#pragma once + +#include + +#define GPIO_PIN(n) (1U<<(n)) + +#define GPIO_PULL_NONE LL_GPIO_PULL_NO +#define GPIO_PULL_UP LL_GPIO_PULL_UP +#define GPIO_PULL_DOWN LL_GPIO_PULL_DOWN + +#define GPIO_OUTPUT_PUSH_PULL LL_GPIO_OUTPUT_PUSHPULL + +static inline void gpio_mode_set_input(uint32_t pin, uint32_t pull_up_down) +{ + LL_GPIO_SetPinMode(input_port, pin, LL_GPIO_MODE_INPUT); + LL_GPIO_SetPinPull(input_port, pin, pull_up_down); +} + +static inline void gpio_mode_set_output(uint32_t pin, uint32_t output_mode) +{ + LL_GPIO_SetPinMode(input_port, pin, LL_GPIO_MODE_OUTPUT); + LL_GPIO_SetPinOutputType(input_port, pin, output_mode); +} + +static inline void gpio_set(uint32_t pin) +{ + LL_GPIO_SetOutputPin(input_port, pin); +} + +static inline void gpio_clear(uint32_t pin) +{ + LL_GPIO_ResetOutputPin(input_port, pin); +} + +static inline bool gpio_read(uint32_t pin) +{ + return LL_GPIO_IsInputPinSet(input_port, pin); +} + +#define BL_TIMER TIM2 + +/* + initialise timer for 1us per tick + */ +static inline void bl_timer_init(void) +{ + LL_TIM_InitTypeDef TIM_InitStruct = {0}; + + /* Peripheral clock enable */ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2); + + TIM_InitStruct.Prescaler = (160-1); // HSI PLL clock is 160Mz, want 1MHz timer + TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; + TIM_InitStruct.Autoreload = 0xFFFFFFFF; + TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; + LL_TIM_Init(BL_TIMER, &TIM_InitStruct); + LL_TIM_DisableARRPreload(BL_TIMER); + LL_TIM_SetClockSource(BL_TIMER, LL_TIM_CLOCKSOURCE_INTERNAL); + LL_TIM_SetTriggerOutput(BL_TIMER, LL_TIM_TRGO_RESET); + LL_TIM_DisableMasterSlaveMode(BL_TIMER); + + LL_TIM_SetCounterMode(BL_TIMER, LL_TIM_COUNTERMODE_UP); + LL_TIM_EnableCounter(BL_TIMER); +} + +/* + disable timer ready for app start + */ +static inline void bl_timer_disable(void) +{ + LL_TIM_DeInit(BL_TIMER); +} + +static inline uint32_t bl_timer_us(void) +{ + return LL_TIM_GetCounter(BL_TIMER); +} + +static inline void bl_timer_reset(void) +{ + LL_TIM_SetCounter(BL_TIMER, 0); +} + +/* + initialise clocks + */ +static inline void bl_clock_config(void) +{ + LL_FLASH_SetLatency(LL_FLASH_LATENCY_4); + while (LL_FLASH_GetLatency()!= LL_FLASH_LATENCY_4) ; + LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1); + while (LL_PWR_IsActiveFlag_VOS() != 0) ; + + LL_RCC_HSI_Enable(); + + /* Wait till HSI is ready */ + while (LL_RCC_HSI_IsReady() != 1) ; + + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, LL_RCC_PLLM_DIV_2, 40, LL_RCC_PLLR_DIV_2); + LL_RCC_PLL_EnableDomain_SYS(); + LL_RCC_PLL_Enable(); + + /* Wait till PLL is ready */ + while (LL_RCC_PLL_IsReady() != 1) ; + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); + + /* Wait till System clock is ready */ + while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) ; + + LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); + LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1); + LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1); +} + +static inline void bl_gpio_init(void) +{ + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA); + + GPIO_InitStruct.Pin = input_pin; + GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + + LL_GPIO_Init(input_port, &GPIO_InitStruct); +} + +/* + return true if the MCU booted under a software reset + */ +static inline bool bl_was_software_reset(void) +{ + return (RCC->CSR & RCC_CSR_SFTRSTF) != 0; +} + +void Error_Handler() +{ + while (1) {} +} diff --git a/Mcu/g431/Inc/main.h b/Mcu/g431/Inc/main.h index 6097d21c2..99cca86cc 100644 --- a/Mcu/g431/Inc/main.h +++ b/Mcu/g431/Inc/main.h @@ -75,23 +75,6 @@ void Error_Handler(void); /* USER CODE END EFP */ /* Private defines -----------------------------------------------------------*/ -#ifndef NVIC_PRIORITYGROUP_0 -#define NVIC_PRIORITYGROUP_0 \ - ((uint32_t)0x00000007) /*!< 0 bit for pre-emption priority, \ - 4 bits for subpriority */ -#define NVIC_PRIORITYGROUP_1 \ - ((uint32_t)0x00000006) /*!< 1 bit for pre-emption priority, \ - 3 bits for subpriority */ -#define NVIC_PRIORITYGROUP_2 \ - ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority, \ - 2 bits for subpriority */ -#define NVIC_PRIORITYGROUP_3 \ - ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority, \ - 1 bit for subpriority */ -#define NVIC_PRIORITYGROUP_4 \ - ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority, \ - 0 bit for subpriority */ -#endif /* USER CODE BEGIN Private defines */ diff --git a/Mcu/g431/Inc/stm32g4xx_hal_conf.h b/Mcu/g431/Inc/stm32g4xx_hal_conf.h new file mode 100644 index 000000000..b7b9d62c6 --- /dev/null +++ b/Mcu/g431/Inc/stm32g4xx_hal_conf.h @@ -0,0 +1,382 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32g4xx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration file + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G4xx_HAL_CONF_H +#define STM32G4xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ + +#define HAL_MODULE_ENABLED + + /*#define HAL_ADC_MODULE_ENABLED */ +/*#define HAL_COMP_MODULE_ENABLED */ +/*#define HAL_CORDIC_MODULE_ENABLED */ +/*#define HAL_CRC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_DAC_MODULE_ENABLED */ +#ifndef BOOTLOADER +#define HAL_FDCAN_MODULE_ENABLED +#endif +/*#define HAL_FMAC_MODULE_ENABLED */ +/*#define HAL_HRTIM_MODULE_ENABLED */ +/*#define HAL_IRDA_MODULE_ENABLED */ +/*#define HAL_IWDG_MODULE_ENABLED */ +/*#define HAL_I2C_MODULE_ENABLED */ +/*#define HAL_I2S_MODULE_ENABLED */ +/*#define HAL_LPTIM_MODULE_ENABLED */ +/*#define HAL_NAND_MODULE_ENABLED */ +/*#define HAL_NOR_MODULE_ENABLED */ +/*#define HAL_OPAMP_MODULE_ENABLED */ +/*#define HAL_PCD_MODULE_ENABLED */ +/*#define HAL_QSPI_MODULE_ENABLED */ +/*#define HAL_RNG_MODULE_ENABLED */ +/*#define HAL_RTC_MODULE_ENABLED */ +/*#define HAL_SAI_MODULE_ENABLED */ +/*#define HAL_SMARTCARD_MODULE_ENABLED */ +/*#define HAL_SMBUS_MODULE_ENABLED */ +/*#define HAL_SPI_MODULE_ENABLED */ +/*#define HAL_SRAM_MODULE_ENABLED */ +/*#define HAL_TIM_MODULE_ENABLED */ +/*#define HAL_UART_MODULE_ENABLED */ +/*#define HAL_USART_MODULE_ENABLED */ +/*#define HAL_WWDG_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## Register Callbacks selection ############################## */ +/** + * @brief This is the list of modules where register callback can be used + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U +#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U +#define USE_HAL_EXTI_REGISTER_CALLBACKS 0U +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U +#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U +#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U +#define USE_HAL_UART_REGISTER_CALLBACKS 0U +#define USE_HAL_USART_REGISTER_CALLBACKS 0U +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined (HSI48_VALUE) + #define HSI48_VALUE (48000000UL) /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz. + The real value my vary depending on manufacturing process variations.*/ +#endif /* HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) +/*!< Value of the Internal Low Speed oscillator in Hz +The real value may vary depending on the variations in voltage and temperature.*/ +#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) +#define LSE_VALUE (32768UL) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S and SAI peripherals + * This value is used by the I2S and SAI HAL modules to compute the I2S and SAI clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE (12288000UL) /*!< Value of the External oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ + +#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver + * Activated: CRC code is present inside driver + * Deactivated: CRC code cleaned from driver + */ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED +#include "stm32g4xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32g4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED +#include "stm32g4xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED +#include "stm32g4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED +#include "stm32g4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED +#include "stm32g4xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CORDIC_MODULE_ENABLED +#include "stm32g4xx_hal_cordic.h" +#endif /* HAL_CORDIC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED +#include "stm32g4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED +#include "stm32g4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED +#include "stm32g4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED +#include "stm32g4xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FDCAN_MODULE_ENABLED +#include "stm32g4xx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED +#include "stm32g4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_FMAC_MODULE_ENABLED +#include "stm32g4xx_hal_fmac.h" +#endif /* HAL_FMAC_MODULE_ENABLED */ + +#ifdef HAL_HRTIM_MODULE_ENABLED +#include "stm32g4xx_hal_hrtim.h" +#endif /* HAL_HRTIM_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED +#include "stm32g4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED +#include "stm32g4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED +#include "stm32g4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED +#include "stm32g4xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32g4xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED +#include "stm32g4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED +#include "stm32g4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_OPAMP_MODULE_ENABLED +#include "stm32g4xx_hal_opamp.h" +#endif /* HAL_OPAMP_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED +#include "stm32g4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED +#include "stm32g4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED +#include "stm32g4xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED +#include "stm32g4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED +#include "stm32g4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED +#include "stm32g4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED +#include "stm32g4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED +#include "stm32g4xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED +#include "stm32g4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED +#include "stm32g4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED +#include "stm32g4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED +#include "stm32g4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED +#include "stm32g4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED +#include "stm32g4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G4xx_HAL_CONF_H */ diff --git a/Mcu/g431/Src/eeprom.c b/Mcu/g431/Src/eeprom.c index 79afeaee5..c1f46d8fa 100644 --- a/Mcu/g431/Src/eeprom.c +++ b/Mcu/g431/Src/eeprom.c @@ -10,7 +10,7 @@ #include -#define page_size 0x800 // 2 kb for g071 +#define page_size 0x800 // 2 kb for g431 uint32_t FLASH_FKEY1 = 0x45670123; uint32_t FLASH_FKEY2 = 0xCDEF89AB; diff --git a/Mcu/g431/Src/stm32g4xx_it.c b/Mcu/g431/Src/stm32g4xx_it.c index b82363912..6da298229 100644 --- a/Mcu/g431/Src/stm32g4xx_it.c +++ b/Mcu/g431/Src/stm32g4xx_it.c @@ -1,146 +1,196 @@ - -#include "stm32g4xx_it.h" -#include "ADC.h" -#include "IO.h" -#include "WS2812.h" +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32g4xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ #include "main.h" -#include "targets.h" +#include "stm32g4xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ -extern void transfercomplete(); -extern void PeriodElapsedCallback(); -extern void interruptRoutine(); -extern void tenKhzRoutine(); -extern void processDshot(); +/* USER CODE END 0 */ -extern char send_telemetry; -int interrupt_time = 0; -extern char servoPwm; -extern char dshot_telemetry; -extern char armed; -extern char out_put; -extern uint8_t compute_dshot_flag; +/* External variables --------------------------------------------------------*/ -int interrupt = 0; +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M4 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ void NMI_Handler(void) { - while (1) { - } + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ } +/** + * @brief This function handles Hard fault interrupt. + */ void HardFault_Handler(void) { - while (1) { - } + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } } +/** + * @brief This function handles Memory management fault. + */ void MemManage_Handler(void) { - while (1) { - } + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } } +/** + * @brief This function handles Prefetch fault, memory access fault. + */ void BusFault_Handler(void) { - while (1) { - } + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } } +/** + * @brief This function handles Undefined instruction or illegal state. + */ void UsageFault_Handler(void) { - while (1) { - } + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } } -void SVC_Handler(void) { } - -void DebugMon_Handler(void) { } - -void PendSV_Handler(void) { } +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ -void SysTick_Handler(void) { } + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ -void DMA1_Channel1_IRQHandler(void) -{ - if (armed && dshot_telemetry) { - DMA1->IFCR |= DMA_IFCR_CGIF1; - DMA1_Channel1->CCR = 0x00; - if (out_put) { - receiveDshotDma(); - compute_dshot_flag = 2; - } else { - sendDshotDma(); - compute_dshot_flag = 1; - } - EXTI->SWIER1 |= LL_EXTI_LINE_15; - - return; - } - /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ - if (LL_DMA_IsActiveFlag_HT1(DMA1)) { - if (servoPwm) { - LL_TIM_IC_SetPolarity(IC_TIMER_REGISTER, IC_TIMER_CHANNEL, - LL_TIM_IC_POLARITY_FALLING); - LL_DMA_ClearFlag_HT1(DMA1); - } - } - if (LL_DMA_IsActiveFlag_TC1(DMA1) == 1) { - DMA1->IFCR |= DMA_IFCR_CGIF1; - DMA1_Channel1->CCR = 0x00; - transfercomplete(); - EXTI->SWIER1 |= LL_EXTI_LINE_15; - } else if (LL_DMA_IsActiveFlag_TE1(DMA1) == 1) { - LL_DMA_ClearFlag_GI1(DMA1); - } + /* USER CODE END SVCall_IRQn 1 */ } -void COMP1_2_3_IRQHandler(void) +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) { - interrupt++; - if (LL_EXTI_IsActiveFlag_0_31(LL_EXTI_LINE_22)) { - LL_EXTI_ClearFlag_0_31(LL_EXTI_LINE_22); - interruptRoutine(); - return; - } - - if (LL_EXTI_IsActiveFlag_0_31(LL_EXTI_LINE_21)) { - LL_EXTI_ClearFlag_0_31(LL_EXTI_LINE_21); - interruptRoutine(); - return; - } -} + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ -void TIM6_DAC_IRQHandler(void) -{ - if (LL_TIM_IsActiveFlag_UPDATE(TIM6) == 1) { - LL_TIM_ClearFlag_UPDATE(TIM6); - tenKhzRoutine(); - } + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ } -void TIM1_UP_TIM16_IRQHandler(void) +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) { - PeriodElapsedCallback(); - LL_TIM_ClearFlag_UPDATE(TIM16); + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ } -void EXTI15_10_IRQHandler(void) +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) { - LL_EXTI_ClearFlag_0_31(LL_EXTI_LINE_15); - processDshot(); } -void DMA1_Channel3_IRQHandler(void) -{ - if (LL_DMA_IsActiveFlag_TC3(DMA1)) { - send_telemetry = 0; - LL_DMA_ClearFlag_GI3(DMA1); - LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_3); - /* Call function Transmission complete Callback */ - } else if (LL_DMA_IsActiveFlag_TE3(DMA1)) { - LL_DMA_ClearFlag_GI3(DMA1); - LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_3); - /* Call Error function */ - // USART_TransferError_Callback(); - } -} \ No newline at end of file +/******************************************************************************/ +/* STM32G4xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32g4xx.s). */ +/******************************************************************************/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Mcu/g431/Src/system_stm32g4xx.c b/Mcu/g431/Src/system_stm32g4xx.c index b4d2dfdda..47a32303f 100644 --- a/Mcu/g431/Src/system_stm32g4xx.c +++ b/Mcu/g431/Src/system_stm32g4xx.c @@ -236,37 +236,23 @@ void SystemCoreClockUpdate(void) { uint32_t tmp, pllvco, pllr, pllsource, pllm; - /* Get SYSCLK source -------------------------------------------------------*/ - switch (RCC->CFGR & RCC_CFGR_SWS) { - case 0x04: /* HSI used as system clock source */ - SystemCoreClock = HSI_VALUE; - break; - - case 0x08: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; - - case 0x0C: /* PLL used as system clock source */ - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN - SYSCLK = PLL_VCO / PLLR - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); - pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U; - if (pllsource == 0x02UL) /* HSI used as PLL clock source */ - { - pllvco = (HSI_VALUE / pllm); - } else /* HSE used as PLL clock source */ - { - pllvco = (HSE_VALUE / pllm); - } - pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8); - pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U; - SystemCoreClock = pllvco / pllr; - break; - - default: - break; + /* PLL used as system clock source */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U; + if (pllsource == 0x02UL) /* HSI used as PLL clock source */ + { + pllvco = (HSI_VALUE / pllm); + } else /* HSE used as PLL clock source */ + { + pllvco = (HSE_VALUE / pllm); } + pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8); + pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U; + SystemCoreClock = pllvco / pllr; + /* Compute HCLK clock frequency --------------------------------------------*/ /* Get HCLK prescaler */ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; diff --git a/Mcu/g431/Startup/startup_stm32g431xx.s b/Mcu/g431/Startup/startup_stm32g431xx.s new file mode 100644 index 000000000..741b53350 --- /dev/null +++ b/Mcu/g431/Startup/startup_stm32g431xx.s @@ -0,0 +1,515 @@ +/** + ****************************************************************************** + * @file startup_stm32g431xx.s + * @author MCD Application Team + * @brief STM32G431xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +Default_Handler2: +Infinite_Loop2: + b Infinite_Loop2 + .size Default_Handler2, .-Default_Handler2 + +Default_Handler3: +Infinite_Loop3: + b Infinite_Loop3 + .size Default_Handler3, .-Default_Handler3 + +Default_Handler4: +Infinite_Loop4: + b Infinite_Loop4 + .size Default_Handler4, .-Default_Handler4 + + +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_PVM_IRQHandler + .word RTC_TAMP_LSECSS_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word 0 + .word ADC1_2_IRQHandler + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word FDCAN1_IT0_IRQHandler + .word FDCAN1_IT1_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USBWakeUp_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word 0 + .word 0 + .word LPTIM1_IRQHandler + .word 0 + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word 0 + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word 0 + .word 0 + .word UCPD1_IRQHandler + .word COMP1_2_3_IRQHandler + .word COMP4_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word CRS_IRQHandler + .word SAI1_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word FPU_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word RNG_IRQHandler + .word LPUART1_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word DMAMUX_OVR_IRQHandler + .word 0 + .word 0 + .word DMA2_Channel6_IRQHandler + .word 0 + .word 0 + .word CORDIC_IRQHandler + .word FMAC_IRQHandler + + .size g_pfnVectors, .-g_pfnVectors + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler3 + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler3 + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler4 + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler3 + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler3 + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler2 + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler2 + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler2 + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + +// .weak SysTick_Handler +// .thumb_set SysTick_Handler,Default_Handler3 + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak RTC_TAMP_LSECSS_IRQHandler + .thumb_set RTC_TAMP_LSECSS_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler2 + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler2 + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler2 + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler2 + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler2 + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler2 + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler2 + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler2 + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler2 + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler2 + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler2 + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler2 + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler2 + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler2 + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler2 + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler2 + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler2 + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler2 + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler2 + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler2 + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler2 + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler2 + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler2 + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler2 + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler2 + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler2 + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler2 + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler2 + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler2 + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler2 + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler2 + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler2 + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler2 + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler2 + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler2 + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler2 + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler2 + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler2 + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler2 + + .weak UCPD1_IRQHandler + .thumb_set UCPD1_IRQHandler,Default_Handler2 + + .weak COMP1_2_3_IRQHandler + .thumb_set COMP1_2_3_IRQHandler,Default_Handler2 + + .weak COMP4_IRQHandler + .thumb_set COMP4_IRQHandler,Default_Handler2 + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler2 + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler2 + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler2 + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler2 + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler2 + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler2 + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler2 + + .weak DMAMUX_OVR_IRQHandler + .thumb_set DMAMUX_OVR_IRQHandler,Default_Handler2 + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak CORDIC_IRQHandler + .thumb_set CORDIC_IRQHandler,Default_Handler + + .weak FMAC_IRQHandler + .thumb_set FMAC_IRQHandler,Default_Handler + diff --git a/bootloader/main.c b/bootloader/main.c index 656853f4f..e2abd0df7 100644 --- a/bootloader/main.c +++ b/bootloader/main.c @@ -8,11 +8,6 @@ #include -#if !defined(USE_PA2) && !defined(USE_PB4) -//#define USE_PB4 -#define USE_PA2 -#endif - /* Includes ------------------------------------------------------------------*/ #include #include @@ -23,6 +18,10 @@ //#define USE_ADC_INPUT // will go right to application and ignore eeprom //#define UPDATE_EEPROM_ENABLE +// use this to check the clock config for the MCU (with a logic +// analyser on the input pin) +//#define BOOTLOADER_TEST_CLOCK + #include #define STM32_FLASH_START 0x08000000 @@ -34,7 +33,6 @@ #define EEPROM_RELATIVE_START 0x7c00 #endif - typedef void (*pFunction)(void); #define APPLICATION_ADDRESS (uint32_t)(STM32_FLASH_START + FIRMWARE_RELATIVE_START) // 4k @@ -57,25 +55,29 @@ typedef void (*pFunction)(void); #define CMD_SET_ADDRESS 0xFF #define CMD_SET_BUFFER 0xFE - #ifdef USE_PA2 -#define input_pin GPIO_PINS_2 +#define input_pin GPIO_PIN(2) #define input_port GPIOA #define PIN_NUMBER 2 #define PORT_LETTER 0 -#endif - -#ifdef USE_PB4 -#define input_pin GPIO_PINS_4 +#elif defined(USE_PB4) +#define input_pin GPIO_PIN(4) #define input_port GPIOB #define PIN_NUMBER 4 #define PORT_LETTER 1 +#elif defined(USE_PA15) +#define input_pin GPIO_PIN(15) +#define input_port GPIOA +#define PIN_NUMBER 15 +#define PORT_LETTER 0 +#else +#error "Bootloader comms pin not defined" #endif #include static uint16_t low_pin_count; -static char receviedByte; +static char receiveByte; static int count; static char messagereceived; static uint16_t invalid_command; @@ -115,11 +117,11 @@ static pFunction JumpToApplication; /* USER CODE BEGIN PFP */ static void serialwriteChar(char data); static void sendString(uint8_t data[], int len); -static void recieveBuffer(); +static void receiveBuffer(); -#define BAUDRATE 19200 -#define BITTIME 1000000/BAUDRATE -#define HALFBITTIME 500000/BAUDRATE +#define BAUDRATE 19200 +#define BITTIME 52 // 1000000/BAUDRATE +#define HALFBITTIME 26 // 500000/BAUDRATE static void delayMicroseconds(uint32_t micros) { @@ -458,7 +460,7 @@ static void serialreadChar() delayMicroseconds(HALFBITTIME); //wait till the stop bit time begins messagereceived = 1; - receviedByte = rxbyte; + receiveByte = rxbyte; } @@ -492,7 +494,7 @@ static void sendString(uint8_t *data, int len) } } -static void recieveBuffer() +static void receiveBuffer() { count = 0; messagereceived = 0; @@ -550,7 +552,6 @@ static void checkForSignal() if(!gpio_read(input_pin)){ low_pin_count++; }else{ - } delayMicroseconds(10); @@ -599,14 +600,36 @@ static void checkForSignal() } } +#ifdef BOOTLOADER_TEST_CLOCK +/* + this should provide a 2ms low followed by a 1ms high if the clock is correct + */ +static void test_clock(void) +{ + setTransmit(); + while (1) { + gpio_clear(input_pin); + bl_timer_reset(); + while (bl_timer_us() < 2000) ; + gpio_set(input_pin); + bl_timer_reset(); + while (bl_timer_us() < 1000) ; + } +} +#endif // BOOTLOADER_TEST_CLOCK + int main(void) { bl_clock_config(); bl_timer_init(); bl_gpio_init(); +#ifdef BOOTLOADER_TEST_CLOCK + test_clock(); +#endif + checkForSignal(); - + gpio_mode_set_input(input_pin, GPIO_PULL_NONE); #ifdef USE_ADC_INPUT // go right to application @@ -620,7 +643,7 @@ int main(void) #endif while (1) { - recieveBuffer(); + receiveBuffer(); if (invalid_command > 100) { jump(); } diff --git a/g431makefile.mk b/g431makefile.mk index 2d5be0682..a0f86eaec 100644 --- a/g431makefile.mk +++ b/g431makefile.mk @@ -1,34 +1,36 @@ +MCU := G431 +PART := STM32G431xx -TARGETS_G431 := $(call get_targets,G431) +TARGETS_$(MCU) := $(call get_targets,$(MCU)) -HAL_FOLDER_G431 := $(HAL_FOLDER)/g431 +HAL_FOLDER_$(MCU) := $(HAL_FOLDER)/g431 -MCU_G431 := -mcpu=cortex-m0 -mthumb -LDSCRIPT_G431 := $(HAL_FOLDER_G431)/STM32G431CBUX_FLASH.ld +MCU_$(MCU) := -mcpu=cortex-m4 -mthumb +LDSCRIPT_$(MCU) := $(wildcard $(HAL_FOLDER_$(MCU))/*.ld) -SRC_DIR_G431 := \ - $(HAL_FOLDER_G431)/Startup \ - $(HAL_FOLDER_G431)/Src \ - $(HAL_FOLDER_G431)/Drivers/STM32G4xx_HAL_Driver/Src +SRC_BASE_DIR_$(MCU) := \ + $(HAL_FOLDER_$(MCU))/Startup \ + $(HAL_FOLDER_$(MCU))/Drivers/STM32G4xx_HAL_Driver/Src -CFLAGS_G431 := \ - -I$(HAL_FOLDER_G431)/Inc \ - -I$(HAL_FOLDER_G431)/Drivers/STM32G4xx_HAL_Driver/Inc \ - -I$(HAL_FOLDER_G431)/Drivers/CMSIS/Include \ - -I$(HAL_FOLDER_G431)/Drivers/CMSIS/Device/ST/STM32G4xx/Include +SRC_DIR_$(MCU) := \ + $(SRC_BASE_DIR_$(MCU)) \ + $(HAL_FOLDER_$(MCU))/Src -CFLAGS_G431 += \ +CFLAGS_$(MCU) := \ + -I$(HAL_FOLDER_$(MCU))/Inc \ + -I$(HAL_FOLDER_$(MCU))/Drivers/STM32G4xx_HAL_Driver/Inc \ + -I$(HAL_FOLDER_$(MCU))/Drivers/CMSIS/Include \ + -I$(HAL_FOLDER_$(MCU))/Drivers/CMSIS/Device/ST/STM32G4xx/Include + +CFLAGS_$(MCU) += \ -DHSE_VALUE=8000000 \ - -DSTM32G431xx \ + -D$(PART) \ -DHSE_STARTUP_TIMEOUT=100 \ -DLSE_STARTUP_TIMEOUT=5000 \ - -DLSE_VALUE=32768 \ - -DDATA_CACHE_ENABLE=1 \ - -DINSTRUCTION_CACHE_ENABLE=0 \ - -DVDD_VALUE=3300 \ - -DLSI_VALUE=32000 \ - -DHSI_VALUE=16000000 \ - -DUSE_FULL_LL_DRIVER \ - -DPREFETCH_ENABLE=1 - -SRC_G431 := $(foreach dir,$(SRC_DIR_G431),$(wildcard $(dir)/*.[cs])) + -DUSE_FULL_LL_DRIVER + +SRC_$(MCU) := $(foreach dir,$(SRC_DIR_$(MCU)),$(wildcard $(dir)/*.[cs])) +SRC_$(MCU)_BL := $(foreach dir,$(SRC_BASE_DIR_$(MCU)),$(wildcard $(dir)/*.[cs])) \ + $(HAL_FOLDER_$(MCU))/Src/eeprom.c \ + $(HAL_FOLDER_$(MCU))/Src/system_stm32g4xx.c \ + $(wildcard $(HAL_FOLDER_$(MCU))/Src/*_it.c) From 79e34334ae4cc41874b1dadfb2a2ea2b202a2d72 Mon Sep 17 00:00:00 2001 From: Andrew Tridgell Date: Mon, 29 Jul 2024 13:27:15 +1000 Subject: [PATCH 11/11] l431: added bootloader --- Makefile | 4 +- .../STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c | 765 ------ .../Src/stm32l4xx_hal_can.c | 2437 ----------------- Mcu/l431/Inc/blutil.h | 135 + Mcu/l431/STM32L431KCUX_FLASH.ld | 187 ++ Mcu/l431/Src/stm32l4xx_it.c | 5 + Mcu/l431/Startup/startup_stm32l431xx.s | 846 +++--- Mcu/l431/openocd.cfg | 7 + bootloader/main.c | 5 + l431makefile.mk | 44 + 10 files changed, 844 insertions(+), 3591 deletions(-) delete mode 100644 Mcu/l431/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c delete mode 100644 Mcu/l431/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c create mode 100644 Mcu/l431/Inc/blutil.h create mode 100644 Mcu/l431/STM32L431KCUX_FLASH.ld create mode 100644 Mcu/l431/openocd.cfg create mode 100644 l431makefile.mk diff --git a/Makefile b/Makefile index 9d60bb085..67f58921e 100644 --- a/Makefile +++ b/Makefile @@ -23,12 +23,12 @@ ROOT := $(patsubst %/,%,$(dir $(lastword $(MAKEFILE_LIST)))) include $(ROOT)/make/tools.mk # supported MCU types -MCU_TYPES := E230 F031 F051 F415 F421 G071 G431 +MCU_TYPES := E230 F031 F051 F415 F421 G071 G431 L431 MCU_TYPE := NONE # MCU types that we build a bootloader for - this should be $(MCU_TYPES) in the future # when all bootloader porting is completed -BL_MCU_TYPES := E230 F031 F051 F415 F421 G071 G431 +BL_MCU_TYPES := E230 F031 F051 F415 F421 G071 G431 L431 # Function to include makefile for each MCU type define INCLUDE_MCU_MAKEFILES diff --git a/Mcu/l431/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c b/Mcu/l431/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c deleted file mode 100644 index 87385fc50..000000000 --- a/Mcu/l431/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c +++ /dev/null @@ -1,765 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal.c - * @author MCD Application Team - * @brief HAL module driver. - * This is the common part of the HAL initialization - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The common HAL driver contains a set of generic and common APIs that can be - used by the PPP peripheral drivers and the user to start using the HAL. - [..] - The HAL contains two APIs' categories: - (+) Common HAL APIs - (+) Services HAL APIs - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup HAL HAL - * @brief HAL module driver - * @{ - */ - -#ifdef HAL_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** - * @brief STM32L4xx HAL Driver version number - */ -#define STM32L4XX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define STM32L4XX_HAL_VERSION_SUB1 (0x0DU) /*!< [23:16] sub1 version */ -#define STM32L4XX_HAL_VERSION_SUB2 (0x04U) /*!< [15:8] sub2 version */ -#define STM32L4XX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ -#define STM32L4XX_HAL_VERSION ((STM32L4XX_HAL_VERSION_MAIN << 24U)\ - |(STM32L4XX_HAL_VERSION_SUB1 << 16U)\ - |(STM32L4XX_HAL_VERSION_SUB2 << 8U)\ - |(STM32L4XX_HAL_VERSION_RC)) - -#if defined(VREFBUF) -#define VREFBUF_TIMEOUT_VALUE 10U /* 10 ms (to be confirmed) */ -#endif /* VREFBUF */ - -/* ------------ SYSCFG registers bit address in the alias region ------------ */ -#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) -/* --- MEMRMP Register ---*/ -/* Alias word address of FB_MODE bit */ -#define MEMRMP_OFFSET SYSCFG_OFFSET -#define FB_MODE_BitNumber 8U -#define FB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32U) + (FB_MODE_BitNumber * 4U)) - -/* --- SCSR Register ---*/ -/* Alias word address of SRAM2ER bit */ -#define SCSR_OFFSET (SYSCFG_OFFSET + 0x18U) -#define BRER_BitNumber 0U -#define SCSR_SRAM2ER_BB (PERIPH_BB_BASE + (SCSR_OFFSET * 32U) + (BRER_BitNumber * 4U)) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - -/* Exported variables --------------------------------------------------------*/ - -/** @defgroup HAL_Exported_Variables HAL Exported Variables - * @{ - */ -__IO uint32_t uwTick; -uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid priority */ -HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup HAL_Exported_Functions HAL Exported Functions - * @{ - */ - -/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions - * @brief Initialization and de-initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize the Flash interface, the NVIC allocation and initial time base - clock configuration. - (+) De-initialize common part of the HAL. - (+) Configure the time base source to have 1ms time base with a dedicated - Tick interrupt priority. - (++) SysTick timer is used by default as source of time base, but user - can eventually implement his proper time base source (a general purpose - timer for example or other time source), keeping in mind that Time base - duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and - handled in milliseconds basis. - (++) Time base configuration function (HAL_InitTick ()) is called automatically - at the beginning of the program after reset by HAL_Init() or at any time - when clock is configured, by HAL_RCC_ClockConfig(). - (++) Source of time base is configured to generate interrupts at regular - time intervals. Care must be taken if HAL_Delay() is called from a - peripheral ISR process, the Tick interrupt line must have higher priority - (numerically lower) than the peripheral interrupt. Otherwise the caller - ISR process will be blocked. - (++) functions affecting time base configurations are declared as __weak - to make override possible in case of other implementations in user file. -@endverbatim - * @{ - */ - -/** - * @brief Configure the Flash prefetch, the Instruction and Data caches, - * the time base source, NVIC and any required global low level hardware - * by calling the HAL_MspInit() callback function to be optionally defined in user file - * stm32l4xx_hal_msp.c. - * - * @note HAL_Init() function is called at the beginning of program after reset and before - * the clock configuration. - * - * @note In the default implementation the System Timer (Systick) is used as source of time base. - * The Systick configuration is based on MSI clock, as MSI is the clock - * used after a system Reset and the NVIC configuration is set to Priority group 4. - * Once done, time base tick starts incrementing: the tick variable counter is incremented - * each 1ms in the SysTick_Handler() interrupt handler. - * - * @retval HAL status - */ -HAL_StatusTypeDef HAL_Init(void) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Configure Flash prefetch, Instruction cache, Data cache */ - /* Default configuration at reset is: */ - /* - Prefetch disabled */ - /* - Instruction cache enabled */ - /* - Data cache enabled */ -#if (INSTRUCTION_CACHE_ENABLE == 0) - __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); -#endif /* INSTRUCTION_CACHE_ENABLE */ - -#if (DATA_CACHE_ENABLE == 0) - __HAL_FLASH_DATA_CACHE_DISABLE(); -#endif /* DATA_CACHE_ENABLE */ - -#if (PREFETCH_ENABLE != 0) - __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); -#endif /* PREFETCH_ENABLE */ - - /* Set Interrupt Group Priority */ - HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); - - /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */ - if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) - { - status = HAL_ERROR; - } - else - { - /* Init the low level hardware */ - HAL_MspInit(); - } - - /* Return function status */ - return status; -} - -/** - * @brief De-initialize common part of the HAL and stop the source of time base. - * @note This function is optional. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DeInit(void) -{ - /* Reset of all peripherals */ - __HAL_RCC_APB1_FORCE_RESET(); - __HAL_RCC_APB1_RELEASE_RESET(); - - __HAL_RCC_APB2_FORCE_RESET(); - __HAL_RCC_APB2_RELEASE_RESET(); - - __HAL_RCC_AHB1_FORCE_RESET(); - __HAL_RCC_AHB1_RELEASE_RESET(); - - __HAL_RCC_AHB2_FORCE_RESET(); - __HAL_RCC_AHB2_RELEASE_RESET(); - - __HAL_RCC_AHB3_FORCE_RESET(); - __HAL_RCC_AHB3_RELEASE_RESET(); - - /* De-Init the low level hardware */ - HAL_MspDeInit(); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initialize the MSP. - * @retval None - */ -__weak void HAL_MspInit(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize the MSP. - * @retval None - */ -__weak void HAL_MspDeInit(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief This function configures the source of the time base: - * The time source is configured to have 1ms time base with a dedicated - * Tick interrupt priority. - * @note This function is called automatically at the beginning of program after - * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). - * @note In the default implementation, SysTick timer is the source of time base. - * It is used to generate interrupts at regular time intervals. - * Care must be taken if HAL_Delay() is called from a peripheral ISR process, - * The SysTick interrupt must have higher priority (numerically lower) - * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. - * The function is declared as __weak to be overwritten in case of other - * implementation in user file. - * @param TickPriority Tick interrupt priority. - * @retval HAL status - */ -__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/ - if ((uint32_t)uwTickFreq != 0U) - { - /*Configure the SysTick to have interrupt in 1ms time basis*/ - if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / (uint32_t)uwTickFreq)) == 0U) - { - /* Configure the SysTick IRQ priority */ - if (TickPriority < (1UL << __NVIC_PRIO_BITS)) - { - HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); - uwTickPrio = TickPriority; - } - else - { - status = HAL_ERROR; - } - } - else - { - status = HAL_ERROR; - } - } - else - { - status = HAL_ERROR; - } - - /* Return function status */ - return status; -} - -/** - * @} - */ - -/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions - * @brief HAL Control functions - * -@verbatim - =============================================================================== - ##### HAL Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Provide a tick value in millisecond - (+) Provide a blocking delay in millisecond - (+) Suspend the time base source interrupt - (+) Resume the time base source interrupt - (+) Get the HAL API driver version - (+) Get the device identifier - (+) Get the device revision identifier - -@endverbatim - * @{ - */ - -/** - * @brief This function is called to increment a global variable "uwTick" - * used as application time base. - * @note In the default implementation, this variable is incremented each 1ms - * in SysTick ISR. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_IncTick(void) -{ - uwTick += (uint32_t)uwTickFreq; -} - -/** - * @brief Provide a tick value in millisecond. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval tick value - */ -__weak uint32_t HAL_GetTick(void) -{ - return uwTick; -} - -/** - * @brief This function returns a tick priority. - * @retval tick priority - */ -uint32_t HAL_GetTickPrio(void) -{ - return uwTickPrio; -} - -/** - * @brief Set new tick Freq. - * @param Freq tick frequency - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) -{ - HAL_StatusTypeDef status = HAL_OK; - HAL_TickFreqTypeDef prevTickFreq; - - if (uwTickFreq != Freq) - { - /* Back up uwTickFreq frequency */ - prevTickFreq = uwTickFreq; - - /* Update uwTickFreq global variable used by HAL_InitTick() */ - uwTickFreq = Freq; - - /* Apply the new tick Freq */ - status = HAL_InitTick(uwTickPrio); - if (status != HAL_OK) - { - /* Restore previous tick frequency */ - uwTickFreq = prevTickFreq; - } - } - - return status; -} - -/** - * @brief Return tick frequency. - * @retval Tick frequency. - * Value of @ref HAL_TickFreqTypeDef. - */ -HAL_TickFreqTypeDef HAL_GetTickFreq(void) -{ - return uwTickFreq; -} - -/** - * @brief This function provides minimum delay (in milliseconds) based - * on variable incremented. - * @note In the default implementation , SysTick timer is the source of time base. - * It is used to generate interrupts at regular time intervals where uwTick - * is incremented. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @param Delay specifies the delay time length, in milliseconds. - * @retval None - */ -__weak void HAL_Delay(uint32_t Delay) -{ - uint32_t tickstart = HAL_GetTick(); - uint32_t wait = Delay; - - /* Add a period to guaranty minimum wait */ - if (wait < HAL_MAX_DELAY) - { - wait += (uint32_t)uwTickFreq; - } - - while ((HAL_GetTick() - tickstart) < wait) - { - } -} - -/** - * @brief Suspend Tick increment. - * @note In the default implementation , SysTick timer is the source of time base. It is - * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() - * is called, the SysTick interrupt will be disabled and so Tick increment - * is suspended. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_SuspendTick(void) -{ - /* Disable SysTick Interrupt */ - SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; -} - -/** - * @brief Resume Tick increment. - * @note In the default implementation , SysTick timer is the source of time base. It is - * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() - * is called, the SysTick interrupt will be enabled and so Tick increment - * is resumed. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_ResumeTick(void) -{ - /* Enable SysTick Interrupt */ - SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; -} - -/** - * @brief Return the HAL revision. - * @retval version : 0xXYZR (8bits for each decimal, R for RC) - */ -uint32_t HAL_GetHalVersion(void) -{ - return STM32L4XX_HAL_VERSION; -} - -/** - * @brief Return the device revision identifier. - * @retval Device revision identifier - */ -uint32_t HAL_GetREVID(void) -{ - return((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16); -} - -/** - * @brief Return the device identifier. - * @retval Device identifier - */ -uint32_t HAL_GetDEVID(void) -{ - return(DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID); -} - -/** - * @brief Return the first word of the unique device identifier (UID based on 96 bits) - * @retval Device identifier - */ -uint32_t HAL_GetUIDw0(void) -{ - return(READ_REG(*((uint32_t *)UID_BASE))); -} - -/** - * @brief Return the second word of the unique device identifier (UID based on 96 bits) - * @retval Device identifier - */ -uint32_t HAL_GetUIDw1(void) -{ - return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); -} - -/** - * @brief Return the third word of the unique device identifier (UID based on 96 bits) - * @retval Device identifier - */ -uint32_t HAL_GetUIDw2(void) -{ - return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); -} - -/** - * @} - */ - -/** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions - * @brief HAL Debug functions - * -@verbatim - =============================================================================== - ##### HAL Debug functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Enable/Disable Debug module during SLEEP mode - (+) Enable/Disable Debug module during STOP0/STOP1/STOP2 modes - (+) Enable/Disable Debug module during STANDBY mode - -@endverbatim - * @{ - */ - -/** - * @brief Enable the Debug Module during SLEEP mode. - * @retval None - */ -void HAL_DBGMCU_EnableDBGSleepMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); -} - -/** - * @brief Disable the Debug Module during SLEEP mode. - * @retval None - */ -void HAL_DBGMCU_DisableDBGSleepMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); -} - -/** - * @brief Enable the Debug Module during STOP0/STOP1/STOP2 modes. - * @retval None - */ -void HAL_DBGMCU_EnableDBGStopMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Disable the Debug Module during STOP0/STOP1/STOP2 modes. - * @retval None - */ -void HAL_DBGMCU_DisableDBGStopMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Enable the Debug Module during STANDBY mode. - * @retval None - */ -void HAL_DBGMCU_EnableDBGStandbyMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @brief Disable the Debug Module during STANDBY mode. - * @retval None - */ -void HAL_DBGMCU_DisableDBGStandbyMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @} - */ - -/** @defgroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions - * @brief HAL SYSCFG configuration functions - * -@verbatim - =============================================================================== - ##### HAL SYSCFG configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Start a hardware SRAM2 erase operation - (+) Enable/Disable the Internal FLASH Bank Swapping - (+) Configure the Voltage reference buffer - (+) Enable/Disable the Voltage reference buffer - (+) Enable/Disable the I/O analog switch voltage booster - -@endverbatim - * @{ - */ - -/** - * @brief Start a hardware SRAM2 erase operation. - * @note As long as SRAM2 is not erased the SRAM2ER bit will be set. - * This bit is automatically reset at the end of the SRAM2 erase operation. - * @retval None - */ -void HAL_SYSCFG_SRAM2Erase(void) -{ - /* unlock the write protection of the SRAM2ER bit */ - SYSCFG->SKR = 0xCA; - SYSCFG->SKR = 0x53; - /* Starts a hardware SRAM2 erase operation*/ - *(__IO uint32_t *) SCSR_SRAM2ER_BB = 0x00000001UL; -} - -/** - * @brief Enable the Internal FLASH Bank Swapping. - * - * @note This function can be used only for STM32L4xx devices. - * - * @note Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) - * and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000) - * - * @retval None - */ -void HAL_SYSCFG_EnableMemorySwappingBank(void) -{ - *(__IO uint32_t *)FB_MODE_BB = 0x00000001UL; -} - -/** - * @brief Disable the Internal FLASH Bank Swapping. - * - * @note This function can be used only for STM32L4xx devices. - * - * @note The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000) - * and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000) - * - * @retval None - */ -void HAL_SYSCFG_DisableMemorySwappingBank(void) -{ - - *(__IO uint32_t *)FB_MODE_BB = 0x00000000UL; -} - -#if defined(VREFBUF) -/** - * @brief Configure the internal voltage reference buffer voltage scale. - * @param VoltageScaling specifies the output voltage to achieve - * This parameter can be one of the following values: - * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V. - * This requires VDDA equal to or higher than 2.4 V. - * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.5 V. - * This requires VDDA equal to or higher than 2.8 V. - * @retval None - */ -void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling) -{ - /* Check the parameters */ - assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling)); - - MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling); -} - -/** - * @brief Configure the internal voltage reference buffer high impedance mode. - * @param Mode specifies the high impedance mode - * This parameter can be one of the following values: - * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output. - * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance. - * @retval None - */ -void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) -{ - /* Check the parameters */ - assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode)); - - MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode); -} - -/** - * @brief Tune the Internal Voltage Reference buffer (VREFBUF). - * @retval None - */ -void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue) -{ - /* Check the parameters */ - assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue)); - - MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue); -} - -/** - * @brief Enable the Internal Voltage Reference buffer (VREFBUF). - * @retval HAL_OK/HAL_TIMEOUT - */ -HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void) -{ - uint32_t tickstart; - - SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait for VRR bit */ - while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0U) - { - if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - return HAL_OK; -} - -/** - * @brief Disable the Internal Voltage Reference buffer (VREFBUF). - * - * @retval None - */ -void HAL_SYSCFG_DisableVREFBUF(void) -{ - CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); -} -#endif /* VREFBUF */ - -/** - * @brief Enable the I/O analog switch voltage booster - * - * @retval None - */ -void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void) -{ - SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); -} - -/** - * @brief Disable the I/O analog switch voltage booster - * - * @retval None - */ -void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void) -{ - CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ diff --git a/Mcu/l431/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c b/Mcu/l431/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c deleted file mode 100644 index 9c51e6fb2..000000000 --- a/Mcu/l431/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c +++ /dev/null @@ -1,2437 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_can.c - * @author MCD Application Team - * @brief CAN HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Controller Area Network (CAN) peripheral: - * + Initialization and de-initialization functions - * + Configuration functions - * + Control functions - * + Interrupts management - * + Callbacks functions - * + Peripheral State and Error functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Initialize the CAN low level resources by implementing the - HAL_CAN_MspInit(): - (++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE() - (++) Configure CAN pins - (+++) Enable the clock for the CAN GPIOs - (+++) Configure CAN pins as alternate function open-drain - (++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification()) - (+++) Configure the CAN interrupt priority using - HAL_NVIC_SetPriority() - (+++) Enable the CAN IRQ handler using HAL_NVIC_EnableIRQ() - (+++) In CAN IRQ handler, call HAL_CAN_IRQHandler() - - (#) Initialize the CAN peripheral using HAL_CAN_Init() function. This - function resorts to HAL_CAN_MspInit() for low-level initialization. - - (#) Configure the reception filters using the following configuration - functions: - (++) HAL_CAN_ConfigFilter() - - (#) Start the CAN module using HAL_CAN_Start() function. At this level - the node is active on the bus: it receive messages, and can send - messages. - - (#) To manage messages transmission, the following Tx control functions - can be used: - (++) HAL_CAN_AddTxMessage() to request transmission of a new - message. - (++) HAL_CAN_AbortTxRequest() to abort transmission of a pending - message. - (++) HAL_CAN_GetTxMailboxesFreeLevel() to get the number of free Tx - mailboxes. - (++) HAL_CAN_IsTxMessagePending() to check if a message is pending - in a Tx mailbox. - (++) HAL_CAN_GetTxTimestamp() to get the timestamp of Tx message - sent, if time triggered communication mode is enabled. - - (#) When a message is received into the CAN Rx FIFOs, it can be retrieved - using the HAL_CAN_GetRxMessage() function. The function - HAL_CAN_GetRxFifoFillLevel() allows to know how many Rx message are - stored in the Rx Fifo. - - (#) Calling the HAL_CAN_Stop() function stops the CAN module. - - (#) The deinitialization is achieved with HAL_CAN_DeInit() function. - - - *** Polling mode operation *** - ============================== - [..] - (#) Reception: - (++) Monitor reception of message using HAL_CAN_GetRxFifoFillLevel() - until at least one message is received. - (++) Then get the message using HAL_CAN_GetRxMessage(). - - (#) Transmission: - (++) Monitor the Tx mailboxes availability until at least one Tx - mailbox is free, using HAL_CAN_GetTxMailboxesFreeLevel(). - (++) Then request transmission of a message using - HAL_CAN_AddTxMessage(). - - - *** Interrupt mode operation *** - ================================ - [..] - (#) Notifications are activated using HAL_CAN_ActivateNotification() - function. Then, the process can be controlled through the - available user callbacks: HAL_CAN_xxxCallback(), using same APIs - HAL_CAN_GetRxMessage() and HAL_CAN_AddTxMessage(). - - (#) Notifications can be deactivated using - HAL_CAN_DeactivateNotification() function. - - (#) Special care should be taken for CAN_IT_RX_FIFO0_MSG_PENDING and - CAN_IT_RX_FIFO1_MSG_PENDING notifications. These notifications trig - the callbacks HAL_CAN_RxFIFO0MsgPendingCallback() and - HAL_CAN_RxFIFO1MsgPendingCallback(). User has two possible options - here. - (++) Directly get the Rx message in the callback, using - HAL_CAN_GetRxMessage(). - (++) Or deactivate the notification in the callback without - getting the Rx message. The Rx message can then be got later - using HAL_CAN_GetRxMessage(). Once the Rx message have been - read, the notification can be activated again. - - - *** Sleep mode *** - ================== - [..] - (#) The CAN peripheral can be put in sleep mode (low power), using - HAL_CAN_RequestSleep(). The sleep mode will be entered as soon as the - current CAN activity (transmission or reception of a CAN frame) will - be completed. - - (#) A notification can be activated to be informed when the sleep mode - will be entered. - - (#) It can be checked if the sleep mode is entered using - HAL_CAN_IsSleepActive(). - Note that the CAN state (accessible from the API HAL_CAN_GetState()) - is HAL_CAN_STATE_SLEEP_PENDING as soon as the sleep mode request is - submitted (the sleep mode is not yet entered), and become - HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective. - - (#) The wake-up from sleep mode can be triggered by two ways: - (++) Using HAL_CAN_WakeUp(). When returning from this function, - the sleep mode is exited (if return status is HAL_OK). - (++) When a start of Rx CAN frame is detected by the CAN peripheral, - if automatic wake up mode is enabled. - - *** Callback registration *** - ============================================= - - The compilation define USE_HAL_CAN_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - Use Function HAL_CAN_RegisterCallback() to register an interrupt callback. - - Function HAL_CAN_RegisterCallback() allows to register following callbacks: - (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback. - (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback. - (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback. - (+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback. - (+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback. - (+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback. - (+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback. - (+) RxFifo0FullCallback : Rx Fifo 0 Full Callback. - (+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback. - (+) RxFifo1FullCallback : Rx Fifo 1 Full Callback. - (+) SleepCallback : Sleep Callback. - (+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback. - (+) ErrorCallback : Error Callback. - (+) MspInitCallback : CAN MspInit. - (+) MspDeInitCallback : CAN MspDeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - Use function HAL_CAN_UnRegisterCallback() to reset a callback to the default - weak function. - HAL_CAN_UnRegisterCallback takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback. - (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback. - (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback. - (+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback. - (+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback. - (+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback. - (+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback. - (+) RxFifo0FullCallback : Rx Fifo 0 Full Callback. - (+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback. - (+) RxFifo1FullCallback : Rx Fifo 1 Full Callback. - (+) SleepCallback : Sleep Callback. - (+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback. - (+) ErrorCallback : Error Callback. - (+) MspInitCallback : CAN MspInit. - (+) MspDeInitCallback : CAN MspDeInit. - - By default, after the HAL_CAN_Init() and when the state is HAL_CAN_STATE_RESET, - all callbacks are set to the corresponding weak functions: - example HAL_CAN_ErrorCallback(). - Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak function in the HAL_CAN_Init()/ HAL_CAN_DeInit() only when - these callbacks are null (not registered beforehand). - if not, MspInit or MspDeInit are not null, the HAL_CAN_Init()/ HAL_CAN_DeInit() - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) - - Callbacks can be registered/unregistered in HAL_CAN_STATE_READY state only. - Exception done MspInit/MspDeInit that can be registered/unregistered - in HAL_CAN_STATE_READY or HAL_CAN_STATE_RESET state, - thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using HAL_CAN_RegisterCallback() before calling HAL_CAN_DeInit() - or HAL_CAN_Init() function. - - When The compilation define USE_HAL_CAN_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all callbacks - are set to the corresponding weak functions. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -#if defined(CAN1) - -/** @defgroup CAN CAN - * @brief CAN driver modules - * @{ - */ - -#ifdef HAL_CAN_MODULE_ENABLED - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED -#error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup CAN_Private_Constants CAN Private Constants - * @{ - */ -#define CAN_TIMEOUT_VALUE 10U -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup CAN_Exported_Functions CAN Exported Functions - * @{ - */ - -/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and de-initialization functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) HAL_CAN_Init : Initialize and configure the CAN. - (+) HAL_CAN_DeInit : De-initialize the CAN. - (+) HAL_CAN_MspInit : Initialize the CAN MSP. - (+) HAL_CAN_MspDeInit : DeInitialize the CAN MSP. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the CAN peripheral according to the specified - * parameters in the CAN_InitStruct. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) -{ - uint32_t tickstart; - - /* Check CAN handle */ - if (hcan == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority)); - assert_param(IS_CAN_MODE(hcan->Init.Mode)); - assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth)); - assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1)); - assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2)); - assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); - -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - if (hcan->State == HAL_CAN_STATE_RESET) - { - /* Reset callbacks to legacy functions */ - hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; /* Legacy weak RxFifo0MsgPendingCallback */ - hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; /* Legacy weak RxFifo0FullCallback */ - hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; /* Legacy weak RxFifo1MsgPendingCallback */ - hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; /* Legacy weak RxFifo1FullCallback */ - hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; /* Legacy weak TxMailbox0CompleteCallback */ - hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; /* Legacy weak TxMailbox1CompleteCallback */ - hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; /* Legacy weak TxMailbox2CompleteCallback */ - hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; /* Legacy weak TxMailbox0AbortCallback */ - hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; /* Legacy weak TxMailbox1AbortCallback */ - hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; /* Legacy weak TxMailbox2AbortCallback */ - hcan->SleepCallback = HAL_CAN_SleepCallback; /* Legacy weak SleepCallback */ - hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; /* Legacy weak WakeUpFromRxMsgCallback */ - hcan->ErrorCallback = HAL_CAN_ErrorCallback; /* Legacy weak ErrorCallback */ - - if (hcan->MspInitCallback == NULL) - { - hcan->MspInitCallback = HAL_CAN_MspInit; /* Legacy weak MspInit */ - } - - /* Init the low level hardware: CLOCK, NVIC */ - hcan->MspInitCallback(hcan); - } - -#else - if (hcan->State == HAL_CAN_STATE_RESET) - { - /* Init the low level hardware: CLOCK, NVIC */ - HAL_CAN_MspInit(hcan); - } -#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ - - /* Request initialisation */ - SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait initialisation acknowledge */ - while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) - { - if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - - return HAL_ERROR; - } - } - - /* Exit from sleep mode */ - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check Sleep mode leave acknowledge */ - while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) - { - if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - - return HAL_ERROR; - } - } - - /* Set the time triggered communication mode */ - if (hcan->Init.TimeTriggeredMode == ENABLE) - { - SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); - } - else - { - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); - } - - /* Set the automatic bus-off management */ - if (hcan->Init.AutoBusOff == ENABLE) - { - SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); - } - else - { - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); - } - - /* Set the automatic wake-up mode */ - if (hcan->Init.AutoWakeUp == ENABLE) - { - SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); - } - else - { - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); - } - - /* Set the automatic retransmission */ - if (hcan->Init.AutoRetransmission == ENABLE) - { - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); - } - else - { - SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); - } - - /* Set the receive FIFO locked mode */ - if (hcan->Init.ReceiveFifoLocked == ENABLE) - { - SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); - } - else - { - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); - } - - /* Set the transmit FIFO priority */ - if (hcan->Init.TransmitFifoPriority == ENABLE) - { - SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); - } - else - { - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); - } - - /* Set the bit timing register */ - WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | - hcan->Init.SyncJumpWidth | - hcan->Init.TimeSeg1 | - hcan->Init.TimeSeg2 | - (hcan->Init.Prescaler - 1U))); - - /* Initialize the error code */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Initialize the CAN state */ - hcan->State = HAL_CAN_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Deinitializes the CAN peripheral registers to their default - * reset values. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan) -{ - /* Check CAN handle */ - if (hcan == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); - - /* Stop the CAN module */ - (void)HAL_CAN_Stop(hcan); - -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - if (hcan->MspDeInitCallback == NULL) - { - hcan->MspDeInitCallback = HAL_CAN_MspDeInit; /* Legacy weak MspDeInit */ - } - - /* DeInit the low level hardware: CLOCK, NVIC */ - hcan->MspDeInitCallback(hcan); - -#else - /* DeInit the low level hardware: CLOCK, NVIC */ - HAL_CAN_MspDeInit(hcan); -#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ - - /* Reset the CAN peripheral */ - SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET); - - /* Reset the CAN ErrorCode */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_RESET; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CAN MSP. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes the CAN MSP. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_MspDeInit could be implemented in the user file - */ -} - -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 -/** - * @brief Register a CAN CallBack. - * To be used instead of the weak predefined callback - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for CAN module - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID - * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID - * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID - * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID - * @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID - * @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID - * @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID - * @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID - * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID - * @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID - * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID - * @param pCallback pointer to the Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, - void (* pCallback)(CAN_HandleTypeDef *_hcan)) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - if (hcan->State == HAL_CAN_STATE_READY) - { - switch (CallbackID) - { - case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID : - hcan->TxMailbox0CompleteCallback = pCallback; - break; - - case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID : - hcan->TxMailbox1CompleteCallback = pCallback; - break; - - case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID : - hcan->TxMailbox2CompleteCallback = pCallback; - break; - - case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID : - hcan->TxMailbox0AbortCallback = pCallback; - break; - - case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID : - hcan->TxMailbox1AbortCallback = pCallback; - break; - - case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID : - hcan->TxMailbox2AbortCallback = pCallback; - break; - - case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID : - hcan->RxFifo0MsgPendingCallback = pCallback; - break; - - case HAL_CAN_RX_FIFO0_FULL_CB_ID : - hcan->RxFifo0FullCallback = pCallback; - break; - - case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID : - hcan->RxFifo1MsgPendingCallback = pCallback; - break; - - case HAL_CAN_RX_FIFO1_FULL_CB_ID : - hcan->RxFifo1FullCallback = pCallback; - break; - - case HAL_CAN_SLEEP_CB_ID : - hcan->SleepCallback = pCallback; - break; - - case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID : - hcan->WakeUpFromRxMsgCallback = pCallback; - break; - - case HAL_CAN_ERROR_CB_ID : - hcan->ErrorCallback = pCallback; - break; - - case HAL_CAN_MSPINIT_CB_ID : - hcan->MspInitCallback = pCallback; - break; - - case HAL_CAN_MSPDEINIT_CB_ID : - hcan->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (hcan->State == HAL_CAN_STATE_RESET) - { - switch (CallbackID) - { - case HAL_CAN_MSPINIT_CB_ID : - hcan->MspInitCallback = pCallback; - break; - - case HAL_CAN_MSPDEINIT_CB_ID : - hcan->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Unregister a CAN CallBack. - * CAN callback is redirected to the weak predefined callback - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for CAN module - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID - * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID - * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID - * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID - * @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID - * @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID - * @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID - * @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID - * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID - * @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID - * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (hcan->State == HAL_CAN_STATE_READY) - { - switch (CallbackID) - { - case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID : - hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; - break; - - case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID : - hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; - break; - - case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID : - hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; - break; - - case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID : - hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; - break; - - case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID : - hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; - break; - - case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID : - hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; - break; - - case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID : - hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; - break; - - case HAL_CAN_RX_FIFO0_FULL_CB_ID : - hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; - break; - - case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID : - hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; - break; - - case HAL_CAN_RX_FIFO1_FULL_CB_ID : - hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; - break; - - case HAL_CAN_SLEEP_CB_ID : - hcan->SleepCallback = HAL_CAN_SleepCallback; - break; - - case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID : - hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; - break; - - case HAL_CAN_ERROR_CB_ID : - hcan->ErrorCallback = HAL_CAN_ErrorCallback; - break; - - case HAL_CAN_MSPINIT_CB_ID : - hcan->MspInitCallback = HAL_CAN_MspInit; - break; - - case HAL_CAN_MSPDEINIT_CB_ID : - hcan->MspDeInitCallback = HAL_CAN_MspDeInit; - break; - - default : - /* Update the error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (hcan->State == HAL_CAN_STATE_RESET) - { - switch (CallbackID) - { - case HAL_CAN_MSPINIT_CB_ID : - hcan->MspInitCallback = HAL_CAN_MspInit; - break; - - case HAL_CAN_MSPDEINIT_CB_ID : - hcan->MspDeInitCallback = HAL_CAN_MspDeInit; - break; - - default : - /* Update the error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup CAN_Exported_Functions_Group2 Configuration functions - * @brief Configuration functions. - * -@verbatim - ============================================================================== - ##### Configuration functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) HAL_CAN_ConfigFilter : Configure the CAN reception filters - -@endverbatim - * @{ - */ - -/** - * @brief Configures the CAN reception filter according to the specified - * parameters in the CAN_FilterInitStruct. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that - * contains the filter configuration information. - * @retval None - */ -HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig) -{ - uint32_t filternbrbitpos; - CAN_TypeDef *can_ip = hcan->Instance; - HAL_CAN_StateTypeDef state = hcan->State; - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Check the parameters */ - assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh)); - assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow)); - assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh)); - assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow)); - assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); - assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); - assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); - assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation)); - -#if defined(CAN2) - /* CAN1 and CAN2 are dual instances with 28 common filters banks */ - /* Select master instance to access the filter banks */ - can_ip = CAN1; - - /* Check the parameters */ - assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank)); - assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank)); -#else - /* CAN1 is single instance with 14 dedicated filters banks */ - - /* Check the parameters */ - assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); -#endif - - /* Initialisation mode for the filter */ - SET_BIT(can_ip->FMR, CAN_FMR_FINIT); - -#if defined(CAN2) - /* Select the start filter number of CAN2 slave instance */ - CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); - SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); - -#endif - /* Convert filter number into bit position */ - filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); - - /* Filter Deactivation */ - CLEAR_BIT(can_ip->FA1R, filternbrbitpos); - - /* Filter Scale */ - if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) - { - /* 16-bit scale for the filter */ - CLEAR_BIT(can_ip->FS1R, filternbrbitpos); - - /* First 16-bit identifier and First 16-bit mask */ - /* Or First 16-bit identifier and Second 16-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); - - /* Second 16-bit identifier and Second 16-bit mask */ - /* Or Third 16-bit identifier and Fourth 16-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); - } - - if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) - { - /* 32-bit scale for the filter */ - SET_BIT(can_ip->FS1R, filternbrbitpos); - - /* 32-bit identifier or First 32-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); - - /* 32-bit mask or Second 32-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); - } - - /* Filter Mode */ - if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) - { - /* Id/Mask mode for the filter*/ - CLEAR_BIT(can_ip->FM1R, filternbrbitpos); - } - else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ - { - /* Identifier list mode for the filter*/ - SET_BIT(can_ip->FM1R, filternbrbitpos); - } - - /* Filter FIFO assignment */ - if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) - { - /* FIFO 0 assignation for the filter */ - CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); - } - else - { - /* FIFO 1 assignation for the filter */ - SET_BIT(can_ip->FFA1R, filternbrbitpos); - } - - /* Filter activation */ - if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) - { - SET_BIT(can_ip->FA1R, filternbrbitpos); - } - - /* Leave the initialisation mode for the filter */ - CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); - - /* Return function status */ - return HAL_OK; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - - return HAL_ERROR; - } -} - -/** - * @} - */ - -/** @defgroup CAN_Exported_Functions_Group3 Control functions - * @brief Control functions - * -@verbatim - ============================================================================== - ##### Control functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) HAL_CAN_Start : Start the CAN module - (+) HAL_CAN_Stop : Stop the CAN module - (+) HAL_CAN_RequestSleep : Request sleep mode entry. - (+) HAL_CAN_WakeUp : Wake up from sleep mode. - (+) HAL_CAN_IsSleepActive : Check is sleep mode is active. - (+) HAL_CAN_AddTxMessage : Add a message to the Tx mailboxes - and activate the corresponding - transmission request - (+) HAL_CAN_AbortTxRequest : Abort transmission request - (+) HAL_CAN_GetTxMailboxesFreeLevel : Return Tx mailboxes free level - (+) HAL_CAN_IsTxMessagePending : Check if a transmission request is - pending on the selected Tx mailbox - (+) HAL_CAN_GetRxMessage : Get a CAN frame from the Rx FIFO - (+) HAL_CAN_GetRxFifoFillLevel : Return Rx FIFO fill level - -@endverbatim - * @{ - */ - -/** - * @brief Start the CAN module. - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) -{ - uint32_t tickstart; - - if (hcan->State == HAL_CAN_STATE_READY) - { - /* Change CAN peripheral state */ - hcan->State = HAL_CAN_STATE_LISTENING; - - /* Request leave initialisation */ - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait the acknowledge */ - while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - - return HAL_ERROR; - } - } - - /* Reset the CAN ErrorCode */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Return function status */ - return HAL_OK; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; - - return HAL_ERROR; - } -} - -/** - * @brief Stop the CAN module and enable access to configuration registers. - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) -{ - uint32_t tickstart; - - if (hcan->State == HAL_CAN_STATE_LISTENING) - { - /* Request initialisation */ - SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait the acknowledge */ - while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - - return HAL_ERROR; - } - } - - /* Exit from sleep mode */ - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); - - /* Change CAN peripheral state */ - hcan->State = HAL_CAN_STATE_READY; - - /* Return function status */ - return HAL_OK; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; - - return HAL_ERROR; - } -} - -/** - * @brief Request the sleep mode (low power) entry. - * When returning from this function, Sleep mode will be entered - * as soon as the current CAN activity (transmission or reception - * of a CAN frame) has been completed. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan) -{ - HAL_CAN_StateTypeDef state = hcan->State; - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Request Sleep mode */ - SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); - - /* Return function status */ - return HAL_OK; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - - /* Return function status */ - return HAL_ERROR; - } -} - -/** - * @brief Wake up from sleep mode. - * When returning with HAL_OK status from this function, Sleep mode - * is exited. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) -{ - __IO uint32_t count = 0; - uint32_t timeout = 1000000U; - HAL_CAN_StateTypeDef state = hcan->State; - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Wake up request */ - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); - - /* Wait sleep mode is exited */ - do - { - /* Increment counter */ - count++; - - /* Check if timeout is reached */ - if (count > timeout) - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - - return HAL_ERROR; - } - } - while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U); - - /* Return function status */ - return HAL_OK; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - - return HAL_ERROR; - } -} - -/** - * @brief Check is sleep mode is active. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval Status - * - 0 : Sleep mode is not active. - * - 1 : Sleep mode is active. - */ -uint32_t HAL_CAN_IsSleepActive(const CAN_HandleTypeDef *hcan) -{ - uint32_t status = 0U; - HAL_CAN_StateTypeDef state = hcan->State; - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Check Sleep mode */ - if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) - { - status = 1U; - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Add a message to the first free Tx mailbox and activate the - * corresponding transmission request. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param pHeader pointer to a CAN_TxHeaderTypeDef structure. - * @param aData array containing the payload of the Tx frame. - * @param pTxMailbox pointer to a variable where the function will return - * the TxMailbox used to store the Tx message. - * This parameter can be a value of @arg CAN_Tx_Mailboxes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, - const uint8_t aData[], uint32_t *pTxMailbox) -{ - uint32_t transmitmailbox; - HAL_CAN_StateTypeDef state = hcan->State; - uint32_t tsr = READ_REG(hcan->Instance->TSR); - - /* Check the parameters */ - assert_param(IS_CAN_IDTYPE(pHeader->IDE)); - assert_param(IS_CAN_RTR(pHeader->RTR)); - assert_param(IS_CAN_DLC(pHeader->DLC)); - if (pHeader->IDE == CAN_ID_STD) - { - assert_param(IS_CAN_STDID(pHeader->StdId)); - } - else - { - assert_param(IS_CAN_EXTID(pHeader->ExtId)); - } - assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Check that all the Tx mailboxes are not full */ - if (((tsr & CAN_TSR_TME0) != 0U) || - ((tsr & CAN_TSR_TME1) != 0U) || - ((tsr & CAN_TSR_TME2) != 0U)) - { - /* Select an empty transmit mailbox */ - transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; - - /* Store the Tx mailbox */ - *pTxMailbox = (uint32_t)1 << transmitmailbox; - - /* Set up the Id */ - if (pHeader->IDE == CAN_ID_STD) - { - hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | - pHeader->RTR); - } - else - { - hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | - pHeader->IDE | - pHeader->RTR); - } - - /* Set up the DLC */ - hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); - - /* Set up the Transmit Global Time mode */ - if (pHeader->TransmitGlobalTime == ENABLE) - { - SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); - } - - /* Set up the data field */ - WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, - ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | - ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | - ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | - ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); - WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, - ((uint32_t)aData[3] << CAN_TDL0R_DATA3_Pos) | - ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | - ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | - ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); - - /* Request transmission */ - SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); - - /* Return function status */ - return HAL_OK; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; - - return HAL_ERROR; - } - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - - return HAL_ERROR; - } -} - -/** - * @brief Abort transmission requests - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param TxMailboxes List of the Tx Mailboxes to abort. - * This parameter can be any combination of @arg CAN_Tx_Mailboxes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) -{ - HAL_CAN_StateTypeDef state = hcan->State; - - /* Check function parameters */ - assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Check Tx Mailbox 0 */ - if ((TxMailboxes & CAN_TX_MAILBOX0) != 0U) - { - /* Add cancellation request for Tx Mailbox 0 */ - SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0); - } - - /* Check Tx Mailbox 1 */ - if ((TxMailboxes & CAN_TX_MAILBOX1) != 0U) - { - /* Add cancellation request for Tx Mailbox 1 */ - SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1); - } - - /* Check Tx Mailbox 2 */ - if ((TxMailboxes & CAN_TX_MAILBOX2) != 0U) - { - /* Add cancellation request for Tx Mailbox 2 */ - SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2); - } - - /* Return function status */ - return HAL_OK; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - - return HAL_ERROR; - } -} - -/** - * @brief Return Tx Mailboxes free level: number of free Tx Mailboxes. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval Number of free Tx Mailboxes. - */ -uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan) -{ - uint32_t freelevel = 0U; - HAL_CAN_StateTypeDef state = hcan->State; - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Check Tx Mailbox 0 status */ - if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U) - { - freelevel++; - } - - /* Check Tx Mailbox 1 status */ - if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U) - { - freelevel++; - } - - /* Check Tx Mailbox 2 status */ - if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U) - { - freelevel++; - } - } - - /* Return Tx Mailboxes free level */ - return freelevel; -} - -/** - * @brief Check if a transmission request is pending on the selected Tx - * Mailboxes. - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param TxMailboxes List of Tx Mailboxes to check. - * This parameter can be any combination of @arg CAN_Tx_Mailboxes. - * @retval Status - * - 0 : No pending transmission request on any selected Tx Mailboxes. - * - 1 : Pending transmission request on at least one of the selected - * Tx Mailbox. - */ -uint32_t HAL_CAN_IsTxMessagePending(const CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) -{ - uint32_t status = 0U; - HAL_CAN_StateTypeDef state = hcan->State; - - /* Check function parameters */ - assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Check pending transmission request on the selected Tx Mailboxes */ - if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos)) - { - status = 1U; - } - } - - /* Return status */ - return status; -} - -/** - * @brief Return timestamp of Tx message sent, if time triggered communication - mode is enabled. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param TxMailbox Tx Mailbox where the timestamp of message sent will be - * read. - * This parameter can be one value of @arg CAN_Tx_Mailboxes. - * @retval Timestamp of message sent from Tx Mailbox. - */ -uint32_t HAL_CAN_GetTxTimestamp(const CAN_HandleTypeDef *hcan, uint32_t TxMailbox) -{ - uint32_t timestamp = 0U; - uint32_t transmitmailbox; - HAL_CAN_StateTypeDef state = hcan->State; - - /* Check function parameters */ - assert_param(IS_CAN_TX_MAILBOX(TxMailbox)); - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Select the Tx mailbox */ - transmitmailbox = POSITION_VAL(TxMailbox); - - /* Get timestamp */ - timestamp = (hcan->Instance->sTxMailBox[transmitmailbox].TDTR & CAN_TDT0R_TIME) >> CAN_TDT0R_TIME_Pos; - } - - /* Return the timestamp */ - return timestamp; -} - -/** - * @brief Get an CAN frame from the Rx FIFO zone into the message RAM. - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param RxFifo Fifo number of the received message to be read. - * This parameter can be a value of @arg CAN_receive_FIFO_number. - * @param pHeader pointer to a CAN_RxHeaderTypeDef structure where the header - * of the Rx frame will be stored. - * @param aData array where the payload of the Rx frame will be stored. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, - CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) -{ - HAL_CAN_StateTypeDef state = hcan->State; - - assert_param(IS_CAN_RX_FIFO(RxFifo)); - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Check the Rx FIFO */ - if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ - { - /* Check that the Rx FIFO 0 is not empty */ - if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; - - return HAL_ERROR; - } - } - else /* Rx element is assigned to Rx FIFO 1 */ - { - /* Check that the Rx FIFO 1 is not empty */ - if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; - - return HAL_ERROR; - } - } - - /* Get the header */ - pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; - if (pHeader->IDE == CAN_ID_STD) - { - pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; - } - else - { - pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & - hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; - } - pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); - if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U) - { - /* Truncate DLC to 8 if received field is over range */ - pHeader->DLC = 8U; - } - else - { - pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; - } - pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; - pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; - - /* Get the data */ - aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); - aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); - aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); - aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); - aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); - aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); - aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); - aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); - - /* Release the FIFO */ - if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ - { - /* Release RX FIFO 0 */ - SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); - } - else /* Rx element is assigned to Rx FIFO 1 */ - { - /* Release RX FIFO 1 */ - SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); - } - - /* Return function status */ - return HAL_OK; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - - return HAL_ERROR; - } -} - -/** - * @brief Return Rx FIFO fill level. - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param RxFifo Rx FIFO. - * This parameter can be a value of @arg CAN_receive_FIFO_number. - * @retval Number of messages available in Rx FIFO. - */ -uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFifo) -{ - uint32_t filllevel = 0U; - HAL_CAN_StateTypeDef state = hcan->State; - - /* Check function parameters */ - assert_param(IS_CAN_RX_FIFO(RxFifo)); - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - if (RxFifo == CAN_RX_FIFO0) - { - filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0; - } - else /* RxFifo == CAN_RX_FIFO1 */ - { - filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1; - } - } - - /* Return Rx FIFO fill level */ - return filllevel; -} - -/** - * @} - */ - -/** @defgroup CAN_Exported_Functions_Group4 Interrupts management - * @brief Interrupts management - * -@verbatim - ============================================================================== - ##### Interrupts management ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) HAL_CAN_ActivateNotification : Enable interrupts - (+) HAL_CAN_DeactivateNotification : Disable interrupts - (+) HAL_CAN_IRQHandler : Handles CAN interrupt request - -@endverbatim - * @{ - */ - -/** - * @brief Enable interrupts. - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param ActiveITs indicates which interrupts will be enabled. - * This parameter can be any combination of @arg CAN_Interrupts. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) -{ - HAL_CAN_StateTypeDef state = hcan->State; - - /* Check function parameters */ - assert_param(IS_CAN_IT(ActiveITs)); - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Enable the selected interrupts */ - __HAL_CAN_ENABLE_IT(hcan, ActiveITs); - - /* Return function status */ - return HAL_OK; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - - return HAL_ERROR; - } -} - -/** - * @brief Disable interrupts. - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param InactiveITs indicates which interrupts will be disabled. - * This parameter can be any combination of @arg CAN_Interrupts. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs) -{ - HAL_CAN_StateTypeDef state = hcan->State; - - /* Check function parameters */ - assert_param(IS_CAN_IT(InactiveITs)); - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Disable the selected interrupts */ - __HAL_CAN_DISABLE_IT(hcan, InactiveITs); - - /* Return function status */ - return HAL_OK; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - - return HAL_ERROR; - } -} - -/** - * @brief Handles CAN interrupt request - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) -{ - uint32_t errorcode = HAL_CAN_ERROR_NONE; - uint32_t interrupts = READ_REG(hcan->Instance->IER); - uint32_t msrflags = READ_REG(hcan->Instance->MSR); - uint32_t tsrflags = READ_REG(hcan->Instance->TSR); - uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); - uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); - uint32_t esrflags = READ_REG(hcan->Instance->ESR); - - /* Transmit Mailbox empty interrupt management *****************************/ - if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) - { - /* Transmit Mailbox 0 management *****************************************/ - if ((tsrflags & CAN_TSR_RQCP0) != 0U) - { - /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); - - if ((tsrflags & CAN_TSR_TXOK0) != 0U) - { - /* Transmission Mailbox 0 complete callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->TxMailbox0CompleteCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_TxMailbox0CompleteCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - else - { - if ((tsrflags & CAN_TSR_ALST0) != 0U) - { - /* Update error code */ - errorcode |= HAL_CAN_ERROR_TX_ALST0; - } - else if ((tsrflags & CAN_TSR_TERR0) != 0U) - { - /* Update error code */ - errorcode |= HAL_CAN_ERROR_TX_TERR0; - } - else - { - /* Transmission Mailbox 0 abort callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->TxMailbox0AbortCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_TxMailbox0AbortCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - } - - /* Transmit Mailbox 1 management *****************************************/ - if ((tsrflags & CAN_TSR_RQCP1) != 0U) - { - /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); - - if ((tsrflags & CAN_TSR_TXOK1) != 0U) - { - /* Transmission Mailbox 1 complete callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->TxMailbox1CompleteCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_TxMailbox1CompleteCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - else - { - if ((tsrflags & CAN_TSR_ALST1) != 0U) - { - /* Update error code */ - errorcode |= HAL_CAN_ERROR_TX_ALST1; - } - else if ((tsrflags & CAN_TSR_TERR1) != 0U) - { - /* Update error code */ - errorcode |= HAL_CAN_ERROR_TX_TERR1; - } - else - { - /* Transmission Mailbox 1 abort callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->TxMailbox1AbortCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_TxMailbox1AbortCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - } - - /* Transmit Mailbox 2 management *****************************************/ - if ((tsrflags & CAN_TSR_RQCP2) != 0U) - { - /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); - - if ((tsrflags & CAN_TSR_TXOK2) != 0U) - { - /* Transmission Mailbox 2 complete callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->TxMailbox2CompleteCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_TxMailbox2CompleteCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - else - { - if ((tsrflags & CAN_TSR_ALST2) != 0U) - { - /* Update error code */ - errorcode |= HAL_CAN_ERROR_TX_ALST2; - } - else if ((tsrflags & CAN_TSR_TERR2) != 0U) - { - /* Update error code */ - errorcode |= HAL_CAN_ERROR_TX_TERR2; - } - else - { - /* Transmission Mailbox 2 abort callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->TxMailbox2AbortCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_TxMailbox2AbortCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - } - } - - /* Receive FIFO 0 overrun interrupt management *****************************/ - if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) - { - if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) - { - /* Set CAN error code to Rx Fifo 0 overrun error */ - errorcode |= HAL_CAN_ERROR_RX_FOV0; - - /* Clear FIFO0 Overrun Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); - } - } - - /* Receive FIFO 0 full interrupt management ********************************/ - if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) - { - if ((rf0rflags & CAN_RF0R_FULL0) != 0U) - { - /* Clear FIFO 0 full Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); - - /* Receive FIFO 0 full Callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->RxFifo0FullCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_RxFifo0FullCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - - /* Receive FIFO 0 message pending interrupt management *********************/ - if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) - { - /* Check if message is still pending */ - if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) - { - /* Receive FIFO 0 message pending Callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->RxFifo0MsgPendingCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_RxFifo0MsgPendingCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - - /* Receive FIFO 1 overrun interrupt management *****************************/ - if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) - { - if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) - { - /* Set CAN error code to Rx Fifo 1 overrun error */ - errorcode |= HAL_CAN_ERROR_RX_FOV1; - - /* Clear FIFO1 Overrun Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); - } - } - - /* Receive FIFO 1 full interrupt management ********************************/ - if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) - { - if ((rf1rflags & CAN_RF1R_FULL1) != 0U) - { - /* Clear FIFO 1 full Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); - - /* Receive FIFO 1 full Callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->RxFifo1FullCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_RxFifo1FullCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - - /* Receive FIFO 1 message pending interrupt management *********************/ - if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) - { - /* Check if message is still pending */ - if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) - { - /* Receive FIFO 1 message pending Callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->RxFifo1MsgPendingCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_RxFifo1MsgPendingCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - - /* Sleep interrupt management *********************************************/ - if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) - { - if ((msrflags & CAN_MSR_SLAKI) != 0U) - { - /* Clear Sleep interrupt Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); - - /* Sleep Callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->SleepCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_SleepCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - - /* WakeUp interrupt management *********************************************/ - if ((interrupts & CAN_IT_WAKEUP) != 0U) - { - if ((msrflags & CAN_MSR_WKUI) != 0U) - { - /* Clear WakeUp Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); - - /* WakeUp Callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->WakeUpFromRxMsgCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_WakeUpFromRxMsgCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - - /* Error interrupts management *********************************************/ - if ((interrupts & CAN_IT_ERROR) != 0U) - { - if ((msrflags & CAN_MSR_ERRI) != 0U) - { - /* Check Error Warning Flag */ - if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && - ((esrflags & CAN_ESR_EWGF) != 0U)) - { - /* Set CAN error code to Error Warning */ - errorcode |= HAL_CAN_ERROR_EWG; - - /* No need for clear of Error Warning Flag as read-only */ - } - - /* Check Error Passive Flag */ - if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && - ((esrflags & CAN_ESR_EPVF) != 0U)) - { - /* Set CAN error code to Error Passive */ - errorcode |= HAL_CAN_ERROR_EPV; - - /* No need for clear of Error Passive Flag as read-only */ - } - - /* Check Bus-off Flag */ - if (((interrupts & CAN_IT_BUSOFF) != 0U) && - ((esrflags & CAN_ESR_BOFF) != 0U)) - { - /* Set CAN error code to Bus-Off */ - errorcode |= HAL_CAN_ERROR_BOF; - - /* No need for clear of Error Bus-Off as read-only */ - } - - /* Check Last Error Code Flag */ - if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && - ((esrflags & CAN_ESR_LEC) != 0U)) - { - switch (esrflags & CAN_ESR_LEC) - { - case (CAN_ESR_LEC_0): - /* Set CAN error code to Stuff error */ - errorcode |= HAL_CAN_ERROR_STF; - break; - case (CAN_ESR_LEC_1): - /* Set CAN error code to Form error */ - errorcode |= HAL_CAN_ERROR_FOR; - break; - case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0): - /* Set CAN error code to Acknowledgement error */ - errorcode |= HAL_CAN_ERROR_ACK; - break; - case (CAN_ESR_LEC_2): - /* Set CAN error code to Bit recessive error */ - errorcode |= HAL_CAN_ERROR_BR; - break; - case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0): - /* Set CAN error code to Bit Dominant error */ - errorcode |= HAL_CAN_ERROR_BD; - break; - case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): - /* Set CAN error code to CRC error */ - errorcode |= HAL_CAN_ERROR_CRC; - break; - default: - break; - } - - /* Clear Last error code Flag */ - CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); - } - } - - /* Clear ERRI Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); - } - - /* Call the Error call Back in case of Errors */ - if (errorcode != HAL_CAN_ERROR_NONE) - { - /* Update error code in handle */ - hcan->ErrorCode |= errorcode; - - /* Call Error callback function */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->ErrorCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_ErrorCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } -} - -/** - * @} - */ - -/** @defgroup CAN_Exported_Functions_Group5 Callback functions - * @brief CAN Callback functions - * -@verbatim - ============================================================================== - ##### Callback functions ##### - ============================================================================== - [..] - This subsection provides the following callback functions: - (+) HAL_CAN_TxMailbox0CompleteCallback - (+) HAL_CAN_TxMailbox1CompleteCallback - (+) HAL_CAN_TxMailbox2CompleteCallback - (+) HAL_CAN_TxMailbox0AbortCallback - (+) HAL_CAN_TxMailbox1AbortCallback - (+) HAL_CAN_TxMailbox2AbortCallback - (+) HAL_CAN_RxFifo0MsgPendingCallback - (+) HAL_CAN_RxFifo0FullCallback - (+) HAL_CAN_RxFifo1MsgPendingCallback - (+) HAL_CAN_RxFifo1FullCallback - (+) HAL_CAN_SleepCallback - (+) HAL_CAN_WakeUpFromRxMsgCallback - (+) HAL_CAN_ErrorCallback - -@endverbatim - * @{ - */ - -/** - * @brief Transmission Mailbox 0 complete callback. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the - user file - */ -} - -/** - * @brief Transmission Mailbox 1 complete callback. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the - user file - */ -} - -/** - * @brief Transmission Mailbox 2 complete callback. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the - user file - */ -} - -/** - * @brief Transmission Mailbox 0 Cancellation callback. - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_TxMailbox0AbortCallback could be implemented in the - user file - */ -} - -/** - * @brief Transmission Mailbox 1 Cancellation callback. - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_TxMailbox1AbortCallback could be implemented in the - user file - */ -} - -/** - * @brief Transmission Mailbox 2 Cancellation callback. - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_TxMailbox2AbortCallback could be implemented in the - user file - */ -} - -/** - * @brief Rx FIFO 0 message pending callback. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the - user file - */ -} - -/** - * @brief Rx FIFO 0 full callback. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_RxFifo0FullCallback could be implemented in the user - file - */ -} - -/** - * @brief Rx FIFO 1 message pending callback. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the - user file - */ -} - -/** - * @brief Rx FIFO 1 full callback. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_RxFifo1FullCallback could be implemented in the user - file - */ -} - -/** - * @brief Sleep callback. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_SleepCallback could be implemented in the user file - */ -} - -/** - * @brief WakeUp from Rx message callback. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the - user file - */ -} - -/** - * @brief Error CAN callback. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_ErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions - * @brief CAN Peripheral State functions - * -@verbatim - ============================================================================== - ##### Peripheral State and Error functions ##### - ============================================================================== - [..] - This subsection provides functions allowing to : - (+) HAL_CAN_GetState() : Return the CAN state. - (+) HAL_CAN_GetError() : Return the CAN error codes if any. - (+) HAL_CAN_ResetError(): Reset the CAN error codes if any. - -@endverbatim - * @{ - */ - -/** - * @brief Return the CAN state. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL state - */ -HAL_CAN_StateTypeDef HAL_CAN_GetState(const CAN_HandleTypeDef *hcan) -{ - HAL_CAN_StateTypeDef state = hcan->State; - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Check sleep mode acknowledge flag */ - if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) - { - /* Sleep mode is active */ - state = HAL_CAN_STATE_SLEEP_ACTIVE; - } - /* Check sleep mode request flag */ - else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != 0U) - { - /* Sleep mode request is pending */ - state = HAL_CAN_STATE_SLEEP_PENDING; - } - else - { - /* Neither sleep mode request nor sleep mode acknowledge */ - } - } - - /* Return CAN state */ - return state; -} - -/** - * @brief Return the CAN error code. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval CAN Error Code - */ -uint32_t HAL_CAN_GetError(const CAN_HandleTypeDef *hcan) -{ - /* Return CAN error code */ - return hcan->ErrorCode; -} - -/** - * @brief Reset the CAN error code. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan) -{ - HAL_StatusTypeDef status = HAL_OK; - HAL_CAN_StateTypeDef state = hcan->State; - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Reset CAN error code */ - hcan->ErrorCode = 0U; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - - status = HAL_ERROR; - } - - /* Return the status */ - return status; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_CAN_MODULE_ENABLED */ - -/** - * @} - */ - -#endif /* CAN1 */ - -/** - * @} - */ diff --git a/Mcu/l431/Inc/blutil.h b/Mcu/l431/Inc/blutil.h new file mode 100644 index 000000000..56491ceeb --- /dev/null +++ b/Mcu/l431/Inc/blutil.h @@ -0,0 +1,135 @@ +/* + MCU specific utility functions for the bootloader + */ +#pragma once + +#define GPIO_PIN(n) (1U<<(n)) + +#define GPIO_PULL_NONE LL_GPIO_PULL_NO +#define GPIO_PULL_UP LL_GPIO_PULL_UP +#define GPIO_PULL_DOWN LL_GPIO_PULL_DOWN + +#define GPIO_OUTPUT_PUSH_PULL LL_GPIO_OUTPUT_PUSHPULL + +static inline void gpio_mode_set_input(uint32_t pin, uint32_t pull_up_down) +{ + LL_GPIO_SetPinMode(input_port, pin, LL_GPIO_MODE_INPUT); + LL_GPIO_SetPinPull(input_port, pin, pull_up_down); +} + +static inline void gpio_mode_set_output(uint32_t pin, uint32_t output_mode) +{ + LL_GPIO_SetPinMode(input_port, pin, LL_GPIO_MODE_OUTPUT); + LL_GPIO_SetPinOutputType(input_port, pin, output_mode); +} + +static inline void gpio_set(uint32_t pin) +{ + LL_GPIO_SetOutputPin(input_port, pin); +} + +static inline void gpio_clear(uint32_t pin) +{ + LL_GPIO_ResetOutputPin(input_port, pin); +} + +static inline bool gpio_read(uint32_t pin) +{ + return LL_GPIO_IsInputPinSet(input_port, pin); +} + +#define BL_TIMER TIM2 + +/* + initialise timer for 1us per tick + */ +static inline void bl_timer_init(void) +{ + LL_TIM_InitTypeDef TIM_InitStruct = {0}; + + /* Peripheral clock enable */ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2); + + TIM_InitStruct.Prescaler = 79; + TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; + TIM_InitStruct.Autoreload = 0xFFFFFFFF; + TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; + LL_TIM_Init(BL_TIMER, &TIM_InitStruct); + LL_TIM_DisableARRPreload(BL_TIMER); + LL_TIM_SetClockSource(BL_TIMER, LL_TIM_CLOCKSOURCE_INTERNAL); + LL_TIM_SetTriggerOutput(BL_TIMER, LL_TIM_TRGO_RESET); + LL_TIM_DisableMasterSlaveMode(BL_TIMER); + + LL_TIM_SetCounterMode(BL_TIMER, LL_TIM_COUNTERMODE_UP); + LL_TIM_EnableCounter(BL_TIMER); +} + +/* + disable timer ready for app start + */ +static inline void bl_timer_disable(void) +{ + LL_TIM_DeInit(BL_TIMER); +} + +static inline uint32_t bl_timer_us(void) +{ + return LL_TIM_GetCounter(BL_TIMER); +} + +static inline void bl_timer_reset(void) +{ + LL_TIM_SetCounter(BL_TIMER, 0); +} + +/* + initialise clocks + */ +static inline void bl_clock_config(void) +{ + LL_FLASH_SetLatency(LL_FLASH_LATENCY_4); + while (LL_FLASH_GetLatency()!= LL_FLASH_LATENCY_4) ; + LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1); + while (LL_PWR_IsActiveFlag_VOS() != 0) ; + LL_RCC_MSI_Enable(); + + /* Wait till MSI is ready */ + while (LL_RCC_MSI_IsReady() != 1) ; + + LL_RCC_MSI_EnableRangeSelection(); + LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6); + LL_RCC_MSI_SetCalibTrimming(0); + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 40, LL_RCC_PLLR_DIV_2); + LL_RCC_PLL_EnableDomain_SYS(); + LL_RCC_PLL_Enable(); + + /* Wait till PLL is ready */ + while (LL_RCC_PLL_IsReady() != 1) ; + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); + + /* Wait till System clock is ready */ + while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) ; + + LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); + LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1); + LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1); +} + +static inline void bl_gpio_init(void) +{ + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA); + LL_GPIO_ResetOutputPin(input_port, input_pin); +} + +/* + return true if the MCU booted under a software reset + */ +static inline bool bl_was_software_reset(void) +{ + return (RCC->CSR & RCC_CSR_SFTRSTF) != 0; +} + +void Error_Handler() +{ + while (1) {} +} diff --git a/Mcu/l431/STM32L431KCUX_FLASH.ld b/Mcu/l431/STM32L431KCUX_FLASH.ld new file mode 100644 index 000000000..9bbaf3c09 --- /dev/null +++ b/Mcu/l431/STM32L431KCUX_FLASH.ld @@ -0,0 +1,187 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32L431KCUx Device from STM32L4 series +** 256KBytes FLASH +** 64KBytes RAM +** 16KBytes RAM2 +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2024 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K + RAM2 (xrw) : ORIGIN = 0x10000000, LENGTH = 16K + FLASH (rx) : ORIGIN = 0x8001000, LENGTH = 128K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/Mcu/l431/Src/stm32l4xx_it.c b/Mcu/l431/Src/stm32l4xx_it.c index 8826afaea..6878b750e 100644 --- a/Mcu/l431/Src/stm32l4xx_it.c +++ b/Mcu/l431/Src/stm32l4xx_it.c @@ -21,8 +21,10 @@ /* Includes ------------------------------------------------------------------*/ #include "main.h" #include "stm32l4xx_it.h" +#ifndef BOOTLOADER #include "ADC.h" #include "targets.h" +#endif //#include "WS2812.h" @@ -174,6 +176,7 @@ void SysTick_Handler(void) /* please refer to the startup file (startup_stm32l4xx.s). */ /******************************************************************************/ +#ifndef BOOTLOADER /** * @brief This function handles DMA1 channel4 global interrupt. */ @@ -287,3 +290,5 @@ void COMP_IRQHandler(void) } } +#endif // BOOTLOADER + diff --git a/Mcu/l431/Startup/startup_stm32l431xx.s b/Mcu/l431/Startup/startup_stm32l431xx.s index 090101dfa..f652136e4 100644 --- a/Mcu/l431/Startup/startup_stm32l431xx.s +++ b/Mcu/l431/Startup/startup_stm32l431xx.s @@ -1,389 +1,461 @@ -;******************************************************************************* -;* File Name : startup_stm32l431xx.s -;* Author : MCD Application Team -;* Description : STM32L431xx Ultra Low Power devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* @attention -;* -;* Copyright (c) 2017 STMicroelectronics. -;* All rights reserved. -;* -;* This software is licensed under terms that can be found in the LICENSE file -;* in the root directory of this software component. -;* If no LICENSE file comes with this software, it is provided AS-IS. -; -;******************************************************************************* -;* <<< Use Configuration Wizard in Context Menu >>> -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x200 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_IRQHandler ; ADC1 - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 - DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 - DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10] - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SDMMC1_IRQHandler ; SDMMC1 - DCD 0 ; Reserved - DCD SPI3_IRQHandler ; SPI3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 - DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 - DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 - DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 - DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD COMP_IRQHandler ; COMP Interrupt - DCD LPTIM1_IRQHandler ; LP TIM1 interrupt - DCD LPTIM2_IRQHandler ; LP TIM2 interrupt - DCD 0 ; Reserved - DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 - DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 - DCD LPUART1_IRQHandler ; LP UART1 interrupt - DCD QUADSPI_IRQHandler ; Quad SPI global interrupt - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt - DCD 0 ; Reserved - DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt - DCD TSC_IRQHandler ; Touch Sense Controller global interrupt - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD RNG_IRQHandler ; RNG global interrupt - DCD FPU_IRQHandler ; FPU - DCD CRS_IRQHandler ; CRS interrupt - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_PVM_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_IRQHandler [WEAK] - EXPORT DMA1_Channel5_IRQHandler [WEAK] - EXPORT DMA1_Channel6_IRQHandler [WEAK] - EXPORT DMA1_Channel7_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT SDMMC1_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Channel1_IRQHandler [WEAK] - EXPORT DMA2_Channel2_IRQHandler [WEAK] - EXPORT DMA2_Channel3_IRQHandler [WEAK] - EXPORT DMA2_Channel4_IRQHandler [WEAK] - EXPORT DMA2_Channel5_IRQHandler [WEAK] - EXPORT COMP_IRQHandler [WEAK] - EXPORT LPTIM1_IRQHandler [WEAK] - EXPORT LPTIM2_IRQHandler [WEAK] - EXPORT DMA2_Channel6_IRQHandler [WEAK] - EXPORT DMA2_Channel7_IRQHandler [WEAK] - EXPORT LPUART1_IRQHandler [WEAK] - EXPORT QUADSPI_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT SAI1_IRQHandler [WEAK] - EXPORT SWPMI1_IRQHandler [WEAK] - EXPORT TSC_IRQHandler [WEAK] - EXPORT RNG_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - EXPORT CRS_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_PVM_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_IRQHandler -DMA1_Channel4_IRQHandler -DMA1_Channel5_IRQHandler -DMA1_Channel6_IRQHandler -DMA1_Channel7_IRQHandler -ADC1_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM15_IRQHandler -TIM1_UP_TIM16_IRQHandler -TIM1_TRG_COM_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -SDMMC1_IRQHandler -SPI3_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Channel1_IRQHandler -DMA2_Channel2_IRQHandler -DMA2_Channel3_IRQHandler -DMA2_Channel4_IRQHandler -DMA2_Channel5_IRQHandler -COMP_IRQHandler -LPTIM1_IRQHandler -LPTIM2_IRQHandler -DMA2_Channel6_IRQHandler -DMA2_Channel7_IRQHandler -LPUART1_IRQHandler -QUADSPI_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -SAI1_IRQHandler -SWPMI1_IRQHandler -TSC_IRQHandler -RNG_IRQHandler -FPU_IRQHandler -CRS_IRQHandler - - B . - - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END +/** + ****************************************************************************** + * @file startup_stm32l431xx.s + * @author MCD Application Team + * @brief STM32L431xx devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* Set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_PVM_IRQHandler + .word TAMP_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word CAN1_TX_IRQHandler + .word CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word 0 + .word 0 + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SDMMC1_IRQHandler + .word 0 + .word SPI3_IRQHandler + .word 0 + .word 0 + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word 0 + .word 0 + .word 0 + .word COMP_IRQHandler + .word LPTIM1_IRQHandler + .word LPTIM2_IRQHandler + .word 0 + .word DMA2_Channel6_IRQHandler + .word DMA2_Channel7_IRQHandler + .word LPUART1_IRQHandler + .word QUADSPI_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word SAI1_IRQHandler + .word 0 + .word SWPMI1_IRQHandler + .word TSC_IRQHandler + .word 0 + .word 0 + .word RNG_IRQHandler + .word FPU_IRQHandler + .word CRS_IRQHandler + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak SWPMI1_IRQHandler + .thumb_set SWPMI1_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler diff --git a/Mcu/l431/openocd.cfg b/Mcu/l431/openocd.cfg new file mode 100644 index 000000000..aa6305a2d --- /dev/null +++ b/Mcu/l431/openocd.cfg @@ -0,0 +1,7 @@ +# config for openocd for STM32G431 MCUs +source [find interface/stlink.cfg] +source [find target/stm32l4x.cfg] + +# use -gdb-max-connections to allow for live watch in vscode +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 -gdb-max-connections 4 +init diff --git a/bootloader/main.c b/bootloader/main.c index e2abd0df7..a1de3dbe3 100644 --- a/bootloader/main.c +++ b/bootloader/main.c @@ -22,6 +22,9 @@ // analyser on the input pin) //#define BOOTLOADER_TEST_CLOCK +// when there is no app fw yet, disable jump() +//#define DISABLE_JUMP + #include #define STM32_FLASH_START 0x08000000 @@ -135,6 +138,7 @@ static void delayMicroseconds(uint32_t micros) */ static void jump() { +#ifndef DISABLE_JUMP __disable_irq(); JumpAddress = *(__IO uint32_t*) (APPLICATION_ADDRESS + 4); uint8_t value = *(uint8_t*)(EEPROM_START_ADD); @@ -147,6 +151,7 @@ static void jump() __set_MSP(*(__IO uint32_t*) APPLICATION_ADDRESS); JumpToApplication(); +#endif } diff --git a/l431makefile.mk b/l431makefile.mk new file mode 100644 index 000000000..b739523b0 --- /dev/null +++ b/l431makefile.mk @@ -0,0 +1,44 @@ +MCU := L431 +PART := STM32L431xx + +TARGETS_$(MCU) := \ + VIMDRONES_$(MCU) + +HAL_FOLDER_$(MCU) := $(HAL_FOLDER)/$(call lc,$(MCU)) + +MCU_$(MCU) := -mcpu=cortex-m4 -mthumb -g -gdwarf-2 +LDSCRIPT_$(MCU) := $(wildcard $(HAL_FOLDER_$(MCU))/*.ld) + +SRC_BASE_DIR_$(MCU) := \ + $(HAL_FOLDER_$(MCU))/Startup \ + $(HAL_FOLDER_$(MCU))/Drivers/STM32L4xx_HAL_Driver/Src + +SRC_DIR_$(MCU) := \ + $(SRC_BASE_DIR_$(MCU)) \ + $(HAL_FOLDER_$(MCU))/Src + +CFLAGS_$(MCU) := \ + -I$(HAL_FOLDER_$(MCU))/Inc \ + -I$(HAL_FOLDER_$(MCU))/Drivers/STM32L4xx_HAL_Driver/Inc \ + -I$(HAL_FOLDER_$(MCU))/Drivers/CMSIS/Include \ + -I$(HAL_FOLDER_$(MCU))/Drivers/CMSIS/Device/ST/STM32L4xx/Include + +CFLAGS_$(MCU) += \ + -DHSE_VALUE=8000000 \ + -D$(PART) \ + -DHSE_STARTUP_TIMEOUT=100 \ + -DLSE_STARTUP_TIMEOUT=5000 \ + -DLSE_VALUE=32768 \ + -DDATA_CACHE_ENABLE=1 \ + -DINSTRUCTION_CACHE_ENABLE=0 \ + -DVDD_VALUE=3300 \ + -DLSI_VALUE=32000 \ + -DHSI_VALUE=16000000 \ + -DUSE_FULL_LL_DRIVER \ + -DPREFETCH_ENABLE=1 + +SRC_$(MCU) := $(foreach dir,$(SRC_DIR_$(MCU)),$(wildcard $(dir)/*.[cs])) +SRC_$(MCU)_BL := $(foreach dir,$(SRC_BASE_DIR_$(MCU)),$(wildcard $(dir)/*.[cs])) \ + $(HAL_FOLDER_$(MCU))/Src/eeprom.c \ + $(HAL_FOLDER_$(MCU))/Src/system_stm32l4xx.c \ + $(wildcard $(HAL_FOLDER_$(MCU))/Src/*_it.c)