diff --git a/amaranth/build/plat.py b/amaranth/build/plat.py
index 02dbbaa3b3..0baa83474a 100644
--- a/amaranth/build/plat.py
+++ b/amaranth/build/plat.py
@@ -5,6 +5,7 @@
 import textwrap
 import re
 import jinja2
+import warnings
 
 from .. import __version__
 from .._toolchain import *
@@ -45,11 +46,25 @@ def default_clk_constraint(self):
 
     @property
     def default_clk_frequency(self):
+        # TODO(amaranth-0.7): remove
+        warnings.warn(
+            f"Per RFC 66, `default_clk_frequency` is deprecated. Use `default_clk_period` instead."
+            f" instead.",
+            DeprecationWarning, stacklevel=1)
+
+        constraint = self.default_clk_constraint
+        if constraint is None:
+            raise AttributeError("Platform '{}' does not constrain its default clock"
+                                 .format(type(self).__qualname__))
+        return constraint.period.hertz
+
+    @property
+    def default_clk_period(self):
         constraint = self.default_clk_constraint
         if constraint is None:
             raise AttributeError("Platform '{}' does not constrain its default clock"
                                  .format(type(self).__qualname__))
-        return constraint.frequency
+        return constraint.period
 
     def add_file(self, filename, content):
         if not isinstance(filename, str):
diff --git a/amaranth/vendor/_siliconblue.py b/amaranth/vendor/_siliconblue.py
index 4f4e828dc8..3c245e4b7b 100644
--- a/amaranth/vendor/_siliconblue.py
+++ b/amaranth/vendor/_siliconblue.py
@@ -382,7 +382,7 @@ def create_missing_domain(self, name):
                                          i_CLKHFPU=1,
                                          p_CLKHF_DIV=f"0b{self.hfosc_div:02b}",
                                          o_CLKHF=clk_i)
-                delay = int(100e-6 * self.default_clk_frequency)
+                delay = Period(us=100) // self.default_clk_period
             # Internal low-speed clock: 10 KHz.
             elif self.default_clk == "SB_LFOSC":
                 clk_i = Signal()
@@ -390,13 +390,13 @@ def create_missing_domain(self, name):
                                          i_CLKLFEN=1,
                                          i_CLKLFPU=1,
                                          o_CLKLF=clk_i)
-                delay = int(100e-6 * self.default_clk_frequency)
+                delay = Period(us=100) // self.default_clk_period
             # User-defined clock signal.
             else:
                 clk_io = self.request(self.default_clk, dir="-")
                 m.submodules.clk_buf = clk_buf = io.Buffer("i", clk_io)
                 clk_i = clk_buf.i
-                delay = int(15e-6 * self.default_clk_frequency)
+                delay = Period(us=15) // self.default_clk_period
 
             if self.default_rst is not None:
                 rst_io = self.request(self.default_rst, dir="-")
diff --git a/docs/_code/led_blinker.py b/docs/_code/led_blinker.py
index a450c1f5a5..6c27595208 100644
--- a/docs/_code/led_blinker.py
+++ b/docs/_code/led_blinker.py
@@ -7,7 +7,7 @@ def elaborate(self, platform):
 
         led = platform.request("led")
 
-        half_freq = int(platform.default_clk_frequency // 2)
+        half_freq = int(platform.default_clk_period.hertz // 2)
         timer = Signal(range(half_freq + 1))
 
         with m.If(timer == half_freq):