From 6dfed2ed70cf54d85c05c277090af5eef0ef6485 Mon Sep 17 00:00:00 2001
From: Catherine <whitequark@whitequark.org>
Date: Tue, 5 Sep 2023 22:26:52 +0000
Subject: [PATCH] lib.fifo: annotate for use with CLI. (WIP)

---
 amaranth/lib/fifo.py     | 20 ++++++++++++++++----
 amaranth_cli/__init__.py |  7 ++++---
 2 files changed, 20 insertions(+), 7 deletions(-)

diff --git a/amaranth/lib/fifo.py b/amaranth/lib/fifo.py
index 4fd6f6ccca..5df42241ee 100644
--- a/amaranth/lib/fifo.py
+++ b/amaranth/lib/fifo.py
@@ -3,6 +3,7 @@
 from .. import *
 from ..asserts import *
 from .._utils import log2_int
+from .wiring import Signature, In, Out
 from .coding import GrayEncoder, GrayDecoder
 from .cdc import FFSynchronizer, AsyncFFSynchronizer
 
@@ -64,7 +65,7 @@ class FIFOInterface:
     w_attributes="",
     r_attributes="")
 
-    def __init__(self, *, width, depth, fwft):
+    def __init__(self, *, width: int, depth: int, fwft):
         if not isinstance(width, int) or width < 0:
             raise TypeError("FIFO width must be a non-negative integer, not {!r}"
                             .format(width))
@@ -85,6 +86,17 @@ def __init__(self, *, width, depth, fwft):
         self.r_en   = Signal()
         self.r_level = Signal(range(depth + 1))
 
+    @property
+    def signature(self):
+        return Signature({
+            "w_data": In(self.width),
+            "w_rdy":  Out(1),
+            "w_en":   In(1),
+            "r_data": Out(self.width),
+            "r_rdy":  Out(1),
+            "w_en":   In(1),
+        })
+
 
 def _incr(signal, modulo):
     if modulo == 2 ** len(signal):
@@ -116,7 +128,7 @@ class SyncFIFO(Elaboratable, FIFOInterface):
     r_attributes="",
     w_attributes="")
 
-    def __init__(self, *, width, depth, fwft=True):
+    def __init__(self, *, width: int, depth: int, fwft=True):
         super().__init__(width=width, depth=depth, fwft=fwft)
 
         self.level = Signal(range(depth + 1))
@@ -220,7 +232,7 @@ class SyncFIFOBuffered(Elaboratable, FIFOInterface):
     r_attributes="",
     w_attributes="")
 
-    def __init__(self, *, width, depth):
+    def __init__(self, *, width: int, depth: int):
         super().__init__(width=width, depth=depth, fwft=True)
 
         self.level = Signal(range(depth + 1))
@@ -295,7 +307,7 @@ class AsyncFIFO(Elaboratable, FIFOInterface):
     """.strip(),
     w_attributes="")
 
-    def __init__(self, *, width, depth, r_domain="read", w_domain="write", exact_depth=False):
+    def __init__(self, *, width: int, depth: int, r_domain="read", w_domain="write", exact_depth=False):
         if depth != 0:
             try:
                 depth_bits = log2_int(depth, need_pow2=exact_depth)
diff --git a/amaranth_cli/__init__.py b/amaranth_cli/__init__.py
index 96d8eb0ddb..af42323697 100644
--- a/amaranth_cli/__init__.py
+++ b/amaranth_cli/__init__.py
@@ -52,7 +52,7 @@ def component(reference):
         dest="component", type=component)
     op_generate.add_argument(
         "-p", "--param", metavar=("NAME", "VALUE"), help="parameter(s) for the component",
-        dest="params", nargs=2, type=str, action="append")
+        dest="params", nargs=2, type=str, action="append", default=[])
     gen_language = op_generate.add_subparsers(
         metavar="LANGUAGE", help="language to generate code in",
         dest="language", required=True)
@@ -111,8 +111,9 @@ def dep_audit_hook(event, args):
     if args.operation in ("generate", "gen", "g"):
         if args.language == "verilog":
             # Generate Verilog file.
-            from amaranth.back import verilog
-            args.verilog_file.write(verilog.convert(component))
+            if args.verilog_file:
+                from amaranth.back import verilog
+                args.verilog_file.write(verilog.convert(component))
 
             # Generate dependency file.
             if args.verilog_file and args.dep_file: