Reset CRC start and valid signals on use so they don't get processed …

…for multiple clocks
amaranth-lang · Oct 10, 2024 · e5fa582 · e5fa582
1 parent b6bf515
commit e5fa582
Showing 1 changed file with 5 additions and 1 deletion.
diff --git a/amaranth/lib/crc/__init__.py b/amaranth/lib/crc/__init__.py
@@ -346,8 +346,12 @@ def elaborate(self, platform):
                     if self._matrix_g[j][i]:
                         bit ^= data_in[j]
                 m.d.sync += crc_reg[i].eq(bit)
+            m.d.sync += self.valid.eq(0)
         with m.Elif(self.start):
-            m.d.sync += crc_reg.eq(self._initial_crc)
+            m.d.sync += [
+                crc_reg.eq(self._initial_crc),
+                self.start.eq(0)
+            ]
 
         # Check for residue match, indicating a valid codeword.
         if self._reflect_output: