From e5fa5823773ea7b3b855dd0af8b6e8ad8989d278 Mon Sep 17 00:00:00 2001
From: John Kelley <john@kelley.ca>
Date: Thu, 10 Oct 2024 01:53:33 -0400
Subject: [PATCH] Reset CRC start and valid signals on use so they don't get
 processed for multiple clocks

---
 amaranth/lib/crc/__init__.py | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/amaranth/lib/crc/__init__.py b/amaranth/lib/crc/__init__.py
index 1420a4424..35b6a33a2 100644
--- a/amaranth/lib/crc/__init__.py
+++ b/amaranth/lib/crc/__init__.py
@@ -346,8 +346,12 @@ def elaborate(self, platform):
                     if self._matrix_g[j][i]:
                         bit ^= data_in[j]
                 m.d.sync += crc_reg[i].eq(bit)
+            m.d.sync += self.valid.eq(0)
         with m.Elif(self.start):
-            m.d.sync += crc_reg.eq(self._initial_crc)
+            m.d.sync += [
+                crc_reg.eq(self._initial_crc),
+                self.start.eq(0)
+            ]
 
         # Check for residue match, indicating a valid codeword.
         if self._reflect_output: