From c65383c3c6b7f3704cc2216244bb05ef9530dc43 Mon Sep 17 00:00:00 2001 From: Stanca Pop Date: Thu, 20 Jul 2023 14:05:11 +0300 Subject: [PATCH] Add cn0585 custom targeting --- .../CN0585_streaming_axi4lite_read_write.m | 0 ...0585_host_axi4_lite_read_write_example.slx | Bin .../zynq-zed-adv7511-cn0585.dts | 269 ++++++++++++++++++ .../+common/add_io.m | 17 ++ .../hdlcoder_ref_design_customization.m | 20 ++ .../+common/plugin_board.m | 29 ++ .../+common/plugin_rd.m | 110 +++++++ .../+zed/+tx/add_tx_io.m | 107 +++++++ .../+tx/hdlcoder_ref_design_customization.m | 20 ++ .../+zed/+tx/plugin_board.m | 9 + .../+zed/+tx/plugin_rd.m | 8 + .../hdlworkflow_cn0585_gpio_zed_tx.m | 38 +++ .../testModel_Tx16and8.slx | Bin 0 -> 45619 bytes .../cn0585_fmcz/cn0585_hdl/adi_build.tcl | 59 ++++ .../cn0585_fmcz/cn0585_hdl/build_bsp.sh | 88 ++++++ .../cn0585_fmcz/cn0585_hdl/fh_preprocess.tcl | 6 + .../cn0585_hdl/matlab_processors.tcl | 138 +++++++++ .../cn0585_fmcz/cn0585_hdl/ports.json | 176 ++++++++++++ .../cn0585_hdl/system_project_rxtx.tcl | 35 +++ .../testModel_Tx16and8.slx | Bin 0 -> 45619 bytes 20 files changed, 1129 insertions(+) rename pcx_examples/streaming/cn0585_fmcz/{ => cn0585_axi4_lite_rw_demo}/CN0585_streaming_axi4lite_read_write.m (100%) rename pcx_examples/streaming/cn0585_fmcz/{ => cn0585_axi4_lite_rw_demo}/cn0585_host_axi4_lite_read_write_example.slx (100%) create mode 100644 pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_axi4_lite_demo/zynq-zed-adv7511-cn0585.dts create mode 100644 pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/add_io.m create mode 100644 pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/hdlcoder_ref_design_customization.m create mode 100644 pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/plugin_board.m create mode 100644 pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/plugin_rd.m create mode 100644 pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/add_tx_io.m create mode 100644 pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/hdlcoder_ref_design_customization.m create mode 100644 pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/plugin_board.m create mode 100644 pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/plugin_rd.m create mode 100644 pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/hdlworkflow_cn0585_gpio_zed_tx.m create mode 100644 pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/testModel_Tx16and8.slx create mode 100644 pcx_examples/targeting/cn0585_fmcz/cn0585_hdl/adi_build.tcl create mode 100755 pcx_examples/targeting/cn0585_fmcz/cn0585_hdl/build_bsp.sh create mode 100644 pcx_examples/targeting/cn0585_fmcz/cn0585_hdl/fh_preprocess.tcl create mode 100755 pcx_examples/targeting/cn0585_fmcz/cn0585_hdl/matlab_processors.tcl create mode 100755 pcx_examples/targeting/cn0585_fmcz/cn0585_hdl/ports.json create mode 100644 pcx_examples/targeting/cn0585_fmcz/cn0585_hdl/system_project_rxtx.tcl create mode 100644 pcx_examples/targeting/cn0585_fmcz/cn0585_led_sw_gpio_control_demo/testModel_Tx16and8.slx diff --git a/pcx_examples/streaming/cn0585_fmcz/CN0585_streaming_axi4lite_read_write.m b/pcx_examples/streaming/cn0585_fmcz/cn0585_axi4_lite_rw_demo/CN0585_streaming_axi4lite_read_write.m similarity index 100% rename from pcx_examples/streaming/cn0585_fmcz/CN0585_streaming_axi4lite_read_write.m rename to pcx_examples/streaming/cn0585_fmcz/cn0585_axi4_lite_rw_demo/CN0585_streaming_axi4lite_read_write.m diff --git a/pcx_examples/streaming/cn0585_fmcz/cn0585_host_axi4_lite_read_write_example.slx b/pcx_examples/streaming/cn0585_fmcz/cn0585_axi4_lite_rw_demo/cn0585_host_axi4_lite_read_write_example.slx similarity index 100% rename from pcx_examples/streaming/cn0585_fmcz/cn0585_host_axi4_lite_read_write_example.slx rename to pcx_examples/streaming/cn0585_fmcz/cn0585_axi4_lite_rw_demo/cn0585_host_axi4_lite_read_write_example.slx diff --git a/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_axi4_lite_demo/zynq-zed-adv7511-cn0585.dts b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_axi4_lite_demo/zynq-zed-adv7511-cn0585.dts new file mode 100644 index 0000000..d2260bb --- /dev/null +++ b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_axi4_lite_demo/zynq-zed-adv7511-cn0585.dts @@ -0,0 +1,269 @@ +/dts-v1/; + +#include "zynq-zed.dtsi" +#include "zynq-zed-adv7511.dtsi" +#include +#include +#include + +/ { + clocks { + ext_clk: clock@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <120000000>; + }; + }; + + one-bit-adc-dac@0 { + compatible = "adi,one-bit-adc-dac"; + #address-cells = <1>; + #size-cells = <0>; + + in-gpios = <&gpio_mux 4 GPIO_ACTIVE_HIGH>, + <&gpio_mux 5 GPIO_ACTIVE_HIGH>; + out-gpios = <&gpio_mux 3 GPIO_ACTIVE_HIGH>, + <&gpio_mux 2 GPIO_ACTIVE_HIGH>, + <&gpio_mux 1 GPIO_ACTIVE_HIGH>, + <&gpio_mux 0 GPIO_ACTIVE_HIGH>, + <&gpio_mux 6 GPIO_ACTIVE_HIGH>, + <&gpio_mux 7 GPIO_ACTIVE_HIGH>, + <&gpio_mux 11 GPIO_ACTIVE_HIGH>, + <&gpio_mux 12 GPIO_ACTIVE_HIGH>, + <&gpio_mux 13 GPIO_ACTIVE_HIGH>, + <&gpio_mux 14 GPIO_ACTIVE_HIGH>; + + channel@0 { + reg = <0>; + label = "GPIO4_VIO"; + }; + channel@1 { + reg = <1>; + label = "GPIO5_VIO"; + }; + channel@2 { + reg = <2>; + label = "GPIO0_VIO"; + }; + channel@3 { + reg = <3>; + label = "GPIO1_VIO"; + }; + channel@4 { + reg = <4>; + label = "GPIO2_VIO"; + }; + channel@5 { + reg = <5>; + label = "GPIO3_VIO"; + }; + channel@6 { + reg = <6>; + label = "GPIO6_VIO"; + }; + channel@7 { + reg = <7>; + label = "GPIO7_VIO"; + }; + channel@8 { + reg = <8>; + label = "PAD_ADC0"; + }; + channel@9 { + reg = <9>; + label = "PAD_ADC1"; + }; + channel@10 { + reg = <10>; + label = "PAD_ADC2"; + }; + channel@11 { + reg = <11>; + label = "PAD_ADC3"; + }; + }; +}; + +&fpga_axi { + axi_pwm_gen: pwm@44B10000 { + compatible = "adi,axi-pwmgen"; + reg = <0x44B10000 0x1000>; + label = "ltc2387_if"; + #pwm-cells = <2>; + clocks = <&ext_clk>; + }; + + ref_clk: clk@44B00000 { + compatible = "adi,axi-clkgen-2.00.a"; + reg = <0x44B00000 0x10000>; + #clock-cells = <0>; + clocks = <&clkc 15>, <&clkc 15>; + clock-names = "s_axi_aclk", "clkin1"; + clock-output-names = "ref_clk"; + }; + + rx_dma: dmac@44A40000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x44A40000 0x1000>; + #dma-cells = <1>; + interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc 15>; + + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + + dma-channel@0 { + reg = <0>; + adi,source-bus-width = <64>; + adi,source-bus-type = <2>; + adi,destination-bus-width = <64>; + adi,destination-bus-type = <0>; + }; + }; + }; + + ltc2387@0{ + compatible = "ltc2387-16-x4"; + pwms = <&axi_pwm_gen 0 0 + &axi_pwm_gen 1 0>; + pwm-names = "cnv", "clk_en"; + clocks = <&ref_clk>; + dmas = <&rx_dma 0>; + dma-names = "rx"; + adi,use-two-lanes; + }; + + qspi0: spi@0x44B20000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x44B20000 0x1000>; + num-cs = <0x2>; + compatible = "xlnx,xps-spi-2.00.a"; + bits-per-word = <16>; + fifo-size = <16>; + clock-names = "ext_spi_clk", "s_axi_aclk"; + clocks = <&clkc 15>, <&clkc 15>; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&intc>; + interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; + + gpio_mux: max7301@0 { + compatible = "max7301"; + reg = <0>; + spi-max-frequency = <20000000>; + #gpio-cells = <2>; + gpio-controller; + }; + }; + + dac0_tx_dma: tx-dmac@0x44D30000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x44D30000 0x10000>; + #dma-cells = <1>; + interrupt-parent = <&intc>; + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc 15>; + + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + + dma-channel@0 { + reg = <0>; + adi,source-bus-width = <32>; + adi,source-bus-type = <0>; + adi,destination-bus-width = <32>; + adi,destination-bus-type = <1>; + }; + }; + }; + + dac1_tx_dma: tx-dmac@0x44E30000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x44E30000 0x10000>; + #dma-cells = <1>; + interrupt-parent = <&intc>; + interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc 15>; + + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + + dma-channel@0 { + reg = <0>; + adi,source-bus-width = <32>; + adi,source-bus-type = <0>; + adi,destination-bus-width = <32>; + adi,destination-bus-type = <1>; + }; + }; + }; + + axi_ad3552r_0: axi-ad3552r-0@44d04000 { + compatible = "adi,axi-ad3552r"; + reg = <0x44d04000 0x1000>; + + reset-gpios = <&gpio0 90 GPIO_ACTIVE_LOW>; + + clocks = <&ref_clk>; + + dmas = <&dac0_tx_dma 0>; + dma-names = "tx"; + }; + + axi_ad3552r_1: axi-ad3552r-1@44e04000 { + compatible = "adi,axi-ad3552r"; + reg = <0x44e04000 0x1000>; + + clocks = <&ref_clk>; + + dmas = <&dac1_tx_dma 0>; + dma-names = "tx"; + }; + + mwipcore@43c00000 { + compatible = "mathworks,mwipcore-v3.00"; + reg = <0x43C00000 0xfffff>; + #address-cells = <1>; + #size-cells = <0>; + mmwr-channel@0{ + reg = <0x0>; + compatible = "mathworks,mm-write-channel-v1.00"; + }; + mmrd-channel@1{ + reg = <0x1>; + compatible = "mathworks,mm-read-channel-v1.00"; + }; + + + }; + + i2c@41620000 { + compatible = "xlnx,axi-iic-1.01.b", "xlnx,xps-iic-2.00.a"; + reg = <0x41620000 0x10000>; + interrupt-parent = <&intc>; + interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc 15>; + clock-names = "pclk"; + + #size-cells = <0>; + #address-cells = <1>; + + eeprom@50 { + compatible = "at24,24c02"; + reg = <0x50>; + }; + eeprom2@54 { + compatible = "at24,24c02"; + reg = <0x54>; + }; + ad7291_1@20 { + label = "ADC_I2C_1"; + compatible = "adi,ad7291"; + reg = <0x20>; + }; + + }; +}; diff --git a/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/add_io.m b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/add_io.m new file mode 100644 index 0000000..6cd8cdc --- /dev/null +++ b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/add_io.m @@ -0,0 +1,17 @@ +% function add_io(hRD,project,fpga,type) +% +% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% % Add AXI4 and AXI4-Lite slave interfaces +% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% out = AnalogDevices.get_memory_axi_interface_info(fpga,lower(project)); +% hRD.addAXI4SlaveInterface( ... +% 'InterfaceConnection', out.InterfaceConnection, ... +% 'BaseAddress', out.BaseAddress, ... +% 'MasterAddressSpace', out.MasterAddressSpace); +% +% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% % Add Reference design interfaces +% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% AnalogDevices.add_io_ports(hRD,lower(project),lower(type),lower(fpga)); +% +% end diff --git a/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/hdlcoder_ref_design_customization.m b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/hdlcoder_ref_design_customization.m new file mode 100644 index 0000000..31e4cea --- /dev/null +++ b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/hdlcoder_ref_design_customization.m @@ -0,0 +1,20 @@ +function [rd,boardName] = hdlcoder_ref_design_customization +% Reference design plugin registration file +% 1. The registration file with this name inside of a board plugin folder +% will be picked up +% 2. Any registration file with this name on MATLAB path will also be picked up +% 3. The registration file returns a cell array pointing to the location of +% the reference design plugins +% 4. The registration file also returns its associated board name +% 5. Reference design plugin must be a package folder accessible from +% MATLAB path, and contains a reference design definition file + +% Copyright 2013-2014 The MathWorks, Inc. + +rd = {... + 'AnalogDevicesDemo.cn0585_led_sw_gpio_control_demo.zed.tx.plugin_rd', ... + }; + +boardName = 'AnalogDevices CN0585 GPIO Control'; + +end diff --git a/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/plugin_board.m b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/plugin_board.m new file mode 100644 index 0000000..27d0b67 --- /dev/null +++ b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/plugin_board.m @@ -0,0 +1,29 @@ +function hB = plugin_board(BoardName) +% Use Plugin API to create board plugin object + +% Copyright 2015 The MathWorks, Inc. + +hB = hdlcoder.Board; + +% Target Board Information +hB.BoardName = sprintf('AnalogDevices CN0585 GPIO Control'); + +% FPGA Device +hB.FPGAVendor = 'Xilinx'; +hB.FPGAFamily = 'Zynq'; + +% Determine the device based on the board + +hB.FPGADevice = sprintf('xc7%s', 'z020'); +hB.FPGAPackage = 'clg484'; +hB.FPGASpeed = '-1'; +hB.FPGAFamily = 'Zynq'; + +% Tool Info +hB.SupportedTool = {'Xilinx Vivado'}; + +% FPGA JTAG chain position +hB.JTAGChainPosition = 2; + +%% Add interfaces +% Standard "External Port" interface diff --git a/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/plugin_rd.m b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/plugin_rd.m new file mode 100644 index 0000000..5bc799a --- /dev/null +++ b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/plugin_rd.m @@ -0,0 +1,110 @@ +function hRD = plugin_rd(board, design) +% Reference design definition + +% Copyright 2014-2015 The MathWorks, Inc. + +% pname = upper(project); +% ppath = project; +% if strcmpi(project, 'cn0585') +% ppath = 'cn0585_fmcz'; +% end + +board = 'zed'; +design = 'Tx'; + +hRD = hdlcoder.ReferenceDesign('SynthesisTool', 'Xilinx Vivado'); + +% This is the base reference design that other RDs can build upon +hRD.ReferenceDesignName = sprintf('%s (%s)', upper(board), design); + +% Determine the board name based on the design +hRD.BoardName = sprintf('AnalogDevices CN0585 GPIO Control'); + +% Tool information +hRD.SupportedToolVersion = {'2022.2'}; + +% Get the root directories +rootDirExample = fileparts(strtok(mfilename('fullpath'), '+')); +tmp = strsplit(rootDirExample,filesep); + +if isunix + rootDir = fullfile(filesep,tmp{1:end-3}); +else + rootDir = fullfile(tmp{1:end-3}); +end +rootDirBSP = fullfile('hdl','vendor','AnalogDevices','vivado'); + +% Design files are shared +hRD.SharedRD = true; +hRD.SharedRDFolder = rootDir; + +%% Set top level project pieces +hRD.addParameter( ... + 'ParameterID', 'project', ... + 'DisplayName', 'HDL Project Subfolder', ... + 'DefaultValue', 'cn0585_fmcz'); + +hRD.addParameter( ... + 'ParameterID', 'carrier', ... + 'DisplayName', 'HDL Project Carrier', ... + 'DefaultValue', 'zed'); + +%% Add custom design files +hRD.addCustomVivadoDesign( ... + 'CustomBlockDesignTcl', fullfile('pcx_examples', 'targeting', 'cn0585_fmcz', 'cn0585_hdl', 'system_project_rxtx.tcl')); + +%% Standard reference design pieces +hRD.BlockDesignName = 'system'; + +% custom source files +hRD.CustomFiles = {... + fullfile('projects')..., + fullfile('library')..., + fullfile('scripts')..., + }; + +% custom source files +hRD.CustomFiles = {... + fullfile(rootDirBSP, 'scripts')..., + fullfile(rootDirBSP, 'library')..., + fullfile(rootDirBSP, 'library','xilinx')..., + fullfile(rootDirBSP, 'projects','common')..., + fullfile(rootDirBSP, 'projects','scripts')..., + fullfile(rootDirBSP, 'projects','cn0585_fmcz')..., + fullfile(rootDirBSP, 'projects','cn0585_fmcz', 'common')..., + fullfile(rootDirBSP, 'projects','cn0585_fmcz', 'zed')..., + fullfile('pcx_examples', 'targeting', 'cn0585_fmcz', 'cn0585_hdl')..., + }; + +hRD.addParameter( ... + 'ParameterID', 'ref_design', ... + 'DisplayName', 'Reference Type', ... + 'DefaultValue', lower(strrep(design, ' & ',''))); + +hRD.addParameter( ... + 'ParameterID', 'fpga_board', ... + 'DisplayName', 'FPGA Boad', ... + 'DefaultValue', upper(board)); + +hRD.addParameter( ... + 'ParameterID', 'preprocess', ... + 'DisplayName', 'Preprocess', ... + 'DefaultValue', 'on'); +hRD.addParameter( ... + 'ParameterID', 'preprocess_script', ... + 'DisplayName', 'Preprocess Script', ... + 'DefaultValue', fullfile('pcx_examples', 'targeting', 'cn0585_fmcz','cn0585_hdl','fh_preprocess.tcl')); + +hRD.addParameter( ... + 'ParameterID', 'postprocess', ... + 'DisplayName', 'Postprocess', ... + 'DefaultValue', 'off'); + +%% Add IO +%AnalogDevices.add_io(hRD,'cn0585_led_sw_gpio_control_demo',board,design); + +%% Add interfaces +% add clock interface +hRD.addClockInterface( ... + 'ClockConnection', 'axi_clkgen/clk_0', ... + 'ResetConnection', 'sampling_clk_rstgen/peripheral_aresetn'); diff --git a/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/add_tx_io.m b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/add_tx_io.m new file mode 100644 index 0000000..a5c9ae0 --- /dev/null +++ b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/add_tx_io.m @@ -0,0 +1,107 @@ +function add_tx_io(hRD) + +% add AXI4 and AXI4-Lite slave interfaces +hRD.addAXI4SlaveInterface( ... + 'InterfaceConnection', 'axi_cpu_interconnect/M20_AXI', ... + 'BaseAddress', '0x43C00000', ... + 'MasterAddressSpace', 'sys_ps7/Data'); + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% Tx Reference design interfaces +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 0 IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'axi_ltc2387_0_adc_data', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ltc2387_0/adc_data', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 1 IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'axi_ltc2387_1_adc_data', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ltc2387_1/adc_data', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 2 IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'axi_ltc2387_2_adc_data', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ltc2387_2/adc_data', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 3 IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'axi_ltc2387_3_adc_data', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ltc2387_3/adc_data', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Load Tx Data OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'axi_ad3552r_0_valid_in_a', ... + 'PortWidth', 1, ... + 'InterfaceConnection', 'axi_ad3552r_0/valid_in_a', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Valid Tx Data IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'axi_ltc2387_0_adc_valid', ... + 'PortWidth', 1, ... + 'InterfaceConnection', 'axi_ltc2387_0/adc_valid', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'CN0585 DAC Data 0 OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'axi_ad3552r_0_data_in_a', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ad3552r_0/data_in_a', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'CN0585 DAC Data 1 OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'axi_ad3552r_0_data_in_b', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ad3552r_0/data_in_b', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'CN0585 DAC Data 2 OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'axi_ad3552r_1_data_in_a', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ad3552r_1/data_in_a', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'CN0585 DAC Data 3 OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'axi_ad3552r_1_data_in_b', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ad3552r_1/data_in_b', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'GPIO IN SW', ... + 'InterfaceType', 'IN', ... + 'PortName', 'xlslice_1_Dout', ... + 'PortWidth', 8, ... + 'InterfaceConnection', 'xlslice_1/Dout', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'GPIO OUT LED', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'xlconcat_1_In1', ... + 'PortWidth', 8, ... + 'InterfaceConnection', 'xlconcat_1/In1', ... + 'IsRequired', false); diff --git a/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/hdlcoder_ref_design_customization.m b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/hdlcoder_ref_design_customization.m new file mode 100644 index 0000000..350b2b3 --- /dev/null +++ b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/hdlcoder_ref_design_customization.m @@ -0,0 +1,20 @@ +function [rd, boardName] = hdlcoder_ref_design_customization +% Reference design plugin registration file +% 1. The registration file with this name inside of a board plugin folder +% will be picked up +% 2. Any registration file with this name on MATLAB path will also be picked up +% 3. The registration file returns a cell array pointing to the location of +% the reference design plugins +% 4. The registration file also returns its associated board name +% 5. Reference design plugin must be a package folder accessible from +% MATLAB path, and contains a reference design definition file + +% Copyright 2013-2014 The MathWorks, Inc. + +rd = {... + 'AnalogDevicesDemo.cn0585_led_sw_gpio_control_demo.zed.tx.plugin_rd', ... + }; + +boardName = 'AnalogDevicesDemo cn0585_led_sw_gpio_control AnalogDevies CN0585 GPIO Control (Tx)'; + +end diff --git a/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/plugin_board.m b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/plugin_board.m new file mode 100644 index 0000000..8e69678 --- /dev/null +++ b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/plugin_board.m @@ -0,0 +1,9 @@ +function hP = plugin_board() +% Zynq Platform PCore +% Use Plugin API to create board plugin object + +% Copyright 2015 The MathWorks, Inc. + +% Call the common board definition function +% hP = AnalogDevicesDemo.cn0585_led_sw_gpio_control_demo.common.plugin_board('AnalogDevies CN0585 GPIO Control ', 'Tx'); +hP = AnalogDevicesDemo.cn0585_led_sw_gpio_control_demo.common.plugin_board('AnalogDevies CN0585 GPIO Control'); \ No newline at end of file diff --git a/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/plugin_rd.m b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/plugin_rd.m new file mode 100644 index 0000000..f381dcf --- /dev/null +++ b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/plugin_rd.m @@ -0,0 +1,8 @@ +function hRD = plugin_rd +% Reference design definition + +% Copyright 2014-2015 The MathWorks, Inc. + +% Call the common reference design definition function +hRD = AnalogDevicesDemo.cn0585_led_sw_gpio_control_demo.common.plugin_rd('AnalogDevies CN0585 GPIO Control', 'Tx'); +AnalogDevicesDemo.cn0585_led_sw_gpio_control_demo.zed.tx.add_tx_io(hRD); diff --git a/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/hdlworkflow_cn0585_gpio_zed_tx.m b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/hdlworkflow_cn0585_gpio_zed_tx.m new file mode 100644 index 0000000..bd9e518 --- /dev/null +++ b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/hdlworkflow_cn0585_gpio_zed_tx.m @@ -0,0 +1,38 @@ +function out = hdlworkflow_cn0585_gpio_zed_tx(vivado) + +if nargin < 1 + vivado = '2022.2'; +end + +%-------------------------------------------------------------------------- +% HDL Workflow Script +% Generated with MATLAB 9.8 (R2020a) at 12:56:00 on 24/09/2020 +% This script was generated using the following parameter values: +% Filename : '/tmp/hsx-add-boot-bin-test/test/hdlworkflow_daq2_zcu102_rx.m' +% Overwrite : true +% Comments : true +% Headers : true +% DUT : 'testModel_Rx64Tx64/HDL_DUT' +% To view changes after modifying the workflow, run the following command: +% >> hWC.export('DUT','testModel_Rx64Tx64/HDL_DUT'); +%-------------------------------------------------------------------------- + +%% Load the Model +load_system('testModel_Tx16and8'); + +%% Restore the Model to default HDL parameters +hdlrestoreparams('testModel_Tx16and8/HDL_DUT'); + +%% Model HDL Parameters +%% Set Model 'testModel_Rx64Tx64' HDL parameters +hdlset_param('testModel_Tx16and8', 'HDLSubsystem', 'testModel_Tx16and8/HDL_DUT'); +hdlset_param('testModel_Tx16and8', 'ReferenceDesign', 'AnalogDevies CN0585 GPIO Control (TX)'); +hdlset_param('testModel_Tx16and8', 'SynthesisTool', 'Xilinx Vivado'); +hdlset_param('testModel_Tx16and8', 'SynthesisToolChipFamily', 'Zynq'); +hdlset_param('testModel_Tx16and8', 'SynthesisToolDeviceName', 'xc7z020-clg484-1'); +hdlset_param('testModel_Tx16and8', 'SynthesisToolPackageName', ''); +hdlset_param('testModel_Tx16and8', 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b/pcx_examples/targeting/cn0585_fmcz/cn0585_hdl/fh_preprocess.tcl @@ -0,0 +1,6 @@ +set ad_hdl_dir [pwd] + +#### Move files +file rename -force $ad_hdl_dir/hdl/vendor/AnalogDevices/vivado/scripts $ad_hdl_dir/scripts +file rename -force $ad_hdl_dir/hdl/vendor/AnalogDevices/vivado/projects $ad_hdl_dir/projects +file rename -force $ad_hdl_dir/hdl/vendor/AnalogDevices/vivado/library $ad_hdl_dir/library diff --git a/pcx_examples/targeting/cn0585_fmcz/cn0585_hdl/matlab_processors.tcl b/pcx_examples/targeting/cn0585_fmcz/cn0585_hdl/matlab_processors.tcl new file mode 100755 index 0000000..5376448 --- /dev/null +++ b/pcx_examples/targeting/cn0585_fmcz/cn0585_hdl/matlab_processors.tcl @@ -0,0 +1,138 @@ +proc preprocess_bd {project carrier rxtx} { + + puts "Preprocessing $project $carrier $rxtx" + + switch $project { + cn0585_fmcz { + # Disconnect the ADC PACK pins + delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_data] + delete_bd_objs [get_bd_nets axi_ltc2387_1_adc_data] + delete_bd_objs [get_bd_nets axi_ltc2387_2_adc_data] + delete_bd_objs [get_bd_nets axi_ltc2387_3_adc_data] + + set sys_cstring "matlab $rxtx" + sysid_gen_sys_init_file $sys_cstring + + # Disconnect adc_valid + delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_valid] + # Reconnect the adc_valid in the system + connect_bd_net [get_bd_pins axi_ltc2387_0/adc_valid] [get_bd_pins axi_ltc2387_dma/fifo_wr_en] + + if {$rxtx == "rx"} { + connect_bd_net [get_bd_pins axi_ltc2387_0/adc_data] [get_bd_pins axi_ad3552r_0/data_in_a] + connect_bd_net [get_bd_pins axi_ltc2387_1/adc_data] [get_bd_pins axi_ad3552r_0/data_in_b] + connect_bd_net [get_bd_pins axi_ltc2387_2/adc_data] [get_bd_pins axi_ad3552r_1/data_in_a] + connect_bd_net [get_bd_pins axi_ltc2387_3/adc_data] [get_bd_pins axi_ad3552r_1/data_in_b] + } + + if {$rxtx == "tx"} { + connect_bd_net [get_bd_pins axi_ltc2387_0/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_0] + connect_bd_net [get_bd_pins axi_ltc2387_1/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_1] + connect_bd_net [get_bd_pins axi_ltc2387_2/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_2] + connect_bd_net [get_bd_pins axi_ltc2387_3/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_3] + connect_bd_net [get_bd_pins axi_ltc2387_0/adc_valid] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_en] + } + + if {$rxtx == "tx" || $rxtx == "rxtx"} { + + delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_valid] + delete_bd_objs [get_bd_nets axi_ltc2387_1_adc_valid] + delete_bd_objs [get_bd_nets axi_ltc2387_2_adc_valid] + delete_bd_objs [get_bd_nets axi_ltc2387_3_adc_valid] + + # Connect dac valids together + connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_0/valid_in_b] + connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_1/valid_in_a] + connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_1/valid_in_b] + + # Remove the gpio bd connections + delete_bd_objs [get_bd_nets gpio_i_1] + delete_bd_objs [get_bd_nets sys_ps7_GPIO_O] + # Split the input gpios into 3 to separate the switches + create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 + set_property -dict [list \ + CONFIG.DIN_FROM {63} \ + CONFIG.DIN_TO {19} \ + CONFIG.DIN_WIDTH {64} \ + CONFIG.DOUT_WIDTH {45} \ + ] [get_bd_cells xlslice_0] + create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_1 + set_property -dict [list \ + CONFIG.DIN_FROM {18} \ + CONFIG.DIN_TO {11} \ + CONFIG.DIN_WIDTH {64} \ + CONFIG.DOUT_WIDTH {8} \ + ] [get_bd_cells xlslice_1] + create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_2 + set_property -dict [list \ + CONFIG.DIN_FROM {10} \ + CONFIG.DIN_TO {0} \ + CONFIG.DIN_WIDTH {64} \ + CONFIG.DOUT_WIDTH {11} \ + ] [get_bd_cells xlslice_2] + # Reconnect the input gpios + connect_bd_net [get_bd_ports gpio_i] [get_bd_pins xlslice_0/Din] + connect_bd_net [get_bd_ports gpio_i] [get_bd_pins xlslice_1/Din] + connect_bd_net [get_bd_ports gpio_i] [get_bd_pins xlslice_2/Din] + create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 + set_property CONFIG.NUM_PORTS {3} [get_bd_cells xlconcat_0] + set_property -dict [list CONFIG.IN2_WIDTH.VALUE_SRC USER CONFIG.IN1_WIDTH.VALUE_SRC USER CONFIG.IN0_WIDTH.VALUE_SRC USER] [get_bd_cells xlconcat_0] + set_property -dict [list \ + CONFIG.IN0_WIDTH {45} \ + CONFIG.IN1_WIDTH {8} \ + CONFIG.IN2_WIDTH {11} \ + ] [get_bd_cells xlconcat_0] + connect_bd_net [get_bd_pins xlslice_0/Dout] [get_bd_pins xlconcat_0/In0] + connect_bd_net [get_bd_pins xlslice_2/Dout] [get_bd_pins xlconcat_0/In2] + # Reconnect the input gpios to the ps7 + connect_bd_net [get_bd_pins sys_ps7/GPIO_I] [get_bd_pins xlconcat_0/dout] + # Split the output gpios into 3 to separate the leds + create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_3 + set_property -dict [list \ + CONFIG.DIN_FROM {63} \ + CONFIG.DIN_TO {27} \ + CONFIG.DIN_WIDTH {64} \ + CONFIG.DOUT_WIDTH {37} \ + ] [get_bd_cells xlslice_3] + create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_4 + set_property -dict [list \ + CONFIG.DIN_FROM {26} \ + CONFIG.DIN_TO {19} \ + CONFIG.DIN_WIDTH {64} \ + CONFIG.DOUT_WIDTH {8} \ + ] [get_bd_cells xlslice_4] + create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_5 + set_property -dict [list \ + CONFIG.DIN_FROM {18} \ + CONFIG.DIN_TO {0} \ + CONFIG.DIN_WIDTH {64} \ + CONFIG.DOUT_WIDTH {19} \ + ] [get_bd_cells xlslice_5] + # Reconnect the output gpios + connect_bd_net [get_bd_pins sys_ps7/GPIO_O] [get_bd_pins xlslice_3/Din] + connect_bd_net [get_bd_pins sys_ps7/GPIO_O] [get_bd_pins xlslice_4/Din] + connect_bd_net [get_bd_pins sys_ps7/GPIO_O] [get_bd_pins xlslice_5/Din] + create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_1 + set_property CONFIG.NUM_PORTS {3} [get_bd_cells xlconcat_1] + set_property -dict [list CONFIG.IN2_WIDTH.VALUE_SRC USER CONFIG.IN1_WIDTH.VALUE_SRC USER CONFIG.IN0_WIDTH.VALUE_SRC USER] [get_bd_cells xlconcat_1] + set_property -dict [list \ + CONFIG.IN0_WIDTH {37} \ + CONFIG.IN1_WIDTH {8} \ + CONFIG.IN2_WIDTH {19} \ + ] [get_bd_cells xlconcat_1] + connect_bd_net [get_bd_pins xlslice_3/Dout] [get_bd_pins xlconcat_1/In0] + connect_bd_net [get_bd_pins xlslice_5/Dout] [get_bd_pins xlconcat_1/In2] + # Reconnect the output gpios to the output port + connect_bd_net [get_bd_ports gpio_o] [get_bd_pins xlconcat_1/Dout] + + } + switch $carrier { + zed { + set_property -dict [list CONFIG.NUM_MI {21}] [get_bd_cells axi_cpu_interconnect] + connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ACLK] [get_bd_pins axi_clkgen/clk_0] + connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ARESETN] [get_bd_pins sampling_clk_rstgen/peripheral_aresetn] + } + } + } + } +} diff --git a/pcx_examples/targeting/cn0585_fmcz/cn0585_hdl/ports.json b/pcx_examples/targeting/cn0585_fmcz/cn0585_hdl/ports.json new file mode 100755 index 0000000..f972fc3 --- /dev/null +++ b/pcx_examples/targeting/cn0585_fmcz/cn0585_hdl/ports.json @@ -0,0 +1,176 @@ +{ + "cn0585": { + "chip": "CN0585", + "complex": "true", + "fpga": [ + "zed" + ], + "supported_rd": [ + "rx", + "tx", + "rx & tx" + ], + "ports": [ + { + "rx": [ + { + "input": "false", + "width": 1, + "name": "util_ltc2387_adc_pack/fifo_wr_en", + "type": "valid", + "m_name": "IP Data Valid OUT" + }, + { + "input": "false", + "width": 16, + "name": "util_ltc2387_adc_pack/fifo_wr_data_0", + "type": "data", + "m_name": "IP Data 0 OUT" + }, + { + "input": "false", + "width": 16, + "name": "util_ltc2387_adc_pack/fifo_wr_data_1", + "type": "data", + "m_name": "IP Data 1 OUT" + }, + { + "input": "false", + "width": 16, + "name": "util_ltc2387_adc_pack/fifo_wr_data_2", + "type": "data", + "m_name": "IP Data 2 OUT" + }, + { + "input": "false", + "width": 16, + "name": "util_ltc2387_adc_pack/fifo_wr_data_3", + "type": "data", + "m_name": "IP Data 3 OUT" + }, + { + "input": "true", + "width": 1, + "name": "axi_ltc2387_0/adc_valid", + "type": "valid", + "m_name": "IP Valid Rx Data IN" + }, + { + "input": "true", + "width": 16, + "name": "axi_ltc2387_0/adc_data", + "type": "data", + "m_name": "CN0585 ADC Data 0 IN" + }, + { + "input": "true", + "width": 16, + "name": "axi_ltc2387_1/adc_data", + "type": "data", + "m_name": "CN0585 ADC Data 1 IN" + }, + { + "input": "true", + "width": 16, + "name": "axi_ltc2387_2/adc_data", + "type": "data", + "m_name": "CN0585 ADC Data 2 IN" + }, + { + "input": "true", + "width": 16, + "name": "axi_ltc2387_3/adc_data", + "type": "data", + "m_name": "CN0585 ADC Data 3 IN" + } + ], + "tx": [ + { + "input": "true", + "width": 16, + "name": "axi_ltc2387_0/adc_data", + "type": "data", + "m_name": "IP Data 0 IN" + }, + { + "input": "true", + "width": 16, + "name": "axi_ltc2387_1/adc_data", + "type": "data", + "m_name": "IP Data 1 IN" + }, + { + "input": "true", + "width": 16, + "name": "axi_ltc2387_2/adc_data", + "type": "data", + "m_name": "IP Data 2 IN" + }, + { + "input": "true", + "width": 16, + "name": "axi_ltc2387_3/adc_data", + "type": "data", + "m_name": "IP Data 3 IN" + }, + { + "input": "true", + "width": 1, + "name": "axi_ltc2387_0/adc_valid", + "type": "valid", + "m_name": "IP Valid Tx Data IN" + }, + { + "input": "false", + "width": 16, + "name": "axi_ad3552r_0/data_in_a", + "type": "data", + "m_name": "CN0585 DAC Data 0 OUT" + }, + { + "input": "false", + "width": 16, + "name": "axi_ad3552r_0/data_in_b", + "type": "data", + "m_name": "CN0585 DAC Data 1 OUT" + }, + { + "input": "false", + "width": 1, + "name": "axi_ad3552r_0/valid_in_a", + "type": "valid", + "m_name": "IP Load Tx Data OUT" + }, + { + "input": "false", + "width": 16, + "name": "axi_ad3552r_1/data_in_a", + "type": "data", + "m_name": "CN0585 DAC Data 2 OUT" + }, + { + "input": "false", + "width": 16, + "name": "axi_ad3552r_1/data_in_b", + "type": "data", + "m_name": "CN0585 DAC Data 3 OUT" + }, + { + "input": "true", + "width": 8, + "name": "xlslice_1/Dout", + "type": "data", + "m_name": "IP Data 4 IN" + }, + { + "input": "false", + "width": 8, + "name": "xlconcat_1/In1", + "type": "data", + "m_name": "CN0585 DAC Data 4 OUT" + } + ] + } + ] + } +} diff --git a/pcx_examples/targeting/cn0585_fmcz/cn0585_hdl/system_project_rxtx.tcl b/pcx_examples/targeting/cn0585_fmcz/cn0585_hdl/system_project_rxtx.tcl new file mode 100644 index 0000000..d180513 --- /dev/null +++ b/pcx_examples/targeting/cn0585_fmcz/cn0585_hdl/system_project_rxtx.tcl @@ -0,0 +1,35 @@ +set start_dir [pwd] +puts "Starting Precision Toolbox HDL build" + +if {$preprocess == "on"} { + source $preprocess_script +} + +cd projects/$project/$carrier +source ../../scripts/adi_make.tcl +adi_make::lib all + +set ::env(ADI_SKIP_SYNTHESIS) 1 +set ::env(SKIP_SYNTHESIS) 1 +set ::env(ADI_MATLAB) 1 +set ::env(MATLAB) 1 +set ::env(ADI_USE_OOC_SYNTHESYS) 1 +set ::env(ADI_IGNORE_VERSION_CHECK) 1 + +source ./system_project.tcl + +# Update block design to make room for new IP +source ../../scripts/matlab_processors.tcl +preprocess_bd $project $carrier $ref_design + +if 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