diff --git a/+adi/+AD3552R/Base.m b/+adi/+AD3552R/Base.m
new file mode 100755
index 0000000..2604a01
--- /dev/null
+++ b/+adi/+AD3552R/Base.m
@@ -0,0 +1,124 @@
+classdef (Abstract) Base < ...
+ adi.common.RxTx & ...
+ matlabshared.libiio.base & ...
+ adi.common.Attribute
+ % adi.AD3552R.Tx Transmit data to the AD3552R high speed DAC
+ % The adi.AD3552R.Tx System object is a signal source that can send
+ % complex data from the AD3552R.
+ %
+ % tx = adi.AD3552R.Tx;
+ % tx = adi.AD3552R.Tx('uri','192.168.2.1');
+ %
+ % AD3552R Datasheet
+ %
+ % See also adi.CN0585.Tx
+
+ properties (Nontunable)
+ % SamplesPerFrame Samples Per Frame
+ % Number of samples per frame, specified as an even positive
+ % integer from 2 to 16,777,216. Using values less than 3660 can
+ % yield poor performance.
+ SamplesPerFrame = 2 ^ 15;
+ end
+
+ properties (Nontunable, Hidden)
+ Timeout = Inf;
+ kernelBuffersCount = 2;
+ dataTypeStr = 'uint16';
+ end
+
+ properties (Abstract, Hidden, Constant)
+ Type
+ end
+
+ properties (Hidden, Constant)
+ ComplexData = false;
+ end
+
+ properties
+ % InputSource
+ % Lists all the available input sources of the DAC.
+ % Options are: 'adc_input', 'dma_input', 'ramp_input'.
+ % Example: InputSource = 'dma_input';
+ InputSource = 'dma_input';
+ end
+
+ properties
+ % OutputRange
+ % Lists all the available voltage ranges of the output signal.
+ % Options are: '0/2.5V', '0/5V', '0/10V', '-5/+5V', '-10/+10V'.
+ % Example: OutputRange = '-10/+10V';
+ OutputRange = '-10/+10V';
+ end
+
+ properties
+ InputSourceSet = matlab.system.StringSet({...
+ 'adc_input', 'dma_input', 'ramp_input'})
+ OutputRangeSet = matlab.system.StringSet({...
+ '0/2.5V', '0/5V', '0/10V', '-5/+5V', '-10/+10V'})
+ end
+
+ methods
+ %% Constructor
+ function obj = Base(varargin)
+ % Returns the matlabshared.libiio.base object
+ coder.allowpcode('plain');
+ obj = obj@matlabshared.libiio.base(varargin{:});
+ end
+
+ % Check SamplesPerFrame
+ function set.SamplesPerFrame(obj, value)
+ validateattributes(value, {'double', 'single'}, ...
+ {'real', 'positive', 'scalar', 'finite', 'nonnan', 'nonempty', 'integer', '>', 0, '<', 2 ^ 20 + 1}, ...
+ '', 'SamplesPerFrame');
+ obj.SamplesPerFrame = value;
+ end
+
+ % Set/Get Input Source
+ function result = get.InputSource(obj)
+ result = obj.InputSource;
+ end
+
+ function set.InputSource(obj, value)
+ obj.InputSource = value;
+ end
+
+ % Set/Get Output Range
+ function result = get.OutputRange(obj)
+ result = obj.OutputRange;
+ end
+
+ function set.OutputRange(obj, value)
+ obj.OutputRange = value;
+ end
+
+ end
+
+ %% API Functions
+ methods (Hidden, Access = protected)
+
+ function icon = getIconImpl(obj)
+ icon = sprintf(['AD3552R', obj.Type]);
+ end
+
+ end
+
+ %% External Dependency Methods
+ methods (Hidden, Static)
+
+ function tf = isSupportedContext(bldCfg)
+ tf = matlabshared.libiio.ExternalDependency.isSupportedContext(bldCfg);
+ end
+
+ function updateBuildInfo(buildInfo, bldCfg)
+ % Call the matlabshared.libiio.method first
+ matlabshared.libiio.ExternalDependency.updateBuildInfo(buildInfo, bldCfg);
+ end
+
+ function bName = getDescriptiveName(~)
+ bName = 'AD3552R';
+ end
+
+ end
+
+end
diff --git a/+adi/+AD3552R/Tx.m b/+adi/+AD3552R/Tx.m
new file mode 100755
index 0000000..10e62d3
--- /dev/null
+++ b/+adi/+AD3552R/Tx.m
@@ -0,0 +1,88 @@
+classdef Tx < adi.common.Tx & adi.AD3552R.Base
+ % adi.AD3552R.Tx Transmit data to the AD3552R high speed DAC
+ % The adi.AD3552R.Tx System object is a signal source that can send
+ % complex data from the AD3552R.
+ %
+ % tx = adi.AD3552R.Tx;
+ % tx = adi.AD3552R.Tx('uri','192.168.2.1');
+ %
+ % AD3552R Datasheet
+ %
+ % See also adi.CN0585.Tx
+
+ properties (Constant)
+ % SamplingRate Sampling Rate
+ % Baseband sampling rate in Hz, specified as a scalar
+ % in samples per second. This value is constant.
+ SamplingRate = 15e6;
+ end
+
+ properties (Hidden, Nontunable, Access = protected)
+ isOutput = true;
+ end
+
+ properties (Nontunable, Hidden, Constant)
+ Type = 'Tx';
+ end
+
+ properties (Nontunable, Hidden)
+ devName = 'axi-ad3552r';
+ phyDevName = 'axi-ad3552r';
+ channel_names = {'voltage0', 'voltage1'};
+ end
+
+ properties
+ % StreamStatus
+ % Describes the status of the data streaming.
+ % Options are: 'start_stream_synced', 'start_stream', 'stop_stream'.
+ % Example: StreamStatus = 'stop_stream';
+ StreamStatus = 'stop_stream';
+ end
+
+ properties (Hidden, Constant)
+ StreamStatusSet = matlab.system.StringSet({ ...
+ 'start_stream_synced', 'start_stream', 'stop_stream'})
+ end
+
+ methods
+ %% Constructor
+ function obj = Tx(varargin)
+ % Returns the matlabshared.libiio.base object
+ coder.allowpcode('plain');
+ obj = obj@adi.AD3552R.Base(varargin{:});
+ end
+
+ %% Start or stop stream transfer
+ function set.StreamStatus(obj, value)
+
+ if obj.ConnectedToDevice
+ obj.setDeviceAttributeRAW('stream_status', value);
+ else
+ error(['StreamStatus cannot be set before initialization, ']);
+ end
+
+ obj.StreamStatus = value;
+
+ end
+
+ end
+
+ %% External Dependency Methods
+ methods (Hidden, Static)
+
+ function tf = isSupportedContext(bldCfg)
+ tf = matlabshared.libiio.ExternalDependency.isSupportedContext(bldCfg);
+ end
+
+ function updateBuildInfo(buildInfo, bldCfg)
+ % Call the matlabshared.libiio.method first
+ matlabshared.libiio.ExternalDependency.updateBuildInfo(buildInfo, bldCfg);
+ end
+
+ function bName = getDescriptiveName(~)
+ bName = 'AD3552R';
+ end
+
+ end
+
+end
diff --git a/+adi/+CN0585/Base.m b/+adi/+CN0585/Base.m
new file mode 100755
index 0000000..3edc2f5
--- /dev/null
+++ b/+adi/+CN0585/Base.m
@@ -0,0 +1,60 @@
+classdef (Abstract, Hidden = true) Base < ...
+ adi.common.RxTx & ...
+ adi.common.Attribute & ...
+ matlabshared.libiio.base
+ %adi.CN0585.Base Class
+ % This class contains shared parameters and methods between TX and RX
+ % classes
+
+ properties (Hidden)
+ iioOneBitADCDAC;
+ HDLSystemID
+
+ end
+
+ methods
+ %% Constructor
+ function obj = Base(varargin)
+ coder.allowpcode('plain');
+ obj = obj@matlabshared.libiio.base(varargin{:});
+ end
+
+ function result = CheckMathWorksCore(obj)
+ result = contains(obj.HDLSystemID, "matlab");
+ end
+
+ end
+
+ %% API Functions
+ methods (Hidden, Access = protected)
+
+ function setupInit(obj)
+
+ % GPIO CONTROLLER
+
+ obj.iioOneBitADCDAC = getDev(obj, 'one-bit-adc-dac');
+ obj.setAttributeBool('voltage0', 'raw', boolean(1), true, obj.iioOneBitADCDAC);
+ obj.setAttributeBool('voltage1', 'raw', boolean(1), true, obj.iioOneBitADCDAC);
+ obj.setAttributeBool('voltage2', 'raw', boolean(1), true, obj.iioOneBitADCDAC);
+ obj.setAttributeBool('voltage3', 'raw', boolean(1), true, obj.iioOneBitADCDAC);
+ obj.setAttributeBool('voltage4', 'raw', boolean(1), true, obj.iioOneBitADCDAC);
+ obj.setAttributeBool('voltage5', 'raw', boolean(1), true, obj.iioOneBitADCDAC);
+ obj.setAttributeBool('voltage6', 'raw', boolean(1), true, obj.iioOneBitADCDAC);
+ obj.setAttributeBool('voltage7', 'raw', boolean(1), true, obj.iioOneBitADCDAC);
+ obj.setAttributeBool('voltage8', 'raw', boolean(1), true, obj.iioOneBitADCDAC);
+ obj.setAttributeBool('voltage9', 'raw', boolean(1), true, obj.iioOneBitADCDAC);
+
+ % HDLSystemID SYSID STRING VALUE
+
+ obj.HDLSystemID = obj.iio_context_get_attr_value(obj.iioCtx, 'hdl_system_id');
+
+ % UPDATED PARAMETERS
+
+ obj.setDeviceAttributeRAW('input_source', obj.InputSource);
+ obj.setDeviceAttributeRAW('output_range', obj.OutputRange);
+
+ end
+
+ end
+
+end
diff --git a/+adi/+CN0585/Rx.m b/+adi/+CN0585/Rx.m
new file mode 100755
index 0000000..c9c8449
--- /dev/null
+++ b/+adi/+CN0585/Rx.m
@@ -0,0 +1,21 @@
+classdef Rx < adi.LTC2387.Rx
+ % adi.CN0585.Rx Receive data from the LTC2387 evaluation platform
+ %
+ % rx = adi.CN0585.Rx;
+ % rx = adi.CN0585.Rx('uri','192.168.2.1');
+ %
+ % User Guide
+ %
+ % See also adi.LTC2387.Rx
+
+ methods
+ %% Constructor
+ function obj = Rx(varargin)
+ % Returns the matlabshared.libiio.base object
+ coder.allowpcode('plain');
+ obj = obj@adi.LTC2387.Rx(varargin{:});
+ end
+
+ end
+
+end
diff --git a/+adi/+CN0585/Tx0.m b/+adi/+CN0585/Tx0.m
new file mode 100755
index 0000000..50bc2c7
--- /dev/null
+++ b/+adi/+CN0585/Tx0.m
@@ -0,0 +1,23 @@
+classdef Tx0 < adi.AD3552R.Tx & adi.CN0585.Base
+ % adi.CN0585.Tx Transmit data from the AD3552R evaluation platform
+ %
+ % tx0 = adi.CN0585.Tx0;
+ % tx0 = adi.CN0585.Tx0('uri','192.168.2.1');
+ %
+ % User Guide
+ %
+ % See also adi.AD3552R.Tx0
+
+ methods
+ %% Constructor
+ function obj = Tx0(varargin)
+ % Returns the matlabshared.libiio.base object
+ coder.allowpcode('plain');
+ obj = obj@adi.AD3552R.Tx(varargin{:});
+ obj.devName = 'axi-ad3552r-0';
+ obj.phyDevName = 'axi-ad3552r-0';
+ end
+
+ end
+
+end
diff --git a/+adi/+CN0585/Tx1.m b/+adi/+CN0585/Tx1.m
new file mode 100755
index 0000000..352d5e5
--- /dev/null
+++ b/+adi/+CN0585/Tx1.m
@@ -0,0 +1,22 @@
+classdef Tx1 < adi.AD3552R.Tx & adi.CN0585.Base
+ % adi.CN0585.Tx Transmit data from the AD3552R evaluation platform
+ %
+ % tx1 = adi.CN0585.Tx1;
+ % tx1 = adi.CN0585.Tx1('uri','192.168.2.1');
+ %
+ % User Guide
+ %
+ % See also adi.AD3552R.Tx1
+
+ methods
+ %% Constructor
+ function obj = Tx1(varargin)
+ % Returns the matlabshared.libiio.base object
+ coder.allowpcode('plain');
+ obj = obj@adi.AD3552R.Tx(varargin{:});
+ obj.devName = 'axi-ad3552r-1';
+ obj.phyDevName = 'axi-ad3552r-1';
+ end
+ end
+
+end
diff --git a/+adi/+LTC2387/Base.m b/+adi/+LTC2387/Base.m
new file mode 100755
index 0000000..cd1badb
--- /dev/null
+++ b/+adi/+LTC2387/Base.m
@@ -0,0 +1,72 @@
+classdef (Abstract) Base < ...
+ adi.common.RxTx & ...
+ adi.common.Attribute & ...
+ matlabshared.libiio.base
+ %LTC2387 Base Class
+
+ properties (Nontunable)
+ %SamplesPerFrame Samples Per Frame
+ % Number of samples per frame, specified as an even positive
+ % integer from 2 to 16,777,216. Using values less than 3660 can
+ % yield poor performance.
+ SamplesPerFrame = 2^15;
+ end
+
+ properties(Nontunable, Hidden)
+ Timeout = Inf;
+ kernelBuffersCount = 2;
+ dataTypeStr = 'int64';
+ end
+
+ properties (Abstract, Hidden, Constant)
+ Type
+ end
+
+
+ properties (Hidden, Constant)
+ ComplexData = false;
+ end
+
+ methods
+ %% Constructor
+ function obj = Base(varargin)
+ % Returns the matlabshared.libiio.base object
+ coder.allowpcode('plain');
+ obj = obj@matlabshared.libiio.base(varargin{:});
+ end
+ % Check SamplesPerFrame
+ function set.SamplesPerFrame(obj, value)
+ validateattributes( value, { 'double','single' }, ...
+ { 'real', 'positive','scalar', 'finite', 'nonnan', 'nonempty','integer','>',0,'<',2^20+1}, ...
+ '', 'SamplesPerFrame');
+ obj.SamplesPerFrame = value;
+ end
+ end
+
+ %% API Functions
+ methods (Hidden, Access = protected)
+
+ function icon = getIconImpl(obj)
+ icon = sprintf(['LTC2387 ',obj.Type]);
+ end
+
+ end
+
+ %% External Dependency Methods
+ methods (Hidden, Static)
+
+ function tf = isSupportedContext(bldCfg)
+ tf = matlabshared.libiio.ExternalDependency.isSupportedContext(bldCfg);
+ end
+
+ function updateBuildInfo(buildInfo, bldCfg)
+ % Call the matlabshared.libiio.method first
+ matlabshared.libiio.ExternalDependency.updateBuildInfo(buildInfo, bldCfg);
+ end
+
+ function bName = getDescriptiveName(~)
+ bName = 'LTC2387';
+ end
+
+ end
+end
diff --git a/+adi/+LTC2387/Rx.m b/+adi/+LTC2387/Rx.m
new file mode 100755
index 0000000..0b1c6d6
--- /dev/null
+++ b/+adi/+LTC2387/Rx.m
@@ -0,0 +1,73 @@
+classdef Rx < adi.common.Rx & adi.LTC2387.Base & adi.common.Attribute
+ % adi.LTC2387.Rx Receive data from the LTC2387 high speed ADC
+ % The adi.LTC2387.Rx System object is a signal source that can receive
+ % complex data from the LTC2387.
+ %
+ % rx = adi.LTC2387.Rx;
+ % rx = adi.LTC2387.Rx('uri','192.168.2.1');
+ %
+ % LTC2387 Datasheet
+ %
+ % See also adi.CN0585.Rx
+
+ properties (Dependent)
+ %SamplingRate Sampling Rate
+ % Baseband sampling rate in Hz, specified as a scalar
+ % in samples per second. This value is constant
+ SamplingRate
+ end
+ properties (Hidden, Nontunable, Access = protected)
+ isOutput = false;
+ end
+
+ properties(Nontunable, Hidden, Constant)
+ Type = 'Rx';
+ end
+
+ properties (Nontunable, Hidden)
+ devName = 'ltc2387';
+ phyDevName = 'ltc2387';
+ channel_names = {'voltage0','voltage1','voltage2','voltage3'};
+ end
+
+ methods
+ %% Constructor
+ function obj = Rx(varargin)
+ % Returns the matlabshared.libiio.base object
+ coder.allowpcode('plain');
+ obj = obj@adi.LTC2387.Base(varargin{:});
+ end
+ function value = get.SamplingRate(obj)
+ if obj.ConnectedToDevice
+ value= obj.getAttributeLongLong('voltage0','sampling_frequency',false);
+ else
+ value = NaN;
+ end
+ end
+ end
+
+ %% API Functions
+ methods (Hidden, Access = protected)
+ function setupInit(~)
+ %unused
+ end
+ end
+
+ %% External Dependency Methods
+ methods (Hidden, Static)
+
+ function tf = isSupportedContext(bldCfg)
+ tf = matlabshared.libiio.ExternalDependency.isSupportedContext(bldCfg);
+ end
+
+ function updateBuildInfo(buildInfo, bldCfg)
+ % Call the matlabshared.libiio.method first
+ matlabshared.libiio.ExternalDependency.updateBuildInfo(buildInfo, bldCfg);
+ end
+
+ function bName = getDescriptiveName(~)
+ bName = 'LTC2387';
+ end
+
+ end
+end
diff --git a/+adi/Contents.m b/+adi/Contents.m
index 5823d37..8beb514 100644
--- a/+adi/Contents.m
+++ b/+adi/Contents.m
@@ -9,5 +9,12 @@
% AD7768 - ADC
% AD7768-1 - ADC
% AD4030-24 - ADC
-% AD4630-16 - ADC
-% AD4630-24 - ADC
+% AD4630-16 - ADC
+% AD4630-24 - ADC
+% AD43552R - DAC
+% LTC2387 - DAC
+%
+% Boards and Platforms
+% -----------------------
+% CN0585 - FMC development board for precision data acquisition
+
diff --git a/+adi/Version.m b/+adi/Version.m
index cffb464..f749edb 100644
--- a/+adi/Version.m
+++ b/+adi/Version.m
@@ -2,7 +2,8 @@
% Version
% BSP Version information
properties (Constant)
- MATLAB = 'R2021b'
+ Vivado = '2022.2'
+ MATLAB = 'R2022a'
Release = '21.2.1'
AppName = 'Analog Devices, Inc. Precision Toolbox'
ToolboxName = 'PrecisionToolbox'
diff --git a/CI/scripts_hdl/matlab_processors.tcl b/CI/scripts_hdl/matlab_processors.tcl
new file mode 100755
index 0000000..12427a1
--- /dev/null
+++ b/CI/scripts_hdl/matlab_processors.tcl
@@ -0,0 +1,58 @@
+proc preprocess_bd {project carrier rxtx} {
+
+ puts "Preprocessing $project $carrier $rxtx"
+
+ switch $project {
+ cn0585_fmcz {
+ # Disconnect the ADC PACK pins
+ delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_data]
+ delete_bd_objs [get_bd_nets axi_ltc2387_1_adc_data]
+ delete_bd_objs [get_bd_nets axi_ltc2387_2_adc_data]
+ delete_bd_objs [get_bd_nets axi_ltc2387_3_adc_data]
+
+
+ set sys_cstring "matlab $rxtx"
+ sysid_gen_sys_init_file $sys_cstring
+
+ #Disconnect adc_valid
+ delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_valid]
+ # Reconnect the adc_valid in the system
+ connect_bd_net [get_bd_pins axi_ltc2387_0/adc_valid] [get_bd_pins axi_ltc2387_dma/fifo_wr_en]
+
+ if {$rxtx == "rx"} {
+ connect_bd_net [get_bd_pins axi_ltc2387_0/adc_data] [get_bd_pins axi_ad3552r_0/data_in_a]
+ connect_bd_net [get_bd_pins axi_ltc2387_1/adc_data] [get_bd_pins axi_ad3552r_0/data_in_b]
+ connect_bd_net [get_bd_pins axi_ltc2387_2/adc_data] [get_bd_pins axi_ad3552r_1/data_in_a]
+ connect_bd_net [get_bd_pins axi_ltc2387_3/adc_data] [get_bd_pins axi_ad3552r_1/data_in_b]
+ }
+
+ if {$rxtx == "tx"} {
+ connect_bd_net [get_bd_pins axi_ltc2387_0/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_0]
+ connect_bd_net [get_bd_pins axi_ltc2387_1/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_1]
+ connect_bd_net [get_bd_pins axi_ltc2387_2/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_2]
+ connect_bd_net [get_bd_pins axi_ltc2387_3/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_3]
+ connect_bd_net [get_bd_pins axi_ltc2387_0/adc_valid] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_en]
+ }
+
+ if {$rxtx == "tx" || $rxtx == "rxtx"} {
+
+ delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_valid]
+ delete_bd_objs [get_bd_nets axi_ltc2387_1_adc_valid]
+ delete_bd_objs [get_bd_nets axi_ltc2387_2_adc_valid]
+ delete_bd_objs [get_bd_nets axi_ltc2387_3_adc_valid]
+
+ # Connect dac valids together
+ connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_0/valid_in_b]
+ connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_1/valid_in_a]
+ connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_1/valid_in_b]
+ }
+ switch $carrier {
+ zed {
+ set_property -dict [list CONFIG.NUM_MI {21}] [get_bd_cells axi_cpu_interconnect]
+ connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ACLK] [get_bd_pins axi_clkgen/clk_0]
+ connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ARESETN] [get_bd_pins sampling_clk_rstgen/peripheral_aresetn]
+ }
+ }
+ }
+ }
+}
diff --git a/CI/scripts_hdl/ports.json b/CI/scripts_hdl/ports.json
new file mode 100755
index 0000000..51f6fb1
--- /dev/null
+++ b/CI/scripts_hdl/ports.json
@@ -0,0 +1,142 @@
+{
+ "cn0585": {
+ "chip": "CN0585",
+ "complex": "true",
+ "fpga": [
+ "zed"
+ ],
+ "supported_rd": [
+ "rx",
+ "tx",
+ "rx & tx"
+ ],
+ "ports": [
+ {
+ "rx": [
+ {
+ "input": "false",
+ "width": 1,
+ "name": "util_ltc2387_adc_pack/fifo_wr_en",
+ "type": "valid"
+ },
+ {
+ "input": "false",
+ "width": 16,
+ "name": "util_ltc2387_adc_pack/fifo_wr_data_0",
+ "type": "data"
+ },
+ {
+ "input": "false",
+ "width": 16,
+ "name": "util_ltc2387_adc_pack/fifo_wr_data_1",
+ "type": "data"
+ },
+ {
+ "input": "false",
+ "width": 16,
+ "name": "util_ltc2387_adc_pack/fifo_wr_data_2",
+ "type": "data"
+ },
+ {
+ "input": "false",
+ "width": 16,
+ "name": "util_ltc2387_adc_pack/fifo_wr_data_3",
+ "type": "data"
+ },
+ {
+ "input": "true",
+ "width": 1,
+ "name": "axi_ltc2387_0/adc_valid",
+ "type": "valid"
+ },
+ {
+ "input": "true",
+ "width": 16,
+ "name": "axi_ltc2387_0/adc_data",
+ "type": "data"
+ },
+ {
+ "input": "true",
+ "width": 16,
+ "name": "axi_ltc2387_1/adc_data",
+ "type": "data"
+ },
+ {
+ "input": "true",
+ "width": 16,
+ "name": "axi_ltc2387_2/adc_data",
+ "type": "data"
+ },
+ {
+ "input": "true",
+ "width": 16,
+ "name": "axi_ltc2387_3/adc_data",
+ "type": "data"
+ }
+ ],
+ "tx": [
+ {
+ "input": "true",
+ "width": 16,
+ "name": "axi_ltc2387_0/adc_data",
+ "type": "data"
+ },
+ {
+ "input": "true",
+ "width": 16,
+ "name": "axi_ltc2387_1/adc_data",
+ "type": "data"
+ },
+ {
+ "input": "true",
+ "width": 16,
+ "name": "axi_ltc2387_2/adc_data",
+ "type": "data"
+ },
+ {
+ "input": "true",
+ "width": 16,
+ "name": "axi_ltc2387_3/adc_data",
+ "type": "data"
+ },
+ {
+ "input": "true",
+ "width": 1,
+ "name": "axi_ltc2387_0/adc_valid",
+ "type": "valid"
+ },
+ {
+ "input": "false",
+ "width": 16,
+ "name": "axi_ad3552r_0/data_in_a",
+ "type": "data"
+ },
+ {
+ "input": "false",
+ "width": 16,
+ "name": "axi_ad3552r_0/data_in_b",
+ "type": "data"
+ },
+ {
+ "input": "false",
+ "width": 1,
+ "name": "axi_ad3552r_0/valid_in_a",
+ "type": "valid"
+ },
+ {
+ "input": "false",
+ "width": 16,
+ "name": "axi_ad3552r_1/data_in_a",
+ "type": "data"
+ },
+ {
+ "input": "false",
+ "width": 16,
+ "name": "axi_ad3552r_1/data_in_b",
+ "type": "data"
+ }
+ ]
+ }
+ ]
+ }
+}
diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585_fmcz/+zed/hdlcoder_ref_design_customization.m b/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585_fmcz/+zed/hdlcoder_ref_design_customization.m
new file mode 100755
index 0000000..8e2c2c9
--- /dev/null
+++ b/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585_fmcz/+zed/hdlcoder_ref_design_customization.m
@@ -0,0 +1,22 @@
+function [rd, boardName] = hdlcoder_ref_design_customization
+% Reference design plugin registration file
+% 1. The registration file with this name inside of a board plugin folder
+% will be picked up
+% 2. Any registration file with this name on MATLAB path will also be picked up
+% 3. The registration file returns a cell array pointing to the location of
+% the reference design plugins
+% 4. The registration file also returns its associated board name
+% 5. Reference design plugin must be a package folder accessible from
+% MATLAB path, and contains a reference design definition file
+
+% Copyright 2013-2014 The MathWorks, Inc.
+
+rd = {...
+ 'AnalogDevices.cn0585_fmcz.zed.plugin_rd_rx', ...
+ 'AnalogDevices.cn0585_fmcz.zed.plugin_rd_tx', ...
+ 'AnalogDevices.cn0585_fmcz.zed.plugin_rd_rxtx', ...
+ };
+
+boardName = 'AnalogDevices CN0585 ZED';
+
+end
diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585_fmcz/+zed/plugin_board.m b/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585_fmcz/+zed/plugin_board.m
new file mode 100755
index 0000000..22b5cf4
--- /dev/null
+++ b/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585_fmcz/+zed/plugin_board.m
@@ -0,0 +1,8 @@
+function hP = plugin_board()
+% Zynq Platform PCore
+% Use Plugin API to create board plugin object
+
+% Copyright 2015 The MathWorks, Inc.
+
+% Call the common board definition function
+hP = AnalogDevices.plugin_board('CN0585', 'ZED');
diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585_fmcz/+zed/plugin_rd_rx.m b/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585_fmcz/+zed/plugin_rd_rx.m
new file mode 100755
index 0000000..002adf5
--- /dev/null
+++ b/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585_fmcz/+zed/plugin_rd_rx.m
@@ -0,0 +1,5 @@
+function hRD = plugin_rd_rx
+% Reference design definition
+
+% Call the common reference design definition function
+hRD = AnalogDevices.plugin_rd('cn0585','ZED', 'Rx');
diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585_fmcz/+zed/plugin_rd_rxtx.m b/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585_fmcz/+zed/plugin_rd_rxtx.m
new file mode 100755
index 0000000..dc334fc
--- /dev/null
+++ b/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585_fmcz/+zed/plugin_rd_rxtx.m
@@ -0,0 +1,7 @@
+function hRD = plugin_rd_rxtx
+% Reference design definition
+
+% Copyright 2014-2015 The MathWorks, Inc.
+
+% Call the common reference design definition function
+hRD = AnalogDevices.plugin_rd('cn0585','ZED', 'Rx & Tx');
diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585_fmcz/+zed/plugin_rd_tx.m b/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585_fmcz/+zed/plugin_rd_tx.m
new file mode 100755
index 0000000..ae6ae98
--- /dev/null
+++ b/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585_fmcz/+zed/plugin_rd_tx.m
@@ -0,0 +1,7 @@
+function hRD = plugin_rd_tx
+% Reference design definition
+
+% Copyright 2014-2015 The MathWorks, Inc.
+
+% Call the common reference design definition function
+hRD = AnalogDevices.plugin_rd('cn0585', 'ZED', 'Tx');
diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/+util/ADIZynqSDRAttributeInfo.xml b/hdl/vendor/AnalogDevices/+AnalogDevices/+util/ADIZynqSDRAttributeInfo.xml
new file mode 100755
index 0000000..7c9a676
--- /dev/null
+++ b/hdl/vendor/AnalogDevices/+AnalogDevices/+util/ADIZynqSDRAttributeInfo.xml
@@ -0,0 +1,37 @@
+
+
+
+ Analog Devices Zynq SDR
+ true
+
+ $(MATLAB_ROOT)/rtw/c/src/ext_mode/common/rtiostream_interface.c
+
+ $(ARM_CORTEX_A_ROOT_DIR)/src/rtiostream_tcpip.c
+ codertarget.zynq.internal.extmodeHooksADI(hObj,'setupfcn');
+
+ TCP/IP
+
+
+
+
+
+
+
+
+
+ $(TARGET_ROOT)/src/axi4Lite.c
+ $(TARGET_ROOT)/include
+ ARM_PROJECT
+ ADI_ZYNQ_SDR_IPADDRESS
+ ZYNQ_USERNAME
+ ZYNQ_PASSWORD
+
+ codertarget.zynq.internal.onAfterCodeGen
+ codertarget.zynq.internal.onBuildEntryHook
+ codertarget.zynq.internal.onHardwareSelect
+
+
diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/+util/ADIZynqSDRParameterInfo.xml b/hdl/vendor/AnalogDevices/+AnalogDevices/+util/ADIZynqSDRParameterInfo.xml
new file mode 100755
index 0000000..5965474
--- /dev/null
+++ b/hdl/vendor/AnalogDevices/+AnalogDevices/+util/ADIZynqSDRParameterInfo.xml
@@ -0,0 +1,13 @@
+
+
+
+ Analog Devices Zynq SDR
+
+ Clocking
+
+
+
+ Build options
+
+
+
diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/+util/adizynqsdr.xml b/hdl/vendor/AnalogDevices/+AnalogDevices/+util/adizynqsdr.xml
new file mode 100755
index 0000000..3df950a
--- /dev/null
+++ b/hdl/vendor/AnalogDevices/+AnalogDevices/+util/adizynqsdr.xml
@@ -0,0 +1,16 @@
+
+
+
+ Analog Devices Zynq SDR
+ ARM Cortex-A9
+ ARM Cortex-A
+ ARM Compatible->ARM Cortex
+
+ "$(ARM_CORTEX_A_ROOT_DIR)/ssh_download.bat"
+ "$(MATLAB_ROOT)/toolbox/idelink/foundation/hostapps" root analog $(ADI_ZYNQ_SDR_IPADDRESS) /home/analog/Downloads
+
+ $(TARGET_ROOT)/registry/parameters/ADIZynqSDRParameterInfo.xml
+ $(TARGET_ROOT)/registry/attributes/ADIZynqSDRAttributeInfo.xml
+
+
+
diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/+util/extmodeHooksADI.m b/hdl/vendor/AnalogDevices/+AnalogDevices/+util/extmodeHooksADI.m
new file mode 100755
index 0000000..a600f58
--- /dev/null
+++ b/hdl/vendor/AnalogDevices/+AnalogDevices/+util/extmodeHooksADI.m
@@ -0,0 +1,21 @@
+function extmodeHooksADI(hObj,hookpoint)
+
+% Copyright 2014-2015 The MathWorks, Inc.
+
+modelName = get(getModel(hObj),'Name');
+modelName = sprintf('%s.elf', modelName);
+data = codertarget.data.getData(hObj);
+h__z = zynq(data.RTOS);
+h__z.IPAddress = getenv('ADI_ZYNQ_SDR_IPADDRESS');
+h__z.Username = 'root';
+h__z.Password = 'analog';
+
+switch (lower(hookpoint))
+ case 'preconnectfcn',
+ waitForAppToStart(h__z, modelName, 60);
+ case 'setupfcn'
+ checkConnection(h__z);
+ otherwise
+end
+
+end
diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/add_clocks.m b/hdl/vendor/AnalogDevices/+AnalogDevices/add_clocks.m
new file mode 100755
index 0000000..1faebf9
--- /dev/null
+++ b/hdl/vendor/AnalogDevices/+AnalogDevices/add_clocks.m
@@ -0,0 +1,22 @@
+function add_clocks(hRD,project,design)
+
+switch lower(project)
+ case 'cn0585'
+ switch(upper(design))
+ case 'RX'
+ hRD.addClockInterface( ...
+ 'ClockConnection', 'axi_clkgen/clk_0', ...
+ 'ResetConnection', 'sampling_clk_rstgen/peripheral_aresetn');
+
+ case 'TX'
+ hRD.addClockInterface( ...
+ 'ClockConnection', 'axi_clkgen/clk_0', ...
+ 'ResetConnection', 'sampling_clk_rstgen/peripheral_aresetn');
+ case 'RX & TX'
+ hRD.addClockInterface( ...
+ 'ClockConnection', 'axi_clkgen/clk_0', ...
+ 'ResetConnection', 'sampling_clk_rstgen/peripheral_aresetn');
+ otherwise
+ error('Unknown reference design');
+ end
+end
diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/add_io.m b/hdl/vendor/AnalogDevices/+AnalogDevices/add_io.m
new file mode 100755
index 0000000..58f6341
--- /dev/null
+++ b/hdl/vendor/AnalogDevices/+AnalogDevices/add_io.m
@@ -0,0 +1,17 @@
+function add_io(hRD,project,fpga,type)
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+% Add AXI4 and AXI4-Lite slave interfaces
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+out = AnalogDevices.get_memory_axi_interface_info(fpga,lower(project));
+hRD.addAXI4SlaveInterface( ...
+ 'InterfaceConnection', out.InterfaceConnection, ...
+ 'BaseAddress', out.BaseAddress, ...
+ 'MasterAddressSpace', out.MasterAddressSpace);
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+% Add Reference design interfaces
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+AnalogDevices.add_io_ports(hRD,lower(project),lower(type),lower(fpga));
+
+end
\ No newline at end of file
diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/add_io_ports.m b/hdl/vendor/AnalogDevices/+AnalogDevices/add_io_ports.m
new file mode 100755
index 0000000..645e5a4
--- /dev/null
+++ b/hdl/vendor/AnalogDevices/+AnalogDevices/add_io_ports.m
@@ -0,0 +1,92 @@
+function root = add_io_ports(hRD,project,type,fpga)
+
+[filepath,~,~] = fileparts(mfilename('fullpath'));
+fileName = fullfile(filepath,'ports.json');
+fid = fopen(fileName);
+raw = fread(fid,inf);
+str = char(raw');
+fclose(fid);
+data = jsondecode(str);
+
+project = erase(project,'-');
+if ~contains(fields(data),project)
+ error(sprintf('No project found in database for %s',project));
+end
+
+root = getfield(data, project);
+
+if ~contains(root.supported_rd,type)
+ error(sprintf('No project found in database for %s',project));
+end
+
+if ~contains(root.fpga,fpga)
+ error(sprintf('No project found in database for %s',fpga));
+end
+
+
+if contains(type,'rx')
+ process(hRD, root.ports.rx, 'rx');
+end
+if contains(type,'tx')
+ process(hRD, root.ports.tx, 'tx');
+end
+
+
+end
+
+function process(hRD, rtx, type)
+count = [-1 -1];
+for i = 1:length(rtx)
+ rx = rtx(i);
+ if strcmpi(rx.type,'valid')
+ hRD.addInternalIOInterface( ...
+ 'InterfaceID', rx.m_name, ...
+ 'InterfaceType', inout(rx.input), ...
+ 'PortName', inout_pn(rx.input, type), ...
+ 'PortWidth', rx.width, ...
+ 'InterfaceConnection', rx.name, ...
+ 'IsRequired', false);
+ elseif strcmpi(rx.type,'data')
+ if strcmp(rx.input, 'true')
+ count(1)=count(1)+1;
+ else
+ count(2)=count(2)+1;
+ end
+ hRD.addInternalIOInterface( ...
+ 'InterfaceID', rx.m_name, ...
+ 'InterfaceType', inout(rx.input), ...
+ 'PortName', inout_pn_d(rx.input,count,type), ...
+ 'PortWidth', rx.width, ...
+ 'InterfaceConnection', rx.name, ...
+ 'IsRequired', false);
+ else
+ error(sprintf('Unknown port type %s',rx.type));
+ end
+end
+end
+
+%%
+function out = inout_pn_d(in,count,type)
+if strcmp(in, 'true')
+ out = sprintf('dut_data_in_%d_%s',count(1), type);
+else
+ out = sprintf('dut_data_out_%d_%s',count(2), type);
+end
+end
+%%
+function out = inout_pn(in, type)
+ if strcmp(in, 'true')
+ out = sprintf('dut_data_valid_in_%s', type);
+ else
+ out = sprintf('dut_data_valid_out_%s', type);
+ end
+end
+%%
+function out = inout(in)
+if strcmp(in, 'true')
+ out = 'IN';
+else
+ out = 'OUT';
+end
+end
+
diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/get_memory_axi_interface_info.m b/hdl/vendor/AnalogDevices/+AnalogDevices/get_memory_axi_interface_info.m
new file mode 100755
index 0000000..fb1328e
--- /dev/null
+++ b/hdl/vendor/AnalogDevices/+AnalogDevices/get_memory_axi_interface_info.m
@@ -0,0 +1,21 @@
+function out = get_memory_axi_interface_info(fpga,project)
+
+
+switch project
+ case 'cn0585'
+ switch fpga
+ case{'ZED'}
+ InterfaceConnection = 'axi_cpu_interconnect/M20_AXI';
+ BaseAddress = '0x43C00000';
+ MasterAddressSpace = 'sys_ps7/Data';
+ otherwise
+ error(sprintf('Unknown Project FPGA %s/%s',project,fpga)); %#ok<*SPERR>
+ end
+ otherwise
+ error(sprintf('Unknown Project %s',project)); %#ok<*SPERR>
+end
+
+out = struct('InterfaceConnection', InterfaceConnection, ...
+ 'BaseAddress', BaseAddress, ...
+ 'MasterAddressSpace', MasterAddressSpace);
+end
diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/install.m b/hdl/vendor/AnalogDevices/+AnalogDevices/install.m
new file mode 100755
index 0000000..9337a51
--- /dev/null
+++ b/hdl/vendor/AnalogDevices/+AnalogDevices/install.m
@@ -0,0 +1,61 @@
+function install(mode)
+% AnalogDevices.install adds/removes AnalogDevices HDL BSPs
+
+% Copyright 2015 MathWorks, Inc. All Rights Reserved.
+
+ if nargin == 0
+ mode = 0;
+ end
+
+ %% Initialization
+ % Determine where we're operating out of
+ vendorRootDir = fileparts(strtok(mfilename('fullpath'), '+'));
+
+ % Add/remove the common contents
+ commonRootDir = fullfile(fileparts(fileparts(vendorRootDir)), 'common');
+ olddir = cd(commonRootDir);
+ cleanup = onCleanup(@()cd(olddir));
+ hdlbsp.install(mode);
+
+
+ % Add/remove the vendor contents
+ paths = {...
+ fullfile(vendorRootDir),...
+ };
+
+ hdlbsp.util.vendorInstall(mode,paths);
+
+ % Copy the Zynq SDR target definition file into the support package
+ source = [];
+ destination = [];
+ zynqRootDir = codertarget.zynq.internal.getSpPkgRootDir;
+ armRootDir = codertarget.arm_cortex_a.internal.getSpPkgRootDir;
+
+ zynqTargetDir = fullfile(zynqRootDir,'registry/targethardware');
+ source = [source {fullfile(vendorRootDir, '/+AnalogDevices/+util/adizynqsdr.xml')}];
+ destination = [destination {fullfile(zynqTargetDir, 'adizynqsdr.xml')}];
+
+ zynqTargetDir = fullfile(zynqRootDir,'registry/attributes');
+ source = [source {fullfile(vendorRootDir, '/+AnalogDevices/+util/ADIZynqSDRAttributeInfo.xml')}];
+ destination = [destination {fullfile(zynqTargetDir, 'ADIZynqSDRAttributeInfo.xml')}];
+
+ zynqTargetDir = fullfile(zynqRootDir,'registry/parameters');
+ source = [source {fullfile(vendorRootDir, '/+AnalogDevices/+util/ADIZynqSDRParameterInfo.xml')}];
+ destination = [destination {fullfile(zynqTargetDir, 'ADIZynqSDRParameterInfo.xml')}];
+
+ source = [source {fullfile(vendorRootDir, '/+AnalogDevices/+util/extmodeHooksADI.m')}];
+ destination = [destination {fullfile(zynqRootDir, '/+codertarget/+zynq/+internal/extmodeHooksADI.m')}];
+
+ source = [source {fullfile(armRootDir,'ssh_download.bat')}];
+ destination = [destination {fullfile(zynqRootDir, 'ssh_download.bat')}];
+
+ if(mode == 0)
+ for i = 1:length(source)
+ copyfile(char(source(:,i)), char(destination(:,i)), 'f');
+ end
+ else
+ for i = 1:length(destination)
+ delete(char(destination(:,i)));
+ end
+ end
+end
\ No newline at end of file
diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/plugin_board.m b/hdl/vendor/AnalogDevices/+AnalogDevices/plugin_board.m
new file mode 100755
index 0000000..7fa2607
--- /dev/null
+++ b/hdl/vendor/AnalogDevices/+AnalogDevices/plugin_board.m
@@ -0,0 +1,42 @@
+function hB = plugin_board(project, board)
+% Use Plugin API to create board plugin object
+
+if nargin < 2
+ board = "";
+end
+hB = hdlcoder.Board;
+
+pname = project;
+
+% Target Board Information
+hB.BoardName = sprintf('AnalogDevices %s', upper(pname));
+if nargin > 1
+ hB.BoardName = sprintf('%s %s', hB.BoardName, upper(board));
+end
+
+% FPGA Device
+hB.FPGAVendor = 'Xilinx';
+
+% Determine the device based on the board
+switch lower(project)
+
+ case {'cn0585'}
+ switch(upper(board))
+ case 'ZED'
+ hB.FPGADevice = sprintf('xc7%s', 'z020');
+ hB.FPGAPackage = 'clg484';
+ hB.FPGASpeed = '-1';
+ hB.FPGAFamily = 'Zynq';
+ end
+
+end
+
+% Tool Info
+hB.SupportedTool = {'Xilinx Vivado'};
+
+% FPGA JTAG chain position
+hB.JTAGChainPosition = 2;
+
+%% Add interfaces
+% Standard "External Port" interface
+
diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/plugin_rd.m b/hdl/vendor/AnalogDevices/+AnalogDevices/plugin_rd.m
new file mode 100755
index 0000000..3ae31d6
--- /dev/null
+++ b/hdl/vendor/AnalogDevices/+AnalogDevices/plugin_rd.m
@@ -0,0 +1,90 @@
+function hRD = plugin_rd(project, board, design)
+% Reference design definition
+
+% Copyright 2014-2015 The MathWorks, Inc.
+
+pname = upper(project);
+ppath = project;
+if strcmpi(project, 'cn0585')
+ ppath = 'cn0585_fmcz';
+end
+
+% Construct reference design object
+hRD = hdlcoder.ReferenceDesign('SynthesisTool', 'Xilinx Vivado');
+
+% Create the reference design for the SOM-only
+% This is the base reference design that other RDs can build upon
+hRD.ReferenceDesignName = sprintf('%s %s (%s)', pname, upper(board), upper(design));
+
+% Determine the board name based on the design
+hRD.BoardName = sprintf('AnalogDevices %s %s', pname, upper(board));
+
+% Tool information
+hRD.SupportedToolVersion = {'2022.2'};
+
+% Get the root directory
+rootDir = fileparts(strtok(mfilename('fullpath'), '+'));
+
+% Design files are shared
+hRD.SharedRD = true;
+hRD.SharedRDFolder = fullfile(rootDir, 'vivado');
+
+%% Set top level project pieces
+hRD.addParameter( ...
+ 'ParameterID', 'project', ...
+ 'DisplayName', 'HDL Project Subfolder', ...
+ 'DefaultValue', lower(ppath));
+
+hRD.addParameter( ...
+ 'ParameterID', 'carrier', ...
+ 'DisplayName', 'HDL Project Carrier', ...
+ 'DefaultValue', lower(board));
+
+
+%% Add custom design files
+% add custom Vivado design
+hRD.addCustomVivadoDesign( ...
+ 'CustomBlockDesignTcl', fullfile('projects', 'scripts', 'system_project_rxtx.tcl'), ...
+ 'CustomTopLevelHDL', fullfile('projects', lower(ppath), lower(board), 'system_top.v'));
+
+hRD.BlockDesignName = 'system';
+
+% custom constraint files
+hRD.CustomConstraints = {...
+ fullfile('projects', lower(ppath), lower(board), 'system_constr.xdc'), ...
+ fullfile('projects', 'common', lower(board), sprintf('%s_system_constr.xdc', lower(board))), ...
+ };
+
+% custom source files
+hRD.CustomFiles = {...
+ fullfile('projects')...,
+ fullfile('library')...,
+ fullfile('scripts')...,
+ };
+
+hRD.addParameter( ...
+ 'ParameterID', 'ref_design', ...
+ 'DisplayName', 'Reference Type', ...
+ 'DefaultValue', lower(strrep(design, ' & ','')));
+
+hRD.addParameter( ...
+ 'ParameterID', 'fpga_board', ...
+ 'DisplayName', 'FPGA Boad', ...
+ 'DefaultValue', upper(board));
+
+hRD.addParameter( ...
+ 'ParameterID', 'preprocess', ...
+ 'DisplayName', 'Preprocess', ...
+ 'DefaultValue', 'off');
+
+hRD.addParameter( ...
+ 'ParameterID', 'postprocess', ...
+ 'DisplayName', 'Postprocess', ...
+ 'DefaultValue', 'off');
+
+%% Add interfaces
+% add clock interface
+AnalogDevices.add_clocks(hRD,project,design)
+
+%% Add IO
+AnalogDevices.add_io(hRD,project,board,design);
diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/uninstall.m b/hdl/vendor/AnalogDevices/+AnalogDevices/uninstall.m
new file mode 100755
index 0000000..ce1a433
--- /dev/null
+++ b/hdl/vendor/AnalogDevices/+AnalogDevices/uninstall.m
@@ -0,0 +1,7 @@
+function uninstall
+% AnalogDevices.uninstall removes AnalogDevices HDL BSPs
+
+% Copyright 2015 MathWorks, Inc. All Rights Reserved.
+
+ AnalogDevices.install(1);
+end
diff --git a/hdl/vendor/AnalogDevices/Contents.m b/hdl/vendor/AnalogDevices/Contents.m
new file mode 100755
index 0000000..9aa4ea5
--- /dev/null
+++ b/hdl/vendor/AnalogDevices/Contents.m
@@ -0,0 +1,2 @@
+% Precision Toolbox: Analog Devices, Inc
+% Version 21.1.1 (R2021a) 3-Dec-2021
\ No newline at end of file
diff --git a/hdl/vendor/AnalogDevices/hdlcoder_board_customization.m b/hdl/vendor/AnalogDevices/hdlcoder_board_customization.m
new file mode 100755
index 0000000..d553377
--- /dev/null
+++ b/hdl/vendor/AnalogDevices/hdlcoder_board_customization.m
@@ -0,0 +1,15 @@
+function r = hdlcoder_board_customization
+% Board plugin registration file
+% 1. Any registration file with this name on MATLAB path will be picked up
+% 2. Registration file returns a cell array pointing to the location of
+% the board plugins
+% 3. Board plugin must be a package folder accessible from MATLAB path,
+% and contains a board definition file
+
+% Copyright 2012-2013 The MathWorks, Inc.
+
+r = { ...
+ 'AnalogDevices.cn0585_fmcz.zed.plugin_board' ...,
+ };
+end
+% LocalWords: Zynq ZC
diff --git a/pcx_examples/streaming/cn0585_fmcz/CN0585_streaming.m b/pcx_examples/streaming/cn0585_fmcz/CN0585_streaming.m
new file mode 100644
index 0000000..a9d9e81
--- /dev/null
+++ b/pcx_examples/streaming/cn0585_fmcz/CN0585_streaming.m
@@ -0,0 +1,74 @@
+% CN0585 Streaming example
+
+board_ip = 'local_board_ip';
+uri = cat(2, 'ip:', board_ip);
+
+% Describe the devices
+
+cn0585_device_rx = adi.CN0585.Rx('uri',uri);
+cn0585_device_tx0 = adi.CN0585.Tx0('uri',uri);
+cn0585_device_tx1 = adi.CN0585.Tx1('uri',uri);
+
+cn0585_device_tx0.EnableCyclicBuffers = true;
+cn0585_device_tx1.EnableCyclicBuffers = true;
+
+cn0585_device_rx.BufferTypeConversionEnable = true;
+
+% Enable the channels to write data to (options are 1, 2 )
+
+cn0585_device_tx0.EnabledChannels = [1, 2];
+cn0585_device_tx1.EnabledChannels = [1, 2];
+
+% Enable the channels to read data from (options are 1, 2, 3 ,4 )
+
+cn0585_device_rx.EnabledChannels = [1, 2, 3, 4];
+
+% Generate the sinewave signal
+
+amplitude = 2 ^ 15;
+sampFreq = cn0585_device_tx0.SamplingRate;
+toneFreq = 1e3;
+N = sampFreq / toneFreq;
+x = linspace(-pi, pi, N).';
+sine_wave = amplitude * sin(x);
+
+% Continuously load data in the buffer and configure the GPIOs state
+% (SetupInit Base file)
+% DAC1 has to be updated and started first and then DAC0 in order to have syncronized data between devices
+
+cn0585_device_tx1([sine_wave, sine_wave]);
+cn0585_device_tx0([sine_wave, sine_wave]);
+
+% Stream status available options: "start_stream_synced", "start_stream", "stop_stream"
+
+cn0585_device_tx1.StreamStatus = 'start_stream';
+cn0585_device_tx0.StreamStatus = 'start_stream';
+
+% The data will be stored inside "data" variable
+
+data = cn0585_device_rx();
+
+title('ADAQ23876 Channels');
+subplot(4, 1, 1);
+plot(data(:, 1));
+ylabel('Channel A');
+subplot(4, 1, 2);
+plot(data(:, 2));
+ylabel('Channel B');
+subplot(4, 1, 3);
+plot(data(:, 3));
+ylabel('Channel C');
+subplot(4, 1, 4);
+plot(data(:, 4));
+ylabel('Channel D');
+xlabel('Number of samples');
+
+% Release the device
+
+cn0585_device_tx1.StreamStatus = 'stop_stream';
+cn0585_device_tx0.StreamStatus = 'stop_stream';
+
+cn0585_device_tx1.release();
+cn0585_device_tx0.release();
+
+cn0585_device_rx.release();
diff --git a/pcx_examples/streaming/cn0585_fmcz/CN0585_streaming_axi4lite_read_write.m b/pcx_examples/streaming/cn0585_fmcz/CN0585_streaming_axi4lite_read_write.m
new file mode 100755
index 0000000..935eaa0
--- /dev/null
+++ b/pcx_examples/streaming/cn0585_fmcz/CN0585_streaming_axi4lite_read_write.m
@@ -0,0 +1,96 @@
+% CN0585 Streaming example for AXI4 Lite register read/write
+
+board_ip = 'local_board_ip';
+uri = cat(2, 'ip:', board_ip);
+
+% Describe the devices
+
+cn0585_device_rx = adi.CN0585.Rx('uri',uri);
+cn0585_device_tx0 = adi.CN0585.Tx0('uri',uri);
+cn0585_device_tx1 = adi.CN0585.Tx1('uri',uri);
+
+cn0585_device_tx0.EnableCyclicBuffers = true;
+cn0585_device_tx1.EnableCyclicBuffers = true;
+
+cn0585_device_rx.BufferTypeConversionEnable = true;
+
+% Enable the channels to write data to (options are 1, 2)
+
+cn0585_device_tx0.EnabledChannels = [1, 2];
+cn0585_device_tx1.EnabledChannels = [1, 2];
+
+% Enable the channels to read data from (options are 1, 2, 3 ,4)
+
+cn0585_device_rx.EnabledChannels = [1, 2, 3, 4];
+
+write_reg = soc.libiio.aximm.WriteHost(devName = 'mwipcore0:mmwr-channel0', IPAddress = board_ip); % MathWorks IP Core Write channel
+read_reg = soc.libiio.aximm.WriteHost(devName = 'mwipcore0:mmrd-channel1', IPAddress = board_ip); % MathWorks IP Core Read channel
+
+% Input source available options: 'adc_input', 'dma_input', 'ramp_input'
+
+cn0585_device_tx0.InputSource = 'dma_input';
+cn0585_device_tx1.InputSource = 'dma_input';
+
+% Output range available options: '0/2.5V', '0/5V', '0/10V', '-5/+5V', '-10/+10V'
+
+cn0585_device_tx0.OutputRange = '-10/+10V';
+cn0585_device_tx1.OutputRange = '-10/+10V';
+
+% Generate the sinewave signal
+
+amplitude = 2 ^ 15;
+sampFreq = cn0585_device_tx0.SamplingRate;
+toneFreq = 1e3;
+N = sampFreq / toneFreq;
+x = linspace(-pi, pi, N).';
+sine_wave = amplitude * sin(x);
+
+% Continuously load data in the buffer and configure the GPIOs state
+% (SetupInit Base file)
+% DAC1 has to be updated and started first and then DAC0 in order to have syncronized data between devices
+
+cn0585_device_tx1([sine_wave, sine_wave]);
+cn0585_device_tx0([sine_wave, sine_wave]);
+
+% Stream status available options: "start_stream_synced", "start_stream", "stop_stream"
+
+cn0585_device_tx1.StreamStatus = 'start_stream';
+cn0585_device_tx0.StreamStatus = 'start_stream';
+
+% The data will be stored inside "data" variable
+
+data = cn0585_device_rx();
+
+if cn0585_device_tx0.CheckMathWorksCore()
+
+ write_reg.writeReg(hex2dec('100'), 85);
+ write_reg.writeReg(hex2dec('104'), 22);
+
+ fprintf('Read value from the 0x108 register is: %d \n', read_reg.readReg(hex2dec('108')));
+ fprintf('Read value from the 0x10c register is: %d \n', read_reg.readReg(hex2dec('10c')));
+end
+
+title('ADAQ23876 Channels');
+subplot(4, 1, 1);
+plot(data(:, 1));
+ylabel('Channel A');
+subplot(4, 1, 2);
+plot(data(:, 2));
+ylabel('Channel B');
+subplot(4, 1, 3);
+plot(data(:, 3));
+ylabel('Channel C');
+subplot(4, 1, 4);
+plot(data(:, 4));
+ylabel('Channel D');
+xlabel('Number of samples');
+
+% Release the device
+
+cn0585_device_tx1.StreamStatus = 'stop_stream';
+cn0585_device_tx0.StreamStatus = 'stop_stream';
+
+cn0585_device_tx1.release();
+cn0585_device_tx0.release();
+
+cn0585_device_rx.release();
diff --git a/test/DemoTests.m b/test/DemoTests.m
new file mode 100755
index 0000000..a2f7d88
--- /dev/null
+++ b/test/DemoTests.m
@@ -0,0 +1,74 @@
+classdef DemoTests < matlab.uitest.TestCase
+
+ properties
+ root = '';
+ end
+
+ methods(TestClassSetup)
+ function addpaths(testCase)
+ here = mfilename('fullpath');
+ here = strsplit(here,'/');
+ here = fullfile('/',here{1:end-2});
+ testCase.root = here;
+ addpath(genpath(fullfile(here,'hdl')));
+ end
+ function setupVivado(~)
+ v=ver('matlab'); Release = v.Release;
+ switch Release
+ case '(R2017a)'
+ vivado = '2016.2';
+ case '(R2017b)'
+ vivado = '2017.4';
+ case '(R2018b)'
+ vivado = '2017.4';
+ case '(R2019a)'
+ vivado = '2018.2';
+ case '(R2019b)'
+ vivado = '2018.2';
+ case '(R2020a)'
+ vivado = '2018.2';
+ case '(R2020b)'
+ vivado = '2018.2';
+ case '(R2021a)'
+ vivado = '2018.2';
+ case '(R2021b)'
+ vivado = '2021.1';
+ case '(R2022a)'
+ vivado = '2022.2';
+ end
+ if ispc
+ hdlsetuptoolpath('ToolName', 'Xilinx Vivado', ...
+ 'ToolPath', ['C:\Xilinx\Vivado\',vivado,'\bin\vivado.bat']);
+ elseif isunix
+ hdlsetuptoolpath('ToolName', 'Xilinx Vivado', ...
+ 'ToolPath', ['/opt/Xilinx/Vivado/',vivado,'/bin/vivado']);
+ end
+
+ end
+ end
+
+ methods(TestMethodTeardown)
+ function cleanup_hdl_prj(testCase)
+ dir = fullfile(testCase.root,'test','hdl_prj');
+ if exist(dir, 'dir')
+ rmdir(fullfile(testCase.root,'test','hdl_prj'), 's');
+ end
+ end
+ end
+
+ methods(Test)
+ %function buildHDLDAQ2ZCU102_BOOTBIN(testCase)
+ % cd(fullfile(testCase.root,'test'));
+ % out = hdlworkflow_daq2_zcu102_rx('2018.2');
+ % if ~isempty(out)
+ % disp(out.message);
+ % end
+ % % Check for BOOT.BIN
+ % if exist('hdl_prj/vivado_ip_prj/boot/BOOT.BIN', 'file') ~= 2
+ % error('BOOT.BIN Failed');
+ % end
+ %end
+ end
+
+end
+
diff --git a/test/NonHWTest.m b/test/NonHWTest.m
new file mode 100755
index 0000000..4e04fc9
--- /dev/null
+++ b/test/NonHWTest.m
@@ -0,0 +1,28 @@
+classdef NonHWTest < matlab.unittest.TestCase
+
+ properties(TestParameter)
+ rootClasses = {...
+ {'AD9081',{'Rx','Tx'}},...
+ {'AD9144',{'Tx'}},...
+ {'AD9152',{'Tx'}},...
+ {'AD9467',{'Rx'}},...
+ {'AD9680',{'Rx'}},...
+ {'DAQ2',{'Rx','Tx'}},...
+ {'QuadMxFE',{'Rx','Tx'}}...
+ };
+ end
+
+ methods (Test)
+
+ function call_constructors(testCase,rootClasses)
+ for trx = rootClasses{2}
+ sdr = eval(['adi.',rootClasses{1},'.',trx{:},'()']);
+ testCase.assertEqual(class(sdr),['adi.',rootClasses{1},'.',trx{:}]);
+ end
+ end
+
+ end
+
+
+end
+
diff --git a/test/adi_build.tcl b/test/adi_build.tcl
new file mode 100755
index 0000000..d4d155a
--- /dev/null
+++ b/test/adi_build.tcl
@@ -0,0 +1,79 @@
+global fpga_board
+
+if {[info exists fpga_board]} {
+ puts "==========="
+ puts $fpga_board
+ puts "==========="
+} else {
+ # Set to something not ZCU102
+ set fpga_board "ZYNQ"
+}
+
+# Build the project
+update_compile_order -fileset sources_1
+reset_run impl_1
+reset_run synth_1
+launch_runs synth_1
+wait_on_run synth_1
+launch_runs impl_1 -to_step write_bitstream
+wait_on_run impl_1
+
+# Define local variables
+set cdir [pwd]
+set sdk_loc vivado_prj.sdk
+
+# Export the hdf
+file delete -force $sdk_loc
+file mkdir $sdk_loc
+write_hw_platform -fixed -force -include_bit -file $sdk_loc/system_top.xsa
+
+# Close the Vivado project
+close_project
+
+# Create the BOOT.bin
+#exec xsdk -batch -source $cdir/projects/scripts/fsbl_build.tcl -tclargs $fpga_board -wait
+
+if {$fpga_board eq "ZCU102"} {
+ exec hsi -source $cdir/projects/scripts/pmufw_zynqmp.tcl
+ file copy -force $cdir/projects/scripts/fixmake.sh $cdir/fixmake.sh
+ exec chmod +x fixmake.sh
+
+ #exec ./fixmake.sh
+ #cd pmufw
+ #exec make
+ #cd ..
+ if [catch "exec -ignorestderr ./fixmake.sh" ret opt] {
+ set makeRet [lindex [dict get $opt -errorcode] end]
+ puts "make returned with $makeRet"
+ }
+ if {[file exist pmufw/executable.elf] eq 0} {
+ puts "ERROR: pmufw not built"
+ return -code error 10
+ } else {
+ puts "pmufw built correctly!"
+ }
+
+ set vversion [version -short]
+ exec xsdk -batch -source $cdir/projects/scripts/fsbl_build_zynqmp.tcl $vversion
+ if {[file exist boot/BOOT.BIN] eq 0} {
+ puts "ERROR: BOOT.BIN not built"
+ return -code error 11
+ } else {
+ puts "BOOT.BIN built correctly!"
+ }
+
+} else {
+ exec xsdk -batch -source $cdir/projects/scripts/fsbl_build_zynq.tcl
+ if {[file exist boot/BOOT.BIN] eq 0} {
+ puts "ERROR: BOOT.BIN not built"
+ return -code error 11
+ } else {
+ puts "BOOT.BIN built correctly!"
+ }
+}
+
+puts "------------------------------------"
+puts "Embedded system build completed."
+puts "You may close this shell."
+puts "------------------------------------"
+exit
diff --git a/test/board_variants.m b/test/board_variants.m
new file mode 100755
index 0000000..441c4ab
--- /dev/null
+++ b/test/board_variants.m
@@ -0,0 +1,17 @@
+function r = board_variants
+% Board plugin registration file
+% 1. Any registration file with this name on MATLAB path will be picked up
+% 2. Registration file returns a cell array pointing to the location of
+% the board plugins
+% 3. Board plugin must be a package folder accessible from MATLAB path,
+% and contains a board definition file
+
+% Copyright 2023 The MathWorks, Inc.
+
+r = { ...
+ 'AnalogDevices.cn0585_fmcz.zed.plugin_rd_rx', ...
+ 'AnalogDevices.cn0585_fmcz.zed.plugin_rd_tx', ...
+ 'AnalogDevices.cn0585_fmcz.zed.plugin_rd_rxtx', ...
+ };
+end
+% LocalWords: Zynq ZC
diff --git a/test/build_design.m b/test/build_design.m
new file mode 100755
index 0000000..8930f65
--- /dev/null
+++ b/test/build_design.m
@@ -0,0 +1,82 @@
+
+function out = build_design(config,ReferenceDesignName,vivado_version,mode,board_name,SynthesizeDesign,folder)
+
+%% Restore the Model to default HDL parameters
+%hdlrestoreparams('testModel/HDL_DUT');
+
+%% Set port mapping based on design configuration
+mdl = setportmapping(mode,ReferenceDesignName,board_name);
+
+%% Model HDL Parameters
+
+%% Set Model mdl HDL parameters
+hdlset_param(mdl, 'HDLSubsystem', [mdl,'/HDL_DUT']);
+hdlset_param(mdl, 'ReferenceDesign', ReferenceDesignName);
+hdlset_param(mdl, 'SynthesisTool', config.SupportedTool{:});
+hdlset_param(mdl, 'SynthesisToolChipFamily', config.FPGAFamily);
+hdlset_param(mdl, 'SynthesisToolDeviceName', config.FPGADevice);
+hdlset_param(mdl, 'SynthesisToolPackageName', config.FPGAPackage);
+hdlset_param(mdl, 'SynthesisToolSpeedValue', config.FPGASpeed);
+hdlset_param(mdl, 'TargetPlatform', config.BoardName);
+hdlset_param(mdl, 'TargetLanguage', 'Verilog');
+hdlset_param(mdl, 'TargetDirectory', [folder,'\hdlsrc']);
+hdlset_param(mdl, 'Workflow', 'IP Core Generation');
+hdlset_param([mdl,'/HDL_DUT'], 'ProcessorFPGASynchronization', 'Free running');
+
+%% Workflow Configuration Settings
+% Construct the Workflow Configuration Object with default settings
+hWC = hdlcoder.WorkflowConfig('SynthesisTool','Xilinx Vivado','TargetWorkflow','IP Core Generation');
+
+% Specify the top level project directory
+hWC.ProjectFolder = folder;
+hWC.ReferenceDesignToolVersion = vivado_version;
+hWC.IgnoreToolVersionMismatch = true;
+hWC.AllowUnsupportedToolVersion = true;
+
+% Set Workflow tasks to run
+hWC.RunTaskGenerateRTLCodeAndIPCore = true;
+hWC.RunTaskCreateProject = true;
+hWC.RunTaskGenerateSoftwareInterfaceModel = false;
+hWC.RunTaskBuildFPGABitstream = SynthesizeDesign;
+hWC.RunTaskProgramTargetDevice = false;
+
+% Set properties related to 'RunTaskGenerateRTLCodeAndIPCore' Task
+hWC.IPCoreRepository = '';
+hWC.GenerateIPCoreReport = false;
+
+% Set properties related to 'RunTaskCreateProject' Task
+hWC.Objective = hdlcoder.Objective.None;
+hWC.AdditionalProjectCreationTclFiles = '';
+hWC.EnableIPCaching = false;
+
+% Set properties related to 'RunTaskGenerateSoftwareInterfaceModel' Task
+hWC.OperatingSystem = 'Linux';
+
+% Set properties related to 'RunTaskBuildFPGABitstream' Task
+hWC.RunExternalBuild = false;
+%hWC.TclFileForSynthesisBuild = hdlcoder.BuildOption.Default;
+%hWC.CustomBuildTclFile = '';
+
+hWC.TclFileForSynthesisBuild = hdlcoder.BuildOption.Custom;
+hWC.CustomBuildTclFile = '../hdl/vendor/AnalogDevices/vivado/projects/scripts/adi_build.tcl';
+
+% Set properties related to 'RunTaskProgramTargetDevice' Task
+%hWC.ProgrammingMethod = hdlcoder.ProgrammingMethod.Download;
+%hWC.ProgrammingMethod = hdlcoder.ProgrammingMethod.Custom;
+
+% Validate the Workflow Configuration Object
+hWC.validate;
+
+%% Run the workflow
+try
+ hdlcoder.runWorkflow([mdl,'/HDL_DUT'], hWC, 'Verbosity', 'on');
+ close_system(mdl, false);
+ bdclose('all');
+ out = [];
+catch ME
+ if SynthesizeDesign && exist([folder,'/vivado_ip_prj/boot/BOOT.BIN'],'file')
+ ME = [];
+ end
+ out = ME;%.identifier
+end
+
diff --git a/test/runDemoTests.m b/test/runDemoTests.m
new file mode 100755
index 0000000..e93f62d
--- /dev/null
+++ b/test/runDemoTests.m
@@ -0,0 +1,44 @@
+function suite = runDemoTests(name)
+
+import matlab.unittest.TestRunner;
+import matlab.unittest.TestSuite;
+import matlab.unittest.plugins.TestReportPlugin;
+import matlab.unittest.plugins.XMLPlugin
+import matlab.unittest.plugins.DiagnosticsValidationPlugin
+
+suite = testsuite({'DemoTests'});
+xmlFile = 'BSPDemoTests.xml';
+
+if nargin > 0
+ xmlFile = [name,'_DemoTests.xml'];
+ suite = suite.selectIf('Name',['*',name,'*']);
+end
+
+
+try
+ runner = matlab.unittest.TestRunner.withTextOutput('OutputDetail',1);
+ runner.addPlugin(DiagnosticsValidationPlugin)
+
+ xmlFile = 'BSPDemoTests.xml';
+ plugin = XMLPlugin.producingJUnitFormat(xmlFile);
+ runner.addPlugin(plugin);
+
+ results = runner.run(suite);
+
+ t = table(results);
+ disp(t);
+ disp(repmat('#',1,80));
+ for test = results
+ if test.Failed
+ disp(test.Name);
+ end
+ end
+catch e
+ disp(getReport(e,'extended'));
+ bdclose('all');
+ exit(1);
+end
+
+save(['BSPInstallerTest_',datestr(now,'dd_mm_yyyy-HH:MM:SS'),'.mat'],'t');
+bdclose('all');
+exit(any([results.Failed]));
diff --git a/test/runInstallerTests.m b/test/runInstallerTests.m
new file mode 100755
index 0000000..14825fa
--- /dev/null
+++ b/test/runInstallerTests.m
@@ -0,0 +1,48 @@
+function runInstallerTests(board)
+
+import matlab.unittest.TestRunner;
+import matlab.unittest.TestSuite;
+import matlab.unittest.plugins.TestReportPlugin;
+import matlab.unittest.plugins.XMLPlugin
+import matlab.unittest.plugins.DiagnosticsValidationPlugin
+import matlab.unittest.parameters.Parameter
+
+SynthesizeDesign = {false};
+param = Parameter.fromData('SynthesizeDesign',SynthesizeDesign);
+
+if nargin == 0
+ suite = testsuite({'BSPInstallerTests'});
+else
+ boards = ['*',lower(board),'*'];
+ suite = TestSuite.fromClass(?BSPInstallerTests,'ExternalParameters',param);
+ suite = suite.selectIf('ParameterProperty','configs', 'ParameterName',boards);
+end
+
+try
+
+ runner = matlab.unittest.TestRunner.withTextOutput('OutputDetail',1);
+ runner.addPlugin(DiagnosticsValidationPlugin)
+
+ xmlFile = 'BSPTestResults.xml';
+ plugin = XMLPlugin.producingJUnitFormat(xmlFile);
+ runner.addPlugin(plugin);
+
+ results = runner.run(suite);
+
+ t = table(results);
+ disp(t);
+ disp(repmat('#',1,80));
+ for test = results
+ if test.Failed
+ disp(test.Name);
+ end
+ end
+catch e
+ disp(getReport(e,'extended'));
+ bdclose('all');
+ exit(1);
+end
+
+save(['BSPInstallerTest_',datestr(now,'dd_mm_yyyy-HH:MM:SS'),'.mat'],'t');
+bdclose('all');
+exit(any([results.Failed]));
diff --git a/test/runNonHWTest.m b/test/runNonHWTest.m
new file mode 100755
index 0000000..c3561c1
--- /dev/null
+++ b/test/runNonHWTest.m
@@ -0,0 +1,39 @@
+function suite = runNonHWTest()
+
+import matlab.unittest.TestRunner;
+import matlab.unittest.TestSuite;
+import matlab.unittest.plugins.TestReportPlugin;
+import matlab.unittest.plugins.XMLPlugin
+import matlab.unittest.plugins.DiagnosticsValidationPlugin
+
+suite = testsuite({'NonHWTest'});
+xmlFile = 'BSPDemoTests.xml';
+
+
+try
+ runner = matlab.unittest.TestRunner.withTextOutput('OutputDetail',1);
+ runner.addPlugin(DiagnosticsValidationPlugin)
+
+ xmlFile = 'BSPDemoTests.xml';
+ plugin = XMLPlugin.producingJUnitFormat(xmlFile);
+ runner.addPlugin(plugin);
+
+ results = runner.run(suite);
+
+ t = table(results);
+ disp(t);
+ disp(repmat('#',1,80));
+ for test = results
+ if test.Failed
+ disp(test.Name);
+ end
+ end
+catch e
+ disp(getReport(e,'extended'));
+ bdclose('all');
+ exit(1);
+end
+
+save(['BSPInstallerTest_',datestr(now,'dd_mm_yyyy-HH:MM:SS'),'.mat'],'t');
+bdclose('all');
+exit(any([results.Failed]));
diff --git a/test/runSynthTests.m b/test/runSynthTests.m
new file mode 100644
index 0000000..e0fdc67
--- /dev/null
+++ b/test/runSynthTests.m
@@ -0,0 +1,68 @@
+function runSynthTests(board)
+
+import matlab.unittest.TestRunner;
+import matlab.unittest.TestSuite;
+import matlab.unittest.plugins.TestReportPlugin;
+import matlab.unittest.plugins.XMLPlugin
+import matlab.unittest.plugins.ToUniqueFile;
+import matlab.unittest.plugins.TAPPlugin;
+import matlab.unittest.plugins.DiagnosticsValidationPlugin
+import matlab.unittest.parameters.Parameter
+
+runParallel = false;
+SynthesizeDesign = {true};
+param = Parameter.fromData('SynthesizeDesign',SynthesizeDesign);
+
+if nargin == 0
+ suite = testsuite({'BSPTests'});
+else
+ boards = ['*',lower(board),'*'];
+ suite = TestSuite.fromClass(?BSPTests,'ExternalParameters',param);
+ suite = suite.selectIf('ParameterProperty','configs', 'ParameterName',boards);
+end
+
+try
+
+ runner = matlab.unittest.TestRunner.withTextOutput('OutputDetail',4);
+ runner.addPlugin(DiagnosticsValidationPlugin)
+
+ xmlFile = 'BSPTestResults.xml';
+ plugin = XMLPlugin.producingJUnitFormat(xmlFile);
+ runner.addPlugin(plugin);
+
+ if runParallel
+ try %#ok
+ parpool(4);
+ results = runInParallel(runner,suite);
+ catch ME
+ disp(ME);
+ results = runner.run(suite);
+ end
+ else
+ results = runner.run(suite);
+ end
+
+ t = table(results);
+ disp(t);
+ disp(repmat('#',1,80));
+ for test = results
+ if test.Failed
+ disp(test.Name);
+ end
+ end
+catch e
+ disp(getReport(e,'extended'));
+ bdclose('all');
+ exit(1);
+end
+
+try
+ poolobj = gcp('nocreate');
+ delete(poolobj);
+catch ME
+ disp(ME)
+end
+
+save(['BSPTest_',datestr(now,'dd_mm_yyyy-HH:MM:SS'),'.mat'],'t');
+bdclose('all');
+exit(any([results.Failed]));
diff --git a/test/setportmapping.m b/test/setportmapping.m
new file mode 100644
index 0000000..295644e
--- /dev/null
+++ b/test/setportmapping.m
@@ -0,0 +1,106 @@
+function mdl = setportmapping(mode,ReferenceDesignName,board_name)
+
+% ! this script will work with test models that have 16 data ports and 4
+% boolean ports
+
+if contains(lower(ReferenceDesignName),'cn0585')
+ dev = 'CN0585';
+ mdl = 'testModel';
+ portWidthRX = 16;
+ portWidthTX = 16;
+else
+ error('Unknown device');
+end
+
+load_system(mdl);
+
+% First set all ports to NIS
+for k=1:16
+ hdlset_param([mdl,'/HDL_DUT/in',num2str(k)], 'IOInterface', 'No Interface Specified');
+ hdlset_param([mdl,'/HDL_DUT/in',num2str(k)], 'IOInterfaceMapping', '');
+ hdlset_param([mdl,'/HDL_DUT/out',num2str(k)], 'IOInterface', 'No Interface Specified');
+ hdlset_param([mdl,'/HDL_DUT/out',num2str(k)], 'IOInterfaceMapping', '');
+end
+
+for k = 1:4
+ hdlset_param([mdl,'/HDL_DUT/validIn',num2str(k)], 'IOInterface', 'No Interface Specified');
+ hdlset_param([mdl,'/HDL_DUT/validIn',num2str(k)], 'IOInterfaceMapping', '');
+ hdlset_param([mdl,'/HDL_DUT/validOut',num2str(k)], 'IOInterface', 'No Interface Specified');
+ hdlset_param([mdl,'/HDL_DUT/validOut',num2str(k)], 'IOInterfaceMapping', '');
+end
+
+
+filePath = '../CI/ports.json';
+str = fileread(filePath);
+val = jsondecode(str);
+
+fn = fieldnames(val);
+
+for k = 1:numel(fn)
+ x = val.(fn{k});
+ if (strcmp(x.chip, dev))
+ inIndex = 1;
+ outIndex = 1;
+ validInIndex = 1;
+ validOutIndex = 1;
+ if (mode == "rx") || (mode == "rxtx")
+ rx = x.ports.rx;
+ for indexRx = 1:numel(rx)
+ element = rx(indexRx);
+ if(element.type == "data")
+ if(element.input == "true")
+ hdlset_param([mdl,'/HDL_DUT/in',num2str(inIndex)], 'IOInterface', [element.m_name,' [0:',num2str(portWidthRX-1),']']);
+ hdlset_param([mdl,'/HDL_DUT/in',num2str(inIndex)], 'IOInterfaceMapping', ['[0:',num2str(portWidthRX-1),']']);
+ inIndex = inIndex + 1;
+ else
+ hdlset_param([mdl,'/HDL_DUT/out',num2str(outIndex)], 'IOInterface', [element.m_name,' [0:',num2str(portWidthRX-1),']']);
+ hdlset_param([mdl,'/HDL_DUT/out',num2str(outIndex)], 'IOInterfaceMapping', ['[0:',num2str(portWidthRX-1),']']);
+ outIndex = outIndex + 1;
+ end
+ elseif (element.type == "valid")
+ if(element.input == "true")
+ hdlset_param([mdl,'/HDL_DUT/validIn',num2str(validInIndex)], 'IOInterface', element.m_name);
+ hdlset_param([mdl,'/HDL_DUT/validIn',num2str(validInIndex)], 'IOInterfaceMapping', '[0]');
+ validInIndex = validInIndex + 1;
+ else
+ hdlset_param([mdl,'/HDL_DUT/validOut',num2str(validOutIndex)], 'IOInterface', element.m_name);
+ hdlset_param([mdl,'/HDL_DUT/validOut',num2str(validOutIndex)], 'IOInterfaceMapping', '[0]');
+ validOutIndex = validOutIndex + 1;
+ end
+ end
+ end
+
+ end
+ if (mode == "tx") || (mode == "rxtx")
+ tx = x.ports.tx;
+ if (mode == "tx")
+ inIndex = 1;
+ outIndex = 1;
+ end
+ for indexTx = 1:numel(tx)
+ element = tx(indexTx);
+ if(element.type == "data")
+ if(element.input == "true")
+ hdlset_param([mdl,'/HDL_DUT/in',num2str(inIndex)], 'IOInterface', [element.m_name,' [0:',num2str(portWidthTX-1),']']);
+ hdlset_param([mdl,'/HDL_DUT/in',num2str(inIndex)], 'IOInterfaceMapping', ['[0:',num2str(portWidthTX-1),']']);
+ inIndex = inIndex + 1;
+ else
+ hdlset_param([mdl,'/HDL_DUT/out',num2str(outIndex)], 'IOInterface', [element.m_name,' [0:',num2str(portWidthTX-1),']']);
+ hdlset_param([mdl,'/HDL_DUT/out',num2str(outIndex)], 'IOInterfaceMapping', ['[0:',num2str(portWidthTX-1),']']);
+ outIndex = outIndex + 1;
+ end
+ elseif (element.type == "valid")
+ if(element.input == "true")
+ hdlset_param([mdl,'/HDL_DUT/validIn',num2str(validInIndex)], 'IOInterface', element.m_name);
+ hdlset_param([mdl,'/HDL_DUT/validIn',num2str(validInIndex)], 'IOInterfaceMapping', '[0]');
+ validInIndex = validInIndex + 1;
+ else
+ hdlset_param([mdl,'/HDL_DUT/validOut',num2str(validOutIndex)], 'IOInterface', element.m_name);
+ hdlset_param([mdl,'/HDL_DUT/validOut',num2str(validOutIndex)], 'IOInterfaceMapping', '[0]');
+ validOutIndex = validOutIndex + 1;
+ end
+ end
+ end
+ end
+ end
+end
diff --git a/test/testModel.slx b/test/testModel.slx
new file mode 100755
index 0000000..7021254
Binary files /dev/null and b/test/testModel.slx differ