From e5de6b624dbd0658cad400ff38d4c575df403264 Mon Sep 17 00:00:00 2001 From: Stanca Pop Date: Tue, 19 Sep 2023 12:40:53 +0300 Subject: [PATCH] Tmp commit for custom lldk --- .../zynq-zed-adv7511-cn0585.dts | 0 .../+common/add_io.m | 17 +++ .../hdlcoder_ref_design_customization.m | 20 ++++ .../+common/plugin_board.m | 29 +++++ .../+common/plugin_rd.m | 110 ++++++++++++++++++ .../+zed/+tx/add_tx_io.m | 107 +++++++++++++++++ .../+tx/hdlcoder_ref_design_customization.m | 20 ++++ .../+zed/+tx/plugin_board.m | 9 ++ .../+zed/+tx/plugin_rd.m | 8 ++ .../build_bsp.sh | 88 ++++++++++++++ .../hdlworkflow_cn0585_gpio_zed_tx.m | 38 ++++++ .../testModel_Tx16and8.slx | Bin 0 -> 45619 bytes .../targeting/cn0585_fmcz/adi_build.tcl | 59 ++++++++++ .../cn0585_fmcz/cn0585_hdl/fh_preprocess.tcl | 8 ++ .../matlab_processors.tcl | 12 +- .../ports.json | 86 +++++++++----- .../cn0585_hdl/system_project_rxtx.tcl | 37 ++++++ 17 files changed, 610 insertions(+), 38 deletions(-) rename pcx_examples/targeting/cn0585_fmcz/{cn0585_axi4_lite_demo => +AnalogDevicesDemo/+cn0585_axi4_lite_demo}/zynq-zed-adv7511-cn0585.dts (100%) create mode 100644 pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/add_io.m create mode 100644 pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/hdlcoder_ref_design_customization.m create mode 100644 pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/plugin_board.m create mode 100644 pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/plugin_rd.m create mode 100644 pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/add_tx_io.m create mode 100644 pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/hdlcoder_ref_design_customization.m create mode 100644 pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/plugin_board.m create mode 100644 pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/plugin_rd.m create mode 100755 pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/build_bsp.sh create mode 100644 pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/hdlworkflow_cn0585_gpio_zed_tx.m create mode 100644 pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/testModel_Tx16and8.slx create mode 100644 pcx_examples/targeting/cn0585_fmcz/adi_build.tcl create mode 100644 pcx_examples/targeting/cn0585_fmcz/cn0585_hdl/fh_preprocess.tcl rename pcx_examples/targeting/cn0585_fmcz/{cn0585_led_sw_gpio_control_demo => cn0585_hdl}/matlab_processors.tcl (94%) rename pcx_examples/targeting/cn0585_fmcz/{cn0585_led_sw_gpio_control_demo => cn0585_hdl}/ports.json (63%) create mode 100644 pcx_examples/targeting/cn0585_fmcz/cn0585_hdl/system_project_rxtx.tcl diff --git a/pcx_examples/targeting/cn0585_fmcz/cn0585_axi4_lite_demo/zynq-zed-adv7511-cn0585.dts b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_axi4_lite_demo/zynq-zed-adv7511-cn0585.dts similarity index 100% rename from pcx_examples/targeting/cn0585_fmcz/cn0585_axi4_lite_demo/zynq-zed-adv7511-cn0585.dts rename to pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_axi4_lite_demo/zynq-zed-adv7511-cn0585.dts diff --git a/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/add_io.m b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/add_io.m new file mode 100644 index 0000000..6cd8cdc --- /dev/null +++ b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/add_io.m @@ -0,0 +1,17 @@ +% function add_io(hRD,project,fpga,type) +% +% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% % Add AXI4 and AXI4-Lite slave interfaces +% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% out = AnalogDevices.get_memory_axi_interface_info(fpga,lower(project)); +% hRD.addAXI4SlaveInterface( ... +% 'InterfaceConnection', out.InterfaceConnection, ... +% 'BaseAddress', out.BaseAddress, ... +% 'MasterAddressSpace', out.MasterAddressSpace); +% +% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% % Add Reference design interfaces +% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% AnalogDevices.add_io_ports(hRD,lower(project),lower(type),lower(fpga)); +% +% end diff --git a/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/hdlcoder_ref_design_customization.m b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/hdlcoder_ref_design_customization.m new file mode 100644 index 0000000..31e4cea --- /dev/null +++ b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/hdlcoder_ref_design_customization.m @@ -0,0 +1,20 @@ +function [rd,boardName] = hdlcoder_ref_design_customization +% Reference design plugin registration file +% 1. The registration file with this name inside of a board plugin folder +% will be picked up +% 2. Any registration file with this name on MATLAB path will also be picked up +% 3. The registration file returns a cell array pointing to the location of +% the reference design plugins +% 4. The registration file also returns its associated board name +% 5. Reference design plugin must be a package folder accessible from +% MATLAB path, and contains a reference design definition file + +% Copyright 2013-2014 The MathWorks, Inc. + +rd = {... + 'AnalogDevicesDemo.cn0585_led_sw_gpio_control_demo.zed.tx.plugin_rd', ... + }; + +boardName = 'AnalogDevices CN0585 GPIO Control'; + +end diff --git a/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/plugin_board.m b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/plugin_board.m new file mode 100644 index 0000000..27d0b67 --- /dev/null +++ b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/plugin_board.m @@ -0,0 +1,29 @@ +function hB = plugin_board(BoardName) +% Use Plugin API to create board plugin object + +% Copyright 2015 The MathWorks, Inc. + +hB = hdlcoder.Board; + +% Target Board Information +hB.BoardName = sprintf('AnalogDevices CN0585 GPIO Control'); + +% FPGA Device +hB.FPGAVendor = 'Xilinx'; +hB.FPGAFamily = 'Zynq'; + +% Determine the device based on the board + +hB.FPGADevice = sprintf('xc7%s', 'z020'); +hB.FPGAPackage = 'clg484'; +hB.FPGASpeed = '-1'; +hB.FPGAFamily = 'Zynq'; + +% Tool Info +hB.SupportedTool = {'Xilinx Vivado'}; + +% FPGA JTAG chain position +hB.JTAGChainPosition = 2; + +%% Add interfaces +% Standard "External Port" interface diff --git a/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/plugin_rd.m b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/plugin_rd.m new file mode 100644 index 0000000..53ff2ba --- /dev/null +++ b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/plugin_rd.m @@ -0,0 +1,110 @@ +function hRD = plugin_rd(board, design) +% Reference design definition + +% Copyright 2014-2015 The MathWorks, Inc. + +% pname = upper(project); +% ppath = project; +% if strcmpi(project, 'cn0585') +% ppath = 'cn0585_fmcz'; +% end + +board = 'zed'; +design = 'Tx'; + +hRD = hdlcoder.ReferenceDesign('SynthesisTool', 'Xilinx Vivado'); + +% This is the base reference design that other RDs can build upon +hRD.ReferenceDesignName = sprintf('%s (%s)', upper(board), design); + +% Determine the board name based on the design +hRD.BoardName = sprintf('AnalogDevices CN0585 GPIO Control'); + +% Tool information +hRD.SupportedToolVersion = {'2022.2'}; + +% Get the root directories +rootDirExample = fileparts(strtok(mfilename('fullpath'), '+')); +tmp = strsplit(rootDirExample,filesep); + +if isunix + rootDir = fullfile(filesep,tmp{1:end-3}); +else + rootDir = fullfile(tmp{1:end-3}); +end +rootDirBSP = fullfile('hdl','vendor','AnalogDevices','vivado'); + +% Design files are shared +hRD.SharedRD = true; +hRD.SharedRDFolder = rootDir; + +%% Set top level project pieces +hRD.addParameter( ... + 'ParameterID', 'project', ... + 'DisplayName', 'HDL Project Subfolder', ... + 'DefaultValue', 'cn0585_led_sw_gpio_control_demo'); + +hRD.addParameter( ... + 'ParameterID', 'carrier', ... + 'DisplayName', 'HDL Project Carrier', ... + 'DefaultValue', 'zed'); + +%% Add custom design files +hRD.addCustomVivadoDesign( ... + 'CustomBlockDesignTcl', fullfile('hdl','vendor','AnalogDevices','vivado','projects','scripts', 'system_project_rxtx.tcl')); + +%% Standard reference design pieces +hRD.BlockDesignName = 'system'; + +% custom source files +hRD.CustomFiles = {... + fullfile('projects')..., + fullfile('library')..., + fullfile('scripts')..., + }; + +% custom source files +hRD.CustomFiles = {... + fullfile(rootDirBSP, 'scripts')..., + fullfile(rootDirBSP, 'library')..., + fullfile(rootDirBSP, 'library','xilinx')..., + fullfile(rootDirBSP, 'projects','common')..., + fullfile(rootDirBSP, 'projects','scripts')..., + fullfile(rootDirBSP, 'projects','cn0585_fmcz')..., + fullfile(rootDirBSP, 'projects','cn0585_fmcz', 'common')..., + fullfile(rootDirBSP, 'projects','cn0585_fmcz', 'zed')..., + fullfile('pcx_examples', 'targeting', 'cn0585_fmcz', 'cn0585_hdl')..., + }; + +hRD.addParameter( ... + 'ParameterID', 'ref_design', ... + 'DisplayName', 'Reference Type', ... + 'DefaultValue', lower(strrep(design, ' & ',''))); + +hRD.addParameter( ... + 'ParameterID', 'fpga_board', ... + 'DisplayName', 'FPGA Boad', ... + 'DefaultValue', upper(board)); + +hRD.addParameter( ... + 'ParameterID', 'preprocess', ... + 'DisplayName', 'Preprocess', ... + 'DefaultValue', 'on'); +hRD.addParameter( ... + 'ParameterID', 'preprocess_script', ... + 'DisplayName', 'Preprocess Script', ... + 'DefaultValue', fullfile('pcx_examples', 'targeting', 'cn0585_fmcz','fh_preprocess.tcl')); + +hRD.addParameter( ... + 'ParameterID', 'postprocess', ... + 'DisplayName', 'Postprocess', ... + 'DefaultValue', 'off'); + +%% Add IO +%AnalogDevices.add_io(hRD,'cn0585_led_sw_gpio_control_demo',board,design); + +%% Add interfaces +% add clock interface +hRD.addClockInterface( ... + 'ClockConnection', 'axi_clkgen/clk_0', ... + 'ResetConnection', 'sampling_clk_rstgen/peripheral_aresetn'); diff --git a/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/add_tx_io.m b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/add_tx_io.m new file mode 100644 index 0000000..a5c9ae0 --- /dev/null +++ b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/add_tx_io.m @@ -0,0 +1,107 @@ +function add_tx_io(hRD) + +% add AXI4 and AXI4-Lite slave interfaces +hRD.addAXI4SlaveInterface( ... + 'InterfaceConnection', 'axi_cpu_interconnect/M20_AXI', ... + 'BaseAddress', '0x43C00000', ... + 'MasterAddressSpace', 'sys_ps7/Data'); + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% Tx Reference design interfaces +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 0 IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'axi_ltc2387_0_adc_data', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ltc2387_0/adc_data', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 1 IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'axi_ltc2387_1_adc_data', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ltc2387_1/adc_data', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 2 IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'axi_ltc2387_2_adc_data', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ltc2387_2/adc_data', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 3 IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'axi_ltc2387_3_adc_data', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ltc2387_3/adc_data', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Load Tx Data OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'axi_ad3552r_0_valid_in_a', ... + 'PortWidth', 1, ... + 'InterfaceConnection', 'axi_ad3552r_0/valid_in_a', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Valid Tx Data IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'axi_ltc2387_0_adc_valid', ... + 'PortWidth', 1, ... + 'InterfaceConnection', 'axi_ltc2387_0/adc_valid', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'CN0585 DAC Data 0 OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'axi_ad3552r_0_data_in_a', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ad3552r_0/data_in_a', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'CN0585 DAC Data 1 OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'axi_ad3552r_0_data_in_b', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ad3552r_0/data_in_b', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'CN0585 DAC Data 2 OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'axi_ad3552r_1_data_in_a', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ad3552r_1/data_in_a', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'CN0585 DAC Data 3 OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'axi_ad3552r_1_data_in_b', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ad3552r_1/data_in_b', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'GPIO IN SW', ... + 'InterfaceType', 'IN', ... + 'PortName', 'xlslice_1_Dout', ... + 'PortWidth', 8, ... + 'InterfaceConnection', 'xlslice_1/Dout', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'GPIO OUT LED', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'xlconcat_1_In1', ... + 'PortWidth', 8, ... + 'InterfaceConnection', 'xlconcat_1/In1', ... + 'IsRequired', false); diff --git a/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/hdlcoder_ref_design_customization.m b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/hdlcoder_ref_design_customization.m new file mode 100644 index 0000000..350b2b3 --- /dev/null +++ b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/hdlcoder_ref_design_customization.m @@ -0,0 +1,20 @@ +function [rd, boardName] = hdlcoder_ref_design_customization +% Reference design plugin registration file +% 1. The registration file with this name inside of a board plugin folder +% will be picked up +% 2. Any registration file with this name on MATLAB path will also be picked up +% 3. The registration file returns a cell array pointing to the location of +% the reference design plugins +% 4. The registration file also returns its associated board name +% 5. Reference design plugin must be a package folder accessible from +% MATLAB path, and contains a reference design definition file + +% Copyright 2013-2014 The MathWorks, Inc. + +rd = {... + 'AnalogDevicesDemo.cn0585_led_sw_gpio_control_demo.zed.tx.plugin_rd', ... + }; + +boardName = 'AnalogDevicesDemo cn0585_led_sw_gpio_control AnalogDevies CN0585 GPIO Control (Tx)'; + +end diff --git a/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/plugin_board.m b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/plugin_board.m new file mode 100644 index 0000000..8e69678 --- /dev/null +++ b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/plugin_board.m @@ -0,0 +1,9 @@ +function hP = plugin_board() +% Zynq Platform PCore +% Use Plugin API to create board plugin object + +% Copyright 2015 The MathWorks, Inc. + +% Call the common board definition function +% hP = AnalogDevicesDemo.cn0585_led_sw_gpio_control_demo.common.plugin_board('AnalogDevies CN0585 GPIO Control ', 'Tx'); +hP = AnalogDevicesDemo.cn0585_led_sw_gpio_control_demo.common.plugin_board('AnalogDevies CN0585 GPIO Control'); \ No newline at end of file diff --git a/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/plugin_rd.m b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/plugin_rd.m new file mode 100644 index 0000000..f381dcf --- /dev/null +++ b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/plugin_rd.m @@ -0,0 +1,8 @@ +function hRD = plugin_rd +% Reference design definition + +% Copyright 2014-2015 The MathWorks, Inc. + +% Call the common reference design definition function +hRD = AnalogDevicesDemo.cn0585_led_sw_gpio_control_demo.common.plugin_rd('AnalogDevies CN0585 GPIO Control', 'Tx'); +AnalogDevicesDemo.cn0585_led_sw_gpio_control_demo.zed.tx.add_tx_io(hRD); diff --git a/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/build_bsp.sh b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/build_bsp.sh new file mode 100755 index 0000000..7cb1529 --- /dev/null +++ b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/build_bsp.sh @@ -0,0 +1,88 @@ +#!/bin/bash +set -x +cd "$(dirname "$0")" +if [ -z "${HDLBRANCH}" ]; then +HDLBRANCH='cn0585_pr' +fi + +# Script is designed to run from specific location +scriptdir=`dirname "$BASH_SOURCE"` +cd $scriptdir +#cd .. +# Get HDL +if [ -d "hdl" ]; then + rm -rf "hdl" +fi +for i in {1..5} +do + if git clone --single-branch -b $HDLBRANCH https://github.com/analogdevicesinc/hdl.git + then + break + fi + if [ -d "hdl" ]; then + break + fi +done +if [ ! -d "hdl" ]; then + echo "HDL clone failed" + exit 1 +fi + +# Get required vivado version needed for HDL +if [ -f "hdl/library/scripts/adi_ip.tcl" ]; then + TARGET="hdl/library/scripts/adi_ip.tcl" +else + TARGET="hdl/library/scripts/adi_ip_xilinx.tcl" +fi +VER=$(awk '/set required_vivado_version/ {print $3}' $TARGET | sed 's/"//g') +echo "Required Vivado version ${VER}" +VIVADOFULL=${VER} +if [ ${#VER} = 8 ] +then +VER=${VER:0:6} +fi +VIVADO=${VER} + +# Setup +#source /opt/Xilinx/Vivado/$VIVADO/settings64.sh +source /emea/mediadata/opt/Xilinx/Vivado/$VIVADO/settings64.sh + +# Rename .prj files since MATLAB ignores then during packaging +FILES=$(grep -lrn hdl/projects/common -e '.prj' | grep -v Makefile | grep -v .git) +for f in $FILES +do + echo "Updating prj reference in: $f" + sed -i "s/\.prj/\.mk/g" "$f" +done +FILES=$(find hdl/projects/common -name "*.prj") +for f in $FILES +do + DEST="${f::-3}mk" + echo "Renaming: $f to $DEST" + mv "$f" "$DEST" +done + +# Remove git directory move to bsp folder +rm -fr hdl/.git* +TARGET="../../../../../hdl/vendor/AnalogDevices/vivado" +if [ -d "$TARGET" ]; then + rm -rf "$TARGET" +fi + +mv hdl $TARGET + +# Post-process ports.json +cp ./ports.json ../../../../../CI/ +python3 ../../../../../CI/scripts/read_ports_json.py +cp ../../../../../CI/ports.json ../../../../../hdl/vendor/AnalogDevices/+AnalogDevices/ + +# Updates +cp ./matlab_processors.tcl ../../../../../hdl/vendor/AnalogDevices/vivado/projects/scripts/matlab_processors.tcl +cp ./system_project_rxtx.tcl ../../../../../hdl/vendor/AnalogDevices/vivado/projects/scripts/system_project_rxtx.tcl +cp ../../adi_build.tcl ../../../../../hdl/vendor/AnalogDevices/vivado/projects/scripts/adi_build.tcl + +# Copy boot files +mkdir ../../../../../hdl/vendor/AnalogDevices/vivado/projects/common/boot/ +cp -r ../../../../../CI/scripts/boot/* ../../../../../hdl/vendor/AnalogDevices/vivado/projects/common/boot/ + +echo 'puts "Skipping"' > ../../../../../hdl/vendor/AnalogDevices/vivado/library/axi_ad9361/axi_ad9361_delay.tcl diff --git a/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/hdlworkflow_cn0585_gpio_zed_tx.m b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/hdlworkflow_cn0585_gpio_zed_tx.m new file mode 100644 index 0000000..bd9e518 --- /dev/null +++ b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/hdlworkflow_cn0585_gpio_zed_tx.m @@ -0,0 +1,38 @@ +function out = hdlworkflow_cn0585_gpio_zed_tx(vivado) + +if nargin < 1 + vivado = '2022.2'; +end + +%-------------------------------------------------------------------------- +% HDL Workflow Script +% Generated with MATLAB 9.8 (R2020a) at 12:56:00 on 24/09/2020 +% This script was generated using the following parameter values: +% Filename : '/tmp/hsx-add-boot-bin-test/test/hdlworkflow_daq2_zcu102_rx.m' +% Overwrite : true +% Comments : true +% Headers : true +% DUT : 'testModel_Rx64Tx64/HDL_DUT' +% To view changes after modifying the workflow, run the following command: +% >> hWC.export('DUT','testModel_Rx64Tx64/HDL_DUT'); +%-------------------------------------------------------------------------- + +%% Load the Model +load_system('testModel_Tx16and8'); + +%% Restore the Model to default HDL parameters +hdlrestoreparams('testModel_Tx16and8/HDL_DUT'); + +%% Model HDL Parameters +%% Set Model 'testModel_Rx64Tx64' HDL parameters +hdlset_param('testModel_Tx16and8', 'HDLSubsystem', 'testModel_Tx16and8/HDL_DUT'); +hdlset_param('testModel_Tx16and8', 'ReferenceDesign', 'AnalogDevies CN0585 GPIO Control (TX)'); +hdlset_param('testModel_Tx16and8', 'SynthesisTool', 'Xilinx Vivado'); +hdlset_param('testModel_Tx16and8', 'SynthesisToolChipFamily', 'Zynq'); +hdlset_param('testModel_Tx16and8', 'SynthesisToolDeviceName', 'xc7z020-clg484-1'); +hdlset_param('testModel_Tx16and8', 'SynthesisToolPackageName', ''); +hdlset_param('testModel_Tx16and8', 'SynthesisToolSpeedValue', ''); +hdlset_param('testModel_Tx16and8', 'TargetDirectory', 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