diff --git a/CI/ci_flags.md b/CI/ci_flags.md new file mode 100644 index 0000000..b8ee9e5 --- /dev/null +++ b/CI/ci_flags.md @@ -0,0 +1,7 @@ +# CI Signaling + +Its possible to configure CI on build a project based on flags in the commit message. This is done by adding a special line to the commit that starts with CI: (must be all caps). The line can contain a list of flags separated by semi-colons. The following flags are supported: +- skip= +- skip_branch=: +- enable_only_branch=: +- env:= diff --git a/CI/doc/Makefile b/CI/doc/Makefile new file mode 100644 index 0000000..f664662 --- /dev/null +++ b/CI/doc/Makefile @@ -0,0 +1,28 @@ +# Minimal makefile for Sphinx documentation +# + +# You can set these variables from the command line, and also +# from the environment for the first two. +SPHINXOPTS ?= +SPHINXBUILD ?= sphinx-build +SOURCEDIR = source +BUILDDIR = build + +PYTHON = python + +# Put it first so that "make" without argument is like "make help". +help: + @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) + +.PHONY: help Makefile + +# Catch-all target: route all unknown targets to Sphinx using the new +# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS). +%: Makefile + @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) + +gen_autodocs: + cd gen_pages ; \ + $(PYTHON) gen_sysobj_pages.py ; \ + $(PYTHON) gen_rd_svg.py ; \ + $(PYTHON) gen_hdl_refdesigns.py diff --git a/CI/doc/README_doc.md b/CI/doc/README_doc.md new file mode 100644 index 0000000..5d1ea87 --- /dev/null +++ b/CI/doc/README_doc.md @@ -0,0 +1,24 @@ +# Doc Creation + +Doc is create by leveraging Sphinx as the documentation engine. To create the entire documentation set you must generate the dynamic pages which document the system object APIs and the reference designs. Then the output targets can be run. Since doc gen requires sphinx and some plugins they need to be installed first and ideally in a virtual environment. The following commands will create a virtual environment and install the necessary packages: + +```bash +python3 -m venv venv +source venv/bin/activate +pip install -r CI/doc/requirements_doc.txt +``` + +Next we can build the documentation. The following commands will build the documentation and place it in the *build* folder under the *CI/doc* folder: + +```bash +make -C CI/doc gen_autodocs html +``` + +## Updating the System Object Documentation + +The system object documentation is generated from the MATLAB code and comments, which requires use of MATLAB itself. By running the script gen_sysobj_doc.m within the *gen_pages* folder, it will create the necessary sysobjs.json file which sphinx will then use to create the individual component pages. This is done by running the following command from the root of the toolbox in MATLAB: + +```matlab +cd CI/doc/gen_pages +gen_sysobj_doc +``` diff --git a/CI/doc/gen_pages/Makefile b/CI/doc/gen_pages/Makefile new file mode 100644 index 0000000..e7b54bc --- /dev/null +++ b/CI/doc/gen_pages/Makefile @@ -0,0 +1,14 @@ +# Define the Python interpreter +PYTHON = python + +# Define the targets and their dependencies +all: gen_sysobj_pages gen_rd_svg gen_hdl_refdesigns + +gen_sysobj_pages: + $(PYTHON) gen_sysobj_pages.py + +gen_rd_svg: + $(PYTHON) gen_rd_svg.py + +gen_hdl_refdesigns: + $(PYTHON) gen_hdl_refdesigns.py \ No newline at end of file diff --git a/CI/doc/gen_pages/_templates/allrefdesigns.tmpl b/CI/doc/gen_pages/_templates/allrefdesigns.tmpl new file mode 100644 index 0000000..c4c2a86 --- /dev/null +++ b/CI/doc/gen_pages/_templates/allrefdesigns.tmpl @@ -0,0 +1,20 @@ +{% include 'header.tmpl' %} +# HDL Reference Designs + +Available hardware streaming interfaces in HSX Toolbox: + + +```{eval-rst} +.. toctree:: + :maxdepth: 1 +{% for obj in designs %} + _generated/hdlrefdesigns/{{ obj }} +{%- endfor %} + +``` + + + +Click on left table of contents for individual component pages. \ No newline at end of file diff --git a/CI/doc/gen_pages/_templates/allsysobjs.tmpl b/CI/doc/gen_pages/_templates/allsysobjs.tmpl new file mode 100644 index 0000000..01186f1 --- /dev/null +++ b/CI/doc/gen_pages/_templates/allsysobjs.tmpl @@ -0,0 +1,20 @@ +{% include 'header.tmpl' %} +# Hardware Interface APIs + +Available hardware streaming interfaces in HSX Toolbox: + + +```{eval-rst} +.. toctree:: + :maxdepth: 1 +{% for obj in devices %} + _generated/sysobjects/{{ obj }} +{%- endfor %} + +``` + + + +Click on left table of contents for individual component pages. \ No newline at end of file diff --git a/CI/doc/gen_pages/_templates/header.tmpl b/CI/doc/gen_pages/_templates/header.tmpl new file mode 100644 index 0000000..5b41e10 --- /dev/null +++ b/CI/doc/gen_pages/_templates/header.tmpl @@ -0,0 +1,7 @@ +{%- if disable_nav -%} +--- +hide: + - navigation + - toc +--- +{%- endif -%} \ No newline at end of file diff --git a/CI/doc/gen_pages/_templates/refdesign.html b/CI/doc/gen_pages/_templates/refdesign.html new file mode 100644 index 0000000..f19dbe5 --- /dev/null +++ b/CI/doc/gen_pages/_templates/refdesign.html @@ -0,0 +1,46 @@ +{% block content %} + +# {{ obj.name }} Reference Design Integration + +This page outlines the HDL reference design integration for the *{{ obj.name }}* reference design for the Analog Devices +{{ obj.chip }} component. The IP-Core Generation follow is available on the based on the following base HDL reference design for the following board and design variants: + +- [Base reference design documentation]({{ obj.hdl_rd_doc }}) +- Supported FPGA carriers: +{%- for carrier in obj.fpga %} + - {{ carrier.upper() }} +{%- endfor %} +- Supported design variants: +{%- for supported_rd in obj.supported_rd %} + - {{ supported_rd.upper() }} +{%- endfor %} + +## Reference Design + + {% if obj.rd_image == "ad9361" %} +```{figure} /_static/assets/rd_ad9361_custom.svg + {% elif obj.rd_image == "adrv9001" %} +```{figure} /_static/assets/rd_adrv9001_custom.svg + {% elif obj.rd_image == "jesd" %} +```{figure} /_static/assets/rd_jesd_custom.svg + {% endif %} +HDL Reference Design with Custom IP from HDL-Coder. Click on sub-blocks for more documentation. +``` + +The IP-Core generation flow will integrate IP generated from Simulink subsystem into an ADI authored reference design. Depending on the FPGA carrier and FMC card or SoM, this will support different IP locations based on the diagram above. + +## HDL Worflow Advisor Port Mappings + +When using the HDL Worflow Advisor, the following port mappings are used to connect the reference design to the HDL-Coder generated IP-Core: + +| Type | Target Platform Interface (MATLAB) | Reference Design Connection (Vivado) | Width | Reference Design Variant | +| ---- | ------------------------ | --------------------------- | ----- | ----------- | +{%- for rds in obj.ports[0] %} + +{%- for rd in obj.ports[0][rds] %} +| {{ rd['type'].upper() }}-{% if rd['input' == "true"] %}IN{% else %}OUT{% endif %} | {{ rd['m_name'] }} | {{ rd['name'] }} | {{ rd['width'] }} | {{ rds.upper() }} | +{%- endfor %} + +{%- endfor %} + +{% endblock %} diff --git a/CI/doc/gen_pages/_templates/sysobj.html b/CI/doc/gen_pages/_templates/sysobj.html new file mode 100644 index 0000000..2bd6e66 --- /dev/null +++ b/CI/doc/gen_pages/_templates/sysobj.html @@ -0,0 +1,94 @@ +{% block content %} +# {{ obj.name }} + + + + + + +
+ +{{ obj.dec }} + + +
+ +
Creation
+ +The class can be instantiated in the following way with and without property name value pairs. + +```matlab +dev = {{ obj.name }} +dev = {{ obj.name }}(Name, Value) +``` + +
Properties
+ +
+ +Unless otherwise indicated, properties are non-tunable, which means you cannot change their values after calling the object. Objects lock when you call them, and the release function unlocks them. +

+If a property is tunable, you can change its value at any time. +

+For more information on changing property values, see System Design in MATLAB Using System Objects. + +
+
+ + +{% for prop in obj.props %} +:::{dropdown} {{ prop.prop_name }} +{{ prop.prop_description }} +::: +{% endfor -%} + + + + +{% endblock %} + +
+
Example Usage
+ +```matlab +{% if obj.type == "Tx" %} +%% Configure device +tx = {{ obj.name }}; +tx.uri = 'ip:analog.local'; +{% if obj.name == "adi.ADRV9002.Tx" %} +tx.CenterFrequencyChannel0 = 1e9; +{% else %} +tx.CenterFrequency = 1e9; +{% endif %} +tx.DataSource = 'DMA'; +tx.EnableCyclicBuffers = true; +tx.EnabledChannels = 1; +%% Generate tone +amplitude = 2^15; frequency = 0.12e6; +swv1 = dsp.SineWave(amplitude, frequency); +swv1.ComplexOutput = true; +swv1.SamplesPerFrame = 2^14; +swv1.SampleRate = tx.SamplingRate; +y = swv1(); +% Send +tx(y); +{% else %} +%% Rx set up +rx = {{ obj.name }}('uri','ip:analog.local'); +{% if obj.name == "adi.ADRV9002.Rx" %} +rx.CenterFrequencyChannel0 = 1e9; +{% else %} +rx.CenterFrequency = 1e9; +{% endif %} +rx.EnabledChannels = 1; +%% Run +for k=1:10 + valid = false; + while ~valid + [out, valid] = rx(); + end +end +{% endif %} +``` diff --git a/CI/doc/gen_pages/gen_hdl_refdesigns.py b/CI/doc/gen_pages/gen_hdl_refdesigns.py new file mode 100644 index 0000000..e6bc42c --- /dev/null +++ b/CI/doc/gen_pages/gen_hdl_refdesigns.py @@ -0,0 +1,83 @@ +from jinja2 import Environment, FileSystemLoader +import os +import json +import numpy as np + + +def update_hdl_refdesigns(): + + template_filename = "refdesign.html" + + folder_of_this_file = os.path.dirname(__file__) + source_folder = os.path.join(folder_of_this_file, "..", "source") + + ci_scripts_folder = os.path.join(folder_of_this_file, "..", "..", "scripts") + + _generated_folder = os.path.join(folder_of_this_file, "..", "source", "_generated") + if not os.path.exists(_generated_folder): + os.mkdir(_generated_folder) + + hdlrefdesigns_folder = os.path.join(_generated_folder, "hdlrefdesigns") + if not os.path.exists(hdlrefdesigns_folder): + os.mkdir(hdlrefdesigns_folder) + + + with open(os.path.join(ci_scripts_folder, "ports.json")) as f: + objs = json.load(f) + + # Import template + loc = os.path.dirname(__file__) + loc = os.path.join(loc, "_templates") + file_loader = FileSystemLoader(loc) + env = Environment(loader=file_loader) + + loc = os.path.join(template_filename) + template = env.get_template(loc) + + designs = {} + + for obj in objs: + + print("Generating", obj) + + # Render template + objs[obj]["name"] = obj + + if objs[obj]["name"] in ["fmcomms2", "adrv9361z7035", "adrv9364z7020", "pluto"]: + objs[obj]["rd_image"] = "ad9361" + elif objs[obj]["name"] in ["adrv9002"]: + objs[obj]["rd_image"] = "adrv9001" + else: + objs[obj]["rd_image"] = "jesd" + + output = template.render(obj=objs[obj]) + # Write output + output_filename = os.path.join(hdlrefdesigns_folder, f"{obj}.md") + loc = os.path.join(output_filename) + f = open(loc, "w") + f.write(output) + f.close() + designs[obj] = output_filename + + # # Update mkdocs.yml + # loc = os.path.join("mkdocs.tmpl") + # template = env.get_template(loc) + # output = template.render(designs=designs) + + # loc = os.path.join("..", "mkdocs.yml") + # with open(loc, "w") as f: + # f.write(output) + + # Create allrefdesigns.md + loc = os.path.join("allrefdesigns.tmpl") + template = env.get_template(loc) + output = template.render(designs=designs) + + loc = os.path.join(source_folder, "allrefdesigns.md") + with open(loc, "w") as f: + f.write(output) + + return designs + +if __name__ == "__main__": + update_hdl_refdesigns() diff --git a/CI/doc/gen_pages/gen_rd_svg.py b/CI/doc/gen_pages/gen_rd_svg.py new file mode 100644 index 0000000..9ce4c8e --- /dev/null +++ b/CI/doc/gen_pages/gen_rd_svg.py @@ -0,0 +1,105 @@ +import os + +def gen_rd_svg(): + + folder_of_this_file = os.path.dirname(__file__) + assets_folder = os.path.join(folder_of_this_file, "..", "source", "_static", "assets") + stylesheets_folder = os.path.join(folder_of_this_file, "..", "source", "_static", "css") + + refs = ["rd_ad9361","rd_adrv9001","rd_jesd"] + css_out = "" + + for ref in refs: + + print("Generating svg for", ref) + + with open(os.path.join(assets_folder,f"{ref}.svg"), "r") as f: + svg = f.read() + + selectable_boxes = { + "AXIAD9361Box": {"link": "https://wiki.analog.com/resources/fpga/docs/axi_ad9361"}, + "AXIADRV9002Box": {"link": "https://wiki.analog.com/resources/eval/user-guides/adrv9002/axi_adrv9002"}, + "TxDMAEngineBox": {"link": "https://wiki.analog.com/resources/fpga/docs/axi_dmac"}, + "TxUPACKBox": {"link": "https://wiki.analog.com/resources/fpga/docs/util_upack"}, + "TxFIFOBox": {"link": "https://wiki.analog.com/resources/fpga/docs/util_rfifo"}, + "RxDMAEngineBox": {"link": "https://wiki.analog.com/resources/fpga/docs/axi_dmac"}, + "CPACKBox": {"link": "https://wiki.analog.com/resources/fpga/docs/util_cpack"}, + "RxFIFOBox": {"link": "https://wiki.analog.com/resources/fpga/docs/util_rfifo"}, + "RxJESDTPL": {"link": "https://wiki.analog.com/resources/fpga/peripherals/jesd204/jesd204_tpl_adc"}, + "TxJESDTPL": {"link": "https://wiki.analog.com/resources/fpga/peripherals/jesd204/jesd204_tpl_dac"}, + "RxJESDLink": {"link": "https://wiki.analog.com/resources/fpga/peripherals/jesd204/axi_jesd204_rx"}, + "TxJESDLink": {"link": "https://wiki.analog.com/resources/fpga/peripherals/jesd204/axi_jesd204_tx"}, + "RxJESDPHY": {"link": "https://wiki.analog.com/resources/fpga/docs/axi_adxcvr"}, + "TxJESDPHY": {"link": "https://wiki.analog.com/resources/fpga/docs/axi_adxcvr"}, + } + + + # "TxCustomIPBox", + # CarrierBox + # AXIInterconnectBox + # ZynqBox + # DDRxBox + # InterruptsBox + # UARTBox + # EthernetBox + # RxCustomIPBox + # CustomIPOutline + + + # Parse each g tag + output = "" + for i, sec in enumerate(svg.split("") + 4 + gtag = o[:loc] + post_gtag = o[loc:] + # print(gtag) + loc = gtag.find("id=") + 4 + id = gtag[loc : gtag.find('"', loc)] + if id == "CarrierBox": + css_out += ( + f"\n#{id} > rect {{\n" + + " fill: var(--md-default-fg-color--light);\n" + + "}\n" + ) + + + if not id or id not in selectable_boxes: + output += o + continue + # Add link wrapper + output += f'{gtag}{post_gtag}' + # output += o + # print(sec) + # Add css to change fill color + css_out += f"#{id} > rect {{\n" + " stroke: white;\n" + "}\n" + css_out += f"\n#{id}:hover > rect {{\n" + " fill: rgb(0, 174, 255);\n" + "}\n" + + + + with open(os.path.join(assets_folder,f"{ref}_custom.svg"), "w") as f: + f.write(output) + + css_out += "\n#FPGACarrierText {\n" + " fill: var(--rd-title-color);\n" + "}\n" + css_out += "\n#CarrierBox > rect {\n" + " fill: none;\n stroke: black\n" + "}\n" + css_out += ( + "\n#CustomIPOutline > rect {\n" + " stroke: var(--rd-title-color);\n" + "}\n" + ) + css_out += ("\n#CustomIPIntegrationText {\n" + " fill: var(--rd-title-color);\n" + "}\n") + + print("Writing css") + with open(os.path.join(stylesheets_folder,"rd_style.css"), "w") as f: + f.write(css_out) + +if __name__ == "__main__": + gen_rd_svg() \ No newline at end of file diff --git a/CI/doc/gen_pages/gen_sysobj_doc.m b/CI/doc/gen_pages/gen_sysobj_doc.m new file mode 100644 index 0000000..eb6ffe8 --- /dev/null +++ b/CI/doc/gen_pages/gen_sysobj_doc.m @@ -0,0 +1,74 @@ +[filepath,name,ext] = fileparts(mfilename('fullpath')); +cd(filepath); +cd('..'); +files = dir(filepath); + +mfiledir = fullfile('adi'); +docdir = fullfile('doc'); + +rootClasses = {... + {'Attribute'},... + {'DDS'},... + {'Tx'},... + {'BufferADI'},... + {'Channel'},... + {'DDS'},... + {'DebugAttribute'},... + {'DeviceAttribute'},... + {'RegisterReadWrite'},... + {'Rx'},... + {'RxTx'},... + {'Sensor'},... + }; + +all_devs = []; +for ii = 1:numel(rootClasses) + part = rootClasses{ii}{1}; + all_props = []; + dotmfilename = strcat(part); + props = properties(dotmfilename); + for prop = 1:length(props) + + if props{prop} == "enIO" + continue; + end + pdoc = help(strcat(dotmfilename,'.',props{prop})); + + pdocs = strsplit(pdoc,'\n'); + prop_title = pdocs{1}; + prop_description = strip(replace(strjoin(pdocs(2:end),'\n'),'\n','')); + prop_description = int32(prop_description); + prop_description(prop_description==10) = []; + prop_description(prop_description==13) = []; + prop_description = char(prop_description); + prop_description = replace(prop_description,' ',' '); + prop_description = replace(prop_description,' ',' '); + + s = struct('prop_name',props{prop},... + 'prop_title',prop_title,... + 'prop_description',prop_description); + all_props = [all_props,s]; + end + top_doc = help(dotmfilename); + top_doc = strsplit(top_doc,'\n'); + top_doc = replace(top_doc,'\n','
'); + top_doc = strjoin(top_doc(2:end),'
'); + +% top_doc = strip(replace(top_doc,'\n','')); +% top_doc = int32(top_doc); +% top_doc(top_doc==10) = []; +% top_doc(top_doc==13) = []; +% top_doc = char(top_doc); +% top_doc = replace(top_doc,' ',' '); +% top_doc = replace(top_doc,' ',' '); + + + oname = struct('name',dotmfilename, 'dec',top_doc, 'props',all_props); + all_devs = [all_devs, oname]; +end +%% +jsonText = jsonencode(all_devs,'PrettyPrint',true); +fid = fopen('docs/sysobjs.json', 'w'); +fprintf(fid, '%s', jsonText); +fclose(fid); + diff --git a/CI/doc/gen_pages/gen_sysobj_pages.py b/CI/doc/gen_pages/gen_sysobj_pages.py new file mode 100644 index 0000000..6f8a628 --- /dev/null +++ b/CI/doc/gen_pages/gen_sysobj_pages.py @@ -0,0 +1,101 @@ +from jinja2 import Environment, FileSystemLoader +import os +import json + + +def gen_sys_obj_pages(matlab): + + folder_of_this_file = os.path.dirname(__file__) + + source_folder = os.path.join(folder_of_this_file, "..", "source") + + _generated_folder = os.path.join(folder_of_this_file, "..", "source", "_generated") + if not os.path.exists(_generated_folder): + os.mkdir(_generated_folder) + + sys_obj_gen_folder = os.path.join(_generated_folder, "sysobjects") + if not os.path.exists(sys_obj_gen_folder): + os.mkdir(sys_obj_gen_folder) + + + template_filename = "sysobj.html" + + # Data for template + if not os.path.exists("sysobjs.json"): + raise Exception("sysobjs.json not found. Run gen_sysobj_doc.m first.") + with open("sysobjs.json") as f: + objs = json.load(f) + + # Import template + loc = os.path.dirname(__file__) + loc = os.path.join(loc, "_templates") + file_loader = FileSystemLoader(loc) + env = Environment(loader=file_loader) + + loc = os.path.join(template_filename) + template = env.get_template(loc) + + devices = {} + + def cleanup(obj): + + obj["dec"] = obj["dec"].replace("192.168.2.1", "ip:192.168.2.1") + d = obj["dec"] + ol = [] + for d in obj["dec"].split("
"): + + if "See also" in d: + continue + if "Documentation for" in d: + continue + if "doc adi." in d: + continue + + ol.append(d) + + obj["dec"] = "
".join(ol) + if ".Rx" in obj["name"]: + obj["type"] = "Rx" + else: + obj["type"] = "Tx" + + return obj + + for obj in objs: + print("Generating doc page for", obj["name"]) + # Render template + obj = cleanup(obj) + output = template.render(obj=obj, disable_nav=matlab) + # Write output + output_filename = os.path.join(sys_obj_gen_folder, f"{obj['name']}.md") + # output_filename = f"sysobjects/{obj['name']}.md" + loc = os.path.join(output_filename) + f = open(loc, "w") + f.write(output) + f.close() + devices[obj["name"]] = output_filename + + # Create allsysobjs.md + loc = os.path.join("allsysobjs.tmpl") + template = env.get_template(loc) + output = template.render(devices=devices, disable_nav=matlab) + + loc = os.path.join(source_folder, "objects.md") + with open(loc, "w") as f: + f.write(output) + + + if matlab: + # Generate index for objs + loc = os.path.join("allsysobjs.tmpl") + template = env.get_template(loc) + output = template.render(devices=devices, disable_nav=matlab) + + loc = os.path.join("objects.md") + with open(loc, "w") as f: + f.write(output) + + return devices + +if __name__ == "__main__": + gen_sys_obj_pages(False) diff --git a/CI/doc/gen_pages/sysobjs.json b/CI/doc/gen_pages/sysobjs.json new file mode 100644 index 0000000..8f44916 --- /dev/null +++ b/CI/doc/gen_pages/sysobjs.json @@ -0,0 +1,569 @@ +[ + { + "name": "Attribute", + "dec": " Documentation for Attribute
doc Attribute
", + "props": [ + { + "prop_name": "uri", + "prop_title": " URI - remote host URI", + "prop_description": "Hostname or IP address of remote libIIO deviceHelp for Attribute/uri is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "SamplesPerFrame", + "prop_title": " Frame size", + "prop_description": "Size of the frame in samplesHelp for Attribute/SamplesPerFrame is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "devName", + "prop_title": " Device name", + "prop_description": "Name of the libIIO deviceHelp for Attribute/devName is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "kernelBuffersCount", + "prop_title": " Kernel buffers count", + "prop_description": "The number of buffers allocated in the kernel for data transfersHelp for Attribute/kernelBuffersCount is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "dataTypeStr", + "prop_title": " Data type for the output data", + "prop_description": "A String Representing the data typeHelp for Attribute/dataTypeStr is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "channelCount", + "prop_title": " Number of channels", + "prop_description": "Number of enabled channelsHelp for Attribute/channelCount is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "DataTimeout", + "prop_title": " Timeout for I/O", + "prop_description": "Timeout for I/O operations (in seconds) 0 = non-blocking (or default context timeout) Inf = infiniteHelp for Attribute/DataTimeout is inherited from superclass matlabshared.libiio.base" + } + ] + }, + { + "name": "DDS", + "dec": " Documentation for DDS
doc DDS
DDS Blockset Documentation
doc DDS
", + "props": [ + { + "prop_name": "DataSource", + "prop_title": " DataSource Data Source", + "prop_description": "Data source, specified as one of the following: 'DMA' — Specify the host as the source of the data. 'DDS' — Specify the DDS on the radio hardware as the source of the data. In this case, each channel has two additive tones." + }, + { + "prop_name": "DDSFrequencies", + "prop_title": " DDSFrequencies DDS Frequencies", + "prop_description": "Frequencies values in Hz of the DDS tone generators. For complex data devices the input is a [2xN] matrix where N is the available channels on the board. For complex data devices this is at most max(EnabledChannels)*2. For non-complex data devices this is at most max(EnabledChannels). If N < this upper limit, other DDSs are not set." + }, + { + "prop_name": "DDSScales", + "prop_title": " DDSScales DDS Scales", + "prop_description": "Scale of DDS tones in range [0,1]. For complex data devices the input is a [2xN] matrix where N is the available channels on the board. For complex data devices this is at most max(EnabledChannels)*2. For non-complex data devices this is at most max(EnabledChannels). If N < this upper limit, other DDSs are not set." + }, + { + "prop_name": "DDSPhases", + "prop_title": " DDSPhases DDS Phases", + "prop_description": "Phases of DDS tones in range [0,360000]. For complex data devices the input is a [2xN] matrix where N is the available channels on the board. For complex data devices this is at most max(EnabledChannels)*2. For non-complex data devices this is at most max(EnabledChannels). If N < this upper limit, other DDSs are not set." + }, + { + "prop_name": "EnableCyclicBuffers", + "prop_title": " EnableCyclicBuffers Enable Cyclic Buffers", + "prop_description": "Enable Cyclic Buffers, configures transmit buffers to be cyclic, which makes them continuously repeat" + }, + { + "prop_name": "EnabledChannels", + "prop_title": "DDS/EnabledChannels is a property.", + "prop_description": "" + }, + { + "prop_name": "uri", + "prop_title": " URI - remote host URI", + "prop_description": "Hostname or IP address of remote libIIO deviceHelp for DDS/uri is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "SamplesPerFrame", + "prop_title": " Frame size", + "prop_description": "Size of the frame in samplesHelp for DDS/SamplesPerFrame is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "devName", + "prop_title": " Device name", + "prop_description": "Name of the libIIO deviceHelp for DDS/devName is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "kernelBuffersCount", + "prop_title": " Kernel buffers count", + "prop_description": "The number of buffers allocated in the kernel for data transfersHelp for DDS/kernelBuffersCount is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "dataTypeStr", + "prop_title": " Data type for the output data", + "prop_description": "A String Representing the data typeHelp for DDS/dataTypeStr is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "channelCount", + "prop_title": " Number of channels", + "prop_description": "Number of enabled channelsHelp for DDS/channelCount is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "DataTimeout", + "prop_title": " Timeout for I/O", + "prop_description": "Timeout for I/O operations (in seconds) 0 = non-blocking (or default context timeout) Inf = infiniteHelp for DDS/DataTimeout is inherited from superclass matlabshared.libiio.base" + } + ] + }, + { + "name": "Tx", + "dec": " Documentation for Tx
doc Tx
", + "props": [ + { + "prop_name": "EnabledChannels", + "prop_title": " EnabledChannels Enabled Channels", + "prop_description": "Indexs of channels to be enabled. Input should be a [1xN] vector with the indexes of channels to be enabled. Order is irrelevant" + }, + { + "prop_name": "uri", + "prop_title": " URI - remote host URI", + "prop_description": "Hostname or IP address of remote libIIO deviceHelp for Tx/uri is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "SamplesPerFrame", + "prop_title": " Frame size", + "prop_description": "Size of the frame in samplesHelp for Tx/SamplesPerFrame is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "devName", + "prop_title": " Device name", + "prop_description": "Name of the libIIO deviceHelp for Tx/devName is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "kernelBuffersCount", + "prop_title": " Kernel buffers count", + "prop_description": "The number of buffers allocated in the kernel for data transfersHelp for Tx/kernelBuffersCount is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "dataTypeStr", + "prop_title": " Data type for the output data", + "prop_description": "A String Representing the data typeHelp for Tx/dataTypeStr is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "DataSource", + "prop_title": " DataSource Data Source", + "prop_description": "Data source, specified as one of the following: 'DMA' — Specify the host as the source of the data. 'DDS' — Specify the DDS on the radio hardware as the source of the data. In this case, each channel has two additive tones.Help for Tx/DataSource is inherited from superclass adi.common.DDS" + }, + { + "prop_name": "DDSFrequencies", + "prop_title": " DDSFrequencies DDS Frequencies", + "prop_description": "Frequencies values in Hz of the DDS tone generators. For complex data devices the input is a [2xN] matrix where N is the available channels on the board. For complex data devices this is at most max(EnabledChannels)*2. For non-complex data devices this is at most max(EnabledChannels). If N < this upper limit, other DDSs are not set.Help for Tx/DDSFrequencies is inherited from superclass adi.common.DDS" + }, + { + "prop_name": "DDSScales", + "prop_title": " DDSScales DDS Scales", + "prop_description": "Scale of DDS tones in range [0,1]. For complex data devices the input is a [2xN] matrix where N is the available channels on the board. For complex data devices this is at most max(EnabledChannels)*2. For non-complex data devices this is at most max(EnabledChannels). If N < this upper limit, other DDSs are not set.Help for Tx/DDSScales is inherited from superclass adi.common.DDS" + }, + { + "prop_name": "DDSPhases", + "prop_title": " DDSPhases DDS Phases", + "prop_description": "Phases of DDS tones in range [0,360000]. For complex data devices the input is a [2xN] matrix where N is the available channels on the board. For complex data devices this is at most max(EnabledChannels)*2. For non-complex data devices this is at most max(EnabledChannels). If N < this upper limit, other DDSs are not set.Help for Tx/DDSPhases is inherited from superclass adi.common.DDS" + }, + { + "prop_name": "EnableCyclicBuffers", + "prop_title": " EnableCyclicBuffers Enable Cyclic Buffers", + "prop_description": "Enable Cyclic Buffers, configures transmit buffers to be cyclic, which makes them continuously repeatHelp for Tx/EnableCyclicBuffers is inherited from superclass adi.common.DDS" + } + ] + }, + { + "name": "BufferADI", + "dec": " Documentation for BufferADI
doc BufferADI
", + "props": [ + { + "prop_name": "uri", + "prop_title": " URI - remote host URI", + "prop_description": "Hostname or IP address of remote libIIO deviceHelp for BufferADI/uri is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "SamplesPerFrame", + "prop_title": " Frame size", + "prop_description": "Size of the frame in samplesHelp for BufferADI/SamplesPerFrame is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "devName", + "prop_title": " Device name", + "prop_description": "Name of the libIIO deviceHelp for BufferADI/devName is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "kernelBuffersCount", + "prop_title": " Kernel buffers count", + "prop_description": "The number of buffers allocated in the kernel for data transfersHelp for BufferADI/kernelBuffersCount is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "dataTypeStr", + "prop_title": " Data type for the output data", + "prop_description": "A String Representing the data typeHelp for BufferADI/dataTypeStr is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "channelCount", + "prop_title": " Number of channels", + "prop_description": "Number of enabled channelsHelp for BufferADI/channelCount is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "DataTimeout", + "prop_title": " Timeout for I/O", + "prop_description": "Timeout for I/O operations (in seconds) 0 = non-blocking (or default context timeout) Inf = infiniteHelp for BufferADI/DataTimeout is inherited from superclass matlabshared.libiio.base" + } + ] + }, + { + "name": "Channel", + "dec": " Documentation for Channel
helpwin Channel
", + "props": [ + { + "prop_name": "uri", + "prop_title": " URI - remote host URI", + "prop_description": "Hostname or IP address of remote libIIO deviceHelp for Channel/uri is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "SamplesPerFrame", + "prop_title": " Frame size", + "prop_description": "Size of the frame in samplesHelp for Channel/SamplesPerFrame is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "devName", + "prop_title": " Device name", + "prop_description": "Name of the libIIO deviceHelp for Channel/devName is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "kernelBuffersCount", + "prop_title": " Kernel buffers count", + "prop_description": "The number of buffers allocated in the kernel for data transfersHelp for Channel/kernelBuffersCount is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "dataTypeStr", + "prop_title": " Data type for the output data", + "prop_description": "A String Representing the data typeHelp for Channel/dataTypeStr is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "channelCount", + "prop_title": " Number of channels", + "prop_description": "Number of enabled channelsHelp for Channel/channelCount is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "DataTimeout", + "prop_title": " Timeout for I/O", + "prop_description": "Timeout for I/O operations (in seconds) 0 = non-blocking (or default context timeout) Inf = infiniteHelp for Channel/DataTimeout is inherited from superclass matlabshared.libiio.base" + } + ] + }, + { + "name": "DDS", + "dec": " Documentation for DDS
doc DDS
DDS Blockset Documentation
doc DDS
", + "props": [ + { + "prop_name": "DataSource", + "prop_title": " DataSource Data Source", + "prop_description": "Data source, specified as one of the following: 'DMA' — Specify the host as the source of the data. 'DDS' — Specify the DDS on the radio hardware as the source of the data. In this case, each channel has two additive tones." + }, + { + "prop_name": "DDSFrequencies", + "prop_title": " DDSFrequencies DDS Frequencies", + "prop_description": "Frequencies values in Hz of the DDS tone generators. For complex data devices the input is a [2xN] matrix where N is the available channels on the board. For complex data devices this is at most max(EnabledChannels)*2. For non-complex data devices this is at most max(EnabledChannels). If N < this upper limit, other DDSs are not set." + }, + { + "prop_name": "DDSScales", + "prop_title": " DDSScales DDS Scales", + "prop_description": "Scale of DDS tones in range [0,1]. For complex data devices the input is a [2xN] matrix where N is the available channels on the board. For complex data devices this is at most max(EnabledChannels)*2. For non-complex data devices this is at most max(EnabledChannels). If N < this upper limit, other DDSs are not set." + }, + { + "prop_name": "DDSPhases", + "prop_title": " DDSPhases DDS Phases", + "prop_description": "Phases of DDS tones in range [0,360000]. For complex data devices the input is a [2xN] matrix where N is the available channels on the board. For complex data devices this is at most max(EnabledChannels)*2. For non-complex data devices this is at most max(EnabledChannels). If N < this upper limit, other DDSs are not set." + }, + { + "prop_name": "EnableCyclicBuffers", + "prop_title": " EnableCyclicBuffers Enable Cyclic Buffers", + "prop_description": "Enable Cyclic Buffers, configures transmit buffers to be cyclic, which makes them continuously repeat" + }, + { + "prop_name": "EnabledChannels", + "prop_title": "DDS/EnabledChannels is a property.", + "prop_description": "" + }, + { + "prop_name": "uri", + "prop_title": " URI - remote host URI", + "prop_description": "Hostname or IP address of remote libIIO deviceHelp for DDS/uri is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "SamplesPerFrame", + "prop_title": " Frame size", + "prop_description": "Size of the frame in samplesHelp for DDS/SamplesPerFrame is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "devName", + "prop_title": " Device name", + "prop_description": "Name of the libIIO deviceHelp for DDS/devName is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "kernelBuffersCount", + "prop_title": " Kernel buffers count", + "prop_description": "The number of buffers allocated in the kernel for data transfersHelp for DDS/kernelBuffersCount is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "dataTypeStr", + "prop_title": " Data type for the output data", + "prop_description": "A String Representing the data typeHelp for DDS/dataTypeStr is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "channelCount", + "prop_title": " Number of channels", + "prop_description": "Number of enabled channelsHelp for DDS/channelCount is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "DataTimeout", + "prop_title": " Timeout for I/O", + "prop_description": "Timeout for I/O operations (in seconds) 0 = non-blocking (or default context timeout) Inf = infiniteHelp for DDS/DataTimeout is inherited from superclass matlabshared.libiio.base" + } + ] + }, + { + "name": "DebugAttribute", + "dec": " obj = DebugAttribute
Documentation for DebugAttribute
doc DebugAttribute
", + "props": [ + { + "prop_name": "uri", + "prop_title": " URI - remote host URI", + "prop_description": "Hostname or IP address of remote libIIO deviceHelp for DebugAttribute/uri is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "SamplesPerFrame", + "prop_title": " Frame size", + "prop_description": "Size of the frame in samplesHelp for DebugAttribute/SamplesPerFrame is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "devName", + "prop_title": " Device name", + "prop_description": "Name of the libIIO deviceHelp for DebugAttribute/devName is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "kernelBuffersCount", + "prop_title": " Kernel buffers count", + "prop_description": "The number of buffers allocated in the kernel for data transfersHelp for DebugAttribute/kernelBuffersCount is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "dataTypeStr", + "prop_title": " Data type for the output data", + "prop_description": "A String Representing the data typeHelp for DebugAttribute/dataTypeStr is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "channelCount", + "prop_title": " Number of channels", + "prop_description": "Number of enabled channelsHelp for DebugAttribute/channelCount is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "DataTimeout", + "prop_title": " Timeout for I/O", + "prop_description": "Timeout for I/O operations (in seconds) 0 = non-blocking (or default context timeout) Inf = infiniteHelp for DebugAttribute/DataTimeout is inherited from superclass matlabshared.libiio.base" + } + ] + }, + { + "name": "DeviceAttribute", + "dec": " Documentation for DeviceAttribute
doc DeviceAttribute
", + "props": [ + { + "prop_name": "uri", + "prop_title": " URI - remote host URI", + "prop_description": "Hostname or IP address of remote libIIO deviceHelp for DeviceAttribute/uri is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "SamplesPerFrame", + "prop_title": " Frame size", + "prop_description": "Size of the frame in samplesHelp for DeviceAttribute/SamplesPerFrame is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "devName", + "prop_title": " Device name", + "prop_description": "Name of the libIIO deviceHelp for DeviceAttribute/devName is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "kernelBuffersCount", + "prop_title": " Kernel buffers count", + "prop_description": "The number of buffers allocated in the kernel for data transfersHelp for DeviceAttribute/kernelBuffersCount is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "dataTypeStr", + "prop_title": " Data type for the output data", + "prop_description": "A String Representing the data typeHelp for DeviceAttribute/dataTypeStr is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "channelCount", + "prop_title": " Number of channels", + "prop_description": "Number of enabled channelsHelp for DeviceAttribute/channelCount is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "DataTimeout", + "prop_title": " Timeout for I/O", + "prop_description": "Timeout for I/O operations (in seconds) 0 = non-blocking (or default context timeout) Inf = infiniteHelp for DeviceAttribute/DataTimeout is inherited from superclass matlabshared.libiio.base" + } + ] + }, + { + "name": "RegisterReadWrite", + "dec": " obj = RegisterReadWrite
Documentation for RegisterReadWrite
doc RegisterReadWrite
", + "props": [ + { + "prop_name": "uri", + "prop_title": " URI - remote host URI", + "prop_description": "Hostname or IP address of remote libIIO deviceHelp for RegisterReadWrite/uri is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "SamplesPerFrame", + "prop_title": " Frame size", + "prop_description": "Size of the frame in samplesHelp for RegisterReadWrite/SamplesPerFrame is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "devName", + "prop_title": " Device name", + "prop_description": "Name of the libIIO deviceHelp for RegisterReadWrite/devName is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "kernelBuffersCount", + "prop_title": " Kernel buffers count", + "prop_description": "The number of buffers allocated in the kernel for data transfersHelp for RegisterReadWrite/kernelBuffersCount is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "dataTypeStr", + "prop_title": " Data type for the output data", + "prop_description": "A String Representing the data typeHelp for RegisterReadWrite/dataTypeStr is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "channelCount", + "prop_title": " Number of channels", + "prop_description": "Number of enabled channelsHelp for RegisterReadWrite/channelCount is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "DataTimeout", + "prop_title": " Timeout for I/O", + "prop_description": "Timeout for I/O operations (in seconds) 0 = non-blocking (or default context timeout) Inf = infiniteHelp for RegisterReadWrite/DataTimeout is inherited from superclass matlabshared.libiio.base" + } + ] + }, + { + "name": "Rx", + "dec": " Documentation for Rx
doc Rx
", + "props": [ + { + "prop_name": "EnabledChannels", + "prop_title": " EnabledChannels Enabled Channels", + "prop_description": "Indexs of channels to be enabled. Input should be a [1xN] vector with the indexes of channels to be enabled. Order is irrelevant" + }, + { + "prop_name": "uri", + "prop_title": " URI - remote host URI", + "prop_description": "Hostname or IP address of remote libIIO deviceHelp for Rx/uri is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "SamplesPerFrame", + "prop_title": " Frame size", + "prop_description": "Size of the frame in samplesHelp for Rx/SamplesPerFrame is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "devName", + "prop_title": " Device name", + "prop_description": "Name of the libIIO deviceHelp for Rx/devName is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "kernelBuffersCount", + "prop_title": " Kernel buffers count", + "prop_description": "The number of buffers allocated in the kernel for data transfersHelp for Rx/kernelBuffersCount is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "dataTypeStr", + "prop_title": " Data type for the output data", + "prop_description": "A String Representing the data typeHelp for Rx/dataTypeStr is inherited from superclass matlabshared.libiio.base" + } + ] + }, + { + "name": "RxTx", + "dec": " obj = RxTx
Documentation for RxTx
doc RxTx
", + "props": [ + { + "prop_name": "EnabledChannels", + "prop_title": " EnabledChannels Enabled Channels", + "prop_description": "Indexs of channels to be enabled. Input should be a [1xN] vector with the indexes of channels to be enabled. Order is irrelevant" + }, + { + "prop_name": "uri", + "prop_title": " URI - remote host URI", + "prop_description": "Hostname or IP address of remote libIIO deviceHelp for RxTx/uri is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "SamplesPerFrame", + "prop_title": " Frame size", + "prop_description": "Size of the frame in samplesHelp for RxTx/SamplesPerFrame is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "devName", + "prop_title": " Device name", + "prop_description": "Name of the libIIO deviceHelp for RxTx/devName is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "kernelBuffersCount", + "prop_title": " Kernel buffers count", + "prop_description": "The number of buffers allocated in the kernel for data transfersHelp for RxTx/kernelBuffersCount is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "dataTypeStr", + "prop_title": " Data type for the output data", + "prop_description": "A String Representing the data typeHelp for RxTx/dataTypeStr is inherited from superclass matlabshared.libiio.base" + } + ] + }, + { + "name": "Sensor", + "dec": " Documentation for Sensor
helpwin Sensor
", + "props": [ + { + "prop_name": "ReadMode", + "prop_title": " ReadMode Read Mode", + "prop_description": "Specify whether to return the latest or the oldest data samples. The number of samples depends on the SamplesPerRead value. The data read from the sensor is stored in the MATLAB buffer." + }, + { + "prop_name": "OutputFormat", + "prop_title": " Set the output format of the data returned by executing the read", + "prop_description": "function. When the OutputFormat is set to timetable, the data returned has the following fields (if supported by device): Time — Time stamps in datetime or duration format Acceleration — N-by-3 array in units of m/s^2 AngularVelocity — N-by-3 array in units of rad/s MagneticField — N-by-3 array in units of µT (microtesla) When the OutputFormat is set to matrix, the data is returned as matrices of acceleration, angular velocity, magnetic field, and time stamps. The units for the sensor readings are the same as the timetable format. The size of each matrix is N-by-3. N is the number of samples per read specified by SamplesPerRead. The three columns of each field represent the measurements in x, y, and z axes." + }, + { + "prop_name": "SamplesPerRead", + "prop_title": " SamplesPerRead Samples Per Read", + "prop_description": "Number of samples per read, specified as a positive integer." + }, + { + "prop_name": "EnabledChannels", + "prop_title": " EnabledChannels Enabled Channels", + "prop_description": "Indexs of channels to be enabled. Input should be a [1xN] vector with the indexes of channels to be enabled. Order is irrelevant" + }, + { + "prop_name": "uri", + "prop_title": " URI - remote host URI", + "prop_description": "Hostname or IP address of remote libIIO deviceHelp for Sensor/uri is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "devName", + "prop_title": " Device name", + "prop_description": "Name of the libIIO deviceHelp for Sensor/devName is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "kernelBuffersCount", + "prop_title": " Kernel buffers count", + "prop_description": "The number of buffers allocated in the kernel for data transfersHelp for Sensor/kernelBuffersCount is inherited from superclass matlabshared.libiio.base" + }, + { + "prop_name": "dataTypeStr", + "prop_title": " Data type for the output data", + "prop_description": "A String Representing the data typeHelp for Sensor/dataTypeStr is inherited from superclass matlabshared.libiio.base" + } + ] + } +] \ No newline at end of file diff --git a/CI/doc/make.bat b/CI/doc/make.bat new file mode 100644 index 0000000..6247f7e --- /dev/null +++ b/CI/doc/make.bat @@ -0,0 +1,35 @@ +@ECHO OFF + +pushd %~dp0 + +REM Command file for Sphinx documentation + +if "%SPHINXBUILD%" == "" ( + set SPHINXBUILD=sphinx-build +) +set SOURCEDIR=source +set BUILDDIR=build + +if "%1" == "" goto help + +%SPHINXBUILD% >NUL 2>NUL +if errorlevel 9009 ( + echo. + echo.The 'sphinx-build' command was not found. Make sure you have Sphinx + echo.installed, then set the SPHINXBUILD environment variable to point + echo.to the full path of the 'sphinx-build' executable. Alternatively you + echo.may add the Sphinx directory to PATH. + echo. + echo.If you don't have Sphinx installed, grab it from + echo.http://sphinx-doc.org/ + exit /b 1 +) + +%SPHINXBUILD% -M %1 %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O% +goto end + +:help +%SPHINXBUILD% -M help %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O% + +:end +popd diff --git a/CI/doc/requirements_doc.txt b/CI/doc/requirements_doc.txt new file mode 100644 index 0000000..411fbf9 --- /dev/null +++ b/CI/doc/requirements_doc.txt @@ -0,0 +1,10 @@ +sphinx>=2.0 +myst-parser +furo +sphinx-favicon +sphinxcontrib-mermaid +sphinx-simplepdf +pillow +numpy +jinja2 +sphinx_design \ No newline at end of file diff --git a/CI/doc/source/_static/assets/ADI_Logo_AWP_Large.png b/CI/doc/source/_static/assets/ADI_Logo_AWP_Large.png new file mode 100644 index 0000000..7a11a0c Binary files /dev/null and b/CI/doc/source/_static/assets/ADI_Logo_AWP_Large.png differ diff --git a/CI/doc/source/_static/assets/HWA.png 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+#CustomIPIntegrationText { + fill: var(--rd-title-color); +} + +#CarrierBox > rect { + fill: var(--md-default-fg-color--light); +} +#TxDMAEngineBox > rect { + stroke: white; +} + +#TxDMAEngineBox:hover > rect { + fill: rgb(0, 174, 255); +} +#TxUPACKBox > rect { + stroke: white; +} + +#TxUPACKBox:hover > rect { + fill: rgb(0, 174, 255); +} +#RxDMAEngineBox > rect { + stroke: white; +} + +#RxDMAEngineBox:hover > rect { + fill: rgb(0, 174, 255); +} +#CPACKBox > rect { + stroke: white; +} + +#CPACKBox:hover > rect { + fill: rgb(0, 174, 255); +} +#AXIADRV9002Box > rect { + stroke: white; +} + +#AXIADRV9002Box:hover > rect { + fill: rgb(0, 174, 255); +} + +#FPGACarrierText { + fill: var(--rd-title-color); +} + +#CarrierBox > rect { + fill: none; + stroke: black +} + +#CustomIPOutline > rect { + stroke: var(--rd-title-color); +} + +#CustomIPIntegrationText { + fill: var(--rd-title-color); +} + +#CarrierBox > rect { + fill: var(--md-default-fg-color--light); +} +#TxDMAEngineBox > rect { + stroke: white; +} + +#TxDMAEngineBox:hover > rect { + fill: rgb(0, 174, 255); +} +#TxUPACKBox > rect { + stroke: white; +} + +#TxUPACKBox:hover > rect { + fill: rgb(0, 174, 255); +} +#RxDMAEngineBox > rect { + stroke: white; +} + +#RxDMAEngineBox:hover > rect { + fill: rgb(0, 174, 255); +} +#CPACKBox > rect { + stroke: white; +} + +#CPACKBox:hover > rect { + fill: rgb(0, 174, 255); +} +#RxJESDTPL > rect { + stroke: white; +} + +#RxJESDTPL:hover > rect { + fill: rgb(0, 174, 255); +} +#RxJESDLink > rect { + stroke: white; +} + +#RxJESDLink:hover > rect { + fill: rgb(0, 174, 255); +} +#RxJESDPHY > rect { + stroke: white; +} + +#RxJESDPHY:hover > rect { + fill: rgb(0, 174, 255); +} +#TxJESDTPL > rect { + stroke: white; +} + +#TxJESDTPL:hover > rect { + fill: rgb(0, 174, 255); +} +#TxJESDLink > rect { + stroke: white; +} + +#TxJESDLink:hover > rect { + fill: rgb(0, 174, 255); +} +#TxJESDPHY > rect { + stroke: white; +} + +#TxJESDPHY:hover > rect { + fill: rgb(0, 174, 255); +} + +#FPGACarrierText { + fill: var(--rd-title-color); +} + +#CarrierBox > rect { + fill: none; + stroke: black +} + +#CustomIPOutline > rect { + stroke: var(--rd-title-color); +} + +#CustomIPIntegrationText { + fill: var(--rd-title-color); +} diff --git a/CI/doc/source/_static/css/style.css b/CI/doc/source/_static/css/style.css new file mode 100644 index 0000000..6116014 --- /dev/null +++ b/CI/doc/source/_static/css/style.css @@ -0,0 +1,95 @@ +:root { + /* Defaults */ + --display-dark-stuff: none; + --display-light-stuff: block; + --sidebar-highligh-color-hover: black; + --sidebar-highligh-color: white; + --display-dark-stuff: none; + --display-light-stuff: block; +} + +@media (prefers-color-scheme: dark) { + :root { + /* Change to dark if user prefers dark */ + --display-dark-stuff: block; + --display-light-stuff: none; + --sidebar-highligh-color-hover: white; + --sidebar-highligh-color: black; + --display-dark-stuff: block; + --display-light-stuff: none; + } +} + + +[data-theme=light] { + --sidebar-highligh-color-hover: black; + --sidebar-highligh-color: white; + --display-dark-stuff: none; + --display-light-stuff: block; +} + +[data-theme=dark] { + --sidebar-highligh-color-hover: white; + --sidebar-highligh-color: black; + --display-dark-stuff: block; + --display-light-stuff: none; +} + +/* Pad sidebar entries so radius does not touch content or browser*/ +body>div>aside>div>div>div.sidebar-scroll>div>ul { + padding-right: 10px; + padding-left: 10px; +} + +/* Disable sidebar title */ +.sidebar-brand-text { + display: none; +} + +/* Add better highlighting on selected sidebar entry */ +.sidebar-tree .current>.reference { + border-radius: 25px; + color: var(--sidebar-highligh-color); + padding-bottom: 5px; + padding-top: 5px; +} + +/* Add better highlighting on selected second level sidebar entry */ +.toctree-l2 .current.reference.internal { + border-radius: 25px; + color: var(--sidebar-highligh-color); + padding-bottom: 1px; + padding-top: 1px; + margin: 2px; +} + +/* Add better highlighting on selected hovered sidebar entry */ +.sidebar-tree .current>.reference:hover { + color: var(--sidebar-highligh-color-hover); + border: 1px solid var(--sidebar-highligh-color-hover); + padding-bottom: 4px; + padding-top: 4px; +} + +/* Add better highlighting on selected second level hovered sidebar entry */ +.toctree-l2 .current.reference.internal:hover { + color: var(--sidebar-highligh-color-hover); + border: 1px solid var(--sidebar-highligh-color-hover); + padding-bottom: 1px; + padding-top: 1px; + margin: 2px; +} + + +/* Hide/display logo on index page based on theme */ +#indexlogo_light { + display: var(--display-dark-stuff); +} + +#indexlogo_dark { + display: var(--display-light-stuff); +} + +element.style { + display: none; +} diff --git a/CI/doc/source/_static/favicon.png b/CI/doc/source/_static/favicon.png new file mode 100644 index 0000000..e18d7b0 Binary files /dev/null and b/CI/doc/source/_static/favicon.png differ diff --git a/CI/doc/source/_static/logos/logo_black.png b/CI/doc/source/_static/logos/logo_black.png new file mode 100644 index 0000000..7be4e68 Binary files /dev/null and b/CI/doc/source/_static/logos/logo_black.png differ diff --git a/CI/doc/source/_static/logos/logo_black_cropped.png b/CI/doc/source/_static/logos/logo_black_cropped.png new file mode 100644 index 0000000..35e3c1f Binary files /dev/null and b/CI/doc/source/_static/logos/logo_black_cropped.png differ diff --git a/CI/doc/source/_static/logos/logo_white.png b/CI/doc/source/_static/logos/logo_white.png new file mode 100644 index 0000000..4570498 Binary files /dev/null and b/CI/doc/source/_static/logos/logo_white.png differ diff --git a/CI/doc/source/_static/logos/logo_white_cropped.png b/CI/doc/source/_static/logos/logo_white_cropped.png new file mode 100644 index 0000000..3c97227 Binary files /dev/null and b/CI/doc/source/_static/logos/logo_white_cropped.png differ diff --git a/CI/doc/source/allrefdesigns.md b/CI/doc/source/allrefdesigns.md new file mode 100644 index 0000000..89cd892 --- /dev/null +++ b/CI/doc/source/allrefdesigns.md @@ -0,0 +1,27 @@ + +# HDL Reference Designs + +Available hardware streaming interfaces in HSX Toolbox: + + +```{eval-rst} +.. toctree:: + :maxdepth: 1 + + _generated/hdlrefdesigns/adrv9361z7035 + _generated/hdlrefdesigns/adrv9364z7020 + _generated/hdlrefdesigns/pluto + _generated/hdlrefdesigns/fmcomms2 + _generated/hdlrefdesigns/fmcomms5 + _generated/hdlrefdesigns/adrv9371 + _generated/hdlrefdesigns/adrv9002 + _generated/hdlrefdesigns/adrv9009 + _generated/hdlrefdesigns/fmcomms8 + +``` + + + +Click on left table of contents for individual component pages. \ No newline at end of file diff --git a/CI/doc/source/conf.py b/CI/doc/source/conf.py new file mode 100644 index 0000000..fc451e0 --- /dev/null +++ b/CI/doc/source/conf.py @@ -0,0 +1,146 @@ +# Configuration file for the Sphinx documentation builder. +# +# This file only contains a selection of the most common options. For a full +# list see the documentation: +# http://www.sphinx-doc.org/en/master/config + +# -- Path setup -------------------------------------------------------------- + +# If extensions (or modules to document with autodoc) are in another directory, +# add these directories to sys.path here. If the directory is relative to the +# documentation root, use os.path.abspath to make it absolute, like shown here. +# +import contextlib +import os +import shutil +import sys +from typing import List + +sys.path.insert(0, os.path.abspath("../..")) +sys.setrecursionlimit(1500) + +# Move logos over to doc directory +p = os.path.join("_static", "logos") +if not os.path.exists(p): + os.mkdir("_static/logos") + +for filename in os.listdir(os.path.join("..", "..", "..", "logos")): + if filename.endswith(".png"): + shutil.copy( + os.path.join("..", "..", "..", "logos", filename), + os.path.join("_static", "logos", filename), + ) + fn = os.path.join("_static", "logos", filename) + from PIL import Image + + im = Image.open(fn) + # Remove left 30% of image + #im = im.crop((int(im.size[0] * 0.45), 0, int(im.size[0] * 1), im.size[1])) + im = im.crop((int(im.size[0] * 0.32), 0, int(im.size[0] * 1), im.size[1])) + im.save(fn.replace(".png", "_cropped.png")) + + +# -- Project information ----------------------------------------------------- + +project = "Analog Devices, Inc. Transceiver Toolbox" +copyright = "2019-2022, Analog Devices, Inc" +author = "Analog Devices, Inc." + +# The full version, including alpha/beta/rc tags +release = "v22.2.1" + + +# -- General configuration --------------------------------------------------- + +# The master toctree document. +master_doc = "index" + +# Add any Sphinx extension module names here, as strings. They can be +# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom +# ones. +extensions = [ + # "sphinx.ext.autodoc", + "sphinx.ext.coverage", + "sphinx.ext.githubpages", + "myst_parser", + "sphinx_favicon", + "sphinxcontrib.mermaid", + # "sphinx_copybutton", + # "sphinx_togglebutton", # Using this? + "sphinx_design", +] + +myst_enable_extensions = [ + "colon_fence", +] + +# Add any paths that contain templates here, relative to this directory. +templates_path = ["_templates"] + +# List of patterns, relative to source directory, that match files and +# directories to ignore when looking for source files. +# This pattern also affects html_static_path and html_extra_path. +exclude_patterns: List[str] = [] + +# Configuration of sphinx.ext.coverage +#coverage_show_missing_items = True + +# -- Options for HTML output ------------------------------------------------- + +# The theme to use for HTML and HTML Help pages. See the documentation for +# a list of builtin themes. +# +html_theme = "furo" + +html_title = f"{project} {release}" +#favicons = ["favicon.png"] + +# Add any paths that contain custom static files (such as style sheets) here, +# relative to this directory. They are copied after the builtin static files, +# so a file named "default.css" will overwrite the builtin "default.css". +html_static_path = ["_static"] + +html_css_files = [ + "css/style.css", +] + +html_theme_options = { + "light_logo": os.path.join("logos", "logo_black_cropped.png"), + "dark_logo": os.path.join("logos", "logo_white_cropped.png"), + "dark_css_variables": { + "color-sidebar-item-background--current": "white", + "color-sidebar-link-text": "white", + "color-sidebar-link-text--top-level": "white", + }, + "light_css_variables": { + "color-sidebar-item-background--current": "black", + "color-sidebar-link-text": "black", + "color-sidebar-link-text--top-level": "black", + }, +} + +if os.getenv("DEV_BUILD"): + branch = os.getenv("GIT_BRANCH") + if branch is None: + with contextlib.suppress(Exception): + # Try to get branch from git + import subprocess + + branch = ( + subprocess.run( + args=["git", "rev-parse", "--abbrev-ref", "HEAD"], + capture_output=True, + ) + .stdout.decode("utf-8") + .strip() + ) + if branch is None: + branch = "_UNKNOWN_" # type: ignore + html_theme_options["announcement"] = ( + "WARNING: This is a development \ + build of branch: " + + branch + + ". Please use the latest stable release." + ) + html_theme_options["dark_css_variables"]["color-announcement-text"] = "red" + html_theme_options["light_css_variables"]["color-announcement-text"] = "red" diff --git a/CI/doc/source/dev_hdl_workflow.md b/CI/doc/source/dev_hdl_workflow.md new file mode 100644 index 0000000..5207272 --- /dev/null +++ b/CI/doc/source/dev_hdl_workflow.md @@ -0,0 +1,95 @@ +# HDL Workflow + +:::{warning} +This content is meant for developers or advanced users and is not meant for general consumption. +::: + +This page discusses the HDL targeting support from the perspective of the HDL source repo and HDL-Coder itself. It is not necessary for users to understand these details but for those managing the toolbox or developers extending support to new platforms this information is valuable. + +This page assumes a basic understanding of MathWork's [HDL Workflow Advisor (HWA)](https://www.mathworks.com/help/hdlcoder/ug/overview-of-workflows-in-hdl-workflow-advisor.html) and its different steps for creating IP, creating a HDL project, and generating a bitstream. + +## HDL Repo Preparation + +When the toolbox is built it will clone a specific branch of the [ADI HDL repo](github.com/analogdevicesinc/hdl) and apply certain changes to support the [IP-Core Generation HDL-Coder](https://www.mathworks.com/discovery/ip-core-generation.html) workflow. However, with the current flow there are minimal changes required which makes moving between release simpler. This is currently done by simply replacing certain TCL scripts within the HDL repo. + +Creation of the toolbox, cloning of the HDL source, and applying the necessary update is driven through a Makefile in the **CI/scripts** folder. The toolbox is built in source form with the **build** as follows: + +```bash +make -C CI/scripts build +``` +After the above command completes the HDL source will be in place with necessary changes. + +The changes primarily required of the HDL source are interceptions of the build functions (procs) to skip synthesis when building a project. This is done by inserting environmental variable checks into the [adi_project_xilinx.tcl](https://github.com/analogdevicesinc/TransceiverToolbox/blob/master/CI/scripts/adi_project_xilinx.tcl#L138) script. At build time these environmental variables are set and will prevent synthesis. This way an HDL project can be built, then handed off to HDL-Coder for IP insertion and eventual synthesis. + +HDL-Coder is limited to only interact with Vivado or Quartus. Therefore, it cannot leverage the makefiles as traditionally used to build HDL projects in the HDL repo. HDL-Coder and the authored scripts in the toolbox use the [TCL flow](https://wiki.analog.com/resources/fpga/docs/build#xilinx_auto_tcl_build) normally recommended for just Windows users. This is used on all platforms (Windows and Linux) to support HDL code-generation and integration with ADI toolboxes. + +## HDL-Coder IP Core Generation Flow + +The orchestration of Vivado and calling of specific TCL scripts is managed through MathWork's [HWA](https://www.mathworks.com/help/hdlcoder/ug/overview-of-workflows-in-hdl-workflow-advisor.html). HWA generates HDL (Verilog is currently the only supported language) for specific Simulink blocks, calls a number of TCL scripts maintained by ADI to build a project and make room for IP, then inserts that IP and calls synthesis. This will be discussed from HWA and the generated scripts it creates. This is detailed from the scripting perspective first in the figure below: + +```{mermaid} +graph LR +A[1. Generate Verilog
From Simulink IP]-->B[2. Optional: Pre-Build
Project Script]; +subgraph SS[vivado_create_prj.tcl] +subgraph vivado_custom_block_design.tcl +B --> C[3. Build Standard
Project
system_project.tcl]; +C --> D[4. Prune Preprocessor
Script
matlab_processors.tcl]; +D --> E[5. Optional: Post-Build
Project Script
]; +end +end +E --> F[6. Insert and Connect
Generate IP
vivado_insert_ip.tcl]; + +style B fill:#f9f,stroke:#333,stroke-width:4px +style E fill:#f9f,stroke:#333,stroke-width:4px +style C fill:#FF0,stroke:#333,stroke-width:4px,stroke-dasharray: 5 5 +style D fill:#FF0,stroke:#333,stroke-width:4px,stroke-dasharray: 5 5 +``` +
Figure 1: Details IP-Core Generation flow with Toolbox
+ +At a high-level there are six main steps, two of which are optional. From the far left stage "Generate Verilog From Simulink IP" occurs in Stage 3 "HDL Code Generation" within HWA as outlined in red below. This will create Verilog within the defined project folder and then be copied into the full HDL project later on. + +```{figure} /_static/assets/HWA_verilog_gen.png + +HDL Workflow Advisor IP verilog generation. +``` + +Within the largest central block of the flowchart labeled **vivado_create_prj.tcl** are all the core steps related the HWA Step 4.1, where the reference HDL project folder is built and necessary cores and nets removed to make room for IP from Simulink generated in HWA Step 3. This stage is highlighed in the figure below. The purple boxes are optional stages that are used in certain customized examples when additional work is required to prepare a reference design. The [Frequency Hopping example](https://github.com/analogdevicesinc/TransceiverToolbox/tree/master/trx_examples/targeting/frequency-hopping) leverages these stages. Once the project is prepared the IP is inserted and bitstream generated, which occurs through HWA Step 4.3. + + +```{figure} /_static/assets/HWA_project_gen.png + +HDL Workflow Advisor project generation step. +``` + + +### Vivado Project Perspective + +Based on the flow in Figure 1, there are a three main states the HDL reference design enters from a high level. These states will be discussed more from the Vivado project perspective, specifically the data path of an FMComms2 project. Other HDL projects will be similar. + +The first state is just the initial creation of the standard unmodified block design. Looking at Figure 4, the three IPs show the dataflow from the interface core (axi_ad9361), through the ADC FIFO, and finally into the pack core. In orange are the data buses and valid signal highlighted. These are important since the generated IP needs to be inserted where these nets are connected. Therefore, in the second state of the design these nets are removed to make room from the new IP. + + +```{figure} /_static/assets/stock_reference_design.png + +RX path in unmodified standard reference design. +``` + + + +Once the IP is inserted into the project by HDL-Coder it is connected to the FIFO and pack cores where the nets in Figure 4 were highlighted. The new inserted and connected IP can be see in Figure 5. + +```{figure} /_static/assets/reference_design_with_IP.png + +RX path with inserted IP from HDL-Coder. +``` + +The connecting of the IPs and insertion are entirely managed by HDL-Coder and through the [add_io_ports](https://github.com/analogdevicesinc/TransceiverToolbox/blob/master/hdl/vendor/AnalogDevices/+AnalogDevices/add_io_ports.m) function and supporting [JSON port definition file](https://github.com/analogdevicesinc/TransceiverToolbox/blob/master/hdl/vendor/AnalogDevices/+AnalogDevices/ports.json). + +### Generated TCL Scripts + + +The following scripts outlined in the figure above have certain purposes: + +- **vivado_create_prj.tcl**: This is the first TCL scripted called in Stage 4 of HWA and is responsible for setting up a standard reference design and trimming nets and IPs to make room for IP from Simulink +- **vivado_custom_block_design.tcl**: This is a carbon copy of the **system_project_rxtx.tcl** script and is called by **vivado_create_prj.tcl**. This script will call [adi_make.tcl](https://wiki.analog.com/resources/fpga/docs/build#xilinx_auto_tcl_build), the correct system_project.tcl file, and finally matlab_processor.tcl. It will optionally call the pre/post processor TCL scripts. +- **vivado_insert_ip.tcl**: This script is fully generated by MATLAB based on the [add_io](https://github.com/analogdevicesinc/TransceiverToolbox/blob/master/hdl/vendor/AnalogDevices/+AnalogDevices/add_io.m) definitions in MATLAB to insert the custom IP into the prepared reference design. \ No newline at end of file diff --git a/CI/doc/source/examples.md b/CI/doc/source/examples.md new file mode 100644 index 0000000..83038fa --- /dev/null +++ b/CI/doc/source/examples.md @@ -0,0 +1,22 @@ + +# Examples + +Examples for streaming data and targeting FPGAs are listed within the Toolbox documentation itself. To view run the following with MATLAB: + +``` +doc adi +``` + +They can also be viewed on GitHub: + + - [Targeting examples](https://github.com/analogdevicesinc/TransceiverToolbox/tree/master/trx_examples/targeting) + - [Streaming examples](https://github.com/analogdevicesinc/TransceiverToolbox/tree/master/trx_examples/streaming) + +## Highlighted Demos + +Certain examples have full articles that discuss different applications + +- [Frequency hopping](https://wiki.analog.com/resources/eval/user-guides/adrv936x_rfsom/tutorials/frequency_hopping) +- [Loopback delay estimation](https://wiki.analog.com/resources/eval/user-guides/adrv936x_rfsom/tutorials/loopback_delay_estimation) +- [AGC Optimization](https://wiki.analog.com/resources/eval/user-guides/ad9361_agc_tuning) +- [Pluto LTE App](https://wiki.analog.com/resources/tools-software/transceiver-toolbox/examples/pluto_lte_app) \ No newline at end of file diff --git a/CI/doc/source/index.md b/CI/doc/source/index.md new file mode 100644 index 0000000..4c43bec --- /dev/null +++ b/CI/doc/source/index.md @@ -0,0 +1,69 @@ + + + +
+
+
+
+PyADI-IIO Logo +
+
+PyADI-IIO Logo +
+
+
+ + + + +ADI maintains a set of tools to model, interface, and target with ADI transceiver devices within MATLAB and Simulink. These are combined into single Toolbox which contains a set of Board Support Packages (BSP). The list of supported boards is provided below. + +The following have device-specific implementations in MATLAB and Simulink. If a device has an IIO driver, MATLAB support is possible, but a device-specific MATLAB or Simulink interface may not exist yet. + + +| Evaluation Card | FPGA Board | Streaming Support | Targeting | Variants and Minimum Supported Release | +| --------- | --------- | --------- | --------- | --------- | +| Pluto | | Yes | Yes | ADI (2018b) MathWorks (2017a) | +| FMComms2/3/4 | Zedboard | Yes | Yes | ADI (2018b) MathWorks (2014b) | +| | ZC702 | Yes | Yes | ADI (2018b) MathWorks (2014b) | +| | ZC706 | Yes | Yes | ADI (2018b) MathWorks (2014b) | +| | ZCU102 | Yes | Yes | ADI (2018b) MathWorks (2014b) | +| ARRADIO | Arrow SoCKit | Yes | No | ADI (2018b) | +| ADRV9361-Z7035 | | Yes | Yes | ADI (2018b) MathWorks (2015b) | +| ADRV9364-Z7020 | | Yes | Yes | ADI (2018b) | +| ADRV9371/5 | ZC706 | Yes | Yes | ADI (2018b) | +| | ZCU102 | Yes | Yes | ADI (2018b) | +| | ZYNQ3 | Yes | No | ADI (2018b) | +| ADRV9002 | ZCU102 | Yes | Yes | ADI (2020a) | +| ADRV9009/8 | ZC706 | Yes | No | ADI (2018b) | +| | ZCU102 | Yes | Yes | ADI (2018b) | +| ADRV9009-ZU11EG | | Yes | No | ADI (2020a) | + + + +## Sections + +```{eval-rst} +.. toctree:: + :maxdepth: 1 + + install.md + streaming.md + targeting.md + examples.md + objects.md + allrefdesigns.md + +``` + +```{toctree} +:caption: Development + +dev_hdl_workflow.md +``` + diff --git a/CI/doc/source/install.md b/CI/doc/source/install.md new file mode 100644 index 0000000..024e8f2 --- /dev/null +++ b/CI/doc/source/install.md @@ -0,0 +1,67 @@ + +# Installation + +## Dependencies + +The toolbox has different dependencies based on the features required. These are broken down into the base dependencies for data stream and control, and HDL code generation. + +The base dependencies for the toolbox requires libiio and the libiio MATLAB bindings. There are three options for this install with different required MathWorks Toolboxes: + +- [Communications Toolbox Support Package for Xilinx Zynq-Based Radio](https://www.mathworks.com/help/supportpkg/xilinxzynqbasedradio/index.html) + - Communications Toolbox + - Signal Processing Toolbox™ + - DSP System Toolbox™ +- [Communications Toolbox Support Package for Analog Devices ADALM-Pluto Radio](https://www.mathworks.com/help/supportpkg/plutoradio/index.html) + - Communications Toolbox + - Signal Processing Toolbox™ + - DSP System Toolbox™ +- [libiio MATLAB Binding Standalone Installer (R2021b+)](https://github.com/mathworks/buildroot/releases/download/mathworks_zynq_R21.2.0/libiio.mlpkginstall) + - Signal Processing Toolbox™ + + +### HDL Generation Support + +To leverage HDL-Coder and the reference designs with the toolbox requires the following components: + +- Xilinx Vivado 2021.2 +- Xilinx Vitis 2021.2 +- Simulink +- [HDL-Coder™](https://www.mathworks.com/products/hdl-coder.html) +- [HDL Coder™ Support Package for Xilinx Zynq Platform](https://www.mathworks.com/matlabcentral/fileexchange/40447-hdl-coder-support-package-for-xilinx-zynq-platform) + +## Transceiver Toolbox Install + +The Transceiver Toolbox itself can be installed either from: + +- [MATLAB's Add-On Explorer](https://www.mathworks.com/products/matlab/add-on-explorer.html) +- [GitHub Releases page](https://github.com/analogdevicesinc/TransceiverToolbox/releases). + +:::{admonition} MATLAB Versions +:class: warning + +Before installing Transceiver Toolbox check the [Release Page](https://github.com/analogdevicesinc/TransceiverToolbox/releases) to check for the lasted supported of MATLAB. The latest version is the one which is available in [Add-on Explorer](https://www.mathworks.com/products/matlab/add-on-explorer.html), since Add-On Explorer does not currently support hosting multiple versions. If ypu have an older release of MATLAB, download the MLTBX installer from matching release on the [Release Page](https://github.com/analogdevicesinc/TransceiverToolbox/releases). + +::: + + +### Add-On Explorer Walkthrough + +To install the toolbox from within MATLAB using the Add-On Explorer, first launch the Explorer from MATLAB's Home tab: + + + +Search for the toolbox: + + + + +Select Transceiver Toolbox from results: + + + + + +Select add: + + + \ No newline at end of file diff --git a/CI/doc/source/objects.md b/CI/doc/source/objects.md new file mode 100644 index 0000000..cb5e30f --- /dev/null +++ b/CI/doc/source/objects.md @@ -0,0 +1,29 @@ + +# Hardware Interface APIs + +Available hardware streaming interfaces in HSX Toolbox: + + +```{eval-rst} +.. toctree:: + :maxdepth: 1 + + _generated/sysobjects/Attribute + _generated/sysobjects/DDS + _generated/sysobjects/Tx + _generated/sysobjects/BufferADI + _generated/sysobjects/Channel + _generated/sysobjects/DebugAttribute + _generated/sysobjects/DeviceAttribute + _generated/sysobjects/RegisterReadWrite + _generated/sysobjects/Rx + _generated/sysobjects/RxTx + _generated/sysobjects/Sensor + +``` + + + +Click on left table of contents for individual component pages. \ No newline at end of file diff --git a/CI/doc/source/streaming.md b/CI/doc/source/streaming.md new file mode 100644 index 0000000..4cdc02c --- /dev/null +++ b/CI/doc/source/streaming.md @@ -0,0 +1,140 @@ + +# Receiving and Sending Data + +Remote data streaming to and from hardware is made available through [system object interfaces](https://www.mathworks.com/help/matlab/matlab_prog/what-are-system-objects.html), which are unique for each component or platform. The hardware interfacing system objects provide a since class to both configure a given platform and move data back and forth from the device. + +Command and control of hardware from MATLAB is accomplished by leveraging the [IIO drivers](https://wiki.analog.com/software/linux/docs/iio/iio) built into the target platform's kernel and [libiio](https://wiki.analog.com/resources/tools-software/linux-software/libiio) which provides remote backends to control drivers across different backends. Backends can be Ethernet, serial, or USB based. Below is a diagram of the different components in the stack for an FMComms based systems, but will be nearly identical for all transceiver based systems. + +![MATLAB libiio Stack](/_static/assets/MATLAB_libiio_Stack.png) + +Since libiio is cross-platform it can be used from Windows, Linux, or macOS based systems. It is also a lower level library independent of MATLAB, so when moving toward production or untethered systems similar APIs that are used in MATLAB can be used in C,C++,Python, or other languages. + +## Connecting and Configuration + +Connecting to hardware is done by setting the **uri** property of the system object interface. The **uri** for libiio always has the convention "*< backend >:< address >*", where *backend* can be ip,usb, or serial. *address* will be specific to the backend. This is documented in the [libiio API](https://analogdevicesinc.github.io/libiio/master/libiio/group__Context.html#gafdcee40508700fa395370b6c636e16fe). + +Below is a basic example of setting up an AD9361 receiver using an Ethernet/IP backend where the address of the target system is 192.168.2.1: +```linenums="1" +rx = adi.AD9361.Rx; +rx.uri = 'ip:192.168.2.1'; +data = rx(); +``` +With the code above, the hardware is not contacted until the operator or step method is called on line 3. Therefore, any properties that are set or defined before line 3 are not applied or updated on the hardware until after line 3. However, after line 3 has completed the object will become locked and certain configuration changes cannot be applied after this point. These will primarily sample rates and buffer sizes. + +The state of the object follows the flow of the diagram below triggered by line line 3 above. + +```{mermaid} +graph LR + Z[Operator Called] -->A; + A[Connect To Board] --> B[Update Properties]; + B --> C[Initialize Buffers]; + C --> D[Send or Receive Data]; + D --> E[Lock Object]; +``` +Once the object becomes locked it must be released if the sample rate or buffers need to be modified. This will disconnect from the hardware: +``` +rx.release(); % Release object +``` + +To provide a complete example we can do more advanced configuration like so to demonstrate property changes: +```linenums="1" +rx = adi.AD9361.Rx; +rx.uri = 'ip:192.168.2.1'; +rx.SamplesPerFrame = 1024; +rx.CenterFrequency = 1e9; +dataLO1 = rx(); + +% Update tunable property +rx.CenterFrequency = 2e9; +dataLO2 = rx(); + +% Update non-tunable property +rx.release(); +rx.SamplesPerFrame = 4096; +dataLargerBuffer = rx(); +``` + +## Receiving Data + +To receive or capture data from a given device first you must instantiate that device's interface class. For example on a AD9361 based system, this would be as follows: + +``` +rx = adi.AD9361.Rx; +``` + +Once instantiated you can configure the number of samples to be captured by setting the property **SamplesPerFrame.** + +``` +rx.SamplesPerFrame = 1e6; +``` + +**SamplesPerFrame** is the number of samples per channel which will be captured. If your device produces complex data (I and Q) this is the number of complex samples. There will be a limit to the maximum samples which can be collected. By default this is set to 2^20, but it may be possible to make it larger depending on hardware. Once the operator methods are used for a give instantiation, the object will become locked and the **SamplesPerFrame** property cannot be changed. This is known as a non-tunable property. + +To actually collect the samples or perform the capture, the operator of the system object should be used or the **step** method as so: + +``` +data = rx(); % Operator method +data = rx.step(); % Step method +``` + +Both method calls are equivalent, and the produced matrix **data** will be of size [SamplesPerFrame x length(EnabledChannels)]. **EnabledChannels** determines the channels which data will be collected from. **EnabledChannels** is a [1xN] vector with indexes starting at 1 of the desired channels. If the device transmits or receive complex data, these indexes are for complex channel pairs. For example, the AD9361 has 2 receivers (4 ADC) and setting **EnabledChannels** as so will capture data from all 4 converters: + +``` +rx.EnabledChannels = [1,2]; +``` + +You cannot enable individual converters on complex data based devices, and the **EnabledChannels** property is always sorted so the channel mappings cannot be changed within the produced data. + +## Sending Data + +Transmitting data is very similar to receiving it, a transmitter class needs to be instantiated to send data first. For a ADRV9009 based device this would be as follows: + +``` +tx = adi.ADRV9009.Tx; +``` + +Unlike the receivers, transmit objects automatically create their internal buffers based on the data passed to them during their operator or step methods. These methods can be called as follows with some data: + +``` +tx_data = complex(2^15.*randn(1024,1),2^15.*randn(1024,1)); +tx(tx_data); % Operator method +tx.step(tx_data); % Step method +``` + +However, once the step or operator method is called the object becomes locked and future passed data vectors must be the same length. As with the receive classes, the size of the passed data must be [SomeFixedSize x EnabledChannels]. **EnabledChannels** has the same definition as the receive side, except applied to DACs. + +Unlike the receiver, transmit objects have the ability to utilize [cyclic buffers](https://analogdevicesinc.github.io/libiio/group__Buffer.html#ga6caadf077c112ae55a64276aa24ef832) which will continuously transmit a provided vector without gaps forever. To utilize cyclic buffers set the **EnableCyclicBuffers** property then pass the operator data as follows: + +``` +tx = adi.ADRV9009.Tx; +tx.EnableCyclicBuffers = true; +tx_data = complex(2^15.*randn(1024,1),2^15.*randn(1024,1)); +tx(tx_data); % Data will repeat forever +``` + +One a vector is passed to the object with **EnableCyclicBuffers** set to **true**, the object will not accept future buffers unless first release or cleared. + +By default the system objects will utilize **DMA** as the source of data for the DACs, which will use data past from the operator. This can be set manually through the **DataSource** properties as follows: + +``` +rx.DataSource = 'DMA'; +``` + +## DDS + +Instead of providing data for transmission, it is possible to utilize DDSs inside the FPGA to send tones to individual DACs. For specific boards there are two DDS per DAC, which can be used to create complex (one-sided) tones. These DDSs can be used by first setting the **DataSource** property: + +``` +rx.DataSource = 'DDS'; +``` + +Then the scale, frequency, and phase of each DDS can be controlled through three attributes as follows: + +``` +rx.DDSFrequencies = [1e3,1e3,1e3,1e3;1e4,1e4,1e4,1e4]; % Must be range [0 FS/2] +rx.DDSScales = [1,1,1,1;0,0,0,0]; % Must be range [0,1] +rx.DDSPhases = [0,90e3,0,90e3,0,0;0,0,0,0]; % Each in millidegrees [0,90000] +``` + +Each of the above properties must be of size [2x(NumberOfPartDACs)], where each row is the first DDS of a given DAC (column) and the second row is the second DDS of a given DAC (column). + diff --git a/CI/doc/source/targeting.md b/CI/doc/source/targeting.md new file mode 100644 index 0000000..860afa6 --- /dev/null +++ b/CI/doc/source/targeting.md @@ -0,0 +1,12 @@ + +# HDL Targeting with HDL-Coder + +Transceiver Toolbox supports the IP Core generation flow from MathWorks which allows for automated integration of DSP into HDL reference designs from Analog Devices. This workflow will take Simulink subsystems, run HDL-Coder to generate source Verilog, and then integrate that into a larger reference design. The figure below is a simplified block diagram of a SoC (Fabric+ARM) device, where specialized IP are inserted into the receive and transmit datapaths. This is supported on specific FPGA families and transceiver based reference designs. This support is based on the Zynq HDL-Coder and support + + + +## Recommended Review + +- [Getting started with Zynq](https://www.mathworks.com/support/search.html/videos/getting-started-with-zynq-80338.html?fq%5B%5D=asset_type_name:video&fq%5B%5D=category:hdlcoder/index&page=1) + +## Getting Started diff --git a/CI/scripts/Docker b/CI/scripts/Docker new file mode 100644 index 0000000..a919c79 --- /dev/null +++ b/CI/scripts/Docker @@ -0,0 +1,10 @@ +FROM ubuntu:16.04 + +MAINTAINER Travis Collins +RUN DEBIAN_FRONTEND=noninteractive apt update +RUN DEBIAN_FRONTEND=noninteractive apt-get install -y libpng-dev libfreetype6-dev libblas-dev liblapack-dev gfortran build-essential xorg +RUN DEBIAN_FRONTEND=noninteractive apt-get install -y openjdk-8-jre openjdk-8-jdk libgtk2.0-0 libxss1 libxt6 zip unzip curl wget tar git xvfb +RUN DEBIAN_FRONTEND=noninteractive apt-get install -y fakeroot libncurses5-dev libssl-dev ccache dfu-util u-boot-tools device-tree-compiler +RUN DEBIAN_FRONTEND=noninteractive apt-get install -y libssl-dev mtools bc python cpio zip unzip rsync file wget +RUN DEBIAN_FRONTEND=noninteractive dpkg --add-architecture i386 +RUN DEBIAN_FRONTEND=noninteractive apt-get install -y lib32stdc++6 diff --git a/CI/scripts/Makefile b/CI/scripts/Makefile new file mode 100644 index 0000000..3c5101e --- /dev/null +++ b/CI/scripts/Makefile @@ -0,0 +1,128 @@ +# Usage: +# make MLRELEASE= HDLBRANCH= +# Example +# make build MLRELEASE=R2018b HDLBRANCH=hdl_2018_r1 + +SHELL := /bin/bash + +MLFLAGS := -nodisplay -nodesktop -nosplash + +ifeq ($(MLRELEASE),) +MLRELEASE := R2022b +endif + +ifeq ($(HDLBRANCH),) +HDLBRANCH := hdl_2021_r2 +endif + +ifeq ($(OS),Windows_NT) +MLPATH := /cygdrive/c/Program\ Files/MATLAB +MLFLAGS := $(MLFLAGS) -wait +else +UNAME_S := $(shell uname -s) +ifeq ($(UNAME_S),Linux) +MLPATH := /usr/local/MATLAB +endif +ifeq ($(UNAME_S),Darwin) +MLPATH := /Applications +MLRELEASE := MATLAB_${MLRELEASE}.app +endif +endif + +ifeq ($(BOARD),) +BOARD := +endif + +ifeq ($(INCLUDE_EXAMPLES),) +INCLUDE_EXAMPLES := 1 +endif + +GITTAG := $(shell git describe --tags HEAD) + +.ONESHELL: +build: + # Uses the HDLBRANCH variable + bash build_bsp.sh + +add_libad9361: + cd ../.. ; \ + mkdir deps ; \ + cd deps ; \ + mkdir linux ; \ + cd linux ; \ + wget http://swdownloads.analog.com/cse/travis_builds/master_latest_libad9361-iio-trusty.tar.gz ; \ + tar xvf *.tar.gz ; \ + mv usr/local/lib/* . ; \ + mv usr/local/include ../ ; \ + rm -rf usr ; \ + rm *.tar.gz ; \ + cd .. ; \ + mkdir osx ; \ + cd osx ; \ + wget http://swdownloads.analog.com/cse/travis_builds/master_latest_libad9361-iio-osx_10.12.tar.gz ; \ + tar xvf *.tar.gz ; \ + cd ad9361* ; \ + mv usr/local/lib/ad9361.framework/Versions/Current/ad9361 ../libad9361.dylib ; \ + cd .. ; \ + rm -rf ad9361-*-Darwin ; \ + rm *.tar.gz ; \ + cd .. ; \ + mkdir win ; \ + cd win ; \ + wget "https://github.com/analogdevicesinc/libad9361-iio/releases/download/v0.2/libad9361-0.2-win64.zip" -O lib.zip ; \ + unzip lib.zip ; \ + mv libad9361-win64/* . ; \ + rm -rf libad9361-win64 ; \ + rm *.h ; \ + rm lib.zip + +test_installer: + cd ../.. ; \ + cp *.mltbx test/ ; \ + cp hdl/vendor/AnalogDevices/hdlcoder_board_customization.m test/hdlcoder_board_customization_local.m ; \ + sed -i "s/hdlcoder_board_customization/hdlcoder_board_customization_local/g" test/hdlcoder_board_customization_local.m ; \ + ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "cd('test');runInstallerTests('$(BOARD)');" + +test: + cd ../.. ; \ + ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "cd('test');runTests('$(BOARD)');" + +test_streaming: + cd ../.. ; \ + ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "addpath(genpath('test'));addpath(genpath('deps'));runHWTests;" + +run_NonHWTests: + cd ../.. ; \ + ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "addpath(genpath('test'));runNonHWTest;" + +test_evm: + cd ../.. ; \ + ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "addpath(genpath('test'));addpath(genpath('deps'));hwTestRunner;" + +test_modem: + cd ../.. ; \ + ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "addpath(genpath('hdl'));cd('targeting');addpath(genpath('modem-qpsk'))" + +test_synth: + bash synth_designs.sh $(BOARD) + +test_targeting_demos: + bash targeting_designs.sh + +lte_pa_app: + cd ../../trx_examples/streaming/LTE_PA_App/ ; \ + ${MLPATH}/$(MLRELEASE)/bin/matlab -batch "genLTEPAInstaller" + +gen_tlbx: + ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "genTlbx($(INCLUDE_EXAMPLES));exit();" + +linter: + ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "linter;exit();" + +doc: + ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "cd('../doc');genhtml();exit();" + +zip: + cd ../.. ; \ + mkdir zip ; \ + zip -r zip/AnalogDevicesBSP_$(GITTAG).zip deps doc hdl hil_models targeting info.xml LICENSE README.md test/*.log diff --git a/CI/scripts/adi_build.tcl b/CI/scripts/adi_build.tcl new file mode 100644 index 0000000..b8d903a --- /dev/null +++ b/CI/scripts/adi_build.tcl @@ -0,0 +1,64 @@ +# Define local variables +set cdir [pwd] +set sdk_loc vivado_prj.sdk +set project_system_dir vivado_prj.srcs/sources_1/bd/system +set prj_carrier $project$carrier + +if {$project == "adrv9361z7035"} { + set fpga_board "adrv9361" +} elseif {$project == "adrv9364z7020"} { + set fpga_board "adrv9364" +} +set fpga_board_lc [string tolower $fpga_board] + +puts "FPGA Board: $fpga_board_lc" + +# Verify support files exist +if {![file exists $cdir/projects/common/boot/$fpga_board_lc/u-boot.elf]} { + puts "ERROR: Missing u-boot.elf for $fpga_board_lc" + return +} + +# Build the project +update_compile_order -fileset sources_1 +reset_run impl_1 +reset_run synth_1 +set_property synth_checkpoint_mode Hierarchical [get_files $project_system_dir/system.bd] +export_ip_user_files -of_objects [get_files $project_system_dir/system.bd] -no_script -sync -force -quiet +launch_runs synth_1 +wait_on_run synth_1 +launch_runs impl_1 -to_step write_bitstream +wait_on_run impl_1 + +# Export the hdf +file delete -force $sdk_loc +file mkdir $sdk_loc +write_hw_platform -fixed -force -include_bit -file $sdk_loc/system_top.xsa + +# Close the Vivado project +close_project + +# Create the BOOT.bin +puts "Generating BOOT.BIN" +puts "Please wait, this may take a few minutes." +file mkdir $cdir/boot +file copy -force $cdir/vivado_prj.runs/impl_1/system_top.bit $cdir/boot/system_top.bit +file copy -force $cdir/projects/common/boot/$fpga_board_lc/u-boot.elf $cdir/boot/u-boot.elf +file copy -force $cdir/projects/common/boot/$fpga_board_lc/zynq.bif $cdir/boot/zynq.bif +file copy -force $cdir/projects/common/boot/$fpga_board_lc/fsbl.elf $cdir/boot/fsbl.elf + +if {$fpga_board_lc == "zcu102"} { + file copy -force $cdir/projects/common/boot/$fpga_board_lc/bl31.elf $cdir/boot/bl31.elf + file copy -force $cdir/projects/common/boot/$fpga_board_lc/pmufw.elf $cdir/boot/pmufw.elf + cd $cdir/boot + exec bootgen -arch zynqmp -image zynq.bif -o BOOT.BIN -w +} else { + cd $cdir/boot + exec bootgen -arch zynq -image zynq.bif -o BOOT.BIN -w +} + +puts "------------------------------------" +puts "Embedded system build completed." +puts "You may close this shell." +puts "------------------------------------" +exit diff --git a/CI/scripts/adi_build_win.tcl b/CI/scripts/adi_build_win.tcl new file mode 100644 index 0000000..dcb82c6 --- /dev/null +++ b/CI/scripts/adi_build_win.tcl @@ -0,0 +1,58 @@ +global fpga_board + +if {[info exists fpga_board]} { + puts "===========" + puts $fpga_board + puts "===========" +} else { + # Set to something not ZCU102 + set fpga_board "ZYNQ" +} + +# Build the project +update_compile_order -fileset sources_1 +reset_run impl_1 +reset_run synth_1 +launch_runs synth_1 +wait_on_run synth_1 +launch_runs impl_1 -to_step write_bitstream +wait_on_run impl_1 + +# Define local variables +set cdir [pwd] +set sdk_loc vivado_prj.sdk + +# Export the hdf +file delete -force $sdk_loc +file mkdir $sdk_loc +write_hw_platform -fixed -force -include_bit -file $sdk_loc/system_top.xsa + +# Close the Vivado project +close_project + +# Create the BOOT.bin +if {$fpga_board eq "ZCU102"} { + set vversion [version -short] + exec xsct $cdir/projects/scripts/fsbl_build_zynqmp.tcl $vversion + if {[file exist boot/BOOT.BIN] eq 0} { + puts "ERROR: BOOT.BIN not built" + return -code error 11 + } else { + puts "BOOT.BIN built correctly!" + } + +} else { + exec xsct -batch $cdir/projects/scripts/fsbl_build_zynq.tcl + if {[file exist boot/BOOT.BIN] eq 0} { + puts "ERROR: BOOT.BIN not built" + return -code error 11 + } else { + puts "BOOT.BIN built correctly!" + } +} + +puts "------------------------------------" +puts "Embedded system build completed." +puts "You may close this shell." +puts "------------------------------------" +exit diff --git a/CI/scripts/adi_ip.tcl b/CI/scripts/adi_ip.tcl new file mode 100644 index 0000000..d878f6d --- /dev/null +++ b/CI/scripts/adi_ip.tcl @@ -0,0 +1,387 @@ +## ############################################################################################### +## ############################################################################################### +## check tool version + +if {![info exists REQUIRED_VIVADO_VERSION]} { + set REQUIRED_VIVADO_VERSION "2018.2" +} + +if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { + set IGNORE_VERSION_CHECK 1 +} elseif {![info exists IGNORE_VERSION_CHECK]} { + set IGNORE_VERSION_CHECK 0 +} + +## ############################################################################################### +## ############################################################################################### +## ip related stuff + +proc adi_ip_ttcl {ip_name ip_constr_files} { + + set cdir [pwd] + set m_file "" + set ip_constr_files_clean "" + foreach m_file $ip_constr_files { + file copy -force $m_file $cdir + set m_file [file tail $m_file] + lappend ip_constr_files_clean $m_file + } + set ip_constr_files $ip_constr_files_clean + + set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] + set f [ipx::add_file $ip_constr_files $proj_filegroup] + set_property -dict [list \ + type ttcl \ + ] $f + ipx::reorder_files -front $ip_constr_files $proj_filegroup +} + +# add ttcl file to the simulation file set +proc adi_ip_sim_ttcl {ip_name ip_files} { + + set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] + set f [ipx::add_file $ip_files $proj_filegroup] + set_property -dict [list \ + type ttcl \ + ] $f + ipx::reorder_files -front $ip_files $proj_filegroup +} + +proc adi_ip_bd {ip_name ip_bd_files} { + set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] + if {$proj_filegroup == {}} { + set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] + } + set f [ipx::add_file $ip_bd_files $proj_filegroup] + set_property -dict [list \ + type tclSource \ + ] $f +} + +proc adi_ip_infer_streaming_interfaces {ip_name} { + + ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] + +} + +proc adi_ip_infer_mm_interfaces {ip_name} { + + ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] + +} + +proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { + foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { + set_property ENABLEMENT_DEPENDENCY $dependency $port + if {$driver_value != {}} { + set_property DRIVER_VALUE $driver_value $port + } + } +} + +proc adi_set_bus_dependency {bus prefix dependency} { + set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] + adi_set_ports_dependency $prefix $dependency 0 +} + +proc adi_add_port_map {bus phys logic} { + set map [ipx::add_port_map $phys $bus] + set_property "PHYSICAL_NAME" $phys $map + set_property "LOGICAL_NAME" $logic $map +} + +proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { + set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] + + set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus + set_property "BUS_TYPE_VLNV" $bus_type $bus + set_property "INTERFACE_MODE" $mode $bus + + foreach port_map $port_maps { + adi_add_port_map $bus {*}$port_map + } +} + +proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { + for {set i 0} {$i < 8} {incr i} { + set bus_name [format "%s%d" $bus_name_prefix $i] + set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] + + set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus + set_property "BUS_TYPE_VLNV" $bus_type $bus + set_property "INTERFACE_MODE" $mode $bus + + if {$dependency ne ""} { + set bus_dependency [string map [list "{i}" $i] $dependency] + set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus + } + + foreach port_map $port_maps { + lassign $port_map phys logic width + set map [ipx::add_port_map $phys $bus] + set_property "PHYSICAL_NAME" $phys $map + set_property "LOGICAL_NAME" $logic $map + set_property "PHYSICAL_RIGHT" [expr $i*$width] $map + set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map + } + } +} + +proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { + set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] + set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] + set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] + set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf + set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf + set_property display_name $clock_inf_name $clock_inf + set clock_map [ipx::add_port_map "CLK" $clock_inf] + set_property physical_name $clock_signal_name $clock_map + + set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] + set_property value $bus_inf_name $assoc_busif + + if { $reset_signal_name != "" } { + set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] + set_property value $reset_signal_name $assoc_reset + + set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] + set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] + set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf + set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf + set_property display_name $reset_inf_name $reset_inf + set_property interface_mode $reset_signal_mode $reset_inf + set reset_map [ipx::add_port_map "RST" $reset_inf] + set_property physical_name $reset_signal_name $reset_map + + set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] + if {[string match {*[Nn]} $reset_signal_name] == 1} { + set_property value "ACTIVE_LOW" $reset_polarity + } else { + set_property value "ACTIVE_HIGH" $reset_polarity + } + } +} + +proc adi_ip_add_core_dependencies {vlnvs} { + foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { + foreach vlnv $vlnvs { + ipx::add_subcore $vlnv $file_group + } + } +} + +## ############################################################################################### +## ############################################################################################### +## ip related stuff + +variable ip_constr_files + +proc adi_ip_create {ip_name} { + + global ad_hdl_dir + global ad_phdl_dir + global ip_constr_files + global REQUIRED_VIVADO_VERSION + global IGNORE_VERSION_CHECK + + set VIVADO_VERSION [version -short] + if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { + puts -nonewline "CRITICAL WARNING: vivado version mismatch; " + puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " + puts -nonewline "got $VIVADO_VERSION.\n" + } + + create_project $ip_name . -force + + ## Load custom message severity definitions + source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl + + set ip_constr_files "" + set lib_dirs $ad_hdl_dir/library + if {$ad_hdl_dir ne $ad_phdl_dir} { + lappend lib_dirs $ad_phdl_dir/library + } + + set_property ip_repo_paths $lib_dirs [current_fileset] + update_ip_catalog +} + +proc adi_ip_files {ip_name ip_files} { + + global ip_constr_files + + set cdir [pwd] + set ip_constr_files "" + set ip_files_clean "" + foreach m_file $ip_files { + file copy -force $m_file $cdir + set m_file [file tail $m_file] + puts $m_file + if {[file extension $m_file] eq ".xdc"} { + lappend ip_constr_files $m_file + } + lappend ip_files_clean $m_file + } + + set ip_files $ip_files_clean + + set proj_fileset [get_filesets sources_1] + add_files -norecurse -scan_for_includes -fileset $proj_fileset $ip_files + add_files -norecurse -copy_to $cdir -force -fileset $proj_fileset $ip_files + set_property "top" "$ip_name" $proj_fileset +} + +proc adi_ip_properties_lite {ip_name} { + + global ip_constr_files + + ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices + set_property name $ip_name [ipx::current_core] + set_property vendor_display_name {Analog Devices} [ipx::current_core] + set_property company_url {http://www.analog.com} [ipx::current_core] + + set i_families "" + foreach i_part [get_parts] { + lappend i_families [get_property FAMILY $i_part] + } + set i_families [lsort -unique $i_families] + set s_families [get_property supported_families [ipx::current_core]] + foreach i_family $i_families { + set s_families "$s_families $i_family Production" + set s_families "$s_families $i_family Beta" + } + set_property supported_families $s_families [ipx::current_core] + ipx::save_core + + ipx::remove_all_bus_interface [ipx::current_core] + set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] + foreach map $memory_maps { + ipx::remove_memory_map [lindex $map 2] [ipx::current_core ] + } + ipx::save_core + + set i_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] + foreach i_file $ip_constr_files { + set i_module [file tail $i_file] + regsub {_constr\.xdc} $i_module {} i_module + ipx::add_file $i_file $i_filegroup + ipx::reorder_files -front $i_file $i_filegroup + set_property SCOPED_TO_REF $i_module [ipx::get_files $i_file -of_objects $i_filegroup] + } + ipx::save_core +} + +proc adi_ip_properties {ip_name} { + + adi_ip_properties_lite $ip_name + + ipx::infer_bus_interface {\ + s_axi_awvalid \ + s_axi_awaddr \ + s_axi_awprot \ + s_axi_awready \ + s_axi_wvalid \ + s_axi_wdata \ + s_axi_wstrb \ + s_axi_wready \ + s_axi_bvalid \ + s_axi_bresp \ + s_axi_bready \ + s_axi_arvalid \ + s_axi_araddr \ + s_axi_arprot \ + s_axi_arready \ + s_axi_rvalid \ + s_axi_rdata \ + s_axi_rresp \ + s_axi_rready} \ + xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] + + ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + + set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] + set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] + + if {$raddr_width != $waddr_width} { + puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] + set range 65536 + } else { + if {$raddr_width >= 16} { + set range 65536 + } else { + set range [expr 1 << $raddr_width] + } + } + + ipx::add_memory_map {s_axi} [ipx::current_core] + set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] + ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] + set_property range $range [ipx::get_address_blocks axi_lite \ + -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] + ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] + ipx::save_core +} + +## ############################################################################################### +## ############################################################################################### +## interface related stuff + +proc adi_if_define {name} { + + ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 + ipx::create_bus_definition analog.com interface $name 1.0 + + set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] + set_property xml_file_name ${name}.xml [ipx::current_busdef] + set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] + + ipx::save_abstraction_definition [ipx::current_busabs] + ipx::save_bus_definition [ipx::current_busdef] +} + +proc adi_if_ports {dir width name {type none}} { + + ipx::add_bus_abstraction_port $name [ipx::current_busabs] + set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] + set_property master_presence required $m_intf + set_property slave_presence required $m_intf + set_property master_width $width $m_intf + set_property slave_width $width $m_intf + + set m_dir "in" + set s_dir "out" + if {$dir eq "output"} { + set m_dir "out" + set s_dir "in" + } + + set_property master_direction $m_dir $m_intf + set_property slave_direction $s_dir $m_intf + + if {$type ne "none"} { + set_property is_${type} true $m_intf + } + + ipx::save_bus_definition [ipx::current_busdef] + ipx::save_abstraction_definition [ipx::current_busabs] +} + +proc adi_if_infer_bus {if_name mode name maps} { + + ipx::add_bus_interface $name [ipx::current_core] + set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] + set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if + set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if + set_property interface_mode $mode $m_bus_if + + foreach map $maps { + set m_maps [regexp -all -inline {\S+} $map] + lassign $m_maps p_name p_map + ipx::add_port_map $p_name $m_bus_if + set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] + } +} + +## ############################################################################################### +## ############################################################################################### diff --git a/CI/scripts/adi_project.tcl b/CI/scripts/adi_project.tcl new file mode 100644 index 0000000..6656693 --- /dev/null +++ b/CI/scripts/adi_project.tcl @@ -0,0 +1,205 @@ + +variable p_board +variable p_device +variable sys_zynq +variable p_prcfg_init +variable p_prcfg_list +variable p_prcfg_status + +if {![info exists REQUIRED_VIVADO_VERSION]} { + set REQUIRED_VIVADO_VERSION "2018.2" +} + +if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { + set IGNORE_VERSION_CHECK 1 +} elseif {![info exists IGNORE_VERSION_CHECK]} { + set IGNORE_VERSION_CHECK 0 +} + +set p_board "not-applicable" +set p_device "none" +set sys_zynq 1 +set ADI_POWER_OPTIMIZATION 0 + +proc adi_project_xilinx {project_name project_dir update_tcl {mode 0}} { + + global ad_hdl_dir + global ad_phdl_dir + global p_board + global p_device + global sys_zynq + global REQUIRED_VIVADO_VERSION + global IGNORE_VERSION_CHECK + + if [regexp "_ac701$" $project_name] { + set p_device "xc7a200tfbg676-2" + set p_board "xilinx.com:ac701:part0:1.0" + set sys_zynq 0 + } + if [regexp "_kc705$" $project_name] { + set p_device "xc7k325tffg900-2" + set p_board "xilinx.com:kc705:part0:1.1" + set sys_zynq 0 + } + if [regexp "_vc707$" $project_name] { + set p_device "xc7vx485tffg1761-2" + set p_board "xilinx.com:vc707:part0:1.1" + set sys_zynq 0 + } + if [regexp "_kcu105$" $project_name] { + set p_device "xcku040-ffva1156-2-e" + set p_board "xilinx.com:kcu105:part0:1.1" + set sys_zynq 0 + } + if [regexp "_zed$" $project_name] { + set p_device "xc7z020clg484-1" + set p_board "em.avnet.com:zed:part0:1.3" + set sys_zynq 1 + } + if [regexp "_microzed$" $project_name] { + set p_device "xc7z010clg400-1" + set p_board "not-applicable" + set sys_zynq 1 + } + if [regexp "_zc702$" $project_name] { + set p_device "xc7z020clg484-1" + set p_board "xilinx.com:zc702:part0:1.2" + set sys_zynq 1 + } + if [regexp "_zc706$" $project_name] { + set p_device "xc7z045ffg900-2" + set p_board "xilinx.com:zc706:part0:1.2" + set sys_zynq 1 + } + if [regexp "_mitx045$" $project_name] { + set p_device "xc7z045ffg900-2" + set p_board "not-applicable" + set sys_zynq 1 + } + if [regexp "_zcu102$" $project_name] { + set p_device "xczu9eg-ffvb1156-2-e" + set p_board "xilinx.com:zcu102:part0:3.1" + set sys_zynq 2 + } + + #Added + set project_name_org $project_name + set project_name vivado_prj + + set VIVADO_VERSION [version -short] + if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { + puts -nonewline "CRITICAL WARNING: vivado version mismatch; " + puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " + puts -nonewline "got $VIVADO_VERSION.\n" + } + + #Added + adi_setup_libs + + if {$mode == 0} { + set project_system_dir "./$project_name.srcs/sources_1/bd/system" + #Removed + #create_project $project_name . -part $p_device -force + } else { + set project_system_dir ".srcs/sources_1/bd/system" + #Removed + #create_project -in_memory -part $p_device + } + + if {$mode == 1} { + file mkdir $project_name.data + } + + if {$p_board ne "not-applicable"} { + set_property board_part $p_board [current_project] + } + + #Removed + #set lib_dirs $ad_hdl_dir/library + #if {$ad_hdl_dir ne $ad_phdl_dir} { + # lappend lib_dirs $ad_phdl_dir/library + #} + + #set_property ip_repo_paths $lib_dirs [current_fileset] + #update_ip_catalog + + set_msg_config -id {BD 41-1348} -new_severity info + set_msg_config -id {BD 41-1343} -new_severity info + set_msg_config -id {BD 41-1306} -new_severity info + set_msg_config -id {IP_Flow 19-1687} -new_severity info + set_msg_config -id {filemgmt 20-1763} -new_severity info + set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity error + + #Added + create_bd_design "system" + source $project_dir/system_bd.tcl + if {$project_name_org != "adrv9361z7035_ccbox_lvds_modem"} { + source $project_dir/$update_tcl + } + + + regenerate_bd_layout + save_bd_design + validate_bd_design + + set_property synth_checkpoint_mode None [get_files $project_system_dir/system.bd] + generate_target {synthesis implementation} [get_files $project_system_dir/system.bd] + make_wrapper -files [get_files $project_system_dir/system.bd] -top + + if {$mode == 0} { + import_files -force -norecurse -fileset sources_1 $project_system_dir/hdl/system_wrapper.v + } else { + write_hwdef -file "$project_name.data/$project_name.hwdef" + } +} + +#Added +proc adi_setup_libs {} { + global ad_hdl_dir + global ad_phdl_dir + + set lib_dirs [get_property ip_repo_paths [current_fileset]] + + lappend lib_dirs $ad_hdl_dir/library + if {$ad_hdl_dir ne $ad_phdl_dir} { + lappend lib_dirs $ad_phdl_dir/library + } + + set_property ip_repo_paths $lib_dirs [current_fileset] + update_ip_catalog + adi_add_archive_ip $lib_dirs +} + +#Added +proc adi_add_archive_ip {lib_dirs} { + global ad_hdl_dir + global ad_phdl_dir + foreach libDir $lib_dirs { + set ipList [glob -nocomplain -directory $libDir *.zip] + foreach ipCore $ipList { + catch {update_ip_catalog -add_ip $ipCore -repo_path $libDir} + file delete -force $ipCore + } + } +} + +proc adi_project_files {project_name project_files} { + + global ad_hdl_dir + global ad_phdl_dir + global proj_dir + + #Added + cd $proj_dir + + add_files -norecurse -fileset sources_1 $project_files + set_property top system_top [current_fileset] + + #Added + cd $ad_hdl_dir +} + +proc adi_project_run {project_name} { + #Removed +} + diff --git a/CI/scripts/adi_project_xilinx.tcl b/CI/scripts/adi_project_xilinx.tcl new file mode 100644 index 0000000..6c1aae3 --- /dev/null +++ b/CI/scripts/adi_project_xilinx.tcl @@ -0,0 +1,604 @@ +## Define the ADI_USE_OOC_SYNTHESIS environment variable to enable out of context +# synthesis +if {[info exists ::env(ADI_USE_OOC_SYNTHESIS)]} { + if {[string equal $::env(ADI_USE_OOC_SYNTHESIS) n]} { + set ADI_USE_OOC_SYNTHESIS 0 + } else { + set ADI_USE_OOC_SYNTHESIS 1 + } +} elseif {![info exists ADI_USE_OOC_SYNTHESIS]} { + set ADI_USE_OOC_SYNTHESIS 1 +} + +## Set number of parallel out of context jobs through environment variable +if {![info exists ::env(ADI_MAX_OOC_JOBS)]} { + set ADI_MAX_OOC_JOBS 4 +} else { + set ADI_MAX_OOC_JOBS $::env(ADI_MAX_OOC_JOBS) +} + +## Set to enable incremental compilation +set ADI_USE_INCR_COMP 1 + +## Set to enable power optimization +set ADI_POWER_OPTIMIZATION 0 + +## Initialize global variables +set p_board "not-applicable" +set p_device "none" +set sys_zynq 1 + +set p_prcfg_init "" +set p_prcfg_list "" +set p_prcfg_status "" + +## Creates a Xilinx project for a given board +# +# \param[project_name] - name of the project +# \param[mode] - if set non-project mode will be used, otherwise project mode +# flow, see UG892 for more information +# \param[parameter_list] - a list of global parameters (parameters of the +# system_top module) +# +# Supported carrier names are: ac701, kc705, vc707, vcu118, vcu128, kcu105, zed, +# microzed, zc702, zc706, mitx405, zcu102. +# +proc adi_project {project_name {mode 0} {parameter_list {}} } { + + set device "" + set board "" + + # Determine the device based on the board name + if [regexp "_ac701$" $project_name] { + set device "xc7a200tfbg676-2" + set board [lindex [lsearch -all -inline [get_board_parts] *ac701*] end] + } + if [regexp "_kc705$" $project_name] { + set device "xc7k325tffg900-2" + set board [lindex [lsearch -all -inline [get_board_parts] *kc705*] end] + } + if [regexp "_vc707$" $project_name] { + set device "xc7vx485tffg1761-2" + set board [lindex [lsearch -all -inline [get_board_parts] *vc707*] end] + } + if [regexp "_vcu118$" $project_name] { + set device "xcvu9p-flga2104-2L-e" + set board [lindex [lsearch -all -inline [get_board_parts] *vcu118*] end] + } + if [regexp "_vcu128$" $project_name] { + set device "xcvu37p-fsvh2892-2L-e" + set board [lindex [lsearch -all -inline [get_board_parts] *vcu128:part0*] end] + } + if [regexp "_kcu105$" $project_name] { + set device "xcku040-ffva1156-2-e" + set board [lindex [lsearch -all -inline [get_board_parts] *kcu105*] end] + } + if [regexp "_zed$" $project_name] { + set device "xc7z020clg484-1" + set board [lindex [lsearch -all -inline [get_board_parts] *zed*] end] + } + if [regexp "_coraz7s$" $project_name] { + set device "xc7z007sclg400-1" + set board "not-applicable" + } + if [regexp "_microzed$" $project_name] { + set device "xc7z010clg400-1" + set board "not-applicable" + } + if [regexp "_zc702$" $project_name] { + set device "xc7z020clg484-1" + set board [lindex [lsearch -all -inline [get_board_parts] *zc702*] end] + } + if [regexp "_zc706$" $project_name] { + set device "xc7z045ffg900-2" + set board [lindex [lsearch -all -inline [get_board_parts] *zc706*] end] + } + if [regexp "_mitx045$" $project_name] { + set device "xc7z045ffg900-2" + set board "not-applicable" + } + if [regexp "_zcu102$" $project_name] { + set device "xczu9eg-ffvb1156-2-e" + set board [lindex [lsearch -all -inline [get_board_parts] *zcu102*] end] + } + if [regexp "_vmk180_es1$" $project_name] { + enable_beta_device xcvm* + xhub::refresh_catalog [xhub::get_xstores xilinx_board_store] + xhub::install [xhub::get_xitems xilinx.com:xilinx_board_store:vmk180_es:*] -quiet + set_param board.repoPaths [get_property LOCAL_ROOT_DIR [xhub::get_xstores xilinx_board_store]] + set device "xcvm1802-vsva2197-2MP-e-S-es1" + set board [lindex [lsearch -all -inline [get_board_parts] *vmk180_es*] end] + } + if [regexp "_vmk180$" $project_name] { + set device "xcvm1802-vsva2197-2MP-e-S" + set board [lindex [lsearch -all -inline [get_board_parts] *vmk180*] end] + } + if [regexp "_vck190$" $project_name] { + set device "xcvc1902-vsva2197-2MP-e-S" + set board [lindex [lsearch -all -inline [get_board_parts] *vck190*] end] + } + if [regexp "_vc709$" $project_name] { + set device "xc7vx690tffg1761-2" + set board [lindex [lsearch -all -inline [get_board_parts] *vc709*] end] + } + + adi_project_create $project_name $mode $parameter_list $device $board +} + + +## Creates a Xilinx project. +# +# \param[project_name] - name of the project +# \param[mode] - if set non-project mode will be used, otherwise project mode +# flow, see UG892 for more information +# \param[parameter_list] - a list of global parameters (parameters of the +# system_top module) +# \param[device] - Canonical Xilinx device string +# \param[board] - board BSP name (optional) +# +proc adi_project_create {project_name mode parameter_list device {board "not-applicable"}} { + + global ad_hdl_dir + global ad_ghdl_dir + global p_board + global p_device + global sys_zynq + global required_vivado_version + global IGNORE_VERSION_CHECK + global ADI_USE_OOC_SYNTHESIS + global ADI_USE_INCR_COMP + + ## update the value of $p_device only if it was not already updated elsewhere + if {$p_device eq "none"} { + set p_device $device + } + set p_board $board + + if [regexp "^xc7z" $p_device] { + set sys_zynq 1 + } elseif [regexp "^xczu" $p_device] { + set sys_zynq 2 + } elseif [regexp "^xcv\[ecmph\]" $p_device] { + set sys_zynq 3 + } else { + set sys_zynq 0 + } + + set VIVADO_VERSION [version -short] + if {$IGNORE_VERSION_CHECK} { + if {[string compare $VIVADO_VERSION $required_vivado_version] != 0} { + puts -nonewline "CRITICAL WARNING: vivado version mismatch; " + puts -nonewline "expected $required_vivado_version, " + puts -nonewline "got $VIVADO_VERSION.\n" + } + } else { + if {[string compare $VIVADO_VERSION $required_vivado_version] != 0} { + puts -nonewline "ERROR: vivado version mismatch; " + puts -nonewline "expected $required_vivado_version, " + puts -nonewline "got $VIVADO_VERSION.\n" + puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" + exit 2 + } + } + + if {[info exists ::env(MATLAB)]} { + set MATLAB 1 + set project_name "vivado_prj" + set project_root $ad_hdl_dir + if {$mode != 0} { + puts -nonewline "MATLAB builds do not support mode 2" + exit 2 + } + } else { + set MATLAB 0 + set project_root [pwd] + } + + if {$mode == 0} { + set project_system_dir "$project_root/$project_name.srcs/sources_1/bd/system" + if {$MATLAB == 0} { + create_project $project_name . -part $p_device -force + } + } else { + set project_system_dir "$project_root/.srcs/sources_1/bd/system" + create_project -in_memory -part $p_device + } + + if {$mode == 1} { + file mkdir $project_root/$project_name.data + } + + if {$p_board ne "not-applicable"} { + set_property board_part $p_board [current_project] + } + + if {$MATLAB == 0} { + set lib_dirs $ad_hdl_dir/library + } else { + set lib_dirs [get_property ip_repo_paths [current_fileset]] + lappend lib_dirs $ad_hdl_dir/library + } + if {[info exists ::env(ADI_GHDL_DIR)]} { + if {$ad_hdl_dir ne $ad_ghdl_dir} { + lappend lib_dirs $ad_ghdl_dir/library + } + } else { + # puts -nonew-line "INFO: ADI_GHDL_DIR not defined.\n" + } + + # Set a common IP cache for all projects + if {$ADI_USE_OOC_SYNTHESIS == 1} { + if {[file exists $ad_hdl_dir/ipcache] == 0} { + file mkdir $ad_hdl_dir/ipcache + } + config_ip_cache -import_from_project -use_cache_location $ad_hdl_dir/ipcache + } + + set_property ip_repo_paths $lib_dirs [current_fileset] + update_ip_catalog + + ## Load custom message severity definitions + + if {![info exists ::env(ADI_DISABLE_MESSAGE_SUPPRESION)]} { + source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl + } + + ## In Vivado there is a limit for the number of warnings and errors which are + ## displayed by the tool for a particular error or warning; the default value + ## of this limit is 100. + ## Overrides the default limit to 2000. + set_param messaging.defaultLimit 2000 + + # Set parameters of the top level file + # Make the same parameters available to system_bd.tcl + set proj_params [get_property generic [current_fileset]] + foreach {param value} $parameter_list { + lappend proj_params $param=$value + set ad_project_params($param) $value + } + set_property generic $proj_params [current_fileset] + + create_bd_design "system" + source system_bd.tcl + + save_bd_design + validate_bd_design + + if {$ADI_USE_OOC_SYNTHESIS == 1} { + set_property synth_checkpoint_mode Hierarchical [get_files $project_system_dir/system.bd] + } else { + set_property synth_checkpoint_mode None [get_files $project_system_dir/system.bd] + } + generate_target {synthesis implementation} [get_files $project_system_dir/system.bd] + if {$ADI_USE_OOC_SYNTHESIS == 1} { + export_ip_user_files -of_objects [get_files $project_system_dir/system.bd] -no_script -sync -force -quiet + create_ip_run [get_files $project_system_dir/system.bd] + } + make_wrapper -files [get_files $project_system_dir/system.bd] -top + + if {$mode == 0} { + import_files -force -norecurse -fileset sources_1 $project_system_dir/hdl/system_wrapper.v + } else { + write_hwdef -file "$project_name.data/$project_name.hwdef" + } + + if {$ADI_USE_INCR_COMP == 1} { + if {[file exists ./reference.dcp]} { + set_property incremental_checkpoint ./reference.dcp [get_runs impl_1] + } + } + +} + +## Add source files to an exiting project. +# +# \param[project_name] - name of the project +# \param[project_files] - list of project files +# +proc adi_project_files {project_name project_files} { + + foreach pfile $project_files { + if {[string range $pfile [expr 1 + [string last . $pfile]] end] == "xdc"} { + add_files -norecurse -fileset constrs_1 $pfile + } elseif [regexp "_constr.tcl" $pfile] { + add_files -norecurse -fileset sources_1 $pfile + } else { + add_files -norecurse -fileset sources_1 $pfile + } + } + + # NOTE: top file name is always system_top + set_property top system_top [current_fileset] +} + +## Run an existing project (generate bit stream). +# +# \param[project_name] - name of the project +# +proc adi_project_run {project_name} { + + global ADI_POWER_OPTIMIZATION + global ADI_USE_OOC_SYNTHESIS + global ADI_MAX_OOC_JOBS + + if {[info exists ::env(SKIP_SYNTHESIS)]} { + puts "Skipping synthesis" + return + } + + if {$ADI_USE_OOC_SYNTHESIS == 1} { + launch_runs -jobs $ADI_MAX_OOC_JOBS system_*_synth_1 synth_1 + } else { + launch_runs synth_1 + } + wait_on_run synth_1 + open_run synth_1 + report_timing_summary -file timing_synth.log + + if {![info exists ::env(ADI_NO_BITSTREAM_COMPRESSION)] && ![info exists ADI_NO_BITSTREAM_COMPRESSION]} { + set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] + } + + if {$ADI_POWER_OPTIMIZATION == 1} { + set_property STEPS.POWER_OPT_DESIGN.IS_ENABLED true [get_runs impl_1] + set_property STEPS.POST_PLACE_POWER_OPT_DESIGN.IS_ENABLED true [get_runs impl_1] + } + + set_param board.repoPaths [get_property LOCAL_ROOT_DIR [xhub::get_xstores xilinx_board_store]] + + launch_runs impl_1 -to_step write_bitstream + wait_on_run impl_1 + open_run impl_1 + report_timing_summary -warn_on_violation -file timing_impl.log + + if {[info exists ::env(ADI_GENERATE_UTILIZATION)]} { + set csv_file resource_utilization.csv + if {[ catch { + xilinx::designutils::report_failfast -csv -file $csv_file -transpose -no_header -ignore_pr -quiet + set MMCM [llength [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ *MMCM* }]] + set PLL [llength [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ *PLL* }]] + set worst_slack_setup [get_property SLACK [get_timing_paths -setup]] + set worst_slack_hold [get_property SLACK [get_timing_paths -hold]] + + set fileRead [open $csv_file r] + set lines [split [read $fileRead] "\n"] + set names_line [lindex $lines end-3] + set values_line [lindex $lines end-2] + close $fileRead + + set fileWrite [open $csv_file w] + puts $fileWrite "$names_line,MMCM*,PLL*,Worst_Setup_Slack,Worst_Hold_Slack" + puts $fileWrite "$values_line,$MMCM,$PLL,$worst_slack_setup,$worst_slack_hold" + close $fileWrite + } issue ] != 0 } { + puts "GENERATE_REPORTS: tclapp::xilinx::designutils not installed" + } + + # Define a list of IPs for which to generate report utilization + set IP_list { + ad_ip_jesd_204_tpl_adc + ad_ip_jesd_204_tpl_dac + axi_jesd204_rx + axi_jesd204_tx + jesd204_rx + jesd204_tx + axi_adxcvr + util_adxcvr + axi_dmac + util_cpack2 + util_upack2 + } + + foreach IP_name $IP_list { + set output_file ${IP_name}_resource_utilization.log + file delete $output_file + foreach IP_instance [ get_cells -quiet -hierarchical -filter " ORIG_REF_NAME =~ $IP_name || REF_NAME =~ $IP_name " ] { + report_utilization -hierarchical -hierarchical_depth 1 -cells $IP_instance -file $output_file -append -quiet + report_property $IP_instance -file $output_file -append -quiet + set report_file [ open $output_file a ] + puts $report_file "\n\n\n" + close $report_file + } + } + } else { + puts "GENERATE_REPORTS: Resource utilization files won't be generated because ADI_GENERATE_UTILIZATION env var is not set" + } + + if {[info exists ::env(ADI_GENERATE_XPA)]} { + set csv_file power_analysis.csv + set Layers "8to11" + set CapLoad "20" + set ToggleRate "15.00000" + set StatProb "0.500000" + + set_load $CapLoad [all_outputs] + set_operating_conditions -board_layers $Layers + set_switching_activity -default_toggle_rate $ToggleRate + set_switching_activity -default_static_probability $StatProb + set_switching_activity -type lut -toggle_rate $ToggleRate -static_probability $StatProb -all + set_switching_activity -type register -toggle_rate $ToggleRate -static_probability $StatProb -all + set_switching_activity -type shift_register -toggle_rate $ToggleRate -static_probability $StatProb -all + set_switching_activity -type lut_ram -toggle_rate $ToggleRate -static_probability $StatProb -all + set_switching_activity -type bram -toggle_rate $ToggleRate -static_probability $StatProb -all + set_switching_activity -type dsp -toggle_rate $ToggleRate -static_probability $StatProb -all + set_switching_activity -type gt_rxdata -toggle_rate $ToggleRate -static_probability $StatProb -all + set_switching_activity -type gt_txdata -toggle_rate $ToggleRate -static_probability $StatProb -all + set_switching_activity -type io_output -toggle_rate $ToggleRate -static_probability $StatProb -all + set_switching_activity -type bram_enable -toggle_rate $ToggleRate -static_probability $StatProb -all + set_switching_activity -type bram_wr_enable -toggle_rate $ToggleRate -static_probability $StatProb -all + set_switching_activity -type io_bidir_enable -toggle_rate $ToggleRate -static_probability $StatProb -all + report_power -file $csv_file + + set fileRead [open $csv_file r] + set filecontent [read $fileRead] + set input_list [split $filecontent "\n"] + + set TextList [lsearch -all -inline $input_list "*Total On-Chip Power (W)*"] + set on_chip_pwr "[lindex [lindex $TextList 0] 6] W" + set TextList [lsearch -all -inline $input_list "*Junction Temperature (C)*"] + set junction_temp "[lindex [lindex $TextList 0] 5] *C" + close $fileRead + + set fileWrite [open $csv_file w] + puts $fileWrite "On-chip_power,Junction_temp" + puts $fileWrite "$on_chip_pwr,$junction_temp" + close $fileWrite + } else { + puts "GENERATE_REPORTS: Power analysis files won't be generated because ADI_GENERATE_XPA env var is not set" + } + + # Look for undefined clocks which do not show up in the timing summary + set timing_check [check_timing -override_defaults no_clock -no_header -return_string] + if {[regexp { (\d+) register} $timing_check -> num_regs]} { + + if {[info exist num_regs]} { + if {$num_regs > 0} { + puts "CRITICAL WARNING: There are $num_regs registers with no clocks !!! See no_clock.log for details." + check_timing -override_defaults no_clock -verbose -file no_clock.log + } + } + + } else { + puts "CRITICAL WARNING: The search for undefined clocks failed !!!" + } + + file mkdir $project_name.sdk + + set timing_string $[report_timing_summary -return_string] + if { [string match "*VIOLATED*" $timing_string] == 1 || + [string match "*Timing constraints are not met*" $timing_string] == 1} { + write_hw_platform -fixed -force -include_bit -file $project_name.sdk/system_top_bad_timing.xsa + return -code error [format "ERROR: Timing Constraints NOT met!"] + } else { + write_hw_platform -fixed -force -include_bit -file $project_name.sdk/system_top.xsa + } +} + +## Run synthesis on an partial design; use it in Partial Reconfiguration flow. +# +# \param[project_name] - project name +# \param[prcfg_name] - name of the partial design +# \param[hdl_files] - hdl source of the partial design +# \param[xdc_files] - XDC constraint source of the partial design +# +proc adi_project_synth {project_name prcfg_name hdl_files {xdc_files ""}} { + + global p_device + + set p_prefix "$project_name.data/$project_name" + + if {$prcfg_name eq ""} { + + read_verilog .srcs/sources_1/bd/system/hdl/system_wrapper.v + read_verilog $hdl_files + read_xdc $xdc_files + + synth_design -mode default -top system_top -part $p_device > $p_prefix.synth.rds + write_checkpoint -force $p_prefix.synth.dcp + close_project + + } else { + + create_project -in_memory -part $p_device + read_verilog $hdl_files + synth_design -mode out_of_context -top "prcfg" -part $p_device > $p_prefix.${prcfg_name}_synth.rds + write_checkpoint -force $p_prefix.${prcfg_name}_synth.dcp + close_project + } +} + +## Run implementation on an partial design; use it in Partial Reconfiguration +# flow. +# +# \param[project_name] - project name +# \param[prcfg_name] - name of the partial design +# \param[xdc_files] - XDC constraint source of the partial design +# +proc adi_project_impl {project_name prcfg_name {xdc_files ""}} { + + global p_device + global p_prcfg_init + global p_prcfg_list + global p_prcfg_status + + set p_prefix "$project_name.data/$project_name" + + if {$prcfg_name eq "default"} { + set p_prcfg_status 0 + set p_prcfg_list "" + set p_prcfg_init "$p_prefix.${prcfg_name}_impl.dcp" + file mkdir $project_name.sdk + } + + if {$prcfg_name eq "default"} { + + open_checkpoint $p_prefix.synth.dcp -part $p_device + read_xdc $xdc_files + read_checkpoint -cell i_prcfg $p_prefix.${prcfg_name}_synth.dcp + set_property HD.RECONFIGURABLE 1 [get_cells i_prcfg] + opt_design > $p_prefix.${prcfg_name}_opt.rds + write_debug_probes -force $p_prefix.${prcfg_name}_debug_nets.ltx + place_design > $p_prefix.${prcfg_name}_place.rds + route_design > $p_prefix.${prcfg_name}_route.rds + + } else { + + open_checkpoint $p_prefix.default_impl_bb.dcp -part $p_device + lock_design -level routing + read_checkpoint -cell i_prcfg $p_prefix.${prcfg_name}_synth.dcp + read_xdc $xdc_files + opt_design > $p_prefix.${prcfg_name}_opt.rds + place_design > $p_prefix.${prcfg_name}_place.rds + route_design > $p_prefix.${prcfg_name}_route.rds + } + + write_checkpoint -force $p_prefix.${prcfg_name}_impl.dcp + report_utilization -pblocks pb_prcfg -file $p_prefix.${prcfg_name}_utilization.rpt + report_timing_summary -file $p_prefix.${prcfg_name}_timing_summary.rpt + + if [expr [get_property SLACK [get_timing_paths]] < 0] { + set p_prcfg_status 1 + puts "CRITICAL WARNING: Timing Constraints NOT met ($prcfg_name)!" + } + + write_checkpoint -force -cell i_prcfg $p_prefix.${prcfg_name}_prcfg_impl.dcp + update_design -cell i_prcfg -black_box + write_checkpoint -force $p_prefix.${prcfg_name}_impl_bb.dcp + open_checkpoint $p_prefix.${prcfg_name}_impl.dcp -part $p_device + write_bitstream -force -bin_file -file $p_prefix.${prcfg_name}.bit + write_sysdef -hwdef $p_prefix.hwdef -bitfile $p_prefix.${prcfg_name}.bit -file $p_prefix.${prcfg_name}.hdf + file copy -force $p_prefix.${prcfg_name}.hdf $project_name.sdk/system_top.${prcfg_name}.hdf + + if {$prcfg_name ne "default"} { + lappend p_prcfg_list "$p_prefix.${prcfg_name}_impl.dcp" + } + + if {$prcfg_name eq "default"} { + file copy -force $p_prefix.${prcfg_name}.hdf $project_name.sdk/system_top.hdf + } +} + +## Verify an implemented partial reconfiguration design, checks if all the +# partial design are compatible with the base design. +# +# \param[project_name] - project name +# +proc adi_project_verify {project_name} { + + # checkpoint for the default design + global p_prcfg_init + # list of checkpoints with all the PRs integrated into the default design + global p_prcfg_list + global p_prcfg_status + + set p_prefix "$project_name.data/$project_name" + + pr_verify -full_check -initial $p_prcfg_init \ + -additional $p_prcfg_list \ + -file $p_prefix.prcfg_verify.log + + if {$p_prcfg_status == 1} { + return -code error [format "ERROR: Timing Constraints NOT met!"] + } +} + diff --git a/CI/scripts/boot/adrv9361/fsbl.elf b/CI/scripts/boot/adrv9361/fsbl.elf new file mode 100644 index 0000000..a902ebf Binary files /dev/null and b/CI/scripts/boot/adrv9361/fsbl.elf differ diff --git a/CI/scripts/boot/adrv9361/u-boot.elf b/CI/scripts/boot/adrv9361/u-boot.elf new file mode 100644 index 0000000..e2822e9 Binary files /dev/null and b/CI/scripts/boot/adrv9361/u-boot.elf differ diff --git a/CI/scripts/boot/adrv9361/zynq.bif b/CI/scripts/boot/adrv9361/zynq.bif new file mode 100644 index 0000000..17acde4 --- /dev/null +++ b/CI/scripts/boot/adrv9361/zynq.bif @@ -0,0 +1,6 @@ +the_ROM_image: +{ +[bootloader] ./fsbl.elf +./system_top.bit +./u-boot.elf +} diff --git a/CI/scripts/boot/adrv9364/fsbl.elf b/CI/scripts/boot/adrv9364/fsbl.elf new file mode 100644 index 0000000..431eb81 Binary files /dev/null and b/CI/scripts/boot/adrv9364/fsbl.elf differ diff --git a/CI/scripts/boot/adrv9364/u-boot.elf b/CI/scripts/boot/adrv9364/u-boot.elf new file mode 100644 index 0000000..e2822e9 Binary files /dev/null and b/CI/scripts/boot/adrv9364/u-boot.elf differ diff --git a/CI/scripts/boot/adrv9364/zynq.bif b/CI/scripts/boot/adrv9364/zynq.bif new file mode 100644 index 0000000..17acde4 --- /dev/null +++ b/CI/scripts/boot/adrv9364/zynq.bif @@ -0,0 +1,6 @@ +the_ROM_image: +{ +[bootloader] ./fsbl.elf +./system_top.bit +./u-boot.elf +} diff --git a/CI/scripts/boot/zc702/fsbl.elf b/CI/scripts/boot/zc702/fsbl.elf new file mode 100644 index 0000000..4454bed Binary files /dev/null and b/CI/scripts/boot/zc702/fsbl.elf differ diff --git a/CI/scripts/boot/zc702/u-boot.elf b/CI/scripts/boot/zc702/u-boot.elf new file mode 100644 index 0000000..3d04955 Binary files /dev/null and b/CI/scripts/boot/zc702/u-boot.elf differ diff --git a/CI/scripts/boot/zc702/zynq.bif b/CI/scripts/boot/zc702/zynq.bif new file mode 100644 index 0000000..17acde4 --- /dev/null +++ b/CI/scripts/boot/zc702/zynq.bif @@ -0,0 +1,6 @@ +the_ROM_image: +{ +[bootloader] ./fsbl.elf +./system_top.bit +./u-boot.elf +} diff --git a/CI/scripts/boot/zc706/fsbl.elf b/CI/scripts/boot/zc706/fsbl.elf new file mode 100644 index 0000000..0a6de07 Binary files /dev/null and b/CI/scripts/boot/zc706/fsbl.elf differ diff --git a/CI/scripts/boot/zc706/u-boot.elf b/CI/scripts/boot/zc706/u-boot.elf new file mode 100644 index 0000000..87ce579 Binary files /dev/null and b/CI/scripts/boot/zc706/u-boot.elf differ diff --git a/CI/scripts/boot/zc706/zynq.bif b/CI/scripts/boot/zc706/zynq.bif new file mode 100644 index 0000000..17acde4 --- /dev/null +++ b/CI/scripts/boot/zc706/zynq.bif @@ -0,0 +1,6 @@ +the_ROM_image: +{ +[bootloader] ./fsbl.elf +./system_top.bit +./u-boot.elf +} diff --git a/CI/scripts/boot/zcu102/bl31.elf b/CI/scripts/boot/zcu102/bl31.elf new file mode 100644 index 0000000..7461992 Binary files /dev/null and b/CI/scripts/boot/zcu102/bl31.elf differ diff --git a/CI/scripts/boot/zcu102/fsbl.elf b/CI/scripts/boot/zcu102/fsbl.elf new file mode 100644 index 0000000..d812cf4 Binary files /dev/null and b/CI/scripts/boot/zcu102/fsbl.elf differ diff --git a/CI/scripts/boot/zcu102/pmufw.elf b/CI/scripts/boot/zcu102/pmufw.elf new file mode 100644 index 0000000..7626f7a Binary files /dev/null and b/CI/scripts/boot/zcu102/pmufw.elf differ diff --git a/CI/scripts/boot/zcu102/u-boot.elf b/CI/scripts/boot/zcu102/u-boot.elf new file mode 100644 index 0000000..b651e27 Binary files /dev/null and b/CI/scripts/boot/zcu102/u-boot.elf differ diff --git a/CI/scripts/boot/zcu102/zynq.bif b/CI/scripts/boot/zcu102/zynq.bif new file mode 100644 index 0000000..338d461 --- /dev/null +++ b/CI/scripts/boot/zcu102/zynq.bif @@ -0,0 +1,8 @@ +the_ROM_image: +{ +[pmufw_image] ./pmufw.elf +[bootloader,destination_cpu=a53-0] ./fsbl.elf +[destination_device=pl] ./system_top.bit +[destination_cpu=a53-0,exception_level=el-3,trustzone] ./bl31.elf +[destination_cpu=a53-0,exception_level=el-2] ./u-boot.elf +} diff --git a/CI/scripts/boot/zed/fsbl.elf b/CI/scripts/boot/zed/fsbl.elf new file mode 100644 index 0000000..ebcea23 Binary files /dev/null and b/CI/scripts/boot/zed/fsbl.elf differ diff --git a/CI/scripts/boot/zed/u-boot.elf b/CI/scripts/boot/zed/u-boot.elf new file mode 100644 index 0000000..e2822e9 Binary files /dev/null and b/CI/scripts/boot/zed/u-boot.elf differ diff --git a/CI/scripts/boot/zed/zynq.bif b/CI/scripts/boot/zed/zynq.bif new file mode 100644 index 0000000..17acde4 --- /dev/null +++ b/CI/scripts/boot/zed/zynq.bif @@ -0,0 +1,6 @@ +the_ROM_image: +{ +[bootloader] ./fsbl.elf +./system_top.bit +./u-boot.elf +} diff --git a/CI/scripts/bsp.tmpl b/CI/scripts/bsp.tmpl new file mode 100644 index 0000000..a25926f --- /dev/null +++ b/CI/scripts/bsp.tmpl @@ -0,0 +1,161 @@ + + + __APP-NAME__ + Travis Collins + travis.collins@analog.com + Analog Devices, Inc + Board support package for HDL targeting and data streaming from Analog Devices transceivers. + Scripts and tools created by ADI to be used with MATLAB and Simulink with ADI transceivers +Documentation: https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/software/matlab_bsp +Support: https://ez.analog.com/ + __REPO-ROOT__/CI/doc/source/_static/assets/ADI_Logo_AWP_Large.png + __VERSION__ + ${PROJECT_ROOT}/Analog Devices Board Support Packages.mltbx + + MATLAB + Simulink + Communications Toolbox + DSP System Toolbox + HDL Coder + Signal Processing Toolbox + Simulink Coder + + + 1 + 2 + 36 + 24 + 101 + 8 + 14 + + + 9.5 + 9.2 + 7.0 + 9.7 + 3.13 + 8.1 + 9.0 + + + __UUID__ + % +CI/* +hdl_prj/* +slprj/* +.git/* +test/* +itests/* +mltbx/* +*~ +.Xil/* + true + + + + + ${PROJECT_ROOT}/info.xml + + + + false + __ML-RELEASE__ + __ML-RELEASE__ + true + true + false + true + false + + + + + + + + + + + + + + + + + + + + + + + + + + + + + __REPO-ROOT__ + + + ${PROJECT_ROOT}/LICENSE + ${PROJECT_ROOT}/README.md + ${PROJECT_ROOT}/doc + ${PROJECT_ROOT}/hdl + ${PROJECT_ROOT}/info.xml + ${PROJECT_ROOT}/__EXAMPLES-DIR__ + + + + + + + __REPO-ROOT__/AnalogDevicesTransceiverToolbox.mltbx + + + + /usr/local/MATLAB/__ML-RELEASE__ + + + + + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + false + false + false + false + false + true + false + 4.15.0-34-generic + false + true + glnxa64 + true + + + diff --git a/CI/scripts/bsp_noexamples.tmpl b/CI/scripts/bsp_noexamples.tmpl new file mode 100644 index 0000000..e34f347 --- /dev/null +++ b/CI/scripts/bsp_noexamples.tmpl @@ -0,0 +1,162 @@ + + + __APP-NAME__ + Travis Collins + travis.collins@analog.com + Analog Devices, Inc + Board support package for HDL targeting and data streaming from Analog Devices transceivers. + Scripts and tools created by ADI to be used with MATLAB and Simulink with ADI transceivers +Documentation: https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/software/matlab_bsp +Support: https://ez.analog.com/ + __REPO-ROOT__/CI/doc/source/_static/assets/ADI_Logo_AWP_Large.png + __VERSION__ + ${PROJECT_ROOT}/AnalogDevicesTransceiverToolbox.mltbx + + MATLAB + Simulink + Communications Toolbox + DSP System Toolbox + HDL Coder + Signal Processing Toolbox + Simulink Coder + + + 1 + 2 + 36 + 24 + 101 + 8 + 14 + + + 9.5 + 9.2 + 7.0 + 9.7 + 3.13 + 8.1 + 9.0 + + + __UUID__ + % +CI/* +deps/* +hdl_prj/* +slprj/* +.git/* +test/* +itests/* +mltbx/* +trx_examples/* +*~ +.Xil/* + true + + + + + ${PROJECT_ROOT}/info.xml + + + + false + __ML-RELEASE__ + __ML-RELEASE__ + true + true + false + true + false + + + + + + + + + + + + + + + + + + + + + + + + + + + + + __REPO-ROOT__ + + + ${PROJECT_ROOT}/LICENSE + ${PROJECT_ROOT}/README.md + ${PROJECT_ROOT}/doc + ${PROJECT_ROOT}/hdl + ${PROJECT_ROOT}/info.xml + + + + + + + __REPO-ROOT__/AnalogDevicesTransceiverToolbox.mltbx + + + + /usr/local/MATLAB/__ML-RELEASE__ + + + + + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + false + false + false + false + false + true + false + 4.15.0-34-generic + false + true + glnxa64 + true + + + diff --git a/CI/scripts/build_bsp.sh b/CI/scripts/build_bsp.sh new file mode 100644 index 0000000..bd4d827 --- /dev/null +++ b/CI/scripts/build_bsp.sh @@ -0,0 +1,163 @@ +#!/bin/bash +set -xe + +if [ -z "${HDLBRANCH}" ]; then +HDLBRANCH='hdl_2021_r2' +fi + +# Script is designed to run from specific location +scriptdir=`dirname "$BASH_SOURCE"` +cd $scriptdir +cd .. + +# Get HDL +if [ -d "hdl" ]; then + rm -rf "hdl" +fi +for i in {1..5} +do + if git clone --single-branch -b $HDLBRANCH https://github.com/analogdevicesinc/hdl.git + then + break + fi + if [ -d "hdl" ]; then + break + fi +done +if [ ! -d "hdl" ]; then + echo "HDL clone failed" + exit 1 +fi + +if [ -z "${VIVADO}" ]; then + echo "VIVADO not set, will parse HDL" + + # Get required vivado version needed for HDL + TARGET="hdl/scripts/adi_env.tcl" + # Use grep to find the line containing "set required_vivado_version" + matched_line=$(grep 'set required_vivado_version' "$TARGET") + + # Use awk to extract the version number + VIVADO=$(echo "$matched_line" | awk -F'"' '{print $2}') + + # Print the extracted version number + echo "Parsed Vivado Version: $VIVADO" +fi + +# If not of the form 20xx.x, exit +if [[ ! $VIVADO =~ ^20[0-9]{2}\.[0-9]$ ]]; then + echo "Vivado version not of the form 20xx.x" + exit 1 +fi + +# Update vivado version in MATLAB files +echo "Updating toolbox files to use desired Vivado version" +cd .. +# Update Version.m +sed -i "s/Vivado = .*/Vivado = \'${VIVADO}\';/" +adi/Version.m +# Update plugin_rd +sed -i "s/hRD\.SupportedToolVersion = .*/hRD\.SupportedToolVersion = {\'${VIVADO}\'};/" hdl/vendor/AnalogDevices/+AnalogDevices/plugin_rd.m + +# Demos +cd trx_examples +# Update all occurances of hWC.ReferenceDesignToolVersion = '20XX.X'; to use new version +FILES=$(grep -lrn . -e 'hWC.ReferenceDesignToolVersion =') +for f in $FILES; do + echo "Updating: $f" + sed -i "s/hWC\.ReferenceDesignToolVersion = .*/hWC\.ReferenceDesignToolVersion = \'${VIVADO}\';/" "$f" +done +# Update all occurances of hRD.SupportedToolVersion = {'20XX.X'}; to use new version +FILES=$(grep -lr . -e 'hRD.SupportedToolVersion =') +for f in $FILES; do + echo "Updating: $f" + sed -i "s/hRD\.SupportedToolVersion = .*/hRD\.SupportedToolVersion = {\'${VIVADO}\'};/" "$f" +done +# Update all occurances of Vivado sourcing +FILES=$(grep -lrn . -e 'source /opt/Xilinx/Vivado/20') +for f in $FILES; do + echo "Updating: $f" + sed -i "s/source \/opt\/Xilinx\/Vivado\/20.*/source \/opt\/Xilinx\/Vivado\/${VIVADO}\/settings64.sh/" "$f" +done +cd .. + +# Tests +cd test +# Update line 35 of DemoTests.m to use new version +sed -i "35s/.*/ testCase.setupVivado('${VIVADO}');/" DemoTests.m +sed -i "47s/.*/ testCase.setupVivado('${VIVADO}');/" DemoTests.m +sed -i "59s/.*/ testCase.setupVivado('${VIVADO}');/" DemoTests.m + +cd .. + +cd CI + +# Setup +# source /opt/Xilinx/Vivado/$VIVADO/settings64.sh + +# Pre-build IP library +# cd hdl/library +# make +# cd ../.. + +# Rename .prj files since MATLAB ignores then during packaging +FILES=$(grep -lrn hdl/projects/common -e '.prj' | grep -v Makefile | grep -v .git) +for f in $FILES +do + echo "Updating prj reference in: $f" + sed -i "s/\.prj/\.mk/g" "$f" +done +FILES=$(find hdl/projects/common -name "*.prj") +for f in $FILES +do + DEST="${f::-3}mk" + echo "Renaming: $f to $DEST" + mv "$f" "$DEST" +done + +# Remove git directory move to bsp folder +rm -fr hdl/.git* +TARGET="../hdl/vendor/AnalogDevices/vivado" +if [ -d "$TARGET" ]; then + rm -rf "$TARGET" +fi +# Increase rx_clk period to fix timing failures for Pluto designs in R2021b +sed -i 's/16.27/30/' hdl/projects/pluto/system_constr.xdc +# update .mk to .prj in zc706_plddr3_dacfifo_bd.tcl +sed -i 's/.mk/.prj/' hdl/projects/common/zc706/zc706_plddr3_dacfifo_bd.tcl +sed -i '10i file copy -force $ad_hdl_dir/projects/common/zc706/zc706_plddr3_mig.mk $ad_hdl_dir/projects/common/zc706/zc706_plddr3_mig.prj' hdl/projects/common/zc706/zc706_plddr3_dacfifo_bd.tcl +# Update ADRV9001 design to include util_sync as dependent IP +sed -i '23i # Custom Sync IP' hdl/projects/adrv9001/zcu102/Makefile +sed -i '24i LIB_DEPS += util_sync/util_delay' hdl/projects/adrv9001/zcu102/Makefile +sed -i '25i LIB_DEPS += util_sync/sync_fast_to_slow' hdl/projects/adrv9001/zcu102/Makefile +sed -i '26i LIB_DEPS += util_sync/sync_slow_to_fast' hdl/projects/adrv9001/zcu102/Makefile + +mv hdl $TARGET + +# Post-process ports.json +cp ./scripts/ports.json ./ +python3 ./scripts/read_ports_json.py +cp ports.json ../hdl/vendor/AnalogDevices/+AnalogDevices/ + +# Updates +cp scripts/matlab_processors.tcl ../hdl/vendor/AnalogDevices/vivado/projects/scripts/matlab_processors.tcl +cp scripts/adi_project_xilinx.tcl ../hdl/vendor/AnalogDevices/vivado/projects/scripts/adi_project_xilinx.tcl +cp scripts/system_project_rxtx.tcl ../hdl/vendor/AnalogDevices/vivado/projects/scripts/system_project_rxtx.tcl +cp scripts/adi_build.tcl ../hdl/vendor/AnalogDevices/vivado/projects/scripts/adi_build.tcl +cp scripts/adi_build_win.tcl ../hdl/vendor/AnalogDevices/vivado/projects/scripts/adi_build_win.tcl + +# Copy fsbl files +cp scripts/fsbl_build_zynq.tcl ../hdl/vendor/AnalogDevices/vivado/projects/scripts/fsbl_build_zynq.tcl +cp scripts/fsbl_build_zynqmp.tcl ../hdl/vendor/AnalogDevices/vivado/projects/scripts/fsbl_build_zynqmp.tcl +cp scripts/pmufw_zynqmp.tcl ../hdl/vendor/AnalogDevices/vivado/projects/scripts/pmufw_zynqmp.tcl +cp scripts/fixmake.sh ../hdl/vendor/AnalogDevices/vivado/projects/scripts/fixmake.sh + +# Copy boot files +mkdir ../hdl/vendor/AnalogDevices/vivado/projects/common/boot/ +cp -r scripts/boot/* ../hdl/vendor/AnalogDevices/vivado/projects/common/boot/ + +# Copy additional IP files +cp -r scripts/library/* ../hdl/vendor/AnalogDevices/vivado/library/ +mkdir -p ../test/hdl/vendor/AnalogDevices/vivado +cp ../hdl/vendor/AnalogDevices/vivado/quiet.mk ../test/hdl/vendor/AnalogDevices/vivado + +echo 'puts "Skipping"' > ../hdl/vendor/AnalogDevices/vivado/library/axi_ad9361/axi_ad9361_delay.tcl diff --git a/CI/scripts/copy_all_packed_ips.tcl b/CI/scripts/copy_all_packed_ips.tcl new file mode 100644 index 0000000..d7628a4 --- /dev/null +++ b/CI/scripts/copy_all_packed_ips.tcl @@ -0,0 +1,69 @@ + + +proc copy_all_packed_ips { DEST_FOLDER } { + + #set WD [pwd] + #set DEST_FOLDER D:/Work/hdlbsp-master/vendor/AnalogDevices/vivado/library + #set DEST_FOLDER $WD + + set folder_list [glob -types d *] + foreach dir $folder_list { + puts "$dir" + cd $dir + + if {[catch {set files_list [glob *]}]} { + cd .. + continue + } + + foreach file $files_list { + set idx [string first .zip $file 1] + if {$idx != -1} { + file copy -force $file $DEST_FOLDER/$file + puts $file + } + } + cd .. + + # Don't remove these folders + if {$dir=="common"} {continue} + if {$dir=="interfaces"} {continue} + if {$dir=="prcfg"} {continue} + if {$dir=="scripts"} {continue} + if {$dir=="xilinx"} {continue} + if {$dir=="jesd204"} {continue} + if {$dir=="spi_engine"} {continue} + file delete -force -- $dir + + + } + +} + +cd hdl + +# Move main library core zips +cd library +set DEST [pwd] +puts $DEST +copy_all_packed_ips $DEST + +# Move Xilinx core zips +cd xilinx +set DEST [pwd] +copy_all_packed_ips $DEST +cd .. + +# Move jesd204 core zips +cd jesd204 +set DEST [pwd] +copy_all_packed_ips $DEST +cd .. + +# Move spi_engine core zips +cd spi_engine +set DEST [pwd] +copy_all_packed_ips $DEST + + +cd ../../.. diff --git a/CI/scripts/dockermake b/CI/scripts/dockermake new file mode 100644 index 0000000..ae4cae2 --- /dev/null +++ b/CI/scripts/dockermake @@ -0,0 +1,3 @@ +#!/bin/bash +docker build . -t matlabci -f CI/scripts/Docker +docker run --rm -e "INCLUDE_EXAMPLES=$INCLUDE_EXAMPLES" -e "BOARD=$BOARD" -e "LM_LICENSE_FILE=$LM_LICENSE_FILE" -e "XILINXD_LICENSE_FILE=$XILINXD_LICENSE_FILE" -e "MLRELEASE=$MLRELEASE" -e "HDLBRANCH=$HDLBRANCH" -v "$(pwd):/work" -v /mlhsp:/mlhspro:ro -v /usr/local/MATLAB:/usr/local/MATLAB -v /root/.matlab:/root/.matlabro:ro -v /root/.Xilinx:/root/.Xilinxro:ro -v /opt/Xilinx:/opt/Xilinx --mac-address="$ADDR" matlabci /bin/bash -c "cd /work && chmod +x CI/scripts/setupDocker.sh && ./CI/scripts/setupDocker.sh && make -C CI/scripts '$@'" diff --git a/CI/scripts/fixmake.sh b/CI/scripts/fixmake.sh new file mode 100644 index 0000000..b700fb3 --- /dev/null +++ b/CI/scripts/fixmake.sh @@ -0,0 +1,3 @@ +#grep "CC_FLAGS :=" pmufw/Makefile | grep -e "-Os" || sed -i '/-mxl-soft-mul/ s/$/ -Os -flto -ffat-lto-objects/' pmufw/Makefile +cd pmufw +make diff --git a/CI/scripts/fsbl_build_zynq.tcl b/CI/scripts/fsbl_build_zynq.tcl new file mode 100644 index 0000000..fe4867e --- /dev/null +++ b/CI/scripts/fsbl_build_zynq.tcl @@ -0,0 +1,25 @@ + + +### Calling script must generated have system_top.bit + + +set cdir [pwd] +set sdk_loc $cdir/vivado_prj.sdk + +### Copy common dependent files for ZCU102 +file mkdir $cdir/boot +file copy -force $cdir/projects/common/boot/zynq.bif $cdir/boot/zynq.bif +if {$argc == 1} { + file copy -force $cdir/projects/common/boot/[lindex $argv 0]/u-boot.elf $cdir/boot/u-boot.elf +} else { + file copy -force $cdir/projects/common/boot/u-boot.elf $cdir/boot/u-boot.elf +} + +### Copy system_top.bit into the output folder +file copy -force $cdir/projects/common/boot/fsbl.elf $cdir/boot/fsbl.elf +file copy -force $cdir/vivado_prj.runs/impl_1/system_top.bit $cdir/boot/system_top.bit + +### Build BOOT.BIN +cd $cdir/boot +exec bootgen -arch zynq -image zynq.bif -o BOOT.BIN -w +exit diff --git a/CI/scripts/fsbl_build_zynqmp.tcl b/CI/scripts/fsbl_build_zynqmp.tcl new file mode 100644 index 0000000..2759f6b --- /dev/null +++ b/CI/scripts/fsbl_build_zynqmp.tcl @@ -0,0 +1,23 @@ + + +### Calling script must generated have system_top.bit + + +set cdir [pwd] +set sdk_loc $cdir/vivado_prj.sdk + +### Copy common dependent files for ZCU102 +file mkdir $cdir/boot +file copy -force $cdir/projects/common/boot/zynqmp.bif $cdir/boot/zynqmp.bif +file copy -force $cdir/projects/common/boot/bl31.elf $cdir/boot/bl31.elf +file copy -force $cdir/projects/common/boot/pmufw.elf $cdir/boot/pmufw.elf +file copy -force $cdir/projects/common/boot/u-boot-zcu.elf $cdir/boot/u-boot-zcu.elf +file copy -force $cdir/projects/common/boot/fsbl.elf $cdir/boot/fsbl.elf + +### Copy system_top.bit into the output folder +file copy -force $cdir/vivado_prj.runs/impl_1/system_top.bit $cdir/boot/system_top.bit + +### Build BOOT.BIN +cd $cdir/boot +exec bootgen -arch zynqmp -image zynqmp.bif -o BOOT.BIN -w +exit diff --git a/CI/scripts/genTlbx.m b/CI/scripts/genTlbx.m new file mode 100644 index 0000000..3adb266 --- /dev/null +++ b/CI/scripts/genTlbx.m @@ -0,0 +1,82 @@ +function genTlbx(examples) + +if nargin==0 + examples = 0; +end + +% Lookup versioning info from adi.Version +cwd = pwd; +parts = strsplit(mfilename('fullpath'),filesep); +tbroot = strjoin(parts(1:end-3),filesep); +cd(tbroot); +v = adi.Version; +uuid = matlab.lang.internal.uuid; + +%% +cd(fileparts((mfilename('fullpath')))); +cd('../..'); +p = pwd; +cd(fileparts((mfilename('fullpath')))); + +if examples + fid = fopen('bsp.tmpl','r'); +else + fid = fopen('bsp_noexamples.tmpl','r'); +end +f=fread(fid,'*char')'; +fclose(fid); + +f = strrep(f,'__REPO-ROOT__',p); +f = strrep(f,'__VERSION__',v.Release); +f = strrep(f,'__ML-RELEASE__',v.MATLAB); +f = strrep(f,'__APP-NAME__',v.AppName); +f = strrep(f,'__EXAMPLES-DIR__',v.ExamplesDir); +f = strrep(f,'__UUID__',uuid); + +fid = fopen('../../bsp.prj','w'); +fprintf(fid,'%s',f); +fclose(fid); + +cd('../..'); +addpath(genpath(matlabshared.supportpkg.getSupportPackageRoot)); +addpath(genpath('.')); +rmpath(genpath('.')); +if examples + ps = {'doc',v.ExamplesDir}; +else + ps = {'doc'}; +end +if isprop(v,'HasHDL') && v.HasHDL + ps = [ps(:)',{'hdl'}]; +end + +% Check for deps +if ~isfolder('deps') + error('deps folder with libad9361 not available') +else + ps = [ps(:)',{'deps'}]; +end + +paths = ''; +for p = ps + pp = genpath(p{:}); + ppF = pp; + pp = pp(1:end-1); + pp = strrep(pp,':',''); + paths = [paths,['',pp,'']]; %#ok + addpath(ppF); +end +rehash +projectFile = 'bsp.prj'; +currentVersion = matlab.addons.toolbox.toolboxVersion(projectFile); +if examples + outputFile = sprintf('AnalogDevices%s_v%s',v.ToolboxName,currentVersion); +else + outputFile = sprintf('AnalogDevices%s_noexamples_v%s',v.ToolboxName,currentVersion); +end +matlab.addons.toolbox.packageToolbox(projectFile,outputFile) + +delete bsp.prj + + + diff --git a/CI/scripts/generate_ip_map.py b/CI/scripts/generate_ip_map.py new file mode 100644 index 0000000..7ae547a --- /dev/null +++ b/CI/scripts/generate_ip_map.py @@ -0,0 +1,75 @@ +import json + +board = { + "fmcomms2": { + "fpga": ["zed", "zc706", "zc702"], + "supported_rd": ["rx", "tx", "rxtx"], + "ports": [ + { + "rx": [ + { + "input": False, + "width": 1, + "name": "util_ad9361_adc_pack/fifo_wr_en", + "count": 1, + "type": "valid", + }, + { + "input": True, + "width": 1, + "name": "util_ad9361_adc_fifo/dout_valid_0", + "count": 1, + "type": "valid", + }, + { + "input": False, + "width": 16, + "name": "util_ad9361_adc_pack/fifo_wr_data_@", + "count": 4, + "type": "data", + }, + { + "input": True, + "width": 16, + "name": "util_ad9361_adc_fifo/dout_data_@", + "count": 4, + "type": "data", + }, + ], + "tx": [ + { + "input": True, + "width": 1, + "name": "util_ad9361_dac_upack/fifo_rd_valid", + "count": 1, + "type": "valid", + }, + { + "input": False, + "width": 1, + "name": "axi_ad9361_dac_fifo/din_valid_in_0", + "count": 1, + "type": "valid", + }, + { + "input": False, + "width": 16, + "name": "axi_ad9361_dac_fifo/din_data_@", + "count": 4, + "type": "data", + }, + { + "input": True, + "width": 16, + "name": "util_ad9361_dac_upack/fifo_rd_data_@", + "count": 4, + "type": "data", + }, + ], + }, + ], + } +} + +with open("sample.json", "w") as outfile: + json.dump(board, outfile, indent=4) diff --git a/CI/scripts/library/util_sync/sync_fast_to_slow/Makefile b/CI/scripts/library/util_sync/sync_fast_to_slow/Makefile new file mode 100644 index 0000000..b62342f --- /dev/null +++ b/CI/scripts/library/util_sync/sync_fast_to_slow/Makefile @@ -0,0 +1,13 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := sync_fast_to_slow + +GENERIC_DEPS += sync_fast_to_slow.v + +XILINX_DEPS += sync_fast_to_slow_ip.tcl + +include ../../scripts/library.mk diff --git a/CI/scripts/library/util_sync/sync_fast_to_slow/sync_fast_to_slow.v b/CI/scripts/library/util_sync/sync_fast_to_slow/sync_fast_to_slow.v new file mode 100644 index 0000000..d887fd6 --- /dev/null +++ b/CI/scripts/library/util_sync/sync_fast_to_slow/sync_fast_to_slow.v @@ -0,0 +1,136 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +/* + * Helper module for synchronizing bit signals from one clock domain to another. + * It uses the standard approach of 2 FF in series. + * Note, that while the module allows to synchronize multiple bits at once it is + * only able to synchronize multi-bit signals where at max one bit changes per + * clock cycle (e.g. a gray counter). + */ + +`timescale 1ns/100ps + +module sync_fast_to_slow #( + // Depth of the fifo + parameter DEPTH = 4, + // Number of bits to synchronize + parameter WIDTH = 2, + // Clock ratio between fast and slow clock + // Used to improve latency + // At a ratio of 4, the design slightly changes in favor of latency + parameter RATIO = 4 +) ( + input [WIDTH-1:0] in_data, + input in_resetn, + input in_clk, + + output reg [WIDTH-1:0] out_data, + input out_resetn, + input out_clk +); + + reg [WIDTH-1:0] fifo [DEPTH-1:0]; + + reg [DEPTH/2-1:0] rd_addr; + reg [DEPTH/2-1:0] wr_addr; + + reg cdc_sync_stage0_tick; + reg cdc_sync_stage1_tick; + reg cdc_sync_stage2_tick; + reg cdc_sync_stage3_tick; + + wire tick; + + assign tick = cdc_sync_stage2_tick ^ cdc_sync_stage3_tick; + + always @(posedge out_clk) + begin + if (out_resetn == 1'b0) + cdc_sync_stage0_tick <= 1'b0; + else + cdc_sync_stage0_tick <= ~cdc_sync_stage0_tick; + end + + always @(posedge in_clk) + begin + if (in_resetn == 1'b0) begin + cdc_sync_stage1_tick <= 1'b0; + cdc_sync_stage2_tick <= 1'b0; + cdc_sync_stage3_tick <= 1'b0; + end else begin + cdc_sync_stage1_tick <= cdc_sync_stage0_tick; + cdc_sync_stage2_tick <= cdc_sync_stage1_tick; + cdc_sync_stage3_tick <= cdc_sync_stage2_tick; + end + end + + generate if (RATIO < 4) begin + always @(posedge in_clk) + begin + if (in_resetn == 1'b0) begin + wr_addr <= 0; + end else begin + if ((tick == 1'b1) || (rd_addr == wr_addr)) begin + fifo[wr_addr] <= in_data; + wr_addr <= (wr_addr + 1) % DEPTH; + end + end + end + end else begin + always @(posedge in_clk) + begin + if (in_resetn == 1'b0) begin + wr_addr <= 1; + end else begin + if (tick == 1'b1) begin + fifo[wr_addr] <= in_data; + wr_addr <= (wr_addr + 1) % DEPTH; + end + end + end + end endgenerate + + always @(posedge out_clk) + begin + if (out_resetn == 1'b0) + rd_addr <= 0; + else + if (rd_addr != wr_addr) + rd_addr <= (rd_addr + 1) % DEPTH; + out_data <= fifo[rd_addr]; + end + +endmodule diff --git a/CI/scripts/library/util_sync/sync_fast_to_slow/sync_fast_to_slow_ip.tcl b/CI/scripts/library/util_sync/sync_fast_to_slow/sync_fast_to_slow_ip.tcl new file mode 100644 index 0000000..2426f22 --- /dev/null +++ b/CI/scripts/library/util_sync/sync_fast_to_slow/sync_fast_to_slow_ip.tcl @@ -0,0 +1,48 @@ +# *************************************************************************** +# *************************************************************************** +# Copyright 2023 (c) Analog Devices, Inc. All rights reserved. +# +# Each core or library found in this collection may have its own licensing terms. +# The user should keep this in in mind while exploring these cores. +# +# Redistribution and use in source and binary forms, +# with or without modification of this file, are permitted under the terms of either +# (at the option of the user): +# +# 1. The GNU General Public License version 2 as published by the +# Free Software Foundation, which can be found in the top level directory, or at: +# https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html +# +# OR +# +# 2. An ADI specific BSD license as noted in the top level directory, or on-line at: +# https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE +# +# *************************************************************************** +# *************************************************************************** + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create sync_fast_to_slow +adi_ip_files sync_fast_to_slow [list \ + "sync_fast_to_slow.v" ] + +adi_ip_properties_lite sync_fast_to_slow + +set cc [ipx::current_core] + +foreach {k v} { \ + "DEPTH" "FIFO Depth" \ + "WIDTH" "Data Width" \ + "RATIO" "Fast and slow clock ratio" \ + } { \ + set p [ipgui::get_guiparamspec -name $k -component $cc] +# ipgui::move_param -component $cc -order $i $p -parent $ + set_property -dict [list \ + DISPLAY_NAME $v \ + ] $p + incr i +} + +ipx::save_core [ipx::current_core] diff --git a/CI/scripts/library/util_sync/sync_slow_to_fast/Makefile b/CI/scripts/library/util_sync/sync_slow_to_fast/Makefile new file mode 100644 index 0000000..d0fbe4f --- /dev/null +++ b/CI/scripts/library/util_sync/sync_slow_to_fast/Makefile @@ -0,0 +1,13 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := sync_slow_to_fast + +GENERIC_DEPS += sync_slow_to_fast.v + +XILINX_DEPS += sync_slow_to_fast_ip.tcl + +include ../../scripts/library.mk diff --git a/CI/scripts/library/util_sync/sync_slow_to_fast/sync_slow_to_fast.v b/CI/scripts/library/util_sync/sync_slow_to_fast/sync_slow_to_fast.v new file mode 100644 index 0000000..3d701c5 --- /dev/null +++ b/CI/scripts/library/util_sync/sync_slow_to_fast/sync_slow_to_fast.v @@ -0,0 +1,128 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +/* + * Helper module for synchronizing bit signals from one clock domain to another. + * It uses the standard approach of 2 FF in series. + * Note, that while the module allows to synchronize multiple bits at once it is + * only able to synchronize multi-bit signals where at max one bit changes per + * clock cycle (e.g. a gray counter). + */ + +`timescale 1ns/100ps + +module sync_slow_to_fast #( + // Depth of the fifo + parameter DEPTH = 4, + // Number of bits to synchronize + parameter WIDTH = 2, + parameter CONTINUOUS = 1 +) ( + input [WIDTH-1:0] in_data, + input in_resetn, + input in_clk, + input in_tick, + + output reg [WIDTH-1:0] out_data, + input out_resetn, + input out_clk, + output out_tick +); + + reg [WIDTH-1:0] fifo [DEPTH-1:0]; + + reg [DEPTH/2-1:0] rd_addr; + reg [DEPTH/2-1:0] wr_addr; + + reg cdc_sync_stage0_tick; + reg cdc_sync_stage1_tick; + reg cdc_sync_stage2_tick; + reg cdc_sync_stage3_tick; + + wire tick; + + assign tick = cdc_sync_stage2_tick ^ cdc_sync_stage3_tick; + assign out_tick = tick; + + always @(posedge in_clk) + begin + if (in_resetn == 1'b0) + cdc_sync_stage0_tick <= 1'b0; + else + if (in_tick == 1'b1) + cdc_sync_stage0_tick <= ~cdc_sync_stage0_tick; + end + + always @(posedge out_clk) + begin + if (out_resetn == 1'b0) begin + cdc_sync_stage1_tick <= 1'b0; + cdc_sync_stage2_tick <= 1'b0; + cdc_sync_stage3_tick <= 1'b0; + end else begin + cdc_sync_stage1_tick <= cdc_sync_stage0_tick; + cdc_sync_stage2_tick <= cdc_sync_stage1_tick; + cdc_sync_stage3_tick <= cdc_sync_stage2_tick; + end + end + + always @(posedge in_clk) + begin + if (in_resetn == 1'b0) + wr_addr <= 0; + else + if (in_tick == 1'b1) begin + fifo[wr_addr] <= in_data; + wr_addr <= (wr_addr + 1) % DEPTH; + end + end + + always @(posedge out_clk) + begin + if (out_resetn == 1'b0) + rd_addr <= 0; + else + if (tick == 1'b1) begin + rd_addr <= (rd_addr + 1) % DEPTH; + end + end + + always @(posedge out_clk) + begin + if (tick == 1'b1) + out_data <= fifo[rd_addr]; + end + +endmodule diff --git a/CI/scripts/library/util_sync/sync_slow_to_fast/sync_slow_to_fast_ip.tcl b/CI/scripts/library/util_sync/sync_slow_to_fast/sync_slow_to_fast_ip.tcl new file mode 100644 index 0000000..f7da94d --- /dev/null +++ b/CI/scripts/library/util_sync/sync_slow_to_fast/sync_slow_to_fast_ip.tcl @@ -0,0 +1,57 @@ +# *************************************************************************** +# *************************************************************************** +# Copyright 2023 (c) Analog Devices, Inc. All rights reserved. +# +# Each core or library found in this collection may have its own licensing terms. +# The user should keep this in in mind while exploring these cores. +# +# Redistribution and use in source and binary forms, +# with or without modification of this file, are permitted under the terms of either +# (at the option of the user): +# +# 1. The GNU General Public License version 2 as published by the +# Free Software Foundation, which can be found in the top level directory, or at: +# https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html +# +# OR +# +# 2. An ADI specific BSD license as noted in the top level directory, or on-line at: +# https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE +# +# *************************************************************************** +# *************************************************************************** + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create sync_slow_to_fast +adi_ip_files sync_slow_to_fast [list \ + "sync_slow_to_fast.v" ] + +adi_ip_properties_lite sync_slow_to_fast + +set cc [ipx::current_core] + +foreach {k v} { \ + "DEPTH" "FIFO Depth" \ + "WIDTH" "Data Width" \ + "CONTINUOUS" "Continuous mode" \ + } { \ + set p [ipgui::get_guiparamspec -name $k -component $cc] +# ipgui::move_param -component $cc -order $i $p -parent $ + set_property -dict [list \ + DISPLAY_NAME $v \ + ] $p + incr i +} + +set_property widget {checkBox} [ipgui::get_guiparamspec -name "CONTINUOUS" -component $cc ] +set_property value true [ipx::get_user_parameters CONTINUOUS -of_objects $cc] +set_property value true [ipx::get_hdl_parameters CONTINUOUS -of_objects $cc] +set_property value_format bool [ipx::get_user_parameters CONTINUOUS -of_objects $cc] +set_property value_format bool [ipx::get_hdl_parameters CONTINUOUS -of_objects $cc] + +set_property enablement_dependency {spirit:decode(id('PARAM_VALUE.CONTINUOUS')) == false} [ipx::get_ports *_tick -of_objects $cc] +set_property driver_value 1 [ipx::get_ports in_tick -of_objects $cc] + +ipx::save_core $cc diff --git a/CI/scripts/library/util_sync/util_delay/Makefile b/CI/scripts/library/util_sync/util_delay/Makefile new file mode 100644 index 0000000..a3eea52 --- /dev/null +++ b/CI/scripts/library/util_sync/util_delay/Makefile @@ -0,0 +1,13 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_delay + +GENERIC_DEPS += util_delay.v + +XILINX_DEPS += util_delay_ip.tcl + +include ../../scripts/library.mk diff --git a/CI/scripts/library/util_sync/util_delay/util_delay.v b/CI/scripts/library/util_sync/util_delay/util_delay.v new file mode 100644 index 0000000..7fe813f --- /dev/null +++ b/CI/scripts/library/util_sync/util_delay/util_delay.v @@ -0,0 +1,76 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 202323232323232323232323232323232323232323232323 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module util_delay #( + + parameter DATA_WIDTH = 8, + // the minimum valid value for DELAY_CYCLES is 1 + parameter DELAY_CYCLES = 3 +) ( + input clk, + input rstn, + input [DATA_WIDTH-1:0] din, + output [DATA_WIDTH-1:0] dout +); + + reg [DATA_WIDTH-1:0] dbuf[0:(DELAY_CYCLES-1)]; + + always @(posedge clk) begin + //if (rstn == 0) begin + if (rstn == 0) begin + dbuf[0] <= 0; + end else begin + dbuf[0] <= din; + end + end + + generate + genvar i; + for (i = 1; i < DELAY_CYCLES; i=i+1) begin:register_pipe + always @(posedge clk) begin + if (rstn == 0) begin + dbuf[i] <= 0; + end else begin + dbuf[i] <= dbuf[i-1]; + end + end + end + endgenerate + + assign dout = dbuf[(DELAY_CYCLES-1)]; + +endmodule diff --git a/CI/scripts/library/util_sync/util_delay/util_delay_ip.tcl b/CI/scripts/library/util_sync/util_delay/util_delay_ip.tcl new file mode 100644 index 0000000..a9c1d5c --- /dev/null +++ b/CI/scripts/library/util_sync/util_delay/util_delay_ip.tcl @@ -0,0 +1,47 @@ +# *************************************************************************** +# *************************************************************************** +# Copyright 2023 (c) Analog Devices, Inc. All rights reserved. +# +# Each core or library found in this collection may have its own licensing terms. +# The user should keep this in in mind while exploring these cores. +# +# Redistribution and use in source and binary forms, +# with or without modification of this file, are permitted under the terms of either +# (at the option of the user): +# +# 1. The GNU General Public License version 2 as published by the +# Free Software Foundation, which can be found in the top level directory, or at: +# https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html +# +# OR +# +# 2. An ADI specific BSD license as noted in the top level directory, or on-line at: +# https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE +# +# *************************************************************************** +# *************************************************************************** + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create util_delay +adi_ip_files util_delay [list \ + "util_delay.v" ] + +adi_ip_properties_lite util_delay + +set cc [ipx::current_core] + +foreach {k v} { \ + "DELAY_CYCLES" "Delay Cycles" \ + "DATA_WIDTH" "Data Width" \ + } { \ + set p [ipgui::get_guiparamspec -name $k -component $cc] +# ipgui::move_param -component $cc -order $i $p -parent $ + set_property -dict [list \ + DISPLAY_NAME $v \ + ] $p + incr i +} + +ipx::save_core [ipx::current_core] diff --git a/CI/scripts/linter.m b/CI/scripts/linter.m new file mode 100644 index 0000000..3eb7fcf --- /dev/null +++ b/CI/scripts/linter.m @@ -0,0 +1,23 @@ +clc; +ignoreFolders = {'CI','doc','test'}; +cd ../.. +d = pwd; +cd .. +addpath(genpath(d)); +cd(d); + +files = dir('**/*.m'); +for file = 1:length(files) + if contains(files(file).folder,ignoreFolders) + continue; + end + mfile = fullfile(files(file).folder,files(file).name); + rpt = mlint(mfile); + if ~isempty(rpt) + disp(mfile); + for l = 1:length(rpt) + disp([num2str(rpt(l).line) ': ' rpt(l).message]); + end + end +end + diff --git a/CI/scripts/matlab_processors.tcl b/CI/scripts/matlab_processors.tcl new file mode 100644 index 0000000..2676efd --- /dev/null +++ b/CI/scripts/matlab_processors.tcl @@ -0,0 +1,866 @@ +proc connect_interfaces {rxtx hierarchy shift_register synchronizer number_of_inputs number_of_valids number_of_bits delay multiple} { + set number_of_inputs_total [expr $number_of_inputs + $number_of_valids] + set number_of_bits_total [expr $number_of_inputs*$number_of_bits + $number_of_valids] + + set version ":1.0" + + create_bd_cell -type ip -vlnv analog.com:user:$synchronizer$version $hierarchy/${synchronizer} + set_property -dict [list CONFIG.DEPTH {6}] [get_bd_cells $hierarchy/${synchronizer}] + set_property CONFIG.WIDTH $number_of_bits_total [get_bd_cells $hierarchy/${synchronizer}] + if {$multiple != 1} { + set_property CONFIG.RATIO $multiple [get_bd_cells $hierarchy/${synchronizer}] + } + + create_bd_cell -type ip -vlnv analog.com:user:$shift_register$version $hierarchy/${shift_register} + set_property CONFIG.DATA_WIDTH $number_of_bits_total [get_bd_cells $hierarchy/${shift_register}] + set_property CONFIG.DELAY_CYCLES $delay [get_bd_cells $hierarchy/${shift_register}] + + create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 $hierarchy/bit_concatenator_sync + set_property CONFIG.NUM_PORTS $number_of_inputs_total [get_bd_cells $hierarchy/bit_concatenator_sync] + + ad_connect $hierarchy/${synchronizer}/in_data $hierarchy/bit_concatenator_sync/dout + + create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 $hierarchy/bit_concatenator_shifter + set_property CONFIG.NUM_PORTS $number_of_inputs_total [get_bd_cells $hierarchy/bit_concatenator_shifter] + + ad_connect $hierarchy/${shift_register}/din $hierarchy/bit_concatenator_shifter/dout + + # data priority / faster data + if {$rxtx == "rxtx"} { + # clocking + ad_connect $hierarchy/${shift_register}/clk $hierarchy/rx_clk + + # reset + ad_connect $hierarchy/${shift_register}/rstn $hierarchy/rx_rstn + } else { + # clocking + ad_connect $hierarchy/${shift_register}/clk $hierarchy/tx_clk + + # reset + ad_connect $hierarchy/${shift_register}/rstn $hierarchy/tx_rstn + } + + set i 0 + for {} {$i < $number_of_inputs} {incr i} { + create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 $hierarchy/bit_slicer_rx_${i} + set_property -dict [list CONFIG.DIN_TO [expr int($i*$number_of_bits)] CONFIG.DIN_FROM [expr int(($i+1)*$number_of_bits-1)] CONFIG.DIN_WIDTH [expr int($number_of_bits_total)]] [get_bd_cells $hierarchy/bit_slicer_rx_${i}] + + create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 $hierarchy/bit_slicer_tx_${i} + set_property -dict [list CONFIG.DIN_TO [expr int($i*$number_of_bits)] CONFIG.DIN_FROM [expr int(($i+1)*$number_of_bits-1)] CONFIG.DIN_WIDTH [ expr int($number_of_bits_total)]] [get_bd_cells $hierarchy/bit_slicer_tx_${i}] + + set_property CONFIG.IN${i}_WIDTH.VALUE_SRC USER [get_bd_cells $hierarchy/bit_concatenator_sync] + set_property CONFIG.IN${i}_WIDTH $number_of_bits [get_bd_cells $hierarchy/bit_concatenator_sync] + + set_property CONFIG.IN${i}_WIDTH.VALUE_SRC USER [get_bd_cells $hierarchy/bit_concatenator_shifter] + set_property CONFIG.IN${i}_WIDTH $number_of_bits [get_bd_cells $hierarchy/bit_concatenator_shifter] + + # data priority / faster data + if {$rxtx == "rxtx"} { + # data + ad_connect $hierarchy/${synchronizer}/out_data $hierarchy/bit_slicer_tx_${i}/Din + ad_connect $hierarchy/bit_concatenator_sync/In${i} $hierarchy/data_in_tx_${i} + ad_connect $hierarchy/bit_slicer_tx_${i}/Dout $hierarchy/data_out_tx_${i} + + ad_connect $hierarchy/${shift_register}/dout $hierarchy/bit_slicer_rx_${i}/Din + ad_connect $hierarchy/bit_concatenator_shifter/In${i} $hierarchy/data_in_rx_${i} + ad_connect $hierarchy/bit_slicer_rx_${i}/Dout $hierarchy/data_out_rx_${i} + } else { + # data + ad_connect $hierarchy/${synchronizer}/out_data $hierarchy/bit_slicer_rx_${i}/Din + ad_connect $hierarchy/bit_concatenator_sync/In${i} $hierarchy/data_in_rx_${i} + ad_connect $hierarchy/bit_slicer_rx_${i}/Dout $hierarchy/data_out_rx_${i} + + ad_connect $hierarchy/${shift_register}/dout $hierarchy/bit_slicer_tx_${i}/Din + ad_connect $hierarchy/bit_concatenator_shifter/In${i} $hierarchy/data_in_tx_${i} + ad_connect $hierarchy/bit_slicer_tx_${i}/Dout $hierarchy/data_out_tx_${i} + } + } + + for {set j 0} {$i < $number_of_inputs+$number_of_valids} {incr i} { + create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 $hierarchy/bit_slicer_valid_rx_${j} + set_property -dict [list CONFIG.DIN_TO [expr int($number_of_inputs*$number_of_bits+$i-$number_of_inputs)] CONFIG.DIN_FROM [expr int($number_of_inputs*$number_of_bits+$i-$number_of_inputs)] CONFIG.DIN_WIDTH [expr int($number_of_bits_total)]] [get_bd_cells $hierarchy/bit_slicer_valid_rx_${j}] + + create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 $hierarchy/bit_slicer_valid_tx_${j} + set_property -dict [list CONFIG.DIN_TO [expr int($number_of_inputs*$number_of_bits+$i-$number_of_inputs)] CONFIG.DIN_FROM [expr int($number_of_inputs*$number_of_bits+$i-$number_of_inputs)] CONFIG.DIN_WIDTH [expr int($number_of_bits_total)]] [get_bd_cells $hierarchy/bit_slicer_valid_tx_${j}] + + set_property CONFIG.IN${i}_WIDTH.VALUE_SRC USER [get_bd_cells $hierarchy/bit_concatenator_sync] + set_property CONFIG.IN${i}_WIDTH {1} [get_bd_cells $hierarchy/bit_concatenator_sync] + + set_property CONFIG.IN${i}_WIDTH.VALUE_SRC USER [get_bd_cells $hierarchy/bit_concatenator_shifter] + set_property CONFIG.IN${i}_WIDTH {1} [get_bd_cells $hierarchy/bit_concatenator_shifter] + + # data priority / faster data + if {$rxtx == "rxtx"} { + # data + ad_connect $hierarchy/${synchronizer}/out_data $hierarchy/bit_slicer_valid_tx_${j}/Din + ad_connect $hierarchy/bit_concatenator_sync/In${i} $hierarchy/data_valid_in_tx_${j} + ad_connect $hierarchy/bit_slicer_valid_tx_${j}/Dout $hierarchy/data_valid_out_tx_${j} + + ad_connect $hierarchy/${shift_register}/dout $hierarchy/bit_slicer_valid_rx_${j}/Din + ad_connect $hierarchy/bit_concatenator_shifter/In${i} $hierarchy/data_valid_in_rx_${j} + ad_connect $hierarchy/bit_slicer_valid_rx_${j}/Dout $hierarchy/data_valid_out_rx_${j} + } else { + # data + ad_connect $hierarchy/${synchronizer}/out_data $hierarchy/bit_slicer_valid_rx_${j}/Din + ad_connect $hierarchy/bit_concatenator_sync/In${i} $hierarchy/data_valid_in_rx_${j} + ad_connect $hierarchy/bit_slicer_valid_rx_${j}/Dout $hierarchy/data_valid_out_rx_${j} + + ad_connect $hierarchy/${shift_register}/dout $hierarchy/bit_slicer_valid_tx_${j}/Din + ad_connect $hierarchy/bit_concatenator_shifter/In${i} $hierarchy/data_valid_in_tx_${j} + ad_connect $hierarchy/bit_slicer_valid_tx_${j}/Dout $hierarchy/data_valid_out_tx_${j} + } + + incr j + } +} + +proc data_synchronizer {rxtx number_of_inputs number_of_bits number_of_valids multiple} { + set hierarchy sync_input + + create_bd_cell -type hier $hierarchy + + set hierarchy sync_output + + create_bd_cell -type hier $hierarchy + + if {$rxtx != "tx"} { + set hierarchy sync_input + + create_bd_pin -dir I $hierarchy/rx_clk + create_bd_pin -dir I $hierarchy/rx_rstn + + for {set i 0} {$i < $number_of_inputs} {incr i} { + create_bd_pin -dir I -from [expr $number_of_bits-1] -to 0 $hierarchy/data_in_rx_${i} + create_bd_pin -dir O -from [expr $number_of_bits-1] -to 0 $hierarchy/data_out_rx_${i} + } + + for {set i 0} {$i < $number_of_valids} {incr i} { + create_bd_pin -dir I $hierarchy/data_valid_in_rx_${i} + create_bd_pin -dir O $hierarchy/data_valid_out_rx_${i} + } + + set hierarchy sync_output + + create_bd_pin -dir I $hierarchy/rx_clk + create_bd_pin -dir I $hierarchy/rx_rstn + + for {set i 0} {$i < $number_of_inputs} {incr i} { + create_bd_pin -dir I -from [expr $number_of_bits-1] -to 0 $hierarchy/data_in_rx_${i} + create_bd_pin -dir O -from [expr $number_of_bits-1] -to 0 $hierarchy/data_out_rx_${i} + } + + for {set i 0} {$i < $number_of_valids} {incr i} { + create_bd_pin -dir I $hierarchy/data_valid_in_rx_${i} + create_bd_pin -dir O $hierarchy/data_valid_out_rx_${i} + } + } + if {$rxtx != "rx"} { + set hierarchy sync_input + + create_bd_pin -dir I $hierarchy/tx_clk + create_bd_pin -dir I $hierarchy/tx_rstn + + for {set i 0} {$i < $number_of_inputs} {incr i} { + create_bd_pin -dir I -from [expr $number_of_bits-1] -to 0 $hierarchy/data_in_tx_${i} + create_bd_pin -dir O -from [expr $number_of_bits-1] -to 0 $hierarchy/data_out_tx_${i} + } + + for {set i 0} {$i < $number_of_valids} {incr i} { + create_bd_pin -dir I $hierarchy/data_valid_in_tx_${i} + create_bd_pin -dir O $hierarchy/data_valid_out_tx_${i} + } + + set hierarchy sync_output + + create_bd_pin -dir I $hierarchy/tx_clk + create_bd_pin -dir I $hierarchy/tx_rstn + + for {set i 0} {$i < $number_of_inputs} {incr i} { + create_bd_pin -dir I -from [expr $number_of_bits-1] -to 0 $hierarchy/data_in_tx_${i} + create_bd_pin -dir O -from [expr $number_of_bits-1] -to 0 $hierarchy/data_out_tx_${i} + } + + for {set i 0} {$i < $number_of_valids} {incr i} { + create_bd_pin -dir I $hierarchy/data_valid_in_tx_${i} + create_bd_pin -dir O $hierarchy/data_valid_out_tx_${i} + } + } + if {$rxtx == "rx"} { + set hierarchy sync_input + + for {set i 0} {$i < $number_of_inputs} {incr i} { + ad_connect $hierarchy/data_in_rx_${i} $hierarchy/data_out_rx_${i} + } + + for {set i 0} {$i < $number_of_valids} {incr i} { + ad_connect $hierarchy/data_valid_in_rx_${i} $hierarchy/data_valid_out_rx_${i} + } + + set hierarchy sync_output + + for {set i 0} {$i < $number_of_inputs} {incr i} { + ad_connect $hierarchy/data_in_rx_${i} $hierarchy/data_out_rx_${i} + } + + for {set i 0} {$i < $number_of_valids} {incr i} { + ad_connect $hierarchy/data_valid_in_rx_${i} $hierarchy/data_valid_out_rx_${i} + } + } + if {$rxtx == "tx"} { + set hierarchy sync_input + + for {set i 0} {$i < $number_of_inputs} {incr i} { + ad_connect $hierarchy/data_in_tx_${i} $hierarchy/data_out_tx_${i} + } + + for {set i 0} {$i < $number_of_valids} {incr i} { + ad_connect $hierarchy/data_valid_in_tx_${i} $hierarchy/data_valid_out_tx_${i} + } + + set hierarchy sync_output + + for {set i 0} {$i < $number_of_inputs} {incr i} { + ad_connect $hierarchy/data_in_tx_${i} $hierarchy/data_out_tx_${i} + } + + for {set i 0} {$i < $number_of_valids} {incr i} { + ad_connect $hierarchy/data_valid_in_tx_${i} $hierarchy/data_valid_out_tx_${i} + } + } + if {$rxtx == "rxtx" || $rxtx == "txrx"} { + # build synchronizer IPs + #exec cp ../../../../../hdl/vendor/AnalogDevices/vivado/quiet.mk ../../../. + #exec make -C ../../../library/util_sync/sync_delay + #exec make -C ../../../library/util_sync/sync_fast_to_slow + #exec make -C ../../../library/util_sync/sync_slow_to_fast + update_ip_catalog -rebuild + + ### synchronize the input + + set hierarchy sync_input + + set shift_register util_delay + + set synchronizer sync_slow_to_fast + + set delay [expr {$multiple+3}] + + #create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 $hierarchy/VCC + #set_property -dict [list CONFIG.CONST_VAL {1}] [get_bd_cells $hierarchy/VCC] + + connect_interfaces $rxtx $hierarchy $shift_register $synchronizer $number_of_inputs $number_of_valids $number_of_bits $delay 1 + + #ad_connect $hierarchy/${synchronizer}/in_tick $hierarchy/VCC/dout + + # data priority / faster data + if {$rxtx == "rxtx"} { + # clocking + ad_connect $hierarchy/${synchronizer}/in_clk $hierarchy/tx_clk + ad_connect $hierarchy/${synchronizer}/out_clk $hierarchy/rx_clk + + # reset + ad_connect $hierarchy/${synchronizer}/in_resetn $hierarchy/tx_rstn + ad_connect $hierarchy/${synchronizer}/out_resetn $hierarchy/rx_rstn + } else { + # clocking + ad_connect $hierarchy/${synchronizer}/in_clk $hierarchy/rx_clk + ad_connect $hierarchy/${synchronizer}/out_clk $hierarchy/tx_clk + + # reset + ad_connect $hierarchy/${synchronizer}/in_resetn $hierarchy/rx_rstn + ad_connect $hierarchy/${synchronizer}/out_resetn $hierarchy/tx_rstn + } + + ### synchronize the output + + set hierarchy sync_output + + if {$multiple==1} { + #create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 $hierarchy/VCC + #set_property -dict [list CONFIG.CONST_VAL {1}] [get_bd_cells $hierarchy/VCC] + } else { + set synchronizer sync_fast_to_slow + + if {$multiple>3} { + set delay [expr {$multiple-2}] + } else { + set delay [expr {($multiple-1)*2}] + } + } + + connect_interfaces $rxtx $hierarchy $shift_register $synchronizer $number_of_inputs $number_of_valids $number_of_bits $delay $multiple + + #if {$multiple==1} { + #ad_connect $hierarchy/${synchronizer}/in_tick $hierarchy/VCC/dout + #} + + # data priority / faster data + if {$rxtx == "rxtx"} { + # clocking + ad_connect $hierarchy/${synchronizer}/in_clk $hierarchy/rx_clk + ad_connect $hierarchy/${synchronizer}/out_clk $hierarchy/tx_clk + + # reset + ad_connect $hierarchy/${synchronizer}/in_resetn $hierarchy/rx_rstn + ad_connect $hierarchy/${synchronizer}/out_resetn $hierarchy/tx_rstn + } else { + # clocking + ad_connect $hierarchy/${synchronizer}/in_clk $hierarchy/tx_clk + ad_connect $hierarchy/${synchronizer}/out_clk $hierarchy/rx_clk + + # reset + ad_connect $hierarchy/${synchronizer}/in_resetn $hierarchy/tx_rstn + ad_connect $hierarchy/${synchronizer}/out_resetn $hierarchy/rx_rstn + } + } +} + +proc preprocess_bd {project carrier rxtx number_of_inputs number_of_bits number_of_valids multiple} { + + puts "Preprocessing $project $carrier $rxtx" + + switch $project { + adrv9361z7035 { + if {$rxtx == "rx" || $rxtx == "rxtx"} { + # Disconnect the ADC PACK pins + delete_bd_objs [get_bd_nets util_ad9361_adc_fifo_dout_data_0] + delete_bd_objs [get_bd_nets util_ad9361_adc_fifo_dout_data_1] + delete_bd_objs [get_bd_nets util_ad9361_adc_fifo_dout_data_2] + delete_bd_objs [get_bd_nets util_ad9361_adc_fifo_dout_data_3] + delete_bd_objs [get_bd_nets util_ad9361_adc_fifo_dout_valid_0] + + global dma_config + # Configure DMA + if {[info exists dma_config]} { + if {$dma_config eq "Packetized"} { + set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {256} CONFIG.DMA_TYPE_SRC {1} CONFIG.MAX_BYTES_PER_BURST {32768}] [get_bd_cells axi_ad9361_adc_dma] + connect_bd_net [get_bd_pins axi_ad9361_adc_dma/s_axis_aclk] [get_bd_pins util_ad9361_divclk/clk_out] + connect_bd_net [get_bd_pins util_ad9361_adc_pack/packed_fifo_wr_data] [get_bd_pins axi_ad9361_adc_dma/s_axis_data] + connect_bd_net [get_bd_pins axi_ad9361_adc_dma/s_axis_valid] [get_bd_pins util_ad9361_adc_pack/packed_fifo_wr_en] + } + } + } + if {$rxtx == "tx" || $rxtx == "rxtx"} { + # Disconnect the DAC UNPACK pins + delete_bd_objs [get_bd_nets util_ad9361_dac_upack_fifo_rd_data_0] + delete_bd_objs [get_bd_nets util_ad9361_dac_upack_fifo_rd_data_1] + delete_bd_objs [get_bd_nets util_ad9361_dac_upack_fifo_rd_data_2] + delete_bd_objs [get_bd_nets util_ad9361_dac_upack_fifo_rd_data_3] + delete_bd_objs [get_bd_nets util_ad9361_dac_upack_fifo_rd_valid] + + # Connect fifo valids together + connect_bd_net [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_1] [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_0] + connect_bd_net [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_2] [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_0] + connect_bd_net [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_3] [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_0] + + # Remove data lines where IP will go + delete_bd_objs [get_bd_nets util_ad9361_dac_upack_dac_data_0] + delete_bd_objs [get_bd_nets util_ad9361_dac_upack_dac_data_1] + delete_bd_objs [get_bd_nets util_ad9361_dac_upack_dac_data_2] + delete_bd_objs [get_bd_nets util_ad9361_dac_upack_dac_data_3] + } + switch $carrier { + ccbob_cmos { + # Add 1 extra AXI master ports to the interconnect + set_property -dict [list CONFIG.NUM_MI {8}] [get_bd_cells axi_cpu_interconnect] + connect_bd_net -net [get_bd_nets util_ad9361_divclk_clk_out] [get_bd_pins axi_cpu_interconnect/M07_ACLK] [get_bd_pins util_ad9361_divclk/clk_out] + connect_bd_net [get_bd_pins util_ad9361_divclk_reset/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M07_ARESETN] + } + ccbob_lvds { + # Add 1 extra AXI master ports to the interconnect + set_property -dict [list CONFIG.NUM_MI {8}] [get_bd_cells axi_cpu_interconnect] + connect_bd_net -net [get_bd_nets util_ad9361_divclk_clk_out] [get_bd_pins axi_cpu_interconnect/M07_ACLK] [get_bd_pins util_ad9361_divclk/clk_out] + connect_bd_net [get_bd_pins util_ad9361_divclk_reset/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M07_ARESETN] + } + ccbox_lvds { + # Add 1 extra AXI master ports to the interconnect + set_property -dict [list CONFIG.NUM_MI {6}] [get_bd_cells axi_cpu_interconnect] + connect_bd_net -net [get_bd_nets util_ad9361_divclk_clk_out] [get_bd_pins axi_cpu_interconnect/M05_ACLK] [get_bd_pins util_ad9361_divclk/clk_out] + connect_bd_net [get_bd_pins util_ad9361_divclk_reset/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M05_ARESETN] + } + ccfmc_lvds { + # Add 1 extra AXI master ports to the interconnect + set_property -dict [list CONFIG.NUM_MI {13}] [get_bd_cells axi_cpu_interconnect] + connect_bd_net -net [get_bd_nets util_ad9361_divclk_clk_out] [get_bd_pins axi_cpu_interconnect/M12_ACLK] [get_bd_pins util_ad9361_divclk/clk_out] + connect_bd_net [get_bd_pins util_ad9361_divclk_reset/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M12_ARESETN] + } + ccpackrf_lvds { + # Add 1 extra AXI master ports to the interconnect + set_property -dict [list CONFIG.NUM_MI {7}] [get_bd_cells axi_cpu_interconnect] + connect_bd_net -net [get_bd_nets util_ad9361_divclk_clk_out] [get_bd_pins axi_cpu_interconnect/M06_ACLK] [get_bd_pins util_ad9361_divclk/clk_out] + connect_bd_net [get_bd_pins util_ad9361_divclk_reset/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M06_ARESETN] + } + } + } + adrv9364z7020 { + if {$rxtx == "rx" || $rxtx == "rxtx"} { + # Disconnect the ADC PACK pins + delete_bd_objs [get_bd_nets util_ad9361_adc_fifo_dout_data_0] + delete_bd_objs [get_bd_nets util_ad9361_adc_fifo_dout_data_1] + delete_bd_objs [get_bd_nets util_ad9361_adc_fifo_dout_data_2] + delete_bd_objs [get_bd_nets util_ad9361_adc_fifo_dout_data_3] + delete_bd_objs [get_bd_nets util_ad9361_adc_fifo_dout_valid_0] + } + if {$rxtx == "tx" || $rxtx == "rxtx"} { + # Disconnect the DAC PACK pins + delete_bd_objs [get_bd_nets util_ad9361_dac_upack_fifo_rd_data_0] + delete_bd_objs [get_bd_nets util_ad9361_dac_upack_fifo_rd_data_1] + delete_bd_objs [get_bd_nets util_ad9361_dac_upack_fifo_rd_data_2] + delete_bd_objs [get_bd_nets util_ad9361_dac_upack_fifo_rd_data_3] + delete_bd_objs [get_bd_nets util_ad9361_dac_upack_fifo_rd_valid] + + # Connect fifo valids together + connect_bd_net [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_1] [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_0] + connect_bd_net [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_2] [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_0] + connect_bd_net [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_3] [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_0] + } + switch $carrier { + ccbob_cmos { + # Add 1 extra AXI master ports to the interconnect + set_property -dict [list CONFIG.NUM_MI {7}] [get_bd_cells axi_cpu_interconnect] + connect_bd_net -net [get_bd_nets util_ad9361_divclk_clk_out] [get_bd_pins axi_cpu_interconnect/M06_ACLK] [get_bd_pins util_ad9361_divclk/clk_out] + connect_bd_net [get_bd_pins util_ad9361_divclk_reset/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M06_ARESETN] + } + ccbob_lvds { + # Add 1 extra AXI master ports to the interconnect + set_property -dict [list CONFIG.NUM_MI {7}] [get_bd_cells axi_cpu_interconnect] + connect_bd_net -net [get_bd_nets util_ad9361_divclk_clk_out] [get_bd_pins axi_cpu_interconnect/M06_ACLK] [get_bd_pins util_ad9361_divclk/clk_out] + connect_bd_net [get_bd_pins util_ad9361_divclk_reset/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M06_ARESETN] + } + ccbox_lvds { + # Add 1 extra AXI master ports to the interconnect + set_property -dict [list CONFIG.NUM_MI {7}] [get_bd_cells axi_cpu_interconnect] + connect_bd_net -net [get_bd_nets util_ad9361_divclk_clk_out] [get_bd_pins axi_cpu_interconnect/M06_ACLK] [get_bd_pins util_ad9361_divclk/clk_out] + connect_bd_net [get_bd_pins util_ad9361_divclk_reset/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M06_ARESETN] + } + } + } + fmcomms2 { + if {$rxtx == "rx" || $rxtx == "rxtx"} { + # Disconnect the ADC PACK pins + delete_bd_objs [get_bd_nets util_ad9361_adc_fifo_dout_valid_0] + + delete_bd_objs [get_bd_nets util_ad9361_adc_fifo_dout_data_0] + delete_bd_objs [get_bd_nets util_ad9361_adc_fifo_dout_data_1] + delete_bd_objs [get_bd_nets util_ad9361_adc_fifo_dout_data_2] + delete_bd_objs [get_bd_nets util_ad9361_adc_fifo_dout_data_3] + } + if {$rxtx == "tx" || $rxtx == "rxtx"} { + # Disconnect the DAC UNPACK pins + delete_bd_objs [get_bd_nets util_ad9361_dac_upack_fifo_rd_valid] + + # Connect fifo valids together + connect_bd_net [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_1] [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_0] + connect_bd_net [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_2] [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_0] + connect_bd_net [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_3] [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_0] + + # Remove data lines where IP will go + delete_bd_objs [get_bd_nets util_ad9361_dac_upack_fifo_rd_data_0] + delete_bd_objs [get_bd_nets util_ad9361_dac_upack_fifo_rd_data_1] + delete_bd_objs [get_bd_nets util_ad9361_dac_upack_fifo_rd_data_2] + delete_bd_objs [get_bd_nets util_ad9361_dac_upack_fifo_rd_data_3] + } + switch $carrier { + zed { + # Add 1 extra AXI master ports to the interconnect + set_property -dict [list CONFIG.NUM_MI {12}] [get_bd_cells axi_cpu_interconnect] + connect_bd_net -net [get_bd_nets util_ad9361_divclk_clk_out] [get_bd_pins axi_cpu_interconnect/M11_ACLK] [get_bd_pins util_ad9361_divclk/clk_out] + connect_bd_net [get_bd_pins util_ad9361_divclk_reset/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M11_ARESETN] + } + zc702 { + # Add 1 extra AXI master ports to the interconnect + set_property -dict [list CONFIG.NUM_MI {10}] [get_bd_cells axi_cpu_interconnect] + connect_bd_net -net [get_bd_nets util_ad9361_divclk_clk_out] [get_bd_pins axi_cpu_interconnect/M09_ACLK] [get_bd_pins util_ad9361_divclk/clk_out] + connect_bd_net [get_bd_pins util_ad9361_divclk_reset/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M09_ARESETN] + } + zc706 { + # Add 1 extra AXI master ports to the interconnect + set_property -dict [list CONFIG.NUM_MI {10}] [get_bd_cells axi_cpu_interconnect] + connect_bd_net -net [get_bd_nets util_ad9361_divclk_clk_out] [get_bd_pins axi_cpu_interconnect/M09_ACLK] [get_bd_pins util_ad9361_divclk/clk_out] + connect_bd_net [get_bd_pins util_ad9361_divclk_reset/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M09_ARESETN] + } + zcu102 { + set_property -dict [list CONFIG.NUM_CLKS {2}] [get_bd_cells axi_cpu_interconnect] + # Add 1 extra AXI master ports to the interconnect + set_property -dict [list CONFIG.NUM_MI {5}] [get_bd_cells axi_cpu_interconnect] + connect_bd_net [get_bd_pins axi_cpu_interconnect/aclk1] [get_bd_pins util_ad9361_divclk/clk_out] + } + } + } + fmcomms5 { + if {$rxtx == "rx" || $rxtx == "rxtx"} { + # Disconnect the ADC PACK pins + delete_bd_objs [get_bd_nets util_ad9361_adc_fifo_dout_valid_0] + + delete_bd_objs [get_bd_nets util_ad9361_adc_fifo_dout_data_0] + delete_bd_objs [get_bd_nets util_ad9361_adc_fifo_dout_data_1] + delete_bd_objs [get_bd_nets util_ad9361_adc_fifo_dout_data_2] + delete_bd_objs [get_bd_nets util_ad9361_adc_fifo_dout_data_3] + delete_bd_objs [get_bd_nets util_ad9361_adc_fifo_dout_data_4] + delete_bd_objs [get_bd_nets util_ad9361_adc_fifo_dout_data_5] + delete_bd_objs [get_bd_nets util_ad9361_adc_fifo_dout_data_6] + delete_bd_objs [get_bd_nets util_ad9361_adc_fifo_dout_data_7] + } + if {$rxtx == "tx" || $rxtx == "rxtx"} { + # Disconnect the DAC UNPACK pins + delete_bd_objs [get_bd_nets util_ad9361_dac_upack_fifo_rd_valid] + + # Connect fifo valids together + connect_bd_net [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_1] [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_0] + connect_bd_net [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_2] [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_0] + connect_bd_net [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_3] [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_0] + connect_bd_net [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_4] [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_0] + connect_bd_net [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_5] [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_0] + connect_bd_net [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_6] [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_0] + connect_bd_net [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_7] [get_bd_pins axi_ad9361_dac_fifo/din_valid_in_0] + + # Remove data lines where IP will go + delete_bd_objs [get_bd_nets util_ad9361_dac_upack_fifo_rd_data_0] + delete_bd_objs [get_bd_nets util_ad9361_dac_upack_fifo_rd_data_1] + delete_bd_objs [get_bd_nets util_ad9361_dac_upack_fifo_rd_data_2] + delete_bd_objs [get_bd_nets util_ad9361_dac_upack_fifo_rd_data_3] + delete_bd_objs [get_bd_nets util_ad9361_dac_upack_fifo_rd_data_4] + delete_bd_objs [get_bd_nets util_ad9361_dac_upack_fifo_rd_data_5] + delete_bd_objs [get_bd_nets util_ad9361_dac_upack_fifo_rd_data_6] + delete_bd_objs [get_bd_nets util_ad9361_dac_upack_fifo_rd_data_7] + } + # Add 1 extra AXI master ports to the interconnect + set_property -dict [list CONFIG.NUM_MI {11}] [get_bd_cells axi_cpu_interconnect] + connect_bd_net -net [get_bd_nets util_ad9361_divclk_clk_out] [get_bd_pins axi_cpu_interconnect/M10_ACLK] [get_bd_pins util_ad9361_divclk/clk_out] + connect_bd_net [get_bd_pins util_ad9361_divclk_reset/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M10_ARESETN] + } + pluto { + if {$rxtx == "rx" || $rxtx == "rxtx"} { + # Disconnect the ADC PACK pins + delete_bd_objs [get_bd_nets axi_ad9361_adc_data_i0] + delete_bd_objs [get_bd_nets axi_ad9361_adc_data_q0] + # Disconnect valid + delete_bd_objs [get_bd_nets axi_ad9361_adc_valid_i0] + } + if {$rxtx == "tx" || $rxtx == "rxtx"} { + # Disconnect the DAC UNPACK pins + delete_bd_objs [get_bd_nets fir_interpolator_channel_0] + delete_bd_objs [get_bd_nets fir_interpolator_channel_1] + # Disconnect valid + #delete_bd_objs [get_bd_nets axi_ad9361_dac_dma_fifo_rd_valid] + } + ## Add 1 extra AXI master ports to the interconnect + set_property -dict [list CONFIG.NUM_MI {6}] [get_bd_cells axi_cpu_interconnect] + connect_bd_net [get_bd_pins axi_cpu_interconnect/M05_ACLK] [get_bd_pins axi_ad9361/l_clk] + #connect_bddd_net [get_bd_pins axi_cpu_interconnect/M05_ARESETN] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] + connect_bd_net [get_bd_pins axi_cpu_interconnect/M05_ARESETN] [get_bd_pins sys_rstgen/peripheral_aresetn] + + # Remove filters + #delete_bd_objs [get_bd_cells fir_decimator] + #delete_bd_objs [get_bd_cells fir_interpolator] + delete_bd_objs [get_bd_nets axi_ad9361_adc_valid_i0] [get_bd_nets axi_ad9361_adc_data_i0] [get_bd_nets axi_ad9361_adc_enable_q0] [get_bd_nets rx_fir_decimator_enable_out_1] [get_bd_nets rx_fir_decimator_data_out_1] [get_bd_nets rx_fir_decimator_enable_out_0] [get_bd_nets active_1] [get_bd_nets axi_ad9361_adc_enable_i0] [get_bd_nets rx_fir_decimator_valid_out_0] [get_bd_nets rx_fir_decimator_data_out_0] [get_bd_nets axi_ad9361_adc_valid_q0] [get_bd_nets axi_ad9361_adc_data_q0] [get_bd_cells rx_fir_decimator] + delete_bd_objs [get_bd_nets active_2] [get_bd_nets GND_32_dout] [get_bd_nets axi_ad9361_dac_enable_i0] [get_bd_nets tx_fir_interpolator_valid_out_0] [get_bd_nets tx_upack_fifo_rd_data_0] [get_bd_nets tx_fir_interpolator_data_out_0] [get_bd_nets axi_ad9361_dac_valid_q0] [get_bd_nets tx_upack_fifo_rd_data_1] [get_bd_nets axi_ad9361_dac_valid_i0] [get_bd_nets tx_fir_interpolator_enable_out_0] [get_bd_nets axi_ad9361_dac_enable_q0] [get_bd_nets tx_fir_interpolator_enable_out_1] [get_bd_nets tx_fir_interpolator_data_out_1] [get_bd_cells tx_fir_interpolator] + #delete_bd_objs [get_bd_nets fir_decimator_m_axis_data_tvalid] [get_bd_nets fir_decimator_m_axis_data_tdata] [get_bd_nets decim_slice_Dout] [get_bd_cells fir_decimator] + #delete_bd_objs [get_bd_nets axi_ad9361_dac_dma_fifo_rd_valid] [get_bd_nets fir_interpolator_s_axis_data_tready] [get_bd_nets interp_slice_Dout] [get_bd_nets axi_ad9361_dac_valid_i0] [get_bd_cells fir_interpolator] + + delete_bd_objs [get_bd_nets axi_ad9361_dac_valid_i1] [get_bd_nets logic_or_Res] [get_bd_cells logic_or] + connect_bd_net [get_bd_pins axi_ad9361/dac_valid_i1] [get_bd_pins tx_upack/fifo_rd_en] + } + adrv9009 { + if {$rxtx == "rx" || $rxtx == "rxtx"} { + # Remove decimators + delete_bd_objs [get_bd_nets rx_fir_decimator_valid_out_0] [get_bd_nets rx_adrv9009_tpl_core_adc_data_0] [get_bd_nets rx_adrv9009_tpl_core_adc_enable_1] [get_bd_nets rx_adrv9009_tpl_core_adc_valid_2] [get_bd_nets rx_adrv9009_tpl_core_adc_data_2] [get_bd_nets rx_adrv9009_tpl_core_adc_enable_3] [get_bd_nets rx_fir_decimator_enable_out_0] [get_bd_nets rx_adrv9009_tpl_core_adc_data_1] [get_bd_nets rx_fir_decimator_enable_out_2] [get_bd_nets rx_adrv9009_tpl_core_adc_data_3] [get_bd_nets active_2] [get_bd_nets rx_adrv9009_tpl_core_adc_valid_0] [get_bd_nets rx_fir_decimator_data_out_0] [get_bd_nets rx_fir_decimator_enable_out_1] [get_bd_nets rx_fir_decimator_data_out_2] [get_bd_nets rx_fir_decimator_enable_out_3] [get_bd_nets rx_adrv9009_tpl_core_adc_enable_0] [get_bd_nets rx_adrv9009_tpl_core_adc_valid_1] [get_bd_nets rx_fir_decimator_data_out_1] [get_bd_nets rx_adrv9009_tpl_core_adc_enable_2] [get_bd_nets rx_adrv9009_tpl_core_adc_valid_3] [get_bd_nets rx_fir_decimator_data_out_3] [get_bd_cells rx_fir_decimator] + + # Connect the ADC PACK valid signals together + connect_bd_net [get_bd_pins util_adrv9009_rx_cpack/enable_0] [get_bd_pins util_adrv9009_rx_cpack/enable_1] + connect_bd_net [get_bd_pins util_adrv9009_rx_cpack/enable_0] [get_bd_pins util_adrv9009_rx_cpack/enable_2] + connect_bd_net [get_bd_pins util_adrv9009_rx_cpack/enable_0] [get_bd_pins util_adrv9009_rx_cpack/enable_3] + # Connect enables + connect_bd_net [get_bd_pins rx_adrv9009_tpl_core/adc_enable_0] [get_bd_pins util_adrv9009_rx_cpack/enable_0] + } + if {$rxtx == "tx" || $rxtx == "rxtx"} { + # Remove interpolators + delete_bd_objs [get_bd_nets active_1] [get_bd_nets tx_fir_interpolator_enable_out_0] [get_bd_nets util_adrv9009_tx_upack_fifo_rd_data_1] [get_bd_nets tx_adrv9009_tpl_core_dac_valid_2] [get_bd_nets tx_adrv9009_tpl_core_dac_enable_3] [get_bd_nets tx_fir_interpolator_data_out_3] [get_bd_nets tx_adrv9009_tpl_core_dac_enable_0] [get_bd_nets tx_fir_interpolator_valid_out_0] [get_bd_nets tx_fir_interpolator_data_out_0] [get_bd_nets tx_fir_interpolator_enable_out_1] [get_bd_nets util_adrv9009_tx_upack_fifo_rd_data_2] [get_bd_nets tx_adrv9009_tpl_core_dac_valid_3] [get_bd_nets tx_adrv9009_tpl_core_dac_valid_0] [get_bd_nets tx_adrv9009_tpl_core_dac_enable_1] [get_bd_nets tx_fir_interpolator_data_out_1] [get_bd_nets tx_fir_interpolator_valid_out_2] [get_bd_nets tx_fir_interpolator_enable_out_2] [get_bd_nets util_adrv9009_tx_upack_fifo_rd_data_3] [get_bd_nets GND_32_dout] [get_bd_nets util_adrv9009_tx_upack_fifo_rd_data_0] [get_bd_nets tx_adrv9009_tpl_core_dac_valid_1] [get_bd_nets tx_adrv9009_tpl_core_dac_enable_2] [get_bd_nets tx_fir_interpolator_data_out_2] [get_bd_nets tx_fir_interpolator_enable_out_3] [get_bd_cells tx_fir_interpolator] + + # Connect enables together + connect_bd_net [get_bd_pins util_adrv9009_tx_upack/enable_0] [get_bd_pins tx_adrv9009_tpl_core/dac_enable_0] + connect_bd_net [get_bd_pins util_adrv9009_tx_upack/enable_1] [get_bd_pins tx_adrv9009_tpl_core/dac_enable_1] + connect_bd_net [get_bd_pins util_adrv9009_tx_upack/enable_2] [get_bd_pins tx_adrv9009_tpl_core/dac_enable_2] + connect_bd_net [get_bd_pins util_adrv9009_tx_upack/enable_3] [get_bd_pins tx_adrv9009_tpl_core/dac_enable_3] + } + switch $carrier { + zc706 { + # Add 1 extra AXI master ports to the interconnect + set_property -dict [list CONFIG.NUM_MI {22}] [get_bd_cells axi_cpu_interconnect] + + if {$rxtx == "rx" || $rxtx == "rxtx"} { + connect_bd_net [get_bd_pins axi_cpu_interconnect/M21_ACLK] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0] + } + if {$rxtx == "tx" || $rxtx == "rxtx"} { + # Remove valid combiner + delete_bd_objs [get_bd_nets tx_fir_interpolator_valid_out_0] [get_bd_nets tx_fir_interpolator_valid_out_2] [get_bd_nets logic_or_Res] [get_bd_cells logic_or] + } + if {$rxtx == "rxtx"} { + # Map all TX clocks to RX + delete_bd_objs [get_bd_nets adrv9009_tx_device_clk] + + connect_bd_net [get_bd_pins axi_adrv9009_tx_jesd/device_clk] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0] + connect_bd_net [get_bd_pins util_adrv9009_tx_upack/clk] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0] + connect_bd_net [get_bd_pins tx_adrv9009_tpl_core/link_clk] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0] + connect_bd_net [get_bd_pins axi_adrv9009_dacfifo/dac_clk] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0] + connect_bd_net [get_bd_pins adrv9009_tx_device_clk_rstgen/slowest_sync_clk] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0] + connect_bd_net [get_bd_pins axi_adrv9009_tx_jesd/link_clk] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0] + + connect_bd_net [get_bd_pins util_adrv9009_xcvr/tx_clk_0] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0] + connect_bd_net [get_bd_pins util_adrv9009_xcvr/tx_clk_1] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0] + connect_bd_net [get_bd_pins util_adrv9009_xcvr/tx_clk_2] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0] + connect_bd_net [get_bd_pins util_adrv9009_xcvr/tx_clk_3] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0] + } + if {$rxtx == "tx"} { + connect_bd_net [get_bd_pins axi_cpu_interconnect/M21_ACLK] [get_bd_pins axi_adrv9009_tx_clkgen/clk_0] + } + } + zcu102 { + + # RX ONLY + # IPCORE_RESETN -> adrv9009_rx_device_clk_rstgen/peripheral_aresetn + # AXI4_LITE_ARESETN -> adrv9009_rx_device_clk_rstgen/peripheral_aresetn + # M16_RESET -> adrv9009_rx_device_clk_rstgen/peripheral_aresetn + # M16 -> rx_clkgen/clk_0 + + # Add 1 extra AXI master ports to the interconnect + set_property -dict [list CONFIG.NUM_CLKS {2}] [get_bd_cells axi_cpu_interconnect] + set_property -dict [list CONFIG.NUM_MI {17}] [get_bd_cells axi_cpu_interconnect] + #connect_bd_net [get_bd_pins axi_cpu_interconnect/M16_ARESETN] [get_bd_pins sys_rstgen/peripheral_aresetn] + #connect_bd_net -net [get_bd_nets axi_adrv9009_rx_clkgen] [get_bd_pins axi_cpu_interconnect/M16_ACLK] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0] + #connect_bd_net [get_bd_pins sys_rstgen/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M16_ARESETN] + + if {$rxtx == "rx" || $rxtx == "rxtx"} { + connect_bd_net [get_bd_pins axi_cpu_interconnect/aclk1] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0] + } + if {$rxtx == "tx" || $rxtx == "rxtx"} { + # Remove valid combiner + delete_bd_objs [get_bd_nets tx_fir_interpolator_valid_out_0] [get_bd_nets tx_fir_interpolator_valid_out_2] [get_bd_nets logic_or_Res] [get_bd_cells logic_or] + } + if {$rxtx == "rxtx"} { + # Map all TX clocks to RX + delete_bd_objs [get_bd_nets adrv9009_tx_device_clk] + connect_bd_net [get_bd_pins axi_adrv9009_tx_jesd/link_clk] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0] + + connect_bd_net [get_bd_pins axi_adrv9009_tx_jesd/device_clk] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0] + connect_bd_net [get_bd_pins util_adrv9009_tx_upack/clk] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0] + connect_bd_net [get_bd_pins tx_adrv9009_tpl_core/link_clk] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0] + connect_bd_net [get_bd_pins axi_adrv9009_dacfifo/dac_clk] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0] + connect_bd_net [get_bd_pins adrv9009_tx_device_clk_rstgen/slowest_sync_clk] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0] + + connect_bd_net [get_bd_pins util_adrv9009_xcvr/tx_clk_0] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0] + connect_bd_net [get_bd_pins util_adrv9009_xcvr/tx_clk_1] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0] + connect_bd_net [get_bd_pins util_adrv9009_xcvr/tx_clk_2] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0] + connect_bd_net [get_bd_pins util_adrv9009_xcvr/tx_clk_3] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0] + } + if {$rxtx == "tx"} { + connect_bd_net [get_bd_pins axi_cpu_interconnect/aclk1] [get_bd_pins axi_adrv9009_tx_clkgen/clk_0] + } + } + } + } + fmcomms8 { + if {$rxtx == "rx" || $rxtx == "rxtx"} { + # Remove data between TPL and CPACK + for { set port 0} {$port < 8} {incr port} { + delete_bd_objs [get_bd_nets rx_adrv9009_fmc_tpl_core_adc_data_$port] + } + # Remove valid + delete_bd_objs [get_bd_nets rx_adrv9009_fmc_tpl_core_adc_valid_0] + + } + if {$rxtx == "tx" || $rxtx == "rxtx"} { + # Remove data between TPL and CPACK + for { set port 0} {$port < 8} {incr port} { + delete_bd_objs [get_bd_nets util_fmc_tx_upack_fifo_rd_data_$port] + } + } + switch $carrier { + zcu102 { + # Add 1 extra AXI master ports to the interconnect + set_property -dict [list CONFIG.NUM_MI {14}] [get_bd_cells axi_cpu_interconnect] + #connect_bd_net [get_bd_pins axi_cpu_interconnect/M13_ACLK] [get_bd_pins sys_ps8/pl_clk0] + #connect_bd_net [get_bd_pins axi_cpu_interconnect/M13_ARESETN] [get_bd_pins sys_rstgen/peripheral_aresetn] + set_property -dict [list CONFIG.NUM_CLKS {2}] [get_bd_cells axi_cpu_interconnect] + + if {$rxtx == "rx" || $rxtx == "rxtx"} { + # connect_bd_net [get_bd_pins axi_cpu_interconnect/M13_ACLK] [get_bd_pins core_clk_d] + connect_bd_net [get_bd_pins axi_cpu_interconnect/aclk1] [get_bd_pins core_clk_d] + # connect_bd_net [get_bd_pins core_clk_d_rstgen/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M13_ARESETN] + } + if {$rxtx == "tx" || $rxtx == "rxtx"} { + # Remove valid combiner + # delete_bd_objs [get_bd_nets tx_fir_interpolator_valid_out_0] [get_bd_nets tx_fir_interpolator_valid_out_2] [get_bd_nets logic_or_Res] [get_bd_cells logic_or] + } + if {$rxtx == "tx"} { + connect_bd_net [get_bd_pins axi_cpu_interconnect/aclk1] [get_bd_pins core_clk_c] + } + } + } + } + adrv9001 { + if {$rxtx != "tx"} { + # Remove ADC->Pack + delete_bd_objs [get_bd_nets axi_adrv9001_adc_1_data_i0] + delete_bd_objs [get_bd_nets axi_adrv9001_adc_1_data_q0] + delete_bd_objs [get_bd_nets axi_adrv9001_adc_1_data_i1] + delete_bd_objs [get_bd_nets axi_adrv9001_adc_1_data_q1] + # Remove enable aka valid + delete_bd_objs [get_bd_nets axi_adrv9001_adc_1_valid_i0] + } + if {$rxtx != "rx"} { + # Remove UPack->DAC + delete_bd_objs [get_bd_nets util_dac_1_upack_fifo_rd_data_0] + delete_bd_objs [get_bd_nets util_dac_1_upack_fifo_rd_data_1] + delete_bd_objs [get_bd_nets util_dac_1_upack_fifo_rd_data_2] + delete_bd_objs [get_bd_nets util_dac_1_upack_fifo_rd_data_3] + # Remove enable aka valid + delete_bd_objs [get_bd_nets axi_adrv9001_dac_1_valid_i0] + } + switch $carrier { + zcu102 { + # Create and connect synchronizers + data_synchronizer $rxtx $number_of_inputs $number_of_bits $number_of_valids $multiple + + # Add 1 extra AXI master ports to the interconnect + set_property -dict [list CONFIG.NUM_MI {7}] [get_bd_cells axi_cpu_interconnect] + set_property -dict [list CONFIG.NUM_CLKS {2}] [get_bd_cells axi_cpu_interconnect] + + create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rx_rstn_inverter + set_property -dict [list CONFIG.C_SIZE {1} CONFIG.C_OPERATION {not} CONFIG.LOGO_FILE {data/sym_notgate.png}] [get_bd_cells rx_rstn_inverter] + + ad_connect axi_adrv9001/adc_1_rst rx_rstn_inverter/Op1 + + create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 tx_rstn_inverter + set_property -dict [list CONFIG.C_SIZE {1} CONFIG.C_OPERATION {not} CONFIG.LOGO_FILE {data/sym_notgate.png}] [get_bd_cells tx_rstn_inverter] + + ad_connect axi_adrv9001/dac_1_rst tx_rstn_inverter/Op1 + + # Connect clock and reset + if {$rxtx == "rx" || $rxtx == "rxtx"} { + connect_bd_net [get_bd_pins axi_cpu_interconnect/aclk1] [get_bd_pins axi_adrv9001/adc_1_clk] + } else { + connect_bd_net [get_bd_pins axi_cpu_interconnect/aclk1] [get_bd_pins axi_adrv9001/dac_1_clk] + } + if {$rxtx != "tx"} { + # clock and reset + connect_bd_net [get_bd_pins axi_adrv9001/adc_1_clk] [get_bd_pins sync_input/rx_clk] + connect_bd_net [get_bd_pins rx_rstn_inverter/Res] [get_bd_pins sync_input/rx_rstn] + connect_bd_net [get_bd_pins axi_adrv9001/adc_1_clk] [get_bd_pins sync_output/rx_clk] + connect_bd_net [get_bd_pins rx_rstn_inverter/Res] [get_bd_pins sync_output/rx_rstn] + # sync input connections + connect_bd_net [get_bd_pins sync_input/data_in_rx_0] [get_bd_pins axi_adrv9001/adc_1_data_i0] + connect_bd_net [get_bd_pins sync_input/data_in_rx_1] [get_bd_pins axi_adrv9001/adc_1_data_i1] + connect_bd_net [get_bd_pins sync_input/data_in_rx_2] [get_bd_pins axi_adrv9001/adc_1_data_q0] + connect_bd_net [get_bd_pins sync_input/data_in_rx_3] [get_bd_pins axi_adrv9001/adc_1_data_q1] + connect_bd_net [get_bd_pins sync_input/data_valid_in_rx_0] [get_bd_pins axi_adrv9001/adc_1_valid_i0] + # sync ouput connections + connect_bd_net [get_bd_pins sync_output/data_out_rx_0] [get_bd_pins util_adc_1_pack/fifo_wr_data_0] + connect_bd_net [get_bd_pins sync_output/data_out_rx_1] [get_bd_pins util_adc_1_pack/fifo_wr_data_1] + connect_bd_net [get_bd_pins sync_output/data_out_rx_2] [get_bd_pins util_adc_1_pack/fifo_wr_data_2] + connect_bd_net [get_bd_pins sync_output/data_out_rx_3] [get_bd_pins util_adc_1_pack/fifo_wr_data_3] + connect_bd_net [get_bd_pins sync_output/data_valid_out_rx_0] [get_bd_pins util_adc_1_pack/fifo_wr_en] + } + if {$rxtx != "rx"} { + # clock and reset + connect_bd_net [get_bd_pins axi_adrv9001/dac_1_clk] [get_bd_pins sync_input/tx_clk] + connect_bd_net [get_bd_pins tx_rstn_inverter/Res] [get_bd_pins sync_input/tx_rstn] + connect_bd_net [get_bd_pins axi_adrv9001/dac_1_clk] [get_bd_pins sync_output/tx_clk] + connect_bd_net [get_bd_pins tx_rstn_inverter/Res] [get_bd_pins sync_output/tx_rstn] + # sync input connections + connect_bd_net [get_bd_pins sync_input/data_in_tx_0] [get_bd_pins util_dac_1_upack/fifo_rd_data_0] + connect_bd_net [get_bd_pins sync_input/data_in_tx_1] [get_bd_pins util_dac_1_upack/fifo_rd_data_1] + connect_bd_net [get_bd_pins sync_input/data_in_tx_2] [get_bd_pins util_dac_1_upack/fifo_rd_data_2] + connect_bd_net [get_bd_pins sync_input/data_in_tx_3] [get_bd_pins util_dac_1_upack/fifo_rd_data_3] + connect_bd_net [get_bd_pins sync_input/data_valid_in_tx_0] [get_bd_pins axi_adrv9001/dac_1_valid_i0] + # sync ouput connections + connect_bd_net [get_bd_pins sync_output/data_out_tx_0] [get_bd_pins axi_adrv9001/dac_1_data_i0] + connect_bd_net [get_bd_pins sync_output/data_out_tx_1] [get_bd_pins axi_adrv9001/dac_1_data_i1] + connect_bd_net [get_bd_pins sync_output/data_out_tx_2] [get_bd_pins axi_adrv9001/dac_1_data_q0] + connect_bd_net [get_bd_pins sync_output/data_out_tx_3] [get_bd_pins axi_adrv9001/dac_1_data_q1] + connect_bd_net [get_bd_pins sync_output/data_valid_out_tx_0] [get_bd_pins util_dac_1_upack/fifo_rd_en] + } + } + } + } + adrv9371x { + if {$rxtx == "rx" || $rxtx == "rxtx"} { + # Remove decimator + delete_bd_objs [get_bd_nets rx_fir_decimator_valid_out_0] [get_bd_nets rx_ad9371_tpl_core_adc_data_0] [get_bd_nets rx_ad9371_tpl_core_adc_enable_1] [get_bd_nets rx_ad9371_tpl_core_adc_valid_2] [get_bd_nets rx_ad9371_tpl_core_adc_data_2] [get_bd_nets rx_ad9371_tpl_core_adc_enable_3] [get_bd_nets rx_fir_decimator_enable_out_0] [get_bd_nets rx_ad9371_tpl_core_adc_data_1] [get_bd_nets rx_fir_decimator_enable_out_2] [get_bd_nets rx_ad9371_tpl_core_adc_data_3] [get_bd_nets active_2] [get_bd_nets rx_ad9371_tpl_core_adc_valid_0] [get_bd_nets rx_fir_decimator_data_out_0] [get_bd_nets rx_fir_decimator_enable_out_1] [get_bd_nets rx_fir_decimator_data_out_2] [get_bd_nets rx_fir_decimator_enable_out_3] [get_bd_nets rx_ad9371_tpl_core_adc_enable_0] [get_bd_nets rx_ad9371_tpl_core_adc_valid_1] [get_bd_nets rx_fir_decimator_data_out_1] [get_bd_nets rx_ad9371_tpl_core_adc_enable_2] [get_bd_nets rx_ad9371_tpl_core_adc_valid_3] [get_bd_nets rx_fir_decimator_data_out_3] [get_bd_cells rx_fir_decimator] + + # Connect the TPL enables to pack enables + connect_bd_net [get_bd_pins rx_ad9371_tpl_core/adc_enable_0] [get_bd_pins util_ad9371_rx_cpack/enable_0] + connect_bd_net [get_bd_pins rx_ad9371_tpl_core/adc_enable_1] [get_bd_pins util_ad9371_rx_cpack/enable_1] + connect_bd_net [get_bd_pins rx_ad9371_tpl_core/adc_enable_2] [get_bd_pins util_ad9371_rx_cpack/enable_2] + connect_bd_net [get_bd_pins rx_ad9371_tpl_core/adc_enable_3] [get_bd_pins util_ad9371_rx_cpack/enable_3] + + + } + if {$rxtx == "tx" || $rxtx == "rxtx"} { + # Remove interpolators + delete_bd_objs [get_bd_nets active_1] [get_bd_nets tx_fir_interpolator_enable_out_0] [get_bd_nets util_ad9371_tx_upack_fifo_rd_data_1] [get_bd_nets tx_ad9371_tpl_core_dac_valid_2] [get_bd_nets tx_ad9371_tpl_core_dac_enable_3] [get_bd_nets tx_fir_interpolator_data_out_3] [get_bd_nets tx_ad9371_tpl_core_dac_enable_0] [get_bd_nets tx_fir_interpolator_valid_out_0] [get_bd_nets tx_fir_interpolator_data_out_0] [get_bd_nets tx_fir_interpolator_enable_out_1] [get_bd_nets util_ad9371_tx_upack_fifo_rd_data_2] [get_bd_nets tx_ad9371_tpl_core_dac_valid_3] [get_bd_nets tx_ad9371_tpl_core_dac_valid_0] [get_bd_nets tx_ad9371_tpl_core_dac_enable_1] [get_bd_nets tx_fir_interpolator_data_out_1] [get_bd_nets tx_fir_interpolator_valid_out_2] [get_bd_nets tx_fir_interpolator_enable_out_2] [get_bd_nets util_ad9371_tx_upack_fifo_rd_data_3] [get_bd_nets GND_32_dout] [get_bd_nets util_ad9371_tx_upack_fifo_rd_data_0] [get_bd_nets tx_ad9371_tpl_core_dac_valid_1] [get_bd_nets tx_ad9371_tpl_core_dac_enable_2] [get_bd_nets tx_fir_interpolator_data_out_2] [get_bd_nets tx_fir_interpolator_enable_out_3] [get_bd_cells tx_fir_interpolator] + + # Connect the TPL enables to pack enables + connect_bd_net [get_bd_pins tx_ad9371_tpl_core/dac_enable_0] [get_bd_pins util_ad9371_tx_upack/enable_0] + connect_bd_net [get_bd_pins tx_ad9371_tpl_core/dac_enable_1] [get_bd_pins util_ad9371_tx_upack/enable_1] + connect_bd_net [get_bd_pins tx_ad9371_tpl_core/dac_enable_2] [get_bd_pins util_ad9371_tx_upack/enable_2] + connect_bd_net [get_bd_pins tx_ad9371_tpl_core/dac_enable_3] [get_bd_pins util_ad9371_tx_upack/enable_3] + + # Remove valid combiner + delete_bd_objs [get_bd_nets tx_fir_interpolator_valid_out_0] [get_bd_nets tx_fir_interpolator_valid_out_2] [get_bd_nets logic_or_Res] [get_bd_cells logic_or] + } + if {$rxtx == "rxtx"} { + #delete_bd_objs [get_bd_nets axi_ad9371_tx_clkgen_clk] + delete_bd_objs [get_bd_nets ad9371_tx_device_clk] + + connect_bd_net [get_bd_pins util_ad9371_xcvr/tx_clk_0] [get_bd_pins axi_ad9371_rx_clkgen/clk_0] + connect_bd_net [get_bd_pins util_ad9371_xcvr/tx_clk_1] [get_bd_pins axi_ad9371_rx_clkgen/clk_0] + connect_bd_net [get_bd_pins util_ad9371_xcvr/tx_clk_2] [get_bd_pins axi_ad9371_rx_clkgen/clk_0] + connect_bd_net [get_bd_pins util_ad9371_xcvr/tx_clk_3] [get_bd_pins axi_ad9371_rx_clkgen/clk_0] + + connect_bd_net [get_bd_pins axi_ad9371_tx_jesd/device_clk] [get_bd_pins axi_ad9371_rx_clkgen/clk_0] + connect_bd_net [get_bd_pins util_ad9371_tx_upack/clk] [get_bd_pins axi_ad9371_rx_clkgen/clk_0] + connect_bd_net [get_bd_pins ad9371_tx_device_clk_rstgen/slowest_sync_clk] [get_bd_pins axi_ad9371_rx_clkgen/clk_0] + connect_bd_net [get_bd_pins axi_ad9371_dacfifo/dac_clk] [get_bd_pins axi_ad9371_rx_clkgen/clk_0] + connect_bd_net [get_bd_pins tx_ad9371_tpl_core/link_clk] [get_bd_pins axi_ad9371_rx_clkgen/clk_0] + connect_bd_net [get_bd_pins axi_ad9371_tx_jesd/link_clk] [get_bd_pins axi_ad9371_rx_clkgen/clk_0] + } + switch $carrier { + zc706 { + # Add 1 extra AXI master ports to the interconnect + set_property -dict [list CONFIG.NUM_MI {22}] [get_bd_cells axi_cpu_interconnect] + #set_property -dict [list CONFIG.NUM_CLKS {2}] [get_bd_cells axi_cpu_interconnect] + connect_bd_net [get_bd_pins sys_rstgen/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M21_ARESETN] + + if {$rxtx == "rx" || $rxtx == "rxtx"} { + #connect_bd_net [get_bd_pins axi_cpu_interconnect/aclk1] [get_bd_pins axi_ad9371_rx_clkgen/clk_0] + connect_bd_net -net [get_bd_nets axi_ad9371_rx_clkgen] [get_bd_pins axi_cpu_interconnect/M21_ACLK] [get_bd_pins axi_ad9371_rx_clkgen/clk_0] + } + if {$rxtx == "tx"} { + #connect_bd_net [get_bd_pins axi_cpu_interconnect/aclk1] [get_bd_pins axi_ad9371_tx_clkgen/clk_0] + connect_bd_net -net [get_bd_nets axi_ad9371_tx_clkgen] [get_bd_pins axi_cpu_interconnect/M21_ACLK] [get_bd_pins axi_ad9371_tx_clkgen/clk_0] + } + } + zcu102 { + set_property -dict [list CONFIG.NUM_CLKS {2}] [get_bd_cells axi_cpu_interconnect] + # connect_bd_net [get_bd_pins axi_cpu_interconnect/aclk1] [get_bd_pins axi_ad9371_rx_clkgen/clk_0] + # Add 1 extra AXI master ports to the interconnect + set_property -dict [list CONFIG.NUM_MI {17}] [get_bd_cells axi_cpu_interconnect] + #connect_bd_net -net [get_bd_nets axi_adrv9009_rx_clkgen] [get_bd_pins axi_cpu_interconnect/M16_ACLK] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0] + # connect_bd_net [get_bd_pins sys_rstgen/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M16_ARESETN] + + if {$rxtx == "rx" || $rxtx == "rxtx"} { + connect_bd_net [get_bd_pins axi_cpu_interconnect/aclk1] [get_bd_pins axi_ad9371_rx_clkgen/clk_0] + #connect_bd_net -net [get_bd_nets axi_ad9371_rx_clkgen] [get_bd_pins axi_cpu_interconnect/M16_ACLK] [get_bd_pins axi_ad9371_rx_clkgen/clk_0] + } + if {$rxtx == "tx"} { + connect_bd_net [get_bd_pins axi_cpu_interconnect/aclk1] [get_bd_pins axi_ad9371_tx_clkgen/clk_0] + # Remove valid combiner + # delete_bd_objs [get_bd_nets tx_fir_interpolator_valid_out_0] [get_bd_nets tx_fir_interpolator_valid_out_2] [get_bd_nets logic_or_Res] [get_bd_cells logic_or] + # connect_bd_net -net [get_bd_nets axi_ad9371_tx_clkgen] [get_bd_pins axi_cpu_interconnect/M16_ACLK] [get_bd_pins axi_ad9371_tx_clkgen/clk_0] + } + } + } + } + } +} diff --git a/CI/scripts/pack_all_ips.tcl b/CI/scripts/pack_all_ips.tcl new file mode 100644 index 0000000..afe66e1 --- /dev/null +++ b/CI/scripts/pack_all_ips.tcl @@ -0,0 +1,53 @@ + +# Create zip of IP cores +proc pack_ip_core {} { + + set folder_list [glob -types d *] + + foreach dir $folder_list { + puts "$dir" + cd $dir + + if {[catch {set fp [open ${dir}_ip.tcl r]}]} { + cd .. + continue + } + close $fp + + set fp [open ${dir}_ip.tcl a+] + puts -nonewline $fp "ipx::archive_core -verbose {analog.com_user_" + puts -nonewline $fp "$dir" + puts -nonewline $fp "_1.0.zip} \[ipx::current_core\]" + close $fp + + source ./${dir}_ip.tcl + + cd .. + } +} + +source hdl/library/scripts/adi_ip_xilinx.tcl +source hdl/scripts/adi_env.tcl + +cd hdl + +# Pack main library cores +cd library +pack_ip_core + +# Pack Xilinx cores +cd xilinx +pack_ip_core +cd .. + +# Pack JESD cores +cd jesd204 +pack_ip_core +cd .. + +# Pack spi_engine cores +cd spi_engine +pack_ip_core +cd .. + +cd ../../ diff --git a/CI/scripts/pmufw_zynqmp.tcl b/CI/scripts/pmufw_zynqmp.tcl new file mode 100644 index 0000000..a431e71 --- /dev/null +++ b/CI/scripts/pmufw_zynqmp.tcl @@ -0,0 +1,8 @@ + +set cdir [pwd] +set sdk_loc $cdir/vivado_prj.sdk + +### Create create_pmufw_project.tcl +set hwdsgn [open_hw_design $sdk_loc/system_top.hdf] +generate_app -hw $hwdsgn -os standalone -proc psu_pmu_0 -app zynqmp_pmufw -sw pmufw -dir pmufw +quit diff --git a/CI/scripts/ports.json b/CI/scripts/ports.json new file mode 100644 index 0000000..1e6b1b2 --- /dev/null +++ b/CI/scripts/ports.json @@ -0,0 +1,1405 @@ +{ + "adrv9361z7035": { + "chip": "AD9361", + "complex": "true", + "fpga": [ + "ccbob_cmos", + "ccbob_lvds", + "ccbox_lvds", + "ccfmc_lvds", + "ccpackrf_lvds" + ], + "supported_rd": [ + "rx", + "tx", + "rx & tx" + ], + "ports": [ + { + "rx": [ + { + "input": "false", + "width": 1, + "name": "util_ad9361_adc_pack/fifo_wr_en", + "type": "valid" + }, + { + "input": "true", + "width": 1, + "name": "util_ad9361_adc_fifo/dout_valid_0", + "type": "valid" + }, + { + "input": "false", + "width": 16, + "name": "util_ad9361_adc_pack/fifo_wr_data_0", + "type": "data" + }, + { + "input": "false", + "width": 16, + "name": "util_ad9361_adc_pack/fifo_wr_data_1", + "type": "data" + }, + { + "input": "false", + "width": 16, + "name": "util_ad9361_adc_pack/fifo_wr_data_2", + "type": "data" + }, + { + "input": "false", + "width": 16, + "name": "util_ad9361_adc_pack/fifo_wr_data_3", + "type": "data" + }, + { + "input": "true", + "width": 16, + "name": "util_ad9361_adc_fifo/dout_data_0", + "type": "data" + }, + { + "input": "true", + "width": 16, + "name": "util_ad9361_adc_fifo/dout_data_1", + "type": "data" + }, + { + "input": "true", + "width": 16, + "name": "util_ad9361_adc_fifo/dout_data_2", + "type": "data" + }, + { + "input": "true", + "width": 16, + "name": "util_ad9361_adc_fifo/dout_data_3", + "type": "data" + } + ], + "tx": [ + { + "input": "true", + "width": 1, + "name": "util_ad9361_dac_upack/fifo_rd_valid", + "type": "valid" + }, + { + "input": "false", + "width": 1, + "name": "axi_ad9361_dac_fifo/din_valid_in_0", + "type": "valid" + }, + { + "input": "false", + "width": 16, + "name": "axi_ad9361_dac_fifo/din_data_0", + "type": "data" + }, + { + "input": "false", + "width": 16, + "name": "axi_ad9361_dac_fifo/din_data_1", + "type": "data" + }, + { + "input": "false", + "width": 16, + "name": "axi_ad9361_dac_fifo/din_data_2", + "type": "data" + }, + { + "input": "false", + "width": 16, + "name": "axi_ad9361_dac_fifo/din_data_3", + "type": "data" + }, + { + "input": "true", + "width": 16, + "name": "util_ad9361_dac_upack/fifo_rd_data_0", + "type": "data" + }, + { + "input": "true", + "width": 16, + "name": "util_ad9361_dac_upack/fifo_rd_data_1", + "type": "data" + }, + { + "input": "true", + "width": 16, + "name": "util_ad9361_dac_upack/fifo_rd_data_2", + "type": "data" + }, + { + "input": "true", + "width": 16, + "name": "util_ad9361_dac_upack/fifo_rd_data_3", + "type": "data" + } + ] + } + ] + }, + "adrv9364z7020": { + "chip": "AD9364", + "complex": "true", + "fpga": [ + "ccbob_cmos", + "ccbob_lvds", + "ccbox_lvds" + ], + "supported_rd": [ + "rx", + "tx", + "rx & tx" + ], + "ports": [ + { + "rx": [ + { + "input": "false", + "width": 1, + "name": "util_ad9361_adc_pack/fifo_wr_en", + "type": "valid" + }, + { + "input": "true", + "width": 1, + "name": "util_ad9361_adc_fifo/dout_valid_0", + "type": "valid" + }, + { + "input": "false", + "width": 16, + "name": "util_ad9361_adc_pack/fifo_wr_data_0", + "type": "data" + }, + { + "input": "false", + "width": 16, + "name": "util_ad9361_adc_pack/fifo_wr_data_1", + "type": "data" + }, + { + "input": "false", + "width": 16, + "name": "util_ad9361_adc_pack/fifo_wr_data_2", + "type": "data" + }, + { + "input": "false", + "width": 16, + "name": "util_ad9361_adc_pack/fifo_wr_data_3", + "type": "data" + }, + { + "input": "true", + "width": 16, + "name": "util_ad9361_adc_fifo/dout_data_0", + "type": "data" + }, + { + "input": "true", + "width": 16, + "name": "util_ad9361_adc_fifo/dout_data_1", + "type": "data" + }, + { + "input": "true", + "width": 16, + "name": "util_ad9361_adc_fifo/dout_data_2", + "type": "data" + }, + { + "input": "true", + "width": 16, + "name": "util_ad9361_adc_fifo/dout_data_3", + "type": "data" + } + ], + "tx": [ + { + "input": "true", + "width": 1, + "name": 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"type": "data" + }, + { + "input": "false", + "width": 16, + "name": "util_adrv9009_rx_cpack/fifo_wr_data_2", + "type": "data" + }, + { + "input": "false", + "width": 16, + "name": "util_adrv9009_rx_cpack/fifo_wr_data_3", + "type": "data" + }, + { + "input": "true", + "width": 16, + "name": "rx_adrv9009_tpl_core/adc_data_0", + "type": "data" + }, + { + "input": "true", + "width": 16, + "name": "rx_adrv9009_tpl_core/adc_data_1", + "type": "data" + }, + { + "input": "true", + "width": 16, + "name": "rx_adrv9009_tpl_core/adc_data_2", + "type": "data" + }, + { + "input": "true", + "width": 16, + "name": "rx_adrv9009_tpl_core/adc_data_3", + "type": "data" + } + ], + "tx": [ + { + "input": "true", + "width": 1, + "name": "util_adrv9009_tx_upack/fifo_rd_valid", + "type": "valid" + }, + { + "input": "false", + "width": 1, + "name": "util_adrv9009_tx_upack/fifo_rd_en", + "type": "valid" + }, + { + "input": "false", + "width": 32, + "name": "tx_adrv9009_tpl_core/dac_data_0", + "type": "data" + }, + { + "input": "false", + "width": 32, + "name": "tx_adrv9009_tpl_core/dac_data_1", + "type": "data" + }, + { + "input": "false", + "width": 32, + "name": "tx_adrv9009_tpl_core/dac_data_2", + "type": "data" + }, + { + "input": "false", + "width": 32, + "name": "tx_adrv9009_tpl_core/dac_data_3", + "type": "data" + }, + { + "input": "true", + "width": 32, + "name": "util_adrv9009_tx_upack/fifo_rd_data_0", + "type": "data" + }, + { + "input": "true", + "width": 32, + "name": "util_adrv9009_tx_upack/fifo_rd_data_1", + "type": "data" + }, + { + "input": "true", + "width": 32, + "name": "util_adrv9009_tx_upack/fifo_rd_data_2", + "type": "data" + }, + { + "input": "true", + "width": 32, + "name": "util_adrv9009_tx_upack/fifo_rd_data_3", + "type": "data" + } + ] + } + ] + }, + "fmcomms8": { + "chip": "ADRV9009", + "complex": "true", + "fpga": [ + "zcu102" + ], + "supported_rd": [ + "rx", + "tx", + "rx & tx" + ], + "ports": [ + { + "rx": [ + { + "input": "false", + "width": 1, + "name": "util_fmc_rx_cpack/fifo_wr_en", + "type": "valid" + }, + { + "input": "true", + "width": 1, + "name": "rx_adrv9009_fmc_tpl_core/adc_valid_0", + "type": "valid" + }, + { + "input": "false", + "width": 16, + "name": "util_fmc_rx_cpack/fifo_wr_data_0", + "type": "data" + }, + { + "input": "false", + "width": 16, + "name": "util_fmc_rx_cpack/fifo_wr_data_1", + "type": "data" + }, + { + "input": "false", + "width": 16, + "name": "util_fmc_rx_cpack/fifo_wr_data_2", + "type": "data" + }, + { + "input": "false", + "width": 16, + "name": "util_fmc_rx_cpack/fifo_wr_data_3", + "type": "data" + }, + { + "input": "false", + "width": 16, + "name": "util_fmc_rx_cpack/fifo_wr_data_4", + "type": "data" + }, + { + "input": "false", + "width": 16, + "name": "util_fmc_rx_cpack/fifo_wr_data_5", + "type": "data" + }, + { + "input": "false", + "width": 16, + "name": "util_fmc_rx_cpack/fifo_wr_data_6", + "type": "data" + }, + { + "input": "false", + "width": 16, + "name": "util_fmc_rx_cpack/fifo_wr_data_7", + "type": "data" + }, + { + "input": "true", + "width": 16, + "name": "rx_adrv9009_fmc_tpl_core/adc_data_0", + "type": "data" + }, + { + "input": "true", + "width": 16, + "name": "rx_adrv9009_fmc_tpl_core/adc_data_1", + "type": "data" + }, + { + "input": "true", + "width": 16, + "name": "rx_adrv9009_fmc_tpl_core/adc_data_2", + "type": "data" + }, + { + "input": "true", + "width": 16, + "name": "rx_adrv9009_fmc_tpl_core/adc_data_3", + "type": "data" + }, + { + "input": "true", + "width": 16, + "name": "rx_adrv9009_fmc_tpl_core/adc_data_4", + "type": "data" + }, + { + "input": "true", + "width": 16, + "name": "rx_adrv9009_fmc_tpl_core/adc_data_5", + "type": "data" + }, + { + "input": "true", + "width": 16, + "name": "rx_adrv9009_fmc_tpl_core/adc_data_6", + "type": "data" + }, + { + "input": "true", + "width": 16, + "name": "rx_adrv9009_fmc_tpl_core/adc_data_7", + "type": "data" + } + ], + "tx": [ + { + "input": "true", + "width": 1, + "name": "util_fmc_tx_upack/fifo_rd_valid", + "type": "valid" + }, + { + "input": "false", + "width": 32, + "name": "tx_adrv9009_fmc_tpl_core/dac_data_0", + "type": "data" + }, + { + "input": "false", + "width": 32, + "name": "tx_adrv9009_fmc_tpl_core/dac_data_1", + "type": "data" + }, + { + "input": "false", + "width": 32, + "name": "tx_adrv9009_fmc_tpl_core/dac_data_2", + "type": "data" + }, + { + "input": "false", + "width": 32, + "name": "tx_adrv9009_fmc_tpl_core/dac_data_3", + "type": "data" + }, + { + "input": "false", + "width": 32, + "name": "tx_adrv9009_fmc_tpl_core/dac_data_4", + "type": "data" + }, + { + "input": "false", + "width": 32, + "name": "tx_adrv9009_fmc_tpl_core/dac_data_5", + "type": "data" + }, + { + "input": "false", + "width": 32, + "name": "tx_adrv9009_fmc_tpl_core/dac_data_6", + "type": "data" + }, + { + "input": "false", + "width": 32, + "name": "tx_adrv9009_fmc_tpl_core/dac_data_7", + "type": "data" + }, + { + "input": "true", + "width": 32, + "name": "util_fmc_tx_upack/fifo_rd_data_0", + "type": "data" + }, + { + "input": "true", + "width": 32, + "name": "util_fmc_tx_upack/fifo_rd_data_1", + "type": "data" + }, + { + "input": "true", + "width": 32, + "name": "util_fmc_tx_upack/fifo_rd_data_2", + "type": "data" + }, + { + "input": "true", + "width": 32, + "name": "util_fmc_tx_upack/fifo_rd_data_3", + "type": "data" + }, + { + "input": "true", + "width": 32, + "name": "util_fmc_tx_upack/fifo_rd_data_4", + "type": "data" + }, + { + "input": "true", + "width": 32, + "name": "util_fmc_tx_upack/fifo_rd_data_5", + "type": "data" + }, + { + "input": "true", + "width": 32, + "name": "util_fmc_tx_upack/fifo_rd_data_6", + "type": "data" + }, + { + "input": "true", + "width": 32, + "name": "util_fmc_tx_upack/fifo_rd_data_7", + "type": "data" + } + ] + } + ] + } +} diff --git a/CI/scripts/read_ports_json.py b/CI/scripts/read_ports_json.py new file mode 100644 index 0000000..0c082cb --- /dev/null +++ b/CI/scripts/read_ports_json.py @@ -0,0 +1,69 @@ +import json + +# open ports.json file and parse +ports_json_file = 'ports.json' +with open(ports_json_file) as json_file: + ports = json.load(json_file) + + tmp_key = "m_name" + for key0 in ports.keys(): + for key1 in ports[key0]['ports'][0].keys(): + if (key1 == "rx"): + for ii in range(0, len(ports[key0]['ports'][0][key1])): + tmp_dict = ports[key0]['ports'][0][key1][ii] + if (tmp_dict['type'].lower() == "data"): + if (tmp_dict['input'] == "true"): + if tmp_key not in tmp_dict: + tmp_list = tmp_dict['name'].split("_") + last_ele = tmp_list[-1] + if (len(last_ele) == 1): + res = divmod(int(last_ele), 2) + if res[1]: + i_or_q = "Q" + else: + i_or_q = "I" + tmp_dict[tmp_key] = f"{ports[key0]['chip']} ADC Data {i_or_q}{res[0]}" + elif (len(last_ele) == 2): + tmp_dict[tmp_key] = f"{ports[key0]['chip']} ADC Data {last_ele.upper()}" + elif (tmp_dict['input'] == "false"): + if tmp_key not in tmp_dict: + tmp_list = tmp_dict['name'].split("_") + last_ele = tmp_list[-1] + tmp_dict[tmp_key] = f"IP Data {last_ele.upper()} OUT" + elif (tmp_dict['type'].lower() == "valid"): + if (tmp_dict['input'] == "true"): + tmp_dict[tmp_key] = f"IP Valid Rx Data IN" + elif (tmp_dict['input'] == "false"): + tmp_dict[tmp_key] = f"IP Data Valid OUT" + ports[key0]['ports'][0][key1][ii] = tmp_dict + elif (key1 == "tx"): + for ii in range(0, len(ports[key0]['ports'][0][key1])): + tmp_dict = ports[key0]['ports'][0][key1][ii] + if (tmp_dict['type'].lower() == "data"): + if (tmp_dict['input'] == "false"): + if tmp_key not in tmp_dict: + tmp_list = tmp_dict['name'].split("_") + last_ele = tmp_list[-1] + if (len(last_ele) == 1): + res = divmod(int(last_ele), 2) + if res[1]: + i_or_q = "Q" + else: + i_or_q = "I" + tmp_dict[tmp_key] = f"{ports[key0]['chip']} DAC Data {i_or_q}{res[0]}" + elif (len(last_ele) == 2): + tmp_dict[tmp_key] = f"{ports[key0]['chip']} DAC Data {last_ele.upper()}" + elif (tmp_dict['input'] == "true"): + if tmp_key not in tmp_dict: + tmp_list = tmp_dict['name'].split("_") + last_ele = tmp_list[-1] + tmp_dict[tmp_key] = f"IP Data {last_ele.upper()} IN" + elif (tmp_dict['type'].lower() == "valid"): + if (tmp_dict['input'] == "true"): + tmp_dict[tmp_key] = f"IP Valid Tx Data IN" + elif (tmp_dict['input'] == "false"): + tmp_dict[tmp_key] = f"IP Load Tx Data OUT" + ports[key0]['ports'][0][key1][ii] = tmp_dict + +with open(ports_json_file, 'w') as json_file: + json.dump(ports, json_file, indent = 4) \ No newline at end of file diff --git a/CI/scripts/setupDocker.sh b/CI/scripts/setupDocker.sh new file mode 100644 index 0000000..cf70342 --- /dev/null +++ b/CI/scripts/setupDocker.sh @@ -0,0 +1,8 @@ +#!/bin/bash +# This file is run inside of the docker container +echo "Copying HSP files" +cp -r /mlhspro /mlhsp +echo "Copying .matlab" +cp -r /root/.matlabro /root/.matlab +echo "Copying .Xilinx" +cp -r /root/.Xilinxro /root/.Xilinx diff --git a/CI/scripts/synth_designs.sh b/CI/scripts/synth_designs.sh new file mode 100644 index 0000000..3814a45 --- /dev/null +++ b/CI/scripts/synth_designs.sh @@ -0,0 +1,25 @@ +#!/bin/bash + +BOARD=$1 +MLFLAGS="-nodisplay -nodesktop -nosplash" + +if [ -z "$MLRELEASE" ] +then + MLRELEASE=R2022b +fi + +MLPATH=/usr/local/MATLAB + +cd ../.. +cp hdl/vendor/AnalogDevices/hdlcoder_board_customization.m test/hdlcoder_board_customization_local.m +sed -i "s/hdlcoder_board_customization/hdlcoder_board_customization_local/g" test/hdlcoder_board_customization_local.m +source /opt/Xilinx/Vivado/2021.2/settings64.sh +Xvfb :77 & +export DISPLAY=:77 +export SWT_GTK3=0 +source /opt/Xilinx/Vivado/2021.2/settings64.sh +$MLPATH/$MLRELEASE/bin/matlab $MLFLAGS -r "cd('test');runSynthTests('$BOARD');" +pidof Xvfb +if [ $? -eq 0 ]; then + kill -9 `pidof Xvfb` +fi diff --git a/CI/scripts/system_project_rxtx.tcl b/CI/scripts/system_project_rxtx.tcl new file mode 100644 index 0000000..f454cb0 --- /dev/null +++ b/CI/scripts/system_project_rxtx.tcl @@ -0,0 +1,41 @@ +set start_dir [pwd] +puts "Starting Transceiver Toolbox HDL build" + +if {$preprocess == "on"} { + source $preprocess_script +} + +if {$project == "pluto"} { + cd projects/$project/ + source ../scripts/adi_make.tcl +} else { + cd projects/$project/$carrier + source ../../scripts/adi_make.tcl +} +adi_make::lib all + +set ::env(SKIP_SYNTHESIS) 1 +set ::env(MATLAB) 1 +set ::env(ADI_USE_OOC_SYNTHESYS) 1 + +source ./system_project.tcl + +# Update block design to make room for new IP +if {$project == "pluto"} { + source ../scripts/matlab_processors.tcl +} else { + source ../../scripts/matlab_processors.tcl +} +preprocess_bd $project $carrier $ref_design $number_of_inputs $number_of_bits $number_of_valids $multiple + +if {$postprocess == "on"} { + cd $start_dir + source $postprocess_script +} + +regenerate_bd_layout +save_bd_design +validate_bd_design + +# Back to root +cd $start_dir diff --git a/CI/scripts/targeting_designs.sh b/CI/scripts/targeting_designs.sh new file mode 100644 index 0000000..3f2964b --- /dev/null +++ b/CI/scripts/targeting_designs.sh @@ -0,0 +1,27 @@ +#!/bin/bash + +MLFLAGS="-nodisplay -nodesktop -nosplash" + +if [ -z "$MLRELEASE" ] +then + MLRELEASE=R2022b +fi +if [ -z "$DEMO" ] +then + DEMO="" +fi +echo "Testing demo: $DEMO" + +MLPATH=/usr/local/MATLAB + +cd ../.. +source /opt/Xilinx/Vivado/2021.2/settings64.sh +Xvfb :77 & +export DISPLAY=:77 +export SWT_GTK3=0 +source /opt/Xilinx/Vivado/2021.2/settings64.sh +$MLPATH/$MLRELEASE/bin/matlab $MLFLAGS -r "addpath(genpath('test'));addpath(genpath('deps'));runDemoTests('$DEMO');" +pidof Xvfb +if [ $? -eq 0 ]; then + kill -9 `pidof Xvfb` +fi diff --git a/logos/logo_black.png b/logos/logo_black.png new file mode 100644 index 0000000..7be4e68 Binary files /dev/null and b/logos/logo_black.png differ diff --git a/logos/logo_black.svg b/logos/logo_black.svg new file mode 100644 index 0000000..a9902e6 --- /dev/null +++ b/logos/logo_black.svg @@ -0,0 +1,268 @@ + + + + + + + + + + + + + + image/svg+xml + + + + + + + + ADI TOOLBOX-COMMON FOR MATLAB® & SIMULINK® + + + + + + + + + + + + + + + + + + + + + + + + + + + + + TOOLBOXCOMMON + + diff --git a/logos/logo_white.png b/logos/logo_white.png new file mode 100644 index 0000000..4570498 Binary files /dev/null and b/logos/logo_white.png differ diff --git a/logos/logo_white.svg b/logos/logo_white.svg new file mode 100644 index 0000000..3966852 --- /dev/null +++ b/logos/logo_white.svg @@ -0,0 +1,257 @@ + + + + + + + + + + + + image/svg+xml + + + + + + + + + ADI TOOLBOX-COMMON FOR MATLAB® & SIMULINK® + + + + + + + + + + + + + + + + + + + + + + + + + + + + + TOOLBOXCOMMON + +