diff --git a/CI/gen_doc/docs/hdlrefdesigns/adrv9002.md b/CI/gen_doc/docs/hdlrefdesigns/adrv9002.md deleted file mode 100644 index 2a938ce..0000000 --- a/CI/gen_doc/docs/hdlrefdesigns/adrv9002.md +++ /dev/null @@ -1,53 +0,0 @@ - - - -# adrv9002 Reference Design Integration - -This page outlines the HDL reference design integration for the *adrv9002* reference design for the Analog Devices -ADRV9002 component. The IP-Core Generation follow is available on the based on the following base HDL reference design for the following board and design variants: - -- [Base reference design documentation](https://wiki.analog.com/resources/eval/user-guides/adrv9001/reference_hdl) -- Supported FPGA carriers: - - ZCU102 -- Supported design variants: - - RX - - TX - - RX & TX - -## Reference Design - -
- - ![Reference Design](../assets/rd_adrv9001_custom.svg) - -
HDL Reference Design with Custom IP from HDL-Coder. Click on sub-blocks for more documentation.
-
-The IP-Core generation flow will integrate IP generated from Simulink subsystem into an ADI authored reference design. Depending on the FPGA carrier and FMC card or SoM, this will support different IP locations based on the diagram above. - -## HDL Worflow Advisor Port Mappings - -When using the HDL Worflow Advisor, the following port mappings are used to connect the reference design to the HDL-Coder generated IP-Core: - -| Type | Target Platform Interface (MATLAB) | Reference Design Connection (Vivado) | Width | Reference Design Variant | -| ---- | ------------------------ | --------------------------- | ----- | ----------- | -| VALID-OUT | IP Data Valid OUT | util_adc_1_pack/fifo_wr_en | 1 | RX | -| VALID-IN | IP Valid Rx Data IN | axi_adrv9001/adc_1_valid_i0 | 1 | RX | -| DATA-OUT | IP Data 0 OUT | util_adc_1_pack/fifo_wr_data_0 | 16 | RX | -| DATA-OUT | IP Data 1 OUT | util_adc_1_pack/fifo_wr_data_1 | 16 | RX | -| DATA-OUT | IP Data 2 OUT | util_adc_1_pack/fifo_wr_data_2 | 16 | RX | -| DATA-OUT | IP Data 3 OUT | util_adc_1_pack/fifo_wr_data_3 | 16 | RX | -| DATA-IN | ADRV9002 ADC Data Q0 | axi_adrv9001/adc_1_data_i0 | 16 | RX | -| DATA-IN | ADRV9002 ADC Data I0 | axi_adrv9001/adc_1_data_i1 | 16 | RX | -| DATA-IN | ADRV9002 ADC Data Q0 | axi_adrv9001/adc_1_data_q0 | 16 | RX | -| DATA-IN | ADRV9002 ADC Data I0 | axi_adrv9001/adc_1_data_q1 | 16 | RX | -| VALID-IN | IP Valid Tx Data IN | util_dac_1_upack/fifo_rd_valid | 1 | TX | -| VALID-OUT | IP Load Tx Data OUT | util_dac_1_upack/fifo_rd_en | 1 | TX | -| DATA-OUT | ADRV9002 DAC Data Q0 | axi_adrv9001/dac_1_data_i0 | 16 | TX | -| DATA-OUT | ADRV9002 DAC Data I0 | axi_adrv9001/dac_1_data_i1 | 16 | TX | -| DATA-OUT | ADRV9002 DAC Data Q0 | axi_adrv9001/dac_1_data_q0 | 16 | TX | -| DATA-OUT | ADRV9002 DAC Data I0 | axi_adrv9001/dac_1_data_q1 | 16 | TX | -| DATA-IN | IP Data 0 IN | util_dac_1_upack/fifo_rd_data_0 | 16 | TX | -| DATA-IN | IP Data 1 IN | util_dac_1_upack/fifo_rd_data_1 | 16 | TX | -| DATA-IN | IP Data 2 IN | util_dac_1_upack/fifo_rd_data_2 | 16 | TX | -| DATA-IN | IP Data 3 IN | util_dac_1_upack/fifo_rd_data_3 | 16 | TX | - diff --git a/CI/gen_doc/docs/hdlrefdesigns/adrv9009.md b/CI/gen_doc/docs/hdlrefdesigns/adrv9009.md deleted file mode 100644 index 3b0a946..0000000 --- a/CI/gen_doc/docs/hdlrefdesigns/adrv9009.md +++ /dev/null @@ -1,53 +0,0 @@ - - - -# adrv9009 Reference Design Integration - -This page outlines the HDL reference design integration for the *adrv9009* reference design for the Analog Devices -ADRV9009 component. The IP-Core Generation follow is available on the based on the following base HDL reference design for the following board and design variants: - -- [Base reference design documentation](https://wiki.analog.com/resources/eval/user-guides/adrv9009/reference_hdl) -- Supported FPGA carriers: - - ZCU102 -- Supported design variants: - - RX - - TX - - RX & TX - -## Reference Design - -
- - ![Reference Design](../assets/rd_jesd_custom.svg) - -
HDL Reference Design with Custom IP from HDL-Coder. Click on sub-blocks for more documentation.
-
-The IP-Core generation flow will integrate IP generated from Simulink subsystem into an ADI authored reference design. Depending on the FPGA carrier and FMC card or SoM, this will support different IP locations based on the diagram above. - -## HDL Worflow Advisor Port Mappings - -When using the HDL Worflow Advisor, the following port mappings are used to connect the reference design to the HDL-Coder generated IP-Core: - -| Type | Target Platform Interface (MATLAB) | Reference Design Connection (Vivado) | Width | Reference Design Variant | -| ---- | ------------------------ | --------------------------- | ----- | ----------- | -| VALID-OUT | IP Data Valid OUT | util_adrv9009_rx_cpack/fifo_wr_en | 1 | RX | -| VALID-IN | IP Valid Rx Data IN | rx_adrv9009_tpl_core/adc_valid_0 | 1 | RX | -| DATA-OUT | IP Data 0 OUT | util_adrv9009_rx_cpack/fifo_wr_data_0 | 16 | RX | -| DATA-OUT | IP Data 1 OUT | util_adrv9009_rx_cpack/fifo_wr_data_1 | 16 | RX | -| DATA-OUT | IP Data 2 OUT | util_adrv9009_rx_cpack/fifo_wr_data_2 | 16 | RX | -| DATA-OUT | IP Data 3 OUT | util_adrv9009_rx_cpack/fifo_wr_data_3 | 16 | RX | -| DATA-IN | ADRV9009 ADC Data Q0 | rx_adrv9009_tpl_core/adc_data_0 | 16 | RX | -| DATA-IN | ADRV9009 ADC Data I0 | rx_adrv9009_tpl_core/adc_data_1 | 16 | RX | -| DATA-IN | ADRV9009 ADC Data Q1 | rx_adrv9009_tpl_core/adc_data_2 | 16 | RX | -| DATA-IN | ADRV9009 ADC Data I1 | rx_adrv9009_tpl_core/adc_data_3 | 16 | RX | -| VALID-IN | IP Valid Tx Data IN | util_adrv9009_tx_upack/fifo_rd_valid | 1 | TX | -| VALID-OUT | IP Load Tx Data OUT | util_adrv9009_tx_upack/fifo_rd_en | 1 | TX | -| DATA-OUT | ADRV9009 DAC Data Q0 | tx_adrv9009_tpl_core/dac_data_0 | 16 | TX | -| DATA-OUT | ADRV9009 DAC Data I0 | tx_adrv9009_tpl_core/dac_data_1 | 16 | TX | -| DATA-OUT | ADRV9009 DAC Data Q1 | tx_adrv9009_tpl_core/dac_data_2 | 16 | TX | -| DATA-OUT | ADRV9009 DAC Data I1 | tx_adrv9009_tpl_core/dac_data_3 | 16 | TX | -| DATA-IN | IP Data 0 IN | util_adrv9009_tx_upack/fifo_rd_data_0 | 16 | TX | -| DATA-IN | IP Data 1 IN | util_adrv9009_tx_upack/fifo_rd_data_1 | 16 | TX | -| DATA-IN | IP Data 2 IN | util_adrv9009_tx_upack/fifo_rd_data_2 | 16 | TX | -| DATA-IN | IP Data 3 IN | util_adrv9009_tx_upack/fifo_rd_data_3 | 16 | TX | - diff --git a/CI/gen_doc/docs/hdlrefdesigns/adrv9361z7035.md b/CI/gen_doc/docs/hdlrefdesigns/adrv9361z7035.md deleted file mode 100644 index b47713e..0000000 --- a/CI/gen_doc/docs/hdlrefdesigns/adrv9361z7035.md +++ /dev/null @@ -1,57 +0,0 @@ - - - -# adrv9361z7035 Reference Design Integration - -This page outlines the HDL reference design integration for the *adrv9361z7035* reference design for the Analog Devices -AD9361 component. The IP-Core Generation follow is available on the based on the following base HDL reference design for the following board and design variants: - -- [Base reference design documentation](https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/reference_hdl) -- Supported FPGA carriers: - - CCBOB_CMOS - - CCBOB_LVDS - - CCBOX_LVDS - - CCFMC_LVDS - - CCPACKRF_LVDS -- Supported design variants: - - RX - - TX - - RX & TX - -## Reference Design - -
- - ![Reference Design](../assets/rd_ad9361_custom.svg) - -
HDL Reference Design with Custom IP from HDL-Coder. Click on sub-blocks for more documentation.
-
-The IP-Core generation flow will integrate IP generated from Simulink subsystem into an ADI authored reference design. Depending on the FPGA carrier and FMC card or SoM, this will support different IP locations based on the diagram above. - -## HDL Worflow Advisor Port Mappings - -When using the HDL Worflow Advisor, the following port mappings are used to connect the reference design to the HDL-Coder generated IP-Core: - -| Type | Target Platform Interface (MATLAB) | Reference Design Connection (Vivado) | Width | Reference Design Variant | -| ---- | ------------------------ | --------------------------- | ----- | ----------- | -| VALID-OUT | IP Data Valid OUT | util_ad9361_adc_pack/fifo_wr_en | 1 | RX | -| VALID-IN | IP Valid Rx Data IN | util_ad9361_adc_fifo/dout_valid_0 | 1 | RX | -| DATA-OUT | IP Data 0 OUT | util_ad9361_adc_pack/fifo_wr_data_0 | 16 | RX | -| DATA-OUT | IP Data 1 OUT | util_ad9361_adc_pack/fifo_wr_data_1 | 16 | RX | -| DATA-OUT | IP Data 2 OUT | util_ad9361_adc_pack/fifo_wr_data_2 | 16 | RX | -| DATA-OUT | IP Data 3 OUT | util_ad9361_adc_pack/fifo_wr_data_3 | 16 | RX | -| DATA-IN | AD9361 ADC Data Q0 | util_ad9361_adc_fifo/dout_data_0 | 16 | RX | -| DATA-IN | AD9361 ADC Data I0 | util_ad9361_adc_fifo/dout_data_1 | 16 | RX | -| DATA-IN | AD9361 ADC Data Q1 | util_ad9361_adc_fifo/dout_data_2 | 16 | RX | -| DATA-IN | AD9361 ADC Data I1 | util_ad9361_adc_fifo/dout_data_3 | 16 | RX | -| VALID-IN | IP Valid Tx Data IN | util_ad9361_dac_upack/fifo_rd_valid | 1 | TX | -| VALID-OUT | IP Load Tx Data OUT | axi_ad9361_dac_fifo/din_valid_in_0 | 1 | TX | -| DATA-OUT | AD9361 DAC Data Q0 | axi_ad9361_dac_fifo/din_data_0 | 16 | TX | -| DATA-OUT | AD9361 DAC Data I0 | axi_ad9361_dac_fifo/din_data_1 | 16 | TX | -| DATA-OUT | AD9361 DAC Data Q1 | axi_ad9361_dac_fifo/din_data_2 | 16 | TX | -| DATA-OUT | AD9361 DAC Data I1 | axi_ad9361_dac_fifo/din_data_3 | 16 | TX | -| DATA-IN | IP Data 0 IN | util_ad9361_dac_upack/fifo_rd_data_0 | 16 | TX | -| DATA-IN | IP Data 1 IN | util_ad9361_dac_upack/fifo_rd_data_1 | 16 | TX | -| DATA-IN | IP Data 2 IN | util_ad9361_dac_upack/fifo_rd_data_2 | 16 | TX | -| DATA-IN | IP Data 3 IN | util_ad9361_dac_upack/fifo_rd_data_3 | 16 | TX | - diff --git a/CI/gen_doc/docs/hdlrefdesigns/adrv9364z7020.md b/CI/gen_doc/docs/hdlrefdesigns/adrv9364z7020.md deleted file mode 100644 index 9f1d72f..0000000 --- a/CI/gen_doc/docs/hdlrefdesigns/adrv9364z7020.md +++ /dev/null @@ -1,55 +0,0 @@ - - - -# adrv9364z7020 Reference Design Integration - -This page outlines the HDL reference design integration for the *adrv9364z7020* reference design for the Analog Devices -AD9364 component. The IP-Core Generation follow is available on the based on the following base HDL reference design for the following board and design variants: - -- [Base reference design documentation](https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/reference_hdl) -- Supported FPGA carriers: - - CCBOB_CMOS - - CCBOB_LVDS - - CCBOX_LVDS -- Supported design variants: - - RX - - TX - - RX & TX - -## Reference Design - -
- - ![Reference Design](../assets/rd_ad9361_custom.svg) - -
HDL Reference Design with Custom IP from HDL-Coder. Click on sub-blocks for more documentation.
-
-The IP-Core generation flow will integrate IP generated from Simulink subsystem into an ADI authored reference design. Depending on the FPGA carrier and FMC card or SoM, this will support different IP locations based on the diagram above. - -## HDL Worflow Advisor Port Mappings - -When using the HDL Worflow Advisor, the following port mappings are used to connect the reference design to the HDL-Coder generated IP-Core: - -| Type | Target Platform Interface (MATLAB) | Reference Design Connection (Vivado) | Width | Reference Design Variant | -| ---- | ------------------------ | --------------------------- | ----- | ----------- | -| VALID-OUT | IP Data Valid OUT | util_ad9361_adc_pack/fifo_wr_en | 1 | RX | -| VALID-IN | IP Valid Rx Data IN | util_ad9361_adc_fifo/dout_valid_0 | 1 | RX | -| DATA-OUT | IP Data 0 OUT | util_ad9361_adc_pack/fifo_wr_data_0 | 16 | RX | -| DATA-OUT | IP Data 1 OUT | util_ad9361_adc_pack/fifo_wr_data_1 | 16 | RX | -| DATA-OUT | IP Data 2 OUT | util_ad9361_adc_pack/fifo_wr_data_2 | 16 | RX | -| DATA-OUT | IP Data 3 OUT | util_ad9361_adc_pack/fifo_wr_data_3 | 16 | RX | -| DATA-IN | AD9364 ADC Data Q0 | util_ad9361_adc_fifo/dout_data_0 | 16 | RX | -| DATA-IN | AD9364 ADC Data I0 | util_ad9361_adc_fifo/dout_data_1 | 16 | RX | -| DATA-IN | AD9364 ADC Data Q1 | util_ad9361_adc_fifo/dout_data_2 | 16 | RX | -| DATA-IN | AD9364 ADC Data I1 | util_ad9361_adc_fifo/dout_data_3 | 16 | RX | -| VALID-IN | IP Valid Tx Data IN | util_ad9361_dac_upack/fifo_rd_valid | 1 | TX | -| VALID-OUT | IP Load Tx Data OUT | axi_ad9361_dac_fifo/din_valid_in_0 | 1 | TX | -| DATA-OUT | AD9364 DAC Data Q0 | axi_ad9361_dac_fifo/din_data_0 | 16 | TX | -| DATA-OUT | AD9364 DAC Data I0 | axi_ad9361_dac_fifo/din_data_1 | 16 | TX | -| DATA-OUT | AD9364 DAC Data Q1 | axi_ad9361_dac_fifo/din_data_2 | 16 | TX | -| DATA-OUT | AD9364 DAC Data I1 | axi_ad9361_dac_fifo/din_data_3 | 16 | TX | -| DATA-IN | IP Data 0 IN | util_ad9361_dac_upack/fifo_rd_data_0 | 16 | TX | -| DATA-IN | IP Data 1 IN | util_ad9361_dac_upack/fifo_rd_data_1 | 16 | TX | -| DATA-IN | IP Data 2 IN | util_ad9361_dac_upack/fifo_rd_data_2 | 16 | TX | -| DATA-IN | IP Data 3 IN | util_ad9361_dac_upack/fifo_rd_data_3 | 16 | TX | - diff --git a/CI/gen_doc/docs/hdlrefdesigns/adrv9371.md b/CI/gen_doc/docs/hdlrefdesigns/adrv9371.md deleted file mode 100644 index 7635006..0000000 --- a/CI/gen_doc/docs/hdlrefdesigns/adrv9371.md +++ /dev/null @@ -1,53 +0,0 @@ - - - -# adrv9371 Reference Design Integration - -This page outlines the HDL reference design integration for the *adrv9371* reference design for the Analog Devices -AD9371 component. The IP-Core Generation follow is available on the based on the following base HDL reference design for the following board and design variants: - -- [Base reference design documentation](https://wiki.analog.com/resources/eval/user-guides/mykonos/reference_hdl) -- Supported FPGA carriers: - - ZC706 - - ZCU102 -- Supported design variants: - - RX - - TX - -## Reference Design - -
- - ![Reference Design](../assets/rd_jesd_custom.svg) - -
HDL Reference Design with Custom IP from HDL-Coder. Click on sub-blocks for more documentation.
-
-The IP-Core generation flow will integrate IP generated from Simulink subsystem into an ADI authored reference design. Depending on the FPGA carrier and FMC card or SoM, this will support different IP locations based on the diagram above. - -## HDL Worflow Advisor Port Mappings - -When using the HDL Worflow Advisor, the following port mappings are used to connect the reference design to the HDL-Coder generated IP-Core: - -| Type | Target Platform Interface (MATLAB) | Reference Design Connection (Vivado) | Width | Reference Design Variant | -| ---- | ------------------------ | --------------------------- | ----- | ----------- | -| VALID-OUT | IP Data Valid OUT | util_ad9371_rx_cpack/fifo_wr_en | 1 | RX | -| VALID-IN | IP Valid Rx Data IN | rx_ad9371_tpl_core/adc_valid_0 | 1 | RX | -| DATA-OUT | IP Data 0 OUT | util_ad9361_adc_pack/fifo_wr_data_0 | 16 | RX | -| DATA-OUT | IP Data 1 OUT | util_ad9361_adc_pack/fifo_wr_data_1 | 16 | RX | -| DATA-OUT | IP Data 2 OUT | util_ad9361_adc_pack/fifo_wr_data_2 | 16 | RX | -| DATA-OUT | IP Data 3 OUT | util_ad9361_adc_pack/fifo_wr_data_3 | 16 | RX | -| DATA-IN | AD9371 ADC Data Q0 | rx_ad9371_tpl_core/adc_data_0 | 16 | RX | -| DATA-IN | AD9371 ADC Data I0 | rx_ad9371_tpl_core/adc_data_1 | 16 | RX | -| DATA-IN | AD9371 ADC Data Q1 | rx_ad9371_tpl_core/adc_data_2 | 16 | RX | -| DATA-IN | AD9371 ADC Data I1 | rx_ad9371_tpl_core/adc_data_3 | 16 | RX | -| VALID-IN | IP Valid Tx Data IN | util_ad9371_tx_upack/fifo_rd_valid | 1 | TX | -| VALID-OUT | IP Load Tx Data OUT | util_ad9371_tx_upack/fifo_rd_en | 1 | TX | -| DATA-OUT | AD9371 DAC Data Q0 | tx_ad9371_tpl_core/dac_data_0 | 32 | TX | -| DATA-OUT | AD9371 DAC Data I0 | tx_ad9371_tpl_core/dac_data_1 | 32 | TX | -| DATA-OUT | AD9371 DAC Data Q1 | tx_ad9371_tpl_core/dac_data_2 | 32 | TX | -| DATA-OUT | AD9371 DAC Data I1 | tx_ad9371_tpl_core/dac_data_3 | 32 | TX | -| DATA-IN | IP Data 0 IN | util_ad9371_tx_upack/fifo_rd_data_0 | 32 | TX | -| DATA-IN | IP Data 1 IN | util_ad9371_tx_upack/fifo_rd_data_1 | 32 | TX | -| DATA-IN | IP Data 2 IN | util_ad9371_tx_upack/fifo_rd_data_2 | 32 | TX | -| DATA-IN | IP Data 3 IN | util_ad9371_tx_upack/fifo_rd_data_3 | 32 | TX | - diff --git a/CI/gen_doc/docs/hdlrefdesigns/pluto.md b/CI/gen_doc/docs/hdlrefdesigns/pluto.md deleted file mode 100644 index 0e98f89..0000000 --- a/CI/gen_doc/docs/hdlrefdesigns/pluto.md +++ /dev/null @@ -1,42 +0,0 @@ - - - -# pluto Reference Design Integration - -This page outlines the HDL reference design integration for the *pluto* reference design for the Analog Devices -AD9361 component. The IP-Core Generation follow is available on the based on the following base HDL reference design for the following board and design variants: - -- [Base reference design documentation](https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/reference_hdl) -- Supported FPGA carriers: -- Supported design variants: - - RX - - TX - -## Reference Design - -
- - ![Reference Design](../assets/rd_ad9361_custom.svg) - -
HDL Reference Design with Custom IP from HDL-Coder. Click on sub-blocks for more documentation.
-
-The IP-Core generation flow will integrate IP generated from Simulink subsystem into an ADI authored reference design. Depending on the FPGA carrier and FMC card or SoM, this will support different IP locations based on the diagram above. - -## HDL Worflow Advisor Port Mappings - -When using the HDL Worflow Advisor, the following port mappings are used to connect the reference design to the HDL-Coder generated IP-Core: - -| Type | Target Platform Interface (MATLAB) | Reference Design Connection (Vivado) | Width | Reference Design Variant | -| ---- | ------------------------ | --------------------------- | ----- | ----------- | -| VALID-OUT | IP Data Valid OUT | cpack/fifo_wr_en | 1 | RX | -| VALID-IN | IP Valid Rx Data IN | axi_ad9361/adc_valid_i0 | 1 | RX | -| DATA-OUT | IP Data 0 OUT | cpack/fifo_wr_data_0 | 16 | RX | -| DATA-OUT | IP Data 1 OUT | cpack/fifo_wr_data_1 | 16 | RX | -| DATA-IN | AD9361 ADC Data Q0 | axi_ad9361/adc_data_i0 | 16 | RX | -| DATA-IN | AD9361 ADC Data Q0 | axi_ad9361/adc_data_q0 | 16 | RX | -| VALID-IN | IP Valid Tx Data IN | tx_upack/fifo_rd_valid | 1 | TX | -| DATA-OUT | AD9361 DAC Data Q0 | axi_ad9361/dac_data_i0 | 16 | TX | -| DATA-OUT | AD9361 DAC Data Q0 | axi_ad9361/dac_data_q0 | 16 | TX | -| DATA-IN | IP Data 0 IN | util_ad9361_dac_upack/fifo_rd_data_0 | 16 | TX | -| DATA-IN | IP Data 1 IN | util_ad9361_dac_upack/fifo_rd_data_1 | 16 | TX | -